Author: v1.0
Description: An AsciiDoctor demo with wavedrom python command line

# AsciiDoctor demo for HDL designers

v1.0

## 1. WaveDrom diagrams examples

### 1.1. Test #0

### 1.2. Test #1 (default)

### 1.3. Test #1 (narrow)

### 1.4. Test #2

### 1.5. Test #3

### 1.6. Test #4

### 1.7. Test #5

### 1.8. Test #6

### 1.9. Test #7

### 1.10. Test #8

### 1.11. Test #9

### 1.12. Test #10

### 1.13. Test #11

### 1.14. Test #12

## 2. Port description example

Signal name | Type | Description
--- | --- | ---
clk | in | Clk input
reset | in | Reset
address | in | Address bus
read | in | Read signal
readdata | out | Read data bus
readvalid | out | Read valid signal
write | in | Write signal
writedata | in | Write data bus

## 3. Register description example

Address | Bits | Field Name | Access | Description
--- | --- | --- | --- | ---
0x00000000 | 31:24 | NU | RO | Not used.
23:16 | VMAJ | RO | Version major.
15:8 | VMIN | RO | Version minor.
7:0 | VPATCH | RO | Version patch.
0x00000004 | 31:16 | STATUS | RO | Status bits.
15 | PLL_LOCKED | RO | PLL locked.
14 | DDR_INIT_DONE | RO | DDR Init_done.
13:12 | NU | RO | Not used.
11:8 | GROUP_0_INTR | R/W | Group #0 interrupt requests.
7:4 | GROUP_1_INTR | R/W | Group #1 interrupt requests.
3:0 | GROUP_2_INTR | R/W | Group #2 interrupt requests.

## 4. VHDL syntax coloring example

    proc_column_counter : process ( reset, clk )
      begin
        if reset = '1' then
          col <= 0;
        elsif rising_edge( clk ) then
          if enable then
            if sink_endofpacket = '1' then
              col <= 0;
            elsif col = g_width - g_data_size / c_pixel_size then
              col <= 0;
            else
              col <= col + g_data_size / c_pixel_size;
            end if;
          end if;
        end if;
      end process proc_column_counter;