= AsciiDoctor demo for HDL designers =
v1.0
:toc: left
:icons: font
:numbered:
:source-autofit:
:doctype: book
:description: An AsciiDoctor demo with wavedrom python command line
:source-highlighter: pygments

== WaveDrom diagrams examples ==

=== Test #0 ===
[wavedrom,wavedrom_test0,svg]
----
{ "signal": [{ "name": "Alfa", "wave": "01.zx=ud.23.45" }] }
----

=== Test #1 (default) ===
[wavedrom,wavedrom_test1,svg]
----
{ "signal": [
  { "name": "pclk", "wave": "p......." },
  { "name": "Pclk", "wave": "P......." },
  { "name": "nclk", "wave": "n......." },
  { "name": "Nclk", "wave": "N......." },
  {},
  { "name": "clk0", "wave": "phnlPHNL" },
  { "name": "clk1", "wave": "xhlhLHl." },
  { "name": "clk2", "wave": "hpHplnLn" },
  { "name": "clk3", "wave": "nhNhplPl" },
  { "name": "clk4", "wave": "xlh.L.Hx" }
]}
----

=== Test #1 (narrow) ===
[wavedrom,wavedrom_test1n,svg]
----
{ "signal": [
  { "name": "pclk", "wave": "p......." },
  { "name": "Pclk", "wave": "P......." },
  { "name": "nclk", "wave": "n......." },
  { "name": "Nclk", "wave": "N......." },
  {},
  { "name": "clk0", "wave": "phnlPHNL" },
  { "name": "clk1", "wave": "xhlhLHl." },
  { "name": "clk2", "wave": "hpHplnLn" },
  { "name": "clk3", "wave": "nhNhplPl" },
  { "name": "clk4", "wave": "xlh.L.Hx" }
  ],
   "config": { "skin": "narrow" }
}
----

=== Test #2 ===
[wavedrom,wavedrom_test2,svg]
----
{ "signal": [
  { "name": "clk",  "wave": "P......" },
  { "name": "bus",  "wave": "x.==.=x", "data": ["head", "body", "tail", "data"] },
  { "name": "wire", "wave": "0.1..0." }
]}
----

=== Test #3 ===
[wavedrom,wavedrom_test3,svg]
----
{ "signal": [
  { "name": "clk",         "wave": "p.....|..." },
  { "name": "data",        "wave": "x.345x|=.x", "data": ["head", "body", "tail", "data"] },
  { "name": "Request",     "wave": "0.1..0|1.0" },
  {},
  { "name": "Acknowledge", "wave": "1.....|01." }
]}
----

=== Test #4 ===
[wavedrom,wavedrom_test4,svg]
----
{ "signal": [
  {    "name": "clk",   "wave": "p..Pp..P"},
  ["Master",
    ["ctrl",
      {"name": "write", "wave": "01.0...."},
      {"name": "read",  "wave": "0...1..0"}
    ],
    {  "name": "addr",  "wave": "x3.x4..x", "data": "A1 A2"},
    {  "name": "wdata", "wave": "x3.x....", "data": "D1"   }
  ],
  {},
  ["Slave",
    ["ctrl",
      {"name": "ack",   "wave": "x01x0.1x"}
    ],
    {  "name": "rdata", "wave": "x.....4x", "data": "Q2"}
  ]
]}
----

=== Test #5 ===
[wavedrom,wavedrom_test5,svg]
----
{ "signal": [
  { "name": "CK",   "wave": "P.......",                                              "period": 2  },
  { "name": "CMD",  "wave": "x.3x=x4x=x=x=x=x", "data": "RAS NOP CAS NOP NOP NOP NOP", "phase": 0.5 },
  { "name": "ADDR", "wave": "x.=x..=x........", "data": "ROW COL",                     "phase": 0.5 },
  { "name": "DQS",  "wave": "z.......0.1010z." },
  { "name": "DQ",   "wave": "z.........5555z.", "data": "D0 D1 D2 D3" }
]}
----

=== Test #6 ===
[wavedrom,wavedrom_test6,svg]
----
{ "signal": [
  { "name": "clk",     "wave": "p...." },
  { "name": "data",    "wave": "x345x",  "data": ["head", "body", "tail"] },
  { "name": "Request", "wave": "01..0" }
  ],
  "config": { "hscale": 1 }
}
----

=== Test #7 ===
[wavedrom,wavedrom_test7,svg]
----
{ "signal" : [
  { "name": "clk",         "wave": "p...." },
  { "name": "data",        "wave": "x345x", "data": ["head", "body", "tail"] },
  { "name": "Request",     "wave": "01..0" }
],
  "config" : { "hscale" : 2 }
}
----

=== Test #8 ===
[wavedrom,wavedrom_test8,svg]
----
{ "signal" : [
  { "name": "clk",         "wave": "p...." },
  { "name": "data",        "wave": "x345x", "data": ["head", "body", "tail"] },
  { "name": "Request",     "wave": "01..0" }
],
  "config" : { "hscale" : 3 }
}
----

=== Test #9 ===
[wavedrom,wavedrom_test9,svg]
----
{"signal": [
  {"name":"clk",         "wave": "p...." },
  {"name":"data",        "wave": "x345x", "data": "a b c" },
  {"name":"Request",     "wave": "01..0" }
],
 "head":{
   "text":"WaveDrom example",
   "tick":0
 },
 "foot":{
   "text":"Figure 100",
   "tock":9
 }
}
----

=== Test #10 ===
[wavedrom,wavedrom_test10,svg]
----
{"signal": [
  {"name":"clk", "wave": "p.....PPPPp...." },
  {"name":"dat", "wave": "x....2345x.....", "data": "a b c d" },
  {"name":"req", "wave": "0....1...0....." }
],
"head": {"text":
  ["tspan",
    ["tspan", {"class":"error h1"}, "error "],
    ["tspan", {"class":"warning h2"}, "warning "],
    ["tspan", {"class":"info h3"}, "info "],
    ["tspan", {"class":"success h4"}, "success "],
    ["tspan", {"class":"muted h5"}, "muted "],
    ["tspan", {"class":"h6"}, "h6 "],
    "default ",
    ["tspan", {"fill":"pink", "font-weight":"bold", "font-style":"italic"}, "pink-bold-italic"]
  ]
},
"foot": {"text":
  ["tspan", "E=mc",
    ["tspan", {"dy":"-5"}, "2"],
    ["tspan", {"dy": "5"}, ". "],
    ["tspan", {"font-size":"25"}, "B "],
    ["tspan", {"text-decoration":"overline"},"over "],
    ["tspan", {"text-decoration":"underline"},"under "],
    ["tspan", {"baseline-shift":"sub"}, "sub "],
    ["tspan", {"baseline-shift":"super"}, "super "]
  ],"tock":-5
}
}
----

=== Test #11 ===
[wavedrom,wavedrom_test11,svg]
----
{ "signal": [
  { "name": "A", "wave": "01........0....",  "node": ".a........j" },
  { "name": "B", "wave": "0.1.......0.1..",  "node": "..b.......i" },
  { "name": "C", "wave": "0..1....0...1..",  "node": "...c....h.." },
  { "name": "D", "wave": "0...1..0.....1.",  "node": "....d..g..." },
  { "name": "E", "wave": "0....10.......1",  "node": ".....ef...." }
  ],
  "edge": [
    "a~b t1", "c-~a t2", "c-~>d time 3", "d~-e",
    "e~>f", "f->g", "g-~>h", "h~>i some text", "h~->j"
  ]
}
----

=== Test #12 ===
[wavedrom,wavedrom_test12,svg]
----
{ "signal": [
  { "name": "A", "wave": "01..0..",  "node": ".a..e.." },
  { "name": "B", "wave": "0.1..0.",  "node": "..b..d.", "phase":0.5 },
  { "name": "C", "wave": "0..1..0",  "node": "...c..f" },
  {                                  "node": "...g..h" }
  ],
  "edge": [
    "b-|a t1", "a-|c t2", "b-|-c t3", "c-|->e t4", "e-|>f more text",
    "e|->d t6", "c-g", "f-h", "g<->h 3 ms"
  ]
}
----

== Port description example ==

[width="100%",cols="<2,^1,^7",options="header"]
|=================================
|Signal name    |Type  | Description
|clk            | in  <| Clk input
|reset          | in  <| Reset
|address        | in  <| Address bus
|read           | in  <| Read signal
|readdata       | out <| Read data bus
|readvalid      | out <| Read valid signal
|write          | in  <| Write signal
|writedata      | in  <| Write data bus
|=================================

== Register description example ==

[width="100%",cols="^2,^1,^2,^1,^4",options="header"]
|=========================================================
|Address       |Bits  | Field Name    |Access |Description
.4+|0x00000000
               |31:24 | NU            |RO    <| Not used.
               |23:16 | VMAJ          |RO    <| Version major.
               |15:8  | VMIN          |RO    <| Version minor.
               |7:0   | VPATCH        |RO    <| Version patch.
.7+|0x00000004
               |31:16 | STATUS        | RO   <| Status bits.
               |15    | PLL_LOCKED    | RO   <| PLL locked.
               |14    | DDR_INIT_DONE | RO   <| DDR Init_done.
               |13:12 | NU            | RO   <| Not used.
               |11:8  | GROUP_0_INTR  | R/W  <| Group #0 interrupt requests. 
               |7:4   | GROUP_1_INTR  | R/W  <| Group #1 interrupt requests.
               |3:0   | GROUP_2_INTR  | R/W  <| Group #2 interrupt requests.
|=========================================================

== VHDL syntax coloring example ==
[source,vhdl]
----
proc_column_counter : process ( reset, clk )
  begin
    if reset = '1' then
      col <= 0;
    elsif rising_edge( clk ) then
      if enable then
        if sink_endofpacket = '1' then
          col <= 0;
        elsif col = g_width - g_data_size / c_pixel_size then
          col <= 0;
        else
          col <= col + g_data_size / c_pixel_size;
        end if;
      end if;
    end if;
  end process proc_column_counter;
----