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0 |
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1 |
<class 'vsg.parser.blank_line'>
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2 | architecture RTL of FIFO is
<class 'vsg.token.architecture_body.architecture_keyword'>
<class 'vsg.token.architecture_body.identifier'>
<class 'vsg.token.architecture_body.of_keyword'>
<class 'vsg.token.architecture_body.entity_name'>
<class 'vsg.token.architecture_body.is_keyword'>
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3 |
<class 'vsg.parser.blank_line'>
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4 |   signal fifo_wr : std_logic;
<class 'vsg.token.signal_declaration.signal_keyword'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.signal_declaration.colon'>
<class 'vsg.token.ieee.std_logic_1164.types.std_logic'>
<class 'vsg.token.signal_declaration.semicolon'>
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5 |
<class 'vsg.parser.blank_line'>
--------------------------------------------------------------------------------
6 |   signal fifo_wr : std_logic_vector(3 downto 0);
<class 'vsg.token.signal_declaration.signal_keyword'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.signal_declaration.colon'>
<class 'vsg.token.ieee.std_logic_1164.types.std_logic_vector'>
<class 'vsg.token.index_constraint.open_parenthesis'>
<class 'vsg.parser.todo'>
<class 'vsg.token.direction.downto'>
<class 'vsg.parser.todo'>
<class 'vsg.token.index_constraint.close_parenthesis'>
<class 'vsg.token.signal_declaration.semicolon'>
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7 |
<class 'vsg.parser.blank_line'>
--------------------------------------------------------------------------------
8 |   signal fifo_wr : std_logic_vector(3 downto 0) := "000";
<class 'vsg.token.signal_declaration.signal_keyword'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.signal_declaration.colon'>
<class 'vsg.token.ieee.std_logic_1164.types.std_logic_vector'>
<class 'vsg.token.index_constraint.open_parenthesis'>
<class 'vsg.parser.todo'>
<class 'vsg.token.direction.downto'>
<class 'vsg.parser.todo'>
<class 'vsg.token.index_constraint.close_parenthesis'>
<class 'vsg.token.signal_declaration.assignment_operator'>
<class 'vsg.parser.todo'>
<class 'vsg.token.signal_declaration.semicolon'>
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9 |
<class 'vsg.parser.blank_line'>
--------------------------------------------------------------------------------
10 |   signal fifo_wr, fifo_rd, fifo_empty : std_logic := '1';
<class 'vsg.token.signal_declaration.signal_keyword'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.identifier_list.comma'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.identifier_list.comma'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.signal_declaration.colon'>
<class 'vsg.token.ieee.std_logic_1164.types.std_logic'>
<class 'vsg.token.signal_declaration.assignment_operator'>
<class 'vsg.parser.character_literal'>
<class 'vsg.token.signal_declaration.semicolon'>
--------------------------------------------------------------------------------
11 |
<class 'vsg.parser.blank_line'>
--------------------------------------------------------------------------------
12 |   signal fifo_rd : fifo_wr'subtype;
<class 'vsg.token.signal_declaration.signal_keyword'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.signal_declaration.colon'>
<class 'vsg.token.type_mark.name'>
<class 'vsg.token.type_mark.tic'>
<class 'vsg.token.type_mark.attribute'>
<class 'vsg.token.signal_declaration.semicolon'>
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13 |
<class 'vsg.parser.blank_line'>
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14 |   signal slv : std_logic_vector(integer_range_subtype);
<class 'vsg.token.signal_declaration.signal_keyword'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.signal_declaration.colon'>
<class 'vsg.token.ieee.std_logic_1164.types.std_logic_vector'>
<class 'vsg.token.index_constraint.open_parenthesis'>
<class 'vsg.parser.todo'>
<class 'vsg.token.index_constraint.close_parenthesis'>
<class 'vsg.token.signal_declaration.semicolon'>
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15 |
<class 'vsg.parser.blank_line'>
--------------------------------------------------------------------------------
16 |   signal slv : std_logic_vector(open);
<class 'vsg.token.signal_declaration.signal_keyword'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.signal_declaration.colon'>
<class 'vsg.token.ieee.std_logic_1164.types.std_logic_vector'>
<class 'vsg.token.array_constraint.open_parenthesis'>
<class 'vsg.token.array_constraint.open_keyword'>
<class 'vsg.token.array_constraint.close_parenthesis'>
<class 'vsg.token.signal_declaration.semicolon'>
--------------------------------------------------------------------------------
17 |
<class 'vsg.parser.blank_line'>
--------------------------------------------------------------------------------
18 |   signal slv : std_logic_vector(open) bus;
<class 'vsg.token.signal_declaration.signal_keyword'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.signal_declaration.colon'>
<class 'vsg.token.ieee.std_logic_1164.types.std_logic_vector'>
<class 'vsg.token.array_constraint.open_parenthesis'>
<class 'vsg.token.array_constraint.open_keyword'>
<class 'vsg.token.array_constraint.close_parenthesis'>
<class 'vsg.token.signal_kind.bus_keyword'>
<class 'vsg.token.signal_declaration.semicolon'>
--------------------------------------------------------------------------------
19 |
<class 'vsg.parser.blank_line'>
--------------------------------------------------------------------------------
20 |   signal slv : std_logic_vector(open) register;
<class 'vsg.token.signal_declaration.signal_keyword'>
<class 'vsg.token.signal_declaration.identifier'>
<class 'vsg.token.signal_declaration.colon'>
<class 'vsg.token.ieee.std_logic_1164.types.std_logic_vector'>
<class 'vsg.token.array_constraint.open_parenthesis'>
<class 'vsg.token.array_constraint.open_keyword'>
<class 'vsg.token.array_constraint.close_parenthesis'>
<class 'vsg.token.signal_kind.register_keyword'>
<class 'vsg.token.signal_declaration.semicolon'>
--------------------------------------------------------------------------------
21 |
<class 'vsg.parser.blank_line'>
--------------------------------------------------------------------------------
22 | begin
<class 'vsg.token.architecture_body.begin_keyword'>
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23 |
<class 'vsg.parser.blank_line'>
--------------------------------------------------------------------------------
24 | end architecture RTL;
<class 'vsg.token.architecture_body.end_keyword'>
<class 'vsg.token.architecture_body.end_architecture_keyword'>
<class 'vsg.token.architecture_body.architecture_simple_name'>
<class 'vsg.token.architecture_body.semicolon'>
