domain: "vlsir.primitives"
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "resistor"
  }
  desc: "\n# Ideal Resistor\n\nPorts: (p, n) \nParams: `r`, resistance (in Ohms)\n\nPrimitive ideal resistor. \nLargely corresponds to the \"R-prefix\" element of Spice-class simulators. \n\nAdditional parameters such as temperature coefficients are allowed, and are to be passed unmodified to netlist formats. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  parameters {
    name: "r"
    desc: "Resistance (Ohms)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "capacitor"
  }
  desc: "\n# Ideal Capacitor\n\nPorts: (p, n) \nParams: `c`, capacitance (in Farads)\n\nPrimitive ideal capacitor. \nLargely corresponds to the \"C-prefix\" element of Spice-class simulators. \n\nAdditional parameters are allowed, and are to be passed unmodified to netlist formats. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  parameters {
    name: "c"
    desc: "Capacitance (Farads)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "inductor"
  }
  desc: "\n# Ideal Inductor\n\nPorts: (p, n) \nParams: `l`, inductance (in Henries)\n\nPrimitive ideal inductor. \nLargely corresponds to the \"L-prefix\" element of Spice-class simulators. \n\nAdditional parameters are allowed, and are to be passed unmodified to netlist formats. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  parameters {
    name: "l"
    desc: "Inductance (Henries)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "vcvs"
  }
  desc: "\n# Voltage-Controlled Voltage Source\n\nPorts: (p, n, ctrlp, ctrln) \nParams: `gain`, voltage gain (in Volts/Volt)\n\nLargely corresponds to the \"e-prefix\" element of Spice-class simulators. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  ports {
    signal: "cp"
    direction: NONE
  }
  ports {
    signal: "cn"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  signals {
    name: "cp"
    width: 1
  }
  signals {
    name: "cn"
    width: 1
  }
  parameters {
    name: "gain"
    desc: "Voltage Gain (Volts/Volt)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "vccs"
  }
  desc: "\n# Voltage-Controlled Current Source\n\nPorts: (p, n, ctrlp, ctrln) \nParams: `gain`, transconductance gain (in Amps/Volt)\n\nLargely corresponds to the \"g-prefix\" element of Spice-class simulators. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  ports {
    signal: "cp"
    direction: NONE
  }
  ports {
    signal: "cn"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  signals {
    name: "cp"
    width: 1
  }
  signals {
    name: "cn"
    width: 1
  }
  parameters {
    name: "gain"
    desc: "Transconductance Gain (Amps/Volt)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "cccs"
  }
  desc: "\n# Current-Controlled Current Source\n\nPorts: (p, n, ctrlp, ctrln) \nParams: `gain`, current gain (in Amps/Amp)\n\nLargely corresponds to the \"f-prefix\" element of Spice-class simulators. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  ports {
    signal: "cp"
    direction: NONE
  }
  ports {
    signal: "cn"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  signals {
    name: "cp"
    width: 1
  }
  signals {
    name: "cn"
    width: 1
  }
  parameters {
    name: "gain"
    desc: "Current Gain (Amps/Amp)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "ccvs"
  }
  desc: "\n# Current-Controlled Voltage Source\n\nPorts: (p, n, ctrlp, ctrln) \nParams: `gain`, transresistance gain (in Volts/Amp)\n\nLargely corresponds to the \"h-prefix\" element of Spice-class simulators. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  ports {
    signal: "cp"
    direction: NONE
  }
  ports {
    signal: "cn"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  signals {
    name: "cp"
    width: 1
  }
  signals {
    name: "cn"
    width: 1
  }
  parameters {
    name: "gain"
    desc: "Transresistance Gain (Volts/Amp)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "isource"
  }
  desc: "\n# Independent Current Source\n\nPorts: (p, n) \nParams: `dc`, dc current (in Amps)\n\nLargely corresponds to the \"i-prefix\" element of Spice-class simulators. \nSole required parameter `dc` sets the DC value. \nAll other parameters are passed unmodifed to netlist-level formats. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  parameters {
    name: "dc"
    desc: "DC Current (Amps)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "vdc"
  }
  desc: "\n# Independent Voltage Source\n\nPorts: (p, n) \nParams: `dc`, dc voltage (in Volts)\n\nAll other parameters are passed unmodifed to netlist-level formats. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  parameters {
    name: "dc"
    desc: "DC Voltage (Volts)"
  }
  parameters {
    name: "ac"
    value {
      integer: 0
    }
    desc: "AC/ Small-Signal Magnitude (Volts)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "vpulse"
  }
  desc: "\n# Pulse Voltage Source\nTwo-value time-alternating voltage, with parametrizable rise and fall times and delays.\n\nPorts: (p, n) \nParams: FIXME!\n\nAll other parameters are passed unmodifed to netlist-level formats. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  parameters {
    name: "v1"
    desc: "Initial Value (V)"
  }
  parameters {
    name: "v2"
    desc: "Pulse Value (V)"
  }
  parameters {
    name: "td"
    desc: "Delay Time (s)"
  }
  parameters {
    name: "tr"
    desc: "Rise Time (s)"
  }
  parameters {
    name: "tf"
    desc: "Fall Time (s)"
  }
  parameters {
    name: "tpw"
    desc: "Pulse Width (s)"
  }
  parameters {
    name: "tper"
    desc: "Period (s)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "vsin"
  }
  desc: "\n# Sinusoidal Voltage Source\n\nPorts: (p, n) \nParams: FIXME!\n\nAll other parameters are passed unmodifed to netlist-level formats. \n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  parameters {
    name: "voff"
    desc: "Offset voltage (V)"
  }
  parameters {
    name: "vamp"
    desc: "Amplitude (V)"
  }
  parameters {
    name: "freq"
    desc: "Frequency (Hz)"
  }
  parameters {
    name: "td"
    desc: "Delay Time (s)"
  }
  parameters {
    name: "phase"
    desc: "Phase when t=td (degrees)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "mos"
  }
  desc: "\n# Mosfet Transistor\n\nPorts: (d, g, s, b), in identical order to SPICE convention \nParams: string modelname\n\n`vlsir.primitives.mos` Largely corresponds to the \"M-prefix\" element of Spice-class simulators. \nEach instance maps to a *spice model* instance (\"`m1`\"), *not* to sub-circuit instance (\"`x1`\"). \nIn many cases, particularly for technology-provided devices, using a foundry-provided sub-circuit will be appropriate instead. \n\nThe *sole* required parameter to each `vlsir.primitives.mos` is its string-valued `modelname`. \nAdditional parameters such as physical dimensions are typically model-specific and vary widely between models. \nConversion from `vlsir.primitives.mos` to spice-netlist formats is to pass all such additional parameters unmodified. \n\nExample instantiation:\n\n```python\nInstance(\n    name=\"mos1\",\n    module=Reference(domain=\"vlsir.primitives\", name=\"mos\"),\n    connections=dict(d=d, g=g, s=s, b=b),\n    parameters=dict(\n        modelname=\"my_favorite_nmos\", \n        w=1e-6, \n        geomod=2, # An example highly model-specific parameter\n    ),\n)\n```\n\nCorresponds to netlist-level content along the lines of: \n\n```spice\n.model my_favorite_nmos     * Model statement provided externally \n+ nmos level=53             * Model parameters\n\n* Instance compiled from `vlsir.primitives.mos`:\nmmos1                       * Note the `m` prefix\n+ d g s b                   * Connections \n+ my_favorite_nmos          * Model name\n+ w=1e-6 geomod=2           * Instance parameters, unmodified\n```\n"
  ports {
    signal: "d"
    direction: NONE
  }
  ports {
    signal: "g"
    direction: NONE
  }
  ports {
    signal: "s"
    direction: NONE
  }
  ports {
    signal: "b"
    direction: NONE
  }
  signals {
    name: "d"
    width: 1
  }
  signals {
    name: "g"
    width: 1
  }
  signals {
    name: "s"
    width: 1
  }
  signals {
    name: "b"
    width: 1
  }
  parameters {
    name: "modelname"
    desc: "Model Name (string)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "bipolar"
  }
  desc: "\n# Bipolar Junction Transistor (BJT)\n\nPorts: (c, b, e), in identical order to SPICE convention \nParams: string modelname\n\n`vlsir.primitives.bipolar` Largely corresponds to the \"Q-prefix\" element of Spice-class simulators. \nEach instance maps to a *spice model* instance (\"`q1`\"), *not* to sub-circuit instance (\"`x1`\"). \nIn many cases, particularly for technology-provided devices, using a foundry-provided sub-circuit will be appropriate instead. \n\nUnlike the SPICE BJT, `vlsir.primitives.bipolar` *does not* include an optional fourth substrate terminal. \n\nThe *sole* required parameter to each `vlsir.primitives.bipolar` is its string-valued `modelname`. \nWhile the level-one BJT model has much more prevalence than any MOS model, \nthere remains a diversity of instance parameters not first-class enumerated here. \n\n"
  ports {
    signal: "c"
    direction: NONE
  }
  ports {
    signal: "b"
    direction: NONE
  }
  ports {
    signal: "e"
    direction: NONE
  }
  signals {
    name: "c"
    width: 1
  }
  signals {
    name: "b"
    width: 1
  }
  signals {
    name: "e"
    width: 1
  }
  parameters {
    name: "modelname"
    desc: "Model Name (string)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "diode"
  }
  desc: "\n# Diode\n\nPorts: (p (anode), n (cathode)), in identical order to SPICE convention \nParams: string modelname\n\n`vlsir.primitives.diode` largely corresponds to the \"D-prefix\" element of Spice-class simulators. \nEach instance maps to a *spice model* instance (\"`d1`\"), *not* to sub-circuit instance (\"`x1`\"). \nIn many cases, particularly for technology-provided devices, using a foundry-provided sub-circuit will be appropriate instead. \n\nThe *sole* required parameter to each `vlsir.primitives.diode` is its string-valued `modelname`. \nWhile the level-one diode model has much more prevalence than any MOS model, \nthere remains a diversity of instance parameters not first-class enumerated here. \n\n"
  ports {
    signal: "p"
    direction: NONE
  }
  ports {
    signal: "n"
    direction: NONE
  }
  signals {
    name: "p"
    width: 1
  }
  signals {
    name: "n"
    width: 1
  }
  parameters {
    name: "modelname"
    desc: "Model Name (string)"
  }
}
ext_modules {
  name {
    domain: "vlsir.primitives"
    name: "tline"
  }
  desc: "\n# Transmission Line\n\nPorts: (p1p, p1n, (port 1), p2p, p2n (port 2)), in identical order to SPICE convention \nParams: string modelname\n\nThe *sole* required parameter is the string-valued `modelname`. \nAll other parameters are passed unmodified to netlist-level formats. \n\nThe \"model-based\" tline specification supports lossy lines in all known SPICE-class simulators, \nand lossless lines in many or most. \n\n"
  ports {
    signal: "p1p"
    direction: NONE
  }
  ports {
    signal: "p1n"
    direction: NONE
  }
  ports {
    signal: "p2p"
    direction: NONE
  }
  ports {
    signal: "p2n"
    direction: NONE
  }
  signals {
    name: "p1p"
    width: 1
  }
  signals {
    name: "p1n"
    width: 1
  }
  signals {
    name: "p2p"
    width: 1
  }
  signals {
    name: "p2n"
    width: 1
  }
  parameters {
    name: "modelname"
    desc: "Model Name (string)"
  }
}
desc: "# Vlsir Primitive Modules \n\nDefines `ExternalModule`s for irreducible primitive elements, placing them in the namespace `vlsir.primitives`. \nThe content of `vlsir.primitives` largely parallels the \"elementary devices\" or \"primitive devices\" \nimplemented by Spice-class simulators. (Example: http://bwrcs.eecs.berkeley.edu/Classes/IcBook/SPICE/UserGuide/elements_fr.html)  \n\nMany `vlsir.primitives` accept absolute-value parameters, such as the resistance of `resistor` and the inductance of `inductor`. \nUnless otherwise noted, these parameters are specified in SI units. \n\nEach `vlsir.primitive` also accepts arbitrary \"pass-through\" parameters, which are passed unmodifed when generating netlist-level formats. \nThese parameters will generally be used, for instance, to specify `mos` devices across the wide variety of SPICE-supported models. \n\n"
