Metadata-Version: 2.1
Name: vlsim
Version: 0.0.1
Summary: vlsim is a wrapper around Verilator that adds in a simple C++ front-end for clock generation and trace control
Home-page: https://github.com/mballance/vlsim
Author: Matthew Ballance
Author-email: matt.ballance@gmail.com
License: Apache 2.0
Keywords: SystemVerilog,Verilog,RTL,Verilator
Platform: UNKNOWN

UNKNOWN


