Veriloggen
==========

A library for constructing a Verilog HDL source code in Python

Copyright (C) 2015, Shinya Takamaeda-Yamazaki

E-mail: shinya\_at\_is.naist.jp

License
=======

Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)

What's Veriloggen?
==================

Veriloggen is an open-sourced library for constructing a Verilog HDL
source code in Python.

Veriloggen is not a behavior synthesis (or high level synthesis).
Veriloggen provides a lightweight abstraction of Verilog HDL AST. You
can build up a hardware design written in Verilog HDL very easily by
using the AST abstraction and the entire functionality of Python.

Veriloggen is not designed for designing a hardware by programmer
directly, but is for providing an efficient abstraction to develop a
more efficient domain specific language and tools.

Installation
============

Requirements
------------

-  Python: 2.7, 3.4 or later

Python3 is recommended.

-  Icarus Verilog: 0.9.7 or later

Install on your platform. For exmple, on Ubuntu:

::

    sudo apt-get install iverilog

-  Jinja2: 2.8 or later
-  pytest: 2.8.2 or later
-  pytest-pythonpath: 0.7 or later

Install on your python environment by using pip.

::

    pip install jinja2 pytest pytest-pythonpath

-  Pyverilog: 1.0.0 or later

Install from pip:

::

    pip install pyverilog

Install
-------

Install Veriloggen.

::

    python setup.py install

On Docker
---------

Dockerfile is available, so that you can try Veriloggen on Docker
without any installation on your host platform.

::

    cd docker
    sudo docker build -t user/veriloggen .
    sudo docker run --name veriloggen -i -t user/veriloggen /bin/bash
    cd veriloggen/examples/led/
    make

Getting Started
===============

You can find some examples in 'veriloggen/examples/' and
'veriloggen/tests'.

Let's begin veriloggen by an example. Create a example Python script in
Python as below. A blinking LED hardware is modeled in Python. Open
'hello\_led.py' in the root directory.

.. code:: python

    import sys
    import os
    from veriloggen import *

    def mkLed():
        m = Module('blinkled')
        width = m.Parameter('WIDTH', 8)
        clk = m.Input('CLK')
        rst = m.Input('RST')
        led = m.OutputReg('LED', width)
        count = m.Reg('count', 32)

        m.Always(Posedge(clk))(
            If(rst)(
                count(0)
            ).Else(
                If(count == 1023)(
                    count(0)
                ).Else(
                    count(count + 1)
                )
            ))
        
        m.Always(Posedge(clk))(
            If(rst)(
                led(0)
            ).Else(
                If(count == 1024 - 1)(
                    led(led + 1)
                )
            ))
        
        return m

    if __name__ == '__main__':
        led = mkLed()
        # led.to_verilog(filename='tmp.v')
        verilog = led.to_verilog()
        print(verilog)

Run the script.

::

    python led.py

You will have a complete Verilog HDL source code that is generated by
the source code generator.

.. code:: verilog

    module blinkled #
    (
      parameter WIDTH = 8
    )
    (
      input CLK,
      input RST,
      output reg [(WIDTH - 1):0] LED
    );

      reg [(32 - 1):0] count;

      always @(posedge CLK) begin
        if(RST) begin
          count <= 0;
        end else begin
          if((count == 1023)) begin
            count <= 0;
          end else begin
            count <= (count + 1);
          end
        end
      end


      always @(posedge CLK) begin
        if(RST) begin
          LED <= 0;
        end else begin
          if((count == 1023)) begin
            LED <= (LED + 1);
          end 
        end
      end


    endmodule

Publication
===========

Not yet.

Related Project
===============

`Pyverilog <https://github.com/PyHDI/Pyverilog>`__ - Python-based
Hardware Design Processing Toolkit for Verilog HDL
