Metadata-Version: 2.1
Name: verilog-parser
Version: 0.0.0
Summary: Parser for structural verilog.
Home-page: https://codeberg.org/tok/py-verilog-parser
Author: T. (Benz|Kramer)
Author-email: dont@spam.me
License: AGPL
Keywords: verilog parser
Platform: UNKNOWN
Classifier: License :: OSI Approved :: GNU Affero General Public License v3
Classifier: Development Status :: 3 - Alpha
Classifier: Topic :: Scientific/Engineering
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Classifier: Programming Language :: Python :: 3
Description-Content-Type: text/markdown
Requires-Dist: lark-parser

# Verilog parser for Python
Lark based parser for Verilog netlists (structural Verilog without behavioral statements).
This is meant to be used to read netlists as generated by HDL logic synthesizers such as Yosys.

## Example
```python
from verilog_parser.parser import parse_verilog
ast = parse_verilog(open(verilog_file_path).read())
```


