Metadata-Version: 2.4
Name: vajax
Version: 0.1.5
Summary: JAX-based analog circuit simulator with Verilog-A support
Project-URL: Homepage, https://github.com/ChipFlow/vajax
Project-URL: Documentation, https://chipflow.github.io/vajax/
Project-URL: Repository, https://github.com/ChipFlow/vajax
Project-URL: Issues, https://github.com/ChipFlow/vajax/issues
Project-URL: Changelog, https://github.com/ChipFlow/vajax/releases
Author: ChipFlow
License-Expression: Apache-2.0
Requires-Python: <3.14,>=3.11
Requires-Dist: jax>=0.9.0
Requires-Dist: jaxlib>=0.9.0
Requires-Dist: jaxtyping>=0.2.0
Requires-Dist: matplotlib>=3.7.0
Requires-Dist: numpy>=1.24.0
Requires-Dist: openvaf-py
Requires-Dist: scipy>=1.11.0
Requires-Dist: simpleeval>=1.0.0
Requires-Dist: umfpack-jax
Provides-Extra: cuda12
Requires-Dist: jax-cuda12-plugin>=0.9.0; (sys_platform != 'darwin') and extra == 'cuda12'
Requires-Dist: spineax-vajax>=0.0.2; extra == 'cuda12'
Provides-Extra: dev
Requires-Dist: beartype>=0.18.0; extra == 'dev'
Requires-Dist: osdi-py; extra == 'dev'
Requires-Dist: pyright; extra == 'dev'
Requires-Dist: pytest-cov; extra == 'dev'
Requires-Dist: pytest>=7.4.0; extra == 'dev'
Requires-Dist: ruff; extra == 'dev'
Requires-Dist: scikit-umfpack>=0.4.2; extra == 'dev'
Provides-Extra: docs
Requires-Dist: mkdocs-material>=9.5; extra == 'docs'
Requires-Dist: mkdocs<2,>=1.6; extra == 'docs'
Provides-Extra: sax
Requires-Dist: sax>=0.13.0; extra == 'sax'
Provides-Extra: test
Requires-Dist: beartype>=0.18.0; extra == 'test'
Requires-Dist: osdi-py; extra == 'test'
Requires-Dist: pytest-cov; extra == 'test'
Requires-Dist: pytest>=7.4.0; extra == 'test'
Provides-Extra: umfpack
Requires-Dist: scikit-umfpack>=0.4.2; extra == 'umfpack'
Provides-Extra: umfpack-ffi
Requires-Dist: umfpack-jax; extra == 'umfpack-ffi'
