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pyproject.toml
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.github/workflows/ci.yml
.github/workflows/lint.yml
.github/workflows/wheels.yml
.github/workflows/bin/collect_tests.py
docs/umi_waveforms.py
docs/_images/bad_valid_toggle.svg
docs/_images/example_rw_xaction.svg
docs/_images/hokusai.jpg
docs/_images/hokusai_full.jpg
docs/_images/ok_double_xaction.svg
docs/_images/ok_ready_toggle.svg
docs/_images/ok_ready_valid.svg
docs/_images/ok_sametime.svg
docs/_images/ok_valid_ready.svg
docs/_images/ready_valid.svg
docs/_images/sumi_connections.png
docs/_images/sumi_connections.svg
docs/_images/swizzle_lumi.png
docs/_images/tumi_connections.png
docs/_images/tumi_connections.svg
docs/_images/umi_connections.png
docs/_images/umi_stack.svg
umi/__init__.py
umi.egg-info/PKG-INFO
umi.egg-info/SOURCES.txt
umi.egg-info/dependency_links.txt
umi.egg-info/requires.txt
umi.egg-info/top_level.txt
umi/lumi/README.md
umi/lumi/__init__.py
umi/lumi/rtl/lumi.v
umi/lumi/rtl/lumi_crossbar.v
umi/lumi/rtl/lumi_regmap.vh
umi/lumi/rtl/lumi_regs.v
umi/lumi/rtl/lumi_rx.v
umi/lumi/rtl/lumi_tx.v
umi/lumi/testbench/config.vlt
umi/lumi/testbench/test_lumi.py
umi/lumi/testbench/test_lumi_rnd.py
umi/lumi/testbench/testbench_lumi.sv
umi/sumi/__init__.py
umi/sumi/rtl/umi_arbiter.v
umi/sumi/rtl/umi_crossbar.v
umi/sumi/rtl/umi_decode.v
umi/sumi/rtl/umi_endpoint.v
umi/sumi/rtl/umi_fifo.v
umi/sumi/rtl/umi_fifo_flex.v
umi/sumi/rtl/umi_isolate.v
umi/sumi/rtl/umi_mem_agent.v
umi/sumi/rtl/umi_messages.vh
umi/sumi/rtl/umi_mux.v
umi/sumi/rtl/umi_pack.v
umi/sumi/rtl/umi_pipeline.v
umi/sumi/rtl/umi_priority.v
umi/sumi/rtl/umi_ram.v
umi/sumi/rtl/umi_regif.v
umi/sumi/rtl/umi_splitter.v
umi/sumi/rtl/umi_stimulus.v
umi/sumi/rtl/umi_unpack.v
umi/sumi/testbench/config.vlt
umi/sumi/testbench/dut_umi_fifo.v
umi/sumi/testbench/dut_umi_fifo_flex.v
umi/sumi/testbench/test_crossbar.py
umi/sumi/testbench/test_fifo.py
umi/sumi/testbench/test_fifo_flex.py
umi/sumi/testbench/test_mem_agent.py
umi/sumi/testbench/test_regif.py
umi/sumi/testbench/test_umi_ram.py
umi/sumi/testbench/testbench_crossbar.sv
umi/sumi/testbench/testbench_fifo.sv
umi/sumi/testbench/testbench_fifo_flex.sv
umi/sumi/testbench/testbench_mem_agent.sv
umi/sumi/testbench/testbench_regif.sv
umi/sumi/testbench/testbench_umi_ram.sv
umi/sumi/testbench/umi_testbench.py
umi/sumi/testbench/cpp/umi_testbench.cc
umi/utils/rtl/README.md
umi/utils/rtl/axilite2umi.v
umi/utils/rtl/tl-uh.vh
umi/utils/rtl/tl2umi_np.v
umi/utils/rtl/umi2apb.v
umi/utils/rtl/umi2axilite.v
umi/utils/rtl/umi2tl_np.v
umi/utils/rtl/umi_address_remap.v
umi/utils/rtl/umi_data_aggregator.v
umi/utils/rtl/umi_packet_merge_greedy.v
umi/utils/testbench/buffer.memh
umi/utils/testbench/buffer_axilite.memh
umi/utils/testbench/config.h
umi/utils/testbench/config.vlt
umi/utils/testbench/tb_axilite2umi.v
umi/utils/testbench/tb_tl2umi_np.v
umi/utils/testbench/tb_umi_data_aggregator.v
umi/utils/testbench/test_tl2umi_np.py
umi/utils/testbench/test_umi2apb.py
umi/utils/testbench/test_umi2axilite.py
umi/utils/testbench/test_umi2tl_np.py
umi/utils/testbench/test_umi_address_remap.py
umi/utils/testbench/test_umi_packet_merge_greedy.py
umi/utils/testbench/testbench_umi2apb.sv
umi/utils/testbench/testbench_umi2axilite.sv
umi/utils/testbench/testbench_umi2tl_np.cc
umi/utils/testbench/testbench_umi2tl_np.v
umi/utils/testbench/testbench_umi_address_remap.v
umi/utils/testbench/testbench_umi_packet_merge_greedy.cc
umi/utils/testbench/testbench_umi_packet_merge_greedy.v
umi/utils/testbench/tilelink.h
umi/utils/testbench/tlmemsim.cpp
umi/utils/testbench/tlmemsim.h