#
# MIT License
#
# Copyright (c) 2024 nbiotcloud
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
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# The above copyright notice and this permission notice shall be included in all
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# SOFTWARE.
#
"""Example."""

import ucdp as u
from fileliststandard import HdlFileList
from glbl.bus import BusType
from glbl.clk_gate import ClkGateMod
from ucdp_glbl.stream import StreamType


class IoType(u.AStructType):
    """IO."""

    title: str = "UART"
    comment: str = "RX/TX"

    def _build(self) -> None:
        self._add("rx", u.BitType(), u.BWD)
        self._add("tx", u.BitType(), u.FWD)


class TopMod(u.AMod):
    """Top Module."""

    filelists: u.ClassVar[u.ModFileLists] = (HdlFileList(gen="full"),)

    def _build(self) -> None:  # noqa: PLR0915
        parser = self.parser

        param_p = self.add_param(u.IntegerType(default=10), "param_p")
        width_p = self.add_param(u.IntegerType(default=parser.log2(param_p + 1)), "width_p")
        default_p = self.add_param(u.UintType(param_p), "default_p")

        self.add_port(u.ClkRstAnType(), "main_i")
        self.add_port(IoType(), "intf_i", route="create(u_core/intf_i)")
        self.add_port(BusType(), "bus_i")

        self.add_port(u.UintType(9), "brick_o", ifdef="ASIC")

        self.add_port(u.UintType(param_p), "data_i")
        self.add_port(u.UintType(width_p), "cnt_o")
        self.add_port(StreamType(9), "key_i")
        self.add_port(u.UintType(4), "bidir_io")

        self.add_port(u.UintType(9), "value_o", ifdef="ASIC")

        self.add_const(u.UintType(param_p, default=default_p // 2), "const_c")

        self.add_signal(StreamType(9), "key_s")
        self.add_signal(u.UintType(4), "bidir_s")

        clkgate = ClkGateMod(self, "u_clk_gate")
        clkgate.con("clk_i", "main_clk_i")
        clkgate.con("clk_o", "create(clk_s)")

        core = TopCoreMod(self, "u_core", paramdict={"width_p": width_p, "param_p": param_p})
        param_p = core.add_param(u.IntegerType(default=10), "param_p")
        width_p = core.add_param(u.IntegerType(default=8), "width_p")
        core.add_param(u.SintType(8, default=-3), "other_p")

        core.add_port(u.ClkRstAnType(), "main_i")
        core.add_port(u.UintType(param_p), "p_i")
        core.add_port(u.UintType(param_p), "p_o")
        core.add_port(u.UintType(width_p, logic=False), "data_i")
        core.add_port(u.UintType(width_p), "data_o")
        core.add_port(u.UintType(9), "brick_o", ifdef="ASIC")
        core.add_port(u.UintType(3), "some_i")
        core.add_port(u.UintType(2), "bits_i")

        core.add_port(StreamType(9), "key_i")

        # open inputs/output
        core.add_port(u.RailType(), "open_rail_i")
        core.add_port(u.StringType(), "open_string_i")
        core.add_port(u.ArrayType(u.UintType(6), 4, direction=u.DOWN), "open_array_i")
        core.add_port(u.ArrayType(u.ArrayType(u.UintType(6), param_p), 2), "open_matrix_i")
        core.add_port(u.ArrayType(u.ArrayType(u.UintType(6), param_p, direction=u.DOWN), 2), "matrix_down_i")
        core.add_port(u.RailType(), "open_rail_o")
        core.add_port(u.StringType(), "open_string_o")
        core.add_port(u.ArrayType(u.UintType(6), 4), "open_array_o")
        core.add_port(u.ArrayType(u.ArrayType(u.UintType(6), 4), 2), "open_matrix_o")

        core.add_port(u.UintType(7), "note_i")
        # core.con("note_i", u.OPEN) # bug in UCDP

        core.add_port(u.UintType(7), "nosuffix0", direction=u.IN)
        core.add_port(u.UintType(7), "nosuffix1", direction=u.OUT)

        core.add_signal(u.UintType(width_p), "one_s")
        core.add_signal(u.UintType(width_p, logic=False), "two_s")
        core.add_signal(u.IntegerType(), "integer_s")
        core.add_signal(u.IntegerType(logic=False), "int_s")
        core.add_signal(u.FloatType(), "float_s")
        core.add_signal(u.DoubleType(), "double_s")

        core.add_port(u.ArrayType(u.UintType(8), param_p), "array_i")
        core.add_port(u.ArrayType(u.UintType(8), 8), "array_open_i")
        core.con("array_i", "create(array_s)")
        core.con("brick_o", "brick_o")

        core.con("main_clk_i", "clk_s")
        core.con("main_rst_an_i", "main_rst_an_i")

        core.con("some_i", "3h4")
        core.con("bits_i", "data_i[3:2]")

        self.route("key_s", "key_i")

        self.add_flipflop(u.UintType(9), "data_r", "main_clk_i", "main_rst_an_i", nxt="key_data_s")
        self.add_flipflop(u.UintType(param_p), "data2_r", "main_clk_i", "main_rst_an_i", nxt="data_i")

        self.assign("value_o", "key_data_s")
        # self.route("bidir_s", "bidir_io")


class TopCoreMod(u.ACoreMod):
    """Core Module."""

    filelists: u.ClassVar[u.ModFileLists] = (HdlFileList(gen="full"),)
