// =============================================================================
//
// THIS FILE IS GENERATED!!! DO NOT EDIT MANUALLY. CHANGES ARE LOST.
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// =============================================================================
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//  MIT License
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// =============================================================================
//
// Module:     tests.portgroup_tx
// Data Model: tests.test_svmako.CoreMod
//
// =============================================================================

`begin_keywords "1800-2009"
`default_nettype none  // implicit wires are forbidden

module portgroup_tx #( // tests.test_svmako.CoreMod
  parameter integer width_p = 1
) (
  // main_i
  input logic       main_clk_i,
  input logic       main_rst_an_i,        // Async Reset (Low-Active)
  // regf_i
  // regf_ctrl_ena_i: bus=RW core=RO in_regf=True
  input logic       regf_ctrl_ena_rval_i, // Core Read Value
  // regf_tx_data0_i: bus=RW core=RO in_regf=True
  input logic [1:0] regf_tx_data0_rval_i  // Core Read Value
);


endmodule // portgroup_tx

`default_nettype wire
`end_keywords
