// =============================================================================
//
// THIS FILE IS GENERATED!!! DO NOT EDIT MANUALLY. CHANGES ARE LOST.
//
// =============================================================================
//
//  MIT License
//
//  Copyright (c) 2024 nbiotcloud
//
//  Permission is hereby granted, free of charge, to any person obtaining a copy
//  of this software and associated documentation files (the "Software"), to deal
//  in the Software without restriction, including without limitation the rights
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// =============================================================================
//
// Module:     tests.all_rom5
// Data Model: tests.test_svmako.RomMod
//
//
// Org:         10240x18 (22.5 KB)
// Wordmasks:   0x3FFFF
// Accesslanes: -
// Powerlanes:  -
// Constraints: -
// Segmentation:
//     y/x     0
//      0  10240x18/1
//     Total: 10240x18/1(22.5 KB)
//
// =============================================================================

`begin_keywords "1800-2009"
`default_nettype none  // implicit wires are forbidden

module all_rom5 ( // tests.test_svmako.RomMod
  // main_i
  input  wire                      main_clk_i,
  input  wire                      main_rst_an_i,   // Async Reset (Low-Active)
  // io_i
  // io_main_i
  input  wire                      io_main_ena_i,
  input  wire  [$clog2(10239)-1:0] io_main_addr_i,
  output logic [17:0]              io_main_rdata_o,
  // pwr_i
  // pwr_main_i
  input  wire                      pwr_main_pwr_i
  // tech_i
);



  // ------------------------------------------------------
  //  Signals
  // ------------------------------------------------------
  // mem_s
  // mem_main_s
  logic                     mem_main_ena_s;
  logic [$clog2(10239)-1:0] mem_main_addr_s;
  logic [17:0]              mem_main_rdata_s;

  // ------------------------------------------------------
  //  Assigns
  // ------------------------------------------------------
  // mem_s
  // mem_main_s
  assign mem_main_ena_s  = io_main_ena_i;
  assign mem_main_addr_s = io_main_addr_i;
  assign io_main_rdata_o = mem_main_rdata_s;

endmodule // all_rom5

`default_nettype wire
`end_keywords
