// =============================================================================
//
// THIS FILE IS GENERATED!!! DO NOT EDIT MANUALLY. CHANGES ARE LOST.
//
// =============================================================================
//
//  MIT License
//
//  Copyright (c) 2024 nbiotcloud
//
//  Permission is hereby granted, free of charge, to any person obtaining a copy
//  of this software and associated documentation files (the "Software"), to deal
//  in the Software without restriction, including without limitation the rights
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// =============================================================================
//
// Module:     ucdp_amba.ucdp_ahb2ahb_example_usertp_minp_hsp_p
// Data Model: ucdp_amba.ucdp_ahb2ahb.UcdpAhb2ahbMod
//
//
// Converting Master to Master
//
// Signal    Src Tgt Conv
// hwrite     x   x  forward
// htrans     x   x  forward
// hsize      x   x  forward
// hresp      x   x  forward
// hsel       -   -  n/a
// haddr      x   x  forward
// hwdata     x   x  forward
// hrdata     x   x  forward
// hwstrb     -   -  n/a
// hburst     -   -  n/a
// hnonsec    -   -  n/a
// hmastlock  -   -  n/a
// hauser     -   x  tie-off
// hwuser     -   x  tie-off
// hruser     x   -  ignore
// hbuser     x   -  ignore
// hmaster    -   -  n/a
// hexcl      -   -  n/a
// hexokay    -   -  n/a
// hready     x   x  forward
// hreadyout  -   -  n/a
// hprot      -   -  n/a
//
// =============================================================================

`begin_keywords "1800-2009"
`default_nettype none  // implicit wires are forbidden

module ucdp_ahb2ahb_example_usertp_minp_hsp_p ( // ucdp_amba.ucdp_ahb2ahb.UcdpAhb2ahbMod
  // ahb_src_i: AHB Source
  input  logic [1:0]  ahb_src_htrans_i, // AHB Transfer Type
  input  logic [31:0] ahb_src_haddr_i,  // AHB Bus Address
  input  logic        ahb_src_hwrite_i, // AHB Write Enable
  input  logic [2:0]  ahb_src_hsize_i,  // AHB Size
  input  logic [31:0] ahb_src_hwdata_i, // AHB Data
  output logic        ahb_src_hready_o, // AHB Transfer Done
  output logic        ahb_src_hresp_o,  // AHB Response Error
  output logic [31:0] ahb_src_hrdata_o, // AHB Data
  // ahb_tgt_o: AHB Target
  output logic [1:0]  ahb_tgt_htrans_o, // AHB Transfer Type
  output logic [31:0] ahb_tgt_haddr_o,  // AHB Bus Address
  output logic [4:0]  ahb_tgt_hauser_o, // AHB Address User Channel
  output logic [4:0]  ahb_tgt_hwuser_o, // AHB Write Data User Channel
  output logic        ahb_tgt_hwrite_o, // AHB Write Enable
  output logic [2:0]  ahb_tgt_hsize_o,  // AHB Size
  output logic [31:0] ahb_tgt_hwdata_o, // AHB Data
  input  logic        ahb_tgt_hready_i, // AHB Transfer Done
  input  logic        ahb_tgt_hresp_i,  // AHB Response Error
  input  logic [31:0] ahb_tgt_hrdata_i, // AHB Data
  input  logic [4:0]  ahb_tgt_hruser_i, // AHB Read Data User Channel
  input  logic [4:0]  ahb_tgt_hbuser_i, // AHB Read Response User Channel
  input  logic [4:0]  hauser_ext_i,     // Target HAUSER Extension
  input  logic [4:0]  hwuser_ext_i      // Target HWUSER Extension
);




  // ------------------------------------------------------
  //  Local Parameter
  // ------------------------------------------------------
  // ahb_trans
  localparam integer       ahb_trans_width_p   = 2;
  localparam logic   [1:0] ahb_trans_min_p     = 2'h0; // AHB Transfer Type
  localparam logic   [1:0] ahb_trans_max_p     = 2'h3; // AHB Transfer Type
  localparam logic   [1:0] ahb_trans_idle_e    = 2'h0;
  localparam logic   [1:0] ahb_trans_busy_e    = 2'h1;
  localparam logic   [1:0] ahb_trans_nonseq_e  = 2'h2;
  localparam logic   [1:0] ahb_trans_seq_e     = 2'h3;
  localparam logic   [1:0] ahb_trans_default_p = 2'h0; // AHB Transfer Type
  // ahb_burst
  localparam integer       ahb_burst_width_p   = 3;
  localparam logic   [2:0] ahb_burst_min_p     = 3'h0; // AHB Burst Type
  localparam logic   [2:0] ahb_burst_max_p     = 3'h7; // AHB Burst Type
  localparam logic   [2:0] ahb_burst_single_e  = 3'h0;
  localparam logic   [2:0] ahb_burst_incr_e    = 3'h1;
  localparam logic   [2:0] ahb_burst_wrap4_e   = 3'h2;
  localparam logic   [2:0] ahb_burst_incr4_e   = 3'h3;
  localparam logic   [2:0] ahb_burst_wrap8_e   = 3'h4;
  localparam logic   [2:0] ahb_burst_incr8_e   = 3'h5;
  localparam logic   [2:0] ahb_burst_wrap16_e  = 3'h6;
  localparam logic   [2:0] ahb_burst_incr16_e  = 3'h7;
  localparam logic   [2:0] ahb_burst_default_p = 3'h0; // AHB Burst Type



  // TODO: handle async


  // === standard forwarding ============
  assign ahb_tgt_htrans_o = ahb_src_htrans_i;
  assign ahb_tgt_hwrite_o = ahb_src_hwrite_i;
  assign ahb_tgt_hsize_o = ahb_src_hsize_i;
  assign ahb_src_hresp_o = ahb_tgt_hresp_i;

  // === haddr handling =================
  assign ahb_tgt_haddr_o = ahb_src_haddr_i;



  // === hxdata handling ================
  // just forward read/write data
  assign ahb_tgt_hwdata_o = ahb_src_hwdata_i;
  assign ahb_src_hrdata_o = ahb_tgt_hrdata_i;


  // === hready handling ================
  assign ahb_src_hready_o = ahb_tgt_hready_i;







  // === hauser handling =================
  assign ahb_tgt_hauser_o = hauser_ext_i;

  // === hwuser handling =================
  assign ahb_tgt_hwuser_o = hwuser_ext_i;




endmodule // ucdp_ahb2ahb_example_usertp_minp_hsp_p

`default_nettype wire
`end_keywords
