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//
// THIS FILE IS GENERATED!!! DO NOT EDIT MANUALLY. CHANGES ARE LOST.
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//  MIT License
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//  Copyright (c) 2024 nbiotcloud
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// =============================================================================
//
// Module:     ucdp_amba.ucdp_ahb2ahb_example_usertp_hep_hep_e
// Data Model: ucdp_amba.ucdp_ahb2ahb.UcdpAhb2ahbMod
//
//
// No conversion, just feed-through.
//
// =============================================================================

`begin_keywords "1800-2009"
`default_nettype none  // implicit wires are forbidden

module ucdp_ahb2ahb_example_usertp_hep_hep_e ( // ucdp_amba.ucdp_ahb2ahb.UcdpAhb2ahbMod
  // ahb_src_i: AHB Source
  input  logic [1:0]  ahb_src_htrans_i, // AHB Transfer Type
  input  logic [31:0] ahb_src_haddr_i,  // AHB Bus Address
  input  logic [3:0]  ahb_src_hauser_i, // AHB Address User Channel
  input  logic [3:0]  ahb_src_hwuser_i, // AHB Write Data User Channel
  input  logic        ahb_src_hwrite_i, // AHB Write Enable
  input  logic [2:0]  ahb_src_hsize_i,  // AHB Size
  input  logic [31:0] ahb_src_hwdata_i, // AHB Data
  output logic        ahb_src_hready_o, // AHB Transfer Done
  output logic        ahb_src_hresp_o,  // AHB Response Error
  output logic [31:0] ahb_src_hrdata_o, // AHB Data
  output logic [3:0]  ahb_src_hruser_o, // AHB Read Data User Channel
  output logic [3:0]  ahb_src_hbuser_o, // AHB Read Response User Channel
  // ahb_tgt_o: AHB Target
  output logic [1:0]  ahb_tgt_htrans_o, // AHB Transfer Type
  output logic [31:0] ahb_tgt_haddr_o,  // AHB Bus Address
  output logic [3:0]  ahb_tgt_hauser_o, // AHB Address User Channel
  output logic [3:0]  ahb_tgt_hwuser_o, // AHB Write Data User Channel
  output logic        ahb_tgt_hwrite_o, // AHB Write Enable
  output logic [2:0]  ahb_tgt_hsize_o,  // AHB Size
  output logic [31:0] ahb_tgt_hwdata_o, // AHB Data
  input  logic        ahb_tgt_hready_i, // AHB Transfer Done
  input  logic        ahb_tgt_hresp_i,  // AHB Response Error
  input  logic [31:0] ahb_tgt_hrdata_i, // AHB Data
  input  logic [3:0]  ahb_tgt_hruser_i, // AHB Read Data User Channel
  input  logic [3:0]  ahb_tgt_hbuser_i  // AHB Read Response User Channel
);





  // TODO: handle async


  // === standard forwarding ============
  assign ahb_tgt_htrans_o = ahb_src_htrans_i;
  assign ahb_tgt_hwrite_o = ahb_src_hwrite_i;
  assign ahb_tgt_hsize_o = ahb_src_hsize_i;
  assign ahb_src_hresp_o = ahb_tgt_hresp_i;

  // === haddr handling =================
  assign ahb_tgt_haddr_o = ahb_src_haddr_i;



  // === hxdata handling ================
  // just forward read/write data
  assign ahb_tgt_hwdata_o = ahb_src_hwdata_i;
  assign ahb_src_hrdata_o = ahb_tgt_hrdata_i;


  // === hready handling ================
  assign ahb_src_hready_o = ahb_tgt_hready_i;







  // === hauser handling =================
  assign ahb_tgt_hauser_o = ahb_src_hauser_i;

  // === hwuser handling =================
  assign ahb_tgt_hwuser_o = ahb_src_hwuser_i;

  // === hruser handling =================
  assign ahb_src_hruser_o = ahb_tgt_hruser_i;

  // === hbuser handling =================
  assign ahb_src_hbuser_o = ahb_tgt_hbuser_i;


endmodule // ucdp_ahb2ahb_example_usertp_hep_hep_e

`default_nettype wire
`end_keywords
