.flake8
.gitignore
.gitlab-ci.yml
license.rst
pyproject.toml
readme.rst
requirements.txt
requirements_develop.txt
setup.py
doc/readme/badges.rst
doc/release_notes/0.1.0.rst
doc/release_notes/0.1.1.rst
doc/release_notes/0.1.2.rst
doc/release_notes/0.1.3.rst
doc/release_notes/0.1.4.rst
doc/release_notes/1.0.0.rst
doc/release_notes/1.0.1.rst
doc/release_notes/2.0.0.rst
doc/release_notes/3.0.0.rst
doc/release_notes/4.0.0.rst
doc/release_notes/4.0.1.rst
doc/release_notes/5.0.0.rst
doc/release_notes/6.0.0.rst
doc/release_notes/7.0.0.rst
doc/release_notes/8.0.0.rst
doc/release_notes/8.0.1.rst
doc/release_notes/unreleased.rst
doc/sphinx/Python-logo-notext.svg
doc/sphinx/conf.py
doc/sphinx/contributing.rst
doc/sphinx/formal.rst
doc/sphinx/fpga_build.rst
doc/sphinx/index.rst
doc/sphinx/license_information.rst
doc/sphinx/module_structure.rst
doc/sphinx/netlist_build.rst
doc/sphinx/registers.rst
doc/sphinx/release_notes.rst
doc/sphinx/robots.txt
doc/sphinx/simulation.rst
doc/sphinx/api_reference/tsfpga.registers.rst
doc/sphinx/api_reference/tsfpga.rst
doc/sphinx/api_reference/tsfpga.vivado.rst
doc/sphinx/files/ci_deploy_jobs.png
doc/sphinx/files/ci_deploy_pipelines.png
doc/sphinx/files/formal_sby_example.sby
docker/readme.rst
docker/formal/Dockerfile
examples/__init__.py
examples/build.py
examples/formal.py
examples/run_formal.sh
examples/simulate.py
examples/tsfpga_example_env.py
examples/modules/artyz7/module_artyz7.py
examples/modules/artyz7/regs_artyz7.toml
examples/modules/artyz7/src/artyz7_top.vhd
examples/modules/artyz7/src/artyz7_top_pkg.vhd
examples/modules/artyz7/src/block_design_pkg.vhd
examples/modules/artyz7/src/block_design_wrapper.vhd
examples/modules/artyz7/tcl/artyz7_pinning.tcl
examples/modules/artyz7/tcl/block_design.tcl
examples/modules/artyz7/test/block_design_mock.vhd
examples/modules/artyz7/test/tb_artyz7_top.vhd
examples/modules/artyz7/test/top_level_sim_pkg.vhd
examples/modules/ddr_buffer/module_ddr_buffer.py
examples/modules/ddr_buffer/regs_ddr_buffer.toml
examples/modules/ddr_buffer/sim/ddr_buffer_sim_pkg.vhd
examples/modules/ddr_buffer/sim/example_reg_operations_pkg.vhd
examples/modules/ddr_buffer/src/ddr_buffer_top.vhd
examples/modules/ddr_buffer/test/tb_ddr_buffer.vhd
examples/modules_with_ip/module_with_ip_cores/ip_cores/fifo_generator_0.tcl
examples/modules_with_ip/module_with_ip_cores/ip_cores/mult_u12_u5.tcl
examples/modules_with_ip/module_with_ip_cores/src/mult.vhd
examples/modules_with_ip/module_with_ip_cores/test/tb_mult.vhd
modules/axi/module_axi.py
modules/axi/src/axi_address_fifo.vhd
modules/axi/src/axi_b_fifo.vhd
modules/axi/src/axi_lite_cdc.vhd
modules/axi/src/axi_lite_mux.vhd
modules/axi/src/axi_lite_pipeline.vhd
modules/axi/src/axi_lite_pkg.vhd
modules/axi/src/axi_lite_simple_read_crossbar.vhd
modules/axi/src/axi_lite_simple_write_crossbar.vhd
modules/axi/src/axi_lite_to_vec.vhd
modules/axi/src/axi_pkg.vhd
modules/axi/src/axi_r_fifo.vhd
modules/axi/src/axi_read_cdc.vhd
modules/axi/src/axi_read_throttle.vhd
modules/axi/src/axi_simple_read_crossbar.vhd
modules/axi/src/axi_simple_write_crossbar.vhd
modules/axi/src/axi_stream_fifo.vhd
modules/axi/src/axi_stream_pkg.vhd
modules/axi/src/axi_to_axi_lite.vhd
modules/axi/src/axi_to_axi_lite_vec.vhd
modules/axi/src/axi_w_fifo.vhd
modules/axi/src/axi_write_cdc.vhd
modules/axi/src/axi_write_throttle.vhd
modules/axi/test/tb_axi_cdc.vhd
modules/axi/test/tb_axi_fifo.vhd
modules/axi/test/tb_axi_lite_cdc.vhd
modules/axi/test/tb_axi_lite_mux.vhd
modules/axi/test/tb_axi_lite_pipeline.vhd
modules/axi/test/tb_axi_lite_pkg.vhd
modules/axi/test/tb_axi_pkg.vhd
modules/axi/test/tb_axi_simple_crossbar.vhd
modules/axi/test/tb_axi_stream_fifo.vhd
modules/axi/test/tb_axi_stream_pkg.vhd
modules/axi/test/tb_axi_to_axi_lite.vhd
modules/axi/test/tb_axi_to_axi_lite_bus_error.vhd
modules/axi/test/tb_axi_to_axi_lite_vec.vhd
modules/bfm/sim/axi_lite_master.vhd
modules/bfm/sim/axi_lite_read_slave.vhd
modules/bfm/sim/axi_lite_slave.vhd
modules/bfm/sim/axi_lite_write_slave.vhd
modules/bfm/sim/axi_master.vhd
modules/bfm/sim/axi_read_slave.vhd
modules/bfm/sim/axi_slave.vhd
modules/bfm/sim/axi_slave_pkg.vhd
modules/bfm/sim/axi_write_slave.vhd
modules/bfm/sim/bfm_pkg.vhd
modules/common/module_common.py
modules/common/src/addr_pkg.vhd
modules/common/src/attribute_pkg.vhd
modules/common/src/clock_counter.vhd
modules/common/src/common_pkg.vhd
modules/common/src/debounce.vhd
modules/common/src/handshake_pipeline.vhd
modules/common/src/handshake_splitter.vhd
modules/common/src/periodic_pulser.vhd
modules/common/src/types_pkg.vhd
modules/common/src/width_conversion.vhd
modules/common/test/tb_addr_pkg.vhd
modules/common/test/tb_clock_counter.vhd
modules/common/test/tb_debounce.vhd
modules/common/test/tb_handshake_pipeline.vhd
modules/common/test/tb_handshake_splitter.vhd
modules/common/test/tb_periodic_pulser.vhd
modules/common/test/tb_types_pkg.vhd
modules/common/test/tb_width_conversion.vhd
modules/fifo/module_fifo.py
modules/fifo/rtl/fifo_netlist_build_wrapper.vhd
modules/fifo/scoped_constraints/asynchronous_fifo.tcl
modules/fifo/src/asynchronous_fifo.vhd
modules/fifo/src/fifo.vhd
modules/fifo/src/fifo_wrapper.vhd
modules/fifo/test/tb_asynchronous_fifo.vhd
modules/fifo/test/tb_fifo.vhd
modules/math/module_math.py
modules/math/src/math_pkg.vhd
modules/math/src/unsigned_divider.vhd
modules/math/test/tb_math_pkg.vhd
modules/math/test/tb_unsigned_divider.vhd
modules/reg_file/module_reg_file.py
modules/reg_file/rtl/axi_lite_reg_file_wrapper.vhd
modules/reg_file/sim/reg_operations_pkg.vhd
modules/reg_file/src/axi_lite_reg_file.vhd
modules/reg_file/src/interrupt_register.vhd
modules/reg_file/src/reg_file_pkg.vhd
modules/reg_file/test/tb_axi_lite_reg_file.vhd
modules/reg_file/test/tb_interrupt_register.vhd
modules/reg_file/test/tb_reg_file_pkg.vhd
modules/reg_file/test/tb_reg_operations_pkg.vhd
modules/resync/module_resync.py
modules/resync/scoped_constraints/resync_counter.tcl
modules/resync/scoped_constraints/resync_level.tcl
modules/resync/scoped_constraints/resync_level_on_signal.tcl
modules/resync/scoped_constraints/resync_slv_level_coherent.tcl
modules/resync/src/resync_counter.vhd
modules/resync/src/resync_cycles.vhd
modules/resync/src/resync_level.vhd
modules/resync/src/resync_level_on_signal.vhd
modules/resync/src/resync_pulse.vhd
modules/resync/src/resync_slv_level.vhd
modules/resync/src/resync_slv_level_coherent.vhd
modules/resync/src/resync_slv_level_on_signal.vhd
modules/resync/test/tb_resync_counter.vhd
modules/resync/test/tb_resync_cycles.vhd
modules/resync/test/tb_resync_pulse.vhd
modules/resync/test/tb_resync_slv_level.vhd
modules/resync/test/tb_resync_slv_level_on_signal.vhd
tools/build_docs.py
tools/release.py
tsfpga/__init__.py
tsfpga/about.py
tsfpga/build_project_list.py
tsfpga/build_step_tcl_hook.py
tsfpga/constraint.py
tsfpga/create_vhdl_ls_config.py
tsfpga/formal_project.py
tsfpga/git_simulation_subset.py
tsfpga/git_utils.py
tsfpga/hdl_file.py
tsfpga/ip_core_file.py
tsfpga/module.py
tsfpga/module_list.py
tsfpga/sby_writer.py
tsfpga/svn_utils.py
tsfpga/system_utils.py
tsfpga/yosys_project.py
tsfpga.egg-info/PKG-INFO
tsfpga.egg-info/SOURCES.txt
tsfpga.egg-info/dependency_links.txt
tsfpga.egg-info/not-zip-safe
tsfpga.egg-info/requires.txt
tsfpga.egg-info/top_level.txt
tsfpga/registers/__init__.py
tsfpga/registers/bit.py
tsfpga/registers/bit_vector.py
tsfpga/registers/constant.py
tsfpga/registers/html_translator.py
tsfpga/registers/parser.py
tsfpga/registers/register.py
tsfpga/registers/register_array.py
tsfpga/registers/register_c_generator.py
tsfpga/registers/register_code_generator.py
tsfpga/registers/register_cpp_generator.py
tsfpga/registers/register_field.py
tsfpga/registers/register_html_generator.py
tsfpga/registers/register_list.py
tsfpga/registers/register_python_generator.py
tsfpga/registers/register_vhdl_generator.py
tsfpga/registers/test/__init__.py
tsfpga/registers/test/conftest.py
tsfpga/registers/test/test_bit.py
tsfpga/registers/test/test_bit_vector.py
tsfpga/registers/test/test_constant.py
tsfpga/registers/test/test_html_translator.py
tsfpga/registers/test/test_parser.py
tsfpga/registers/test/test_register.py
tsfpga/registers/test/test_register_array.py
tsfpga/registers/test/test_register_code_generation.py
tsfpga/registers/test/test_register_html_generator.py
tsfpga/registers/test/test_register_list.py
tsfpga/registers/test/test_register_python_generator.py
tsfpga/registers/test/test_register_vhdl_generator.py
tsfpga/test/__init__.py
tsfpga/test/conftest.py
tsfpga/test/test_utils.py
tsfpga/test/functional/__init__.py
tsfpga/test/functional/commercial_simulators/__init__.py
tsfpga/test/functional/commercial_simulators/test_compilation.py
tsfpga/test/functional/gcc/__init__.py
tsfpga/test/functional/gcc/test_register_compilation.py
tsfpga/test/functional/vivado/__init__.py
tsfpga/test/functional/vivado/test_building_vivado_project.py
tsfpga/test/lint/__init__.py
tsfpga/test/lint/pylintrc
tsfpga/test/lint/pylintrc_original
tsfpga/test/lint/test_copyright.py
tsfpga/test/lint/test_file_format.py
tsfpga/test/lint/test_python_lint.py
tsfpga/test/unit/__init__.py
tsfpga/test/unit/test_build_project_list.py
tsfpga/test/unit/test_build_step_tcl_hook.py
tsfpga/test/unit/test_constraint.py
tsfpga/test/unit/test_formal_project.py
tsfpga/test/unit/test_git_simulation_subset.py
tsfpga/test/unit/test_git_utils.py
tsfpga/test/unit/test_hdl_file.py
tsfpga/test/unit/test_ip_core_file.py
tsfpga/test/unit/test_module.py
tsfpga/test/unit/test_module_list.py
tsfpga/test/unit/test_sby_writer.py
tsfpga/test/unit/test_svn_utils.py
tsfpga/test/unit/test_system_utils.py
tsfpga/test/unit/test_yosys_project.py
tsfpga/vivado/__init__.py
tsfpga/vivado/build_result.py
tsfpga/vivado/build_result_checker.py
tsfpga/vivado/common.py
tsfpga/vivado/hierarchical_utilization_parser.py
tsfpga/vivado/ip_cores.py
tsfpga/vivado/logic_level_distribution_parser.py
tsfpga/vivado/project.py
tsfpga/vivado/simlib.py
tsfpga/vivado/simlib_commercial.py
tsfpga/vivado/simlib_common.py
tsfpga/vivado/simlib_ghdl.py
tsfpga/vivado/tcl.py
tsfpga/vivado/tcl/check_timing.tcl
tsfpga/vivado/tcl/report_logic_level_distribution.tcl
tsfpga/vivado/tcl/report_utilization.tcl
tsfpga/vivado/tcl/vivado_default_run.tcl
tsfpga/vivado/tcl/vivado_fast_run.tcl
tsfpga/vivado/tcl/vivado_messages.tcl
tsfpga/vivado/test/__init__.py
tsfpga/vivado/test/conftest.py
tsfpga/vivado/test/test_build_result.py
tsfpga/vivado/test/test_build_result_checker.py
tsfpga/vivado/test/test_common.py
tsfpga/vivado/test/test_hierarchical_utilization_parser.py
tsfpga/vivado/test/test_ip_cores.py
tsfpga/vivado/test/test_logic_level_distribution_parser.py
tsfpga/vivado/test/test_project.py
tsfpga/vivado/test/test_simlib.py
tsfpga/vivado/test/test_tcl.py