Added

* Add ``fifo.fifo_wrapper`` VHDL entity.
* Add ``drop_packet`` support to synchronous and asynchronous FIFOs.
* Add check for pulse width timing violations after implementation in Vivado build system.
* Check clock interaction after implementation as well in Vivado build system.
* Add ``common.clock_counter`` VHDL entity.
* Add ``bfm.axi_read_slave``, ``bfm.axi_write_slave``, ``bfm.axil_read_slave`` and
  ``bfm.axil_write_slave`` VHDL entities.

Breaking changes

* Rename ``fifo.afifo`` to ``fifo.asynchronous_fifo``.
* Rename :class:`.vivado.project.VivadoNetlistProject` constructor
  argument ``analyze_clock_interaction`` to ``analyze_synthesis_timing``.
* Remove ``tsfpga.vivado.size_checker.Dsp48Blocks`` in favor
  of ``.vivado.size_checker.DspBlocks``.
* Add a pipelining step to improve timing of ``axi.axi_read_throttle`` and
  ``axi.axi_write_throttle``. This introduces three new generics that must be set.
* Change ``bfm.axi_slave`` and ``bfm.axil_slave`` interfaces to require two ``axi_slave_t``
  generics: ``axi_read_slave`` and ``axi_write_slave``.
* Break ``axi.axi_simple_crossbar`` into ``axi.axi_simple_read_crossbar`` and ``axi.axi_simple_write_crossbar``.
* Break ``axi.axil_simple_crossbar`` into ``axi.axil_simple_read_crossbar`` and ``axi.axil_simple_write_crossbar``.

Changes

* Update timing of ``fifo.fifo`` port ``read_ready`` to get lower fanout and shorter critical path.
  The change implies an increased latency from a read transaction until ``write_ready`` is raised.
