module trme_top (
    input wire clk,
    input wire rst_n,

    // Instruction Bus
    input wire [31:0] instruction,

    // Data Bus (Simplified)
    input wire [31:0] data_in,
    output reg [31:0] data_out
);

    // Decode Opcode
    wire [7:0] opcode = instruction[31:24];

    // Instantiation of Tropical Unit
    wire [31:0] trop_res;
    tropical_alu trop_inst (
        .clk(clk),
        .rst_n(rst_n),
        .a(data_in), // Simplification: Source A from input
        .b(data_in), // Simplification: Source B from input (placeholder)
        .opcode(instruction[1:0]),
        .result(trop_res)
    );

    // Instantiation of RSR Unit
    wire [31:0] rsr_res;
    rsr_unit rsr_inst (
        .clk(clk),
        .rst_n(rst_n),
        .write_en(instruction[2]),
        .lut_addr(instruction[10:3]),
        .lut_wdata(data_in),
        .a0(data_in[1:0]), .a1(data_in[3:2]), .a2(data_in[5:4]), .a3(data_in[7:6]),
        .result(rsr_res)
    );

    // Output Mux
    always @(*) begin
        case (opcode)
            8'h10: data_out = trop_res; // Tropical Ops
            8'h20: data_out = rsr_res;  // RSR Ops
            default: data_out = 32'b0;
        endcase
    end

endmodule
