module hbm_axi_stub #(
    parameter DATA_WIDTH = 512, // Standard HBM2 width per channel
    parameter ADDR_WIDTH = 32
)(
    input wire aclk,
    input wire aresetn,

    // AXI4 Read Channel
    input wire [ADDR_WIDTH-1:0] araddr,
    input wire arvalid,
    output reg arready,
    output reg [DATA_WIDTH-1:0] rdata,
    output reg rvalid,
    input wire rready

    // Write channel omitted for brevity in stub
);

    // Simple delay line to simulate HBM latency (e.g., 20 cycles)
    reg [4:0] latency_counter;
    reg [ADDR_WIDTH-1:0] latched_addr;
    reg processing_read;

    // Pseudo-random data generator based on address
    function [DATA_WIDTH-1:0] get_mem_data;
        input [ADDR_WIDTH-1:0] addr;
        begin
            get_mem_data = {16{addr}}; // Replicate address as data
        end
    endfunction

    always @(posedge aclk or negedge aresetn) begin
        if (!aresetn) begin
            arready <= 1;
            rvalid <= 0;
            processing_read <= 0;
            latency_counter <= 0;
        end else begin
            // Address Phase
            if (arvalid && arready) begin
                latched_addr <= araddr;
                processing_read <= 1;
                arready <= 0; // Busy
                latency_counter <= 10; // Simulate latency
            end

            // Latency Simulation
            if (processing_read) begin
                if (latency_counter > 0) begin
                    latency_counter <= latency_counter - 1;
                end else begin
                    // Data Phase
                    if (!rvalid || rready) begin
                        rdata <= get_mem_data(latched_addr);
                        rvalid <= 1;
                        processing_read <= 0;
                        arready <= 1; // Ready for next
                    end
                end
            end else if (rready) begin
                rvalid <= 0;
            end
        end
    end

endmodule
