module rsr_unit #(
    parameter BLOCK_SIZE = 4, // 4 inputs
    parameter WIDTH = 8,      // 8-bit inputs
    parameter ACC_WIDTH = 32
)(
    input wire clk,
    input wire rst_n,
    input wire write_en, // 1 to write to LUT, 0 to lookup
    input wire [7:0] lut_addr, // Index for LUT writing (0-255)
    input wire [ACC_WIDTH-1:0] lut_wdata, // Data to write to LUT

    // Inputs for Lookup Operation
    input wire [1:0] a0, input wire [1:0] a1, input wire [1:0] a2, input wire [1:0] a3, // 2-bit slices of A

    output reg [ACC_WIDTH-1:0] result
);

    // 4 inputs of 2 bits = 8 bits address space = 256 entries
    localparam LUT_DEPTH = 1 << (2 * BLOCK_SIZE);

    // The Lookup Table
    reg [ACC_WIDTH-1:0] lut [0:LUT_DEPTH-1];

    // Address generation from A inputs
    wire [7:0] lookup_addr;
    assign lookup_addr = {a3, a2, a1, a0}; // Concatenate to form address

    always @(posedge clk) begin
        if (write_en) begin
            lut[lut_addr] <= lut_wdata;
        end else begin
            result <= lut[lookup_addr];
        end
    end

endmodule
