`timescale 1ns / 1ps

module tb_lns_adder;

    reg clk;
    reg rst_n;
    reg [31:0] la, lb;
    wire [31:0] lc;

    // Instantiate DUT
    lns_adder dut (
        .clk(clk),
        .rst_n(rst_n),
        .la(la),
        .lb(lb),
        .lc(lc)
    );

    // Clock gen
    always #5 clk = ~clk;

    initial begin
        // Init
        clk = 0;
        rst_n = 0;
        la = 0; lb = 0;

        #20 rst_n = 1;

        // Test Case 1: Equal values (log(A) + log(A) = log(2A) = log(A) + 1.0)
        // 1.0 in Fixed 16.16 is 0x00010000
        la = 32'h00050000; // log(32)
        lb = 32'h00050000;
        #10;
        $display("Test 1: LA=%h LB=%h LC=%h", la, lb, lc);
        // Expected LC approx 0x00060000 (log(64))

        // Test Case 2: Large diff
        la = 32'h000A0000;
        lb = 32'h00010000;
        #10;
        $display("Test 2: LA=%h LB=%h LC=%h", la, lb, lc);

        $finish;
    end

endmodule
