`timescale 1ns / 1ps

module tb_systolic;

    reg clk;
    reg rst_n;
    reg [31:0] a0, a1, a2, a3;
    reg [31:0] b0, b1, b2, b3;
    wire [31:0] c00, c01, c02, c03;
    wire [31:0] c33;

    systolic_array_4x4 dut (
        .clk(clk),
        .rst_n(rst_n),
        .a0(a0), .a1(a1), .a2(a2), .a3(a3),
        .b0(b0), .b1(b1), .b2(b2), .b3(b3),
        .c00(c00), .c01(c01), .c02(c02), .c03(c03),
        .c33(c33)
    );

    always #5 clk = ~clk;

    initial begin
        clk = 0; rst_n = 0;
        a0=0; a1=0; a2=0; a3=0;
        b0=0; b1=0; b2=0; b3=0;

        #15 rst_n = 1;

        // Systolic Feed
        // Cycle 0: Feed A[0,0] and B[0,0]
        a0 = 10; b0 = 5; // C00 should be max(0, 10+5) = 15

        #10;
        // Cycle 1: Feed A[0,1], B[1,0] ...
        // For standard systolic, we need to skew inputs.
        // Array expects A row i at T=i, B col j at T=j.
        // Let's just feed constant stream for test.
        a0 = 10; b0 = 5;
        a1 = 20; b1 = 5;

        #50;
        $display("C00: %d (Expected 15+)", c00);

        $finish;
    end

endmodule
