module rns_core #(
    parameter NUM_CHANNELS = 3,
    parameter [7:0] M0 = 251,
    parameter [7:0] M1 = 253,
    parameter [7:0] M2 = 255
)(
    input wire clk,
    input wire rst_n,
    input wire [1:0] opcode, // 01: ADD, 10: MUL
    // Channel Inputs (Residues)
    input wire [7:0] a_0, input wire [7:0] a_1, input wire [7:0] a_2,
    input wire [7:0] b_0, input wire [7:0] b_1, input wire [7:0] b_2,
    // Channel Outputs
    output reg [7:0] res_0, output reg [7:0] res_1, output reg [7:0] res_2
);

    // RNS operations are parallel and carry-free between channels.

    // Channel 0 Logic
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) res_0 <= 0;
        else begin
            if (opcode == 2'b01) res_0 <= (a_0 + b_0) % M0;
            else if (opcode == 2'b10) res_0 <= (a_0 * b_0) % M0;
        end
    end

    // Channel 1 Logic
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) res_1 <= 0;
        else begin
            if (opcode == 2'b01) res_1 <= (a_1 + b_1) % M1;
            else if (opcode == 2'b10) res_1 <= (a_1 * b_1) % M1;
        end
    end

    // Channel 2 Logic
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) res_2 <= 0;
        else begin
            if (opcode == 2'b01) res_2 <= (a_2 + b_2) % M2;
            else if (opcode == 2'b10) res_2 <= (a_2 * b_2) % M2;
        end
    end

endmodule
