// Co-Simulation Testbench using Verilator
#include <verilated.h>
// #include "Vsystolic_array_NxN.h" // Generated header

// Wrapper for Python ctypes
extern "C" {

void sim_step(const int* a_in, const int* b_in, int* c_out, int cycles) {
    // Vsystolic_array_NxN* top = new Vsystolic_array_NxN;

    // top->clk = 0; top->eval();
    // top->rst_n = 0; top->clk = 1; top->eval(); top->clk = 0; top->eval();
    // top->rst_n = 1;

    for (int t = 0; t < cycles; ++t) {
        // Drive Inputs
        // top->a_in_0 = a_in[t]; ...

        // Tick
        // top->clk = 1; top->eval();
        // top->clk = 0; top->eval();

        // Read
        // c_out[t] = top->c_out_0_0;
    }

    // delete top;
}

}

int main(int argc, char** argv) {
    // Standalone test
    return 0;
}
