-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date        : Fri Jan 15 09:35:24 2016
-- Host        : cimepe30 running 64-bit Debian GNU/Linux 7.2 (wheezy)
-- Command     : write_vhdl -force -mode funcsim /tima/payet/VC707_IPs/PCIeGen1x8If64/PCIeGen1x8If64_funcsim.vhdl
-- Design      : PCIeGen1x8If64
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7vx485tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_null_gen is
  port (
    null_mux_sel_reg : out STD_LOGIC;
    trn_rdst_rdy_xhdl4_reg : out STD_LOGIC;
    \m_axis_rx_tuser_xhdl1_reg[21]\ : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 3 downto 0 );
    reg_tlast_reg : out STD_LOGIC;
    \m_axis_rx_tuser_xhdl1_reg[19]\ : out STD_LOGIC;
    in0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \m_axis_rx_tdata_xhdl0_reg[30]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    user_reset_out_reg : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    user_reset_out_reg_0 : in STD_LOGIC;
    null_mux_sel_reg_0 : in STD_LOGIC;
    null_mux_sel : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    data_prev_reg : in STD_LOGIC;
    \trn_rrem_prev_reg[0]\ : in STD_LOGIC;
    data_prev_reg_0 : in STD_LOGIC;
    m_axis_rx_tvalid_xhdl2_reg : in STD_LOGIC;
    m_axis_rx_tuser : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_null_gen : entity is "PCIeGen1x8If64_axi_basic_rx_null_gen";
end PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_null_gen;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_null_gen is
  signal cur_state : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[19]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[19]_i_3_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[21]_i_4_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[21]_i_5_n_0\ : STD_LOGIC;
  signal new_pkt_len : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of new_pkt_len : signal is "true";
  signal new_pkt_len_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP of new_pkt_len_1 : signal is "true";
  signal next_state : STD_LOGIC;
  signal null_mux_sel_i_2_n_0 : STD_LOGIC;
  signal pkt_len_counter : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal reg_pkt_len_counter : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \reg_pkt_len_counter[10]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[10]_i_2_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[10]_i_3_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[10]_i_4_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_2_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_4_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_5_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_6_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_7_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[2]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[3]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[4]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[4]_i_3_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[4]_i_4_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[4]_i_5_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[4]_i_6_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[4]_i_7_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[5]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[6]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[7]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[8]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[8]_i_3_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[8]_i_4_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[8]_i_5_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[8]_i_6_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[9]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[11]_i_3_n_1\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[11]_i_3_n_2\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[11]_i_3_n_3\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[11]_i_3_n_4\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[11]_i_3_n_5\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[11]_i_3_n_6\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[11]_i_3_n_7\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[4]_i_2_n_1\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[4]_i_2_n_2\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[4]_i_2_n_3\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[4]_i_2_n_4\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[4]_i_2_n_5\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[4]_i_2_n_6\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[4]_i_2_n_7\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[8]_i_2_n_4\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[8]_i_2_n_5\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[8]_i_2_n_6\ : STD_LOGIC;
  signal \reg_pkt_len_counter_reg[8]_i_2_n_7\ : STD_LOGIC;
  signal \reg_tkeep[4]_i_2_n_0\ : STD_LOGIC;
  signal \reg_tkeep[5]_i_2_n_0\ : STD_LOGIC;
  signal \reg_tkeep[6]_i_2_n_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_3_n_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_4_n_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_5_n_0\ : STD_LOGIC;
  signal reg_tlast_i_3_n_0 : STD_LOGIC;
  signal reg_tlast_i_4_n_0 : STD_LOGIC;
  signal reg_tlast_i_5_n_0 : STD_LOGIC;
  signal reg_tlast_i_6_n_0 : STD_LOGIC;
  signal trn_rdst_rdy_xhdl4_i_3_n_0 : STD_LOGIC;
  signal \NLW_reg_pkt_len_counter_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \m_axis_rx_tuser_xhdl1[21]_i_2\ : label is "soft_lutpair218";
  attribute SOFT_HLUTNM of null_mux_sel_i_2 : label is "soft_lutpair219";
  attribute SOFT_HLUTNM of \reg_tkeep[4]_i_1\ : label is "soft_lutpair216";
  attribute SOFT_HLUTNM of \reg_tkeep[5]_i_1\ : label is "soft_lutpair217";
  attribute SOFT_HLUTNM of \reg_tkeep[6]_i_1\ : label is "soft_lutpair216";
  attribute SOFT_HLUTNM of \reg_tkeep[7]_i_1\ : label is "soft_lutpair217";
  attribute SOFT_HLUTNM of reg_tlast_i_1 : label is "soft_lutpair218";
  attribute SOFT_HLUTNM of trn_rdst_rdy_xhdl4_i_3 : label is "soft_lutpair219";
begin
  new_pkt_len(9 downto 5) <= \m_axis_rx_tdata_xhdl0_reg[30]\(4 downto 0);
  new_pkt_len_1(4 downto 0) <= in0(4 downto 0);
cur_state_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"555D5555"
    )
        port map (
      I0 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I1 => m_axis_rx_tvalid_xhdl2_reg,
      I2 => cur_state,
      I3 => m_axis_rx_tuser(0),
      I4 => m_axis_rx_tready,
      O => next_state
    );
cur_state_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => next_state,
      Q => cur_state,
      R => user_reset_out_reg
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => new_pkt_len_1(4),
      O => new_pkt_len(4)
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => new_pkt_len_1(3),
      O => new_pkt_len(3)
    );
i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => new_pkt_len_1(2),
      O => new_pkt_len(2)
    );
i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => new_pkt_len_1(1),
      O => new_pkt_len(1)
    );
i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => new_pkt_len_1(0),
      O => new_pkt_len(0)
    );
i_5: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => new_pkt_len(11)
    );
i_6: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => new_pkt_len(10)
    );
\m_axis_rx_tuser_xhdl1[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000FFFF10000000"
    )
        port map (
      I0 => reg_tlast_i_6_n_0,
      I1 => \reg_tkeep[7]_i_5_n_0\,
      I2 => \m_axis_rx_tuser_xhdl1[19]_i_2_n_0\,
      I3 => \m_axis_rx_tuser_xhdl1[19]_i_3_n_0\,
      I4 => null_mux_sel,
      I5 => \trn_rrem_prev_reg[0]\,
      O => \m_axis_rx_tuser_xhdl1_reg[19]\
    );
\m_axis_rx_tuser_xhdl1[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000047034400"
    )
        port map (
      I0 => new_pkt_len(0),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => reg_pkt_len_counter(0),
      I3 => new_pkt_len(1),
      I4 => \reg_pkt_len_counter_reg[4]_i_2_n_7\,
      I5 => \reg_pkt_len_counter[3]_i_1_n_0\,
      O => \m_axis_rx_tuser_xhdl1[19]_i_2_n_0\
    );
\m_axis_rx_tuser_xhdl1[19]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000010101"
    )
        port map (
      I0 => \reg_pkt_len_counter[4]_i_1_n_0\,
      I1 => \reg_pkt_len_counter[2]_i_1_n_0\,
      I2 => \reg_pkt_len_counter[5]_i_1_n_0\,
      I3 => new_pkt_len(6),
      I4 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I5 => \reg_pkt_len_counter_reg[8]_i_2_n_6\,
      O => \m_axis_rx_tuser_xhdl1[19]_i_3_n_0\
    );
\m_axis_rx_tuser_xhdl1[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAEAAAAAAAA"
    )
        port map (
      I0 => data_prev_reg,
      I1 => \m_axis_rx_tuser_xhdl1[21]_i_4_n_0\,
      I2 => \reg_tkeep[7]_i_5_n_0\,
      I3 => reg_tlast_i_5_n_0,
      I4 => reg_tlast_i_6_n_0,
      I5 => \m_axis_rx_tuser_xhdl1[21]_i_5_n_0\,
      O => \m_axis_rx_tuser_xhdl1_reg[21]\
    );
\m_axis_rx_tuser_xhdl1[21]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000003050500030"
    )
        port map (
      I0 => new_pkt_len(2),
      I1 => \reg_pkt_len_counter_reg[4]_i_2_n_6\,
      I2 => null_mux_sel,
      I3 => \reg_pkt_len_counter_reg[4]_i_2_n_4\,
      I4 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I5 => new_pkt_len(4),
      O => \m_axis_rx_tuser_xhdl1[21]_i_4_n_0\
    );
\m_axis_rx_tuser_xhdl1[21]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000478B74B8"
    )
        port map (
      I0 => new_pkt_len(1),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => \reg_pkt_len_counter_reg[4]_i_2_n_7\,
      I3 => new_pkt_len(0),
      I4 => reg_pkt_len_counter(0),
      I5 => \reg_pkt_len_counter[3]_i_1_n_0\,
      O => \m_axis_rx_tuser_xhdl1[21]_i_5_n_0\
    );
null_mux_sel_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFFE"
    )
        port map (
      I0 => reg_tlast_i_4_n_0,
      I1 => reg_tlast_i_5_n_0,
      I2 => reg_tlast_i_6_n_0,
      I3 => \reg_tkeep[7]_i_5_n_0\,
      I4 => null_mux_sel_i_2_n_0,
      I5 => user_reset_out_reg_0,
      O => null_mux_sel_reg
    );
null_mux_sel_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF7"
    )
        port map (
      I0 => null_mux_sel,
      I1 => m_axis_rx_tready,
      I2 => \reg_pkt_len_counter[4]_i_1_n_0\,
      I3 => \reg_pkt_len_counter[3]_i_1_n_0\,
      I4 => \reg_pkt_len_counter[2]_i_1_n_0\,
      O => null_mux_sel_i_2_n_0
    );
\reg_pkt_len_counter[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => new_pkt_len(0),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => reg_pkt_len_counter(0),
      O => pkt_len_counter(0)
    );
\reg_pkt_len_counter[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFAAAA8000AAAA"
    )
        port map (
      I0 => new_pkt_len(10),
      I1 => \reg_pkt_len_counter[10]_i_2_n_0\,
      I2 => \reg_pkt_len_counter[10]_i_3_n_0\,
      I3 => \reg_pkt_len_counter[10]_i_4_n_0\,
      I4 => cur_state,
      I5 => \reg_pkt_len_counter_reg[11]_i_3_n_6\,
      O => \reg_pkt_len_counter[10]_i_1_n_0\
    );
\reg_pkt_len_counter[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => reg_pkt_len_counter(9),
      I1 => reg_pkt_len_counter(6),
      I2 => reg_pkt_len_counter(11),
      I3 => reg_pkt_len_counter(5),
      I4 => reg_pkt_len_counter(10),
      O => \reg_pkt_len_counter[10]_i_2_n_0\
    );
\reg_pkt_len_counter[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => reg_pkt_len_counter(3),
      I1 => reg_pkt_len_counter(2),
      I2 => m_axis_rx_tready,
      I3 => reg_pkt_len_counter(7),
      I4 => reg_pkt_len_counter(4),
      I5 => reg_pkt_len_counter(8),
      O => \reg_pkt_len_counter[10]_i_3_n_0\
    );
\reg_pkt_len_counter[10]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => reg_pkt_len_counter(1),
      I1 => reg_pkt_len_counter(0),
      O => \reg_pkt_len_counter[10]_i_4_n_0\
    );
\reg_pkt_len_counter[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => new_pkt_len(11),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => \reg_pkt_len_counter_reg[11]_i_3_n_5\,
      O => \reg_pkt_len_counter[11]_i_1_n_0\
    );
\reg_pkt_len_counter[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0888FFFF"
    )
        port map (
      I0 => \reg_pkt_len_counter[10]_i_2_n_0\,
      I1 => \reg_pkt_len_counter[10]_i_3_n_0\,
      I2 => reg_pkt_len_counter(1),
      I3 => reg_pkt_len_counter(0),
      I4 => cur_state,
      O => \reg_pkt_len_counter[11]_i_2_n_0\
    );
\reg_pkt_len_counter[11]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => reg_pkt_len_counter(11),
      O => \reg_pkt_len_counter[11]_i_4_n_0\
    );
\reg_pkt_len_counter[11]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(10),
      I1 => reg_pkt_len_counter(11),
      O => \reg_pkt_len_counter[11]_i_5_n_0\
    );
\reg_pkt_len_counter[11]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(9),
      I1 => reg_pkt_len_counter(10),
      O => \reg_pkt_len_counter[11]_i_6_n_0\
    );
\reg_pkt_len_counter[11]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(8),
      I1 => reg_pkt_len_counter(9),
      O => \reg_pkt_len_counter[11]_i_7_n_0\
    );
\reg_pkt_len_counter[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFAAAA8000AAAA"
    )
        port map (
      I0 => new_pkt_len(1),
      I1 => \reg_pkt_len_counter[10]_i_2_n_0\,
      I2 => \reg_pkt_len_counter[10]_i_3_n_0\,
      I3 => \reg_pkt_len_counter[10]_i_4_n_0\,
      I4 => cur_state,
      I5 => \reg_pkt_len_counter_reg[4]_i_2_n_7\,
      O => pkt_len_counter(1)
    );
\reg_pkt_len_counter[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFAAAA8000AAAA"
    )
        port map (
      I0 => new_pkt_len(2),
      I1 => \reg_pkt_len_counter[10]_i_2_n_0\,
      I2 => \reg_pkt_len_counter[10]_i_3_n_0\,
      I3 => \reg_pkt_len_counter[10]_i_4_n_0\,
      I4 => cur_state,
      I5 => \reg_pkt_len_counter_reg[4]_i_2_n_6\,
      O => \reg_pkt_len_counter[2]_i_1_n_0\
    );
\reg_pkt_len_counter[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFAAAA8000AAAA"
    )
        port map (
      I0 => new_pkt_len(3),
      I1 => \reg_pkt_len_counter[10]_i_2_n_0\,
      I2 => \reg_pkt_len_counter[10]_i_3_n_0\,
      I3 => \reg_pkt_len_counter[10]_i_4_n_0\,
      I4 => cur_state,
      I5 => \reg_pkt_len_counter_reg[4]_i_2_n_5\,
      O => \reg_pkt_len_counter[3]_i_1_n_0\
    );
\reg_pkt_len_counter[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFAAAA8000AAAA"
    )
        port map (
      I0 => new_pkt_len(4),
      I1 => \reg_pkt_len_counter[10]_i_2_n_0\,
      I2 => \reg_pkt_len_counter[10]_i_3_n_0\,
      I3 => \reg_pkt_len_counter[10]_i_4_n_0\,
      I4 => cur_state,
      I5 => \reg_pkt_len_counter_reg[4]_i_2_n_4\,
      O => \reg_pkt_len_counter[4]_i_1_n_0\
    );
\reg_pkt_len_counter[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reg_pkt_len_counter(1),
      I1 => m_axis_rx_tready,
      O => \reg_pkt_len_counter[4]_i_3_n_0\
    );
\reg_pkt_len_counter[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(3),
      I1 => reg_pkt_len_counter(4),
      O => \reg_pkt_len_counter[4]_i_4_n_0\
    );
\reg_pkt_len_counter[4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(2),
      I1 => reg_pkt_len_counter(3),
      O => \reg_pkt_len_counter[4]_i_5_n_0\
    );
\reg_pkt_len_counter[4]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => m_axis_rx_tready,
      I1 => reg_pkt_len_counter(1),
      I2 => reg_pkt_len_counter(2),
      O => \reg_pkt_len_counter[4]_i_6_n_0\
    );
\reg_pkt_len_counter[4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => m_axis_rx_tready,
      I1 => reg_pkt_len_counter(1),
      O => \reg_pkt_len_counter[4]_i_7_n_0\
    );
\reg_pkt_len_counter[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFAAAA8000AAAA"
    )
        port map (
      I0 => new_pkt_len(5),
      I1 => \reg_pkt_len_counter[10]_i_2_n_0\,
      I2 => \reg_pkt_len_counter[10]_i_3_n_0\,
      I3 => \reg_pkt_len_counter[10]_i_4_n_0\,
      I4 => cur_state,
      I5 => \reg_pkt_len_counter_reg[8]_i_2_n_7\,
      O => \reg_pkt_len_counter[5]_i_1_n_0\
    );
\reg_pkt_len_counter[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFAAAA8000AAAA"
    )
        port map (
      I0 => new_pkt_len(6),
      I1 => \reg_pkt_len_counter[10]_i_2_n_0\,
      I2 => \reg_pkt_len_counter[10]_i_3_n_0\,
      I3 => \reg_pkt_len_counter[10]_i_4_n_0\,
      I4 => cur_state,
      I5 => \reg_pkt_len_counter_reg[8]_i_2_n_6\,
      O => \reg_pkt_len_counter[6]_i_1_n_0\
    );
\reg_pkt_len_counter[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => new_pkt_len(7),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => \reg_pkt_len_counter_reg[8]_i_2_n_5\,
      O => \reg_pkt_len_counter[7]_i_1_n_0\
    );
\reg_pkt_len_counter[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFAAAA8000AAAA"
    )
        port map (
      I0 => new_pkt_len(8),
      I1 => \reg_pkt_len_counter[10]_i_2_n_0\,
      I2 => \reg_pkt_len_counter[10]_i_3_n_0\,
      I3 => \reg_pkt_len_counter[10]_i_4_n_0\,
      I4 => cur_state,
      I5 => \reg_pkt_len_counter_reg[8]_i_2_n_4\,
      O => \reg_pkt_len_counter[8]_i_1_n_0\
    );
\reg_pkt_len_counter[8]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(7),
      I1 => reg_pkt_len_counter(8),
      O => \reg_pkt_len_counter[8]_i_3_n_0\
    );
\reg_pkt_len_counter[8]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(6),
      I1 => reg_pkt_len_counter(7),
      O => \reg_pkt_len_counter[8]_i_4_n_0\
    );
\reg_pkt_len_counter[8]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(5),
      I1 => reg_pkt_len_counter(6),
      O => \reg_pkt_len_counter[8]_i_5_n_0\
    );
\reg_pkt_len_counter[8]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(4),
      I1 => reg_pkt_len_counter(5),
      O => \reg_pkt_len_counter[8]_i_6_n_0\
    );
\reg_pkt_len_counter[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFAAAA8000AAAA"
    )
        port map (
      I0 => new_pkt_len(9),
      I1 => \reg_pkt_len_counter[10]_i_2_n_0\,
      I2 => \reg_pkt_len_counter[10]_i_3_n_0\,
      I3 => \reg_pkt_len_counter[10]_i_4_n_0\,
      I4 => cur_state,
      I5 => \reg_pkt_len_counter_reg[11]_i_3_n_7\,
      O => \reg_pkt_len_counter[9]_i_1_n_0\
    );
\reg_pkt_len_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => pkt_len_counter(0),
      Q => reg_pkt_len_counter(0),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter[10]_i_1_n_0\,
      Q => reg_pkt_len_counter(10),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter[11]_i_1_n_0\,
      Q => reg_pkt_len_counter(11),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[11]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \reg_pkt_len_counter_reg[8]_i_2_n_0\,
      CO(3) => \NLW_reg_pkt_len_counter_reg[11]_i_3_CO_UNCONNECTED\(3),
      CO(2) => \reg_pkt_len_counter_reg[11]_i_3_n_1\,
      CO(1) => \reg_pkt_len_counter_reg[11]_i_3_n_2\,
      CO(0) => \reg_pkt_len_counter_reg[11]_i_3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2 downto 0) => reg_pkt_len_counter(10 downto 8),
      O(3) => \reg_pkt_len_counter_reg[11]_i_3_n_4\,
      O(2) => \reg_pkt_len_counter_reg[11]_i_3_n_5\,
      O(1) => \reg_pkt_len_counter_reg[11]_i_3_n_6\,
      O(0) => \reg_pkt_len_counter_reg[11]_i_3_n_7\,
      S(3) => \reg_pkt_len_counter[11]_i_4_n_0\,
      S(2) => \reg_pkt_len_counter[11]_i_5_n_0\,
      S(1) => \reg_pkt_len_counter[11]_i_6_n_0\,
      S(0) => \reg_pkt_len_counter[11]_i_7_n_0\
    );
\reg_pkt_len_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => pkt_len_counter(1),
      Q => reg_pkt_len_counter(1),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter[2]_i_1_n_0\,
      Q => reg_pkt_len_counter(2),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter[3]_i_1_n_0\,
      Q => reg_pkt_len_counter(3),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter[4]_i_1_n_0\,
      Q => reg_pkt_len_counter(4),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[4]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \reg_pkt_len_counter_reg[4]_i_2_n_0\,
      CO(2) => \reg_pkt_len_counter_reg[4]_i_2_n_1\,
      CO(1) => \reg_pkt_len_counter_reg[4]_i_2_n_2\,
      CO(0) => \reg_pkt_len_counter_reg[4]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => reg_pkt_len_counter(3 downto 2),
      DI(1) => \reg_pkt_len_counter[4]_i_3_n_0\,
      DI(0) => '0',
      O(3) => \reg_pkt_len_counter_reg[4]_i_2_n_4\,
      O(2) => \reg_pkt_len_counter_reg[4]_i_2_n_5\,
      O(1) => \reg_pkt_len_counter_reg[4]_i_2_n_6\,
      O(0) => \reg_pkt_len_counter_reg[4]_i_2_n_7\,
      S(3) => \reg_pkt_len_counter[4]_i_4_n_0\,
      S(2) => \reg_pkt_len_counter[4]_i_5_n_0\,
      S(1) => \reg_pkt_len_counter[4]_i_6_n_0\,
      S(0) => \reg_pkt_len_counter[4]_i_7_n_0\
    );
\reg_pkt_len_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter[5]_i_1_n_0\,
      Q => reg_pkt_len_counter(5),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter[6]_i_1_n_0\,
      Q => reg_pkt_len_counter(6),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter[7]_i_1_n_0\,
      Q => reg_pkt_len_counter(7),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter[8]_i_1_n_0\,
      Q => reg_pkt_len_counter(8),
      R => user_reset_out_reg
    );
\reg_pkt_len_counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \reg_pkt_len_counter_reg[4]_i_2_n_0\,
      CO(3) => \reg_pkt_len_counter_reg[8]_i_2_n_0\,
      CO(2) => \reg_pkt_len_counter_reg[8]_i_2_n_1\,
      CO(1) => \reg_pkt_len_counter_reg[8]_i_2_n_2\,
      CO(0) => \reg_pkt_len_counter_reg[8]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => reg_pkt_len_counter(7 downto 4),
      O(3) => \reg_pkt_len_counter_reg[8]_i_2_n_4\,
      O(2) => \reg_pkt_len_counter_reg[8]_i_2_n_5\,
      O(1) => \reg_pkt_len_counter_reg[8]_i_2_n_6\,
      O(0) => \reg_pkt_len_counter_reg[8]_i_2_n_7\,
      S(3) => \reg_pkt_len_counter[8]_i_3_n_0\,
      S(2) => \reg_pkt_len_counter[8]_i_4_n_0\,
      S(1) => \reg_pkt_len_counter[8]_i_5_n_0\,
      S(0) => \reg_pkt_len_counter[8]_i_6_n_0\
    );
\reg_pkt_len_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter[9]_i_1_n_0\,
      Q => reg_pkt_len_counter(9),
      R => user_reset_out_reg
    );
\reg_tkeep[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAFFAAFFAAFCAA"
    )
        port map (
      I0 => \trn_rrem_prev_reg[0]\,
      I1 => \reg_tkeep[7]_i_3_n_0\,
      I2 => \reg_tkeep[4]_i_2_n_0\,
      I3 => null_mux_sel,
      I4 => \reg_pkt_len_counter[4]_i_1_n_0\,
      I5 => \reg_tkeep[7]_i_5_n_0\,
      O => D(0)
    );
\reg_tkeep[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \reg_pkt_len_counter_reg[4]_i_2_n_6\,
      I1 => new_pkt_len(2),
      I2 => \reg_pkt_len_counter_reg[4]_i_2_n_5\,
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => new_pkt_len(3),
      O => \reg_tkeep[4]_i_2_n_0\
    );
\reg_tkeep[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAFFAAFFAAFCAA"
    )
        port map (
      I0 => \trn_rrem_prev_reg[0]\,
      I1 => \reg_tkeep[7]_i_3_n_0\,
      I2 => \reg_tkeep[5]_i_2_n_0\,
      I3 => null_mux_sel,
      I4 => \reg_pkt_len_counter[4]_i_1_n_0\,
      I5 => \reg_tkeep[7]_i_5_n_0\,
      O => D(1)
    );
\reg_tkeep[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \reg_pkt_len_counter_reg[4]_i_2_n_6\,
      I1 => new_pkt_len(2),
      I2 => \reg_pkt_len_counter_reg[4]_i_2_n_5\,
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => new_pkt_len(3),
      O => \reg_tkeep[5]_i_2_n_0\
    );
\reg_tkeep[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAFFAAFFAAFCAA"
    )
        port map (
      I0 => \trn_rrem_prev_reg[0]\,
      I1 => \reg_tkeep[7]_i_3_n_0\,
      I2 => \reg_tkeep[6]_i_2_n_0\,
      I3 => null_mux_sel,
      I4 => \reg_pkt_len_counter[4]_i_1_n_0\,
      I5 => \reg_tkeep[7]_i_5_n_0\,
      O => D(2)
    );
\reg_tkeep[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \reg_pkt_len_counter_reg[4]_i_2_n_6\,
      I1 => new_pkt_len(2),
      I2 => \reg_pkt_len_counter_reg[4]_i_2_n_5\,
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => new_pkt_len(3),
      O => \reg_tkeep[6]_i_2_n_0\
    );
\reg_tkeep[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAFFAAFFAAFCAA"
    )
        port map (
      I0 => \trn_rrem_prev_reg[0]\,
      I1 => \reg_tkeep[7]_i_3_n_0\,
      I2 => \reg_tkeep[7]_i_4_n_0\,
      I3 => null_mux_sel,
      I4 => \reg_pkt_len_counter[4]_i_1_n_0\,
      I5 => \reg_tkeep[7]_i_5_n_0\,
      O => D(3)
    );
\reg_tkeep[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \reg_pkt_len_counter[10]_i_1_n_0\,
      I1 => \reg_pkt_len_counter[8]_i_1_n_0\,
      I2 => pkt_len_counter(1),
      I3 => \reg_pkt_len_counter[6]_i_1_n_0\,
      I4 => \reg_pkt_len_counter[5]_i_1_n_0\,
      O => \reg_tkeep[7]_i_3_n_0\
    );
\reg_tkeep[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \reg_pkt_len_counter_reg[4]_i_2_n_6\,
      I1 => new_pkt_len(2),
      I2 => \reg_pkt_len_counter_reg[4]_i_2_n_5\,
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => new_pkt_len(3),
      O => \reg_tkeep[7]_i_4_n_0\
    );
\reg_tkeep[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFCFFFFFFFCFAFA"
    )
        port map (
      I0 => \reg_pkt_len_counter_reg[8]_i_2_n_5\,
      I1 => new_pkt_len(7),
      I2 => \reg_pkt_len_counter[9]_i_1_n_0\,
      I3 => new_pkt_len(11),
      I4 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I5 => \reg_pkt_len_counter_reg[11]_i_3_n_5\,
      O => \reg_tkeep[7]_i_5_n_0\
    );
reg_tlast_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAAB"
    )
        port map (
      I0 => data_prev_reg_0,
      I1 => \reg_tkeep[7]_i_5_n_0\,
      I2 => reg_tlast_i_3_n_0,
      I3 => reg_tlast_i_4_n_0,
      I4 => reg_tlast_i_5_n_0,
      I5 => reg_tlast_i_6_n_0,
      O => reg_tlast_reg
    );
reg_tlast_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFDFD5"
    )
        port map (
      I0 => null_mux_sel,
      I1 => new_pkt_len(4),
      I2 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I3 => \reg_pkt_len_counter_reg[4]_i_2_n_4\,
      I4 => \reg_pkt_len_counter[3]_i_1_n_0\,
      I5 => \reg_pkt_len_counter[2]_i_1_n_0\,
      O => reg_tlast_i_3_n_0
    );
reg_tlast_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCA000A0"
    )
        port map (
      I0 => reg_pkt_len_counter(0),
      I1 => new_pkt_len(0),
      I2 => \reg_pkt_len_counter_reg[4]_i_2_n_7\,
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => new_pkt_len(1),
      O => reg_tlast_i_4_n_0
    );
reg_tlast_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \reg_pkt_len_counter_reg[8]_i_2_n_6\,
      I1 => new_pkt_len(6),
      I2 => \reg_pkt_len_counter_reg[8]_i_2_n_7\,
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => new_pkt_len(5),
      O => reg_tlast_i_5_n_0
    );
reg_tlast_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => \reg_pkt_len_counter_reg[8]_i_2_n_4\,
      I1 => new_pkt_len(8),
      I2 => \reg_pkt_len_counter_reg[11]_i_3_n_6\,
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => new_pkt_len(10),
      O => reg_tlast_i_6_n_0
    );
trn_rdst_rdy_xhdl4_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAAB"
    )
        port map (
      I0 => null_mux_sel_reg_0,
      I1 => \reg_tkeep[7]_i_5_n_0\,
      I2 => trn_rdst_rdy_xhdl4_i_3_n_0,
      I3 => reg_tlast_i_4_n_0,
      I4 => reg_tlast_i_5_n_0,
      I5 => reg_tlast_i_6_n_0,
      O => trn_rdst_rdy_xhdl4_reg
    );
trn_rdst_rdy_xhdl4_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFF7"
    )
        port map (
      I0 => null_mux_sel,
      I1 => m_axis_rx_tready,
      I2 => \reg_pkt_len_counter[4]_i_1_n_0\,
      I3 => \reg_pkt_len_counter[3]_i_1_n_0\,
      I4 => \reg_pkt_len_counter[2]_i_1_n_0\,
      O => trn_rdst_rdy_xhdl4_i_3_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_pipeline is
  port (
    null_mux_sel : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tvalid : out STD_LOGIC;
    m_axis_rx_tlast : out STD_LOGIC;
    trn_in_packet_reg_0 : out STD_LOGIC;
    null_mux_sel_reg_0 : out STD_LOGIC;
    trn_rdst_rdy_xhdl4_reg_0 : out STD_LOGIC;
    \m_axis_rx_tuser_xhdl1_reg[21]_0\ : out STD_LOGIC;
    reg_tlast_reg_0 : out STD_LOGIC;
    \m_axis_rx_tuser_xhdl1_reg[19]_0\ : out STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    \reg_pkt_len_counter_reg[9]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
    user_reset_out_reg : in STD_LOGIC;
    trn_rsrc_dsc : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    \reg_pkt_len_counter_reg[0]\ : in STD_LOGIC;
    null_mux_sel_reg_1 : in STD_LOGIC;
    rsrc_rdy_filtered10_out : in STD_LOGIC;
    trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 );
    trn_reof : in STD_LOGIC;
    data_prev_reg_0 : in STD_LOGIC;
    trn_rsof : in STD_LOGIC;
    trn_recrc_err : in STD_LOGIC;
    trn_rerrfwd : in STD_LOGIC;
    user_reset_out_reg_0 : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    trn_rdst_rdy_xhdl4_reg_1 : in STD_LOGIC;
    trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 );
    trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 );
    D : in STD_LOGIC_VECTOR ( 3 downto 0 );
    data_prev_reg_1 : in STD_LOGIC;
    null_mux_sel_reg_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_pipeline : entity is "PCIeGen1x8If64_axi_basic_rx_pipeline";
end PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_pipeline;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_pipeline is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal data_hold : STD_LOGIC;
  signal data_prev : STD_LOGIC;
  signal is_eof_prev : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \^m_axis_rx_tdata\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[0]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[14]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[1]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[2]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[3]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[4]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[5]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[6]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[7]_i_1_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[8]_i_1_n_0\ : STD_LOGIC;
  signal \^m_axis_rx_tvalid\ : STD_LOGIC;
  signal m_axis_rx_tvalid_xhdl2_i_1_n_0 : STD_LOGIC;
  signal m_axis_rx_tvalid_xhdl2_i_2_n_0 : STD_LOGIC;
  signal new_pkt_len_1_inferred_i_6_n_0 : STD_LOGIC;
  signal \^null_mux_sel\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal reg_dsc_detect_i_1_n_0 : STD_LOGIC;
  signal reg_dsc_detect_i_3_n_0 : STD_LOGIC;
  signal reg_dsc_detect_reg_n_0 : STD_LOGIC;
  signal \^trn_in_packet_reg_0\ : STD_LOGIC;
  signal trn_rbar_hit_prev : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal trn_rd_prev : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal trn_rdst_rdy_xhdl4_i_4_n_0 : STD_LOGIC;
  signal trn_recrc_err_prev : STD_LOGIC;
  signal trn_rerrfwd_prev : STD_LOGIC;
  signal trn_rsof_prev : STD_LOGIC;
  signal trn_rsrc_dsc_d : STD_LOGIC;
  signal trn_rsrc_dsc_prev : STD_LOGIC;
  signal trn_rsrc_dsc_prev0 : STD_LOGIC;
  signal trn_rsrc_rdy_prev : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \m_axis_rx_tuser_xhdl1[21]_i_3\ : label is "soft_lutpair221";
  attribute SOFT_HLUTNM of new_pkt_len_1_inferred_i_1 : label is "soft_lutpair222";
  attribute SOFT_HLUTNM of new_pkt_len_1_inferred_i_2 : label is "soft_lutpair222";
  attribute SOFT_HLUTNM of new_pkt_len_1_inferred_i_4 : label is "soft_lutpair220";
  attribute SOFT_HLUTNM of new_pkt_len_1_inferred_i_5 : label is "soft_lutpair220";
  attribute SOFT_HLUTNM of reg_tlast_i_2 : label is "soft_lutpair221";
begin
  E(0) <= \^e\(0);
  m_axis_rx_tdata(63 downto 0) <= \^m_axis_rx_tdata\(63 downto 0);
  m_axis_rx_tvalid <= \^m_axis_rx_tvalid\;
  null_mux_sel <= \^null_mux_sel\;
  trn_in_packet_reg_0 <= \^trn_in_packet_reg_0\;
data_prev_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^m_axis_rx_tvalid\,
      I1 => m_axis_rx_tready,
      O => data_hold
    );
data_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => data_hold,
      Q => data_prev,
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(0),
      I1 => data_prev,
      I2 => trn_rd(32),
      O => p_1_in(0)
    );
\m_axis_rx_tdata_xhdl0[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(10),
      I1 => data_prev,
      I2 => trn_rd(42),
      O => p_1_in(10)
    );
\m_axis_rx_tdata_xhdl0[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(11),
      I1 => data_prev,
      I2 => trn_rd(43),
      O => p_1_in(11)
    );
\m_axis_rx_tdata_xhdl0[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(12),
      I1 => data_prev,
      I2 => trn_rd(44),
      O => p_1_in(12)
    );
\m_axis_rx_tdata_xhdl0[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(13),
      I1 => data_prev,
      I2 => trn_rd(45),
      O => p_1_in(13)
    );
\m_axis_rx_tdata_xhdl0[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(14),
      I1 => data_prev,
      I2 => trn_rd(46),
      O => p_1_in(14)
    );
\m_axis_rx_tdata_xhdl0[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(15),
      I1 => data_prev,
      I2 => trn_rd(47),
      O => p_1_in(15)
    );
\m_axis_rx_tdata_xhdl0[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(16),
      I1 => data_prev,
      I2 => trn_rd(48),
      O => p_1_in(16)
    );
\m_axis_rx_tdata_xhdl0[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(17),
      I1 => data_prev,
      I2 => trn_rd(49),
      O => p_1_in(17)
    );
\m_axis_rx_tdata_xhdl0[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(18),
      I1 => data_prev,
      I2 => trn_rd(50),
      O => p_1_in(18)
    );
\m_axis_rx_tdata_xhdl0[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(19),
      I1 => data_prev,
      I2 => trn_rd(51),
      O => p_1_in(19)
    );
\m_axis_rx_tdata_xhdl0[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(1),
      I1 => data_prev,
      I2 => trn_rd(33),
      O => p_1_in(1)
    );
\m_axis_rx_tdata_xhdl0[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(20),
      I1 => data_prev,
      I2 => trn_rd(52),
      O => p_1_in(20)
    );
\m_axis_rx_tdata_xhdl0[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(21),
      I1 => data_prev,
      I2 => trn_rd(53),
      O => p_1_in(21)
    );
\m_axis_rx_tdata_xhdl0[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(22),
      I1 => data_prev,
      I2 => trn_rd(54),
      O => p_1_in(22)
    );
\m_axis_rx_tdata_xhdl0[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(23),
      I1 => data_prev,
      I2 => trn_rd(55),
      O => p_1_in(23)
    );
\m_axis_rx_tdata_xhdl0[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(24),
      I1 => data_prev,
      I2 => trn_rd(56),
      O => p_1_in(24)
    );
\m_axis_rx_tdata_xhdl0[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(25),
      I1 => data_prev,
      I2 => trn_rd(57),
      O => p_1_in(25)
    );
\m_axis_rx_tdata_xhdl0[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(26),
      I1 => data_prev,
      I2 => trn_rd(58),
      O => p_1_in(26)
    );
\m_axis_rx_tdata_xhdl0[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(27),
      I1 => data_prev,
      I2 => trn_rd(59),
      O => p_1_in(27)
    );
\m_axis_rx_tdata_xhdl0[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(28),
      I1 => data_prev,
      I2 => trn_rd(60),
      O => p_1_in(28)
    );
\m_axis_rx_tdata_xhdl0[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(29),
      I1 => data_prev,
      I2 => trn_rd(61),
      O => p_1_in(29)
    );
\m_axis_rx_tdata_xhdl0[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(2),
      I1 => data_prev,
      I2 => trn_rd(34),
      O => p_1_in(2)
    );
\m_axis_rx_tdata_xhdl0[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(30),
      I1 => data_prev,
      I2 => trn_rd(62),
      O => p_1_in(30)
    );
\m_axis_rx_tdata_xhdl0[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(31),
      I1 => data_prev,
      I2 => trn_rd(63),
      O => p_1_in(31)
    );
\m_axis_rx_tdata_xhdl0[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(32),
      I1 => data_prev,
      I2 => trn_rd(0),
      O => p_1_in(32)
    );
\m_axis_rx_tdata_xhdl0[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(33),
      I1 => data_prev,
      I2 => trn_rd(1),
      O => p_1_in(33)
    );
\m_axis_rx_tdata_xhdl0[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(34),
      I1 => data_prev,
      I2 => trn_rd(2),
      O => p_1_in(34)
    );
\m_axis_rx_tdata_xhdl0[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(35),
      I1 => data_prev,
      I2 => trn_rd(3),
      O => p_1_in(35)
    );
\m_axis_rx_tdata_xhdl0[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(36),
      I1 => data_prev,
      I2 => trn_rd(4),
      O => p_1_in(36)
    );
\m_axis_rx_tdata_xhdl0[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(37),
      I1 => data_prev,
      I2 => trn_rd(5),
      O => p_1_in(37)
    );
\m_axis_rx_tdata_xhdl0[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(38),
      I1 => data_prev,
      I2 => trn_rd(6),
      O => p_1_in(38)
    );
\m_axis_rx_tdata_xhdl0[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(39),
      I1 => data_prev,
      I2 => trn_rd(7),
      O => p_1_in(39)
    );
\m_axis_rx_tdata_xhdl0[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(3),
      I1 => data_prev,
      I2 => trn_rd(35),
      O => p_1_in(3)
    );
\m_axis_rx_tdata_xhdl0[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(40),
      I1 => data_prev,
      I2 => trn_rd(8),
      O => p_1_in(40)
    );
\m_axis_rx_tdata_xhdl0[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(41),
      I1 => data_prev,
      I2 => trn_rd(9),
      O => p_1_in(41)
    );
\m_axis_rx_tdata_xhdl0[42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(42),
      I1 => data_prev,
      I2 => trn_rd(10),
      O => p_1_in(42)
    );
\m_axis_rx_tdata_xhdl0[43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(43),
      I1 => data_prev,
      I2 => trn_rd(11),
      O => p_1_in(43)
    );
\m_axis_rx_tdata_xhdl0[44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(44),
      I1 => data_prev,
      I2 => trn_rd(12),
      O => p_1_in(44)
    );
\m_axis_rx_tdata_xhdl0[45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(45),
      I1 => data_prev,
      I2 => trn_rd(13),
      O => p_1_in(45)
    );
\m_axis_rx_tdata_xhdl0[46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(46),
      I1 => data_prev,
      I2 => trn_rd(14),
      O => p_1_in(46)
    );
\m_axis_rx_tdata_xhdl0[47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(47),
      I1 => data_prev,
      I2 => trn_rd(15),
      O => p_1_in(47)
    );
\m_axis_rx_tdata_xhdl0[48]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(48),
      I1 => data_prev,
      I2 => trn_rd(16),
      O => p_1_in(48)
    );
\m_axis_rx_tdata_xhdl0[49]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(49),
      I1 => data_prev,
      I2 => trn_rd(17),
      O => p_1_in(49)
    );
\m_axis_rx_tdata_xhdl0[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(4),
      I1 => data_prev,
      I2 => trn_rd(36),
      O => p_1_in(4)
    );
\m_axis_rx_tdata_xhdl0[50]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(50),
      I1 => data_prev,
      I2 => trn_rd(18),
      O => p_1_in(50)
    );
\m_axis_rx_tdata_xhdl0[51]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(51),
      I1 => data_prev,
      I2 => trn_rd(19),
      O => p_1_in(51)
    );
\m_axis_rx_tdata_xhdl0[52]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(52),
      I1 => data_prev,
      I2 => trn_rd(20),
      O => p_1_in(52)
    );
\m_axis_rx_tdata_xhdl0[53]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(53),
      I1 => data_prev,
      I2 => trn_rd(21),
      O => p_1_in(53)
    );
\m_axis_rx_tdata_xhdl0[54]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(54),
      I1 => data_prev,
      I2 => trn_rd(22),
      O => p_1_in(54)
    );
\m_axis_rx_tdata_xhdl0[55]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(55),
      I1 => data_prev,
      I2 => trn_rd(23),
      O => p_1_in(55)
    );
\m_axis_rx_tdata_xhdl0[56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(56),
      I1 => data_prev,
      I2 => trn_rd(24),
      O => p_1_in(56)
    );
\m_axis_rx_tdata_xhdl0[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(57),
      I1 => data_prev,
      I2 => trn_rd(25),
      O => p_1_in(57)
    );
\m_axis_rx_tdata_xhdl0[58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(58),
      I1 => data_prev,
      I2 => trn_rd(26),
      O => p_1_in(58)
    );
\m_axis_rx_tdata_xhdl0[59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(59),
      I1 => data_prev,
      I2 => trn_rd(27),
      O => p_1_in(59)
    );
\m_axis_rx_tdata_xhdl0[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(5),
      I1 => data_prev,
      I2 => trn_rd(37),
      O => p_1_in(5)
    );
\m_axis_rx_tdata_xhdl0[60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(60),
      I1 => data_prev,
      I2 => trn_rd(28),
      O => p_1_in(60)
    );
\m_axis_rx_tdata_xhdl0[61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(61),
      I1 => data_prev,
      I2 => trn_rd(29),
      O => p_1_in(61)
    );
\m_axis_rx_tdata_xhdl0[62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(62),
      I1 => data_prev,
      I2 => trn_rd(30),
      O => p_1_in(62)
    );
\m_axis_rx_tdata_xhdl0[63]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => m_axis_rx_tready,
      I1 => \^m_axis_rx_tvalid\,
      O => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\
    );
\m_axis_rx_tdata_xhdl0[63]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(63),
      I1 => data_prev,
      I2 => trn_rd(31),
      O => p_1_in(63)
    );
\m_axis_rx_tdata_xhdl0[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(6),
      I1 => data_prev,
      I2 => trn_rd(38),
      O => p_1_in(6)
    );
\m_axis_rx_tdata_xhdl0[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(7),
      I1 => data_prev,
      I2 => trn_rd(39),
      O => p_1_in(7)
    );
\m_axis_rx_tdata_xhdl0[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(8),
      I1 => data_prev,
      I2 => trn_rd(40),
      O => p_1_in(8)
    );
\m_axis_rx_tdata_xhdl0[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(9),
      I1 => data_prev,
      I2 => trn_rd(41),
      O => p_1_in(9)
    );
\m_axis_rx_tdata_xhdl0_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(0),
      Q => \^m_axis_rx_tdata\(0),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(10),
      Q => \^m_axis_rx_tdata\(10),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(11),
      Q => \^m_axis_rx_tdata\(11),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(12),
      Q => \^m_axis_rx_tdata\(12),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(13),
      Q => \^m_axis_rx_tdata\(13),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(14),
      Q => \^m_axis_rx_tdata\(14),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(15),
      Q => \^m_axis_rx_tdata\(15),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(16),
      Q => \^m_axis_rx_tdata\(16),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(17),
      Q => \^m_axis_rx_tdata\(17),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(18),
      Q => \^m_axis_rx_tdata\(18),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(19),
      Q => \^m_axis_rx_tdata\(19),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(1),
      Q => \^m_axis_rx_tdata\(1),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(20),
      Q => \^m_axis_rx_tdata\(20),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(21),
      Q => \^m_axis_rx_tdata\(21),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(22),
      Q => \^m_axis_rx_tdata\(22),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(23),
      Q => \^m_axis_rx_tdata\(23),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(24),
      Q => \^m_axis_rx_tdata\(24),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(25),
      Q => \^m_axis_rx_tdata\(25),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(26),
      Q => \^m_axis_rx_tdata\(26),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(27),
      Q => \^m_axis_rx_tdata\(27),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(28),
      Q => \^m_axis_rx_tdata\(28),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(29),
      Q => \^m_axis_rx_tdata\(29),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(2),
      Q => \^m_axis_rx_tdata\(2),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(30),
      Q => \^m_axis_rx_tdata\(30),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(31),
      Q => \^m_axis_rx_tdata\(31),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(32),
      Q => \^m_axis_rx_tdata\(32),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(33),
      Q => \^m_axis_rx_tdata\(33),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(34),
      Q => \^m_axis_rx_tdata\(34),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(35),
      Q => \^m_axis_rx_tdata\(35),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(36),
      Q => \^m_axis_rx_tdata\(36),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(37),
      Q => \^m_axis_rx_tdata\(37),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(38),
      Q => \^m_axis_rx_tdata\(38),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(39),
      Q => \^m_axis_rx_tdata\(39),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(3),
      Q => \^m_axis_rx_tdata\(3),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(40),
      Q => \^m_axis_rx_tdata\(40),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(41),
      Q => \^m_axis_rx_tdata\(41),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(42),
      Q => \^m_axis_rx_tdata\(42),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(43),
      Q => \^m_axis_rx_tdata\(43),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(44),
      Q => \^m_axis_rx_tdata\(44),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(45),
      Q => \^m_axis_rx_tdata\(45),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(46),
      Q => \^m_axis_rx_tdata\(46),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(47),
      Q => \^m_axis_rx_tdata\(47),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(48),
      Q => \^m_axis_rx_tdata\(48),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(49),
      Q => \^m_axis_rx_tdata\(49),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(4),
      Q => \^m_axis_rx_tdata\(4),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(50),
      Q => \^m_axis_rx_tdata\(50),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(51),
      Q => \^m_axis_rx_tdata\(51),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(52),
      Q => \^m_axis_rx_tdata\(52),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(53),
      Q => \^m_axis_rx_tdata\(53),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(54),
      Q => \^m_axis_rx_tdata\(54),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(55),
      Q => \^m_axis_rx_tdata\(55),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(56),
      Q => \^m_axis_rx_tdata\(56),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(57),
      Q => \^m_axis_rx_tdata\(57),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(58),
      Q => \^m_axis_rx_tdata\(58),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(59),
      Q => \^m_axis_rx_tdata\(59),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(5),
      Q => \^m_axis_rx_tdata\(5),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(60),
      Q => \^m_axis_rx_tdata\(60),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(61),
      Q => \^m_axis_rx_tdata\(61),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(62),
      Q => \^m_axis_rx_tdata\(62),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(63),
      Q => \^m_axis_rx_tdata\(63),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(6),
      Q => \^m_axis_rx_tdata\(6),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(7),
      Q => \^m_axis_rx_tdata\(7),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(8),
      Q => \^m_axis_rx_tdata\(8),
      R => user_reset_out_reg
    );
\m_axis_rx_tdata_xhdl0_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(9),
      Q => \^m_axis_rx_tdata\(9),
      R => user_reset_out_reg
    );
\m_axis_rx_tuser_xhdl1[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_recrc_err_prev,
      I1 => data_prev,
      I2 => trn_recrc_err,
      O => \m_axis_rx_tuser_xhdl1[0]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0F002222"
    )
        port map (
      I0 => trn_rsof,
      I1 => trn_rsrc_dsc,
      I2 => trn_rsrc_dsc_prev,
      I3 => trn_rsof_prev,
      I4 => data_prev,
      O => \m_axis_rx_tuser_xhdl1[14]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rerrfwd_prev,
      I1 => data_prev,
      I2 => trn_rerrfwd,
      O => \m_axis_rx_tuser_xhdl1[1]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFD0"
    )
        port map (
      I0 => \^m_axis_rx_tvalid\,
      I1 => m_axis_rx_tready,
      I2 => \^null_mux_sel\,
      I3 => user_reset_out_reg,
      O => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => user_reset_out_reg,
      I1 => m_axis_rx_tready,
      I2 => \^m_axis_rx_tvalid\,
      O => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[21]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => trn_reof,
      I1 => data_prev,
      I2 => is_eof_prev(4),
      I3 => \^null_mux_sel\,
      O => \m_axis_rx_tuser_xhdl1_reg[21]_0\
    );
\m_axis_rx_tuser_xhdl1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(0),
      I1 => data_prev,
      I2 => trn_rbar_hit(0),
      O => \m_axis_rx_tuser_xhdl1[2]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(1),
      I1 => data_prev,
      I2 => trn_rbar_hit(1),
      O => \m_axis_rx_tuser_xhdl1[3]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(2),
      I1 => data_prev,
      I2 => trn_rbar_hit(2),
      O => \m_axis_rx_tuser_xhdl1[4]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(3),
      I1 => data_prev,
      I2 => trn_rbar_hit(3),
      O => \m_axis_rx_tuser_xhdl1[5]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(4),
      I1 => data_prev,
      I2 => trn_rbar_hit(4),
      O => \m_axis_rx_tuser_xhdl1[6]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(5),
      I1 => data_prev,
      I2 => trn_rbar_hit(5),
      O => \m_axis_rx_tuser_xhdl1[7]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(6),
      I1 => data_prev,
      I2 => trn_rbar_hit(6),
      O => \m_axis_rx_tuser_xhdl1[8]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => \m_axis_rx_tuser_xhdl1[0]_i_1_n_0\,
      Q => m_axis_rx_tuser(0),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => '0',
      Q => m_axis_rx_tuser(10),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => '0',
      Q => m_axis_rx_tuser(11),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => '0',
      Q => m_axis_rx_tuser(12),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => '0',
      Q => m_axis_rx_tuser(13),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => \m_axis_rx_tuser_xhdl1[14]_i_1_n_0\,
      Q => m_axis_rx_tuser(14),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => '0',
      Q => m_axis_rx_tuser(15),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => '0',
      Q => m_axis_rx_tuser(16),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => '1',
      Q => m_axis_rx_tuser(17),
      R => user_reset_out_reg
    );
\m_axis_rx_tuser_xhdl1_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => '1',
      Q => m_axis_rx_tuser(18),
      R => user_reset_out_reg
    );
\m_axis_rx_tuser_xhdl1_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => null_mux_sel_reg_2,
      Q => m_axis_rx_tuser(19),
      R => user_reset_out_reg
    );
\m_axis_rx_tuser_xhdl1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => \m_axis_rx_tuser_xhdl1[1]_i_1_n_0\,
      Q => m_axis_rx_tuser(1),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => '0',
      Q => m_axis_rx_tuser(20),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => data_prev_reg_1,
      Q => m_axis_rx_tuser(21),
      R => user_reset_out_reg
    );
\m_axis_rx_tuser_xhdl1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => \m_axis_rx_tuser_xhdl1[2]_i_1_n_0\,
      Q => m_axis_rx_tuser(2),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => \m_axis_rx_tuser_xhdl1[3]_i_1_n_0\,
      Q => m_axis_rx_tuser(3),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => \m_axis_rx_tuser_xhdl1[4]_i_1_n_0\,
      Q => m_axis_rx_tuser(4),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => \m_axis_rx_tuser_xhdl1[5]_i_1_n_0\,
      Q => m_axis_rx_tuser(5),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => \m_axis_rx_tuser_xhdl1[6]_i_1_n_0\,
      Q => m_axis_rx_tuser(6),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => \m_axis_rx_tuser_xhdl1[7]_i_1_n_0\,
      Q => m_axis_rx_tuser(7),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => \m_axis_rx_tuser_xhdl1[8]_i_1_n_0\,
      Q => m_axis_rx_tuser(8),
      R => \m_axis_rx_tuser_xhdl1[20]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => '0',
      Q => m_axis_rx_tuser(9),
      R => '0'
    );
m_axis_rx_tvalid_xhdl2_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFE2"
    )
        port map (
      I0 => rsrc_rdy_filtered10_out,
      I1 => data_prev,
      I2 => trn_rsrc_rdy_prev,
      I3 => \^null_mux_sel\,
      I4 => reg_dsc_detect_reg_n_0,
      I5 => m_axis_rx_tvalid_xhdl2_i_2_n_0,
      O => m_axis_rx_tvalid_xhdl2_i_1_n_0
    );
m_axis_rx_tvalid_xhdl2_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002020200020"
    )
        port map (
      I0 => \^trn_in_packet_reg_0\,
      I1 => trn_rsrc_dsc_d,
      I2 => trn_rsrc_dsc,
      I3 => trn_rsof,
      I4 => trn_reof,
      I5 => \^e\(0),
      O => m_axis_rx_tvalid_xhdl2_i_2_n_0
    );
m_axis_rx_tvalid_xhdl2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => m_axis_rx_tvalid_xhdl2_i_1_n_0,
      Q => \^m_axis_rx_tvalid\,
      R => user_reset_out_reg
    );
new_pkt_len_1_inferred_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7888"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(4),
      I1 => \^m_axis_rx_tdata\(30),
      I2 => new_pkt_len_1_inferred_i_6_n_0,
      I3 => \^m_axis_rx_tdata\(3),
      O => in0(4)
    );
new_pkt_len_1_inferred_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => new_pkt_len_1_inferred_i_6_n_0,
      I1 => \^m_axis_rx_tdata\(3),
      I2 => \^m_axis_rx_tdata\(30),
      O => in0(3)
    );
new_pkt_len_1_inferred_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0444444CC8888880"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(1),
      I1 => \^m_axis_rx_tdata\(30),
      I2 => \^m_axis_rx_tdata\(0),
      I3 => \^m_axis_rx_tdata\(15),
      I4 => \^m_axis_rx_tdata\(29),
      I5 => \^m_axis_rx_tdata\(2),
      O => in0(2)
    );
new_pkt_len_1_inferred_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B73F3F48"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(0),
      I1 => \^m_axis_rx_tdata\(30),
      I2 => \^m_axis_rx_tdata\(1),
      I3 => \^m_axis_rx_tdata\(29),
      I4 => \^m_axis_rx_tdata\(15),
      O => in0(1)
    );
new_pkt_len_1_inferred_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7887"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(0),
      I2 => \^m_axis_rx_tdata\(15),
      I3 => \^m_axis_rx_tdata\(29),
      O => in0(0)
    );
new_pkt_len_1_inferred_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE80000000000000"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(29),
      I1 => \^m_axis_rx_tdata\(15),
      I2 => \^m_axis_rx_tdata\(0),
      I3 => \^m_axis_rx_tdata\(1),
      I4 => \^m_axis_rx_tdata\(2),
      I5 => \^m_axis_rx_tdata\(30),
      O => new_pkt_len_1_inferred_i_6_n_0
    );
new_pkt_len_inferred_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(9),
      O => \reg_pkt_len_counter_reg[9]\(4)
    );
new_pkt_len_inferred_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(8),
      O => \reg_pkt_len_counter_reg[9]\(3)
    );
new_pkt_len_inferred_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(7),
      O => \reg_pkt_len_counter_reg[9]\(2)
    );
new_pkt_len_inferred_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(6),
      O => \reg_pkt_len_counter_reg[9]\(1)
    );
new_pkt_len_inferred_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(5),
      O => \reg_pkt_len_counter_reg[9]\(0)
    );
null_mux_sel_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAABAAABABBBB"
    )
        port map (
      I0 => user_reset_out_reg,
      I1 => \^null_mux_sel\,
      I2 => \^m_axis_rx_tvalid\,
      I3 => m_axis_rx_tready,
      I4 => reg_dsc_detect_reg_n_0,
      I5 => m_axis_rx_tvalid_xhdl2_i_2_n_0,
      O => null_mux_sel_reg_0
    );
null_mux_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \reg_pkt_len_counter_reg[0]\,
      Q => \^null_mux_sel\,
      R => '0'
    );
reg_dsc_detect_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000040FF00004040"
    )
        port map (
      I0 => trn_rdst_rdy_xhdl4_reg_1,
      I1 => trn_rsrc_dsc,
      I2 => reg_dsc_detect_i_3_n_0,
      I3 => \^null_mux_sel\,
      I4 => user_reset_out_reg,
      I5 => reg_dsc_detect_reg_n_0,
      O => reg_dsc_detect_i_1_n_0
    );
reg_dsc_detect_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^trn_in_packet_reg_0\,
      I1 => trn_rsrc_dsc_d,
      O => reg_dsc_detect_i_3_n_0
    );
reg_dsc_detect_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => reg_dsc_detect_i_1_n_0,
      Q => reg_dsc_detect_reg_n_0,
      R => '0'
    );
\reg_tkeep[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => is_eof_prev(2),
      I1 => data_prev,
      I2 => trn_rrem(0),
      O => \m_axis_rx_tuser_xhdl1_reg[19]_0\
    );
\reg_tkeep_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => '1',
      Q => m_axis_rx_tkeep(0),
      S => user_reset_out_reg
    );
\reg_tkeep_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => '1',
      Q => m_axis_rx_tkeep(1),
      S => user_reset_out_reg
    );
\reg_tkeep_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => '1',
      Q => m_axis_rx_tkeep(2),
      S => user_reset_out_reg
    );
\reg_tkeep_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => '1',
      Q => m_axis_rx_tkeep(3),
      S => user_reset_out_reg
    );
\reg_tkeep_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => D(0),
      Q => m_axis_rx_tkeep(4),
      S => user_reset_out_reg
    );
\reg_tkeep_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => D(1),
      Q => m_axis_rx_tkeep(5),
      S => user_reset_out_reg
    );
\reg_tkeep_reg[6]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => D(2),
      Q => m_axis_rx_tkeep(6),
      S => user_reset_out_reg
    );
\reg_tkeep_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => D(3),
      Q => m_axis_rx_tkeep(7),
      S => user_reset_out_reg
    );
reg_tlast_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => trn_reof,
      I1 => data_prev,
      I2 => is_eof_prev(4),
      I3 => \^null_mux_sel\,
      O => reg_tlast_reg_0
    );
reg_tlast_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => data_prev_reg_0,
      Q => m_axis_rx_tlast,
      R => user_reset_out_reg
    );
trn_in_packet_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => user_reset_out_reg_0,
      Q => \^trn_in_packet_reg_0\,
      R => '0'
    );
\trn_rbar_hit_prev_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rbar_hit(0),
      Q => trn_rbar_hit_prev(0),
      R => user_reset_out_reg
    );
\trn_rbar_hit_prev_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rbar_hit(1),
      Q => trn_rbar_hit_prev(1),
      R => user_reset_out_reg
    );
\trn_rbar_hit_prev_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rbar_hit(2),
      Q => trn_rbar_hit_prev(2),
      R => user_reset_out_reg
    );
\trn_rbar_hit_prev_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rbar_hit(3),
      Q => trn_rbar_hit_prev(3),
      R => user_reset_out_reg
    );
\trn_rbar_hit_prev_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rbar_hit(4),
      Q => trn_rbar_hit_prev(4),
      R => user_reset_out_reg
    );
\trn_rbar_hit_prev_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rbar_hit(5),
      Q => trn_rbar_hit_prev(5),
      R => user_reset_out_reg
    );
\trn_rbar_hit_prev_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rbar_hit(6),
      Q => trn_rbar_hit_prev(6),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(32),
      Q => trn_rd_prev(0),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(42),
      Q => trn_rd_prev(10),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(43),
      Q => trn_rd_prev(11),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(44),
      Q => trn_rd_prev(12),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(45),
      Q => trn_rd_prev(13),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(46),
      Q => trn_rd_prev(14),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(47),
      Q => trn_rd_prev(15),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(48),
      Q => trn_rd_prev(16),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(49),
      Q => trn_rd_prev(17),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(50),
      Q => trn_rd_prev(18),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(51),
      Q => trn_rd_prev(19),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(33),
      Q => trn_rd_prev(1),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(52),
      Q => trn_rd_prev(20),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(53),
      Q => trn_rd_prev(21),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(54),
      Q => trn_rd_prev(22),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(55),
      Q => trn_rd_prev(23),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(56),
      Q => trn_rd_prev(24),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(57),
      Q => trn_rd_prev(25),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(58),
      Q => trn_rd_prev(26),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(59),
      Q => trn_rd_prev(27),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(60),
      Q => trn_rd_prev(28),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(61),
      Q => trn_rd_prev(29),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(34),
      Q => trn_rd_prev(2),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(62),
      Q => trn_rd_prev(30),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(63),
      Q => trn_rd_prev(31),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(0),
      Q => trn_rd_prev(32),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(1),
      Q => trn_rd_prev(33),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(2),
      Q => trn_rd_prev(34),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(3),
      Q => trn_rd_prev(35),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(4),
      Q => trn_rd_prev(36),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(5),
      Q => trn_rd_prev(37),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(6),
      Q => trn_rd_prev(38),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(7),
      Q => trn_rd_prev(39),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(35),
      Q => trn_rd_prev(3),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(8),
      Q => trn_rd_prev(40),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(9),
      Q => trn_rd_prev(41),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(10),
      Q => trn_rd_prev(42),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(11),
      Q => trn_rd_prev(43),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(12),
      Q => trn_rd_prev(44),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(13),
      Q => trn_rd_prev(45),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(14),
      Q => trn_rd_prev(46),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(15),
      Q => trn_rd_prev(47),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(16),
      Q => trn_rd_prev(48),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(17),
      Q => trn_rd_prev(49),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(36),
      Q => trn_rd_prev(4),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(18),
      Q => trn_rd_prev(50),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(19),
      Q => trn_rd_prev(51),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(20),
      Q => trn_rd_prev(52),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(21),
      Q => trn_rd_prev(53),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(22),
      Q => trn_rd_prev(54),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(23),
      Q => trn_rd_prev(55),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(24),
      Q => trn_rd_prev(56),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(25),
      Q => trn_rd_prev(57),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(26),
      Q => trn_rd_prev(58),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(27),
      Q => trn_rd_prev(59),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(37),
      Q => trn_rd_prev(5),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(28),
      Q => trn_rd_prev(60),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(29),
      Q => trn_rd_prev(61),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(30),
      Q => trn_rd_prev(62),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(31),
      Q => trn_rd_prev(63),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(38),
      Q => trn_rd_prev(6),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(39),
      Q => trn_rd_prev(7),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(40),
      Q => trn_rd_prev(8),
      R => user_reset_out_reg
    );
\trn_rd_prev_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rd(41),
      Q => trn_rd_prev(9),
      R => user_reset_out_reg
    );
trn_rdst_rdy_xhdl4_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000E0000000EEE"
    )
        port map (
      I0 => trn_rdst_rdy_xhdl4_reg_1,
      I1 => trn_rdst_rdy_xhdl4_i_4_n_0,
      I2 => \^null_mux_sel\,
      I3 => m_axis_rx_tready,
      I4 => reg_dsc_detect_reg_n_0,
      I5 => \^m_axis_rx_tvalid\,
      O => trn_rdst_rdy_xhdl4_reg_0
    );
trn_rdst_rdy_xhdl4_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => trn_rsrc_dsc,
      I1 => trn_rsrc_dsc_d,
      I2 => \^trn_in_packet_reg_0\,
      O => trn_rdst_rdy_xhdl4_i_4_n_0
    );
trn_rdst_rdy_xhdl4_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => null_mux_sel_reg_1,
      Q => \^e\(0),
      R => user_reset_out_reg
    );
trn_recrc_err_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_recrc_err,
      Q => trn_recrc_err_prev,
      R => user_reset_out_reg
    );
trn_reof_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_reof,
      Q => is_eof_prev(4),
      R => user_reset_out_reg
    );
trn_rerrfwd_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rerrfwd,
      Q => trn_rerrfwd_prev,
      R => user_reset_out_reg
    );
\trn_rrem_prev_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rrem(0),
      Q => is_eof_prev(2),
      R => user_reset_out_reg
    );
trn_rsof_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rsof,
      Q => trn_rsof_prev,
      R => user_reset_out_reg
    );
trn_rsrc_dsc_d_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => trn_rsrc_dsc,
      Q => trn_rsrc_dsc_d,
      R => user_reset_out_reg
    );
trn_rsrc_dsc_prev_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => reg_dsc_detect_reg_n_0,
      I1 => trn_rsrc_dsc,
      O => trn_rsrc_dsc_prev0
    );
trn_rsrc_dsc_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => trn_rsrc_dsc_prev0,
      Q => trn_rsrc_dsc_prev,
      R => user_reset_out_reg
    );
trn_rsrc_rdy_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => \^e\(0),
      D => rsrc_rdy_filtered10_out,
      Q => trn_rsrc_rdy_prev,
      R => user_reset_out_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_pipeline is
  port (
    trn_teof : out STD_LOGIC;
    trn_tsrc_rdy : out STD_LOGIC;
    trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 );
    \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0\ : out STD_LOGIC;
    \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_1\ : out STD_LOGIC;
    trn_tsof : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    user_reset_out_reg : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    p_5_out : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    user_reset_out_reg_0 : in STD_LOGIC;
    tready_thrtl_xhdl1_reg : in STD_LOGIC;
    user_lnk_up_int_reg : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_pipeline : entity is "PCIeGen1x8If64_axi_basic_tx_pipeline";
end PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_pipeline;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_pipeline is
  signal \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1_n_0\ : STD_LOGIC;
  signal \^tnrtl_ctl_trn_flush.reg_disable_trn_reg_0\ : STD_LOGIC;
  signal \^tnrtl_ctl_trn_flush.reg_disable_trn_reg_1\ : STD_LOGIC;
  signal reg_tvalid : STD_LOGIC;
  signal \trn_in_packet_i_1__0_n_0\ : STD_LOGIC;
  signal \trn_in_packet_i_2__0_n_0\ : STD_LOGIC;
  signal trn_in_packet_i_3_n_0 : STD_LOGIC;
  signal trn_in_packet_reg_n_0 : STD_LOGIC;
  signal \^trn_teof\ : STD_LOGIC;
  signal \^trn_tsrc_rdy\ : STD_LOGIC;
begin
  \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0\ <= \^tnrtl_ctl_trn_flush.reg_disable_trn_reg_0\;
  \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_1\ <= \^tnrtl_ctl_trn_flush.reg_disable_trn_reg_1\;
  trn_teof <= \^trn_teof\;
  trn_tsrc_rdy <= \^trn_tsrc_rdy\;
\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11110010"
    )
        port map (
      I0 => user_reset_out_reg,
      I1 => tready_thrtl_xhdl1_reg,
      I2 => \^tnrtl_ctl_trn_flush.reg_disable_trn_reg_0\,
      I3 => user_lnk_up_int_reg,
      I4 => \^tnrtl_ctl_trn_flush.reg_disable_trn_reg_1\,
      O => \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1_n_0\
    );
\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1_n_0\,
      Q => \^tnrtl_ctl_trn_flush.reg_disable_trn_reg_1\,
      R => '0'
    );
axi_in_packet_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => user_reset_out_reg_0,
      Q => \^tnrtl_ctl_trn_flush.reg_disable_trn_reg_0\,
      R => '0'
    );
pcie_block_i_i_31: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => reg_tvalid,
      I1 => trn_in_packet_reg_n_0,
      O => trn_tsof
    );
\trn_in_packet_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10DF1010"
    )
        port map (
      I0 => user_reset_out_reg,
      I1 => \trn_in_packet_i_2__0_n_0\,
      I2 => trn_tdst_rdy,
      I3 => trn_in_packet_i_3_n_0,
      I4 => trn_in_packet_reg_n_0,
      O => \trn_in_packet_i_1__0_n_0\
    );
\trn_in_packet_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \^trn_teof\,
      I1 => \^trn_tsrc_rdy\,
      I2 => trn_in_packet_reg_n_0,
      I3 => reg_tvalid,
      O => \trn_in_packet_i_2__0_n_0\
    );
trn_in_packet_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FDDDDDDD"
    )
        port map (
      I0 => user_lnk_up_int_reg,
      I1 => user_reset_out_reg,
      I2 => \^trn_teof\,
      I3 => trn_in_packet_reg_n_0,
      I4 => \^trn_tsrc_rdy\,
      O => trn_in_packet_i_3_n_0
    );
trn_in_packet_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \trn_in_packet_i_1__0_n_0\,
      Q => trn_in_packet_reg_n_0,
      R => '0'
    );
\xhdl12.reg_tdata_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(0),
      Q => Q(0),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(10),
      Q => Q(10),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(11),
      Q => Q(11),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(12),
      Q => Q(12),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(13),
      Q => Q(13),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(14),
      Q => Q(14),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(15),
      Q => Q(15),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(16),
      Q => Q(16),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(17),
      Q => Q(17),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(18),
      Q => Q(18),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(19),
      Q => Q(19),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(1),
      Q => Q(1),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(20),
      Q => Q(20),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(21),
      Q => Q(21),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(22),
      Q => Q(22),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(23),
      Q => Q(23),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(24),
      Q => Q(24),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(25),
      Q => Q(25),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(26),
      Q => Q(26),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(27),
      Q => Q(27),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(28),
      Q => Q(28),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(29),
      Q => Q(29),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(2),
      Q => Q(2),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(30),
      Q => Q(30),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(31),
      Q => Q(31),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(32),
      Q => Q(32),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(33),
      Q => Q(33),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(34),
      Q => Q(34),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(35),
      Q => Q(35),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(36),
      Q => Q(36),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(37),
      Q => Q(37),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(38),
      Q => Q(38),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(39),
      Q => Q(39),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(3),
      Q => Q(3),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(40),
      Q => Q(40),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(41),
      Q => Q(41),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(42),
      Q => Q(42),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(43),
      Q => Q(43),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(44),
      Q => Q(44),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(45),
      Q => Q(45),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(46),
      Q => Q(46),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(47),
      Q => Q(47),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(48),
      Q => Q(48),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(49),
      Q => Q(49),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(4),
      Q => Q(4),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(50),
      Q => Q(50),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(51),
      Q => Q(51),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(52),
      Q => Q(52),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(53),
      Q => Q(53),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(54),
      Q => Q(54),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(55),
      Q => Q(55),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(56),
      Q => Q(56),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(57),
      Q => Q(57),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(58),
      Q => Q(58),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(59),
      Q => Q(59),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(5),
      Q => Q(5),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(60),
      Q => Q(60),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(61),
      Q => Q(61),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(62),
      Q => Q(62),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(63),
      Q => Q(63),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(6),
      Q => Q(6),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(7),
      Q => Q(7),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(8),
      Q => Q(8),
      R => user_reset_out_reg
    );
\xhdl12.reg_tdata_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tdata(9),
      Q => Q(9),
      R => user_reset_out_reg
    );
\xhdl12.reg_tkeep_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tkeep(0),
      Q => trn_trem(0),
      R => user_reset_out_reg
    );
\xhdl12.reg_tlast_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tlast,
      Q => \^trn_teof\,
      R => user_reset_out_reg
    );
\xhdl12.reg_tsrc_rdy_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => p_5_out,
      Q => \^trn_tsrc_rdy\,
      R => user_reset_out_reg
    );
\xhdl12.reg_tuser_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tuser(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(0),
      R => user_reset_out_reg
    );
\xhdl12.reg_tuser_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tuser(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(1),
      R => user_reset_out_reg
    );
\xhdl12.reg_tuser_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tuser(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(2),
      R => user_reset_out_reg
    );
\xhdl12.reg_tuser_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tuser(3),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(3),
      R => user_reset_out_reg
    );
\xhdl12.reg_tvalid_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => s_axis_tx_tvalid,
      Q => reg_tvalid,
      R => user_reset_out_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_thrtl_ctl is
  port (
    s_axis_tx_tready : out STD_LOGIC;
    tready_thrtl_xhdl1_reg_0 : out STD_LOGIC;
    tbuf_av_gap_thrtl_reg_0 : out STD_LOGIC;
    tbuf_av_gap_thrtl_reg_1 : out STD_LOGIC;
    axi_in_packet_reg : out STD_LOGIC;
    trn_tcfg_gnt : out STD_LOGIC;
    p_5_out : out STD_LOGIC;
    cfg_pm_turnoff_ok_n : out STD_LOGIC;
    user_reset_out_reg : in STD_LOGIC;
    tx_cfg_gnt : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    trn_tcfg_req : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    tbuf_av_min_trig : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axis_tx_tlast : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC;
    user_lnk_up_int_reg : in STD_LOGIC;
    cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 );
    axi_in_packet_reg_0 : in STD_LOGIC;
    user_reset_out_reg_0 : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC;
    \tcfg_req_cnt_reg[1]_0\ : in STD_LOGIC;
    \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg\ : in STD_LOGIC;
    trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_to_turnoff : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_thrtl_ctl : entity is "PCIeGen1x8If64_axi_basic_tx_thrtl_ctl";
end PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_thrtl_ctl;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_thrtl_ctl is
  signal CUR_STATE_A : STD_LOGIC;
  signal CUR_STATE_A_i_2_n_0 : STD_LOGIC;
  signal NEXT_STATE_A : STD_LOGIC;
  signal cfg_pcie_link_state_d : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^cfg_pm_turnoff_ok_n\ : STD_LOGIC;
  signal cfg_turnoff_ok_pending : STD_LOGIC;
  signal cfg_turnoff_ok_pending_i_1_n_0 : STD_LOGIC;
  signal lnk_up_thrtl : STD_LOGIC;
  signal lnk_up_thrtl_i_1_n_0 : STD_LOGIC;
  signal pcie_block_i_i_36_n_0 : STD_LOGIC;
  signal pcie_block_i_i_37_n_0 : STD_LOGIC;
  signal ppm_L1_thrtl_i_1_n_0 : STD_LOGIC;
  signal ppm_L1_thrtl_i_2_n_0 : STD_LOGIC;
  signal ppm_L1_thrtl_i_3_n_0 : STD_LOGIC;
  signal ppm_L1_thrtl_reg_n_0 : STD_LOGIC;
  signal ppm_L23_thrtl : STD_LOGIC;
  signal ppm_L23_thrtl_i_1_n_0 : STD_LOGIC;
  signal reg_axi_in_pkt : STD_LOGIC;
  signal reg_axi_in_pkt_i_1_n_0 : STD_LOGIC;
  signal reg_tcfg_gnt : STD_LOGIC;
  signal reg_to_turnoff : STD_LOGIC;
  signal reg_turnoff_ok : STD_LOGIC;
  signal \^s_axis_tx_tready\ : STD_LOGIC;
  signal tbuf_av_d : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal tbuf_av_gap_thrtl_i_1_n_0 : STD_LOGIC;
  signal tbuf_av_gap_thrtl_i_4_n_0 : STD_LOGIC;
  signal \^tbuf_av_gap_thrtl_reg_0\ : STD_LOGIC;
  signal tbuf_av_gap_thrtl_reg_n_0 : STD_LOGIC;
  signal tbuf_av_min_thrtl : STD_LOGIC;
  signal \tbuf_gap_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \tbuf_gap_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \tbuf_gap_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \tbuf_gap_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \tbuf_gap_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \tbuf_gap_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal tcfg_gnt_pending_i_1_n_0 : STD_LOGIC;
  signal tcfg_gnt_pending_reg_n_0 : STD_LOGIC;
  signal tcfg_req_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \tcfg_req_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \tcfg_req_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal tcfg_req_thrtl : STD_LOGIC;
  signal tcfg_req_thrtl_i_1_n_0 : STD_LOGIC;
  signal tcfg_req_thrtl_i_2_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl10 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_3_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_4_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_6_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_7_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_9_n_0 : STD_LOGIC;
  signal \^tready_thrtl_xhdl1_reg_0\ : STD_LOGIC;
  signal \^trn_tcfg_gnt\ : STD_LOGIC;
  signal trn_tcfg_req_d : STD_LOGIC;
  signal trn_tdst_rdy_d : STD_LOGIC;
  signal \xhdl12.xhdl14.xhdl15.reg_to_turnoff_i_1_n_0\ : STD_LOGIC;
  signal \xhdl17.reg_tx_ecrc_pkt_i_1_n_0\ : STD_LOGIC;
  signal \xhdl17.reg_tx_ecrc_pkt_reg_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of axi_in_packet_i_1 : label is "soft_lutpair223";
  attribute SOFT_HLUTNM of pcie_block_i_i_36 : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of pcie_block_i_i_37 : label is "soft_lutpair223";
  attribute SOFT_HLUTNM of tbuf_av_gap_thrtl_i_3 : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of tbuf_av_gap_thrtl_i_4 : label is "soft_lutpair224";
  attribute SOFT_HLUTNM of \tbuf_gap_cnt[0]_i_1\ : label is "soft_lutpair224";
  attribute SOFT_HLUTNM of tcfg_req_thrtl_i_2 : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of tready_thrtl_xhdl1_i_2 : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of tready_thrtl_xhdl1_i_4 : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of tready_thrtl_xhdl1_i_9 : label is "soft_lutpair228";
  attribute SOFT_HLUTNM of \xhdl12.reg_tsrc_rdy_i_1\ : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of \xhdl12.xhdl14.xhdl15.reg_to_turnoff_i_1\ : label is "soft_lutpair228";
begin
  cfg_pm_turnoff_ok_n <= \^cfg_pm_turnoff_ok_n\;
  s_axis_tx_tready <= \^s_axis_tx_tready\;
  tbuf_av_gap_thrtl_reg_0 <= \^tbuf_av_gap_thrtl_reg_0\;
  tready_thrtl_xhdl1_reg_0 <= \^tready_thrtl_xhdl1_reg_0\;
  trn_tcfg_gnt <= \^trn_tcfg_gnt\;
CUR_STATE_A_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8AA88AAA8AAAAAA"
    )
        port map (
      I0 => CUR_STATE_A_i_2_n_0,
      I1 => CUR_STATE_A,
      I2 => s_axis_tx_tlast,
      I3 => \^s_axis_tx_tready\,
      I4 => s_axis_tx_tvalid,
      I5 => reg_axi_in_pkt,
      O => NEXT_STATE_A
    );
CUR_STATE_A_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => lnk_up_thrtl,
      I1 => ppm_L1_thrtl_reg_n_0,
      I2 => tbuf_av_gap_thrtl_reg_n_0,
      I3 => ppm_L23_thrtl,
      I4 => tcfg_req_thrtl,
      I5 => tbuf_av_min_thrtl,
      O => CUR_STATE_A_i_2_n_0
    );
CUR_STATE_A_reg: unisim.vcomponents.FDSE
     port map (
      C => user_clk,
      CE => '1',
      D => NEXT_STATE_A,
      Q => CUR_STATE_A,
      S => user_reset_out_reg
    );
axi_in_packet_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"13331000"
    )
        port map (
      I0 => s_axis_tx_tlast,
      I1 => user_reset_out_reg,
      I2 => s_axis_tx_tvalid,
      I3 => \^s_axis_tx_tready\,
      I4 => axi_in_packet_reg_0,
      O => axi_in_packet_reg
    );
\cfg_pcie_link_state_d_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => cfg_pcie_link_state(0),
      Q => cfg_pcie_link_state_d(0),
      R => user_reset_out_reg
    );
\cfg_pcie_link_state_d_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => cfg_pcie_link_state(1),
      Q => cfg_pcie_link_state_d(1),
      R => user_reset_out_reg
    );
\cfg_pcie_link_state_d_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => cfg_pcie_link_state(2),
      Q => cfg_pcie_link_state_d(2),
      R => user_reset_out_reg
    );
cfg_turnoff_ok_pending_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF404040"
    )
        port map (
      I0 => ppm_L23_thrtl,
      I1 => reg_to_turnoff,
      I2 => reg_turnoff_ok,
      I3 => \^cfg_pm_turnoff_ok_n\,
      I4 => cfg_turnoff_ok_pending,
      O => cfg_turnoff_ok_pending_i_1_n_0
    );
cfg_turnoff_ok_pending_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => cfg_turnoff_ok_pending_i_1_n_0,
      Q => cfg_turnoff_ok_pending,
      R => user_reset_out_reg
    );
lnk_up_thrtl_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF4F"
    )
        port map (
      I0 => trn_tdst_rdy,
      I1 => lnk_up_thrtl,
      I2 => user_lnk_up_int_reg,
      I3 => user_reset_out_reg,
      O => lnk_up_thrtl_i_1_n_0
    );
lnk_up_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => lnk_up_thrtl_i_1_n_0,
      Q => lnk_up_thrtl,
      R => '0'
    );
pcie_block_i_i_26: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDF505FDFDF5F5F"
    )
        port map (
      I0 => cfg_turnoff_ok_pending,
      I1 => tcfg_gnt_pending_reg_n_0,
      I2 => CUR_STATE_A,
      I3 => ppm_L23_thrtl,
      I4 => tcfg_req_thrtl,
      I5 => pcie_block_i_i_36_n_0,
      O => \^cfg_pm_turnoff_ok_n\
    );
pcie_block_i_i_30: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA222A0000222A"
    )
        port map (
      I0 => tcfg_req_thrtl,
      I1 => pcie_block_i_i_37_n_0,
      I2 => s_axis_tx_tvalid,
      I3 => reg_axi_in_pkt,
      I4 => CUR_STATE_A,
      I5 => tcfg_gnt_pending_reg_n_0,
      O => \^trn_tcfg_gnt\
    );
pcie_block_i_i_36: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D1FF"
    )
        port map (
      I0 => reg_axi_in_pkt,
      I1 => s_axis_tx_tvalid,
      I2 => s_axis_tx_tlast,
      I3 => \^s_axis_tx_tready\,
      O => pcie_block_i_i_36_n_0
    );
pcie_block_i_i_37: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \^s_axis_tx_tready\,
      I1 => s_axis_tx_tlast,
      I2 => s_axis_tx_tvalid,
      O => pcie_block_i_i_37_n_0
    );
ppm_L1_thrtl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"808080FF80808000"
    )
        port map (
      I0 => ppm_L1_thrtl_i_2_n_0,
      I1 => cfg_pcie_link_state(0),
      I2 => cfg_pcie_link_state(2),
      I3 => ppm_L1_thrtl_i_3_n_0,
      I4 => user_reset_out_reg_0,
      I5 => ppm_L1_thrtl_reg_n_0,
      O => ppm_L1_thrtl_i_1_n_0
    );
ppm_L1_thrtl_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => cfg_pcie_link_state_d(2),
      I1 => cfg_pcie_link_state(1),
      I2 => user_reset_out_reg,
      I3 => cfg_pcie_link_state_d(0),
      I4 => cfg_pcie_link_state_d(1),
      O => ppm_L1_thrtl_i_2_n_0
    );
ppm_L1_thrtl_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => cfg_pcie_link_state_d(2),
      I1 => cfg_pcie_link_state(1),
      I2 => cfg_pcie_link_state_d(0),
      I3 => cfg_pcie_link_state_d(1),
      I4 => cfg_pcie_link_state(2),
      I5 => cfg_pcie_link_state(0),
      O => ppm_L1_thrtl_i_3_n_0
    );
ppm_L1_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => ppm_L1_thrtl_i_1_n_0,
      Q => ppm_L1_thrtl_reg_n_0,
      R => '0'
    );
ppm_L23_thrtl_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => reg_to_turnoff,
      I1 => reg_turnoff_ok,
      I2 => ppm_L23_thrtl,
      O => ppm_L23_thrtl_i_1_n_0
    );
ppm_L23_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => ppm_L23_thrtl_i_1_n_0,
      Q => ppm_L23_thrtl,
      R => user_reset_out_reg
    );
reg_axi_in_pkt_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000AEA"
    )
        port map (
      I0 => reg_axi_in_pkt,
      I1 => \^s_axis_tx_tready\,
      I2 => s_axis_tx_tvalid,
      I3 => s_axis_tx_tlast,
      I4 => user_reset_out_reg,
      O => reg_axi_in_pkt_i_1_n_0
    );
reg_axi_in_pkt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => reg_axi_in_pkt_i_1_n_0,
      Q => reg_axi_in_pkt,
      R => '0'
    );
reg_tcfg_gnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => tx_cfg_gnt,
      Q => reg_tcfg_gnt,
      R => user_reset_out_reg
    );
\tbuf_av_d_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => trn_tbuf_av(0),
      Q => tbuf_av_d(0),
      R => user_reset_out_reg
    );
\tbuf_av_d_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => trn_tbuf_av(1),
      Q => tbuf_av_d(1),
      R => user_reset_out_reg
    );
\tbuf_av_d_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => trn_tbuf_av(2),
      Q => tbuf_av_d(2),
      R => user_reset_out_reg
    );
\tbuf_av_d_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => trn_tbuf_av(3),
      Q => tbuf_av_d(3),
      R => user_reset_out_reg
    );
\tbuf_av_d_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => trn_tbuf_av(4),
      Q => tbuf_av_d(4),
      R => user_reset_out_reg
    );
\tbuf_av_d_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => trn_tbuf_av(5),
      Q => tbuf_av_d(5),
      R => user_reset_out_reg
    );
tbuf_av_gap_thrtl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00EF00FF00EE00FF"
    )
        port map (
      I0 => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\,
      I1 => \^tbuf_av_gap_thrtl_reg_0\,
      I2 => tbuf_av_gap_thrtl_i_4_n_0,
      I3 => user_reset_out_reg,
      I4 => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\,
      I5 => tbuf_av_gap_thrtl_reg_n_0,
      O => tbuf_av_gap_thrtl_i_1_n_0
    );
tbuf_av_gap_thrtl_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020000"
    )
        port map (
      I0 => trn_tdst_rdy,
      I1 => tcfg_req_cnt(1),
      I2 => tcfg_req_cnt(0),
      I3 => trn_tdst_rdy_d,
      I4 => tcfg_req_thrtl,
      O => \^tbuf_av_gap_thrtl_reg_0\
    );
tbuf_av_gap_thrtl_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \tbuf_gap_cnt_reg_n_0_[1]\,
      I1 => \tbuf_gap_cnt_reg_n_0_[0]\,
      I2 => \tbuf_gap_cnt_reg_n_0_[2]\,
      O => tbuf_av_gap_thrtl_i_4_n_0
    );
tbuf_av_gap_thrtl_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => tbuf_av_d(4),
      I1 => tbuf_av_d(2),
      I2 => tbuf_av_d(1),
      I3 => tbuf_av_d(0),
      I4 => tbuf_av_d(3),
      I5 => tbuf_av_d(5),
      O => tbuf_av_gap_thrtl_reg_1
    );
tbuf_av_gap_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => tbuf_av_gap_thrtl_i_1_n_0,
      Q => tbuf_av_gap_thrtl_reg_n_0,
      R => '0'
    );
tbuf_av_min_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => tbuf_av_min_trig,
      Q => tbuf_av_min_thrtl,
      R => user_reset_out_reg
    );
\tbuf_gap_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"32FFFFFF"
    )
        port map (
      I0 => \tbuf_gap_cnt_reg_n_0_[1]\,
      I1 => \tbuf_gap_cnt_reg_n_0_[0]\,
      I2 => \tbuf_gap_cnt_reg_n_0_[2]\,
      I3 => CUR_STATE_A,
      I4 => tbuf_av_gap_thrtl_reg_n_0,
      O => \tbuf_gap_cnt[0]_i_1_n_0\
    );
\tbuf_gap_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000098000000"
    )
        port map (
      I0 => \tbuf_gap_cnt_reg_n_0_[1]\,
      I1 => \tbuf_gap_cnt_reg_n_0_[0]\,
      I2 => \tbuf_gap_cnt_reg_n_0_[2]\,
      I3 => tbuf_av_gap_thrtl_reg_n_0,
      I4 => CUR_STATE_A,
      I5 => user_reset_out_reg,
      O => \tbuf_gap_cnt[1]_i_1_n_0\
    );
\tbuf_gap_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000E0000000"
    )
        port map (
      I0 => \tbuf_gap_cnt_reg_n_0_[1]\,
      I1 => \tbuf_gap_cnt_reg_n_0_[0]\,
      I2 => \tbuf_gap_cnt_reg_n_0_[2]\,
      I3 => tbuf_av_gap_thrtl_reg_n_0,
      I4 => CUR_STATE_A,
      I5 => user_reset_out_reg,
      O => \tbuf_gap_cnt[2]_i_1_n_0\
    );
\tbuf_gap_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \tbuf_gap_cnt[0]_i_1_n_0\,
      Q => \tbuf_gap_cnt_reg_n_0_[0]\,
      R => user_reset_out_reg
    );
\tbuf_gap_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \tbuf_gap_cnt[1]_i_1_n_0\,
      Q => \tbuf_gap_cnt_reg_n_0_[1]\,
      R => '0'
    );
\tbuf_gap_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \tbuf_gap_cnt[2]_i_1_n_0\,
      Q => \tbuf_gap_cnt_reg_n_0_[2]\,
      R => '0'
    );
tcfg_gnt_pending_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"004F0044"
    )
        port map (
      I0 => trn_tcfg_req_d,
      I1 => trn_tcfg_req,
      I2 => \^trn_tcfg_gnt\,
      I3 => user_reset_out_reg,
      I4 => tcfg_gnt_pending_reg_n_0,
      O => tcfg_gnt_pending_i_1_n_0
    );
tcfg_gnt_pending_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => tcfg_gnt_pending_i_1_n_0,
      Q => tcfg_gnt_pending_reg_n_0,
      R => '0'
    );
\tcfg_req_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000D00"
    )
        port map (
      I0 => trn_tcfg_req,
      I1 => trn_tcfg_req_d,
      I2 => tcfg_req_cnt(0),
      I3 => tcfg_req_cnt(1),
      I4 => user_reset_out_reg,
      I5 => tcfg_gnt_pending_reg_n_0,
      O => \tcfg_req_cnt[0]_i_1_n_0\
    );
\tcfg_req_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF444"
    )
        port map (
      I0 => trn_tcfg_req_d,
      I1 => trn_tcfg_req,
      I2 => tcfg_req_cnt(0),
      I3 => tcfg_req_cnt(1),
      I4 => tcfg_gnt_pending_reg_n_0,
      O => \tcfg_req_cnt[1]_i_1_n_0\
    );
\tcfg_req_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \tcfg_req_cnt[0]_i_1_n_0\,
      Q => tcfg_req_cnt(0),
      R => '0'
    );
\tcfg_req_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \tcfg_req_cnt[1]_i_1_n_0\,
      Q => tcfg_req_cnt(1),
      R => user_reset_out_reg
    );
tcfg_req_thrtl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00D500C0"
    )
        port map (
      I0 => tcfg_req_thrtl_i_2_n_0,
      I1 => reg_tcfg_gnt,
      I2 => trn_tcfg_req,
      I3 => user_reset_out_reg,
      I4 => tcfg_req_thrtl,
      O => tcfg_req_thrtl_i_1_n_0
    );
tcfg_req_thrtl_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => trn_tdst_rdy,
      I1 => tcfg_req_cnt(0),
      I2 => tcfg_req_cnt(1),
      I3 => trn_tdst_rdy_d,
      O => tcfg_req_thrtl_i_2_n_0
    );
tcfg_req_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => tcfg_req_thrtl_i_1_n_0,
      Q => tcfg_req_thrtl,
      R => '0'
    );
tready_thrtl_xhdl1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D005D005D005D5D"
    )
        port map (
      I0 => \^tready_thrtl_xhdl1_reg_0\,
      I1 => tready_thrtl_xhdl1_i_3_n_0,
      I2 => \xhdl17.reg_tx_ecrc_pkt_reg_n_0\,
      I3 => tready_thrtl_xhdl1_i_4_n_0,
      I4 => \tcfg_req_cnt_reg[1]_0\,
      I5 => tready_thrtl_xhdl1_i_6_n_0,
      O => tready_thrtl_xhdl10
    );
tready_thrtl_xhdl1_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => s_axis_tx_tlast,
      I1 => s_axis_tx_tvalid,
      I2 => \^s_axis_tx_tready\,
      O => \^tready_thrtl_xhdl1_reg_0\
    );
tready_thrtl_xhdl1_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF87"
    )
        port map (
      I0 => s_axis_tx_tdata(0),
      I1 => s_axis_tx_tdata(3),
      I2 => s_axis_tx_tdata(2),
      I3 => tready_thrtl_xhdl1_i_7_n_0,
      O => tready_thrtl_xhdl1_i_3_n_0
    );
tready_thrtl_xhdl1_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000020E0"
    )
        port map (
      I0 => reg_axi_in_pkt,
      I1 => s_axis_tx_tvalid,
      I2 => \^s_axis_tx_tready\,
      I3 => s_axis_tx_tlast,
      I4 => CUR_STATE_A,
      O => tready_thrtl_xhdl1_i_4_n_0
    );
tready_thrtl_xhdl1_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFD5"
    )
        port map (
      I0 => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\,
      I1 => trn_tcfg_req,
      I2 => reg_tcfg_gnt,
      I3 => CUR_STATE_A_i_2_n_0,
      I4 => tready_thrtl_xhdl1_i_9_n_0,
      I5 => ppm_L1_thrtl_i_3_n_0,
      O => tready_thrtl_xhdl1_i_6_n_0
    );
tready_thrtl_xhdl1_i_7: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF7FF"
    )
        port map (
      I0 => s_axis_tx_tvalid,
      I1 => \^s_axis_tx_tready\,
      I2 => reg_axi_in_pkt,
      I3 => s_axis_tx_tuser(0),
      I4 => s_axis_tx_tdata(1),
      O => tready_thrtl_xhdl1_i_7_n_0
    );
tready_thrtl_xhdl1_i_9: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => reg_turnoff_ok,
      I1 => reg_to_turnoff,
      I2 => user_lnk_up_int_reg,
      O => tready_thrtl_xhdl1_i_9_n_0
    );
tready_thrtl_xhdl1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => tready_thrtl_xhdl10,
      Q => \^s_axis_tx_tready\,
      R => user_reset_out_reg
    );
trn_tcfg_req_d_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => trn_tcfg_req,
      Q => trn_tcfg_req_d,
      R => user_reset_out_reg
    );
trn_tdst_rdy_d_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => trn_tdst_rdy,
      Q => trn_tdst_rdy_d,
      S => user_reset_out_reg
    );
\xhdl12.reg_tsrc_rdy_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => s_axis_tx_tvalid,
      I1 => \^s_axis_tx_tready\,
      I2 => user_lnk_up_int_reg,
      I3 => \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg\,
      O => p_5_out
    );
\xhdl12.xhdl14.reg_turnoff_ok_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => cfg_turnoff_ok,
      Q => reg_turnoff_ok,
      R => user_reset_out_reg
    );
\xhdl12.xhdl14.xhdl15.reg_to_turnoff_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => cfg_to_turnoff,
      I1 => reg_to_turnoff,
      O => \xhdl12.xhdl14.xhdl15.reg_to_turnoff_i_1_n_0\
    );
\xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \xhdl12.xhdl14.xhdl15.reg_to_turnoff_i_1_n_0\,
      Q => reg_to_turnoff,
      R => user_reset_out_reg
    );
\xhdl17.reg_tx_ecrc_pkt_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"07070F0F0000000F"
    )
        port map (
      I0 => s_axis_tx_tvalid,
      I1 => \^s_axis_tx_tready\,
      I2 => user_reset_out_reg,
      I3 => tready_thrtl_xhdl1_i_3_n_0,
      I4 => s_axis_tx_tlast,
      I5 => \xhdl17.reg_tx_ecrc_pkt_reg_n_0\,
      O => \xhdl17.reg_tx_ecrc_pkt_i_1_n_0\
    );
\xhdl17.reg_tx_ecrc_pkt_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => user_clk,
      CE => '1',
      D => \xhdl17.reg_tx_ecrc_pkt_i_1_n_0\,
      Q => \xhdl17.reg_tx_ecrc_pkt_reg_n_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x is
  port (
    \pipe_stages_1.pipe_rx_valid_q_reg\ : out STD_LOGIC;
    gt_rx_phy_status_q : out STD_LOGIC;
    gt_rxelecidle_q : out STD_LOGIC;
    \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC;
    CLK_PCLK : in STD_LOGIC;
    gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    \pl_ltssm_state_q_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pl_ltssm_state_q_reg[5]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x : entity is "PCIeGen1x8If64_gt_rx_valid_filter_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x is
  signal \FSM_sequential_reg_state_eios_det[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : signal is "yes";
  signal \^gt_rx_status_q_reg[2]_0\ : STD_LOGIC;
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal gt_rxvalid_q : STD_LOGIC;
  signal gt_rxvalid_q_i_2_n_0 : STD_LOGIC;
  signal gt_rxvalid_q_i_3_n_0 : STD_LOGIC;
  signal gt_rxvalid_q_i_5_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_15_in : STD_LOGIC;
  signal \^pipe_stages_1.pipe_rx_data_q_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^pipe_stages_1.pipe_rx_valid_q_reg\ : STD_LOGIC;
  signal reg_state_eios_det119_out : STD_LOGIC;
  signal reg_symbol_after_eios : STD_LOGIC;
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_reg_state_eios_det[2]_i_5\ : label is "soft_lutpair0";
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[2]\ : label is "yes";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1\ : label is "soft_lutpair0";
begin
  \gt_rx_status_q_reg[2]_0\ <= \^gt_rx_status_q_reg[2]_0\;
  \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) <= \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0);
  \pipe_stages_1.pipe_rx_valid_q_reg\ <= \^pipe_stages_1.pipe_rx_valid_q_reg\;
\FSM_sequential_reg_state_eios_det[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF73FFF3FF7FFFFF"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      I5 => reg_state_eios_det119_out,
      O => \FSM_sequential_reg_state_eios_det[0]_i_1_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0010"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I3 => \FSM_sequential_reg_state_eios_det[1]_i_2_n_0\,
      I4 => reg_state_eios_det119_out,
      I5 => \FSM_sequential_reg_state_eios_det[1]_i_4_n_0\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_1_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[1]_i_2_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[1]_i_5_n_0\,
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I4 => \FSM_sequential_reg_state_eios_det[2]_i_5_n_0\,
      O => reg_state_eios_det119_out
    );
\FSM_sequential_reg_state_eios_det[1]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_4_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      O => \FSM_sequential_reg_state_eios_det[1]_i_5_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03B00000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => \FSM_sequential_reg_state_eios_det[2]_i_1_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I3 => \FSM_sequential_reg_state_eios_det[2]_i_4_n_0\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_2_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      I5 => \FSM_sequential_reg_state_eios_det[2]_i_5_n_0\,
      O => p_15_in
    );
\FSM_sequential_reg_state_eios_det[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[2]_i_4_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      I3 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_5_n_0\
    );
\FSM_sequential_reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[0]_i_1_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      S => Q
    );
\FSM_sequential_reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[1]_i_1_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      R => Q
    );
\FSM_sequential_reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[2]_i_1_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      R => Q
    );
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rx_phy_status_wire_filter(0),
      Q => gt_rx_phy_status_q,
      R => Q
    );
\gt_rx_status_q[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => \pl_ltssm_state_q_reg[5]\(4),
      I1 => \pl_ltssm_state_q_reg[5]\(1),
      I2 => \pl_ltssm_state_q_reg[5]\(2),
      I3 => \pl_ltssm_state_q_reg[5]\(3),
      O => \^gt_rx_status_q_reg[2]_0\
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \pl_ltssm_state_q_reg[5]_0\(0),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(0),
      R => Q
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \pl_ltssm_state_q_reg[5]_0\(1),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(1),
      R => Q
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \pl_ltssm_state_q_reg[5]_0\(2),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2),
      R => Q
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => Q
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(1),
      Q => p_0_in,
      R => Q
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(0),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      R => Q
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(10),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      R => Q
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(11),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      R => Q
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(12),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      R => Q
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(13),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      R => Q
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(14),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      R => Q
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(15),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      R => Q
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(1),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      R => Q
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(2),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      R => Q
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(3),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      R => Q
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(4),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      R => Q
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(5),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      R => Q
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(6),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      R => Q
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(7),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      R => Q
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(8),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      R => Q
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(9),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      R => Q
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXELECIDLE(0),
      Q => gt_rxelecidle_q,
      R => Q
    );
gt_rxvalid_q_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2000000AA00AA00"
    )
        port map (
      I0 => gt_rxvalid_q_i_2_n_0,
      I1 => \FSM_sequential_reg_state_eios_det[2]_i_2_n_0\,
      I2 => gt_rxvalid_q_i_3_n_0,
      I3 => gt_rxvalid_q_reg_0,
      I4 => gt_rxvalid_q_i_5_n_0,
      I5 => p_15_in,
      O => gt_rxvalid_q
    );
gt_rxvalid_q_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => \^gt_rx_status_q_reg[2]_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I4 => \pl_ltssm_state_q_reg[5]\(0),
      I5 => \pl_ltssm_state_q_reg[5]\(5),
      O => gt_rxvalid_q_i_2_n_0
    );
gt_rxvalid_q_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => gt_rxvalid_q_i_3_n_0
    );
gt_rxvalid_q_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      O => gt_rxvalid_q_i_5_n_0
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rxvalid_q,
      Q => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      R => Q
    );
\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => D(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_0_in,
      I1 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I2 => symbol_after_eios,
      O => D(1)
    );
reg_symbol_after_eios_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => reg_symbol_after_eios
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => reg_symbol_after_eios,
      Q => symbol_after_eios,
      R => Q
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_22 is
  port (
    \pipe_stages_1.pipe_rx_valid_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC;
    CLK_PCLK : in STD_LOGIC;
    gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    \pl_ltssm_state_q_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_22 : entity is "PCIeGen1x8If64_gt_rx_valid_filter_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_22;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_22 is
  signal \FSM_sequential_reg_state_eios_det[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_5__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_5__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : signal is "yes";
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal gt_rxvalid_q : STD_LOGIC;
  signal \gt_rxvalid_q_i_2__0_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_3__0_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_5__0_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_15_in : STD_LOGIC;
  signal \^pipe_stages_1.pipe_rx_data_q_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^pipe_stages_1.pipe_rx_valid_q_reg\ : STD_LOGIC;
  signal reg_state_eios_det119_out : STD_LOGIC;
  signal reg_symbol_after_eios : STD_LOGIC;
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_reg_state_eios_det[2]_i_5__0\ : label is "soft_lutpair1";
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[2]\ : label is "yes";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__0\ : label is "soft_lutpair1";
begin
  \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) <= \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0);
  \pipe_stages_1.pipe_rx_valid_q_reg\ <= \^pipe_stages_1.pipe_rx_valid_q_reg\;
\FSM_sequential_reg_state_eios_det[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF73FFF3FF7FFFFF"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      I5 => reg_state_eios_det119_out,
      O => \FSM_sequential_reg_state_eios_det[0]_i_1__0_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0010"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I3 => \FSM_sequential_reg_state_eios_det[1]_i_2__0_n_0\,
      I4 => reg_state_eios_det119_out,
      I5 => \FSM_sequential_reg_state_eios_det[1]_i_4__0_n_0\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_1__0_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[1]_i_2__0_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[1]_i_5__0_n_0\,
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I4 => \FSM_sequential_reg_state_eios_det[2]_i_5__0_n_0\,
      O => reg_state_eios_det119_out
    );
\FSM_sequential_reg_state_eios_det[1]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_4__0_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      O => \FSM_sequential_reg_state_eios_det[1]_i_5__0_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03B00000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => \FSM_sequential_reg_state_eios_det[2]_i_1__0_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I3 => \FSM_sequential_reg_state_eios_det[2]_i_4__0_n_0\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      I5 => \FSM_sequential_reg_state_eios_det[2]_i_5__0_n_0\,
      O => p_15_in
    );
\FSM_sequential_reg_state_eios_det[2]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[2]_i_4__0_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      I3 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_5__0_n_0\
    );
\FSM_sequential_reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[0]_i_1__0_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      S => Q
    );
\FSM_sequential_reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[1]_i_1__0_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      R => Q
    );
\FSM_sequential_reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[2]_i_1__0_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      R => Q
    );
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rx_phy_status_wire_filter(0),
      Q => \pipe_stages_1.pipe_rx_phy_status_q_reg\,
      R => Q
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(0),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(0),
      R => Q
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(1),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(1),
      R => Q
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(2),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2),
      R => Q
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => Q
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(1),
      Q => p_0_in,
      R => Q
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(0),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      R => Q
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(10),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      R => Q
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(11),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      R => Q
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(12),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      R => Q
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(13),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      R => Q
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(14),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      R => Q
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(15),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      R => Q
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(1),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      R => Q
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(2),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      R => Q
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(3),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      R => Q
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(4),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      R => Q
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(5),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      R => Q
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(6),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      R => Q
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(7),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      R => Q
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(8),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      R => Q
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(9),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      R => Q
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXELECIDLE(0),
      Q => \pipe_stages_1.pipe_rx_elec_idle_q_reg\,
      R => Q
    );
\gt_rxvalid_q_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2000000AA00AA00"
    )
        port map (
      I0 => \gt_rxvalid_q_i_2__0_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0\,
      I2 => \gt_rxvalid_q_i_3__0_n_0\,
      I3 => gt_rxvalid_q_reg_0,
      I4 => \gt_rxvalid_q_i_5__0_n_0\,
      I5 => p_15_in,
      O => gt_rxvalid_q
    );
\gt_rxvalid_q_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => \pl_ltssm_state_q_reg[4]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I4 => \pl_ltssm_state_q_reg[5]\(0),
      I5 => \pl_ltssm_state_q_reg[5]\(1),
      O => \gt_rxvalid_q_i_2__0_n_0\
    );
\gt_rxvalid_q_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \gt_rxvalid_q_i_3__0_n_0\
    );
\gt_rxvalid_q_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      O => \gt_rxvalid_q_i_5__0_n_0\
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rxvalid_q,
      Q => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      R => Q
    );
\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_0_in,
      I1 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I2 => symbol_after_eios,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1)
    );
\reg_symbol_after_eios_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => reg_symbol_after_eios
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => reg_symbol_after_eios,
      Q => symbol_after_eios,
      R => Q
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_23 is
  port (
    \pipe_stages_1.pipe_rx_valid_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC;
    CLK_PCLK : in STD_LOGIC;
    gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    \pl_ltssm_state_q_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_23 : entity is "PCIeGen1x8If64_gt_rx_valid_filter_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_23;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_23 is
  signal \FSM_sequential_reg_state_eios_det[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_4__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_5__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_4__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_5__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : signal is "yes";
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal gt_rxvalid_q : STD_LOGIC;
  signal \gt_rxvalid_q_i_2__1_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_3__1_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_5__1_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_15_in : STD_LOGIC;
  signal \^pipe_stages_1.pipe_rx_data_q_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^pipe_stages_1.pipe_rx_valid_q_reg\ : STD_LOGIC;
  signal reg_state_eios_det119_out : STD_LOGIC;
  signal reg_symbol_after_eios : STD_LOGIC;
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_reg_state_eios_det[2]_i_5__1\ : label is "soft_lutpair2";
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[2]\ : label is "yes";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__1\ : label is "soft_lutpair2";
begin
  \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) <= \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0);
  \pipe_stages_1.pipe_rx_valid_q_reg\ <= \^pipe_stages_1.pipe_rx_valid_q_reg\;
\FSM_sequential_reg_state_eios_det[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF73FFF3FF7FFFFF"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      I5 => reg_state_eios_det119_out,
      O => \FSM_sequential_reg_state_eios_det[0]_i_1__1_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0010"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I3 => \FSM_sequential_reg_state_eios_det[1]_i_2__1_n_0\,
      I4 => reg_state_eios_det119_out,
      I5 => \FSM_sequential_reg_state_eios_det[1]_i_4__1_n_0\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_1__1_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[1]_i_2__1_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[1]_i_5__1_n_0\,
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I4 => \FSM_sequential_reg_state_eios_det[2]_i_5__1_n_0\,
      O => reg_state_eios_det119_out
    );
\FSM_sequential_reg_state_eios_det[1]_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_4__1_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      O => \FSM_sequential_reg_state_eios_det[1]_i_5__1_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03B00000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => \FSM_sequential_reg_state_eios_det[2]_i_1__1_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I3 => \FSM_sequential_reg_state_eios_det[2]_i_4__1_n_0\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      I5 => \FSM_sequential_reg_state_eios_det[2]_i_5__1_n_0\,
      O => p_15_in
    );
\FSM_sequential_reg_state_eios_det[2]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[2]_i_4__1_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_5__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      I3 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_5__1_n_0\
    );
\FSM_sequential_reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[0]_i_1__1_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      S => Q
    );
\FSM_sequential_reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[1]_i_1__1_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      R => Q
    );
\FSM_sequential_reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[2]_i_1__1_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      R => Q
    );
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rx_phy_status_wire_filter(0),
      Q => \pipe_stages_1.pipe_rx_phy_status_q_reg\,
      R => Q
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(0),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(0),
      R => Q
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(1),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(1),
      R => Q
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(2),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2),
      R => Q
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => Q
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(1),
      Q => p_0_in,
      R => Q
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(0),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      R => Q
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(10),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      R => Q
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(11),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      R => Q
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(12),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      R => Q
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(13),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      R => Q
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(14),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      R => Q
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(15),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      R => Q
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(1),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      R => Q
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(2),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      R => Q
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(3),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      R => Q
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(4),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      R => Q
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(5),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      R => Q
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(6),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      R => Q
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(7),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      R => Q
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(8),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      R => Q
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(9),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      R => Q
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXELECIDLE(0),
      Q => \pipe_stages_1.pipe_rx_elec_idle_q_reg\,
      R => Q
    );
\gt_rxvalid_q_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2000000AA00AA00"
    )
        port map (
      I0 => \gt_rxvalid_q_i_2__1_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0\,
      I2 => \gt_rxvalid_q_i_3__1_n_0\,
      I3 => gt_rxvalid_q_reg_0,
      I4 => \gt_rxvalid_q_i_5__1_n_0\,
      I5 => p_15_in,
      O => gt_rxvalid_q
    );
\gt_rxvalid_q_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => \pl_ltssm_state_q_reg[4]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I4 => \pl_ltssm_state_q_reg[5]\(0),
      I5 => \pl_ltssm_state_q_reg[5]\(1),
      O => \gt_rxvalid_q_i_2__1_n_0\
    );
\gt_rxvalid_q_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \gt_rxvalid_q_i_3__1_n_0\
    );
\gt_rxvalid_q_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      O => \gt_rxvalid_q_i_5__1_n_0\
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rxvalid_q,
      Q => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      R => Q
    );
\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_0_in,
      I1 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I2 => symbol_after_eios,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1)
    );
\reg_symbol_after_eios_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => reg_symbol_after_eios
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => reg_symbol_after_eios,
      Q => symbol_after_eios,
      R => Q
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_24 is
  port (
    \pipe_stages_1.pipe_rx_valid_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC;
    CLK_PCLK : in STD_LOGIC;
    gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    \pl_ltssm_state_q_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_24 : entity is "PCIeGen1x8If64_gt_rx_valid_filter_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_24;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_24 is
  signal \FSM_sequential_reg_state_eios_det[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_4__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_5__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_4__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_5__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : signal is "yes";
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal gt_rxvalid_q : STD_LOGIC;
  signal \gt_rxvalid_q_i_2__2_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_3__2_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_5__2_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_15_in : STD_LOGIC;
  signal \^pipe_stages_1.pipe_rx_data_q_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^pipe_stages_1.pipe_rx_valid_q_reg\ : STD_LOGIC;
  signal reg_state_eios_det119_out : STD_LOGIC;
  signal reg_symbol_after_eios : STD_LOGIC;
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_reg_state_eios_det[2]_i_5__2\ : label is "soft_lutpair3";
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[2]\ : label is "yes";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__2\ : label is "soft_lutpair3";
begin
  \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) <= \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0);
  \pipe_stages_1.pipe_rx_valid_q_reg\ <= \^pipe_stages_1.pipe_rx_valid_q_reg\;
\FSM_sequential_reg_state_eios_det[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF73FFF3FF7FFFFF"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      I5 => reg_state_eios_det119_out,
      O => \FSM_sequential_reg_state_eios_det[0]_i_1__2_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0010"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I3 => \FSM_sequential_reg_state_eios_det[1]_i_2__2_n_0\,
      I4 => reg_state_eios_det119_out,
      I5 => \FSM_sequential_reg_state_eios_det[1]_i_4__2_n_0\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_1__2_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[1]_i_2__2_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[1]_i_5__2_n_0\,
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I4 => \FSM_sequential_reg_state_eios_det[2]_i_5__2_n_0\,
      O => reg_state_eios_det119_out
    );
\FSM_sequential_reg_state_eios_det[1]_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_4__2_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      O => \FSM_sequential_reg_state_eios_det[1]_i_5__2_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03B00000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => \FSM_sequential_reg_state_eios_det[2]_i_1__2_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I3 => \FSM_sequential_reg_state_eios_det[2]_i_4__2_n_0\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      I5 => \FSM_sequential_reg_state_eios_det[2]_i_5__2_n_0\,
      O => p_15_in
    );
\FSM_sequential_reg_state_eios_det[2]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[2]_i_4__2_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_5__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      I3 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_5__2_n_0\
    );
\FSM_sequential_reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[0]_i_1__2_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      S => Q
    );
\FSM_sequential_reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[1]_i_1__2_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      R => Q
    );
\FSM_sequential_reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[2]_i_1__2_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      R => Q
    );
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rx_phy_status_wire_filter(0),
      Q => \pipe_stages_1.pipe_rx_phy_status_q_reg\,
      R => Q
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(0),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(0),
      R => Q
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(1),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(1),
      R => Q
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(2),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2),
      R => Q
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => Q
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(1),
      Q => p_0_in,
      R => Q
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(0),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      R => Q
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(10),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      R => Q
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(11),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      R => Q
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(12),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      R => Q
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(13),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      R => Q
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(14),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      R => Q
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(15),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      R => Q
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(1),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      R => Q
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(2),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      R => Q
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(3),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      R => Q
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(4),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      R => Q
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(5),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      R => Q
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(6),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      R => Q
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(7),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      R => Q
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(8),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      R => Q
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(9),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      R => Q
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXELECIDLE(0),
      Q => \pipe_stages_1.pipe_rx_elec_idle_q_reg\,
      R => Q
    );
\gt_rxvalid_q_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2000000AA00AA00"
    )
        port map (
      I0 => \gt_rxvalid_q_i_2__2_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0\,
      I2 => \gt_rxvalid_q_i_3__2_n_0\,
      I3 => gt_rxvalid_q_reg_0,
      I4 => \gt_rxvalid_q_i_5__2_n_0\,
      I5 => p_15_in,
      O => gt_rxvalid_q
    );
\gt_rxvalid_q_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => \pl_ltssm_state_q_reg[4]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I4 => \pl_ltssm_state_q_reg[5]\(0),
      I5 => \pl_ltssm_state_q_reg[5]\(1),
      O => \gt_rxvalid_q_i_2__2_n_0\
    );
\gt_rxvalid_q_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \gt_rxvalid_q_i_3__2_n_0\
    );
\gt_rxvalid_q_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      O => \gt_rxvalid_q_i_5__2_n_0\
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rxvalid_q,
      Q => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      R => Q
    );
\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_0_in,
      I1 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I2 => symbol_after_eios,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1)
    );
\reg_symbol_after_eios_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => reg_symbol_after_eios
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => reg_symbol_after_eios,
      Q => symbol_after_eios,
      R => Q
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_25 is
  port (
    \pipe_stages_1.pipe_rx_valid_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC;
    CLK_PCLK : in STD_LOGIC;
    gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    \pl_ltssm_state_q_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_25 : entity is "PCIeGen1x8If64_gt_rx_valid_filter_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_25;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_25 is
  signal \FSM_sequential_reg_state_eios_det[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_2__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_4__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_5__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_4__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_5__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : signal is "yes";
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal gt_rxvalid_q : STD_LOGIC;
  signal \gt_rxvalid_q_i_2__3_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_3__3_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_5__3_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_15_in : STD_LOGIC;
  signal \^pipe_stages_1.pipe_rx_data_q_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^pipe_stages_1.pipe_rx_valid_q_reg\ : STD_LOGIC;
  signal reg_state_eios_det119_out : STD_LOGIC;
  signal reg_symbol_after_eios : STD_LOGIC;
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_reg_state_eios_det[2]_i_5__3\ : label is "soft_lutpair4";
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[2]\ : label is "yes";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__3\ : label is "soft_lutpair4";
begin
  \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) <= \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0);
  \pipe_stages_1.pipe_rx_valid_q_reg\ <= \^pipe_stages_1.pipe_rx_valid_q_reg\;
\FSM_sequential_reg_state_eios_det[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF73FFF3FF7FFFFF"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      I5 => reg_state_eios_det119_out,
      O => \FSM_sequential_reg_state_eios_det[0]_i_1__3_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0004"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I3 => \FSM_sequential_reg_state_eios_det[1]_i_2__3_n_0\,
      I4 => reg_state_eios_det119_out,
      I5 => \FSM_sequential_reg_state_eios_det[1]_i_4__3_n_0\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_1__3_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[1]_i_2__3_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[1]_i_5__3_n_0\,
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I4 => \FSM_sequential_reg_state_eios_det[2]_i_5__3_n_0\,
      O => reg_state_eios_det119_out
    );
\FSM_sequential_reg_state_eios_det[1]_i_4__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_4__3_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      O => \FSM_sequential_reg_state_eios_det[1]_i_5__3_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03B00000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => \FSM_sequential_reg_state_eios_det[2]_i_1__3_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I3 => \FSM_sequential_reg_state_eios_det[2]_i_4__3_n_0\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      I5 => \FSM_sequential_reg_state_eios_det[2]_i_5__3_n_0\,
      O => p_15_in
    );
\FSM_sequential_reg_state_eios_det[2]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[2]_i_4__3_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_5__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      I3 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_5__3_n_0\
    );
\FSM_sequential_reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[0]_i_1__3_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      S => Q
    );
\FSM_sequential_reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[1]_i_1__3_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      R => Q
    );
\FSM_sequential_reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[2]_i_1__3_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      R => Q
    );
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rx_phy_status_wire_filter(0),
      Q => \pipe_stages_1.pipe_rx_phy_status_q_reg\,
      R => Q
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(0),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(0),
      R => Q
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(1),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(1),
      R => Q
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(2),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2),
      R => Q
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => Q
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(1),
      Q => p_0_in,
      R => Q
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(0),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      R => Q
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(10),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      R => Q
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(11),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      R => Q
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(12),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      R => Q
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(13),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      R => Q
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(14),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      R => Q
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(15),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      R => Q
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(1),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      R => Q
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(2),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      R => Q
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(3),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      R => Q
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(4),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      R => Q
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(5),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      R => Q
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(6),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      R => Q
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(7),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      R => Q
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(8),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      R => Q
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(9),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      R => Q
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXELECIDLE(0),
      Q => \pipe_stages_1.pipe_rx_elec_idle_q_reg\,
      R => Q
    );
\gt_rxvalid_q_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2000000AA00AA00"
    )
        port map (
      I0 => \gt_rxvalid_q_i_2__3_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0\,
      I2 => \gt_rxvalid_q_i_3__3_n_0\,
      I3 => gt_rxvalid_q_reg_0,
      I4 => \gt_rxvalid_q_i_5__3_n_0\,
      I5 => p_15_in,
      O => gt_rxvalid_q
    );
\gt_rxvalid_q_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => \pl_ltssm_state_q_reg[4]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I4 => \pl_ltssm_state_q_reg[5]\(0),
      I5 => \pl_ltssm_state_q_reg[5]\(1),
      O => \gt_rxvalid_q_i_2__3_n_0\
    );
\gt_rxvalid_q_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \gt_rxvalid_q_i_3__3_n_0\
    );
\gt_rxvalid_q_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      O => \gt_rxvalid_q_i_5__3_n_0\
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rxvalid_q,
      Q => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      R => Q
    );
\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_0_in,
      I1 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I2 => symbol_after_eios,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1)
    );
\reg_symbol_after_eios_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => reg_symbol_after_eios
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => reg_symbol_after_eios,
      Q => symbol_after_eios,
      R => Q
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_26 is
  port (
    \pipe_stages_1.pipe_rx_valid_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC;
    CLK_PCLK : in STD_LOGIC;
    gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    \pl_ltssm_state_q_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_26 : entity is "PCIeGen1x8If64_gt_rx_valid_filter_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_26;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_26 is
  signal \FSM_sequential_reg_state_eios_det[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_2__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_4__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_5__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_4__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_5__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : signal is "yes";
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal gt_rxvalid_q : STD_LOGIC;
  signal \gt_rxvalid_q_i_2__4_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_3__4_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_5__4_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_15_in : STD_LOGIC;
  signal \^pipe_stages_1.pipe_rx_data_q_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^pipe_stages_1.pipe_rx_valid_q_reg\ : STD_LOGIC;
  signal reg_state_eios_det119_out : STD_LOGIC;
  signal reg_symbol_after_eios : STD_LOGIC;
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_reg_state_eios_det[2]_i_5__4\ : label is "soft_lutpair5";
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[2]\ : label is "yes";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__4\ : label is "soft_lutpair5";
begin
  \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) <= \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0);
  \pipe_stages_1.pipe_rx_valid_q_reg\ <= \^pipe_stages_1.pipe_rx_valid_q_reg\;
\FSM_sequential_reg_state_eios_det[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF73FFF3FF7FFFFF"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      I5 => reg_state_eios_det119_out,
      O => \FSM_sequential_reg_state_eios_det[0]_i_1__4_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0004"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I3 => \FSM_sequential_reg_state_eios_det[1]_i_2__4_n_0\,
      I4 => reg_state_eios_det119_out,
      I5 => \FSM_sequential_reg_state_eios_det[1]_i_4__4_n_0\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_1__4_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[1]_i_2__4_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[1]_i_5__4_n_0\,
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I4 => \FSM_sequential_reg_state_eios_det[2]_i_5__4_n_0\,
      O => reg_state_eios_det119_out
    );
\FSM_sequential_reg_state_eios_det[1]_i_4__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_4__4_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      O => \FSM_sequential_reg_state_eios_det[1]_i_5__4_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03B00000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => \FSM_sequential_reg_state_eios_det[2]_i_1__4_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I3 => \FSM_sequential_reg_state_eios_det[2]_i_4__4_n_0\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      I5 => \FSM_sequential_reg_state_eios_det[2]_i_5__4_n_0\,
      O => p_15_in
    );
\FSM_sequential_reg_state_eios_det[2]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[2]_i_4__4_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_5__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      I3 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_5__4_n_0\
    );
\FSM_sequential_reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[0]_i_1__4_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      S => Q
    );
\FSM_sequential_reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[1]_i_1__4_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      R => Q
    );
\FSM_sequential_reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[2]_i_1__4_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      R => Q
    );
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rx_phy_status_wire_filter(0),
      Q => \pipe_stages_1.pipe_rx_phy_status_q_reg\,
      R => Q
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(0),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(0),
      R => Q
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(1),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(1),
      R => Q
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(2),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2),
      R => Q
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => Q
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(1),
      Q => p_0_in,
      R => Q
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(0),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      R => Q
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(10),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      R => Q
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(11),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      R => Q
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(12),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      R => Q
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(13),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      R => Q
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(14),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      R => Q
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(15),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      R => Q
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(1),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      R => Q
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(2),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      R => Q
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(3),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      R => Q
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(4),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      R => Q
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(5),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      R => Q
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(6),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      R => Q
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(7),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      R => Q
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(8),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      R => Q
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(9),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      R => Q
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXELECIDLE(0),
      Q => \pipe_stages_1.pipe_rx_elec_idle_q_reg\,
      R => Q
    );
\gt_rxvalid_q_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2000000AA00AA00"
    )
        port map (
      I0 => \gt_rxvalid_q_i_2__4_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0\,
      I2 => \gt_rxvalid_q_i_3__4_n_0\,
      I3 => gt_rxvalid_q_reg_0,
      I4 => \gt_rxvalid_q_i_5__4_n_0\,
      I5 => p_15_in,
      O => gt_rxvalid_q
    );
\gt_rxvalid_q_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => \pl_ltssm_state_q_reg[4]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I4 => \pl_ltssm_state_q_reg[5]\(0),
      I5 => \pl_ltssm_state_q_reg[5]\(1),
      O => \gt_rxvalid_q_i_2__4_n_0\
    );
\gt_rxvalid_q_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \gt_rxvalid_q_i_3__4_n_0\
    );
\gt_rxvalid_q_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      O => \gt_rxvalid_q_i_5__4_n_0\
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rxvalid_q,
      Q => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      R => Q
    );
\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_0_in,
      I1 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I2 => symbol_after_eios,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1)
    );
\reg_symbol_after_eios_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => reg_symbol_after_eios
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => reg_symbol_after_eios,
      Q => symbol_after_eios,
      R => Q
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_27 is
  port (
    \pipe_stages_1.pipe_rx_valid_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC;
    CLK_PCLK : in STD_LOGIC;
    gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    \pl_ltssm_state_q_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_27 : entity is "PCIeGen1x8If64_gt_rx_valid_filter_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_27;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_27 is
  signal \FSM_sequential_reg_state_eios_det[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_2__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_4__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_5__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_4__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_5__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : signal is "yes";
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal gt_rxvalid_q : STD_LOGIC;
  signal \gt_rxvalid_q_i_2__5_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_3__5_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_5__5_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_15_in : STD_LOGIC;
  signal \^pipe_stages_1.pipe_rx_data_q_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^pipe_stages_1.pipe_rx_valid_q_reg\ : STD_LOGIC;
  signal reg_state_eios_det119_out : STD_LOGIC;
  signal reg_symbol_after_eios : STD_LOGIC;
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_reg_state_eios_det[2]_i_5__5\ : label is "soft_lutpair6";
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[2]\ : label is "yes";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__5\ : label is "soft_lutpair6";
begin
  \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) <= \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0);
  \pipe_stages_1.pipe_rx_valid_q_reg\ <= \^pipe_stages_1.pipe_rx_valid_q_reg\;
\FSM_sequential_reg_state_eios_det[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF73FFF3FF7FFFFF"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      I5 => reg_state_eios_det119_out,
      O => \FSM_sequential_reg_state_eios_det[0]_i_1__5_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0010"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I3 => \FSM_sequential_reg_state_eios_det[1]_i_2__5_n_0\,
      I4 => reg_state_eios_det119_out,
      I5 => \FSM_sequential_reg_state_eios_det[1]_i_4__5_n_0\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_1__5_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[1]_i_2__5_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[1]_i_5__5_n_0\,
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I4 => \FSM_sequential_reg_state_eios_det[2]_i_5__5_n_0\,
      O => reg_state_eios_det119_out
    );
\FSM_sequential_reg_state_eios_det[1]_i_4__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_4__5_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      O => \FSM_sequential_reg_state_eios_det[1]_i_5__5_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03B00000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => \FSM_sequential_reg_state_eios_det[2]_i_1__5_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I3 => \FSM_sequential_reg_state_eios_det[2]_i_4__5_n_0\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      I5 => \FSM_sequential_reg_state_eios_det[2]_i_5__5_n_0\,
      O => p_15_in
    );
\FSM_sequential_reg_state_eios_det[2]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[2]_i_4__5_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_5__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      I3 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_5__5_n_0\
    );
\FSM_sequential_reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[0]_i_1__5_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      S => Q
    );
\FSM_sequential_reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[1]_i_1__5_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      R => Q
    );
\FSM_sequential_reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[2]_i_1__5_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      R => Q
    );
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rx_phy_status_wire_filter(0),
      Q => \pipe_stages_1.pipe_rx_phy_status_q_reg\,
      R => Q
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(0),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(0),
      R => Q
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(1),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(1),
      R => Q
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(2),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2),
      R => Q
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => Q
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(1),
      Q => p_0_in,
      R => Q
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(0),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      R => Q
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(10),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      R => Q
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(11),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      R => Q
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(12),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      R => Q
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(13),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      R => Q
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(14),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      R => Q
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(15),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      R => Q
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(1),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      R => Q
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(2),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      R => Q
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(3),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      R => Q
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(4),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      R => Q
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(5),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      R => Q
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(6),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      R => Q
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(7),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      R => Q
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(8),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      R => Q
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(9),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      R => Q
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXELECIDLE(0),
      Q => \pipe_stages_1.pipe_rx_elec_idle_q_reg\,
      R => Q
    );
\gt_rxvalid_q_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2000000AA00AA00"
    )
        port map (
      I0 => \gt_rxvalid_q_i_2__5_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0\,
      I2 => \gt_rxvalid_q_i_3__5_n_0\,
      I3 => gt_rxvalid_q_reg_0,
      I4 => \gt_rxvalid_q_i_5__5_n_0\,
      I5 => p_15_in,
      O => gt_rxvalid_q
    );
\gt_rxvalid_q_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => \pl_ltssm_state_q_reg[4]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I4 => \pl_ltssm_state_q_reg[5]\(0),
      I5 => \pl_ltssm_state_q_reg[5]\(1),
      O => \gt_rxvalid_q_i_2__5_n_0\
    );
\gt_rxvalid_q_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \gt_rxvalid_q_i_3__5_n_0\
    );
\gt_rxvalid_q_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      O => \gt_rxvalid_q_i_5__5_n_0\
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rxvalid_q,
      Q => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      R => Q
    );
\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_0_in,
      I1 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I2 => symbol_after_eios,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1)
    );
\reg_symbol_after_eios_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => reg_symbol_after_eios
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => reg_symbol_after_eios,
      Q => symbol_after_eios,
      R => Q
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_28 is
  port (
    \pipe_stages_1.pipe_rx_valid_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC;
    CLK_PCLK : in STD_LOGIC;
    gt_rx_phy_status_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    \pl_ltssm_state_q_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_RXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_RXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_28 : entity is "PCIeGen1x8If64_gt_rx_valid_filter_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_28;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_28 is
  signal \FSM_sequential_reg_state_eios_det[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_2__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_4__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[1]_i_5__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_4__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det[2]_i_5__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\ : signal is "yes";
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal gt_rxvalid_q : STD_LOGIC;
  signal \gt_rxvalid_q_i_2__6_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_3__6_n_0\ : STD_LOGIC;
  signal \gt_rxvalid_q_i_5__6_n_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_15_in : STD_LOGIC;
  signal \^pipe_stages_1.pipe_rx_data_q_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^pipe_stages_1.pipe_rx_valid_q_reg\ : STD_LOGIC;
  signal reg_state_eios_det119_out : STD_LOGIC;
  signal reg_symbol_after_eios : STD_LOGIC;
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_reg_state_eios_det[2]_i_5__6\ : label is "soft_lutpair7";
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_reg_state_eios_det_reg[2]\ : label is "yes";
  attribute SOFT_HLUTNM of \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__6\ : label is "soft_lutpair7";
begin
  \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) <= \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0);
  \pipe_stages_1.pipe_rx_valid_q_reg\ <= \^pipe_stages_1.pipe_rx_valid_q_reg\;
\FSM_sequential_reg_state_eios_det[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF73FFF3FF7FFFFF"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      I5 => reg_state_eios_det119_out,
      O => \FSM_sequential_reg_state_eios_det[0]_i_1__6_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF0004"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I3 => \FSM_sequential_reg_state_eios_det[1]_i_2__6_n_0\,
      I4 => reg_state_eios_det119_out,
      I5 => \FSM_sequential_reg_state_eios_det[1]_i_4__6_n_0\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_1__6_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[1]_i_2__6_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[1]_i_5__6_n_0\,
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I4 => \FSM_sequential_reg_state_eios_det[2]_i_5__6_n_0\,
      O => reg_state_eios_det119_out
    );
\FSM_sequential_reg_state_eios_det[1]_i_4__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \FSM_sequential_reg_state_eios_det[1]_i_4__6_n_0\
    );
\FSM_sequential_reg_state_eios_det[1]_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      O => \FSM_sequential_reg_state_eios_det[1]_i_5__6_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03B00000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => \FSM_sequential_reg_state_eios_det[2]_i_1__6_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      I3 => \FSM_sequential_reg_state_eios_det[2]_i_4__6_n_0\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000400"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      I5 => \FSM_sequential_reg_state_eios_det[2]_i_5__6_n_0\,
      O => p_15_in
    );
\FSM_sequential_reg_state_eios_det[2]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      I2 => p_0_in,
      I3 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      I4 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      I5 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      O => \FSM_sequential_reg_state_eios_det[2]_i_4__6_n_0\
    );
\FSM_sequential_reg_state_eios_det[2]_i_5__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      I1 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      I2 => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      I3 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \FSM_sequential_reg_state_eios_det[2]_i_5__6_n_0\
    );
\FSM_sequential_reg_state_eios_det_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[0]_i_1__6_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      S => Q
    );
\FSM_sequential_reg_state_eios_det_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[1]_i_1__6_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      R => Q
    );
\FSM_sequential_reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => \FSM_sequential_reg_state_eios_det[2]_i_1__6_n_0\,
      Q => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      R => Q
    );
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rx_phy_status_wire_filter(0),
      Q => \pipe_stages_1.pipe_rx_phy_status_q_reg\,
      R => Q
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(0),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(0),
      R => Q
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(1),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(1),
      R => Q
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => D(2),
      Q => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2),
      R => Q
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => Q
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATAK(1),
      Q => p_0_in,
      R => Q
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(0),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(0),
      R => Q
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(10),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(10),
      R => Q
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(11),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(11),
      R => Q
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(12),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(12),
      R => Q
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(13),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(13),
      R => Q
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(14),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(14),
      R => Q
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(15),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(15),
      R => Q
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(1),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(1),
      R => Q
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(2),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(2),
      R => Q
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(3),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(3),
      R => Q
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(4),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(4),
      R => Q
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(5),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(5),
      R => Q
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(6),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(6),
      R => Q
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(7),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(7),
      R => Q
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(8),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(8),
      R => Q
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXDATA(9),
      Q => \^pipe_stages_1.pipe_rx_data_q_reg[15]\(9),
      R => Q
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => PIPE_RXELECIDLE(0),
      Q => \pipe_stages_1.pipe_rx_elec_idle_q_reg\,
      R => Q
    );
\gt_rxvalid_q_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2000000AA00AA00"
    )
        port map (
      I0 => \gt_rxvalid_q_i_2__6_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0\,
      I2 => \gt_rxvalid_q_i_3__6_n_0\,
      I3 => gt_rxvalid_q_reg_0,
      I4 => \gt_rxvalid_q_i_5__6_n_0\,
      I5 => p_15_in,
      O => gt_rxvalid_q
    );
\gt_rxvalid_q_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFBF"
    )
        port map (
      I0 => \pl_ltssm_state_q_reg[4]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I4 => \pl_ltssm_state_q_reg[5]\(0),
      I5 => \pl_ltssm_state_q_reg[5]\(1),
      O => \gt_rxvalid_q_i_2__6_n_0\
    );
\gt_rxvalid_q_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      O => \gt_rxvalid_q_i_3__6_n_0\
    );
\gt_rxvalid_q_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EB"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      O => \gt_rxvalid_q_i_5__6_n_0\
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => gt_rxvalid_q,
      Q => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      R => Q
    );
\pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(0)
    );
\pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_0_in,
      I1 => \^pipe_stages_1.pipe_rx_valid_q_reg\,
      I2 => symbol_after_eios,
      O => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1)
    );
\reg_symbol_after_eios_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0\,
      I1 => \FSM_sequential_reg_state_eios_det_reg_n_0_[0]\,
      I2 => \FSM_sequential_reg_state_eios_det_reg_n_0_[1]\,
      I3 => \FSM_sequential_reg_state_eios_det_reg_n_0_[2]\,
      I4 => p_15_in,
      O => reg_symbol_after_eios
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK_PCLK,
      CE => '1',
      D => reg_symbol_after_eios,
      Q => symbol_after_eios,
      R => Q
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd is
  port (
    CPLLPD0 : out STD_LOGIC;
    CPLLRESET0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in20_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in18_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd : entity is "PCIeGen1x8If64_gtx_cpllpd_ovrd";
end PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd is
  signal cpllpd : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal cpllrst : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 ";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
\gtx_channel.gtxe2_channel_i_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllpd,
      I1 => rst_cpllpd,
      I2 => p_0_in20_in,
      O => CPLLPD0
    );
\gtx_channel.gtxe2_channel_i_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllrst,
      I1 => RST_CPLLRESET,
      I2 => p_0_in18_in,
      O => CPLLRESET0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_73 is
  port (
    CPLLPD0 : out STD_LOGIC;
    CPLLRESET0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in38_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in36_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_73 : entity is "PCIeGen1x8If64_gtx_cpllpd_ovrd";
end PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_73;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_73 is
  signal cpllpd : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal cpllrst : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 ";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
\gtx_channel.gtxe2_channel_i_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllpd,
      I1 => rst_cpllpd,
      I2 => p_0_in38_in,
      O => CPLLPD0
    );
\gtx_channel.gtxe2_channel_i_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllrst,
      I1 => RST_CPLLRESET,
      I2 => p_0_in36_in,
      O => CPLLRESET0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_75 is
  port (
    CPLLPD0 : out STD_LOGIC;
    CPLLRESET0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in49_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in47_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_75 : entity is "PCIeGen1x8If64_gtx_cpllpd_ovrd";
end PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_75;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_75 is
  signal cpllpd : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal cpllrst : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 ";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
\gtx_channel.gtxe2_channel_i_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllpd,
      I1 => rst_cpllpd,
      I2 => p_0_in49_in,
      O => CPLLPD0
    );
\gtx_channel.gtxe2_channel_i_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllrst,
      I1 => RST_CPLLRESET,
      I2 => p_0_in47_in,
      O => CPLLRESET0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_77 is
  port (
    CPLLPD0 : out STD_LOGIC;
    CPLLRESET0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in67_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in65_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_77 : entity is "PCIeGen1x8If64_gtx_cpllpd_ovrd";
end PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_77;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_77 is
  signal cpllpd : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal cpllrst : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 ";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
\gtx_channel.gtxe2_channel_i_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllpd,
      I1 => rst_cpllpd,
      I2 => p_0_in67_in,
      O => CPLLPD0
    );
\gtx_channel.gtxe2_channel_i_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllrst,
      I1 => RST_CPLLRESET,
      I2 => p_0_in65_in,
      O => CPLLRESET0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_79 is
  port (
    CPLLPD0 : out STD_LOGIC;
    CPLLRESET0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in77_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in75_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_79 : entity is "PCIeGen1x8If64_gtx_cpllpd_ovrd";
end PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_79;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_79 is
  signal cpllpd : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal cpllrst : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 ";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
\gtx_channel.gtxe2_channel_i_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllpd,
      I1 => rst_cpllpd,
      I2 => p_0_in77_in,
      O => CPLLPD0
    );
\gtx_channel.gtxe2_channel_i_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllrst,
      I1 => RST_CPLLRESET,
      I2 => p_0_in75_in,
      O => CPLLRESET0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_81 is
  port (
    CPLLPD0 : out STD_LOGIC;
    CPLLRESET0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in123_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in121_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_81 : entity is "PCIeGen1x8If64_gtx_cpllpd_ovrd";
end PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_81;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_81 is
  signal cpllpd : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal cpllrst : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 ";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
\gtx_channel.gtxe2_channel_i_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllpd,
      I1 => rst_cpllpd,
      I2 => p_0_in123_in,
      O => CPLLPD0
    );
\gtx_channel.gtxe2_channel_i_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllrst,
      I1 => RST_CPLLRESET,
      I2 => p_0_in121_in,
      O => CPLLRESET0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_83 is
  port (
    CPLLPD0 : out STD_LOGIC;
    CPLLRESET0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in95_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in93_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_83 : entity is "PCIeGen1x8If64_gtx_cpllpd_ovrd";
end PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_83;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_83 is
  signal cpllpd : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal cpllrst : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 ";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
\gtx_channel.gtxe2_channel_i_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllpd,
      I1 => rst_cpllpd,
      I2 => p_0_in95_in,
      O => CPLLPD0
    );
\gtx_channel.gtxe2_channel_i_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllrst,
      I1 => RST_CPLLRESET,
      I2 => p_0_in93_in,
      O => CPLLRESET0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_87 is
  port (
    CPLLPD0 : out STD_LOGIC;
    CPLLRESET0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in3_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in2_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_87 : entity is "PCIeGen1x8If64_gtx_cpllpd_ovrd";
end PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_87;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_87 is
  signal cpllpd : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal cpllrst : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 ";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '0',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4) => '1',
      A(3) => '1',
      A(2) => '1',
      A(1) => '1',
      A(0) => '1',
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
\gtx_channel.gtxe2_channel_i_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllpd,
      I1 => rst_cpllpd,
      I2 => p_0_in3_in,
      O => CPLLPD0
    );
\gtx_channel.gtxe2_channel_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllrst,
      I1 => RST_CPLLRESET,
      I2 => p_0_in2_in,
      O => CPLLRESET0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane is
  port (
    pipe_rx0_valid_o : out STD_LOGIC;
    pipe_rx0_chanisaligned_o : out STD_LOGIC;
    pipe_rx0_phy_status_o : out STD_LOGIC;
    pipe_rx0_elec_idle_o : out STD_LOGIC;
    PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    phy_rdy_n : in STD_LOGIC;
    pipe_rx0_valid : in STD_LOGIC;
    CLK : in STD_LOGIC;
    PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_q : in STD_LOGIC;
    gt_rxelecidle_q : in STD_LOGIC;
    pipe_rx0_polarity_i : in STD_LOGIC;
    pipe_tx0_compliance_i : in STD_LOGIC;
    pipe_tx0_elec_idle_i : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane : entity is "PCIeGen1x8If64_pcie_pipe_lane";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane is
begin
\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => PIPE_RXCHANISALIGNED(0),
      Q => pipe_rx0_chanisaligned_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(10),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(11),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(12),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(13),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(14),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(15),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(3),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(4),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(5),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(6),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(7),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(8),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(9),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rxelecidle_q,
      Q => pipe_rx0_elec_idle_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rx_phy_status_q,
      Q => pipe_rx0_phy_status_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx0_polarity_i,
      Q => PIPE_RXPOLARITY(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx0_valid,
      Q => pipe_rx0_valid_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(0),
      Q => PIPE_TXDATAK(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1),
      Q => PIPE_TXDATAK(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx0_compliance_i,
      Q => PIPE_TXCOMPLIANCE(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(0),
      Q => PIPE_TXDATA(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(10),
      Q => PIPE_TXDATA(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(11),
      Q => PIPE_TXDATA(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(12),
      Q => PIPE_TXDATA(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(13),
      Q => PIPE_TXDATA(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(14),
      Q => PIPE_TXDATA(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15),
      Q => PIPE_TXDATA(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(1),
      Q => PIPE_TXDATA(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(2),
      Q => PIPE_TXDATA(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(3),
      Q => PIPE_TXDATA(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(4),
      Q => PIPE_TXDATA(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(5),
      Q => PIPE_TXDATA(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(6),
      Q => PIPE_TXDATA(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(7),
      Q => PIPE_TXDATA(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(8),
      Q => PIPE_TXDATA(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(9),
      Q => PIPE_TXDATA(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx0_elec_idle_i,
      Q => PIPE_TXELECIDLE(0),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(0),
      Q => PIPE_POWERDOWN(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1),
      Q => PIPE_POWERDOWN(1),
      S => phy_rdy_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_0 is
  port (
    PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx1_valid_o : out STD_LOGIC;
    pipe_rx1_chanisaligned_o : out STD_LOGIC;
    pipe_rx1_phy_status_o : out STD_LOGIC;
    pipe_rx1_elec_idle_o : out STD_LOGIC;
    PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_rdy_n : in STD_LOGIC;
    pipe_rx1_polarity_i : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_tx1_compliance_i : in STD_LOGIC;
    pipe_tx1_elec_idle_i : in STD_LOGIC;
    pipe_rx1_valid : in STD_LOGIC;
    PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_q_reg : in STD_LOGIC;
    gt_rxelecidle_q_reg : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_0 : entity is "PCIeGen1x8If64_pcie_pipe_lane";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_0;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_0 is
begin
\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => PIPE_RXCHANISALIGNED(0),
      Q => pipe_rx1_chanisaligned_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(10),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(11),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(12),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(13),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(14),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(15),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(3),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(4),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(5),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(6),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(7),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(8),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(9),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rxelecidle_q_reg,
      Q => pipe_rx1_elec_idle_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rx_phy_status_q_reg,
      Q => pipe_rx1_phy_status_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx1_polarity_i,
      Q => PIPE_RXPOLARITY(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx1_valid,
      Q => pipe_rx1_valid_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(0),
      Q => PIPE_TXDATAK(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1),
      Q => PIPE_TXDATAK(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx1_compliance_i,
      Q => PIPE_TXCOMPLIANCE(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(0),
      Q => PIPE_TXDATA(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(10),
      Q => PIPE_TXDATA(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(11),
      Q => PIPE_TXDATA(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(12),
      Q => PIPE_TXDATA(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(13),
      Q => PIPE_TXDATA(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(14),
      Q => PIPE_TXDATA(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15),
      Q => PIPE_TXDATA(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(1),
      Q => PIPE_TXDATA(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(2),
      Q => PIPE_TXDATA(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(3),
      Q => PIPE_TXDATA(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(4),
      Q => PIPE_TXDATA(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(5),
      Q => PIPE_TXDATA(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(6),
      Q => PIPE_TXDATA(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(7),
      Q => PIPE_TXDATA(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(8),
      Q => PIPE_TXDATA(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(9),
      Q => PIPE_TXDATA(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx1_elec_idle_i,
      Q => PIPE_TXELECIDLE(0),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(0),
      Q => PIPE_POWERDOWN(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1),
      Q => PIPE_POWERDOWN(1),
      S => phy_rdy_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_1 is
  port (
    PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx2_valid_o : out STD_LOGIC;
    pipe_rx2_chanisaligned_o : out STD_LOGIC;
    pipe_rx2_phy_status_o : out STD_LOGIC;
    pipe_rx2_elec_idle_o : out STD_LOGIC;
    PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_rdy_n : in STD_LOGIC;
    pipe_rx2_polarity_i : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_tx2_compliance_i : in STD_LOGIC;
    pipe_tx2_elec_idle_i : in STD_LOGIC;
    pipe_rx2_valid : in STD_LOGIC;
    PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_q_reg : in STD_LOGIC;
    gt_rxelecidle_q_reg : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_1 : entity is "PCIeGen1x8If64_pcie_pipe_lane";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_1;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_1 is
begin
\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => PIPE_RXCHANISALIGNED(0),
      Q => pipe_rx2_chanisaligned_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(10),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(11),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(12),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(13),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(14),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(15),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(3),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(4),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(5),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(6),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(7),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(8),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(9),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rxelecidle_q_reg,
      Q => pipe_rx2_elec_idle_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rx_phy_status_q_reg,
      Q => pipe_rx2_phy_status_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx2_polarity_i,
      Q => PIPE_RXPOLARITY(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx2_valid,
      Q => pipe_rx2_valid_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(0),
      Q => PIPE_TXDATAK(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1),
      Q => PIPE_TXDATAK(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx2_compliance_i,
      Q => PIPE_TXCOMPLIANCE(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(0),
      Q => PIPE_TXDATA(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(10),
      Q => PIPE_TXDATA(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(11),
      Q => PIPE_TXDATA(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(12),
      Q => PIPE_TXDATA(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(13),
      Q => PIPE_TXDATA(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(14),
      Q => PIPE_TXDATA(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15),
      Q => PIPE_TXDATA(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(1),
      Q => PIPE_TXDATA(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(2),
      Q => PIPE_TXDATA(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(3),
      Q => PIPE_TXDATA(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(4),
      Q => PIPE_TXDATA(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(5),
      Q => PIPE_TXDATA(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(6),
      Q => PIPE_TXDATA(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(7),
      Q => PIPE_TXDATA(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(8),
      Q => PIPE_TXDATA(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(9),
      Q => PIPE_TXDATA(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx2_elec_idle_i,
      Q => PIPE_TXELECIDLE(0),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(0),
      Q => PIPE_POWERDOWN(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1),
      Q => PIPE_POWERDOWN(1),
      S => phy_rdy_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_2 is
  port (
    PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx3_valid_o : out STD_LOGIC;
    pipe_rx3_chanisaligned_o : out STD_LOGIC;
    pipe_rx3_phy_status_o : out STD_LOGIC;
    pipe_rx3_elec_idle_o : out STD_LOGIC;
    PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_rdy_n : in STD_LOGIC;
    pipe_rx3_polarity_i : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_tx3_compliance_i : in STD_LOGIC;
    pipe_tx3_elec_idle_i : in STD_LOGIC;
    pipe_rx3_valid : in STD_LOGIC;
    PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_q_reg : in STD_LOGIC;
    gt_rxelecidle_q_reg : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_2 : entity is "PCIeGen1x8If64_pcie_pipe_lane";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_2;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_2 is
begin
\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => PIPE_RXCHANISALIGNED(0),
      Q => pipe_rx3_chanisaligned_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(10),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(11),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(12),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(13),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(14),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(15),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(3),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(4),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(5),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(6),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(7),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(8),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(9),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rxelecidle_q_reg,
      Q => pipe_rx3_elec_idle_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rx_phy_status_q_reg,
      Q => pipe_rx3_phy_status_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx3_polarity_i,
      Q => PIPE_RXPOLARITY(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx3_valid,
      Q => pipe_rx3_valid_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(0),
      Q => PIPE_TXDATAK(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1),
      Q => PIPE_TXDATAK(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx3_compliance_i,
      Q => PIPE_TXCOMPLIANCE(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(0),
      Q => PIPE_TXDATA(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(10),
      Q => PIPE_TXDATA(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(11),
      Q => PIPE_TXDATA(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(12),
      Q => PIPE_TXDATA(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(13),
      Q => PIPE_TXDATA(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(14),
      Q => PIPE_TXDATA(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15),
      Q => PIPE_TXDATA(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(1),
      Q => PIPE_TXDATA(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(2),
      Q => PIPE_TXDATA(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(3),
      Q => PIPE_TXDATA(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(4),
      Q => PIPE_TXDATA(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(5),
      Q => PIPE_TXDATA(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(6),
      Q => PIPE_TXDATA(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(7),
      Q => PIPE_TXDATA(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(8),
      Q => PIPE_TXDATA(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(9),
      Q => PIPE_TXDATA(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx3_elec_idle_i,
      Q => PIPE_TXELECIDLE(0),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(0),
      Q => PIPE_POWERDOWN(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1),
      Q => PIPE_POWERDOWN(1),
      S => phy_rdy_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_3 is
  port (
    PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx4_valid_o : out STD_LOGIC;
    pipe_rx4_chanisaligned_o : out STD_LOGIC;
    pipe_rx4_phy_status_o : out STD_LOGIC;
    pipe_rx4_elec_idle_o : out STD_LOGIC;
    PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_rdy_n : in STD_LOGIC;
    pipe_rx4_polarity_i : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_tx4_compliance_i : in STD_LOGIC;
    pipe_tx4_elec_idle_i : in STD_LOGIC;
    pipe_rx4_valid : in STD_LOGIC;
    PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_q_reg : in STD_LOGIC;
    gt_rxelecidle_q_reg : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_3 : entity is "PCIeGen1x8If64_pcie_pipe_lane";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_3;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_3 is
begin
\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => PIPE_RXCHANISALIGNED(0),
      Q => pipe_rx4_chanisaligned_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(10),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(11),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(12),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(13),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(14),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(15),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(3),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(4),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(5),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(6),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(7),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(8),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(9),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rxelecidle_q_reg,
      Q => pipe_rx4_elec_idle_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rx_phy_status_q_reg,
      Q => pipe_rx4_phy_status_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx4_polarity_i,
      Q => PIPE_RXPOLARITY(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx4_valid,
      Q => pipe_rx4_valid_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(0),
      Q => PIPE_TXDATAK(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1),
      Q => PIPE_TXDATAK(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx4_compliance_i,
      Q => PIPE_TXCOMPLIANCE(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(0),
      Q => PIPE_TXDATA(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(10),
      Q => PIPE_TXDATA(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(11),
      Q => PIPE_TXDATA(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(12),
      Q => PIPE_TXDATA(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(13),
      Q => PIPE_TXDATA(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(14),
      Q => PIPE_TXDATA(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15),
      Q => PIPE_TXDATA(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(1),
      Q => PIPE_TXDATA(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(2),
      Q => PIPE_TXDATA(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(3),
      Q => PIPE_TXDATA(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(4),
      Q => PIPE_TXDATA(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(5),
      Q => PIPE_TXDATA(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(6),
      Q => PIPE_TXDATA(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(7),
      Q => PIPE_TXDATA(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(8),
      Q => PIPE_TXDATA(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(9),
      Q => PIPE_TXDATA(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx4_elec_idle_i,
      Q => PIPE_TXELECIDLE(0),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(0),
      Q => PIPE_POWERDOWN(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1),
      Q => PIPE_POWERDOWN(1),
      S => phy_rdy_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_4 is
  port (
    PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx5_valid_o : out STD_LOGIC;
    pipe_rx5_chanisaligned_o : out STD_LOGIC;
    pipe_rx5_phy_status_o : out STD_LOGIC;
    pipe_rx5_elec_idle_o : out STD_LOGIC;
    PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_rdy_n : in STD_LOGIC;
    pipe_rx5_polarity_i : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_tx5_compliance_i : in STD_LOGIC;
    pipe_tx5_elec_idle_i : in STD_LOGIC;
    pipe_rx5_valid : in STD_LOGIC;
    PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_q_reg : in STD_LOGIC;
    gt_rxelecidle_q_reg : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_4 : entity is "PCIeGen1x8If64_pcie_pipe_lane";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_4;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_4 is
begin
\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => PIPE_RXCHANISALIGNED(0),
      Q => pipe_rx5_chanisaligned_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(10),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(11),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(12),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(13),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(14),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(15),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(3),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(4),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(5),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(6),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(7),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(8),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(9),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rxelecidle_q_reg,
      Q => pipe_rx5_elec_idle_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rx_phy_status_q_reg,
      Q => pipe_rx5_phy_status_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx5_polarity_i,
      Q => PIPE_RXPOLARITY(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx5_valid,
      Q => pipe_rx5_valid_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(0),
      Q => PIPE_TXDATAK(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1),
      Q => PIPE_TXDATAK(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx5_compliance_i,
      Q => PIPE_TXCOMPLIANCE(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(0),
      Q => PIPE_TXDATA(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(10),
      Q => PIPE_TXDATA(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(11),
      Q => PIPE_TXDATA(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(12),
      Q => PIPE_TXDATA(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(13),
      Q => PIPE_TXDATA(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(14),
      Q => PIPE_TXDATA(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15),
      Q => PIPE_TXDATA(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(1),
      Q => PIPE_TXDATA(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(2),
      Q => PIPE_TXDATA(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(3),
      Q => PIPE_TXDATA(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(4),
      Q => PIPE_TXDATA(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(5),
      Q => PIPE_TXDATA(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(6),
      Q => PIPE_TXDATA(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(7),
      Q => PIPE_TXDATA(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(8),
      Q => PIPE_TXDATA(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(9),
      Q => PIPE_TXDATA(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx5_elec_idle_i,
      Q => PIPE_TXELECIDLE(0),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(0),
      Q => PIPE_POWERDOWN(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1),
      Q => PIPE_POWERDOWN(1),
      S => phy_rdy_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_5 is
  port (
    PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx6_valid_o : out STD_LOGIC;
    pipe_rx6_chanisaligned_o : out STD_LOGIC;
    pipe_rx6_phy_status_o : out STD_LOGIC;
    pipe_rx6_elec_idle_o : out STD_LOGIC;
    PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_rdy_n : in STD_LOGIC;
    pipe_rx6_polarity_i : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_tx6_compliance_i : in STD_LOGIC;
    pipe_tx6_elec_idle_i : in STD_LOGIC;
    pipe_rx6_valid : in STD_LOGIC;
    PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_q_reg : in STD_LOGIC;
    gt_rxelecidle_q_reg : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_5 : entity is "PCIeGen1x8If64_pcie_pipe_lane";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_5;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_5 is
begin
\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => PIPE_RXCHANISALIGNED(0),
      Q => pipe_rx6_chanisaligned_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(10),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(11),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(12),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(13),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(14),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(15),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(3),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(4),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(5),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(6),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(7),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(8),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(9),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rxelecidle_q_reg,
      Q => pipe_rx6_elec_idle_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rx_phy_status_q_reg,
      Q => pipe_rx6_phy_status_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx6_polarity_i,
      Q => PIPE_RXPOLARITY(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx6_valid,
      Q => pipe_rx6_valid_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(0),
      Q => PIPE_TXDATAK(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1),
      Q => PIPE_TXDATAK(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx6_compliance_i,
      Q => PIPE_TXCOMPLIANCE(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(0),
      Q => PIPE_TXDATA(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(10),
      Q => PIPE_TXDATA(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(11),
      Q => PIPE_TXDATA(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(12),
      Q => PIPE_TXDATA(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(13),
      Q => PIPE_TXDATA(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(14),
      Q => PIPE_TXDATA(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15),
      Q => PIPE_TXDATA(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(1),
      Q => PIPE_TXDATA(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(2),
      Q => PIPE_TXDATA(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(3),
      Q => PIPE_TXDATA(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(4),
      Q => PIPE_TXDATA(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(5),
      Q => PIPE_TXDATA(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(6),
      Q => PIPE_TXDATA(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(7),
      Q => PIPE_TXDATA(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(8),
      Q => PIPE_TXDATA(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(9),
      Q => PIPE_TXDATA(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx6_elec_idle_i,
      Q => PIPE_TXELECIDLE(0),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(0),
      Q => PIPE_POWERDOWN(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1),
      Q => PIPE_POWERDOWN(1),
      S => phy_rdy_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_6 is
  port (
    PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rx7_valid_o : out STD_LOGIC;
    pipe_rx7_chanisaligned_o : out STD_LOGIC;
    pipe_rx7_phy_status_o : out STD_LOGIC;
    pipe_rx7_elec_idle_o : out STD_LOGIC;
    PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_TXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_rdy_n : in STD_LOGIC;
    pipe_rx7_polarity_i : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_tx7_compliance_i : in STD_LOGIC;
    pipe_tx7_elec_idle_i : in STD_LOGIC;
    pipe_rx7_valid : in STD_LOGIC;
    PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_q_reg : in STD_LOGIC;
    gt_rxelecidle_q_reg : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_6 : entity is "PCIeGen1x8If64_pcie_pipe_lane";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_6;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_6 is
begin
\pipe_stages_1.pipe_rx_chanisaligned_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => PIPE_RXCHANISALIGNED(0),
      Q => pipe_rx7_chanisaligned_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(10),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(11),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(12),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(13),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(14),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(15),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(3),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(4),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(5),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(6),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(7),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(8),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rxdata_q_reg[15]\(9),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_elec_idle_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rxelecidle_q_reg,
      Q => pipe_rx7_elec_idle_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_phy_status_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gt_rx_phy_status_q_reg,
      Q => pipe_rx7_phy_status_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_polarity_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx7_polarity_i,
      Q => PIPE_RXPOLARITY(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(0),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(1),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \gt_rx_status_q_reg[2]\(2),
      Q => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_rx_valid_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_rx7_valid,
      Q => pipe_rx7_valid_o,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(0),
      Q => PIPE_TXDATAK(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_char_is_k_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1),
      Q => PIPE_TXDATAK(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_compliance_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx7_compliance_i,
      Q => PIPE_TXCOMPLIANCE(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(0),
      Q => PIPE_TXDATA(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(10),
      Q => PIPE_TXDATA(10),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(11),
      Q => PIPE_TXDATA(11),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(12),
      Q => PIPE_TXDATA(12),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(13),
      Q => PIPE_TXDATA(13),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(14),
      Q => PIPE_TXDATA(14),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15),
      Q => PIPE_TXDATA(15),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(1),
      Q => PIPE_TXDATA(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(2),
      Q => PIPE_TXDATA(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(3),
      Q => PIPE_TXDATA(3),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(4),
      Q => PIPE_TXDATA(4),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(5),
      Q => PIPE_TXDATA(5),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(6),
      Q => PIPE_TXDATA(6),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(7),
      Q => PIPE_TXDATA(7),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(8),
      Q => PIPE_TXDATA(8),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_data_q_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(9),
      Q => PIPE_TXDATA(9),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_elec_idle_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx7_elec_idle_i,
      Q => PIPE_TXELECIDLE(0),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(0),
      Q => PIPE_POWERDOWN(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_powerdown_q_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1),
      Q => PIPE_POWERDOWN(1),
      S => phy_rdy_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_misc is
  port (
    pipe_tx_rcvr_det : out STD_LOGIC;
    \rate_reg1_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDEEMPH : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    \cplllock_reg1_reg[2]\ : out STD_LOGIC;
    \cplllock_reg1_reg[6]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cplllock_reg1_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TXMARGIN : out STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXMARGIN : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_rdy_n : in STD_LOGIC;
    pipe_tx_rcvr_det_i : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_tx_rate_i : in STD_LOGIC;
    pipe_tx_deemph_i : in STD_LOGIC;
    pipe_tx_margin : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_misc : entity is "PCIeGen1x8If64_pcie_pipe_misc";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_misc;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_misc is
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_deemph_q_reg\ : label is "pipe_stages_1.pipe_tx_deemph_q_reg";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_deemph_q_reg_rep\ : label is "pipe_stages_1.pipe_tx_deemph_q_reg";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_deemph_q_reg_rep__0\ : label is "pipe_stages_1.pipe_tx_deemph_q_reg";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_deemph_q_reg_rep__1\ : label is "pipe_stages_1.pipe_tx_deemph_q_reg";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[0]\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[0]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[0]_rep\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[0]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[0]_rep__0\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[0]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[0]_rep__1\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[0]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[1]\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[1]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[1]_rep\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[1]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[1]_rep__0\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[1]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[1]_rep__1\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[1]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[2]\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[2]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[2]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep__0\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[2]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep__1\ : label is "pipe_stages_1.pipe_tx_margin_q_reg[2]";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_rcvr_det_q_reg\ : label is "pipe_stages_1.pipe_tx_rcvr_det_q_reg";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\ : label is "pipe_stages_1.pipe_tx_rcvr_det_q_reg";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\ : label is "pipe_stages_1.pipe_tx_rcvr_det_q_reg";
  attribute ORIG_CELL_NAME of \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__1\ : label is "pipe_stages_1.pipe_tx_rcvr_det_q_reg";
begin
\pipe_stages_1.pipe_tx_deemph_q_reg\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_deemph_i,
      Q => PIPE_TXDEEMPH(0),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_deemph_q_reg_rep\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_deemph_i,
      Q => PIPE_TXDEEMPH(1),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_deemph_q_reg_rep__0\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_deemph_i,
      Q => PIPE_TXDEEMPH(2),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_deemph_q_reg_rep__1\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_deemph_i,
      Q => PIPE_TXDEEMPH(3),
      S => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(0),
      Q => Q(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[0]_rep\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(0),
      Q => \cplllock_reg1_reg[3]_0\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[0]_rep__0\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(0),
      Q => TXMARGIN(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[0]_rep__1\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(0),
      Q => PIPE_TXMARGIN(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(1),
      Q => Q(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[1]_rep\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(1),
      Q => \cplllock_reg1_reg[3]_0\(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[1]_rep__0\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(1),
      Q => TXMARGIN(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[1]_rep__1\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(1),
      Q => PIPE_TXMARGIN(1),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(2),
      Q => Q(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(2),
      Q => \cplllock_reg1_reg[3]_0\(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep__0\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(2),
      Q => TXMARGIN(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep__1\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_margin(2),
      Q => PIPE_TXMARGIN(2),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_rate_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_rate_i,
      Q => \rate_reg1_reg[0]\(0),
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_rcvr_det_q_reg\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_rcvr_det_i,
      Q => pipe_tx_rcvr_det,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_rcvr_det_i,
      Q => \cplllock_reg1_reg[3]\,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_rcvr_det_i,
      Q => \cplllock_reg1_reg[2]\,
      R => phy_rdy_n
    );
\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__1\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_rcvr_det_i,
      Q => \cplllock_reg1_reg[6]\,
      R => phy_rdy_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_clock is
  port (
    CLK_MMCM_LOCK : out STD_LOGIC;
    CLK_PCLK : out STD_LOGIC;
    CLK_DCLK : out STD_LOGIC;
    CLK_USERCLK1 : out STD_LOGIC;
    pipe_txoutclk_out : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 7 downto 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 7 downto 0 );
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_mmcm_rst_n : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_clock : entity is "PCIeGen1x8If64_pipe_clock";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_clock;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_clock is
  signal \^clk_pclk\ : STD_LOGIC;
  signal clk_125mhz : STD_LOGIC;
  signal clk_250mhz : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal mmcm_fb : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC;
  signal \pclk_i1_bufgctrl.pclk_i1_i_1_n_0\ : STD_LOGIC;
  signal pclk_sel : STD_LOGIC;
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of pclk_sel : signal is std.standard.true;
  signal pclk_sel0_out : STD_LOGIC;
  signal \pclk_sel_i_2__7_n_0\ : STD_LOGIC;
  signal pclk_sel_i_3_n_0 : STD_LOGIC;
  signal pclk_sel_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pclk_sel_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pclk_sel_slave_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal pclk_sel_slave_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal refclk : STD_LOGIC;
  signal userclk1 : STD_LOGIC;
  signal NLW_mmcm_i_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT0B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT1B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT2B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT3_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT3B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT4_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT5_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT6_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_DRDY_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_PSDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute box_type : string;
  attribute box_type of \dclk_i_bufg.dclk_i\ : label is "PRIMITIVE";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute box_type of mmcm_i : label is "PRIMITIVE";
  attribute box_type of \pclk_i1_bufgctrl.pclk_i1\ : label is "PRIMITIVE";
  attribute DONT_TOUCH of pclk_sel_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \pclk_sel_slave_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[7]\ : label is "yes";
  attribute box_type of \txoutclk_i.txoutclk_i\ : label is "PRIMITIVE";
  attribute box_type of \userclk1_i1.usrclk1_i1\ : label is "PRIMITIVE";
begin
  CLK_PCLK <= \^clk_pclk\;
\dclk_i_bufg.dclk_i\: unisim.vcomponents.BUFG
     port map (
      I => clk_125mhz,
      O => CLK_DCLK
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => rate_gen3(0),
      Q => gen3_reg1,
      R => \p_0_in__0\
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => \p_0_in__0\
    );
mmcm_i: unisim.vcomponents.MMCME2_ADV
    generic map(
      BANDWIDTH => "OPTIMIZED",
      CLKFBOUT_MULT_F => 10.000000,
      CLKFBOUT_PHASE => 0.000000,
      CLKFBOUT_USE_FINE_PS => false,
      CLKIN1_PERIOD => 10.000000,
      CLKIN2_PERIOD => 0.000000,
      CLKOUT0_DIVIDE_F => 8.000000,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT0_USE_FINE_PS => false,
      CLKOUT1_DIVIDE => 4,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUT1_USE_FINE_PS => false,
      CLKOUT2_DIVIDE => 4,
      CLKOUT2_DUTY_CYCLE => 0.500000,
      CLKOUT2_PHASE => 0.000000,
      CLKOUT2_USE_FINE_PS => false,
      CLKOUT3_DIVIDE => 4,
      CLKOUT3_DUTY_CYCLE => 0.500000,
      CLKOUT3_PHASE => 0.000000,
      CLKOUT3_USE_FINE_PS => false,
      CLKOUT4_CASCADE => false,
      CLKOUT4_DIVIDE => 20,
      CLKOUT4_DUTY_CYCLE => 0.500000,
      CLKOUT4_PHASE => 0.000000,
      CLKOUT4_USE_FINE_PS => false,
      CLKOUT5_DIVIDE => 1,
      CLKOUT5_DUTY_CYCLE => 0.500000,
      CLKOUT5_PHASE => 0.000000,
      CLKOUT5_USE_FINE_PS => false,
      CLKOUT6_DIVIDE => 1,
      CLKOUT6_DUTY_CYCLE => 0.500000,
      CLKOUT6_PHASE => 0.000000,
      CLKOUT6_USE_FINE_PS => false,
      COMPENSATION => "INTERNAL",
      DIVCLK_DIVIDE => 1,
      IS_CLKINSEL_INVERTED => '0',
      IS_PSEN_INVERTED => '0',
      IS_PSINCDEC_INVERTED => '0',
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REF_JITTER1 => 0.010000,
      REF_JITTER2 => 0.010000,
      SS_EN => "FALSE",
      SS_MODE => "CENTER_HIGH",
      SS_MOD_PERIOD => 10000,
      STARTUP_WAIT => false
    )
        port map (
      CLKFBIN => mmcm_fb,
      CLKFBOUT => mmcm_fb,
      CLKFBOUTB => NLW_mmcm_i_CLKFBOUTB_UNCONNECTED,
      CLKFBSTOPPED => NLW_mmcm_i_CLKFBSTOPPED_UNCONNECTED,
      CLKIN1 => refclk,
      CLKIN2 => '0',
      CLKINSEL => '1',
      CLKINSTOPPED => NLW_mmcm_i_CLKINSTOPPED_UNCONNECTED,
      CLKOUT0 => clk_125mhz,
      CLKOUT0B => NLW_mmcm_i_CLKOUT0B_UNCONNECTED,
      CLKOUT1 => clk_250mhz,
      CLKOUT1B => NLW_mmcm_i_CLKOUT1B_UNCONNECTED,
      CLKOUT2 => userclk1,
      CLKOUT2B => NLW_mmcm_i_CLKOUT2B_UNCONNECTED,
      CLKOUT3 => NLW_mmcm_i_CLKOUT3_UNCONNECTED,
      CLKOUT3B => NLW_mmcm_i_CLKOUT3B_UNCONNECTED,
      CLKOUT4 => NLW_mmcm_i_CLKOUT4_UNCONNECTED,
      CLKOUT5 => NLW_mmcm_i_CLKOUT5_UNCONNECTED,
      CLKOUT6 => NLW_mmcm_i_CLKOUT6_UNCONNECTED,
      DADDR(6) => '0',
      DADDR(5) => '0',
      DADDR(4) => '0',
      DADDR(3) => '0',
      DADDR(2) => '0',
      DADDR(1) => '0',
      DADDR(0) => '0',
      DCLK => '0',
      DEN => '0',
      DI(15) => '0',
      DI(14) => '0',
      DI(13) => '0',
      DI(12) => '0',
      DI(11) => '0',
      DI(10) => '0',
      DI(9) => '0',
      DI(8) => '0',
      DI(7) => '0',
      DI(6) => '0',
      DI(5) => '0',
      DI(4) => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      DO(15 downto 0) => NLW_mmcm_i_DO_UNCONNECTED(15 downto 0),
      DRDY => NLW_mmcm_i_DRDY_UNCONNECTED,
      DWE => '0',
      LOCKED => CLK_MMCM_LOCK,
      PSCLK => '0',
      PSDONE => NLW_mmcm_i_PSDONE_UNCONNECTED,
      PSEN => '0',
      PSINCDEC => '0',
      PWRDWN => '0',
      RST => \p_0_in__0\
    );
mmcm_i_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pipe_mmcm_rst_n,
      O => \p_0_in__0\
    );
\pclk_i1_bufgctrl.pclk_i1\: unisim.vcomponents.BUFGCTRL
    generic map(
      INIT_OUT => 0,
      IS_CE0_INVERTED => '0',
      IS_CE1_INVERTED => '0',
      IS_I0_INVERTED => '0',
      IS_I1_INVERTED => '0',
      IS_IGNORE0_INVERTED => '0',
      IS_IGNORE1_INVERTED => '0',
      IS_S0_INVERTED => '0',
      IS_S1_INVERTED => '0',
      PRESELECT_I0 => false,
      PRESELECT_I1 => false
    )
        port map (
      CE0 => '1',
      CE1 => '1',
      I0 => clk_125mhz,
      I1 => clk_250mhz,
      IGNORE0 => '0',
      IGNORE1 => '0',
      O => \^clk_pclk\,
      S0 => \pclk_i1_bufgctrl.pclk_i1_i_1_n_0\,
      S1 => pclk_sel
    );
\pclk_i1_bufgctrl.pclk_i1_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pclk_sel,
      O => \pclk_i1_bufgctrl.pclk_i1_i_1_n_0\
    );
pclk_sel_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF80FC8000000000"
    )
        port map (
      I0 => \pclk_sel_i_2__7_n_0\,
      I1 => pclk_sel_reg2(3),
      I2 => pclk_sel_reg2(2),
      I3 => pclk_sel,
      I4 => pclk_sel_i_3_n_0,
      I5 => pipe_mmcm_rst_n,
      O => pclk_sel0_out
    );
\pclk_sel_i_2__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => pclk_sel_reg2(5),
      I1 => pclk_sel_reg2(4),
      I2 => pclk_sel_reg2(6),
      I3 => pclk_sel_reg2(7),
      I4 => pclk_sel_reg2(0),
      I5 => pclk_sel_reg2(1),
      O => \pclk_sel_i_2__7_n_0\
    );
pclk_sel_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => pclk_sel_reg2(5),
      I1 => pclk_sel_reg2(4),
      I2 => pclk_sel_reg2(6),
      I3 => pclk_sel_reg2(7),
      I4 => pclk_sel_reg2(0),
      I5 => pclk_sel_reg2(1),
      O => pclk_sel_i_3_n_0
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel0_out,
      Q => pclk_sel,
      R => '0'
    );
\pclk_sel_reg1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => D(0),
      Q => pclk_sel_reg1(0),
      R => \p_0_in__0\
    );
\pclk_sel_reg1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => D(1),
      Q => pclk_sel_reg1(1),
      R => \p_0_in__0\
    );
\pclk_sel_reg1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => D(2),
      Q => pclk_sel_reg1(2),
      R => \p_0_in__0\
    );
\pclk_sel_reg1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => D(3),
      Q => pclk_sel_reg1(3),
      R => \p_0_in__0\
    );
\pclk_sel_reg1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => D(4),
      Q => pclk_sel_reg1(4),
      R => \p_0_in__0\
    );
\pclk_sel_reg1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => D(5),
      Q => pclk_sel_reg1(5),
      R => \p_0_in__0\
    );
\pclk_sel_reg1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => D(6),
      Q => pclk_sel_reg1(6),
      R => \p_0_in__0\
    );
\pclk_sel_reg1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => D(7),
      Q => pclk_sel_reg1(7),
      R => \p_0_in__0\
    );
\pclk_sel_reg2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_reg1(0),
      Q => pclk_sel_reg2(0),
      R => \p_0_in__0\
    );
\pclk_sel_reg2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_reg1(1),
      Q => pclk_sel_reg2(1),
      R => \p_0_in__0\
    );
\pclk_sel_reg2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_reg1(2),
      Q => pclk_sel_reg2(2),
      R => \p_0_in__0\
    );
\pclk_sel_reg2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_reg1(3),
      Q => pclk_sel_reg2(3),
      R => \p_0_in__0\
    );
\pclk_sel_reg2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_reg1(4),
      Q => pclk_sel_reg2(4),
      R => \p_0_in__0\
    );
\pclk_sel_reg2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_reg1(5),
      Q => pclk_sel_reg2(5),
      R => \p_0_in__0\
    );
\pclk_sel_reg2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_reg1(6),
      Q => pclk_sel_reg2(6),
      R => \p_0_in__0\
    );
\pclk_sel_reg2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_reg1(7),
      Q => pclk_sel_reg2(7),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => int_pclk_sel_slave(0),
      Q => pclk_sel_slave_reg1(0),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => int_pclk_sel_slave(1),
      Q => pclk_sel_slave_reg1(1),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => int_pclk_sel_slave(2),
      Q => pclk_sel_slave_reg1(2),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => int_pclk_sel_slave(3),
      Q => pclk_sel_slave_reg1(3),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => int_pclk_sel_slave(4),
      Q => pclk_sel_slave_reg1(4),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => int_pclk_sel_slave(5),
      Q => pclk_sel_slave_reg1(5),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => int_pclk_sel_slave(6),
      Q => pclk_sel_slave_reg1(6),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => int_pclk_sel_slave(7),
      Q => pclk_sel_slave_reg1(7),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_slave_reg1(0),
      Q => pclk_sel_slave_reg2(0),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_slave_reg1(1),
      Q => pclk_sel_slave_reg2(1),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_slave_reg1(2),
      Q => pclk_sel_slave_reg2(2),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_slave_reg1(3),
      Q => pclk_sel_slave_reg2(3),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_slave_reg1(4),
      Q => pclk_sel_slave_reg2(4),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_slave_reg1(5),
      Q => pclk_sel_slave_reg2(5),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_slave_reg1(6),
      Q => pclk_sel_slave_reg2(6),
      R => \p_0_in__0\
    );
\pclk_sel_slave_reg2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      D => pclk_sel_slave_reg1(7),
      Q => pclk_sel_slave_reg2(7),
      R => \p_0_in__0\
    );
\txoutclk_i.txoutclk_i\: unisim.vcomponents.BUFG
     port map (
      I => pipe_txoutclk_out,
      O => refclk
    );
\userclk1_i1.usrclk1_i1\: unisim.vcomponents.BUFG
     port map (
      I => userclk1,
      O => CLK_USERCLK1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp is
  port (
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \cplllock_reg1_reg[0]\ : out STD_LOGIC;
    \cplllock_reg1_reg[0]_0\ : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_DONE : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 );
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_X16X20_MODE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    ext_ch_gt_drprdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DRP_X16 : in STD_LOGIC;
    ext_ch_gt_drpdo : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_GTXRESET : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp : entity is "PCIeGen1x8If64_pipe_drp";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \addr_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \addr_reg[1]_i_1_n_0\ : STD_LOGIC;
  signal \addr_reg[2]_i_1_n_0\ : STD_LOGIC;
  signal \addr_reg[3]_i_1_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \addr_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \addr_reg[6]_i_1_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal data15 : STD_LOGIC_VECTOR ( 7 to 7 );
  signal data4 : STD_LOGIC;
  signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_5_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_6_n_0\ : STD_LOGIC;
  signal \di_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_5_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_6_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_7_n_0\ : STD_LOGIC;
  signal \di_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_5_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_6_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_5_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_5_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_6_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_7_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_8_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[9]\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal done_i_1_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm[0]_i_3__0_n_0\ : STD_LOGIC;
  signal gtxreset_reg1 : STD_LOGIC;
  signal gtxreset_reg2 : STD_LOGIC;
  signal index : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \index[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \index[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \index[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \index[3]_i_1_n_0\ : STD_LOGIC;
  signal \index[3]_i_2_n_0\ : STD_LOGIC;
  signal \index[4]_i_1_n_0\ : STD_LOGIC;
  signal \index[4]_i_2_n_0\ : STD_LOGIC;
  signal \index[4]_i_3_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal mode : STD_LOGIC;
  signal mode_i_1_n_0 : STD_LOGIC;
  signal mode_i_2_n_0 : STD_LOGIC;
  signal \mode_i_3__1_n_0\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rdy_reg1 : STD_LOGIC;
  signal rdy_reg2 : STD_LOGIC;
  signal start_reg1 : STD_LOGIC;
  signal start_reg2 : STD_LOGIC;
  signal x16_reg1 : STD_LOGIC;
  signal x16_reg2 : STD_LOGIC;
  signal x16x20_mode_reg1 : STD_LOGIC;
  signal x16x20_mode_reg2 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \di_reg[0]_i_5\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \di_reg[0]_i_6\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \di_reg[14]_i_2\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \di_reg[3]_i_4\ : label is "soft_lutpair15";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \fsm[0]_i_2\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \gt_ch_drp_rdy[0]_INST_0\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_47__3\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_50\ : label is "soft_lutpair8";
  attribute ASYNC_REG of gtxreset_reg1_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg1_reg : label is "yes";
  attribute ASYNC_REG of gtxreset_reg2_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \index[0]_i_1__1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \index[1]_i_1__1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \index[2]_i_1__1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \index[4]_i_3\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \mode_i_3__1\ : label is "soft_lutpair10";
  attribute ASYNC_REG of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute ASYNC_REG of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute ASYNC_REG of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg2_reg : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\addr_reg[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1471357514713564"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2_n_0\,
      O => \addr_reg[0]_i_1_n_0\
    );
\addr_reg[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404050500F0F0500"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[1]_i_1_n_0\
    );
\addr_reg[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"051005105A055A00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(2),
      I4 => mode,
      I5 => index(1),
      O => \addr_reg[2]_i_1_n_0\
    );
\addr_reg[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5767576753275326"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => \addr_reg[4]_i_2_n_0\,
      I5 => index(0),
      O => \addr_reg[3]_i_1_n_0\
    );
\addr_reg[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FCCFFF01"
    )
        port map (
      I0 => \addr_reg[4]_i_2_n_0\,
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => index(4),
      O => \addr_reg[4]_i_1_n_0\
    );
\addr_reg[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      O => \addr_reg[4]_i_2_n_0\
    );
\addr_reg[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001A1A0F0F0F0A"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[5]_i_1_n_0\
    );
\addr_reg[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011545554"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => mode,
      I3 => index(3),
      I4 => index(0),
      I5 => index(4),
      O => \addr_reg[6]_i_1_n_0\
    );
\addr_reg[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5422262254222633"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2_n_0\,
      O => \addr_reg[7]_i_1_n_0\
    );
\addr_reg[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CE"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      I2 => index(0),
      O => \addr_reg[7]_i_2_n_0\
    );
\addr_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[0]_i_1_n_0\,
      Q => \addr_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[1]_i_1_n_0\,
      Q => \addr_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[2]_i_1_n_0\,
      Q => \addr_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[3]_i_1_n_0\,
      Q => \addr_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[4]_i_1_n_0\,
      Q => \addr_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[5]_i_1_n_0\,
      Q => \addr_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[6]_i_1_n_0\,
      Q => \addr_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[7]_i_1_n_0\,
      Q => \addr_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B8BBB8B8B888"
    )
        port map (
      I0 => \di_reg[0]_i_4_n_0\,
      I1 => index(3),
      I2 => do_reg2(0),
      I3 => \di_reg[0]_i_5_n_0\,
      I4 => \di_reg[0]_i_6_n_0\,
      I5 => \di_reg[4]_i_8_n_0\,
      O => \di_reg[0]_i_2_n_0\
    );
\di_reg[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003414"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(0),
      I4 => index(3),
      O => \di_reg[0]_i_3_n_0\
    );
\di_reg[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0BFFFFFB0B00000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => do_reg2(0),
      O => \di_reg[0]_i_4_n_0\
    );
\di_reg[0]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      O => \di_reg[0]_i_5_n_0\
    );
\di_reg[0]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => index(1),
      I1 => mode,
      I2 => index(0),
      O => \di_reg[0]_i_6_n_0\
    );
\di_reg[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(10),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[10]_i_2_n_0\,
      O => di_reg(10)
    );
\di_reg[10]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[10]_i_2_n_0\
    );
\di_reg[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[11]_i_2_n_0\,
      I2 => index(4),
      I3 => \di_reg[11]_i_3_n_0\,
      I4 => \di_reg[11]_i_4_n_0\,
      I5 => \di_reg[11]_i_5_n_0\,
      O => di_reg(11)
    );
\di_reg[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808380808"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(0),
      I4 => rate_reg2(1),
      I5 => index(0),
      O => \di_reg[11]_i_2_n_0\
    );
\di_reg[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC0CCC0C0C0C880C"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => do_reg2(11),
      I3 => index(2),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[11]_i_3_n_0\
    );
\di_reg[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAABAAABA"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[11]_i_4_n_0\
    );
\di_reg[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA00AAAAAAA3"
    )
        port map (
      I0 => do_reg2(11),
      I1 => x16_reg2,
      I2 => \addr_reg[4]_i_2_n_0\,
      I3 => index(0),
      I4 => index(1),
      I5 => index(2),
      O => \di_reg[11]_i_5_n_0\
    );
\di_reg[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \di_reg[12]_i_2_n_0\,
      I1 => index(4),
      I2 => \di_reg[12]_i_3_n_0\,
      I3 => index(3),
      I4 => \di_reg[12]_i_4_n_0\,
      O => di_reg(12)
    );
\di_reg[12]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003202"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(12),
      I4 => index(3),
      O => \di_reg[12]_i_2_n_0\
    );
\di_reg[12]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(12),
      O => \di_reg[12]_i_3_n_0\
    );
\di_reg[12]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAA8AAABAAABA"
    )
        port map (
      I0 => do_reg2(12),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[12]_i_4_n_0\
    );
\di_reg[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \di_reg[13]_i_2_n_0\,
      I1 => index(4),
      I2 => \di_reg[13]_i_3_n_0\,
      I3 => index(3),
      I4 => \di_reg[13]_i_4_n_0\,
      O => di_reg(13)
    );
\di_reg[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080838380838"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[13]_i_2_n_0\
    );
\di_reg[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(13),
      O => \di_reg[13]_i_3_n_0\
    );
\di_reg[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAA8AAABAAA8A"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(1),
      I5 => rate_reg2(0),
      O => \di_reg[13]_i_4_n_0\
    );
\di_reg[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080008FF08000800"
    )
        port map (
      I0 => do_reg2(14),
      I1 => \di_reg[14]_i_2_n_0\,
      I2 => index(3),
      I3 => index(4),
      I4 => \di_reg[14]_i_3_n_0\,
      I5 => \di_reg[14]_i_4_n_0\,
      O => di_reg(14)
    );
\di_reg[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[14]_i_2_n_0\
    );
\di_reg[14]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033303310130033"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => index(2),
      I3 => do_reg2(14),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[14]_i_3_n_0\
    );
\di_reg[14]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000DF10"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => do_reg2(14),
      I4 => index(2),
      I5 => \di_reg[14]_i_6_n_0\,
      O => \di_reg[14]_i_4_n_0\
    );
\di_reg[14]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      O => data15(7)
    );
\di_reg[14]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB3BBBBBBB3FBB"
    )
        port map (
      I0 => \di_reg[14]_i_7_n_0\,
      I1 => index(3),
      I2 => index(0),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => \di_reg[5]_i_4_n_0\,
      O => \di_reg[14]_i_6_n_0\
    );
\di_reg[14]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => index(1),
      I1 => index(2),
      I2 => do_reg2(14),
      I3 => index(0),
      O => \di_reg[14]_i_7_n_0\
    );
\di_reg[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(15),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[15]_i_2_n_0\,
      O => di_reg(15)
    );
\di_reg[15]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[15]_i_2_n_0\
    );
\di_reg[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \di_reg[1]_i_2_n_0\,
      I1 => index(4),
      I2 => \di_reg[1]_i_3_n_0\,
      I3 => \di_reg[1]_i_4_n_0\,
      O => di_reg(1)
    );
\di_reg[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000034140000"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(1),
      I4 => index(4),
      I5 => index(3),
      O => \di_reg[1]_i_2_n_0\
    );
\di_reg[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FB330000"
    )
        port map (
      I0 => index(2),
      I1 => do_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(3),
      I5 => \di_reg[1]_i_5_n_0\,
      O => \di_reg[1]_i_3_n_0\
    );
\di_reg[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFCCC5555"
    )
        port map (
      I0 => \di_reg[1]_i_6_n_0\,
      I1 => do_reg2(1),
      I2 => index(1),
      I3 => index(0),
      I4 => index(2),
      I5 => index(3),
      O => \di_reg[1]_i_4_n_0\
    );
\di_reg[1]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      I3 => index(1),
      O => \di_reg[1]_i_5_n_0\
    );
\di_reg[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"002F0F20F02FFF2F"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(1),
      I3 => index(0),
      I4 => mode,
      I5 => do_reg2(1),
      O => \di_reg[1]_i_6_n_0\
    );
\di_reg[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \di_reg[2]_i_2_n_0\,
      I1 => \di_reg[2]_i_3_n_0\,
      O => di_reg(2)
    );
\di_reg[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00400500FFFFFFFF"
    )
        port map (
      I0 => index(3),
      I1 => do_reg2(2),
      I2 => index(2),
      I3 => index(1),
      I4 => index(0),
      I5 => index(4),
      O => \di_reg[2]_i_2_n_0\
    );
\di_reg[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF470047"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => \di_reg[2]_i_4_n_0\,
      I3 => index(3),
      I4 => \di_reg[2]_i_5_n_0\,
      I5 => index(4),
      O => \di_reg[2]_i_3_n_0\
    );
\di_reg[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F40404F00FF000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => mode,
      I4 => do_reg2(2),
      I5 => index(1),
      O => \di_reg[2]_i_4_n_0\
    );
\di_reg[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5D535D5F5D5F5D5"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[2]_i_5_n_0\
    );
\di_reg[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAA1000AAFF0000"
    )
        port map (
      I0 => \di_reg[3]_i_4_n_0\,
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => do_reg2(3),
      I5 => index(0),
      O => \di_reg[3]_i_2_n_0\
    );
\di_reg[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000033E200"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => do_reg2(3),
      I3 => index(2),
      I4 => index(1),
      I5 => index(3),
      O => \di_reg[3]_i_3_n_0\
    );
\di_reg[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      O => \di_reg[3]_i_4_n_0\
    );
\di_reg[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[4]_i_2_n_0\,
      I2 => index(4),
      I3 => \di_reg[4]_i_3_n_0\,
      I4 => \di_reg[4]_i_4_n_0\,
      I5 => \di_reg[4]_i_5_n_0\,
      O => di_reg(4)
    );
\di_reg[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080B0830303030"
    )
        port map (
      I0 => do_reg2(4),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[4]_i_2_n_0\
    );
\di_reg[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFFFFFFF"
    )
        port map (
      I0 => index(0),
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => index(1),
      I5 => \di_reg[4]_i_6_n_0\,
      O => \di_reg[4]_i_3_n_0\
    );
\di_reg[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFFE00000000"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      I2 => index(1),
      I3 => index(2),
      I4 => index(0),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_4_n_0\
    );
\di_reg[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010C00"
    )
        port map (
      I0 => \di_reg[4]_i_7_n_0\,
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => \di_reg[4]_i_8_n_0\,
      I5 => index(3),
      O => \di_reg[4]_i_5_n_0\
    );
\di_reg[4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1F0FFF0F"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(3),
      I3 => do_reg2(4),
      I4 => index(1),
      O => \di_reg[4]_i_6_n_0\
    );
\di_reg[4]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      O => \di_reg[4]_i_7_n_0\
    );
\di_reg[4]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => \di_reg[4]_i_8_n_0\
    );
\di_reg[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33000000B888B888"
    )
        port map (
      I0 => \di_reg[5]_i_2_n_0\,
      I1 => index(4),
      I2 => \di_reg[5]_i_3_n_0\,
      I3 => do_reg2(5),
      I4 => \di_reg[5]_i_4_n_0\,
      I5 => index(3),
      O => di_reg(5)
    );
\di_reg[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B0B080B33333033"
    )
        port map (
      I0 => do_reg2(5),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[5]_i_2_n_0\
    );
\di_reg[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(1),
      I3 => x16x20_mode_reg2,
      I4 => mode,
      O => \di_reg[5]_i_3_n_0\
    );
\di_reg[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[5]_i_4_n_0\
    );
\di_reg[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"67FF000067000000"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(6),
      I5 => \di_reg[5]_i_3_n_0\,
      O => \di_reg[6]_i_2_n_0\
    );
\di_reg[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002404"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(6),
      I4 => index(3),
      O => \di_reg[6]_i_3_n_0\
    );
\di_reg[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0900"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(7),
      O => \di_reg[7]_i_2_n_0\
    );
\di_reg[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000C320032"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => do_reg2(7),
      I5 => index(3),
      O => \di_reg[7]_i_3_n_0\
    );
\di_reg[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(8),
      O => di_reg(8)
    );
\di_reg[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(9),
      O => di_reg(9)
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(0),
      Q => \di_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[0]_i_2_n_0\,
      I1 => \di_reg[0]_i_3_n_0\,
      O => di_reg(0),
      S => index(4)
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(10),
      Q => \di_reg_reg_n_0_[10]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(11),
      Q => \di_reg_reg_n_0_[11]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(12),
      Q => \di_reg_reg_n_0_[12]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(13),
      Q => \di_reg_reg_n_0_[13]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(14),
      Q => \di_reg_reg_n_0_[14]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(15),
      Q => \di_reg_reg_n_0_[15]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(1),
      Q => \di_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(2),
      Q => \di_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(3),
      Q => \di_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[3]_i_2_n_0\,
      I1 => \di_reg[3]_i_3_n_0\,
      O => di_reg(3),
      S => index(4)
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(4),
      Q => \di_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(5),
      Q => \di_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(6),
      Q => \di_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[6]_i_2_n_0\,
      I1 => \di_reg[6]_i_3_n_0\,
      O => di_reg(6),
      S => index(4)
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(7),
      Q => \di_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[7]_i_2_n_0\,
      I1 => \di_reg[7]_i_3_n_0\,
      O => di_reg(7),
      S => index(4)
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(8),
      Q => \di_reg_reg_n_0_[8]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(9),
      Q => \di_reg_reg_n_0_[9]\,
      R => RST_DCLK_RESET
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(0),
      Q => do_reg1(0),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(10),
      Q => do_reg1(10),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(11),
      Q => do_reg1(11),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(12),
      Q => do_reg1(12),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(13),
      Q => do_reg1(13),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(14),
      Q => do_reg1(14),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(15),
      Q => do_reg1(15),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(1),
      Q => do_reg1(1),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(2),
      Q => do_reg1(2),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(3),
      Q => do_reg1(3),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(4),
      Q => do_reg1(4),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(5),
      Q => do_reg1(5),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(6),
      Q => do_reg1(6),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(7),
      Q => do_reg1(7),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(8),
      Q => do_reg1(8),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(9),
      Q => do_reg1(9),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => RST_DCLK_RESET
    );
done_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => start_reg2,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => done_i_1_n_0
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => done_i_1_n_0,
      Q => DRP_DONE,
      R => RST_DCLK_RESET
    );
\fsm[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B3BFFFF0B3B0000"
    )
        port map (
      I0 => data4,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => rdy_reg2,
      I4 => \^q\(2),
      I5 => \fsm[0]_i_3__0_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFEFFFF"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(4),
      I3 => index(2),
      I4 => mode_i_2_n_0,
      O => data4
    );
\fsm[0]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7477FFFF7477CCCC"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \^q\(1),
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      I4 => \^q\(0),
      I5 => start_reg2,
      O => \fsm[0]_i_3__0_n_0\
    );
\fsm[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"185018501D501850"
    )
        port map (
      I0 => \^q\(2),
      I1 => rdy_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => load_cnt(0),
      I5 => load_cnt(1),
      O => fsm(1)
    );
\fsm[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6222"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      R => RST_DCLK_RESET
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      R => RST_DCLK_RESET
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_DCLK_RESET
    );
\gt_ch_drp_rdy[0]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => gt_ch_drp_rdy(0)
    );
\gtx_channel.gtxe2_channel_i_i_14__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(15),
      I1 => \di_reg_reg_n_0_[15]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(15)
    );
\gtx_channel.gtxe2_channel_i_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(14),
      I1 => \di_reg_reg_n_0_[14]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(14)
    );
\gtx_channel.gtxe2_channel_i_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(13),
      I1 => \di_reg_reg_n_0_[13]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(13)
    );
\gtx_channel.gtxe2_channel_i_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(12),
      I1 => \di_reg_reg_n_0_[12]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(12)
    );
\gtx_channel.gtxe2_channel_i_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(11),
      I1 => \di_reg_reg_n_0_[11]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(11)
    );
\gtx_channel.gtxe2_channel_i_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(10),
      I1 => \di_reg_reg_n_0_[10]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(10)
    );
\gtx_channel.gtxe2_channel_i_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(9),
      I1 => \di_reg_reg_n_0_[9]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(9)
    );
\gtx_channel.gtxe2_channel_i_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(8),
      I1 => \di_reg_reg_n_0_[8]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(8)
    );
\gtx_channel.gtxe2_channel_i_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(7),
      I1 => \di_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(7)
    );
\gtx_channel.gtxe2_channel_i_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(6),
      I1 => \di_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(6)
    );
\gtx_channel.gtxe2_channel_i_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(5),
      I1 => \di_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(5)
    );
\gtx_channel.gtxe2_channel_i_i_25\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(4),
      I1 => \di_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(4)
    );
\gtx_channel.gtxe2_channel_i_i_26\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(3),
      I1 => \di_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(3)
    );
\gtx_channel.gtxe2_channel_i_i_27\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(2),
      I1 => \di_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(2)
    );
\gtx_channel.gtxe2_channel_i_i_28\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(1),
      I1 => \di_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(1)
    );
\gtx_channel.gtxe2_channel_i_i_29\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(0),
      I1 => \di_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(0)
    );
\gtx_channel.gtxe2_channel_i_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"003E"
    )
        port map (
      I0 => ext_ch_gt_drpen(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \cplllock_reg1_reg[0]\
    );
\gtx_channel.gtxe2_channel_i_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0032"
    )
        port map (
      I0 => ext_ch_gt_drpwe(0),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \cplllock_reg1_reg[0]_0\
    );
\gtx_channel.gtxe2_channel_i_i_47__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => DRPADDR(8)
    );
\gtx_channel.gtxe2_channel_i_i_48\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(7),
      I1 => \addr_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(7)
    );
\gtx_channel.gtxe2_channel_i_i_49\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(6),
      I1 => \addr_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(6)
    );
\gtx_channel.gtxe2_channel_i_i_50\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(5),
      I1 => \addr_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(5)
    );
\gtx_channel.gtxe2_channel_i_i_51\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(4),
      I1 => \addr_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(4)
    );
\gtx_channel.gtxe2_channel_i_i_52\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(3),
      I1 => \addr_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(3)
    );
\gtx_channel.gtxe2_channel_i_i_53\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(2),
      I1 => \addr_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(2)
    );
\gtx_channel.gtxe2_channel_i_i_54\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(1),
      I1 => \addr_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(1)
    );
\gtx_channel.gtxe2_channel_i_i_55\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(0),
      I1 => \addr_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(0)
    );
gtxreset_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_GTXRESET,
      Q => gtxreset_reg1,
      R => RST_DCLK_RESET
    );
gtxreset_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => gtxreset_reg1,
      Q => gtxreset_reg2,
      R => RST_DCLK_RESET
    );
\index[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => index(0),
      I1 => \^q\(2),
      I2 => \index[3]_i_2_n_0\,
      O => \index[0]_i_1__1_n_0\
    );
\index[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2_n_0\,
      I2 => index(1),
      I3 => index(0),
      O => \index[1]_i_1__1_n_0\
    );
\index[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02222000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      O => \index[2]_i_1__1_n_0\
    );
\index[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222222220000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => index(3),
      O => \index[3]_i_1_n_0\
    );
\index[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAE"
    )
        port map (
      I0 => \^q\(0),
      I1 => mode_i_2_n_0,
      I2 => index(2),
      I3 => index(4),
      I4 => index(1),
      I5 => index(3),
      O => \index[3]_i_2_n_0\
    );
\index[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"89"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \index[4]_i_1_n_0\
    );
\index[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => index(0),
      I1 => index(2),
      I2 => index(3),
      I3 => index(1),
      I4 => index(4),
      I5 => \index[4]_i_3_n_0\,
      O => \index[4]_i_2_n_0\
    );
\index[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \index[3]_i_2_n_0\,
      I1 => \^q\(2),
      O => \index[4]_i_3_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1_n_0\,
      D => \index[0]_i_1__1_n_0\,
      Q => index(0),
      R => RST_DCLK_RESET
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1_n_0\,
      D => \index[1]_i_1__1_n_0\,
      Q => index(1),
      R => RST_DCLK_RESET
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1_n_0\,
      D => \index[2]_i_1__1_n_0\,
      Q => index(2),
      R => RST_DCLK_RESET
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1_n_0\,
      D => \index[3]_i_1_n_0\,
      Q => index(3),
      R => RST_DCLK_RESET
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1_n_0\,
      D => \index[4]_i_2_n_0\,
      Q => index(4),
      R => RST_DCLK_RESET
    );
\load_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => load_cnt(1),
      I3 => \^q\(2),
      O => \load_cnt[0]_i_1_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[0]_i_1_n_0\,
      Q => load_cnt(0),
      R => RST_DCLK_RESET
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => load_cnt(1),
      R => RST_DCLK_RESET
    );
mode_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AAA2AAAAAAAA00"
    )
        port map (
      I0 => mode,
      I1 => mode_i_2_n_0,
      I2 => \mode_i_3__1_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => mode_i_1_n_0
    );
mode_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCB8"
    )
        port map (
      I0 => mode,
      I1 => index(0),
      I2 => x16x20_mode_reg2,
      I3 => index(2),
      O => mode_i_2_n_0
    );
\mode_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF6"
    )
        port map (
      I0 => index(2),
      I1 => index(4),
      I2 => index(1),
      I3 => index(3),
      O => \mode_i_3__1_n_0\
    );
mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => mode_i_1_n_0,
      Q => mode,
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_reg1(0),
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => RST_DCLK_RESET
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drprdy(0),
      Q => rdy_reg1,
      R => RST_DCLK_RESET
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => RST_DCLK_RESET
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_START,
      Q => start_reg1,
      R => RST_DCLK_RESET
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => RST_DCLK_RESET
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16,
      Q => x16_reg1,
      R => RST_DCLK_RESET
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16X20_MODE,
      Q => x16x20_mode_reg1,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16x20_mode_reg1,
      Q => x16x20_mode_reg2,
      R => RST_DCLK_RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_30 is
  port (
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \cplllock_reg1_reg[1]\ : out STD_LOGIC;
    \cplllock_reg1_reg[1]_0\ : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_DONE : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 );
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_X16X20_MODE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    ext_ch_gt_drprdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DRP_X16 : in STD_LOGIC;
    ext_ch_gt_drpdo : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rst_gtreset : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_30 : entity is "PCIeGen1x8If64_pipe_drp";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_30;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_30 is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \addr_reg[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \addr_reg[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \addr_reg[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \addr_reg[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \addr_reg[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \addr_reg[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal data15 : STD_LOGIC_VECTOR ( 7 to 7 );
  signal data4 : STD_LOGIC;
  signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di_reg[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \di_reg[10]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_5__0_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_6__0_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_7__0_n_0\ : STD_LOGIC;
  signal \di_reg[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_5__0_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_6__0_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_5__0_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_5__0_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_6__0_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_7__0_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_8__0_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[9]\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \done_i_1__0_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm[0]_i_3__2_n_0\ : STD_LOGIC;
  signal gtxreset_reg1 : STD_LOGIC;
  signal gtxreset_reg2 : STD_LOGIC;
  signal index : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \index[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \index[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \index[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \index[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \index[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \index[4]_i_3__0_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
  signal mode : STD_LOGIC;
  signal \mode_i_1__0_n_0\ : STD_LOGIC;
  signal \mode_i_2__0_n_0\ : STD_LOGIC;
  signal \mode_i_3__2_n_0\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rdy_reg1 : STD_LOGIC;
  signal rdy_reg2 : STD_LOGIC;
  signal start_reg1 : STD_LOGIC;
  signal start_reg2 : STD_LOGIC;
  signal x16_reg1 : STD_LOGIC;
  signal x16_reg2 : STD_LOGIC;
  signal x16x20_mode_reg1 : STD_LOGIC;
  signal x16x20_mode_reg2 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \di_reg[0]_i_5__0\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \di_reg[0]_i_6__0\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \di_reg[14]_i_2__0\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \di_reg[3]_i_4__0\ : label is "soft_lutpair52";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \fsm[0]_i_2__0\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \gt_ch_drp_rdy[1]_INST_0\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__0\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_47__4\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__0\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_50__0\ : label is "soft_lutpair45";
  attribute ASYNC_REG of gtxreset_reg1_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg1_reg : label is "yes";
  attribute ASYNC_REG of gtxreset_reg2_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \index[0]_i_1__2\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \index[1]_i_1__2\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \index[2]_i_1__2\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \index[4]_i_3__0\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1__1\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \mode_i_3__2\ : label is "soft_lutpair47";
  attribute ASYNC_REG of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute ASYNC_REG of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute ASYNC_REG of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg2_reg : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\addr_reg[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1471357514713564"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__0_n_0\,
      O => \addr_reg[0]_i_1__0_n_0\
    );
\addr_reg[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404050500F0F0500"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[1]_i_1__0_n_0\
    );
\addr_reg[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"051005105A055A00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(2),
      I4 => mode,
      I5 => index(1),
      O => \addr_reg[2]_i_1__0_n_0\
    );
\addr_reg[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5767576753275326"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => \addr_reg[4]_i_2__0_n_0\,
      I5 => index(0),
      O => \addr_reg[3]_i_1__0_n_0\
    );
\addr_reg[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FCCFFF01"
    )
        port map (
      I0 => \addr_reg[4]_i_2__0_n_0\,
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => index(4),
      O => \addr_reg[4]_i_1__0_n_0\
    );
\addr_reg[4]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      O => \addr_reg[4]_i_2__0_n_0\
    );
\addr_reg[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001A1A0F0F0F0A"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[5]_i_1__0_n_0\
    );
\addr_reg[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011545554"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => mode,
      I3 => index(3),
      I4 => index(0),
      I5 => index(4),
      O => \addr_reg[6]_i_1__0_n_0\
    );
\addr_reg[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5422262254222633"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__0_n_0\,
      O => \addr_reg[7]_i_1__0_n_0\
    );
\addr_reg[7]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CE"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      I2 => index(0),
      O => \addr_reg[7]_i_2__0_n_0\
    );
\addr_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[0]_i_1__0_n_0\,
      Q => \addr_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[1]_i_1__0_n_0\,
      Q => \addr_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[2]_i_1__0_n_0\,
      Q => \addr_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[3]_i_1__0_n_0\,
      Q => \addr_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[4]_i_1__0_n_0\,
      Q => \addr_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[5]_i_1__0_n_0\,
      Q => \addr_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[6]_i_1__0_n_0\,
      Q => \addr_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[7]_i_1__0_n_0\,
      Q => \addr_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B8BBB8B8B888"
    )
        port map (
      I0 => \di_reg[0]_i_4__0_n_0\,
      I1 => index(3),
      I2 => do_reg2(0),
      I3 => \di_reg[0]_i_5__0_n_0\,
      I4 => \di_reg[0]_i_6__0_n_0\,
      I5 => \di_reg[4]_i_8__0_n_0\,
      O => \di_reg[0]_i_2__0_n_0\
    );
\di_reg[0]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003414"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(0),
      I4 => index(3),
      O => \di_reg[0]_i_3__0_n_0\
    );
\di_reg[0]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0BFFFFFB0B00000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => do_reg2(0),
      O => \di_reg[0]_i_4__0_n_0\
    );
\di_reg[0]_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      O => \di_reg[0]_i_5__0_n_0\
    );
\di_reg[0]_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => index(1),
      I1 => mode,
      I2 => index(0),
      O => \di_reg[0]_i_6__0_n_0\
    );
\di_reg[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(10),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[10]_i_2__0_n_0\,
      O => di_reg(10)
    );
\di_reg[10]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[10]_i_2__0_n_0\
    );
\di_reg[11]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[11]_i_2__0_n_0\,
      I2 => index(4),
      I3 => \di_reg[11]_i_3__0_n_0\,
      I4 => \di_reg[11]_i_4__0_n_0\,
      I5 => \di_reg[11]_i_5__0_n_0\,
      O => di_reg(11)
    );
\di_reg[11]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808380808"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(0),
      I4 => rate_reg2(1),
      I5 => index(0),
      O => \di_reg[11]_i_2__0_n_0\
    );
\di_reg[11]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC0CCC0C0C0C880C"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => do_reg2(11),
      I3 => index(2),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[11]_i_3__0_n_0\
    );
\di_reg[11]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAABAAABA"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[11]_i_4__0_n_0\
    );
\di_reg[11]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA00AAAAAAA3"
    )
        port map (
      I0 => do_reg2(11),
      I1 => x16_reg2,
      I2 => \addr_reg[4]_i_2__0_n_0\,
      I3 => index(0),
      I4 => index(1),
      I5 => index(2),
      O => \di_reg[11]_i_5__0_n_0\
    );
\di_reg[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \di_reg[12]_i_2__0_n_0\,
      I1 => index(4),
      I2 => \di_reg[12]_i_3__0_n_0\,
      I3 => index(3),
      I4 => \di_reg[12]_i_4__0_n_0\,
      O => di_reg(12)
    );
\di_reg[12]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003202"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(12),
      I4 => index(3),
      O => \di_reg[12]_i_2__0_n_0\
    );
\di_reg[12]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(12),
      O => \di_reg[12]_i_3__0_n_0\
    );
\di_reg[12]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAA8AAABAAABA"
    )
        port map (
      I0 => do_reg2(12),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[12]_i_4__0_n_0\
    );
\di_reg[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \di_reg[13]_i_2__0_n_0\,
      I1 => index(4),
      I2 => \di_reg[13]_i_3__0_n_0\,
      I3 => index(3),
      I4 => \di_reg[13]_i_4__0_n_0\,
      O => di_reg(13)
    );
\di_reg[13]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080838380838"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[13]_i_2__0_n_0\
    );
\di_reg[13]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(13),
      O => \di_reg[13]_i_3__0_n_0\
    );
\di_reg[13]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAA8AAABAAA8A"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(1),
      I5 => rate_reg2(0),
      O => \di_reg[13]_i_4__0_n_0\
    );
\di_reg[14]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080008FF08000800"
    )
        port map (
      I0 => do_reg2(14),
      I1 => \di_reg[14]_i_2__0_n_0\,
      I2 => index(3),
      I3 => index(4),
      I4 => \di_reg[14]_i_3__0_n_0\,
      I5 => \di_reg[14]_i_4__0_n_0\,
      O => di_reg(14)
    );
\di_reg[14]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[14]_i_2__0_n_0\
    );
\di_reg[14]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033303310130033"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => index(2),
      I3 => do_reg2(14),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[14]_i_3__0_n_0\
    );
\di_reg[14]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000DF10"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => do_reg2(14),
      I4 => index(2),
      I5 => \di_reg[14]_i_6__0_n_0\,
      O => \di_reg[14]_i_4__0_n_0\
    );
\di_reg[14]_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      O => data15(7)
    );
\di_reg[14]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB3BBBBBBB3FBB"
    )
        port map (
      I0 => \di_reg[14]_i_7__0_n_0\,
      I1 => index(3),
      I2 => index(0),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => \di_reg[5]_i_4__0_n_0\,
      O => \di_reg[14]_i_6__0_n_0\
    );
\di_reg[14]_i_7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => index(1),
      I1 => index(2),
      I2 => do_reg2(14),
      I3 => index(0),
      O => \di_reg[14]_i_7__0_n_0\
    );
\di_reg[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(15),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[15]_i_2__0_n_0\,
      O => di_reg(15)
    );
\di_reg[15]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[15]_i_2__0_n_0\
    );
\di_reg[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \di_reg[1]_i_2__0_n_0\,
      I1 => index(4),
      I2 => \di_reg[1]_i_3__0_n_0\,
      I3 => \di_reg[1]_i_4__0_n_0\,
      O => di_reg(1)
    );
\di_reg[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000034140000"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(1),
      I4 => index(4),
      I5 => index(3),
      O => \di_reg[1]_i_2__0_n_0\
    );
\di_reg[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FB330000"
    )
        port map (
      I0 => index(2),
      I1 => do_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(3),
      I5 => \di_reg[1]_i_5__0_n_0\,
      O => \di_reg[1]_i_3__0_n_0\
    );
\di_reg[1]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFCCC5555"
    )
        port map (
      I0 => \di_reg[1]_i_6__0_n_0\,
      I1 => do_reg2(1),
      I2 => index(1),
      I3 => index(0),
      I4 => index(2),
      I5 => index(3),
      O => \di_reg[1]_i_4__0_n_0\
    );
\di_reg[1]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      I3 => index(1),
      O => \di_reg[1]_i_5__0_n_0\
    );
\di_reg[1]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"002F0F20F02FFF2F"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(1),
      I3 => index(0),
      I4 => mode,
      I5 => do_reg2(1),
      O => \di_reg[1]_i_6__0_n_0\
    );
\di_reg[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \di_reg[2]_i_2__0_n_0\,
      I1 => \di_reg[2]_i_3__0_n_0\,
      O => di_reg(2)
    );
\di_reg[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00400500FFFFFFFF"
    )
        port map (
      I0 => index(3),
      I1 => do_reg2(2),
      I2 => index(2),
      I3 => index(1),
      I4 => index(0),
      I5 => index(4),
      O => \di_reg[2]_i_2__0_n_0\
    );
\di_reg[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF470047"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => \di_reg[2]_i_4__0_n_0\,
      I3 => index(3),
      I4 => \di_reg[2]_i_5__0_n_0\,
      I5 => index(4),
      O => \di_reg[2]_i_3__0_n_0\
    );
\di_reg[2]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F40404F00FF000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => mode,
      I4 => do_reg2(2),
      I5 => index(1),
      O => \di_reg[2]_i_4__0_n_0\
    );
\di_reg[2]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5D535D5F5D5F5D5"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[2]_i_5__0_n_0\
    );
\di_reg[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAA1000AAFF0000"
    )
        port map (
      I0 => \di_reg[3]_i_4__0_n_0\,
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => do_reg2(3),
      I5 => index(0),
      O => \di_reg[3]_i_2__0_n_0\
    );
\di_reg[3]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000033E200"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => do_reg2(3),
      I3 => index(2),
      I4 => index(1),
      I5 => index(3),
      O => \di_reg[3]_i_3__0_n_0\
    );
\di_reg[3]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      O => \di_reg[3]_i_4__0_n_0\
    );
\di_reg[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[4]_i_2__0_n_0\,
      I2 => index(4),
      I3 => \di_reg[4]_i_3__0_n_0\,
      I4 => \di_reg[4]_i_4__0_n_0\,
      I5 => \di_reg[4]_i_5__0_n_0\,
      O => di_reg(4)
    );
\di_reg[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080B0830303030"
    )
        port map (
      I0 => do_reg2(4),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[4]_i_2__0_n_0\
    );
\di_reg[4]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFFFFFFF"
    )
        port map (
      I0 => index(0),
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => index(1),
      I5 => \di_reg[4]_i_6__0_n_0\,
      O => \di_reg[4]_i_3__0_n_0\
    );
\di_reg[4]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFFE00000000"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      I2 => index(1),
      I3 => index(2),
      I4 => index(0),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_4__0_n_0\
    );
\di_reg[4]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010C00"
    )
        port map (
      I0 => \di_reg[4]_i_7__0_n_0\,
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => \di_reg[4]_i_8__0_n_0\,
      I5 => index(3),
      O => \di_reg[4]_i_5__0_n_0\
    );
\di_reg[4]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1F0FFF0F"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(3),
      I3 => do_reg2(4),
      I4 => index(1),
      O => \di_reg[4]_i_6__0_n_0\
    );
\di_reg[4]_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      O => \di_reg[4]_i_7__0_n_0\
    );
\di_reg[4]_i_8__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => \di_reg[4]_i_8__0_n_0\
    );
\di_reg[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33000000B888B888"
    )
        port map (
      I0 => \di_reg[5]_i_2__0_n_0\,
      I1 => index(4),
      I2 => \di_reg[5]_i_3__0_n_0\,
      I3 => do_reg2(5),
      I4 => \di_reg[5]_i_4__0_n_0\,
      I5 => index(3),
      O => di_reg(5)
    );
\di_reg[5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B0B080B33333033"
    )
        port map (
      I0 => do_reg2(5),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[5]_i_2__0_n_0\
    );
\di_reg[5]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(1),
      I3 => x16x20_mode_reg2,
      I4 => mode,
      O => \di_reg[5]_i_3__0_n_0\
    );
\di_reg[5]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[5]_i_4__0_n_0\
    );
\di_reg[6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"67FF000067000000"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(6),
      I5 => \di_reg[5]_i_3__0_n_0\,
      O => \di_reg[6]_i_2__0_n_0\
    );
\di_reg[6]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002404"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(6),
      I4 => index(3),
      O => \di_reg[6]_i_3__0_n_0\
    );
\di_reg[7]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0900"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(7),
      O => \di_reg[7]_i_2__0_n_0\
    );
\di_reg[7]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000C320032"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => do_reg2(7),
      I5 => index(3),
      O => \di_reg[7]_i_3__0_n_0\
    );
\di_reg[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(8),
      O => di_reg(8)
    );
\di_reg[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(9),
      O => di_reg(9)
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(0),
      Q => \di_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[0]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[0]_i_2__0_n_0\,
      I1 => \di_reg[0]_i_3__0_n_0\,
      O => di_reg(0),
      S => index(4)
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(10),
      Q => \di_reg_reg_n_0_[10]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(11),
      Q => \di_reg_reg_n_0_[11]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(12),
      Q => \di_reg_reg_n_0_[12]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(13),
      Q => \di_reg_reg_n_0_[13]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(14),
      Q => \di_reg_reg_n_0_[14]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(15),
      Q => \di_reg_reg_n_0_[15]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(1),
      Q => \di_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(2),
      Q => \di_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(3),
      Q => \di_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[3]_i_2__0_n_0\,
      I1 => \di_reg[3]_i_3__0_n_0\,
      O => di_reg(3),
      S => index(4)
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(4),
      Q => \di_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(5),
      Q => \di_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(6),
      Q => \di_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[6]_i_2__0_n_0\,
      I1 => \di_reg[6]_i_3__0_n_0\,
      O => di_reg(6),
      S => index(4)
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(7),
      Q => \di_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[7]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[7]_i_2__0_n_0\,
      I1 => \di_reg[7]_i_3__0_n_0\,
      O => di_reg(7),
      S => index(4)
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(8),
      Q => \di_reg_reg_n_0_[8]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(9),
      Q => \di_reg_reg_n_0_[9]\,
      R => RST_DCLK_RESET
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(0),
      Q => do_reg1(0),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(10),
      Q => do_reg1(10),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(11),
      Q => do_reg1(11),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(12),
      Q => do_reg1(12),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(13),
      Q => do_reg1(13),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(14),
      Q => do_reg1(14),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(15),
      Q => do_reg1(15),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(1),
      Q => do_reg1(1),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(2),
      Q => do_reg1(2),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(3),
      Q => do_reg1(3),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(4),
      Q => do_reg1(4),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(5),
      Q => do_reg1(5),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(6),
      Q => do_reg1(6),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(7),
      Q => do_reg1(7),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(8),
      Q => do_reg1(8),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(9),
      Q => do_reg1(9),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => RST_DCLK_RESET
    );
\done_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => start_reg2,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \done_i_1__0_n_0\
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \done_i_1__0_n_0\,
      Q => DRP_DONE,
      R => RST_DCLK_RESET
    );
\fsm[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B3BFFFF0B3B0000"
    )
        port map (
      I0 => data4,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => rdy_reg2,
      I4 => \^q\(2),
      I5 => \fsm[0]_i_3__2_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFEFFFF"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(4),
      I3 => index(2),
      I4 => \mode_i_2__0_n_0\,
      O => data4
    );
\fsm[0]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7477FFFF7477CCCC"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \^q\(1),
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      I4 => \^q\(0),
      I5 => start_reg2,
      O => \fsm[0]_i_3__2_n_0\
    );
\fsm[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"185018501D501850"
    )
        port map (
      I0 => \^q\(2),
      I1 => rdy_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => load_cnt(0),
      I5 => load_cnt(1),
      O => fsm(1)
    );
\fsm[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6222"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      R => RST_DCLK_RESET
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      R => RST_DCLK_RESET
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_DCLK_RESET
    );
\gt_ch_drp_rdy[1]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => gt_ch_drp_rdy(0)
    );
\gtx_channel.gtxe2_channel_i_i_14__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(15),
      I1 => \di_reg_reg_n_0_[15]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(15)
    );
\gtx_channel.gtxe2_channel_i_i_15__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(14),
      I1 => \di_reg_reg_n_0_[14]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(14)
    );
\gtx_channel.gtxe2_channel_i_i_16__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(13),
      I1 => \di_reg_reg_n_0_[13]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(13)
    );
\gtx_channel.gtxe2_channel_i_i_17__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(12),
      I1 => \di_reg_reg_n_0_[12]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(12)
    );
\gtx_channel.gtxe2_channel_i_i_18__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(11),
      I1 => \di_reg_reg_n_0_[11]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(11)
    );
\gtx_channel.gtxe2_channel_i_i_19__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(10),
      I1 => \di_reg_reg_n_0_[10]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(10)
    );
\gtx_channel.gtxe2_channel_i_i_20__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(9),
      I1 => \di_reg_reg_n_0_[9]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(9)
    );
\gtx_channel.gtxe2_channel_i_i_21__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(8),
      I1 => \di_reg_reg_n_0_[8]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(8)
    );
\gtx_channel.gtxe2_channel_i_i_22__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(7),
      I1 => \di_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(7)
    );
\gtx_channel.gtxe2_channel_i_i_23__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(6),
      I1 => \di_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(6)
    );
\gtx_channel.gtxe2_channel_i_i_24__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(5),
      I1 => \di_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(5)
    );
\gtx_channel.gtxe2_channel_i_i_25__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(4),
      I1 => \di_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(4)
    );
\gtx_channel.gtxe2_channel_i_i_26__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(3),
      I1 => \di_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(3)
    );
\gtx_channel.gtxe2_channel_i_i_27__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(2),
      I1 => \di_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(2)
    );
\gtx_channel.gtxe2_channel_i_i_28__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(1),
      I1 => \di_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(1)
    );
\gtx_channel.gtxe2_channel_i_i_29__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(0),
      I1 => \di_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(0)
    );
\gtx_channel.gtxe2_channel_i_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"003E"
    )
        port map (
      I0 => ext_ch_gt_drpen(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \cplllock_reg1_reg[1]\
    );
\gtx_channel.gtxe2_channel_i_i_47__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => DRPADDR(8)
    );
\gtx_channel.gtxe2_channel_i_i_48__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(7),
      I1 => \addr_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(7)
    );
\gtx_channel.gtxe2_channel_i_i_49__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(6),
      I1 => \addr_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(6)
    );
\gtx_channel.gtxe2_channel_i_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0032"
    )
        port map (
      I0 => ext_ch_gt_drpwe(0),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \cplllock_reg1_reg[1]_0\
    );
\gtx_channel.gtxe2_channel_i_i_50__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(5),
      I1 => \addr_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(5)
    );
\gtx_channel.gtxe2_channel_i_i_51__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(4),
      I1 => \addr_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(4)
    );
\gtx_channel.gtxe2_channel_i_i_52__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(3),
      I1 => \addr_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(3)
    );
\gtx_channel.gtxe2_channel_i_i_53__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(2),
      I1 => \addr_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(2)
    );
\gtx_channel.gtxe2_channel_i_i_54__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(1),
      I1 => \addr_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(1)
    );
\gtx_channel.gtxe2_channel_i_i_55__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(0),
      I1 => \addr_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(0)
    );
gtxreset_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rst_gtreset,
      Q => gtxreset_reg1,
      R => RST_DCLK_RESET
    );
gtxreset_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => gtxreset_reg1,
      Q => gtxreset_reg2,
      R => RST_DCLK_RESET
    );
\index[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => index(0),
      I1 => \^q\(2),
      I2 => \index[3]_i_2__0_n_0\,
      O => \index[0]_i_1__2_n_0\
    );
\index[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__0_n_0\,
      I2 => index(1),
      I3 => index(0),
      O => \index[1]_i_1__2_n_0\
    );
\index[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02222000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__0_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      O => \index[2]_i_1__2_n_0\
    );
\index[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222222220000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__0_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => index(3),
      O => \index[3]_i_1__0_n_0\
    );
\index[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAE"
    )
        port map (
      I0 => \^q\(0),
      I1 => \mode_i_2__0_n_0\,
      I2 => index(2),
      I3 => index(4),
      I4 => index(1),
      I5 => index(3),
      O => \index[3]_i_2__0_n_0\
    );
\index[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"89"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \index[4]_i_1__0_n_0\
    );
\index[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => index(0),
      I1 => index(2),
      I2 => index(3),
      I3 => index(1),
      I4 => index(4),
      I5 => \index[4]_i_3__0_n_0\,
      O => \index[4]_i_2__0_n_0\
    );
\index[4]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \index[3]_i_2__0_n_0\,
      I1 => \^q\(2),
      O => \index[4]_i_3__0_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__0_n_0\,
      D => \index[0]_i_1__2_n_0\,
      Q => index(0),
      R => RST_DCLK_RESET
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__0_n_0\,
      D => \index[1]_i_1__2_n_0\,
      Q => index(1),
      R => RST_DCLK_RESET
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__0_n_0\,
      D => \index[2]_i_1__2_n_0\,
      Q => index(2),
      R => RST_DCLK_RESET
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__0_n_0\,
      D => \index[3]_i_1__0_n_0\,
      Q => index(3),
      R => RST_DCLK_RESET
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__0_n_0\,
      D => \index[4]_i_2__0_n_0\,
      Q => index(4),
      R => RST_DCLK_RESET
    );
\load_cnt[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => load_cnt(1),
      I3 => \^q\(2),
      O => \load_cnt[0]_i_1__1_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[0]_i_1__1_n_0\,
      Q => load_cnt(0),
      R => RST_DCLK_RESET
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => load_cnt(1),
      R => RST_DCLK_RESET
    );
\mode_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AAA2AAAAAAAA00"
    )
        port map (
      I0 => mode,
      I1 => \mode_i_2__0_n_0\,
      I2 => \mode_i_3__2_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \mode_i_1__0_n_0\
    );
\mode_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCB8"
    )
        port map (
      I0 => mode,
      I1 => index(0),
      I2 => x16x20_mode_reg2,
      I3 => index(2),
      O => \mode_i_2__0_n_0\
    );
\mode_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF6"
    )
        port map (
      I0 => index(2),
      I1 => index(4),
      I2 => index(1),
      I3 => index(3),
      O => \mode_i_3__2_n_0\
    );
mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \mode_i_1__0_n_0\,
      Q => mode,
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_reg1(0),
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => RST_DCLK_RESET
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drprdy(0),
      Q => rdy_reg1,
      R => RST_DCLK_RESET
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => RST_DCLK_RESET
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_START,
      Q => start_reg1,
      R => RST_DCLK_RESET
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => RST_DCLK_RESET
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16,
      Q => x16_reg1,
      R => RST_DCLK_RESET
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16X20_MODE,
      Q => x16x20_mode_reg1,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16x20_mode_reg1,
      Q => x16x20_mode_reg2,
      R => RST_DCLK_RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_36 is
  port (
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \cplllock_reg1_reg[2]\ : out STD_LOGIC;
    \cplllock_reg1_reg[2]_0\ : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_DONE : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 );
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_X16X20_MODE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    ext_ch_gt_drprdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DRP_X16 : in STD_LOGIC;
    ext_ch_gt_drpdo : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rst_gtreset : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_36 : entity is "PCIeGen1x8If64_pipe_drp";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_36;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_36 is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \addr_reg[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \addr_reg[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \addr_reg[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \addr_reg[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \addr_reg[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \addr_reg[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_2__1_n_0\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal data15 : STD_LOGIC_VECTOR ( 7 to 7 );
  signal data4 : STD_LOGIC;
  signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di_reg[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_4__1_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_5__1_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_6__1_n_0\ : STD_LOGIC;
  signal \di_reg[10]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_4__1_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_5__1_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_4__1_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_4__1_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_4__1_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_6__1_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_7__1_n_0\ : STD_LOGIC;
  signal \di_reg[15]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_4__1_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_5__1_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_6__1_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_4__1_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_5__1_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_4__1_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_4__1_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_5__1_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_6__1_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_7__1_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_8__1_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_4__1_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_2__1_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_3__1_n_0\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[9]\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \done_i_1__1_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm[0]_i_3__4_n_0\ : STD_LOGIC;
  signal gtxreset_reg1 : STD_LOGIC;
  signal gtxreset_reg2 : STD_LOGIC;
  signal index : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \index[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \index[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \index[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \index[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \index[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \index[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \index[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \index[4]_i_3__1_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
  signal mode : STD_LOGIC;
  signal \mode_i_1__1_n_0\ : STD_LOGIC;
  signal \mode_i_2__1_n_0\ : STD_LOGIC;
  signal \mode_i_3__3_n_0\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rdy_reg1 : STD_LOGIC;
  signal rdy_reg2 : STD_LOGIC;
  signal start_reg1 : STD_LOGIC;
  signal start_reg2 : STD_LOGIC;
  signal x16_reg1 : STD_LOGIC;
  signal x16_reg2 : STD_LOGIC;
  signal x16x20_mode_reg1 : STD_LOGIC;
  signal x16x20_mode_reg2 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \di_reg[0]_i_5__1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \di_reg[0]_i_6__1\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \di_reg[14]_i_2__1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \di_reg[3]_i_4__1\ : label is "soft_lutpair74";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \fsm[0]_i_2__1\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \gt_ch_drp_rdy[2]_INST_0\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_48__3\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__1\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_51__1\ : label is "soft_lutpair67";
  attribute ASYNC_REG of gtxreset_reg1_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg1_reg : label is "yes";
  attribute ASYNC_REG of gtxreset_reg2_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \index[0]_i_1__3\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \index[1]_i_1__3\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \index[2]_i_1__3\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \index[4]_i_3__1\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1__2\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \mode_i_3__3\ : label is "soft_lutpair69";
  attribute ASYNC_REG of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute ASYNC_REG of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute ASYNC_REG of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg2_reg : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\addr_reg[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1471357514713564"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__1_n_0\,
      O => \addr_reg[0]_i_1__1_n_0\
    );
\addr_reg[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404050500F0F0500"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[1]_i_1__1_n_0\
    );
\addr_reg[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"051005105A055A00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(2),
      I4 => mode,
      I5 => index(1),
      O => \addr_reg[2]_i_1__1_n_0\
    );
\addr_reg[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5767576753275326"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => \addr_reg[4]_i_2__1_n_0\,
      I5 => index(0),
      O => \addr_reg[3]_i_1__1_n_0\
    );
\addr_reg[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FCCFFF01"
    )
        port map (
      I0 => \addr_reg[4]_i_2__1_n_0\,
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => index(4),
      O => \addr_reg[4]_i_1__1_n_0\
    );
\addr_reg[4]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      O => \addr_reg[4]_i_2__1_n_0\
    );
\addr_reg[5]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001A1A0F0F0F0A"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[5]_i_1__1_n_0\
    );
\addr_reg[6]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011545554"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => mode,
      I3 => index(3),
      I4 => index(0),
      I5 => index(4),
      O => \addr_reg[6]_i_1__1_n_0\
    );
\addr_reg[7]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5422262254222633"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__1_n_0\,
      O => \addr_reg[7]_i_1__1_n_0\
    );
\addr_reg[7]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CE"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      I2 => index(0),
      O => \addr_reg[7]_i_2__1_n_0\
    );
\addr_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[0]_i_1__1_n_0\,
      Q => \addr_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[1]_i_1__1_n_0\,
      Q => \addr_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[2]_i_1__1_n_0\,
      Q => \addr_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[3]_i_1__1_n_0\,
      Q => \addr_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[4]_i_1__1_n_0\,
      Q => \addr_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[5]_i_1__1_n_0\,
      Q => \addr_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[6]_i_1__1_n_0\,
      Q => \addr_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[7]_i_1__1_n_0\,
      Q => \addr_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg[0]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B8BBB8B8B888"
    )
        port map (
      I0 => \di_reg[0]_i_4__1_n_0\,
      I1 => index(3),
      I2 => do_reg2(0),
      I3 => \di_reg[0]_i_5__1_n_0\,
      I4 => \di_reg[0]_i_6__1_n_0\,
      I5 => \di_reg[4]_i_8__1_n_0\,
      O => \di_reg[0]_i_2__1_n_0\
    );
\di_reg[0]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003414"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(0),
      I4 => index(3),
      O => \di_reg[0]_i_3__1_n_0\
    );
\di_reg[0]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0BFFFFFB0B00000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => do_reg2(0),
      O => \di_reg[0]_i_4__1_n_0\
    );
\di_reg[0]_i_5__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      O => \di_reg[0]_i_5__1_n_0\
    );
\di_reg[0]_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => index(1),
      I1 => mode,
      I2 => index(0),
      O => \di_reg[0]_i_6__1_n_0\
    );
\di_reg[10]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(10),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[10]_i_2__1_n_0\,
      O => di_reg(10)
    );
\di_reg[10]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[10]_i_2__1_n_0\
    );
\di_reg[11]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[11]_i_2__1_n_0\,
      I2 => index(4),
      I3 => \di_reg[11]_i_3__1_n_0\,
      I4 => \di_reg[11]_i_4__1_n_0\,
      I5 => \di_reg[11]_i_5__1_n_0\,
      O => di_reg(11)
    );
\di_reg[11]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808380808"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(0),
      I4 => rate_reg2(1),
      I5 => index(0),
      O => \di_reg[11]_i_2__1_n_0\
    );
\di_reg[11]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC0CCC0C0C0C880C"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => do_reg2(11),
      I3 => index(2),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[11]_i_3__1_n_0\
    );
\di_reg[11]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAABAAABA"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[11]_i_4__1_n_0\
    );
\di_reg[11]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA00AAAAAAA3"
    )
        port map (
      I0 => do_reg2(11),
      I1 => x16_reg2,
      I2 => \addr_reg[4]_i_2__1_n_0\,
      I3 => index(0),
      I4 => index(1),
      I5 => index(2),
      O => \di_reg[11]_i_5__1_n_0\
    );
\di_reg[12]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \di_reg[12]_i_2__1_n_0\,
      I1 => index(4),
      I2 => \di_reg[12]_i_3__1_n_0\,
      I3 => index(3),
      I4 => \di_reg[12]_i_4__1_n_0\,
      O => di_reg(12)
    );
\di_reg[12]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003202"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(12),
      I4 => index(3),
      O => \di_reg[12]_i_2__1_n_0\
    );
\di_reg[12]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(12),
      O => \di_reg[12]_i_3__1_n_0\
    );
\di_reg[12]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAA8AAABAAABA"
    )
        port map (
      I0 => do_reg2(12),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[12]_i_4__1_n_0\
    );
\di_reg[13]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \di_reg[13]_i_2__1_n_0\,
      I1 => index(4),
      I2 => \di_reg[13]_i_3__1_n_0\,
      I3 => index(3),
      I4 => \di_reg[13]_i_4__1_n_0\,
      O => di_reg(13)
    );
\di_reg[13]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080838380838"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[13]_i_2__1_n_0\
    );
\di_reg[13]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(13),
      O => \di_reg[13]_i_3__1_n_0\
    );
\di_reg[13]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAA8AAABAAA8A"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(1),
      I5 => rate_reg2(0),
      O => \di_reg[13]_i_4__1_n_0\
    );
\di_reg[14]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080008FF08000800"
    )
        port map (
      I0 => do_reg2(14),
      I1 => \di_reg[14]_i_2__1_n_0\,
      I2 => index(3),
      I3 => index(4),
      I4 => \di_reg[14]_i_3__1_n_0\,
      I5 => \di_reg[14]_i_4__1_n_0\,
      O => di_reg(14)
    );
\di_reg[14]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[14]_i_2__1_n_0\
    );
\di_reg[14]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033303310130033"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => index(2),
      I3 => do_reg2(14),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[14]_i_3__1_n_0\
    );
\di_reg[14]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000DF10"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => do_reg2(14),
      I4 => index(2),
      I5 => \di_reg[14]_i_6__1_n_0\,
      O => \di_reg[14]_i_4__1_n_0\
    );
\di_reg[14]_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      O => data15(7)
    );
\di_reg[14]_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB3BBBBBBB3FBB"
    )
        port map (
      I0 => \di_reg[14]_i_7__1_n_0\,
      I1 => index(3),
      I2 => index(0),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => \di_reg[5]_i_4__1_n_0\,
      O => \di_reg[14]_i_6__1_n_0\
    );
\di_reg[14]_i_7__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => index(1),
      I1 => index(2),
      I2 => do_reg2(14),
      I3 => index(0),
      O => \di_reg[14]_i_7__1_n_0\
    );
\di_reg[15]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(15),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[15]_i_2__1_n_0\,
      O => di_reg(15)
    );
\di_reg[15]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[15]_i_2__1_n_0\
    );
\di_reg[1]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \di_reg[1]_i_2__1_n_0\,
      I1 => index(4),
      I2 => \di_reg[1]_i_3__1_n_0\,
      I3 => \di_reg[1]_i_4__1_n_0\,
      O => di_reg(1)
    );
\di_reg[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000034140000"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(1),
      I4 => index(4),
      I5 => index(3),
      O => \di_reg[1]_i_2__1_n_0\
    );
\di_reg[1]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FB330000"
    )
        port map (
      I0 => index(2),
      I1 => do_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(3),
      I5 => \di_reg[1]_i_5__1_n_0\,
      O => \di_reg[1]_i_3__1_n_0\
    );
\di_reg[1]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFCCC5555"
    )
        port map (
      I0 => \di_reg[1]_i_6__1_n_0\,
      I1 => do_reg2(1),
      I2 => index(1),
      I3 => index(0),
      I4 => index(2),
      I5 => index(3),
      O => \di_reg[1]_i_4__1_n_0\
    );
\di_reg[1]_i_5__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      I3 => index(1),
      O => \di_reg[1]_i_5__1_n_0\
    );
\di_reg[1]_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"002F0F20F02FFF2F"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(1),
      I3 => index(0),
      I4 => mode,
      I5 => do_reg2(1),
      O => \di_reg[1]_i_6__1_n_0\
    );
\di_reg[2]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \di_reg[2]_i_2__1_n_0\,
      I1 => \di_reg[2]_i_3__1_n_0\,
      O => di_reg(2)
    );
\di_reg[2]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00400500FFFFFFFF"
    )
        port map (
      I0 => index(3),
      I1 => do_reg2(2),
      I2 => index(2),
      I3 => index(1),
      I4 => index(0),
      I5 => index(4),
      O => \di_reg[2]_i_2__1_n_0\
    );
\di_reg[2]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF470047"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => \di_reg[2]_i_4__1_n_0\,
      I3 => index(3),
      I4 => \di_reg[2]_i_5__1_n_0\,
      I5 => index(4),
      O => \di_reg[2]_i_3__1_n_0\
    );
\di_reg[2]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F40404F00FF000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => mode,
      I4 => do_reg2(2),
      I5 => index(1),
      O => \di_reg[2]_i_4__1_n_0\
    );
\di_reg[2]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5D535D5F5D5F5D5"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[2]_i_5__1_n_0\
    );
\di_reg[3]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAA1000AAFF0000"
    )
        port map (
      I0 => \di_reg[3]_i_4__1_n_0\,
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => do_reg2(3),
      I5 => index(0),
      O => \di_reg[3]_i_2__1_n_0\
    );
\di_reg[3]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000033E200"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => do_reg2(3),
      I3 => index(2),
      I4 => index(1),
      I5 => index(3),
      O => \di_reg[3]_i_3__1_n_0\
    );
\di_reg[3]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      O => \di_reg[3]_i_4__1_n_0\
    );
\di_reg[4]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[4]_i_2__1_n_0\,
      I2 => index(4),
      I3 => \di_reg[4]_i_3__1_n_0\,
      I4 => \di_reg[4]_i_4__1_n_0\,
      I5 => \di_reg[4]_i_5__1_n_0\,
      O => di_reg(4)
    );
\di_reg[4]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080B0830303030"
    )
        port map (
      I0 => do_reg2(4),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[4]_i_2__1_n_0\
    );
\di_reg[4]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFFFFFFF"
    )
        port map (
      I0 => index(0),
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => index(1),
      I5 => \di_reg[4]_i_6__1_n_0\,
      O => \di_reg[4]_i_3__1_n_0\
    );
\di_reg[4]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFFE00000000"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      I2 => index(1),
      I3 => index(2),
      I4 => index(0),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_4__1_n_0\
    );
\di_reg[4]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010C00"
    )
        port map (
      I0 => \di_reg[4]_i_7__1_n_0\,
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => \di_reg[4]_i_8__1_n_0\,
      I5 => index(3),
      O => \di_reg[4]_i_5__1_n_0\
    );
\di_reg[4]_i_6__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1F0FFF0F"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(3),
      I3 => do_reg2(4),
      I4 => index(1),
      O => \di_reg[4]_i_6__1_n_0\
    );
\di_reg[4]_i_7__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      O => \di_reg[4]_i_7__1_n_0\
    );
\di_reg[4]_i_8__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => \di_reg[4]_i_8__1_n_0\
    );
\di_reg[5]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33000000B888B888"
    )
        port map (
      I0 => \di_reg[5]_i_2__1_n_0\,
      I1 => index(4),
      I2 => \di_reg[5]_i_3__1_n_0\,
      I3 => do_reg2(5),
      I4 => \di_reg[5]_i_4__1_n_0\,
      I5 => index(3),
      O => di_reg(5)
    );
\di_reg[5]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B0B080B33333033"
    )
        port map (
      I0 => do_reg2(5),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[5]_i_2__1_n_0\
    );
\di_reg[5]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(1),
      I3 => x16x20_mode_reg2,
      I4 => mode,
      O => \di_reg[5]_i_3__1_n_0\
    );
\di_reg[5]_i_4__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[5]_i_4__1_n_0\
    );
\di_reg[6]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"67FF000067000000"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(6),
      I5 => \di_reg[5]_i_3__1_n_0\,
      O => \di_reg[6]_i_2__1_n_0\
    );
\di_reg[6]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002404"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(6),
      I4 => index(3),
      O => \di_reg[6]_i_3__1_n_0\
    );
\di_reg[7]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0900"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(7),
      O => \di_reg[7]_i_2__1_n_0\
    );
\di_reg[7]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000C320032"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => do_reg2(7),
      I5 => index(3),
      O => \di_reg[7]_i_3__1_n_0\
    );
\di_reg[8]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(8),
      O => di_reg(8)
    );
\di_reg[9]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(9),
      O => di_reg(9)
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(0),
      Q => \di_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[0]_i_1__1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[0]_i_2__1_n_0\,
      I1 => \di_reg[0]_i_3__1_n_0\,
      O => di_reg(0),
      S => index(4)
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(10),
      Q => \di_reg_reg_n_0_[10]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(11),
      Q => \di_reg_reg_n_0_[11]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(12),
      Q => \di_reg_reg_n_0_[12]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(13),
      Q => \di_reg_reg_n_0_[13]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(14),
      Q => \di_reg_reg_n_0_[14]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(15),
      Q => \di_reg_reg_n_0_[15]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(1),
      Q => \di_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(2),
      Q => \di_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(3),
      Q => \di_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]_i_1__1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[3]_i_2__1_n_0\,
      I1 => \di_reg[3]_i_3__1_n_0\,
      O => di_reg(3),
      S => index(4)
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(4),
      Q => \di_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(5),
      Q => \di_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(6),
      Q => \di_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]_i_1__1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[6]_i_2__1_n_0\,
      I1 => \di_reg[6]_i_3__1_n_0\,
      O => di_reg(6),
      S => index(4)
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(7),
      Q => \di_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[7]_i_1__1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[7]_i_2__1_n_0\,
      I1 => \di_reg[7]_i_3__1_n_0\,
      O => di_reg(7),
      S => index(4)
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(8),
      Q => \di_reg_reg_n_0_[8]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(9),
      Q => \di_reg_reg_n_0_[9]\,
      R => RST_DCLK_RESET
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(0),
      Q => do_reg1(0),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(10),
      Q => do_reg1(10),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(11),
      Q => do_reg1(11),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(12),
      Q => do_reg1(12),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(13),
      Q => do_reg1(13),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(14),
      Q => do_reg1(14),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(15),
      Q => do_reg1(15),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(1),
      Q => do_reg1(1),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(2),
      Q => do_reg1(2),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(3),
      Q => do_reg1(3),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(4),
      Q => do_reg1(4),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(5),
      Q => do_reg1(5),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(6),
      Q => do_reg1(6),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(7),
      Q => do_reg1(7),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(8),
      Q => do_reg1(8),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(9),
      Q => do_reg1(9),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => RST_DCLK_RESET
    );
\done_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => start_reg2,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \done_i_1__1_n_0\
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \done_i_1__1_n_0\,
      Q => DRP_DONE,
      R => RST_DCLK_RESET
    );
\fsm[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B3BFFFF0B3B0000"
    )
        port map (
      I0 => data4,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => rdy_reg2,
      I4 => \^q\(2),
      I5 => \fsm[0]_i_3__4_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFEFFFF"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(4),
      I3 => index(2),
      I4 => \mode_i_2__1_n_0\,
      O => data4
    );
\fsm[0]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7477FFFF7477CCCC"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \^q\(1),
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      I4 => \^q\(0),
      I5 => start_reg2,
      O => \fsm[0]_i_3__4_n_0\
    );
\fsm[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"185018501D501850"
    )
        port map (
      I0 => \^q\(2),
      I1 => rdy_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => load_cnt(0),
      I5 => load_cnt(1),
      O => fsm(1)
    );
\fsm[2]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6222"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      R => RST_DCLK_RESET
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      R => RST_DCLK_RESET
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_DCLK_RESET
    );
\gt_ch_drp_rdy[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => gt_ch_drp_rdy(0)
    );
\gtx_channel.gtxe2_channel_i_i_15__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(15),
      I1 => \di_reg_reg_n_0_[15]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(15)
    );
\gtx_channel.gtxe2_channel_i_i_16__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(14),
      I1 => \di_reg_reg_n_0_[14]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(14)
    );
\gtx_channel.gtxe2_channel_i_i_17__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(13),
      I1 => \di_reg_reg_n_0_[13]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(13)
    );
\gtx_channel.gtxe2_channel_i_i_18__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(12),
      I1 => \di_reg_reg_n_0_[12]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(12)
    );
\gtx_channel.gtxe2_channel_i_i_19__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(11),
      I1 => \di_reg_reg_n_0_[11]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(11)
    );
\gtx_channel.gtxe2_channel_i_i_20__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(10),
      I1 => \di_reg_reg_n_0_[10]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(10)
    );
\gtx_channel.gtxe2_channel_i_i_21__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(9),
      I1 => \di_reg_reg_n_0_[9]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(9)
    );
\gtx_channel.gtxe2_channel_i_i_22__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(8),
      I1 => \di_reg_reg_n_0_[8]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(8)
    );
\gtx_channel.gtxe2_channel_i_i_23__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(7),
      I1 => \di_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(7)
    );
\gtx_channel.gtxe2_channel_i_i_24__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(6),
      I1 => \di_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(6)
    );
\gtx_channel.gtxe2_channel_i_i_25__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(5),
      I1 => \di_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(5)
    );
\gtx_channel.gtxe2_channel_i_i_26__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(4),
      I1 => \di_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(4)
    );
\gtx_channel.gtxe2_channel_i_i_27__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(3),
      I1 => \di_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(3)
    );
\gtx_channel.gtxe2_channel_i_i_28__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(2),
      I1 => \di_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(2)
    );
\gtx_channel.gtxe2_channel_i_i_29__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(1),
      I1 => \di_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(1)
    );
\gtx_channel.gtxe2_channel_i_i_30__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(0),
      I1 => \di_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(0)
    );
\gtx_channel.gtxe2_channel_i_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"003E"
    )
        port map (
      I0 => ext_ch_gt_drpen(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \cplllock_reg1_reg[2]\
    );
\gtx_channel.gtxe2_channel_i_i_48__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => DRPADDR(8)
    );
\gtx_channel.gtxe2_channel_i_i_49__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(7),
      I1 => \addr_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(7)
    );
\gtx_channel.gtxe2_channel_i_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0032"
    )
        port map (
      I0 => ext_ch_gt_drpwe(0),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \cplllock_reg1_reg[2]_0\
    );
\gtx_channel.gtxe2_channel_i_i_50__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(6),
      I1 => \addr_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(6)
    );
\gtx_channel.gtxe2_channel_i_i_51__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(5),
      I1 => \addr_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(5)
    );
\gtx_channel.gtxe2_channel_i_i_52__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(4),
      I1 => \addr_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(4)
    );
\gtx_channel.gtxe2_channel_i_i_53__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(3),
      I1 => \addr_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(3)
    );
\gtx_channel.gtxe2_channel_i_i_54__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(2),
      I1 => \addr_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(2)
    );
\gtx_channel.gtxe2_channel_i_i_55__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(1),
      I1 => \addr_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(1)
    );
\gtx_channel.gtxe2_channel_i_i_56__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(0),
      I1 => \addr_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(0)
    );
gtxreset_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rst_gtreset,
      Q => gtxreset_reg1,
      R => RST_DCLK_RESET
    );
gtxreset_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => gtxreset_reg1,
      Q => gtxreset_reg2,
      R => RST_DCLK_RESET
    );
\index[0]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => index(0),
      I1 => \^q\(2),
      I2 => \index[3]_i_2__1_n_0\,
      O => \index[0]_i_1__3_n_0\
    );
\index[1]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__1_n_0\,
      I2 => index(1),
      I3 => index(0),
      O => \index[1]_i_1__3_n_0\
    );
\index[2]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02222000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__1_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      O => \index[2]_i_1__3_n_0\
    );
\index[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222222220000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__1_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => index(3),
      O => \index[3]_i_1__1_n_0\
    );
\index[3]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAE"
    )
        port map (
      I0 => \^q\(0),
      I1 => \mode_i_2__1_n_0\,
      I2 => index(2),
      I3 => index(4),
      I4 => index(1),
      I5 => index(3),
      O => \index[3]_i_2__1_n_0\
    );
\index[4]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"89"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \index[4]_i_1__1_n_0\
    );
\index[4]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => index(0),
      I1 => index(2),
      I2 => index(3),
      I3 => index(1),
      I4 => index(4),
      I5 => \index[4]_i_3__1_n_0\,
      O => \index[4]_i_2__1_n_0\
    );
\index[4]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \index[3]_i_2__1_n_0\,
      I1 => \^q\(2),
      O => \index[4]_i_3__1_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__1_n_0\,
      D => \index[0]_i_1__3_n_0\,
      Q => index(0),
      R => RST_DCLK_RESET
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__1_n_0\,
      D => \index[1]_i_1__3_n_0\,
      Q => index(1),
      R => RST_DCLK_RESET
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__1_n_0\,
      D => \index[2]_i_1__3_n_0\,
      Q => index(2),
      R => RST_DCLK_RESET
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__1_n_0\,
      D => \index[3]_i_1__1_n_0\,
      Q => index(3),
      R => RST_DCLK_RESET
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__1_n_0\,
      D => \index[4]_i_2__1_n_0\,
      Q => index(4),
      R => RST_DCLK_RESET
    );
\load_cnt[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => load_cnt(1),
      I3 => \^q\(2),
      O => \load_cnt[0]_i_1__2_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[0]_i_1__2_n_0\,
      Q => load_cnt(0),
      R => RST_DCLK_RESET
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => load_cnt(1),
      R => RST_DCLK_RESET
    );
\mode_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AAA2AAAAAAAA00"
    )
        port map (
      I0 => mode,
      I1 => \mode_i_2__1_n_0\,
      I2 => \mode_i_3__3_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \mode_i_1__1_n_0\
    );
\mode_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCB8"
    )
        port map (
      I0 => mode,
      I1 => index(0),
      I2 => x16x20_mode_reg2,
      I3 => index(2),
      O => \mode_i_2__1_n_0\
    );
\mode_i_3__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF6"
    )
        port map (
      I0 => index(2),
      I1 => index(4),
      I2 => index(1),
      I3 => index(3),
      O => \mode_i_3__3_n_0\
    );
mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \mode_i_1__1_n_0\,
      Q => mode,
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_reg1(0),
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => RST_DCLK_RESET
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drprdy(0),
      Q => rdy_reg1,
      R => RST_DCLK_RESET
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => RST_DCLK_RESET
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_START,
      Q => start_reg1,
      R => RST_DCLK_RESET
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => RST_DCLK_RESET
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16,
      Q => x16_reg1,
      R => RST_DCLK_RESET
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16X20_MODE,
      Q => x16x20_mode_reg1,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16x20_mode_reg1,
      Q => x16x20_mode_reg2,
      R => RST_DCLK_RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_42 is
  port (
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    \cplllock_reg1_reg[3]_0\ : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_DONE : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 );
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_X16X20_MODE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    ext_ch_gt_drprdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DRP_X16 : in STD_LOGIC;
    ext_ch_gt_drpdo : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rst_gtreset : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_42 : entity is "PCIeGen1x8If64_pipe_drp";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_42;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_42 is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \addr_reg[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \addr_reg[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \addr_reg[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \addr_reg[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \addr_reg[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \addr_reg[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_2__2_n_0\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal data15 : STD_LOGIC_VECTOR ( 7 to 7 );
  signal data4 : STD_LOGIC;
  signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di_reg[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_4__2_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_5__2_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_6__2_n_0\ : STD_LOGIC;
  signal \di_reg[10]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_4__2_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_5__2_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_4__2_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_4__2_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_4__2_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_6__2_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_7__2_n_0\ : STD_LOGIC;
  signal \di_reg[15]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_4__2_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_5__2_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_6__2_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_4__2_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_5__2_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_4__2_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_4__2_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_5__2_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_6__2_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_7__2_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_8__2_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_4__2_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_2__2_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_3__2_n_0\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[9]\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \done_i_1__2_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm[0]_i_3__6_n_0\ : STD_LOGIC;
  signal gtxreset_reg1 : STD_LOGIC;
  signal gtxreset_reg2 : STD_LOGIC;
  signal index : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \index[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \index[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \index[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \index[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \index[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \index[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \index[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \index[4]_i_3__2_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1__3_n_0\ : STD_LOGIC;
  signal mode : STD_LOGIC;
  signal \mode_i_1__2_n_0\ : STD_LOGIC;
  signal \mode_i_2__2_n_0\ : STD_LOGIC;
  signal \mode_i_3__4_n_0\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rdy_reg1 : STD_LOGIC;
  signal rdy_reg2 : STD_LOGIC;
  signal start_reg1 : STD_LOGIC;
  signal start_reg2 : STD_LOGIC;
  signal x16_reg1 : STD_LOGIC;
  signal x16_reg2 : STD_LOGIC;
  signal x16x20_mode_reg1 : STD_LOGIC;
  signal x16x20_mode_reg2 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \di_reg[0]_i_5__2\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \di_reg[0]_i_6__2\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \di_reg[14]_i_2__2\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \di_reg[3]_i_4__2\ : label is "soft_lutpair96";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \fsm[0]_i_2__2\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \gt_ch_drp_rdy[3]_INST_0\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__2\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_48__4\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__2\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_51__2\ : label is "soft_lutpair89";
  attribute ASYNC_REG of gtxreset_reg1_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg1_reg : label is "yes";
  attribute ASYNC_REG of gtxreset_reg2_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \index[0]_i_1__4\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \index[1]_i_1__4\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \index[2]_i_1__4\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \index[4]_i_3__2\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1__3\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \mode_i_3__4\ : label is "soft_lutpair91";
  attribute ASYNC_REG of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute ASYNC_REG of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute ASYNC_REG of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg2_reg : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\addr_reg[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1471357514713564"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__2_n_0\,
      O => \addr_reg[0]_i_1__2_n_0\
    );
\addr_reg[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404050500F0F0500"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[1]_i_1__2_n_0\
    );
\addr_reg[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"051005105A055A00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(2),
      I4 => mode,
      I5 => index(1),
      O => \addr_reg[2]_i_1__2_n_0\
    );
\addr_reg[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5767576753275326"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => \addr_reg[4]_i_2__2_n_0\,
      I5 => index(0),
      O => \addr_reg[3]_i_1__2_n_0\
    );
\addr_reg[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FCCFFF01"
    )
        port map (
      I0 => \addr_reg[4]_i_2__2_n_0\,
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => index(4),
      O => \addr_reg[4]_i_1__2_n_0\
    );
\addr_reg[4]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      O => \addr_reg[4]_i_2__2_n_0\
    );
\addr_reg[5]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001A1A0F0F0F0A"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[5]_i_1__2_n_0\
    );
\addr_reg[6]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011545554"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => mode,
      I3 => index(3),
      I4 => index(0),
      I5 => index(4),
      O => \addr_reg[6]_i_1__2_n_0\
    );
\addr_reg[7]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5422262254222633"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__2_n_0\,
      O => \addr_reg[7]_i_1__2_n_0\
    );
\addr_reg[7]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CE"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      I2 => index(0),
      O => \addr_reg[7]_i_2__2_n_0\
    );
\addr_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[0]_i_1__2_n_0\,
      Q => \addr_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[1]_i_1__2_n_0\,
      Q => \addr_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[2]_i_1__2_n_0\,
      Q => \addr_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[3]_i_1__2_n_0\,
      Q => \addr_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[4]_i_1__2_n_0\,
      Q => \addr_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[5]_i_1__2_n_0\,
      Q => \addr_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[6]_i_1__2_n_0\,
      Q => \addr_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[7]_i_1__2_n_0\,
      Q => \addr_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg[0]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B8BBB8B8B888"
    )
        port map (
      I0 => \di_reg[0]_i_4__2_n_0\,
      I1 => index(3),
      I2 => do_reg2(0),
      I3 => \di_reg[0]_i_5__2_n_0\,
      I4 => \di_reg[0]_i_6__2_n_0\,
      I5 => \di_reg[4]_i_8__2_n_0\,
      O => \di_reg[0]_i_2__2_n_0\
    );
\di_reg[0]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003414"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(0),
      I4 => index(3),
      O => \di_reg[0]_i_3__2_n_0\
    );
\di_reg[0]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0BFFFFFB0B00000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => do_reg2(0),
      O => \di_reg[0]_i_4__2_n_0\
    );
\di_reg[0]_i_5__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      O => \di_reg[0]_i_5__2_n_0\
    );
\di_reg[0]_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => index(1),
      I1 => mode,
      I2 => index(0),
      O => \di_reg[0]_i_6__2_n_0\
    );
\di_reg[10]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(10),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[10]_i_2__2_n_0\,
      O => di_reg(10)
    );
\di_reg[10]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[10]_i_2__2_n_0\
    );
\di_reg[11]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[11]_i_2__2_n_0\,
      I2 => index(4),
      I3 => \di_reg[11]_i_3__2_n_0\,
      I4 => \di_reg[11]_i_4__2_n_0\,
      I5 => \di_reg[11]_i_5__2_n_0\,
      O => di_reg(11)
    );
\di_reg[11]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808380808"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(0),
      I4 => rate_reg2(1),
      I5 => index(0),
      O => \di_reg[11]_i_2__2_n_0\
    );
\di_reg[11]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC0CCC0C0C0C880C"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => do_reg2(11),
      I3 => index(2),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[11]_i_3__2_n_0\
    );
\di_reg[11]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAABAAABA"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[11]_i_4__2_n_0\
    );
\di_reg[11]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA00AAAAAAA3"
    )
        port map (
      I0 => do_reg2(11),
      I1 => x16_reg2,
      I2 => \addr_reg[4]_i_2__2_n_0\,
      I3 => index(0),
      I4 => index(1),
      I5 => index(2),
      O => \di_reg[11]_i_5__2_n_0\
    );
\di_reg[12]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \di_reg[12]_i_2__2_n_0\,
      I1 => index(4),
      I2 => \di_reg[12]_i_3__2_n_0\,
      I3 => index(3),
      I4 => \di_reg[12]_i_4__2_n_0\,
      O => di_reg(12)
    );
\di_reg[12]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003202"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(12),
      I4 => index(3),
      O => \di_reg[12]_i_2__2_n_0\
    );
\di_reg[12]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(12),
      O => \di_reg[12]_i_3__2_n_0\
    );
\di_reg[12]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAA8AAABAAABA"
    )
        port map (
      I0 => do_reg2(12),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[12]_i_4__2_n_0\
    );
\di_reg[13]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \di_reg[13]_i_2__2_n_0\,
      I1 => index(4),
      I2 => \di_reg[13]_i_3__2_n_0\,
      I3 => index(3),
      I4 => \di_reg[13]_i_4__2_n_0\,
      O => di_reg(13)
    );
\di_reg[13]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080838380838"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[13]_i_2__2_n_0\
    );
\di_reg[13]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(13),
      O => \di_reg[13]_i_3__2_n_0\
    );
\di_reg[13]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAA8AAABAAA8A"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(1),
      I5 => rate_reg2(0),
      O => \di_reg[13]_i_4__2_n_0\
    );
\di_reg[14]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080008FF08000800"
    )
        port map (
      I0 => do_reg2(14),
      I1 => \di_reg[14]_i_2__2_n_0\,
      I2 => index(3),
      I3 => index(4),
      I4 => \di_reg[14]_i_3__2_n_0\,
      I5 => \di_reg[14]_i_4__2_n_0\,
      O => di_reg(14)
    );
\di_reg[14]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[14]_i_2__2_n_0\
    );
\di_reg[14]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033303310130033"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => index(2),
      I3 => do_reg2(14),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[14]_i_3__2_n_0\
    );
\di_reg[14]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000DF10"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => do_reg2(14),
      I4 => index(2),
      I5 => \di_reg[14]_i_6__2_n_0\,
      O => \di_reg[14]_i_4__2_n_0\
    );
\di_reg[14]_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      O => data15(7)
    );
\di_reg[14]_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB3BBBBBBB3FBB"
    )
        port map (
      I0 => \di_reg[14]_i_7__2_n_0\,
      I1 => index(3),
      I2 => index(0),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => \di_reg[5]_i_4__2_n_0\,
      O => \di_reg[14]_i_6__2_n_0\
    );
\di_reg[14]_i_7__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => index(1),
      I1 => index(2),
      I2 => do_reg2(14),
      I3 => index(0),
      O => \di_reg[14]_i_7__2_n_0\
    );
\di_reg[15]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(15),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[15]_i_2__2_n_0\,
      O => di_reg(15)
    );
\di_reg[15]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[15]_i_2__2_n_0\
    );
\di_reg[1]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \di_reg[1]_i_2__2_n_0\,
      I1 => index(4),
      I2 => \di_reg[1]_i_3__2_n_0\,
      I3 => \di_reg[1]_i_4__2_n_0\,
      O => di_reg(1)
    );
\di_reg[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000034140000"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(1),
      I4 => index(4),
      I5 => index(3),
      O => \di_reg[1]_i_2__2_n_0\
    );
\di_reg[1]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FB330000"
    )
        port map (
      I0 => index(2),
      I1 => do_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(3),
      I5 => \di_reg[1]_i_5__2_n_0\,
      O => \di_reg[1]_i_3__2_n_0\
    );
\di_reg[1]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFCCC5555"
    )
        port map (
      I0 => \di_reg[1]_i_6__2_n_0\,
      I1 => do_reg2(1),
      I2 => index(1),
      I3 => index(0),
      I4 => index(2),
      I5 => index(3),
      O => \di_reg[1]_i_4__2_n_0\
    );
\di_reg[1]_i_5__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      I3 => index(1),
      O => \di_reg[1]_i_5__2_n_0\
    );
\di_reg[1]_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"002F0F20F02FFF2F"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(1),
      I3 => index(0),
      I4 => mode,
      I5 => do_reg2(1),
      O => \di_reg[1]_i_6__2_n_0\
    );
\di_reg[2]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \di_reg[2]_i_2__2_n_0\,
      I1 => \di_reg[2]_i_3__2_n_0\,
      O => di_reg(2)
    );
\di_reg[2]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00400500FFFFFFFF"
    )
        port map (
      I0 => index(3),
      I1 => do_reg2(2),
      I2 => index(2),
      I3 => index(1),
      I4 => index(0),
      I5 => index(4),
      O => \di_reg[2]_i_2__2_n_0\
    );
\di_reg[2]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF470047"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => \di_reg[2]_i_4__2_n_0\,
      I3 => index(3),
      I4 => \di_reg[2]_i_5__2_n_0\,
      I5 => index(4),
      O => \di_reg[2]_i_3__2_n_0\
    );
\di_reg[2]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F40404F00FF000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => mode,
      I4 => do_reg2(2),
      I5 => index(1),
      O => \di_reg[2]_i_4__2_n_0\
    );
\di_reg[2]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5D535D5F5D5F5D5"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[2]_i_5__2_n_0\
    );
\di_reg[3]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAA1000AAFF0000"
    )
        port map (
      I0 => \di_reg[3]_i_4__2_n_0\,
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => do_reg2(3),
      I5 => index(0),
      O => \di_reg[3]_i_2__2_n_0\
    );
\di_reg[3]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000033E200"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => do_reg2(3),
      I3 => index(2),
      I4 => index(1),
      I5 => index(3),
      O => \di_reg[3]_i_3__2_n_0\
    );
\di_reg[3]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      O => \di_reg[3]_i_4__2_n_0\
    );
\di_reg[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[4]_i_2__2_n_0\,
      I2 => index(4),
      I3 => \di_reg[4]_i_3__2_n_0\,
      I4 => \di_reg[4]_i_4__2_n_0\,
      I5 => \di_reg[4]_i_5__2_n_0\,
      O => di_reg(4)
    );
\di_reg[4]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080B0830303030"
    )
        port map (
      I0 => do_reg2(4),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[4]_i_2__2_n_0\
    );
\di_reg[4]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFFFFFFF"
    )
        port map (
      I0 => index(0),
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => index(1),
      I5 => \di_reg[4]_i_6__2_n_0\,
      O => \di_reg[4]_i_3__2_n_0\
    );
\di_reg[4]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFFE00000000"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      I2 => index(1),
      I3 => index(2),
      I4 => index(0),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_4__2_n_0\
    );
\di_reg[4]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010C00"
    )
        port map (
      I0 => \di_reg[4]_i_7__2_n_0\,
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => \di_reg[4]_i_8__2_n_0\,
      I5 => index(3),
      O => \di_reg[4]_i_5__2_n_0\
    );
\di_reg[4]_i_6__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1F0FFF0F"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(3),
      I3 => do_reg2(4),
      I4 => index(1),
      O => \di_reg[4]_i_6__2_n_0\
    );
\di_reg[4]_i_7__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      O => \di_reg[4]_i_7__2_n_0\
    );
\di_reg[4]_i_8__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => \di_reg[4]_i_8__2_n_0\
    );
\di_reg[5]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33000000B888B888"
    )
        port map (
      I0 => \di_reg[5]_i_2__2_n_0\,
      I1 => index(4),
      I2 => \di_reg[5]_i_3__2_n_0\,
      I3 => do_reg2(5),
      I4 => \di_reg[5]_i_4__2_n_0\,
      I5 => index(3),
      O => di_reg(5)
    );
\di_reg[5]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B0B080B33333033"
    )
        port map (
      I0 => do_reg2(5),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[5]_i_2__2_n_0\
    );
\di_reg[5]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(1),
      I3 => x16x20_mode_reg2,
      I4 => mode,
      O => \di_reg[5]_i_3__2_n_0\
    );
\di_reg[5]_i_4__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[5]_i_4__2_n_0\
    );
\di_reg[6]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"67FF000067000000"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(6),
      I5 => \di_reg[5]_i_3__2_n_0\,
      O => \di_reg[6]_i_2__2_n_0\
    );
\di_reg[6]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002404"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(6),
      I4 => index(3),
      O => \di_reg[6]_i_3__2_n_0\
    );
\di_reg[7]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0900"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(7),
      O => \di_reg[7]_i_2__2_n_0\
    );
\di_reg[7]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000C320032"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => do_reg2(7),
      I5 => index(3),
      O => \di_reg[7]_i_3__2_n_0\
    );
\di_reg[8]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(8),
      O => di_reg(8)
    );
\di_reg[9]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(9),
      O => di_reg(9)
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(0),
      Q => \di_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[0]_i_1__2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[0]_i_2__2_n_0\,
      I1 => \di_reg[0]_i_3__2_n_0\,
      O => di_reg(0),
      S => index(4)
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(10),
      Q => \di_reg_reg_n_0_[10]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(11),
      Q => \di_reg_reg_n_0_[11]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(12),
      Q => \di_reg_reg_n_0_[12]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(13),
      Q => \di_reg_reg_n_0_[13]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(14),
      Q => \di_reg_reg_n_0_[14]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(15),
      Q => \di_reg_reg_n_0_[15]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(1),
      Q => \di_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(2),
      Q => \di_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(3),
      Q => \di_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]_i_1__2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[3]_i_2__2_n_0\,
      I1 => \di_reg[3]_i_3__2_n_0\,
      O => di_reg(3),
      S => index(4)
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(4),
      Q => \di_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(5),
      Q => \di_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(6),
      Q => \di_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]_i_1__2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[6]_i_2__2_n_0\,
      I1 => \di_reg[6]_i_3__2_n_0\,
      O => di_reg(6),
      S => index(4)
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(7),
      Q => \di_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[7]_i_1__2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[7]_i_2__2_n_0\,
      I1 => \di_reg[7]_i_3__2_n_0\,
      O => di_reg(7),
      S => index(4)
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(8),
      Q => \di_reg_reg_n_0_[8]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(9),
      Q => \di_reg_reg_n_0_[9]\,
      R => RST_DCLK_RESET
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(0),
      Q => do_reg1(0),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(10),
      Q => do_reg1(10),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(11),
      Q => do_reg1(11),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(12),
      Q => do_reg1(12),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(13),
      Q => do_reg1(13),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(14),
      Q => do_reg1(14),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(15),
      Q => do_reg1(15),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(1),
      Q => do_reg1(1),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(2),
      Q => do_reg1(2),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(3),
      Q => do_reg1(3),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(4),
      Q => do_reg1(4),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(5),
      Q => do_reg1(5),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(6),
      Q => do_reg1(6),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(7),
      Q => do_reg1(7),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(8),
      Q => do_reg1(8),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(9),
      Q => do_reg1(9),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => RST_DCLK_RESET
    );
\done_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => start_reg2,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \done_i_1__2_n_0\
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \done_i_1__2_n_0\,
      Q => DRP_DONE,
      R => RST_DCLK_RESET
    );
\fsm[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B3BFFFF0B3B0000"
    )
        port map (
      I0 => data4,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => rdy_reg2,
      I4 => \^q\(2),
      I5 => \fsm[0]_i_3__6_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFEFFFF"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(4),
      I3 => index(2),
      I4 => \mode_i_2__2_n_0\,
      O => data4
    );
\fsm[0]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7477FFFF7477CCCC"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \^q\(1),
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      I4 => \^q\(0),
      I5 => start_reg2,
      O => \fsm[0]_i_3__6_n_0\
    );
\fsm[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"185018501D501850"
    )
        port map (
      I0 => \^q\(2),
      I1 => rdy_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => load_cnt(0),
      I5 => load_cnt(1),
      O => fsm(1)
    );
\fsm[2]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6222"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      R => RST_DCLK_RESET
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      R => RST_DCLK_RESET
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_DCLK_RESET
    );
\gt_ch_drp_rdy[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => gt_ch_drp_rdy(0)
    );
\gtx_channel.gtxe2_channel_i_i_15__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(15),
      I1 => \di_reg_reg_n_0_[15]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(15)
    );
\gtx_channel.gtxe2_channel_i_i_16__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(14),
      I1 => \di_reg_reg_n_0_[14]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(14)
    );
\gtx_channel.gtxe2_channel_i_i_17__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(13),
      I1 => \di_reg_reg_n_0_[13]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(13)
    );
\gtx_channel.gtxe2_channel_i_i_18__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(12),
      I1 => \di_reg_reg_n_0_[12]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(12)
    );
\gtx_channel.gtxe2_channel_i_i_19__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(11),
      I1 => \di_reg_reg_n_0_[11]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(11)
    );
\gtx_channel.gtxe2_channel_i_i_20__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(10),
      I1 => \di_reg_reg_n_0_[10]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(10)
    );
\gtx_channel.gtxe2_channel_i_i_21__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(9),
      I1 => \di_reg_reg_n_0_[9]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(9)
    );
\gtx_channel.gtxe2_channel_i_i_22__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(8),
      I1 => \di_reg_reg_n_0_[8]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(8)
    );
\gtx_channel.gtxe2_channel_i_i_23__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(7),
      I1 => \di_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(7)
    );
\gtx_channel.gtxe2_channel_i_i_24__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(6),
      I1 => \di_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(6)
    );
\gtx_channel.gtxe2_channel_i_i_25__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(5),
      I1 => \di_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(5)
    );
\gtx_channel.gtxe2_channel_i_i_26__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(4),
      I1 => \di_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(4)
    );
\gtx_channel.gtxe2_channel_i_i_27__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(3),
      I1 => \di_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(3)
    );
\gtx_channel.gtxe2_channel_i_i_28__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(2),
      I1 => \di_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(2)
    );
\gtx_channel.gtxe2_channel_i_i_29__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(1),
      I1 => \di_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(1)
    );
\gtx_channel.gtxe2_channel_i_i_30__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(0),
      I1 => \di_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(0)
    );
\gtx_channel.gtxe2_channel_i_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"003E"
    )
        port map (
      I0 => ext_ch_gt_drpen(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \cplllock_reg1_reg[3]\
    );
\gtx_channel.gtxe2_channel_i_i_48__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => DRPADDR(8)
    );
\gtx_channel.gtxe2_channel_i_i_49__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(7),
      I1 => \addr_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(7)
    );
\gtx_channel.gtxe2_channel_i_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0032"
    )
        port map (
      I0 => ext_ch_gt_drpwe(0),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \cplllock_reg1_reg[3]_0\
    );
\gtx_channel.gtxe2_channel_i_i_50__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(6),
      I1 => \addr_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(6)
    );
\gtx_channel.gtxe2_channel_i_i_51__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(5),
      I1 => \addr_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(5)
    );
\gtx_channel.gtxe2_channel_i_i_52__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(4),
      I1 => \addr_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(4)
    );
\gtx_channel.gtxe2_channel_i_i_53__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(3),
      I1 => \addr_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(3)
    );
\gtx_channel.gtxe2_channel_i_i_54__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(2),
      I1 => \addr_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(2)
    );
\gtx_channel.gtxe2_channel_i_i_55__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(1),
      I1 => \addr_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(1)
    );
\gtx_channel.gtxe2_channel_i_i_56__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(0),
      I1 => \addr_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(0)
    );
gtxreset_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rst_gtreset,
      Q => gtxreset_reg1,
      R => RST_DCLK_RESET
    );
gtxreset_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => gtxreset_reg1,
      Q => gtxreset_reg2,
      R => RST_DCLK_RESET
    );
\index[0]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => index(0),
      I1 => \^q\(2),
      I2 => \index[3]_i_2__2_n_0\,
      O => \index[0]_i_1__4_n_0\
    );
\index[1]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__2_n_0\,
      I2 => index(1),
      I3 => index(0),
      O => \index[1]_i_1__4_n_0\
    );
\index[2]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02222000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__2_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      O => \index[2]_i_1__4_n_0\
    );
\index[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222222220000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__2_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => index(3),
      O => \index[3]_i_1__2_n_0\
    );
\index[3]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAE"
    )
        port map (
      I0 => \^q\(0),
      I1 => \mode_i_2__2_n_0\,
      I2 => index(2),
      I3 => index(4),
      I4 => index(1),
      I5 => index(3),
      O => \index[3]_i_2__2_n_0\
    );
\index[4]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"89"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \index[4]_i_1__2_n_0\
    );
\index[4]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => index(0),
      I1 => index(2),
      I2 => index(3),
      I3 => index(1),
      I4 => index(4),
      I5 => \index[4]_i_3__2_n_0\,
      O => \index[4]_i_2__2_n_0\
    );
\index[4]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \index[3]_i_2__2_n_0\,
      I1 => \^q\(2),
      O => \index[4]_i_3__2_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__2_n_0\,
      D => \index[0]_i_1__4_n_0\,
      Q => index(0),
      R => RST_DCLK_RESET
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__2_n_0\,
      D => \index[1]_i_1__4_n_0\,
      Q => index(1),
      R => RST_DCLK_RESET
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__2_n_0\,
      D => \index[2]_i_1__4_n_0\,
      Q => index(2),
      R => RST_DCLK_RESET
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__2_n_0\,
      D => \index[3]_i_1__2_n_0\,
      Q => index(3),
      R => RST_DCLK_RESET
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__2_n_0\,
      D => \index[4]_i_2__2_n_0\,
      Q => index(4),
      R => RST_DCLK_RESET
    );
\load_cnt[0]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => load_cnt(1),
      I3 => \^q\(2),
      O => \load_cnt[0]_i_1__3_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[0]_i_1__3_n_0\,
      Q => load_cnt(0),
      R => RST_DCLK_RESET
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => load_cnt(1),
      R => RST_DCLK_RESET
    );
\mode_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AAA2AAAAAAAA00"
    )
        port map (
      I0 => mode,
      I1 => \mode_i_2__2_n_0\,
      I2 => \mode_i_3__4_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \mode_i_1__2_n_0\
    );
\mode_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCB8"
    )
        port map (
      I0 => mode,
      I1 => index(0),
      I2 => x16x20_mode_reg2,
      I3 => index(2),
      O => \mode_i_2__2_n_0\
    );
\mode_i_3__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF6"
    )
        port map (
      I0 => index(2),
      I1 => index(4),
      I2 => index(1),
      I3 => index(3),
      O => \mode_i_3__4_n_0\
    );
mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \mode_i_1__2_n_0\,
      Q => mode,
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_reg1(0),
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => RST_DCLK_RESET
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drprdy(0),
      Q => rdy_reg1,
      R => RST_DCLK_RESET
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => RST_DCLK_RESET
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_START,
      Q => start_reg1,
      R => RST_DCLK_RESET
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => RST_DCLK_RESET
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16,
      Q => x16_reg1,
      R => RST_DCLK_RESET
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16X20_MODE,
      Q => x16x20_mode_reg1,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16x20_mode_reg1,
      Q => x16x20_mode_reg2,
      R => RST_DCLK_RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_48 is
  port (
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \cplllock_reg1_reg[4]\ : out STD_LOGIC;
    \cplllock_reg1_reg[4]_0\ : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_DONE : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 );
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_X16X20_MODE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    ext_ch_gt_drprdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DRP_X16 : in STD_LOGIC;
    ext_ch_gt_drpdo : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rst_gtreset : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_48 : entity is "PCIeGen1x8If64_pipe_drp";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_48;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_48 is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \addr_reg[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \addr_reg[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \addr_reg[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \addr_reg[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \addr_reg[5]_i_1__3_n_0\ : STD_LOGIC;
  signal \addr_reg[6]_i_1__3_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_1__3_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_2__3_n_0\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal data15 : STD_LOGIC_VECTOR ( 7 to 7 );
  signal data4 : STD_LOGIC;
  signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di_reg[0]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_4__3_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_5__3_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_6__3_n_0\ : STD_LOGIC;
  signal \di_reg[10]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_4__3_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_5__3_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_4__3_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_4__3_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_4__3_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_6__3_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_7__3_n_0\ : STD_LOGIC;
  signal \di_reg[15]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_4__3_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_5__3_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_6__3_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_4__3_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_5__3_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_4__3_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_4__3_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_5__3_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_6__3_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_7__3_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_8__3_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_4__3_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_2__3_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_3__3_n_0\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[9]\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \done_i_1__3_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm[0]_i_3__8_n_0\ : STD_LOGIC;
  signal gtxreset_reg1 : STD_LOGIC;
  signal gtxreset_reg2 : STD_LOGIC;
  signal index : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \index[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \index[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \index[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \index[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \index[3]_i_2__3_n_0\ : STD_LOGIC;
  signal \index[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \index[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \index[4]_i_3__3_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1__4_n_0\ : STD_LOGIC;
  signal mode : STD_LOGIC;
  signal \mode_i_1__3_n_0\ : STD_LOGIC;
  signal \mode_i_2__3_n_0\ : STD_LOGIC;
  signal \mode_i_3__5_n_0\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rdy_reg1 : STD_LOGIC;
  signal rdy_reg2 : STD_LOGIC;
  signal start_reg1 : STD_LOGIC;
  signal start_reg2 : STD_LOGIC;
  signal x16_reg1 : STD_LOGIC;
  signal x16_reg2 : STD_LOGIC;
  signal x16x20_mode_reg1 : STD_LOGIC;
  signal x16x20_mode_reg2 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \di_reg[0]_i_5__3\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \di_reg[0]_i_6__3\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \di_reg[14]_i_2__3\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \di_reg[3]_i_4__3\ : label is "soft_lutpair118";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \fsm[0]_i_2__3\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \gt_ch_drp_rdy[4]_INST_0\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__3\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_47__5\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__3\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_50__3\ : label is "soft_lutpair111";
  attribute ASYNC_REG of gtxreset_reg1_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg1_reg : label is "yes";
  attribute ASYNC_REG of gtxreset_reg2_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \index[0]_i_1__5\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \index[1]_i_1__5\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \index[2]_i_1__5\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \index[4]_i_3__3\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1__4\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \mode_i_3__5\ : label is "soft_lutpair113";
  attribute ASYNC_REG of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute ASYNC_REG of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute ASYNC_REG of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg2_reg : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\addr_reg[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1471357514713564"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__3_n_0\,
      O => \addr_reg[0]_i_1__3_n_0\
    );
\addr_reg[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404050500F0F0500"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[1]_i_1__3_n_0\
    );
\addr_reg[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"051005105A055A00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(2),
      I4 => mode,
      I5 => index(1),
      O => \addr_reg[2]_i_1__3_n_0\
    );
\addr_reg[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5767576753275326"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => \addr_reg[4]_i_2__3_n_0\,
      I5 => index(0),
      O => \addr_reg[3]_i_1__3_n_0\
    );
\addr_reg[4]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FCCFFF01"
    )
        port map (
      I0 => \addr_reg[4]_i_2__3_n_0\,
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => index(4),
      O => \addr_reg[4]_i_1__3_n_0\
    );
\addr_reg[4]_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      O => \addr_reg[4]_i_2__3_n_0\
    );
\addr_reg[5]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001A1A0F0F0F0A"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[5]_i_1__3_n_0\
    );
\addr_reg[6]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011545554"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => mode,
      I3 => index(3),
      I4 => index(0),
      I5 => index(4),
      O => \addr_reg[6]_i_1__3_n_0\
    );
\addr_reg[7]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5422262254222633"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__3_n_0\,
      O => \addr_reg[7]_i_1__3_n_0\
    );
\addr_reg[7]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CE"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      I2 => index(0),
      O => \addr_reg[7]_i_2__3_n_0\
    );
\addr_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[0]_i_1__3_n_0\,
      Q => \addr_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[1]_i_1__3_n_0\,
      Q => \addr_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[2]_i_1__3_n_0\,
      Q => \addr_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[3]_i_1__3_n_0\,
      Q => \addr_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[4]_i_1__3_n_0\,
      Q => \addr_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[5]_i_1__3_n_0\,
      Q => \addr_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[6]_i_1__3_n_0\,
      Q => \addr_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[7]_i_1__3_n_0\,
      Q => \addr_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg[0]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B8BBB8B8B888"
    )
        port map (
      I0 => \di_reg[0]_i_4__3_n_0\,
      I1 => index(3),
      I2 => do_reg2(0),
      I3 => \di_reg[0]_i_5__3_n_0\,
      I4 => \di_reg[0]_i_6__3_n_0\,
      I5 => \di_reg[4]_i_8__3_n_0\,
      O => \di_reg[0]_i_2__3_n_0\
    );
\di_reg[0]_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003414"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(0),
      I4 => index(3),
      O => \di_reg[0]_i_3__3_n_0\
    );
\di_reg[0]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0BFFFFFB0B00000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => do_reg2(0),
      O => \di_reg[0]_i_4__3_n_0\
    );
\di_reg[0]_i_5__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      O => \di_reg[0]_i_5__3_n_0\
    );
\di_reg[0]_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => index(1),
      I1 => mode,
      I2 => index(0),
      O => \di_reg[0]_i_6__3_n_0\
    );
\di_reg[10]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(10),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[10]_i_2__3_n_0\,
      O => di_reg(10)
    );
\di_reg[10]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[10]_i_2__3_n_0\
    );
\di_reg[11]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[11]_i_2__3_n_0\,
      I2 => index(4),
      I3 => \di_reg[11]_i_3__3_n_0\,
      I4 => \di_reg[11]_i_4__3_n_0\,
      I5 => \di_reg[11]_i_5__3_n_0\,
      O => di_reg(11)
    );
\di_reg[11]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808380808"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(0),
      I4 => rate_reg2(1),
      I5 => index(0),
      O => \di_reg[11]_i_2__3_n_0\
    );
\di_reg[11]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC0CCC0C0C0C880C"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => do_reg2(11),
      I3 => index(2),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[11]_i_3__3_n_0\
    );
\di_reg[11]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAABAAABA"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[11]_i_4__3_n_0\
    );
\di_reg[11]_i_5__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA00AAAAAAA3"
    )
        port map (
      I0 => do_reg2(11),
      I1 => x16_reg2,
      I2 => \addr_reg[4]_i_2__3_n_0\,
      I3 => index(0),
      I4 => index(1),
      I5 => index(2),
      O => \di_reg[11]_i_5__3_n_0\
    );
\di_reg[12]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \di_reg[12]_i_2__3_n_0\,
      I1 => index(4),
      I2 => \di_reg[12]_i_3__3_n_0\,
      I3 => index(3),
      I4 => \di_reg[12]_i_4__3_n_0\,
      O => di_reg(12)
    );
\di_reg[12]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003202"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(12),
      I4 => index(3),
      O => \di_reg[12]_i_2__3_n_0\
    );
\di_reg[12]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(12),
      O => \di_reg[12]_i_3__3_n_0\
    );
\di_reg[12]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAA8AAABAAABA"
    )
        port map (
      I0 => do_reg2(12),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[12]_i_4__3_n_0\
    );
\di_reg[13]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \di_reg[13]_i_2__3_n_0\,
      I1 => index(4),
      I2 => \di_reg[13]_i_3__3_n_0\,
      I3 => index(3),
      I4 => \di_reg[13]_i_4__3_n_0\,
      O => di_reg(13)
    );
\di_reg[13]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080838380838"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[13]_i_2__3_n_0\
    );
\di_reg[13]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(13),
      O => \di_reg[13]_i_3__3_n_0\
    );
\di_reg[13]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAA8AAABAAA8A"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(1),
      I5 => rate_reg2(0),
      O => \di_reg[13]_i_4__3_n_0\
    );
\di_reg[14]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080008FF08000800"
    )
        port map (
      I0 => do_reg2(14),
      I1 => \di_reg[14]_i_2__3_n_0\,
      I2 => index(3),
      I3 => index(4),
      I4 => \di_reg[14]_i_3__3_n_0\,
      I5 => \di_reg[14]_i_4__3_n_0\,
      O => di_reg(14)
    );
\di_reg[14]_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[14]_i_2__3_n_0\
    );
\di_reg[14]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033303310130033"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => index(2),
      I3 => do_reg2(14),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[14]_i_3__3_n_0\
    );
\di_reg[14]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000DF10"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => do_reg2(14),
      I4 => index(2),
      I5 => \di_reg[14]_i_6__3_n_0\,
      O => \di_reg[14]_i_4__3_n_0\
    );
\di_reg[14]_i_5__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      O => data15(7)
    );
\di_reg[14]_i_6__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB3BBBBBBB3FBB"
    )
        port map (
      I0 => \di_reg[14]_i_7__3_n_0\,
      I1 => index(3),
      I2 => index(0),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => \di_reg[5]_i_4__3_n_0\,
      O => \di_reg[14]_i_6__3_n_0\
    );
\di_reg[14]_i_7__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => index(1),
      I1 => index(2),
      I2 => do_reg2(14),
      I3 => index(0),
      O => \di_reg[14]_i_7__3_n_0\
    );
\di_reg[15]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(15),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[15]_i_2__3_n_0\,
      O => di_reg(15)
    );
\di_reg[15]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[15]_i_2__3_n_0\
    );
\di_reg[1]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \di_reg[1]_i_2__3_n_0\,
      I1 => index(4),
      I2 => \di_reg[1]_i_3__3_n_0\,
      I3 => \di_reg[1]_i_4__3_n_0\,
      O => di_reg(1)
    );
\di_reg[1]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000034140000"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(1),
      I4 => index(4),
      I5 => index(3),
      O => \di_reg[1]_i_2__3_n_0\
    );
\di_reg[1]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FB330000"
    )
        port map (
      I0 => index(2),
      I1 => do_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(3),
      I5 => \di_reg[1]_i_5__3_n_0\,
      O => \di_reg[1]_i_3__3_n_0\
    );
\di_reg[1]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFCCC5555"
    )
        port map (
      I0 => \di_reg[1]_i_6__3_n_0\,
      I1 => do_reg2(1),
      I2 => index(1),
      I3 => index(0),
      I4 => index(2),
      I5 => index(3),
      O => \di_reg[1]_i_4__3_n_0\
    );
\di_reg[1]_i_5__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      I3 => index(1),
      O => \di_reg[1]_i_5__3_n_0\
    );
\di_reg[1]_i_6__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"002F0F20F02FFF2F"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(1),
      I3 => index(0),
      I4 => mode,
      I5 => do_reg2(1),
      O => \di_reg[1]_i_6__3_n_0\
    );
\di_reg[2]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \di_reg[2]_i_2__3_n_0\,
      I1 => \di_reg[2]_i_3__3_n_0\,
      O => di_reg(2)
    );
\di_reg[2]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00400500FFFFFFFF"
    )
        port map (
      I0 => index(3),
      I1 => do_reg2(2),
      I2 => index(2),
      I3 => index(1),
      I4 => index(0),
      I5 => index(4),
      O => \di_reg[2]_i_2__3_n_0\
    );
\di_reg[2]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF470047"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => \di_reg[2]_i_4__3_n_0\,
      I3 => index(3),
      I4 => \di_reg[2]_i_5__3_n_0\,
      I5 => index(4),
      O => \di_reg[2]_i_3__3_n_0\
    );
\di_reg[2]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F40404F00FF000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => mode,
      I4 => do_reg2(2),
      I5 => index(1),
      O => \di_reg[2]_i_4__3_n_0\
    );
\di_reg[2]_i_5__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5D535D5F5D5F5D5"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[2]_i_5__3_n_0\
    );
\di_reg[3]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAA1000AAFF0000"
    )
        port map (
      I0 => \di_reg[3]_i_4__3_n_0\,
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => do_reg2(3),
      I5 => index(0),
      O => \di_reg[3]_i_2__3_n_0\
    );
\di_reg[3]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000033E200"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => do_reg2(3),
      I3 => index(2),
      I4 => index(1),
      I5 => index(3),
      O => \di_reg[3]_i_3__3_n_0\
    );
\di_reg[3]_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      O => \di_reg[3]_i_4__3_n_0\
    );
\di_reg[4]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[4]_i_2__3_n_0\,
      I2 => index(4),
      I3 => \di_reg[4]_i_3__3_n_0\,
      I4 => \di_reg[4]_i_4__3_n_0\,
      I5 => \di_reg[4]_i_5__3_n_0\,
      O => di_reg(4)
    );
\di_reg[4]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080B0830303030"
    )
        port map (
      I0 => do_reg2(4),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[4]_i_2__3_n_0\
    );
\di_reg[4]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFFFFFFF"
    )
        port map (
      I0 => index(0),
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => index(1),
      I5 => \di_reg[4]_i_6__3_n_0\,
      O => \di_reg[4]_i_3__3_n_0\
    );
\di_reg[4]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFFE00000000"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      I2 => index(1),
      I3 => index(2),
      I4 => index(0),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_4__3_n_0\
    );
\di_reg[4]_i_5__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010C00"
    )
        port map (
      I0 => \di_reg[4]_i_7__3_n_0\,
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => \di_reg[4]_i_8__3_n_0\,
      I5 => index(3),
      O => \di_reg[4]_i_5__3_n_0\
    );
\di_reg[4]_i_6__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1F0FFF0F"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(3),
      I3 => do_reg2(4),
      I4 => index(1),
      O => \di_reg[4]_i_6__3_n_0\
    );
\di_reg[4]_i_7__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      O => \di_reg[4]_i_7__3_n_0\
    );
\di_reg[4]_i_8__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => \di_reg[4]_i_8__3_n_0\
    );
\di_reg[5]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33000000B888B888"
    )
        port map (
      I0 => \di_reg[5]_i_2__3_n_0\,
      I1 => index(4),
      I2 => \di_reg[5]_i_3__3_n_0\,
      I3 => do_reg2(5),
      I4 => \di_reg[5]_i_4__3_n_0\,
      I5 => index(3),
      O => di_reg(5)
    );
\di_reg[5]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B0B080B33333033"
    )
        port map (
      I0 => do_reg2(5),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[5]_i_2__3_n_0\
    );
\di_reg[5]_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(1),
      I3 => x16x20_mode_reg2,
      I4 => mode,
      O => \di_reg[5]_i_3__3_n_0\
    );
\di_reg[5]_i_4__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[5]_i_4__3_n_0\
    );
\di_reg[6]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"67FF000067000000"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(6),
      I5 => \di_reg[5]_i_3__3_n_0\,
      O => \di_reg[6]_i_2__3_n_0\
    );
\di_reg[6]_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002404"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(6),
      I4 => index(3),
      O => \di_reg[6]_i_3__3_n_0\
    );
\di_reg[7]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0900"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(7),
      O => \di_reg[7]_i_2__3_n_0\
    );
\di_reg[7]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000C320032"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => do_reg2(7),
      I5 => index(3),
      O => \di_reg[7]_i_3__3_n_0\
    );
\di_reg[8]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(8),
      O => di_reg(8)
    );
\di_reg[9]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(9),
      O => di_reg(9)
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(0),
      Q => \di_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[0]_i_1__3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[0]_i_2__3_n_0\,
      I1 => \di_reg[0]_i_3__3_n_0\,
      O => di_reg(0),
      S => index(4)
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(10),
      Q => \di_reg_reg_n_0_[10]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(11),
      Q => \di_reg_reg_n_0_[11]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(12),
      Q => \di_reg_reg_n_0_[12]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(13),
      Q => \di_reg_reg_n_0_[13]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(14),
      Q => \di_reg_reg_n_0_[14]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(15),
      Q => \di_reg_reg_n_0_[15]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(1),
      Q => \di_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(2),
      Q => \di_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(3),
      Q => \di_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]_i_1__3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[3]_i_2__3_n_0\,
      I1 => \di_reg[3]_i_3__3_n_0\,
      O => di_reg(3),
      S => index(4)
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(4),
      Q => \di_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(5),
      Q => \di_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(6),
      Q => \di_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]_i_1__3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[6]_i_2__3_n_0\,
      I1 => \di_reg[6]_i_3__3_n_0\,
      O => di_reg(6),
      S => index(4)
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(7),
      Q => \di_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[7]_i_1__3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[7]_i_2__3_n_0\,
      I1 => \di_reg[7]_i_3__3_n_0\,
      O => di_reg(7),
      S => index(4)
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(8),
      Q => \di_reg_reg_n_0_[8]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(9),
      Q => \di_reg_reg_n_0_[9]\,
      R => RST_DCLK_RESET
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(0),
      Q => do_reg1(0),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(10),
      Q => do_reg1(10),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(11),
      Q => do_reg1(11),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(12),
      Q => do_reg1(12),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(13),
      Q => do_reg1(13),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(14),
      Q => do_reg1(14),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(15),
      Q => do_reg1(15),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(1),
      Q => do_reg1(1),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(2),
      Q => do_reg1(2),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(3),
      Q => do_reg1(3),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(4),
      Q => do_reg1(4),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(5),
      Q => do_reg1(5),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(6),
      Q => do_reg1(6),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(7),
      Q => do_reg1(7),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(8),
      Q => do_reg1(8),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(9),
      Q => do_reg1(9),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => RST_DCLK_RESET
    );
\done_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => start_reg2,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \done_i_1__3_n_0\
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \done_i_1__3_n_0\,
      Q => DRP_DONE,
      R => RST_DCLK_RESET
    );
\fsm[0]_i_1__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B3BFFFF0B3B0000"
    )
        port map (
      I0 => data4,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => rdy_reg2,
      I4 => \^q\(2),
      I5 => \fsm[0]_i_3__8_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFEFFFF"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(4),
      I3 => index(2),
      I4 => \mode_i_2__3_n_0\,
      O => data4
    );
\fsm[0]_i_3__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7477FFFF7477CCCC"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \^q\(1),
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      I4 => \^q\(0),
      I5 => start_reg2,
      O => \fsm[0]_i_3__8_n_0\
    );
\fsm[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"185018501D501850"
    )
        port map (
      I0 => \^q\(2),
      I1 => rdy_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => load_cnt(0),
      I5 => load_cnt(1),
      O => fsm(1)
    );
\fsm[2]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6222"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      R => RST_DCLK_RESET
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      R => RST_DCLK_RESET
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_DCLK_RESET
    );
\gt_ch_drp_rdy[4]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => gt_ch_drp_rdy(0)
    );
\gtx_channel.gtxe2_channel_i_i_14__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(15),
      I1 => \di_reg_reg_n_0_[15]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(15)
    );
\gtx_channel.gtxe2_channel_i_i_15__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(14),
      I1 => \di_reg_reg_n_0_[14]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(14)
    );
\gtx_channel.gtxe2_channel_i_i_16__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(13),
      I1 => \di_reg_reg_n_0_[13]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(13)
    );
\gtx_channel.gtxe2_channel_i_i_17__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(12),
      I1 => \di_reg_reg_n_0_[12]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(12)
    );
\gtx_channel.gtxe2_channel_i_i_18__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(11),
      I1 => \di_reg_reg_n_0_[11]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(11)
    );
\gtx_channel.gtxe2_channel_i_i_19__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(10),
      I1 => \di_reg_reg_n_0_[10]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(10)
    );
\gtx_channel.gtxe2_channel_i_i_20__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(9),
      I1 => \di_reg_reg_n_0_[9]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(9)
    );
\gtx_channel.gtxe2_channel_i_i_21__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(8),
      I1 => \di_reg_reg_n_0_[8]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(8)
    );
\gtx_channel.gtxe2_channel_i_i_22__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(7),
      I1 => \di_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(7)
    );
\gtx_channel.gtxe2_channel_i_i_23__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(6),
      I1 => \di_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(6)
    );
\gtx_channel.gtxe2_channel_i_i_24__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(5),
      I1 => \di_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(5)
    );
\gtx_channel.gtxe2_channel_i_i_25__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(4),
      I1 => \di_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(4)
    );
\gtx_channel.gtxe2_channel_i_i_26__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(3),
      I1 => \di_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(3)
    );
\gtx_channel.gtxe2_channel_i_i_27__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(2),
      I1 => \di_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(2)
    );
\gtx_channel.gtxe2_channel_i_i_28__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(1),
      I1 => \di_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(1)
    );
\gtx_channel.gtxe2_channel_i_i_29__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(0),
      I1 => \di_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(0)
    );
\gtx_channel.gtxe2_channel_i_i_3__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"003E"
    )
        port map (
      I0 => ext_ch_gt_drpen(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \cplllock_reg1_reg[4]\
    );
\gtx_channel.gtxe2_channel_i_i_47__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => DRPADDR(8)
    );
\gtx_channel.gtxe2_channel_i_i_48__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(7),
      I1 => \addr_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(7)
    );
\gtx_channel.gtxe2_channel_i_i_49__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(6),
      I1 => \addr_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(6)
    );
\gtx_channel.gtxe2_channel_i_i_4__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0032"
    )
        port map (
      I0 => ext_ch_gt_drpwe(0),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \cplllock_reg1_reg[4]_0\
    );
\gtx_channel.gtxe2_channel_i_i_50__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(5),
      I1 => \addr_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(5)
    );
\gtx_channel.gtxe2_channel_i_i_51__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(4),
      I1 => \addr_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(4)
    );
\gtx_channel.gtxe2_channel_i_i_52__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(3),
      I1 => \addr_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(3)
    );
\gtx_channel.gtxe2_channel_i_i_53__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(2),
      I1 => \addr_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(2)
    );
\gtx_channel.gtxe2_channel_i_i_54__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(1),
      I1 => \addr_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(1)
    );
\gtx_channel.gtxe2_channel_i_i_55__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(0),
      I1 => \addr_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(0)
    );
gtxreset_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rst_gtreset,
      Q => gtxreset_reg1,
      R => RST_DCLK_RESET
    );
gtxreset_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => gtxreset_reg1,
      Q => gtxreset_reg2,
      R => RST_DCLK_RESET
    );
\index[0]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => index(0),
      I1 => \^q\(2),
      I2 => \index[3]_i_2__3_n_0\,
      O => \index[0]_i_1__5_n_0\
    );
\index[1]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__3_n_0\,
      I2 => index(1),
      I3 => index(0),
      O => \index[1]_i_1__5_n_0\
    );
\index[2]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02222000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__3_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      O => \index[2]_i_1__5_n_0\
    );
\index[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222222220000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__3_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => index(3),
      O => \index[3]_i_1__3_n_0\
    );
\index[3]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAE"
    )
        port map (
      I0 => \^q\(0),
      I1 => \mode_i_2__3_n_0\,
      I2 => index(2),
      I3 => index(4),
      I4 => index(1),
      I5 => index(3),
      O => \index[3]_i_2__3_n_0\
    );
\index[4]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"89"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \index[4]_i_1__3_n_0\
    );
\index[4]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => index(0),
      I1 => index(2),
      I2 => index(3),
      I3 => index(1),
      I4 => index(4),
      I5 => \index[4]_i_3__3_n_0\,
      O => \index[4]_i_2__3_n_0\
    );
\index[4]_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \index[3]_i_2__3_n_0\,
      I1 => \^q\(2),
      O => \index[4]_i_3__3_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__3_n_0\,
      D => \index[0]_i_1__5_n_0\,
      Q => index(0),
      R => RST_DCLK_RESET
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__3_n_0\,
      D => \index[1]_i_1__5_n_0\,
      Q => index(1),
      R => RST_DCLK_RESET
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__3_n_0\,
      D => \index[2]_i_1__5_n_0\,
      Q => index(2),
      R => RST_DCLK_RESET
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__3_n_0\,
      D => \index[3]_i_1__3_n_0\,
      Q => index(3),
      R => RST_DCLK_RESET
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__3_n_0\,
      D => \index[4]_i_2__3_n_0\,
      Q => index(4),
      R => RST_DCLK_RESET
    );
\load_cnt[0]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => load_cnt(1),
      I3 => \^q\(2),
      O => \load_cnt[0]_i_1__4_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[0]_i_1__4_n_0\,
      Q => load_cnt(0),
      R => RST_DCLK_RESET
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => load_cnt(1),
      R => RST_DCLK_RESET
    );
\mode_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AAA2AAAAAAAA00"
    )
        port map (
      I0 => mode,
      I1 => \mode_i_2__3_n_0\,
      I2 => \mode_i_3__5_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \mode_i_1__3_n_0\
    );
\mode_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCB8"
    )
        port map (
      I0 => mode,
      I1 => index(0),
      I2 => x16x20_mode_reg2,
      I3 => index(2),
      O => \mode_i_2__3_n_0\
    );
\mode_i_3__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF6"
    )
        port map (
      I0 => index(2),
      I1 => index(4),
      I2 => index(1),
      I3 => index(3),
      O => \mode_i_3__5_n_0\
    );
mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \mode_i_1__3_n_0\,
      Q => mode,
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_reg1(0),
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => RST_DCLK_RESET
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drprdy(0),
      Q => rdy_reg1,
      R => RST_DCLK_RESET
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => RST_DCLK_RESET
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_START,
      Q => start_reg1,
      R => RST_DCLK_RESET
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => RST_DCLK_RESET
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16,
      Q => x16_reg1,
      R => RST_DCLK_RESET
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16X20_MODE,
      Q => x16x20_mode_reg1,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16x20_mode_reg1,
      Q => x16x20_mode_reg2,
      R => RST_DCLK_RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_55 is
  port (
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \cplllock_reg1_reg[5]\ : out STD_LOGIC;
    \cplllock_reg1_reg[5]_0\ : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_DONE : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 );
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_X16X20_MODE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    ext_ch_gt_drprdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DRP_X16 : in STD_LOGIC;
    ext_ch_gt_drpdo : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rst_gtreset : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_55 : entity is "PCIeGen1x8If64_pipe_drp";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_55;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_55 is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \addr_reg[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \addr_reg[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \addr_reg[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \addr_reg[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \addr_reg[5]_i_1__4_n_0\ : STD_LOGIC;
  signal \addr_reg[6]_i_1__4_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_1__4_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_2__4_n_0\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal data15 : STD_LOGIC_VECTOR ( 7 to 7 );
  signal data4 : STD_LOGIC;
  signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di_reg[0]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_4__4_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_5__4_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_6__4_n_0\ : STD_LOGIC;
  signal \di_reg[10]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_4__4_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_5__4_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_4__4_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_4__4_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_4__4_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_6__4_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_7__4_n_0\ : STD_LOGIC;
  signal \di_reg[15]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_4__4_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_5__4_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_6__4_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_4__4_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_5__4_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_4__4_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_4__4_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_5__4_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_6__4_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_7__4_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_8__4_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_4__4_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_2__4_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_3__4_n_0\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[9]\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \done_i_1__4_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm[0]_i_3__10_n_0\ : STD_LOGIC;
  signal gtxreset_reg1 : STD_LOGIC;
  signal gtxreset_reg2 : STD_LOGIC;
  signal index : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \index[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \index[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \index[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \index[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \index[3]_i_2__4_n_0\ : STD_LOGIC;
  signal \index[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \index[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \index[4]_i_3__4_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1__6_n_0\ : STD_LOGIC;
  signal mode : STD_LOGIC;
  signal \mode_i_1__4_n_0\ : STD_LOGIC;
  signal \mode_i_2__4_n_0\ : STD_LOGIC;
  signal \mode_i_3__6_n_0\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rdy_reg1 : STD_LOGIC;
  signal rdy_reg2 : STD_LOGIC;
  signal start_reg1 : STD_LOGIC;
  signal start_reg2 : STD_LOGIC;
  signal x16_reg1 : STD_LOGIC;
  signal x16_reg2 : STD_LOGIC;
  signal x16x20_mode_reg1 : STD_LOGIC;
  signal x16x20_mode_reg2 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \di_reg[0]_i_5__4\ : label is "soft_lutpair153";
  attribute SOFT_HLUTNM of \di_reg[0]_i_6__4\ : label is "soft_lutpair154";
  attribute SOFT_HLUTNM of \di_reg[14]_i_2__4\ : label is "soft_lutpair153";
  attribute SOFT_HLUTNM of \di_reg[3]_i_4__4\ : label is "soft_lutpair154";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \fsm[0]_i_2__4\ : label is "soft_lutpair149";
  attribute SOFT_HLUTNM of \gt_ch_drp_rdy[5]_INST_0\ : label is "soft_lutpair147";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__4\ : label is "soft_lutpair150";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_47__6\ : label is "soft_lutpair150";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__4\ : label is "soft_lutpair151";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_50__4\ : label is "soft_lutpair147";
  attribute ASYNC_REG of gtxreset_reg1_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg1_reg : label is "yes";
  attribute ASYNC_REG of gtxreset_reg2_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \index[0]_i_1__6\ : label is "soft_lutpair152";
  attribute SOFT_HLUTNM of \index[1]_i_1__6\ : label is "soft_lutpair148";
  attribute SOFT_HLUTNM of \index[2]_i_1__6\ : label is "soft_lutpair148";
  attribute SOFT_HLUTNM of \index[4]_i_3__4\ : label is "soft_lutpair152";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1__6\ : label is "soft_lutpair151";
  attribute SOFT_HLUTNM of \mode_i_3__6\ : label is "soft_lutpair149";
  attribute ASYNC_REG of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute ASYNC_REG of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute ASYNC_REG of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg2_reg : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\addr_reg[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1471357514713564"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__4_n_0\,
      O => \addr_reg[0]_i_1__4_n_0\
    );
\addr_reg[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404050500F0F0500"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[1]_i_1__4_n_0\
    );
\addr_reg[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"051005105A055A00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(2),
      I4 => mode,
      I5 => index(1),
      O => \addr_reg[2]_i_1__4_n_0\
    );
\addr_reg[3]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5767576753275326"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => \addr_reg[4]_i_2__4_n_0\,
      I5 => index(0),
      O => \addr_reg[3]_i_1__4_n_0\
    );
\addr_reg[4]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FCCFFF01"
    )
        port map (
      I0 => \addr_reg[4]_i_2__4_n_0\,
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => index(4),
      O => \addr_reg[4]_i_1__4_n_0\
    );
\addr_reg[4]_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      O => \addr_reg[4]_i_2__4_n_0\
    );
\addr_reg[5]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001A1A0F0F0F0A"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[5]_i_1__4_n_0\
    );
\addr_reg[6]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011545554"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => mode,
      I3 => index(3),
      I4 => index(0),
      I5 => index(4),
      O => \addr_reg[6]_i_1__4_n_0\
    );
\addr_reg[7]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5422262254222633"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__4_n_0\,
      O => \addr_reg[7]_i_1__4_n_0\
    );
\addr_reg[7]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CE"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      I2 => index(0),
      O => \addr_reg[7]_i_2__4_n_0\
    );
\addr_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[0]_i_1__4_n_0\,
      Q => \addr_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[1]_i_1__4_n_0\,
      Q => \addr_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[2]_i_1__4_n_0\,
      Q => \addr_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[3]_i_1__4_n_0\,
      Q => \addr_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[4]_i_1__4_n_0\,
      Q => \addr_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[5]_i_1__4_n_0\,
      Q => \addr_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[6]_i_1__4_n_0\,
      Q => \addr_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[7]_i_1__4_n_0\,
      Q => \addr_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg[0]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B8BBB8B8B888"
    )
        port map (
      I0 => \di_reg[0]_i_4__4_n_0\,
      I1 => index(3),
      I2 => do_reg2(0),
      I3 => \di_reg[0]_i_5__4_n_0\,
      I4 => \di_reg[0]_i_6__4_n_0\,
      I5 => \di_reg[4]_i_8__4_n_0\,
      O => \di_reg[0]_i_2__4_n_0\
    );
\di_reg[0]_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003414"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(0),
      I4 => index(3),
      O => \di_reg[0]_i_3__4_n_0\
    );
\di_reg[0]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0BFFFFFB0B00000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => do_reg2(0),
      O => \di_reg[0]_i_4__4_n_0\
    );
\di_reg[0]_i_5__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      O => \di_reg[0]_i_5__4_n_0\
    );
\di_reg[0]_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => index(1),
      I1 => mode,
      I2 => index(0),
      O => \di_reg[0]_i_6__4_n_0\
    );
\di_reg[10]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(10),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[10]_i_2__4_n_0\,
      O => di_reg(10)
    );
\di_reg[10]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[10]_i_2__4_n_0\
    );
\di_reg[11]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[11]_i_2__4_n_0\,
      I2 => index(4),
      I3 => \di_reg[11]_i_3__4_n_0\,
      I4 => \di_reg[11]_i_4__4_n_0\,
      I5 => \di_reg[11]_i_5__4_n_0\,
      O => di_reg(11)
    );
\di_reg[11]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808380808"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(0),
      I4 => rate_reg2(1),
      I5 => index(0),
      O => \di_reg[11]_i_2__4_n_0\
    );
\di_reg[11]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC0CCC0C0C0C880C"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => do_reg2(11),
      I3 => index(2),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[11]_i_3__4_n_0\
    );
\di_reg[11]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAABAAABA"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[11]_i_4__4_n_0\
    );
\di_reg[11]_i_5__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA00AAAAAAA3"
    )
        port map (
      I0 => do_reg2(11),
      I1 => x16_reg2,
      I2 => \addr_reg[4]_i_2__4_n_0\,
      I3 => index(0),
      I4 => index(1),
      I5 => index(2),
      O => \di_reg[11]_i_5__4_n_0\
    );
\di_reg[12]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \di_reg[12]_i_2__4_n_0\,
      I1 => index(4),
      I2 => \di_reg[12]_i_3__4_n_0\,
      I3 => index(3),
      I4 => \di_reg[12]_i_4__4_n_0\,
      O => di_reg(12)
    );
\di_reg[12]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003202"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(12),
      I4 => index(3),
      O => \di_reg[12]_i_2__4_n_0\
    );
\di_reg[12]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(12),
      O => \di_reg[12]_i_3__4_n_0\
    );
\di_reg[12]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAA8AAABAAABA"
    )
        port map (
      I0 => do_reg2(12),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[12]_i_4__4_n_0\
    );
\di_reg[13]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \di_reg[13]_i_2__4_n_0\,
      I1 => index(4),
      I2 => \di_reg[13]_i_3__4_n_0\,
      I3 => index(3),
      I4 => \di_reg[13]_i_4__4_n_0\,
      O => di_reg(13)
    );
\di_reg[13]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080838380838"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[13]_i_2__4_n_0\
    );
\di_reg[13]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(13),
      O => \di_reg[13]_i_3__4_n_0\
    );
\di_reg[13]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAA8AAABAAA8A"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(1),
      I5 => rate_reg2(0),
      O => \di_reg[13]_i_4__4_n_0\
    );
\di_reg[14]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080008FF08000800"
    )
        port map (
      I0 => do_reg2(14),
      I1 => \di_reg[14]_i_2__4_n_0\,
      I2 => index(3),
      I3 => index(4),
      I4 => \di_reg[14]_i_3__4_n_0\,
      I5 => \di_reg[14]_i_4__4_n_0\,
      O => di_reg(14)
    );
\di_reg[14]_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[14]_i_2__4_n_0\
    );
\di_reg[14]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033303310130033"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => index(2),
      I3 => do_reg2(14),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[14]_i_3__4_n_0\
    );
\di_reg[14]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000DF10"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => do_reg2(14),
      I4 => index(2),
      I5 => \di_reg[14]_i_6__4_n_0\,
      O => \di_reg[14]_i_4__4_n_0\
    );
\di_reg[14]_i_5__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      O => data15(7)
    );
\di_reg[14]_i_6__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB3BBBBBBB3FBB"
    )
        port map (
      I0 => \di_reg[14]_i_7__4_n_0\,
      I1 => index(3),
      I2 => index(0),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => \di_reg[5]_i_4__4_n_0\,
      O => \di_reg[14]_i_6__4_n_0\
    );
\di_reg[14]_i_7__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => index(1),
      I1 => index(2),
      I2 => do_reg2(14),
      I3 => index(0),
      O => \di_reg[14]_i_7__4_n_0\
    );
\di_reg[15]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(15),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[15]_i_2__4_n_0\,
      O => di_reg(15)
    );
\di_reg[15]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[15]_i_2__4_n_0\
    );
\di_reg[1]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \di_reg[1]_i_2__4_n_0\,
      I1 => index(4),
      I2 => \di_reg[1]_i_3__4_n_0\,
      I3 => \di_reg[1]_i_4__4_n_0\,
      O => di_reg(1)
    );
\di_reg[1]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000034140000"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(1),
      I4 => index(4),
      I5 => index(3),
      O => \di_reg[1]_i_2__4_n_0\
    );
\di_reg[1]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FB330000"
    )
        port map (
      I0 => index(2),
      I1 => do_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(3),
      I5 => \di_reg[1]_i_5__4_n_0\,
      O => \di_reg[1]_i_3__4_n_0\
    );
\di_reg[1]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFCCC5555"
    )
        port map (
      I0 => \di_reg[1]_i_6__4_n_0\,
      I1 => do_reg2(1),
      I2 => index(1),
      I3 => index(0),
      I4 => index(2),
      I5 => index(3),
      O => \di_reg[1]_i_4__4_n_0\
    );
\di_reg[1]_i_5__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      I3 => index(1),
      O => \di_reg[1]_i_5__4_n_0\
    );
\di_reg[1]_i_6__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"002F0F20F02FFF2F"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(1),
      I3 => index(0),
      I4 => mode,
      I5 => do_reg2(1),
      O => \di_reg[1]_i_6__4_n_0\
    );
\di_reg[2]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \di_reg[2]_i_2__4_n_0\,
      I1 => \di_reg[2]_i_3__4_n_0\,
      O => di_reg(2)
    );
\di_reg[2]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00400500FFFFFFFF"
    )
        port map (
      I0 => index(3),
      I1 => do_reg2(2),
      I2 => index(2),
      I3 => index(1),
      I4 => index(0),
      I5 => index(4),
      O => \di_reg[2]_i_2__4_n_0\
    );
\di_reg[2]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF470047"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => \di_reg[2]_i_4__4_n_0\,
      I3 => index(3),
      I4 => \di_reg[2]_i_5__4_n_0\,
      I5 => index(4),
      O => \di_reg[2]_i_3__4_n_0\
    );
\di_reg[2]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F40404F00FF000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => mode,
      I4 => do_reg2(2),
      I5 => index(1),
      O => \di_reg[2]_i_4__4_n_0\
    );
\di_reg[2]_i_5__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5D535D5F5D5F5D5"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[2]_i_5__4_n_0\
    );
\di_reg[3]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAA1000AAFF0000"
    )
        port map (
      I0 => \di_reg[3]_i_4__4_n_0\,
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => do_reg2(3),
      I5 => index(0),
      O => \di_reg[3]_i_2__4_n_0\
    );
\di_reg[3]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000033E200"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => do_reg2(3),
      I3 => index(2),
      I4 => index(1),
      I5 => index(3),
      O => \di_reg[3]_i_3__4_n_0\
    );
\di_reg[3]_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      O => \di_reg[3]_i_4__4_n_0\
    );
\di_reg[4]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[4]_i_2__4_n_0\,
      I2 => index(4),
      I3 => \di_reg[4]_i_3__4_n_0\,
      I4 => \di_reg[4]_i_4__4_n_0\,
      I5 => \di_reg[4]_i_5__4_n_0\,
      O => di_reg(4)
    );
\di_reg[4]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080B0830303030"
    )
        port map (
      I0 => do_reg2(4),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[4]_i_2__4_n_0\
    );
\di_reg[4]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFFFFFFF"
    )
        port map (
      I0 => index(0),
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => index(1),
      I5 => \di_reg[4]_i_6__4_n_0\,
      O => \di_reg[4]_i_3__4_n_0\
    );
\di_reg[4]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFFE00000000"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      I2 => index(1),
      I3 => index(2),
      I4 => index(0),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_4__4_n_0\
    );
\di_reg[4]_i_5__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010C00"
    )
        port map (
      I0 => \di_reg[4]_i_7__4_n_0\,
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => \di_reg[4]_i_8__4_n_0\,
      I5 => index(3),
      O => \di_reg[4]_i_5__4_n_0\
    );
\di_reg[4]_i_6__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1F0FFF0F"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(3),
      I3 => do_reg2(4),
      I4 => index(1),
      O => \di_reg[4]_i_6__4_n_0\
    );
\di_reg[4]_i_7__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      O => \di_reg[4]_i_7__4_n_0\
    );
\di_reg[4]_i_8__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => \di_reg[4]_i_8__4_n_0\
    );
\di_reg[5]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33000000B888B888"
    )
        port map (
      I0 => \di_reg[5]_i_2__4_n_0\,
      I1 => index(4),
      I2 => \di_reg[5]_i_3__4_n_0\,
      I3 => do_reg2(5),
      I4 => \di_reg[5]_i_4__4_n_0\,
      I5 => index(3),
      O => di_reg(5)
    );
\di_reg[5]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B0B080B33333033"
    )
        port map (
      I0 => do_reg2(5),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[5]_i_2__4_n_0\
    );
\di_reg[5]_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(1),
      I3 => x16x20_mode_reg2,
      I4 => mode,
      O => \di_reg[5]_i_3__4_n_0\
    );
\di_reg[5]_i_4__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[5]_i_4__4_n_0\
    );
\di_reg[6]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"67FF000067000000"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(6),
      I5 => \di_reg[5]_i_3__4_n_0\,
      O => \di_reg[6]_i_2__4_n_0\
    );
\di_reg[6]_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002404"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(6),
      I4 => index(3),
      O => \di_reg[6]_i_3__4_n_0\
    );
\di_reg[7]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0900"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(7),
      O => \di_reg[7]_i_2__4_n_0\
    );
\di_reg[7]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000C320032"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => do_reg2(7),
      I5 => index(3),
      O => \di_reg[7]_i_3__4_n_0\
    );
\di_reg[8]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(8),
      O => di_reg(8)
    );
\di_reg[9]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(9),
      O => di_reg(9)
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(0),
      Q => \di_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[0]_i_1__4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[0]_i_2__4_n_0\,
      I1 => \di_reg[0]_i_3__4_n_0\,
      O => di_reg(0),
      S => index(4)
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(10),
      Q => \di_reg_reg_n_0_[10]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(11),
      Q => \di_reg_reg_n_0_[11]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(12),
      Q => \di_reg_reg_n_0_[12]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(13),
      Q => \di_reg_reg_n_0_[13]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(14),
      Q => \di_reg_reg_n_0_[14]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(15),
      Q => \di_reg_reg_n_0_[15]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(1),
      Q => \di_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(2),
      Q => \di_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(3),
      Q => \di_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]_i_1__4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[3]_i_2__4_n_0\,
      I1 => \di_reg[3]_i_3__4_n_0\,
      O => di_reg(3),
      S => index(4)
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(4),
      Q => \di_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(5),
      Q => \di_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(6),
      Q => \di_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]_i_1__4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[6]_i_2__4_n_0\,
      I1 => \di_reg[6]_i_3__4_n_0\,
      O => di_reg(6),
      S => index(4)
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(7),
      Q => \di_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[7]_i_1__4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[7]_i_2__4_n_0\,
      I1 => \di_reg[7]_i_3__4_n_0\,
      O => di_reg(7),
      S => index(4)
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(8),
      Q => \di_reg_reg_n_0_[8]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(9),
      Q => \di_reg_reg_n_0_[9]\,
      R => RST_DCLK_RESET
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(0),
      Q => do_reg1(0),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(10),
      Q => do_reg1(10),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(11),
      Q => do_reg1(11),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(12),
      Q => do_reg1(12),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(13),
      Q => do_reg1(13),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(14),
      Q => do_reg1(14),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(15),
      Q => do_reg1(15),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(1),
      Q => do_reg1(1),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(2),
      Q => do_reg1(2),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(3),
      Q => do_reg1(3),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(4),
      Q => do_reg1(4),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(5),
      Q => do_reg1(5),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(6),
      Q => do_reg1(6),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(7),
      Q => do_reg1(7),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(8),
      Q => do_reg1(8),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(9),
      Q => do_reg1(9),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => RST_DCLK_RESET
    );
\done_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => start_reg2,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \done_i_1__4_n_0\
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \done_i_1__4_n_0\,
      Q => DRP_DONE,
      R => RST_DCLK_RESET
    );
\fsm[0]_i_1__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B3BFFFF0B3B0000"
    )
        port map (
      I0 => data4,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => rdy_reg2,
      I4 => \^q\(2),
      I5 => \fsm[0]_i_3__10_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFEFFFF"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(4),
      I3 => index(2),
      I4 => \mode_i_2__4_n_0\,
      O => data4
    );
\fsm[0]_i_3__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7477FFFF7477CCCC"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \^q\(1),
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      I4 => \^q\(0),
      I5 => start_reg2,
      O => \fsm[0]_i_3__10_n_0\
    );
\fsm[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"185018501D501850"
    )
        port map (
      I0 => \^q\(2),
      I1 => rdy_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => load_cnt(0),
      I5 => load_cnt(1),
      O => fsm(1)
    );
\fsm[2]_i_1__10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6222"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      R => RST_DCLK_RESET
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      R => RST_DCLK_RESET
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_DCLK_RESET
    );
\gt_ch_drp_rdy[5]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => gt_ch_drp_rdy(0)
    );
\gtx_channel.gtxe2_channel_i_i_14__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(15),
      I1 => \di_reg_reg_n_0_[15]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(15)
    );
\gtx_channel.gtxe2_channel_i_i_15__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(14),
      I1 => \di_reg_reg_n_0_[14]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(14)
    );
\gtx_channel.gtxe2_channel_i_i_16__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(13),
      I1 => \di_reg_reg_n_0_[13]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(13)
    );
\gtx_channel.gtxe2_channel_i_i_17__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(12),
      I1 => \di_reg_reg_n_0_[12]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(12)
    );
\gtx_channel.gtxe2_channel_i_i_18__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(11),
      I1 => \di_reg_reg_n_0_[11]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(11)
    );
\gtx_channel.gtxe2_channel_i_i_19__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(10),
      I1 => \di_reg_reg_n_0_[10]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(10)
    );
\gtx_channel.gtxe2_channel_i_i_20__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(9),
      I1 => \di_reg_reg_n_0_[9]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(9)
    );
\gtx_channel.gtxe2_channel_i_i_21__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(8),
      I1 => \di_reg_reg_n_0_[8]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(8)
    );
\gtx_channel.gtxe2_channel_i_i_22__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(7),
      I1 => \di_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(7)
    );
\gtx_channel.gtxe2_channel_i_i_23__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(6),
      I1 => \di_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(6)
    );
\gtx_channel.gtxe2_channel_i_i_24__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(5),
      I1 => \di_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(5)
    );
\gtx_channel.gtxe2_channel_i_i_25__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(4),
      I1 => \di_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(4)
    );
\gtx_channel.gtxe2_channel_i_i_26__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(3),
      I1 => \di_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(3)
    );
\gtx_channel.gtxe2_channel_i_i_27__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(2),
      I1 => \di_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(2)
    );
\gtx_channel.gtxe2_channel_i_i_28__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(1),
      I1 => \di_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(1)
    );
\gtx_channel.gtxe2_channel_i_i_29__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(0),
      I1 => \di_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(0)
    );
\gtx_channel.gtxe2_channel_i_i_3__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"003E"
    )
        port map (
      I0 => ext_ch_gt_drpen(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \cplllock_reg1_reg[5]\
    );
\gtx_channel.gtxe2_channel_i_i_47__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => DRPADDR(8)
    );
\gtx_channel.gtxe2_channel_i_i_48__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(7),
      I1 => \addr_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(7)
    );
\gtx_channel.gtxe2_channel_i_i_49__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(6),
      I1 => \addr_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(6)
    );
\gtx_channel.gtxe2_channel_i_i_4__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0032"
    )
        port map (
      I0 => ext_ch_gt_drpwe(0),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \cplllock_reg1_reg[5]_0\
    );
\gtx_channel.gtxe2_channel_i_i_50__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(5),
      I1 => \addr_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(5)
    );
\gtx_channel.gtxe2_channel_i_i_51__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(4),
      I1 => \addr_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(4)
    );
\gtx_channel.gtxe2_channel_i_i_52__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(3),
      I1 => \addr_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(3)
    );
\gtx_channel.gtxe2_channel_i_i_53__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(2),
      I1 => \addr_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(2)
    );
\gtx_channel.gtxe2_channel_i_i_54__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(1),
      I1 => \addr_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(1)
    );
\gtx_channel.gtxe2_channel_i_i_55__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(0),
      I1 => \addr_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(0)
    );
gtxreset_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rst_gtreset,
      Q => gtxreset_reg1,
      R => RST_DCLK_RESET
    );
gtxreset_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => gtxreset_reg1,
      Q => gtxreset_reg2,
      R => RST_DCLK_RESET
    );
\index[0]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => index(0),
      I1 => \^q\(2),
      I2 => \index[3]_i_2__4_n_0\,
      O => \index[0]_i_1__6_n_0\
    );
\index[1]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__4_n_0\,
      I2 => index(1),
      I3 => index(0),
      O => \index[1]_i_1__6_n_0\
    );
\index[2]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02222000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__4_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      O => \index[2]_i_1__6_n_0\
    );
\index[3]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222222220000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__4_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => index(3),
      O => \index[3]_i_1__4_n_0\
    );
\index[3]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAE"
    )
        port map (
      I0 => \^q\(0),
      I1 => \mode_i_2__4_n_0\,
      I2 => index(2),
      I3 => index(4),
      I4 => index(1),
      I5 => index(3),
      O => \index[3]_i_2__4_n_0\
    );
\index[4]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"89"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \index[4]_i_1__4_n_0\
    );
\index[4]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => index(0),
      I1 => index(2),
      I2 => index(3),
      I3 => index(1),
      I4 => index(4),
      I5 => \index[4]_i_3__4_n_0\,
      O => \index[4]_i_2__4_n_0\
    );
\index[4]_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \index[3]_i_2__4_n_0\,
      I1 => \^q\(2),
      O => \index[4]_i_3__4_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__4_n_0\,
      D => \index[0]_i_1__6_n_0\,
      Q => index(0),
      R => RST_DCLK_RESET
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__4_n_0\,
      D => \index[1]_i_1__6_n_0\,
      Q => index(1),
      R => RST_DCLK_RESET
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__4_n_0\,
      D => \index[2]_i_1__6_n_0\,
      Q => index(2),
      R => RST_DCLK_RESET
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__4_n_0\,
      D => \index[3]_i_1__4_n_0\,
      Q => index(3),
      R => RST_DCLK_RESET
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__4_n_0\,
      D => \index[4]_i_2__4_n_0\,
      Q => index(4),
      R => RST_DCLK_RESET
    );
\load_cnt[0]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => load_cnt(1),
      I3 => \^q\(2),
      O => \load_cnt[0]_i_1__6_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[0]_i_1__6_n_0\,
      Q => load_cnt(0),
      R => RST_DCLK_RESET
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => load_cnt(1),
      R => RST_DCLK_RESET
    );
\mode_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AAA2AAAAAAAA00"
    )
        port map (
      I0 => mode,
      I1 => \mode_i_2__4_n_0\,
      I2 => \mode_i_3__6_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \mode_i_1__4_n_0\
    );
\mode_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCB8"
    )
        port map (
      I0 => mode,
      I1 => index(0),
      I2 => x16x20_mode_reg2,
      I3 => index(2),
      O => \mode_i_2__4_n_0\
    );
\mode_i_3__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF6"
    )
        port map (
      I0 => index(2),
      I1 => index(4),
      I2 => index(1),
      I3 => index(3),
      O => \mode_i_3__6_n_0\
    );
mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \mode_i_1__4_n_0\,
      Q => mode,
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_reg1(0),
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => RST_DCLK_RESET
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drprdy(0),
      Q => rdy_reg1,
      R => RST_DCLK_RESET
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => RST_DCLK_RESET
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_START,
      Q => start_reg1,
      R => RST_DCLK_RESET
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => RST_DCLK_RESET
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16,
      Q => x16_reg1,
      R => RST_DCLK_RESET
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16X20_MODE,
      Q => x16x20_mode_reg1,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16x20_mode_reg1,
      Q => x16x20_mode_reg2,
      R => RST_DCLK_RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_61 is
  port (
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \cplllock_reg1_reg[6]\ : out STD_LOGIC;
    \cplllock_reg1_reg[6]_0\ : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_DONE : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 );
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_X16X20_MODE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    ext_ch_gt_drprdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DRP_X16 : in STD_LOGIC;
    ext_ch_gt_drpdo : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rst_gtreset : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_61 : entity is "PCIeGen1x8If64_pipe_drp";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_61;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_61 is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \addr_reg[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \addr_reg[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \addr_reg[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \addr_reg[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \addr_reg[5]_i_1__5_n_0\ : STD_LOGIC;
  signal \addr_reg[6]_i_1__5_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_1__5_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_2__5_n_0\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal data15 : STD_LOGIC_VECTOR ( 7 to 7 );
  signal data4 : STD_LOGIC;
  signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di_reg[0]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_4__5_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_5__5_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_6__5_n_0\ : STD_LOGIC;
  signal \di_reg[10]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_4__5_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_5__5_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_4__5_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_4__5_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_4__5_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_6__5_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_7__5_n_0\ : STD_LOGIC;
  signal \di_reg[15]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_4__5_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_5__5_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_6__5_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_4__5_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_5__5_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_4__5_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_4__5_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_5__5_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_6__5_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_7__5_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_8__5_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_4__5_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_2__5_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_3__5_n_0\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[9]\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \done_i_1__5_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm[0]_i_3__12_n_0\ : STD_LOGIC;
  signal gtxreset_reg1 : STD_LOGIC;
  signal gtxreset_reg2 : STD_LOGIC;
  signal index : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \index[0]_i_1__7_n_0\ : STD_LOGIC;
  signal \index[1]_i_1__7_n_0\ : STD_LOGIC;
  signal \index[2]_i_1__7_n_0\ : STD_LOGIC;
  signal \index[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \index[3]_i_2__5_n_0\ : STD_LOGIC;
  signal \index[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \index[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \index[4]_i_3__5_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1__7_n_0\ : STD_LOGIC;
  signal mode : STD_LOGIC;
  signal \mode_i_1__5_n_0\ : STD_LOGIC;
  signal \mode_i_2__5_n_0\ : STD_LOGIC;
  signal \mode_i_3__7_n_0\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rdy_reg1 : STD_LOGIC;
  signal rdy_reg2 : STD_LOGIC;
  signal start_reg1 : STD_LOGIC;
  signal start_reg2 : STD_LOGIC;
  signal x16_reg1 : STD_LOGIC;
  signal x16_reg2 : STD_LOGIC;
  signal x16x20_mode_reg1 : STD_LOGIC;
  signal x16x20_mode_reg2 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \di_reg[0]_i_5__5\ : label is "soft_lutpair175";
  attribute SOFT_HLUTNM of \di_reg[0]_i_6__5\ : label is "soft_lutpair176";
  attribute SOFT_HLUTNM of \di_reg[14]_i_2__5\ : label is "soft_lutpair175";
  attribute SOFT_HLUTNM of \di_reg[3]_i_4__5\ : label is "soft_lutpair176";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \fsm[0]_i_2__5\ : label is "soft_lutpair171";
  attribute SOFT_HLUTNM of \gt_ch_drp_rdy[6]_INST_0\ : label is "soft_lutpair169";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__5\ : label is "soft_lutpair172";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_48__5\ : label is "soft_lutpair172";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__5\ : label is "soft_lutpair173";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_51__5\ : label is "soft_lutpair169";
  attribute ASYNC_REG of gtxreset_reg1_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg1_reg : label is "yes";
  attribute ASYNC_REG of gtxreset_reg2_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \index[0]_i_1__7\ : label is "soft_lutpair174";
  attribute SOFT_HLUTNM of \index[1]_i_1__7\ : label is "soft_lutpair170";
  attribute SOFT_HLUTNM of \index[2]_i_1__7\ : label is "soft_lutpair170";
  attribute SOFT_HLUTNM of \index[4]_i_3__5\ : label is "soft_lutpair174";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1__7\ : label is "soft_lutpair173";
  attribute SOFT_HLUTNM of \mode_i_3__7\ : label is "soft_lutpair171";
  attribute ASYNC_REG of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute ASYNC_REG of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute ASYNC_REG of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg2_reg : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\addr_reg[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1471357514713564"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__5_n_0\,
      O => \addr_reg[0]_i_1__5_n_0\
    );
\addr_reg[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404050500F0F0500"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[1]_i_1__5_n_0\
    );
\addr_reg[2]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"051005105A055A00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(2),
      I4 => mode,
      I5 => index(1),
      O => \addr_reg[2]_i_1__5_n_0\
    );
\addr_reg[3]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5767576753275326"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => \addr_reg[4]_i_2__5_n_0\,
      I5 => index(0),
      O => \addr_reg[3]_i_1__5_n_0\
    );
\addr_reg[4]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FCCFFF01"
    )
        port map (
      I0 => \addr_reg[4]_i_2__5_n_0\,
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => index(4),
      O => \addr_reg[4]_i_1__5_n_0\
    );
\addr_reg[4]_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      O => \addr_reg[4]_i_2__5_n_0\
    );
\addr_reg[5]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001A1A0F0F0F0A"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[5]_i_1__5_n_0\
    );
\addr_reg[6]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011545554"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => mode,
      I3 => index(3),
      I4 => index(0),
      I5 => index(4),
      O => \addr_reg[6]_i_1__5_n_0\
    );
\addr_reg[7]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5422262254222633"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__5_n_0\,
      O => \addr_reg[7]_i_1__5_n_0\
    );
\addr_reg[7]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CE"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      I2 => index(0),
      O => \addr_reg[7]_i_2__5_n_0\
    );
\addr_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[0]_i_1__5_n_0\,
      Q => \addr_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[1]_i_1__5_n_0\,
      Q => \addr_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[2]_i_1__5_n_0\,
      Q => \addr_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[3]_i_1__5_n_0\,
      Q => \addr_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[4]_i_1__5_n_0\,
      Q => \addr_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[5]_i_1__5_n_0\,
      Q => \addr_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[6]_i_1__5_n_0\,
      Q => \addr_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[7]_i_1__5_n_0\,
      Q => \addr_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg[0]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B8BBB8B8B888"
    )
        port map (
      I0 => \di_reg[0]_i_4__5_n_0\,
      I1 => index(3),
      I2 => do_reg2(0),
      I3 => \di_reg[0]_i_5__5_n_0\,
      I4 => \di_reg[0]_i_6__5_n_0\,
      I5 => \di_reg[4]_i_8__5_n_0\,
      O => \di_reg[0]_i_2__5_n_0\
    );
\di_reg[0]_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003414"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(0),
      I4 => index(3),
      O => \di_reg[0]_i_3__5_n_0\
    );
\di_reg[0]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0BFFFFFB0B00000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => do_reg2(0),
      O => \di_reg[0]_i_4__5_n_0\
    );
\di_reg[0]_i_5__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      O => \di_reg[0]_i_5__5_n_0\
    );
\di_reg[0]_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => index(1),
      I1 => mode,
      I2 => index(0),
      O => \di_reg[0]_i_6__5_n_0\
    );
\di_reg[10]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(10),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[10]_i_2__5_n_0\,
      O => di_reg(10)
    );
\di_reg[10]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[10]_i_2__5_n_0\
    );
\di_reg[11]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[11]_i_2__5_n_0\,
      I2 => index(4),
      I3 => \di_reg[11]_i_3__5_n_0\,
      I4 => \di_reg[11]_i_4__5_n_0\,
      I5 => \di_reg[11]_i_5__5_n_0\,
      O => di_reg(11)
    );
\di_reg[11]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808380808"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(0),
      I4 => rate_reg2(1),
      I5 => index(0),
      O => \di_reg[11]_i_2__5_n_0\
    );
\di_reg[11]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC0CCC0C0C0C880C"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => do_reg2(11),
      I3 => index(2),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[11]_i_3__5_n_0\
    );
\di_reg[11]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAABAAABA"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[11]_i_4__5_n_0\
    );
\di_reg[11]_i_5__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA00AAAAAAA3"
    )
        port map (
      I0 => do_reg2(11),
      I1 => x16_reg2,
      I2 => \addr_reg[4]_i_2__5_n_0\,
      I3 => index(0),
      I4 => index(1),
      I5 => index(2),
      O => \di_reg[11]_i_5__5_n_0\
    );
\di_reg[12]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \di_reg[12]_i_2__5_n_0\,
      I1 => index(4),
      I2 => \di_reg[12]_i_3__5_n_0\,
      I3 => index(3),
      I4 => \di_reg[12]_i_4__5_n_0\,
      O => di_reg(12)
    );
\di_reg[12]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003202"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(12),
      I4 => index(3),
      O => \di_reg[12]_i_2__5_n_0\
    );
\di_reg[12]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(12),
      O => \di_reg[12]_i_3__5_n_0\
    );
\di_reg[12]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAA8AAABAAABA"
    )
        port map (
      I0 => do_reg2(12),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[12]_i_4__5_n_0\
    );
\di_reg[13]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \di_reg[13]_i_2__5_n_0\,
      I1 => index(4),
      I2 => \di_reg[13]_i_3__5_n_0\,
      I3 => index(3),
      I4 => \di_reg[13]_i_4__5_n_0\,
      O => di_reg(13)
    );
\di_reg[13]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080838380838"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[13]_i_2__5_n_0\
    );
\di_reg[13]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(13),
      O => \di_reg[13]_i_3__5_n_0\
    );
\di_reg[13]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAA8AAABAAA8A"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(1),
      I5 => rate_reg2(0),
      O => \di_reg[13]_i_4__5_n_0\
    );
\di_reg[14]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080008FF08000800"
    )
        port map (
      I0 => do_reg2(14),
      I1 => \di_reg[14]_i_2__5_n_0\,
      I2 => index(3),
      I3 => index(4),
      I4 => \di_reg[14]_i_3__5_n_0\,
      I5 => \di_reg[14]_i_4__5_n_0\,
      O => di_reg(14)
    );
\di_reg[14]_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[14]_i_2__5_n_0\
    );
\di_reg[14]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033303310130033"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => index(2),
      I3 => do_reg2(14),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[14]_i_3__5_n_0\
    );
\di_reg[14]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000DF10"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => do_reg2(14),
      I4 => index(2),
      I5 => \di_reg[14]_i_6__5_n_0\,
      O => \di_reg[14]_i_4__5_n_0\
    );
\di_reg[14]_i_5__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      O => data15(7)
    );
\di_reg[14]_i_6__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB3BBBBBBB3FBB"
    )
        port map (
      I0 => \di_reg[14]_i_7__5_n_0\,
      I1 => index(3),
      I2 => index(0),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => \di_reg[5]_i_4__5_n_0\,
      O => \di_reg[14]_i_6__5_n_0\
    );
\di_reg[14]_i_7__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => index(1),
      I1 => index(2),
      I2 => do_reg2(14),
      I3 => index(0),
      O => \di_reg[14]_i_7__5_n_0\
    );
\di_reg[15]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(15),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[15]_i_2__5_n_0\,
      O => di_reg(15)
    );
\di_reg[15]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[15]_i_2__5_n_0\
    );
\di_reg[1]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \di_reg[1]_i_2__5_n_0\,
      I1 => index(4),
      I2 => \di_reg[1]_i_3__5_n_0\,
      I3 => \di_reg[1]_i_4__5_n_0\,
      O => di_reg(1)
    );
\di_reg[1]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000034140000"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(1),
      I4 => index(4),
      I5 => index(3),
      O => \di_reg[1]_i_2__5_n_0\
    );
\di_reg[1]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FB330000"
    )
        port map (
      I0 => index(2),
      I1 => do_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(3),
      I5 => \di_reg[1]_i_5__5_n_0\,
      O => \di_reg[1]_i_3__5_n_0\
    );
\di_reg[1]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFCCC5555"
    )
        port map (
      I0 => \di_reg[1]_i_6__5_n_0\,
      I1 => do_reg2(1),
      I2 => index(1),
      I3 => index(0),
      I4 => index(2),
      I5 => index(3),
      O => \di_reg[1]_i_4__5_n_0\
    );
\di_reg[1]_i_5__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      I3 => index(1),
      O => \di_reg[1]_i_5__5_n_0\
    );
\di_reg[1]_i_6__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"002F0F20F02FFF2F"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(1),
      I3 => index(0),
      I4 => mode,
      I5 => do_reg2(1),
      O => \di_reg[1]_i_6__5_n_0\
    );
\di_reg[2]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \di_reg[2]_i_2__5_n_0\,
      I1 => \di_reg[2]_i_3__5_n_0\,
      O => di_reg(2)
    );
\di_reg[2]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00400500FFFFFFFF"
    )
        port map (
      I0 => index(3),
      I1 => do_reg2(2),
      I2 => index(2),
      I3 => index(1),
      I4 => index(0),
      I5 => index(4),
      O => \di_reg[2]_i_2__5_n_0\
    );
\di_reg[2]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF470047"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => \di_reg[2]_i_4__5_n_0\,
      I3 => index(3),
      I4 => \di_reg[2]_i_5__5_n_0\,
      I5 => index(4),
      O => \di_reg[2]_i_3__5_n_0\
    );
\di_reg[2]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F40404F00FF000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => mode,
      I4 => do_reg2(2),
      I5 => index(1),
      O => \di_reg[2]_i_4__5_n_0\
    );
\di_reg[2]_i_5__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5D535D5F5D5F5D5"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[2]_i_5__5_n_0\
    );
\di_reg[3]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAA1000AAFF0000"
    )
        port map (
      I0 => \di_reg[3]_i_4__5_n_0\,
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => do_reg2(3),
      I5 => index(0),
      O => \di_reg[3]_i_2__5_n_0\
    );
\di_reg[3]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000033E200"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => do_reg2(3),
      I3 => index(2),
      I4 => index(1),
      I5 => index(3),
      O => \di_reg[3]_i_3__5_n_0\
    );
\di_reg[3]_i_4__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      O => \di_reg[3]_i_4__5_n_0\
    );
\di_reg[4]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[4]_i_2__5_n_0\,
      I2 => index(4),
      I3 => \di_reg[4]_i_3__5_n_0\,
      I4 => \di_reg[4]_i_4__5_n_0\,
      I5 => \di_reg[4]_i_5__5_n_0\,
      O => di_reg(4)
    );
\di_reg[4]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080B0830303030"
    )
        port map (
      I0 => do_reg2(4),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[4]_i_2__5_n_0\
    );
\di_reg[4]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFFFFFFF"
    )
        port map (
      I0 => index(0),
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => index(1),
      I5 => \di_reg[4]_i_6__5_n_0\,
      O => \di_reg[4]_i_3__5_n_0\
    );
\di_reg[4]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFFE00000000"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      I2 => index(1),
      I3 => index(2),
      I4 => index(0),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_4__5_n_0\
    );
\di_reg[4]_i_5__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010C00"
    )
        port map (
      I0 => \di_reg[4]_i_7__5_n_0\,
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => \di_reg[4]_i_8__5_n_0\,
      I5 => index(3),
      O => \di_reg[4]_i_5__5_n_0\
    );
\di_reg[4]_i_6__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1F0FFF0F"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(3),
      I3 => do_reg2(4),
      I4 => index(1),
      O => \di_reg[4]_i_6__5_n_0\
    );
\di_reg[4]_i_7__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      O => \di_reg[4]_i_7__5_n_0\
    );
\di_reg[4]_i_8__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => \di_reg[4]_i_8__5_n_0\
    );
\di_reg[5]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33000000B888B888"
    )
        port map (
      I0 => \di_reg[5]_i_2__5_n_0\,
      I1 => index(4),
      I2 => \di_reg[5]_i_3__5_n_0\,
      I3 => do_reg2(5),
      I4 => \di_reg[5]_i_4__5_n_0\,
      I5 => index(3),
      O => di_reg(5)
    );
\di_reg[5]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B0B080B33333033"
    )
        port map (
      I0 => do_reg2(5),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[5]_i_2__5_n_0\
    );
\di_reg[5]_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(1),
      I3 => x16x20_mode_reg2,
      I4 => mode,
      O => \di_reg[5]_i_3__5_n_0\
    );
\di_reg[5]_i_4__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[5]_i_4__5_n_0\
    );
\di_reg[6]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"67FF000067000000"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(6),
      I5 => \di_reg[5]_i_3__5_n_0\,
      O => \di_reg[6]_i_2__5_n_0\
    );
\di_reg[6]_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002404"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(6),
      I4 => index(3),
      O => \di_reg[6]_i_3__5_n_0\
    );
\di_reg[7]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0900"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(7),
      O => \di_reg[7]_i_2__5_n_0\
    );
\di_reg[7]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000C320032"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => do_reg2(7),
      I5 => index(3),
      O => \di_reg[7]_i_3__5_n_0\
    );
\di_reg[8]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(8),
      O => di_reg(8)
    );
\di_reg[9]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(9),
      O => di_reg(9)
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(0),
      Q => \di_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[0]_i_1__5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[0]_i_2__5_n_0\,
      I1 => \di_reg[0]_i_3__5_n_0\,
      O => di_reg(0),
      S => index(4)
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(10),
      Q => \di_reg_reg_n_0_[10]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(11),
      Q => \di_reg_reg_n_0_[11]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(12),
      Q => \di_reg_reg_n_0_[12]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(13),
      Q => \di_reg_reg_n_0_[13]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(14),
      Q => \di_reg_reg_n_0_[14]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(15),
      Q => \di_reg_reg_n_0_[15]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(1),
      Q => \di_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(2),
      Q => \di_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(3),
      Q => \di_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]_i_1__5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[3]_i_2__5_n_0\,
      I1 => \di_reg[3]_i_3__5_n_0\,
      O => di_reg(3),
      S => index(4)
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(4),
      Q => \di_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(5),
      Q => \di_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(6),
      Q => \di_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]_i_1__5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[6]_i_2__5_n_0\,
      I1 => \di_reg[6]_i_3__5_n_0\,
      O => di_reg(6),
      S => index(4)
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(7),
      Q => \di_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[7]_i_1__5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[7]_i_2__5_n_0\,
      I1 => \di_reg[7]_i_3__5_n_0\,
      O => di_reg(7),
      S => index(4)
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(8),
      Q => \di_reg_reg_n_0_[8]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(9),
      Q => \di_reg_reg_n_0_[9]\,
      R => RST_DCLK_RESET
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(0),
      Q => do_reg1(0),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(10),
      Q => do_reg1(10),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(11),
      Q => do_reg1(11),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(12),
      Q => do_reg1(12),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(13),
      Q => do_reg1(13),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(14),
      Q => do_reg1(14),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(15),
      Q => do_reg1(15),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(1),
      Q => do_reg1(1),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(2),
      Q => do_reg1(2),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(3),
      Q => do_reg1(3),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(4),
      Q => do_reg1(4),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(5),
      Q => do_reg1(5),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(6),
      Q => do_reg1(6),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(7),
      Q => do_reg1(7),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(8),
      Q => do_reg1(8),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(9),
      Q => do_reg1(9),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => RST_DCLK_RESET
    );
\done_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => start_reg2,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \done_i_1__5_n_0\
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \done_i_1__5_n_0\,
      Q => DRP_DONE,
      R => RST_DCLK_RESET
    );
\fsm[0]_i_1__12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B3BFFFF0B3B0000"
    )
        port map (
      I0 => data4,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => rdy_reg2,
      I4 => \^q\(2),
      I5 => \fsm[0]_i_3__12_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFEFFFF"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(4),
      I3 => index(2),
      I4 => \mode_i_2__5_n_0\,
      O => data4
    );
\fsm[0]_i_3__12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7477FFFF7477CCCC"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \^q\(1),
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      I4 => \^q\(0),
      I5 => start_reg2,
      O => \fsm[0]_i_3__12_n_0\
    );
\fsm[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"185018501D501850"
    )
        port map (
      I0 => \^q\(2),
      I1 => rdy_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => load_cnt(0),
      I5 => load_cnt(1),
      O => fsm(1)
    );
\fsm[2]_i_1__12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6222"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      R => RST_DCLK_RESET
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      R => RST_DCLK_RESET
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_DCLK_RESET
    );
\gt_ch_drp_rdy[6]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => gt_ch_drp_rdy(0)
    );
\gtx_channel.gtxe2_channel_i_i_15__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(15),
      I1 => \di_reg_reg_n_0_[15]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(15)
    );
\gtx_channel.gtxe2_channel_i_i_16__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(14),
      I1 => \di_reg_reg_n_0_[14]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(14)
    );
\gtx_channel.gtxe2_channel_i_i_17__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(13),
      I1 => \di_reg_reg_n_0_[13]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(13)
    );
\gtx_channel.gtxe2_channel_i_i_18__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(12),
      I1 => \di_reg_reg_n_0_[12]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(12)
    );
\gtx_channel.gtxe2_channel_i_i_19__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(11),
      I1 => \di_reg_reg_n_0_[11]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(11)
    );
\gtx_channel.gtxe2_channel_i_i_20__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(10),
      I1 => \di_reg_reg_n_0_[10]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(10)
    );
\gtx_channel.gtxe2_channel_i_i_21__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(9),
      I1 => \di_reg_reg_n_0_[9]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(9)
    );
\gtx_channel.gtxe2_channel_i_i_22__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(8),
      I1 => \di_reg_reg_n_0_[8]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(8)
    );
\gtx_channel.gtxe2_channel_i_i_23__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(7),
      I1 => \di_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(7)
    );
\gtx_channel.gtxe2_channel_i_i_24__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(6),
      I1 => \di_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(6)
    );
\gtx_channel.gtxe2_channel_i_i_25__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(5),
      I1 => \di_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(5)
    );
\gtx_channel.gtxe2_channel_i_i_26__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(4),
      I1 => \di_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(4)
    );
\gtx_channel.gtxe2_channel_i_i_27__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(3),
      I1 => \di_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(3)
    );
\gtx_channel.gtxe2_channel_i_i_28__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(2),
      I1 => \di_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(2)
    );
\gtx_channel.gtxe2_channel_i_i_29__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(1),
      I1 => \di_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(1)
    );
\gtx_channel.gtxe2_channel_i_i_30__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(0),
      I1 => \di_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(0)
    );
\gtx_channel.gtxe2_channel_i_i_3__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"003E"
    )
        port map (
      I0 => ext_ch_gt_drpen(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \cplllock_reg1_reg[6]\
    );
\gtx_channel.gtxe2_channel_i_i_48__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => DRPADDR(8)
    );
\gtx_channel.gtxe2_channel_i_i_49__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(7),
      I1 => \addr_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(7)
    );
\gtx_channel.gtxe2_channel_i_i_4__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0032"
    )
        port map (
      I0 => ext_ch_gt_drpwe(0),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \cplllock_reg1_reg[6]_0\
    );
\gtx_channel.gtxe2_channel_i_i_50__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(6),
      I1 => \addr_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(6)
    );
\gtx_channel.gtxe2_channel_i_i_51__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(5),
      I1 => \addr_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(5)
    );
\gtx_channel.gtxe2_channel_i_i_52__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(4),
      I1 => \addr_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(4)
    );
\gtx_channel.gtxe2_channel_i_i_53__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(3),
      I1 => \addr_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(3)
    );
\gtx_channel.gtxe2_channel_i_i_54__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(2),
      I1 => \addr_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(2)
    );
\gtx_channel.gtxe2_channel_i_i_55__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(1),
      I1 => \addr_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(1)
    );
\gtx_channel.gtxe2_channel_i_i_56__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(0),
      I1 => \addr_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(0)
    );
gtxreset_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rst_gtreset,
      Q => gtxreset_reg1,
      R => RST_DCLK_RESET
    );
gtxreset_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => gtxreset_reg1,
      Q => gtxreset_reg2,
      R => RST_DCLK_RESET
    );
\index[0]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => index(0),
      I1 => \^q\(2),
      I2 => \index[3]_i_2__5_n_0\,
      O => \index[0]_i_1__7_n_0\
    );
\index[1]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__5_n_0\,
      I2 => index(1),
      I3 => index(0),
      O => \index[1]_i_1__7_n_0\
    );
\index[2]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02222000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__5_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      O => \index[2]_i_1__7_n_0\
    );
\index[3]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222222220000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__5_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => index(3),
      O => \index[3]_i_1__5_n_0\
    );
\index[3]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAE"
    )
        port map (
      I0 => \^q\(0),
      I1 => \mode_i_2__5_n_0\,
      I2 => index(2),
      I3 => index(4),
      I4 => index(1),
      I5 => index(3),
      O => \index[3]_i_2__5_n_0\
    );
\index[4]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"89"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \index[4]_i_1__5_n_0\
    );
\index[4]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => index(0),
      I1 => index(2),
      I2 => index(3),
      I3 => index(1),
      I4 => index(4),
      I5 => \index[4]_i_3__5_n_0\,
      O => \index[4]_i_2__5_n_0\
    );
\index[4]_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \index[3]_i_2__5_n_0\,
      I1 => \^q\(2),
      O => \index[4]_i_3__5_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__5_n_0\,
      D => \index[0]_i_1__7_n_0\,
      Q => index(0),
      R => RST_DCLK_RESET
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__5_n_0\,
      D => \index[1]_i_1__7_n_0\,
      Q => index(1),
      R => RST_DCLK_RESET
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__5_n_0\,
      D => \index[2]_i_1__7_n_0\,
      Q => index(2),
      R => RST_DCLK_RESET
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__5_n_0\,
      D => \index[3]_i_1__5_n_0\,
      Q => index(3),
      R => RST_DCLK_RESET
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__5_n_0\,
      D => \index[4]_i_2__5_n_0\,
      Q => index(4),
      R => RST_DCLK_RESET
    );
\load_cnt[0]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => load_cnt(1),
      I3 => \^q\(2),
      O => \load_cnt[0]_i_1__7_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[0]_i_1__7_n_0\,
      Q => load_cnt(0),
      R => RST_DCLK_RESET
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => load_cnt(1),
      R => RST_DCLK_RESET
    );
\mode_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AAA2AAAAAAAA00"
    )
        port map (
      I0 => mode,
      I1 => \mode_i_2__5_n_0\,
      I2 => \mode_i_3__7_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \mode_i_1__5_n_0\
    );
\mode_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCB8"
    )
        port map (
      I0 => mode,
      I1 => index(0),
      I2 => x16x20_mode_reg2,
      I3 => index(2),
      O => \mode_i_2__5_n_0\
    );
\mode_i_3__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF6"
    )
        port map (
      I0 => index(2),
      I1 => index(4),
      I2 => index(1),
      I3 => index(3),
      O => \mode_i_3__7_n_0\
    );
mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \mode_i_1__5_n_0\,
      Q => mode,
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_reg1(0),
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => RST_DCLK_RESET
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drprdy(0),
      Q => rdy_reg1,
      R => RST_DCLK_RESET
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => RST_DCLK_RESET
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_START,
      Q => start_reg1,
      R => RST_DCLK_RESET
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => RST_DCLK_RESET
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16,
      Q => x16_reg1,
      R => RST_DCLK_RESET
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16X20_MODE,
      Q => x16x20_mode_reg1,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16x20_mode_reg1,
      Q => x16x20_mode_reg2,
      R => RST_DCLK_RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_67 is
  port (
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \cplllock_reg1_reg[7]\ : out STD_LOGIC;
    \cplllock_reg1_reg[7]_0\ : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_DONE : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 );
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_X16X20_MODE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    ext_ch_gt_drprdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    DRP_X16 : in STD_LOGIC;
    ext_ch_gt_drpdo : in STD_LOGIC_VECTOR ( 15 downto 0 );
    rst_gtreset : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_67 : entity is "PCIeGen1x8If64_pipe_drp";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_67;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_67 is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \addr_reg[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \addr_reg[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \addr_reg[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \addr_reg[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \addr_reg[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \addr_reg[5]_i_1__6_n_0\ : STD_LOGIC;
  signal \addr_reg[6]_i_1__6_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_1__6_n_0\ : STD_LOGIC;
  signal \addr_reg[7]_i_2__6_n_0\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \addr_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal data15 : STD_LOGIC_VECTOR ( 7 to 7 );
  signal data4 : STD_LOGIC;
  signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di_reg[0]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_4__6_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_5__6_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_6__6_n_0\ : STD_LOGIC;
  signal \di_reg[10]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_4__6_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_5__6_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_4__6_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_4__6_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_4__6_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_6__6_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_7__6_n_0\ : STD_LOGIC;
  signal \di_reg[15]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_4__6_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_5__6_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_6__6_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_4__6_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_5__6_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_4__6_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_4__6_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_5__6_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_6__6_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_7__6_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_8__6_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_4__6_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_2__6_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_3__6_n_0\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \di_reg_reg_n_0_[9]\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \done_i_1__6_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm[0]_i_3__14_n_0\ : STD_LOGIC;
  signal gtxreset_reg1 : STD_LOGIC;
  signal gtxreset_reg2 : STD_LOGIC;
  signal index : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \index[0]_i_1__8_n_0\ : STD_LOGIC;
  signal \index[1]_i_1__8_n_0\ : STD_LOGIC;
  signal \index[2]_i_1__8_n_0\ : STD_LOGIC;
  signal \index[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \index[3]_i_2__6_n_0\ : STD_LOGIC;
  signal \index[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \index[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \index[4]_i_3__6_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1__8_n_0\ : STD_LOGIC;
  signal mode : STD_LOGIC;
  signal \mode_i_1__6_n_0\ : STD_LOGIC;
  signal \mode_i_2__6_n_0\ : STD_LOGIC;
  signal \mode_i_3__8_n_0\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rdy_reg1 : STD_LOGIC;
  signal rdy_reg2 : STD_LOGIC;
  signal start_reg1 : STD_LOGIC;
  signal start_reg2 : STD_LOGIC;
  signal x16_reg1 : STD_LOGIC;
  signal x16_reg2 : STD_LOGIC;
  signal x16x20_mode_reg1 : STD_LOGIC;
  signal x16x20_mode_reg2 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \di_reg[0]_i_5__6\ : label is "soft_lutpair199";
  attribute SOFT_HLUTNM of \di_reg[0]_i_6__6\ : label is "soft_lutpair200";
  attribute SOFT_HLUTNM of \di_reg[14]_i_2__6\ : label is "soft_lutpair199";
  attribute SOFT_HLUTNM of \di_reg[3]_i_4__6\ : label is "soft_lutpair200";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \fsm[0]_i_2__6\ : label is "soft_lutpair195";
  attribute SOFT_HLUTNM of \gt_ch_drp_rdy[7]_INST_0\ : label is "soft_lutpair193";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__6\ : label is "soft_lutpair196";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_48__6\ : label is "soft_lutpair196";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__6\ : label is "soft_lutpair197";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_51__6\ : label is "soft_lutpair193";
  attribute ASYNC_REG of gtxreset_reg1_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg1_reg : label is "yes";
  attribute ASYNC_REG of gtxreset_reg2_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \index[0]_i_1__8\ : label is "soft_lutpair198";
  attribute SOFT_HLUTNM of \index[1]_i_1__8\ : label is "soft_lutpair194";
  attribute SOFT_HLUTNM of \index[2]_i_1__8\ : label is "soft_lutpair194";
  attribute SOFT_HLUTNM of \index[4]_i_3__6\ : label is "soft_lutpair198";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1__8\ : label is "soft_lutpair197";
  attribute SOFT_HLUTNM of \mode_i_3__8\ : label is "soft_lutpair195";
  attribute ASYNC_REG of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute ASYNC_REG of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute ASYNC_REG of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of x16x20_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg2_reg : label is "yes";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\addr_reg[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1471357514713564"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__6_n_0\,
      O => \addr_reg[0]_i_1__6_n_0\
    );
\addr_reg[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404050500F0F0500"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[1]_i_1__6_n_0\
    );
\addr_reg[2]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"051005105A055A00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(2),
      I4 => mode,
      I5 => index(1),
      O => \addr_reg[2]_i_1__6_n_0\
    );
\addr_reg[3]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5767576753275326"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => \addr_reg[4]_i_2__6_n_0\,
      I5 => index(0),
      O => \addr_reg[3]_i_1__6_n_0\
    );
\addr_reg[4]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FCCFFF01"
    )
        port map (
      I0 => \addr_reg[4]_i_2__6_n_0\,
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => index(4),
      O => \addr_reg[4]_i_1__6_n_0\
    );
\addr_reg[4]_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      O => \addr_reg[4]_i_2__6_n_0\
    );
\addr_reg[5]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00001A1A0F0F0F0A"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => mode,
      I4 => index(1),
      I5 => index(2),
      O => \addr_reg[5]_i_1__6_n_0\
    );
\addr_reg[6]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000011545554"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => mode,
      I3 => index(3),
      I4 => index(0),
      I5 => index(4),
      O => \addr_reg[6]_i_1__6_n_0\
    );
\addr_reg[7]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5422262254222633"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => \addr_reg[7]_i_2__6_n_0\,
      O => \addr_reg[7]_i_1__6_n_0\
    );
\addr_reg[7]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CE"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      I2 => index(0),
      O => \addr_reg[7]_i_2__6_n_0\
    );
\addr_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[0]_i_1__6_n_0\,
      Q => \addr_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[1]_i_1__6_n_0\,
      Q => \addr_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[2]_i_1__6_n_0\,
      Q => \addr_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[3]_i_1__6_n_0\,
      Q => \addr_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[4]_i_1__6_n_0\,
      Q => \addr_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[5]_i_1__6_n_0\,
      Q => \addr_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[6]_i_1__6_n_0\,
      Q => \addr_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\addr_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \addr_reg[7]_i_1__6_n_0\,
      Q => \addr_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg[0]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8B8B8BBB8B8B888"
    )
        port map (
      I0 => \di_reg[0]_i_4__6_n_0\,
      I1 => index(3),
      I2 => do_reg2(0),
      I3 => \di_reg[0]_i_5__6_n_0\,
      I4 => \di_reg[0]_i_6__6_n_0\,
      I5 => \di_reg[4]_i_8__6_n_0\,
      O => \di_reg[0]_i_2__6_n_0\
    );
\di_reg[0]_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003414"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(0),
      I4 => index(3),
      O => \di_reg[0]_i_3__6_n_0\
    );
\di_reg[0]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0BFFFFFB0B00000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(2),
      I4 => index(1),
      I5 => do_reg2(0),
      O => \di_reg[0]_i_4__6_n_0\
    );
\di_reg[0]_i_5__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      O => \di_reg[0]_i_5__6_n_0\
    );
\di_reg[0]_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => index(1),
      I1 => mode,
      I2 => index(0),
      O => \di_reg[0]_i_6__6_n_0\
    );
\di_reg[10]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(10),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[10]_i_2__6_n_0\,
      O => di_reg(10)
    );
\di_reg[10]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[10]_i_2__6_n_0\
    );
\di_reg[11]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[11]_i_2__6_n_0\,
      I2 => index(4),
      I3 => \di_reg[11]_i_3__6_n_0\,
      I4 => \di_reg[11]_i_4__6_n_0\,
      I5 => \di_reg[11]_i_5__6_n_0\,
      O => di_reg(11)
    );
\di_reg[11]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080808380808"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(0),
      I4 => rate_reg2(1),
      I5 => index(0),
      O => \di_reg[11]_i_2__6_n_0\
    );
\di_reg[11]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC0CCC0C0C0C880C"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => do_reg2(11),
      I3 => index(2),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[11]_i_3__6_n_0\
    );
\di_reg[11]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAAAAAABAAABA"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[11]_i_4__6_n_0\
    );
\di_reg[11]_i_5__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA00AAAAAAA3"
    )
        port map (
      I0 => do_reg2(11),
      I1 => x16_reg2,
      I2 => \addr_reg[4]_i_2__6_n_0\,
      I3 => index(0),
      I4 => index(1),
      I5 => index(2),
      O => \di_reg[11]_i_5__6_n_0\
    );
\di_reg[12]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \di_reg[12]_i_2__6_n_0\,
      I1 => index(4),
      I2 => \di_reg[12]_i_3__6_n_0\,
      I3 => index(3),
      I4 => \di_reg[12]_i_4__6_n_0\,
      O => di_reg(12)
    );
\di_reg[12]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003202"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(12),
      I4 => index(3),
      O => \di_reg[12]_i_2__6_n_0\
    );
\di_reg[12]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(12),
      O => \di_reg[12]_i_3__6_n_0\
    );
\di_reg[12]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAAA8AAABAAABA"
    )
        port map (
      I0 => do_reg2(12),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[12]_i_4__6_n_0\
    );
\di_reg[13]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \di_reg[13]_i_2__6_n_0\,
      I1 => index(4),
      I2 => \di_reg[13]_i_3__6_n_0\,
      I3 => index(3),
      I4 => \di_reg[13]_i_4__6_n_0\,
      O => di_reg(13)
    );
\di_reg[13]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0808080838380838"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[13]_i_2__6_n_0\
    );
\di_reg[13]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => do_reg2(13),
      O => \di_reg[13]_i_3__6_n_0\
    );
\di_reg[13]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAA8AAABAAA8A"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => rate_reg2(1),
      I5 => rate_reg2(0),
      O => \di_reg[13]_i_4__6_n_0\
    );
\di_reg[14]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080008FF08000800"
    )
        port map (
      I0 => do_reg2(14),
      I1 => \di_reg[14]_i_2__6_n_0\,
      I2 => index(3),
      I3 => index(4),
      I4 => \di_reg[14]_i_3__6_n_0\,
      I5 => \di_reg[14]_i_4__6_n_0\,
      O => di_reg(14)
    );
\di_reg[14]_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[14]_i_2__6_n_0\
    );
\di_reg[14]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033303310130033"
    )
        port map (
      I0 => data15(7),
      I1 => index(3),
      I2 => index(2),
      I3 => do_reg2(14),
      I4 => index(0),
      I5 => index(1),
      O => \di_reg[14]_i_3__6_n_0\
    );
\di_reg[14]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000DF10"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => do_reg2(14),
      I4 => index(2),
      I5 => \di_reg[14]_i_6__6_n_0\,
      O => \di_reg[14]_i_4__6_n_0\
    );
\di_reg[14]_i_5__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      O => data15(7)
    );
\di_reg[14]_i_6__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBB3BBBBBBB3FBB"
    )
        port map (
      I0 => \di_reg[14]_i_7__6_n_0\,
      I1 => index(3),
      I2 => index(0),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => \di_reg[5]_i_4__6_n_0\,
      O => \di_reg[14]_i_6__6_n_0\
    );
\di_reg[14]_i_7__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => index(1),
      I1 => index(2),
      I2 => do_reg2(14),
      I3 => index(0),
      O => \di_reg[14]_i_7__6_n_0\
    );
\di_reg[15]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"544C4444044C4444"
    )
        port map (
      I0 => index(4),
      I1 => do_reg2(15),
      I2 => index(1),
      I3 => index(3),
      I4 => index(2),
      I5 => \di_reg[15]_i_2__6_n_0\,
      O => di_reg(15)
    );
\di_reg[15]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[15]_i_2__6_n_0\
    );
\di_reg[1]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"ABAA"
    )
        port map (
      I0 => \di_reg[1]_i_2__6_n_0\,
      I1 => index(4),
      I2 => \di_reg[1]_i_3__6_n_0\,
      I3 => \di_reg[1]_i_4__6_n_0\,
      O => di_reg(1)
    );
\di_reg[1]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000034140000"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(1),
      I4 => index(4),
      I5 => index(3),
      O => \di_reg[1]_i_2__6_n_0\
    );
\di_reg[1]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FB330000"
    )
        port map (
      I0 => index(2),
      I1 => do_reg2(1),
      I2 => index(0),
      I3 => index(1),
      I4 => index(3),
      I5 => \di_reg[1]_i_5__6_n_0\,
      O => \di_reg[1]_i_3__6_n_0\
    );
\di_reg[1]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFCCC5555"
    )
        port map (
      I0 => \di_reg[1]_i_6__6_n_0\,
      I1 => do_reg2(1),
      I2 => index(1),
      I3 => index(0),
      I4 => index(2),
      I5 => index(3),
      O => \di_reg[1]_i_4__6_n_0\
    );
\di_reg[1]_i_5__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      I3 => index(1),
      O => \di_reg[1]_i_5__6_n_0\
    );
\di_reg[1]_i_6__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"002F0F20F02FFF2F"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(1),
      I3 => index(0),
      I4 => mode,
      I5 => do_reg2(1),
      O => \di_reg[1]_i_6__6_n_0\
    );
\di_reg[2]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \di_reg[2]_i_2__6_n_0\,
      I1 => \di_reg[2]_i_3__6_n_0\,
      O => di_reg(2)
    );
\di_reg[2]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00400500FFFFFFFF"
    )
        port map (
      I0 => index(3),
      I1 => do_reg2(2),
      I2 => index(2),
      I3 => index(1),
      I4 => index(0),
      I5 => index(4),
      O => \di_reg[2]_i_2__6_n_0\
    );
\di_reg[2]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FF470047"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => \di_reg[2]_i_4__6_n_0\,
      I3 => index(3),
      I4 => \di_reg[2]_i_5__6_n_0\,
      I5 => index(4),
      O => \di_reg[2]_i_3__6_n_0\
    );
\di_reg[2]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4F40404F00FF000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(0),
      I3 => mode,
      I4 => do_reg2(2),
      I5 => index(1),
      O => \di_reg[2]_i_4__6_n_0\
    );
\di_reg[2]_i_5__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F5D535D5F5D5F5D5"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => rate_reg2(0),
      I5 => rate_reg2(1),
      O => \di_reg[2]_i_5__6_n_0\
    );
\di_reg[3]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAA1000AAFF0000"
    )
        port map (
      I0 => \di_reg[3]_i_4__6_n_0\,
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => do_reg2(3),
      I5 => index(0),
      O => \di_reg[3]_i_2__6_n_0\
    );
\di_reg[3]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000033E200"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => do_reg2(3),
      I3 => index(2),
      I4 => index(1),
      I5 => index(3),
      O => \di_reg[3]_i_3__6_n_0\
    );
\di_reg[3]_i_4__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      O => \di_reg[3]_i_4__6_n_0\
    );
\di_reg[4]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"404F404F404F4040"
    )
        port map (
      I0 => index(3),
      I1 => \di_reg[4]_i_2__6_n_0\,
      I2 => index(4),
      I3 => \di_reg[4]_i_3__6_n_0\,
      I4 => \di_reg[4]_i_4__6_n_0\,
      I5 => \di_reg[4]_i_5__6_n_0\,
      O => di_reg(4)
    );
\di_reg[4]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08080B0830303030"
    )
        port map (
      I0 => do_reg2(4),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[4]_i_2__6_n_0\
    );
\di_reg[4]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFFFFFFF"
    )
        port map (
      I0 => index(0),
      I1 => rate_reg2(0),
      I2 => rate_reg2(1),
      I3 => index(2),
      I4 => index(1),
      I5 => \di_reg[4]_i_6__6_n_0\,
      O => \di_reg[4]_i_3__6_n_0\
    );
\di_reg[4]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF0FFFFE00000000"
    )
        port map (
      I0 => mode,
      I1 => x16x20_mode_reg2,
      I2 => index(1),
      I3 => index(2),
      I4 => index(0),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_4__6_n_0\
    );
\di_reg[4]_i_5__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00010C00"
    )
        port map (
      I0 => \di_reg[4]_i_7__6_n_0\,
      I1 => index(1),
      I2 => index(2),
      I3 => index(0),
      I4 => \di_reg[4]_i_8__6_n_0\,
      I5 => index(3),
      O => \di_reg[4]_i_5__6_n_0\
    );
\di_reg[4]_i_6__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1F0FFF0F"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(3),
      I3 => do_reg2(4),
      I4 => index(1),
      O => \di_reg[4]_i_6__6_n_0\
    );
\di_reg[4]_i_7__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => x16x20_mode_reg2,
      I1 => mode,
      O => \di_reg[4]_i_7__6_n_0\
    );
\di_reg[4]_i_8__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => \di_reg[4]_i_8__6_n_0\
    );
\di_reg[5]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33000000B888B888"
    )
        port map (
      I0 => \di_reg[5]_i_2__6_n_0\,
      I1 => index(4),
      I2 => \di_reg[5]_i_3__6_n_0\,
      I3 => do_reg2(5),
      I4 => \di_reg[5]_i_4__6_n_0\,
      I5 => index(3),
      O => di_reg(5)
    );
\di_reg[5]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B0B080B33333033"
    )
        port map (
      I0 => do_reg2(5),
      I1 => index(2),
      I2 => index(1),
      I3 => rate_reg2(1),
      I4 => rate_reg2(0),
      I5 => index(0),
      O => \di_reg[5]_i_2__6_n_0\
    );
\di_reg[5]_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(1),
      I3 => x16x20_mode_reg2,
      I4 => mode,
      O => \di_reg[5]_i_3__6_n_0\
    );
\di_reg[5]_i_4__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      O => \di_reg[5]_i_4__6_n_0\
    );
\di_reg[6]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"67FF000067000000"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(6),
      I5 => \di_reg[5]_i_3__6_n_0\,
      O => \di_reg[6]_i_2__6_n_0\
    );
\di_reg[6]_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002404"
    )
        port map (
      I0 => index(0),
      I1 => index(1),
      I2 => index(2),
      I3 => do_reg2(6),
      I4 => index(3),
      O => \di_reg[6]_i_3__6_n_0\
    );
\di_reg[7]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0900"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(7),
      O => \di_reg[7]_i_2__6_n_0\
    );
\di_reg[7]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000C320032"
    )
        port map (
      I0 => data15(7),
      I1 => index(0),
      I2 => index(1),
      I3 => index(2),
      I4 => do_reg2(7),
      I5 => index(3),
      O => \di_reg[7]_i_3__6_n_0\
    );
\di_reg[8]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(8),
      O => di_reg(8)
    );
\di_reg[9]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"033733F300040000"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(2),
      I3 => index(3),
      I4 => index(1),
      I5 => do_reg2(9),
      O => di_reg(9)
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(0),
      Q => \di_reg_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[0]_i_1__6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[0]_i_2__6_n_0\,
      I1 => \di_reg[0]_i_3__6_n_0\,
      O => di_reg(0),
      S => index(4)
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(10),
      Q => \di_reg_reg_n_0_[10]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(11),
      Q => \di_reg_reg_n_0_[11]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(12),
      Q => \di_reg_reg_n_0_[12]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(13),
      Q => \di_reg_reg_n_0_[13]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(14),
      Q => \di_reg_reg_n_0_[14]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(15),
      Q => \di_reg_reg_n_0_[15]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(1),
      Q => \di_reg_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(2),
      Q => \di_reg_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(3),
      Q => \di_reg_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[3]_i_1__6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[3]_i_2__6_n_0\,
      I1 => \di_reg[3]_i_3__6_n_0\,
      O => di_reg(3),
      S => index(4)
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(4),
      Q => \di_reg_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(5),
      Q => \di_reg_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(6),
      Q => \di_reg_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[6]_i_1__6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[6]_i_2__6_n_0\,
      I1 => \di_reg[6]_i_3__6_n_0\,
      O => di_reg(6),
      S => index(4)
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(7),
      Q => \di_reg_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[7]_i_1__6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[7]_i_2__6_n_0\,
      I1 => \di_reg[7]_i_3__6_n_0\,
      O => di_reg(7),
      S => index(4)
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(8),
      Q => \di_reg_reg_n_0_[8]\,
      R => RST_DCLK_RESET
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di_reg(9),
      Q => \di_reg_reg_n_0_[9]\,
      R => RST_DCLK_RESET
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(0),
      Q => do_reg1(0),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(10),
      Q => do_reg1(10),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(11),
      Q => do_reg1(11),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(12),
      Q => do_reg1(12),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(13),
      Q => do_reg1(13),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(14),
      Q => do_reg1(14),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(15),
      Q => do_reg1(15),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(1),
      Q => do_reg1(1),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(2),
      Q => do_reg1(2),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(3),
      Q => do_reg1(3),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(4),
      Q => do_reg1(4),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(5),
      Q => do_reg1(5),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(6),
      Q => do_reg1(6),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(7),
      Q => do_reg1(7),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(8),
      Q => do_reg1(8),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drpdo(9),
      Q => do_reg1(9),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => RST_DCLK_RESET
    );
\done_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => start_reg2,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \done_i_1__6_n_0\
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \done_i_1__6_n_0\,
      Q => DRP_DONE,
      R => RST_DCLK_RESET
    );
\fsm[0]_i_1__14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0B3BFFFF0B3B0000"
    )
        port map (
      I0 => data4,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => rdy_reg2,
      I4 => \^q\(2),
      I5 => \fsm[0]_i_3__14_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFEFFFF"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(4),
      I3 => index(2),
      I4 => \mode_i_2__6_n_0\,
      O => data4
    );
\fsm[0]_i_3__14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7477FFFF7477CCCC"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \^q\(1),
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      I4 => \^q\(0),
      I5 => start_reg2,
      O => \fsm[0]_i_3__14_n_0\
    );
\fsm[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"185018501D501850"
    )
        port map (
      I0 => \^q\(2),
      I1 => rdy_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => load_cnt(0),
      I5 => load_cnt(1),
      O => fsm(1)
    );
\fsm[2]_i_1__14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6222"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      R => RST_DCLK_RESET
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      R => RST_DCLK_RESET
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_DCLK_RESET
    );
\gt_ch_drp_rdy[7]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => gt_ch_drp_rdy(0)
    );
\gtx_channel.gtxe2_channel_i_i_15__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(15),
      I1 => \di_reg_reg_n_0_[15]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(15)
    );
\gtx_channel.gtxe2_channel_i_i_16__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(14),
      I1 => \di_reg_reg_n_0_[14]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(14)
    );
\gtx_channel.gtxe2_channel_i_i_17__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(13),
      I1 => \di_reg_reg_n_0_[13]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(13)
    );
\gtx_channel.gtxe2_channel_i_i_18__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(12),
      I1 => \di_reg_reg_n_0_[12]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(12)
    );
\gtx_channel.gtxe2_channel_i_i_19__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(11),
      I1 => \di_reg_reg_n_0_[11]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(11)
    );
\gtx_channel.gtxe2_channel_i_i_20__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(10),
      I1 => \di_reg_reg_n_0_[10]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(10)
    );
\gtx_channel.gtxe2_channel_i_i_21__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(9),
      I1 => \di_reg_reg_n_0_[9]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(9)
    );
\gtx_channel.gtxe2_channel_i_i_22__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(8),
      I1 => \di_reg_reg_n_0_[8]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(8)
    );
\gtx_channel.gtxe2_channel_i_i_23__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(7),
      I1 => \di_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(7)
    );
\gtx_channel.gtxe2_channel_i_i_24__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(6),
      I1 => \di_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(6)
    );
\gtx_channel.gtxe2_channel_i_i_25__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(5),
      I1 => \di_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(5)
    );
\gtx_channel.gtxe2_channel_i_i_26__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(4),
      I1 => \di_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(4)
    );
\gtx_channel.gtxe2_channel_i_i_27__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(3),
      I1 => \di_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(3)
    );
\gtx_channel.gtxe2_channel_i_i_28__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(2),
      I1 => \di_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(2)
    );
\gtx_channel.gtxe2_channel_i_i_29__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(1),
      I1 => \di_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(1)
    );
\gtx_channel.gtxe2_channel_i_i_30__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(0),
      I1 => \di_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(0)
    );
\gtx_channel.gtxe2_channel_i_i_3__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"003E"
    )
        port map (
      I0 => ext_ch_gt_drpen(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \cplllock_reg1_reg[7]\
    );
\gtx_channel.gtxe2_channel_i_i_48__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => DRPADDR(8)
    );
\gtx_channel.gtxe2_channel_i_i_49__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(7),
      I1 => \addr_reg_reg_n_0_[7]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(7)
    );
\gtx_channel.gtxe2_channel_i_i_4__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0032"
    )
        port map (
      I0 => ext_ch_gt_drpwe(0),
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      O => \cplllock_reg1_reg[7]_0\
    );
\gtx_channel.gtxe2_channel_i_i_50__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(6),
      I1 => \addr_reg_reg_n_0_[6]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(6)
    );
\gtx_channel.gtxe2_channel_i_i_51__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(5),
      I1 => \addr_reg_reg_n_0_[5]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(5)
    );
\gtx_channel.gtxe2_channel_i_i_52__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(4),
      I1 => \addr_reg_reg_n_0_[4]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(4)
    );
\gtx_channel.gtxe2_channel_i_i_53__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(3),
      I1 => \addr_reg_reg_n_0_[3]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(3)
    );
\gtx_channel.gtxe2_channel_i_i_54__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(2),
      I1 => \addr_reg_reg_n_0_[2]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(2)
    );
\gtx_channel.gtxe2_channel_i_i_55__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(1),
      I1 => \addr_reg_reg_n_0_[1]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(1)
    );
\gtx_channel.gtxe2_channel_i_i_56__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(0),
      I1 => \addr_reg_reg_n_0_[0]\,
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(0)
    );
gtxreset_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rst_gtreset,
      Q => gtxreset_reg1,
      R => RST_DCLK_RESET
    );
gtxreset_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => gtxreset_reg1,
      Q => gtxreset_reg2,
      R => RST_DCLK_RESET
    );
\index[0]_i_1__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => index(0),
      I1 => \^q\(2),
      I2 => \index[3]_i_2__6_n_0\,
      O => \index[0]_i_1__8_n_0\
    );
\index[1]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__6_n_0\,
      I2 => index(1),
      I3 => index(0),
      O => \index[1]_i_1__8_n_0\
    );
\index[2]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02222000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__6_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      O => \index[2]_i_1__8_n_0\
    );
\index[3]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0222222220000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \index[3]_i_2__6_n_0\,
      I2 => index(0),
      I3 => index(1),
      I4 => index(2),
      I5 => index(3),
      O => \index[3]_i_1__6_n_0\
    );
\index[3]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAE"
    )
        port map (
      I0 => \^q\(0),
      I1 => \mode_i_2__6_n_0\,
      I2 => index(2),
      I3 => index(4),
      I4 => index(1),
      I5 => index(3),
      O => \index[3]_i_2__6_n_0\
    );
\index[4]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"89"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      O => \index[4]_i_1__6_n_0\
    );
\index[4]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => index(0),
      I1 => index(2),
      I2 => index(3),
      I3 => index(1),
      I4 => index(4),
      I5 => \index[4]_i_3__6_n_0\,
      O => \index[4]_i_2__6_n_0\
    );
\index[4]_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \index[3]_i_2__6_n_0\,
      I1 => \^q\(2),
      O => \index[4]_i_3__6_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__6_n_0\,
      D => \index[0]_i_1__8_n_0\,
      Q => index(0),
      R => RST_DCLK_RESET
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__6_n_0\,
      D => \index[1]_i_1__8_n_0\,
      Q => index(1),
      R => RST_DCLK_RESET
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__6_n_0\,
      D => \index[2]_i_1__8_n_0\,
      Q => index(2),
      R => RST_DCLK_RESET
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__6_n_0\,
      D => \index[3]_i_1__6_n_0\,
      Q => index(3),
      R => RST_DCLK_RESET
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \index[4]_i_1__6_n_0\,
      D => \index[4]_i_2__6_n_0\,
      Q => index(4),
      R => RST_DCLK_RESET
    );
\load_cnt[0]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => load_cnt(1),
      I3 => \^q\(2),
      O => \load_cnt[0]_i_1__8_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[0]_i_1__8_n_0\,
      Q => load_cnt(0),
      R => RST_DCLK_RESET
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => load_cnt(1),
      R => RST_DCLK_RESET
    );
\mode_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AAA2AAAAAAAA00"
    )
        port map (
      I0 => mode,
      I1 => \mode_i_2__6_n_0\,
      I2 => \mode_i_3__8_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \^q\(2),
      O => \mode_i_1__6_n_0\
    );
\mode_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"CCB8"
    )
        port map (
      I0 => mode,
      I1 => index(0),
      I2 => x16x20_mode_reg2,
      I3 => index(2),
      O => \mode_i_2__6_n_0\
    );
\mode_i_3__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF6"
    )
        port map (
      I0 => index(2),
      I1 => index(4),
      I2 => index(1),
      I3 => index(3),
      O => \mode_i_3__8_n_0\
    );
mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \mode_i_1__6_n_0\,
      Q => mode,
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_reg1(0),
      R => RST_DCLK_RESET
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => RST_DCLK_RESET
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => RST_DCLK_RESET
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ext_ch_gt_drprdy(0),
      Q => rdy_reg1,
      R => RST_DCLK_RESET
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => RST_DCLK_RESET
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_START,
      Q => start_reg1,
      R => RST_DCLK_RESET
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => RST_DCLK_RESET
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16,
      Q => x16_reg1,
      R => RST_DCLK_RESET
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_X16X20_MODE,
      Q => x16x20_mode_reg1,
      R => RST_DCLK_RESET
    );
x16x20_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => x16x20_mode_reg1,
      Q => x16x20_mode_reg2,
      R => RST_DCLK_RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RESETOVRD_START : out STD_LOGIC;
    RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_TXSYNC_START : out STD_LOGIC;
    DRP_X16X20_MODE0 : out STD_LOGIC;
    DRP_X160 : out STD_LOGIC;
    DRP_START0 : out STD_LOGIC;
    \cplllock_reg1_reg[0]\ : out STD_LOGIC;
    rate_gen3 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[0]_0\ : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_RATE_DONE : out STD_LOGIC;
    USER_RATE_RXSYNC : out STD_LOGIC;
    SYNC_RXSYNC_START : out STD_LOGIC;
    RST_RATE_IDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    GT_TXPMARESET0 : out STD_LOGIC;
    USER_PCLK_SEL : out STD_LOGIC;
    QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in2_in : out STD_LOGIC;
    QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in3_in : out STD_LOGIC;
    out1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RST_DRP_X16X20_MODE : in STD_LOGIC;
    RST_DRP_X16 : in STD_LOGIC;
    RST_DRP_START : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_CPLLLOCK : in STD_LOGIC;
    RATE_QPLLLOCK : in STD_LOGIC;
    RATE_DRP_DONE : in STD_LOGIC;
    RATE_MMCM_LOCK : in STD_LOGIC;
    RATE_PHYSTATUS : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    USER_RXRESETDONE : in STD_LOGIC;
    RATE_TXRATEDONE : in STD_LOGIC;
    RATE_RXRATEDONE : in STD_LOGIC;
    RATE_RESETOVRD_DONE : in STD_LOGIC;
    RATE_TXSYNC_DONE : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    p_0_in7_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate : entity is "PCIeGen1x8If64_pipe_rate";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate is
  signal \^gt_txpmareset0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^user_pclk_sel\ : STD_LOGIC;
  signal cplllock_reg1 : STD_LOGIC;
  signal cplllock_reg2 : STD_LOGIC;
  signal cpllpd_i_1_n_0 : STD_LOGIC;
  signal \cpllreset_i_1__0_n_0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC;
  signal drp_done_reg2 : STD_LOGIC;
  signal drp_start_i_1_n_0 : STD_LOGIC;
  signal drp_x16_i_1_n_0 : STD_LOGIC;
  signal drp_x16x20_mode_i_1_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal \fsm[0]_i_10_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_11_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_12_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_3_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_4_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_5_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_6_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_7_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_8_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_9_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_4_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_5_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_6_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_7_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_8_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_9_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_2_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_3_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_4_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_5_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_2_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_3_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_4_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_5_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_8_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_9_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_2_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_3_n_0\ : STD_LOGIC;
  signal \fsm_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_2_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_3_n_0\ : STD_LOGIC;
  signal gen3_exit : STD_LOGIC;
  signal gen3_exit_i_1_n_0 : STD_LOGIC;
  signal gen3_exit_i_2_n_0 : STD_LOGIC;
  signal gen3_i_1_n_0 : STD_LOGIC;
  signal gen3_i_2_n_0 : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^p_0_in2_in\ : STD_LOGIC;
  signal \^p_0_in3_in\ : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_0_in5_in : STD_LOGIC;
  signal p_0_in6_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pclk_sel_i_1__0_n_0\ : STD_LOGIC;
  signal pclk_sel_i_2_n_0 : STD_LOGIC;
  signal phystatus_i_1_n_0 : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  signal phystatus_reg2 : STD_LOGIC;
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal pll_lock : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  signal qplllock_reg2 : STD_LOGIC;
  signal qpllpd : STD_LOGIC;
  signal \qpllpd_i_1__0_n_0\ : STD_LOGIC;
  signal qpllreset : STD_LOGIC;
  signal \qpllreset_i_1__0_n_0\ : STD_LOGIC;
  signal \^rate_gen3\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rate_out[0]_i_1_n_0\ : STD_LOGIC;
  signal \rate_out[1]_i_1_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_1_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_2_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_3_n_0\ : STD_LOGIC;
  signal ratedone_i_1_n_0 : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal resetovrd_done_reg1 : STD_LOGIC;
  signal resetovrd_done_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  signal rxratedone_i_1_n_0 : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  signal rxratedone_reg2 : STD_LOGIC;
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxsync_done_reg1 : STD_LOGIC;
  signal rxsync_done_reg2 : STD_LOGIC;
  signal \sysclksel[0]_i_1_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_2_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_3_n_0\ : STD_LOGIC;
  signal \sysclksel[1]_i_1_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txpmareset_i_1_n_0 : STD_LOGIC;
  signal txpmareset_i_2_n_0 : STD_LOGIC;
  signal txratedone_i_1_n_0 : STD_LOGIC;
  signal txratedone_i_2_n_0 : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  signal txratedone_reg2 : STD_LOGIC;
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC;
  signal txsync_done_reg2 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of cplllock_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of cplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of cplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of cplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of cpllpd_i_2 : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of cpllreset_i_2 : label is "soft_lutpair37";
  attribute ASYNC_REG of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of drp_start_i_1 : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of drp_x16_i_1 : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of drp_x16x20_mode_i_1 : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \fsm[0]_i_9\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \fsm[3]_i_5\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of gen3_i_2 : label is "soft_lutpair40";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of pclk_sel_i_2 : label is "soft_lutpair37";
  attribute ASYNC_REG of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of rate_done_reg1_i_1 : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \rate_idle_reg1[0]_i_1\ : label is "soft_lutpair40";
  attribute ASYNC_REG of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SOFT_HLUTNM of \rate_out[1]_i_1\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \rate_out[2]_i_1\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of rate_rxsync_reg1_i_1 : label is "soft_lutpair32";
  attribute ASYNC_REG of resetovrd_done_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_done_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of resetovrd_start_reg1_i_1 : label is "soft_lutpair31";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of rxsync_start_reg1_i_1 : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of txpmareset_i_2 : label is "soft_lutpair39";
  attribute ASYNC_REG of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
begin
  GT_TXPMARESET0 <= \^gt_txpmareset0\;
  Q(4 downto 0) <= \^q\(4 downto 0);
  QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0);
  QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0);
  RXRATE(2 downto 0) <= \^rxrate\(2 downto 0);
  RXSYSCLKSEL(1 downto 0) <= \^rxsysclksel\(1 downto 0);
  USER_PCLK_SEL <= \^user_pclk_sel\;
  p_0_in2_in <= \^p_0_in2_in\;
  p_0_in3_in <= \^p_0_in3_in\;
  rate_gen3(0) <= \^rate_gen3\(0);
cplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => RATE_CPLLLOCK,
      Q => cplllock_reg1,
      R => RST_CPLLRESET
    );
cplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => cplllock_reg1,
      Q => cplllock_reg2,
      R => RST_CPLLRESET
    );
cpllpd_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^p_0_in3_in\,
      O => cpllpd_i_1_n_0
    );
cpllpd_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000084"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(0),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => qpllpd
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => cpllpd_i_1_n_0,
      Q => \^p_0_in3_in\,
      R => RST_CPLLRESET
    );
\cpllreset_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^p_0_in2_in\,
      O => \cpllreset_i_1__0_n_0\
    );
cpllreset_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"81000002"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => qpllreset
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \cpllreset_i_1__0_n_0\,
      Q => \^p_0_in2_in\,
      R => RST_CPLLRESET
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => RATE_DRP_DONE,
      Q => drp_done_reg1,
      R => RST_CPLLRESET
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => RST_CPLLRESET
    );
drp_start_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08200108"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => \^q\(1),
      O => drp_start_i_1_n_0
    );
drp_start_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => drp_start_i_1_n_0,
      Q => p_0_in4_in,
      R => RST_CPLLRESET
    );
drp_x16_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20020006"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(4),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(0),
      O => drp_x16_i_1_n_0
    );
drp_x16_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => drp_x16_i_1_n_0,
      Q => p_0_in5_in,
      R => RST_CPLLRESET
    );
drp_x16x20_mode_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20001584"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => drp_x16x20_mode_i_1_n_0
    );
drp_x16x20_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => drp_x16x20_mode_i_1_n_0,
      Q => p_0_in6_in,
      R => RST_CPLLRESET
    );
\fsm[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBB88888BBB8BBB8"
    )
        port map (
      I0 => \fsm_reg[0]_i_2_n_0\,
      I1 => \^q\(4),
      I2 => \fsm[0]_i_3_n_0\,
      I3 => \^q\(3),
      I4 => \fsm[0]_i_4_n_0\,
      I5 => \fsm[0]_i_5_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \txdata_wait_cnt_reg__0\(3),
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(0),
      I3 => \txdata_wait_cnt_reg__0\(1),
      O => \fsm[0]_i_10_n_0\
    );
\fsm[0]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F404"
    )
        port map (
      I0 => rxpmaresetdone_reg2,
      I1 => mmcm_lock_reg2,
      I2 => \^q\(0),
      I3 => drp_done_reg2,
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \fsm[0]_i_11_n_0\
    );
\fsm[0]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F737F4343404C"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => rxpmaresetdone_reg2,
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[0]_i_12_n_0\
    );
\fsm[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0344FF440344FF77"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => pll_lock,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \fsm[3]_i_9_n_0\,
      O => \fsm[0]_i_3_n_0\
    );
\fsm[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0000000F800F000"
    )
        port map (
      I0 => pll_lock,
      I1 => rst_idle_reg2,
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => drp_done_reg2,
      I5 => \^q\(0),
      O => \fsm[0]_i_4_n_0\
    );
\fsm[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCC8C0C8"
    )
        port map (
      I0 => \fsm[0]_i_8_n_0\,
      I1 => \^q\(3),
      I2 => \fsm[0]_i_9_n_0\,
      I3 => \^q\(0),
      I4 => \fsm[0]_i_10_n_0\,
      I5 => \fsm[0]_i_11_n_0\,
      O => \fsm[0]_i_5_n_0\
    );
\fsm[0]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0040"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \fsm[0]_i_12_n_0\,
      O => \fsm[0]_i_6_n_0\
    );
\fsm[0]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03880333"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[0]_i_7_n_0\
    );
\fsm[0]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77770777"
    )
        port map (
      I0 => p_0_in7_in,
      I1 => p_1_in8_in,
      I2 => rxresetdone_reg2,
      I3 => txresetdone_reg2,
      I4 => phystatus_reg2,
      O => \fsm[0]_i_8_n_0\
    );
\fsm[0]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      O => \fsm[0]_i_9_n_0\
    );
\fsm[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BBFC00"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_8_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_4_n_0\
    );
\fsm[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC88300000BB3000"
    )
        port map (
      I0 => \fsm[0]_i_10_n_0\,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_9_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[1]_i_5_n_0\
    );
\fsm[1]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70F040F0"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => drp_done_reg2,
      O => \fsm[1]_i_6_n_0\
    );
\fsm[1]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03777700"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_7_n_0\
    );
\fsm[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"53F5FFFFFFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => qplllock_reg2,
      I2 => rate_in_reg2(0),
      I3 => rate_in_reg2(1),
      I4 => rst_idle_reg2,
      I5 => \^q\(0),
      O => \fsm[1]_i_8_n_0\
    );
\fsm[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF4575FFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      I3 => qplllock_reg2,
      I4 => rst_idle_reg2,
      I5 => drp_done_reg2,
      O => \fsm[1]_i_9_n_0\
    );
\fsm[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fsm[2]_i_2_n_0\,
      I1 => \fsm[2]_i_3_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[2]_i_4_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[2]_i_5_n_0\,
      O => fsm(2)
    );
\fsm[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3C0C4040"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_done_reg2,
      I4 => \^q\(0),
      O => \fsm[2]_i_2_n_0\
    );
\fsm[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13CCD3CC1FCCDFCC"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => resetovrd_done_reg2,
      I5 => fsm1,
      O => \fsm[2]_i_3_n_0\
    );
\fsm[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BC0C"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \fsm[2]_i_4_n_0\
    );
\fsm[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4A4A4A4AAAAFAAAA"
    )
        port map (
      I0 => \^q\(2),
      I1 => pll_lock,
      I2 => \^q\(1),
      I3 => \fsm[3]_i_9_n_0\,
      I4 => \fsm[3]_i_8_n_0\,
      I5 => \^q\(0),
      O => \fsm[2]_i_5_n_0\
    );
\fsm[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFE0EFEFEFE0E0E0"
    )
        port map (
      I0 => \fsm[3]_i_2_n_0\,
      I1 => \fsm[3]_i_3_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[3]_i_4_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[3]_i_5_n_0\,
      O => fsm(3)
    );
\fsm[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22AA2A22"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => rxsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[3]_i_2_n_0\
    );
\fsm[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3020002000000000"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => resetovrd_done_reg2,
      I5 => \^q\(0),
      O => \fsm[3]_i_3_n_0\
    );
\fsm[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F545F555FFFFFFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rst_idle_reg2,
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => pll_lock,
      I5 => \^q\(1),
      O => \fsm[3]_i_4_n_0\
    );
\fsm[3]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80808180"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \fsm[3]_i_8_n_0\,
      I4 => \fsm[3]_i_9_n_0\,
      O => \fsm[3]_i_5_n_0\
    );
\fsm[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF8F8FFF8"
    )
        port map (
      I0 => p_1_in8_in,
      I1 => p_0_in7_in,
      I2 => ratedone_reg_n_0,
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg2(0),
      I5 => gen3_exit,
      O => fsm1
    );
\fsm[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => cplllock_reg2,
      O => pll_lock
    );
\fsm[3]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg1(1),
      O => \fsm[3]_i_8_n_0\
    );
\fsm[3]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rate_in_reg1(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(1),
      I3 => rate_in_reg2(1),
      O => \fsm[3]_i_9_n_0\
    );
\fsm[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08880000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \fsm[4]_i_2_n_0\
    );
\fsm[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5F75FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rxsync_done_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \fsm[4]_i_3_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\fsm_reg[0]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[0]_i_6_n_0\,
      I1 => \fsm[0]_i_7_n_0\,
      O => \fsm_reg[0]_i_2_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      S => RST_CPLLRESET
    );
\fsm_reg[1]_i_1\: unisim.vcomponents.MUXF8
     port map (
      I0 => \fsm_reg[1]_i_2_n_0\,
      I1 => \fsm_reg[1]_i_3_n_0\,
      O => fsm(1),
      S => \^q\(4)
    );
\fsm_reg[1]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_4_n_0\,
      I1 => \fsm[1]_i_5_n_0\,
      O => \fsm_reg[1]_i_2_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]_i_3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_6_n_0\,
      I1 => \fsm[1]_i_7_n_0\,
      O => \fsm_reg[1]_i_3_n_0\,
      S => \^q\(3)
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\fsm_reg[4]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[4]_i_2_n_0\,
      I1 => \fsm[4]_i_3_n_0\,
      O => fsm(4),
      S => \^q\(4)
    );
gen3_exit_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => gen3_exit_i_2_n_0,
      I4 => gen3_exit,
      O => gen3_exit_i_1_n_0
    );
gen3_exit_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000000000001"
    )
        port map (
      I0 => \fsm[3]_i_9_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => gen3_exit_i_2_n_0
    );
gen3_exit_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => gen3_exit_i_1_n_0,
      Q => gen3_exit,
      R => RST_CPLLRESET
    );
gen3_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => gen3_i_2_n_0,
      I4 => \^rate_gen3\(0),
      O => gen3_i_1_n_0
    );
gen3_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000008"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(1),
      O => gen3_i_2_n_0
    );
gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => gen3_i_1_n_0,
      Q => \^rate_gen3\(0),
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_6__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[0]_0\
    );
\gtx_channel.gtxe2_channel_i_i_7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[0]\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => RATE_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
\pclk_sel_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06FF0600"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => pclk_sel_i_2_n_0,
      I4 => \^user_pclk_sel\,
      O => \pclk_sel_i_1__0_n_0\
    );
pclk_sel_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80040800"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => pclk_sel_i_2_n_0
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \pclk_sel_i_1__0_n_0\,
      Q => \^user_pclk_sel\,
      R => RST_CPLLRESET
    );
phystatus_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => txratedone_i_2_n_0,
      I2 => phystatus_reg_n_0,
      O => phystatus_i_1_n_0
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => phystatus_i_1_n_0,
      Q => phystatus_reg_n_0,
      R => '0'
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => RATE_PHYSTATUS,
      Q => phystatus_reg1,
      R => RST_CPLLRESET
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => RST_CPLLRESET
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => RATE_QPLLLOCK,
      Q => qplllock_reg1,
      R => RST_CPLLRESET
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => RST_CPLLRESET
    );
\qpllpd_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^qrst_qpllpd_in\(0),
      O => \qpllpd_i_1__0_n_0\
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \qpllpd_i_1__0_n_0\,
      Q => \^qrst_qpllpd_in\(0),
      R => RST_CPLLRESET
    );
\qpllreset_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^qrst_qpllreset_in\(0),
      O => \qpllreset_i_1__0_n_0\
    );
qpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \qpllreset_i_1__0_n_0\,
      Q => \^qrst_qpllreset_in\(0),
      R => RST_CPLLRESET
    );
rate_done_reg1_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => USER_RATE_DONE
    );
\rate_idle_reg1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => RST_RATE_IDLE(0)
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_in_reg1(0),
      R => RST_CPLLRESET
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => RST_CPLLRESET
    );
\rate_out[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      I2 => \^q\(1),
      I3 => \rate_out[2]_i_2_n_0\,
      I4 => \^rxrate\(0),
      O => \rate_out[0]_i_1_n_0\
    );
\rate_out[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2_n_0\,
      I1 => \^rxrate\(1),
      O => \rate_out[1]_i_1_n_0\
    );
\rate_out[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2_n_0\,
      I1 => \^rxrate\(2),
      O => \rate_out[2]_i_1_n_0\
    );
\rate_out[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000002080000220"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \rate_out[2]_i_3_n_0\,
      O => \rate_out[2]_i_2_n_0\
    );
\rate_out[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => gen3_exit,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      O => \rate_out[2]_i_3_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rate_out[0]_i_1_n_0\,
      Q => \^rxrate\(0),
      R => RST_CPLLRESET
    );
\rate_out_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rate_out[1]_i_1_n_0\,
      Q => \^rxrate\(1),
      R => RST_CPLLRESET
    );
\rate_out_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rate_out[2]_i_1_n_0\,
      Q => \^rxrate\(2),
      R => RST_CPLLRESET
    );
rate_rxsync_reg1_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => USER_RATE_RXSYNC
    );
ratedone_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF008000"
    )
        port map (
      I0 => rxratedone_reg_n_0,
      I1 => txratedone_reg_n_0,
      I2 => phystatus_reg_n_0,
      I3 => txratedone_i_2_n_0,
      I4 => ratedone_reg_n_0,
      O => ratedone_i_1_n_0
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ratedone_i_1_n_0,
      Q => ratedone_reg_n_0,
      R => '0'
    );
resetovrd_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => RATE_RESETOVRD_DONE,
      Q => resetovrd_done_reg1,
      R => RST_CPLLRESET
    );
resetovrd_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => resetovrd_done_reg1,
      Q => resetovrd_done_reg2,
      R => RST_CPLLRESET
    );
resetovrd_start_reg1_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(4),
      I4 => \^q\(2),
      O => USER_RESETOVRD_START
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => out1(1),
      Q => rst_idle_reg1,
      R => RST_CPLLRESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => RST_CPLLRESET
    );
rxratedone_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => txratedone_i_2_n_0,
      I2 => rxratedone_reg_n_0,
      O => rxratedone_i_1_n_0
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxratedone_i_1_n_0,
      Q => rxratedone_reg_n_0,
      R => '0'
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => RATE_RXRATEDONE,
      Q => rxratedone_reg1,
      R => RST_CPLLRESET
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => SYNC_RXSYNC_DONE,
      Q => rxsync_done_reg1,
      R => RST_CPLLRESET
    );
rxsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxsync_done_reg1,
      Q => rxsync_done_reg2,
      R => RST_CPLLRESET
    );
rxsync_start_reg1_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => SYNC_RXSYNC_START
    );
start_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in4_in,
      I1 => RST_DRP_START,
      O => DRP_START0
    );
\sysclksel[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF3EFF00000200"
    )
        port map (
      I0 => \sysclksel[0]_i_2_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \sysclksel[0]_i_3_n_0\,
      I5 => \^rxsysclksel\(0),
      O => \sysclksel[0]_i_1_n_0\
    );
\sysclksel[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      O => \sysclksel[0]_i_2_n_0\
    );
\sysclksel[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      O => \sysclksel[0]_i_3_n_0\
    );
\sysclksel[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FFFFFFF00000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^rxsysclksel\(1),
      O => \sysclksel[1]_i_1_n_0\
    );
\sysclksel_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \sysclksel[0]_i_1_n_0\,
      Q => \^rxsysclksel\(0),
      R => RST_CPLLRESET
    );
\sysclksel_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \sysclksel[1]_i_1_n_0\,
      Q => \^rxsysclksel\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(0)
    );
\txdata_wait_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(0),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(3),
      I4 => \txdata_wait_cnt_reg__0\(2),
      O => \p_0_in__0\(1)
    );
\txdata_wait_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AA0A0A0"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(2)
    );
\txdata_wait_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(3),
      O => \p_0_in__0\(3)
    );
\txdata_wait_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \txdata_wait_cnt[3]_i_2_n_0\
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \txdata_wait_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \txdata_wait_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \txdata_wait_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \txdata_wait_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
txpmareset_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5504FFFF55040000"
    )
        port map (
      I0 => \^q\(3),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => gen3_exit,
      I4 => txpmareset_i_2_n_0,
      I5 => \^gt_txpmareset0\,
      O => txpmareset_i_1_n_0
    );
txpmareset_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82000400"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => txpmareset_i_2_n_0
    );
txpmareset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => txpmareset_i_1_n_0,
      Q => \^gt_txpmareset0\,
      R => RST_CPLLRESET
    );
txratedone_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => txratedone_i_2_n_0,
      I2 => txratedone_reg_n_0,
      O => txratedone_i_1_n_0
    );
txratedone_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => RST_CPLLRESET,
      O => txratedone_i_2_n_0
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => txratedone_i_1_n_0,
      Q => txratedone_reg_n_0,
      R => '0'
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => RATE_TXRATEDONE,
      Q => txratedone_reg1,
      R => RST_CPLLRESET
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => RST_CPLLRESET
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => RATE_TXSYNC_DONE,
      Q => txsync_done_reg1,
      R => RST_CPLLRESET
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => RST_CPLLRESET
    );
txsync_start_reg1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAA"
    )
        port map (
      I0 => out1(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => SYNC_TXSYNC_START
    );
x16_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in5_in,
      I1 => RST_DRP_X16,
      O => DRP_X160
    );
x16x20_mode_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in6_in,
      I1 => RST_DRP_X16X20_MODE,
      O => DRP_X16X20_MODE0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_32 is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RESETOVRD_START : out STD_LOGIC;
    RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_TXSYNC_START : out STD_LOGIC;
    DRP_X16X20_MODE0106_out : out STD_LOGIC;
    DRP_X160104_out : out STD_LOGIC;
    DRP_START0102_out : out STD_LOGIC;
    \cplllock_reg1_reg[1]\ : out STD_LOGIC;
    rate_gen3 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[1]_0\ : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_RATE_DONE : out STD_LOGIC;
    USER_RATE_RXSYNC : out STD_LOGIC;
    SYNC_RXSYNC_START : out STD_LOGIC;
    RST_RATE_IDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    GT_TXPMARESET092_out : out STD_LOGIC;
    USER_PCLK_SEL : out STD_LOGIC;
    QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in93_in : out STD_LOGIC;
    QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in95_in : out STD_LOGIC;
    out1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RST_DRP_X16X20_MODE : in STD_LOGIC;
    RST_DRP_X16 : in STD_LOGIC;
    RST_DRP_START : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg_0 : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_CPLLLOCK : in STD_LOGIC;
    RATE_QPLLLOCK : in STD_LOGIC;
    RATE_DRP_DONE : in STD_LOGIC;
    RATE_MMCM_LOCK : in STD_LOGIC;
    RATE_PHYSTATUS : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    USER_RXRESETDONE : in STD_LOGIC;
    RATE_TXRATEDONE : in STD_LOGIC;
    RATE_RXRATEDONE : in STD_LOGIC;
    RATE_RESETOVRD_DONE : in STD_LOGIC;
    RATE_TXSYNC_DONE : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    p_0_in7_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_32 : entity is "PCIeGen1x8If64_pipe_rate";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_32;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_32 is
  signal \^gt_txpmareset092_out\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^user_pclk_sel\ : STD_LOGIC;
  signal cplllock_reg1 : STD_LOGIC;
  signal cplllock_reg2 : STD_LOGIC;
  signal \cpllpd_i_1__0_n_0\ : STD_LOGIC;
  signal \cpllreset_i_1__1_n_0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC;
  signal drp_done_reg2 : STD_LOGIC;
  signal \drp_start_i_1__0_n_0\ : STD_LOGIC;
  signal \drp_x16_i_1__0_n_0\ : STD_LOGIC;
  signal \drp_x16x20_mode_i_1__0_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal \fsm[0]_i_10__0_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_11__0_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_12__0_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_3__1_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_7__0_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_8__0_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_9__0_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_4__0_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_5__0_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_6__0_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_7__0_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_8__0_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_9__0_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_4__0_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_5__0_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_5__0_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_8__0_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_9__0_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \fsm_reg[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_3__0_n_0\ : STD_LOGIC;
  signal gen3_exit : STD_LOGIC;
  signal \gen3_exit_i_1__0_n_0\ : STD_LOGIC;
  signal \gen3_exit_i_2__0_n_0\ : STD_LOGIC;
  signal \gen3_i_1__0_n_0\ : STD_LOGIC;
  signal \gen3_i_2__0_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal p_0_in101_in : STD_LOGIC;
  signal p_0_in103_in : STD_LOGIC;
  signal p_0_in105_in : STD_LOGIC;
  signal \^p_0_in93_in\ : STD_LOGIC;
  signal \^p_0_in95_in\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pclk_sel_i_1__1_n_0\ : STD_LOGIC;
  signal \pclk_sel_i_2__0_n_0\ : STD_LOGIC;
  signal \phystatus_i_1__0_n_0\ : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  signal phystatus_reg2 : STD_LOGIC;
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal pll_lock : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  signal qplllock_reg2 : STD_LOGIC;
  signal qpllpd : STD_LOGIC;
  signal \qpllpd_i_1__1_n_0\ : STD_LOGIC;
  signal qpllreset : STD_LOGIC;
  signal \qpllreset_i_1__1_n_0\ : STD_LOGIC;
  signal \^rate_gen3\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rate_out[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rate_out[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \ratedone_i_1__0_n_0\ : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal resetovrd_done_reg1 : STD_LOGIC;
  signal resetovrd_done_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  signal \rxratedone_i_1__0_n_0\ : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  signal rxratedone_reg2 : STD_LOGIC;
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxsync_done_reg1 : STD_LOGIC;
  signal rxsync_done_reg2 : STD_LOGIC;
  signal \sysclksel[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \sysclksel[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt_reg__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txpmareset_i_1__0_n_0\ : STD_LOGIC;
  signal \txpmareset_i_2__0_n_0\ : STD_LOGIC;
  signal \txratedone_i_1__0_n_0\ : STD_LOGIC;
  signal \txratedone_i_2__0_n_0\ : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  signal txratedone_reg2 : STD_LOGIC;
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC;
  signal txsync_done_reg2 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of cplllock_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of cplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of cplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of cplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cpllpd_i_2__0\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \cpllreset_i_2__0\ : label is "soft_lutpair60";
  attribute ASYNC_REG of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \drp_start_i_1__0\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \drp_x16_i_1__0\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__0\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \fsm[0]_i_9__0\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \fsm[3]_i_5__0\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \gen3_i_2__0\ : label is "soft_lutpair63";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \pclk_sel_i_2__0\ : label is "soft_lutpair60";
  attribute ASYNC_REG of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rate_done_reg1_i_1__0\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \rate_idle_reg1[1]_i_1\ : label is "soft_lutpair63";
  attribute ASYNC_REG of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SOFT_HLUTNM of \rate_out[1]_i_1__0\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \rate_out[2]_i_1__0\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \rate_rxsync_reg1_i_1__0\ : label is "soft_lutpair55";
  attribute ASYNC_REG of resetovrd_done_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_done_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_start_reg1_i_1__0\ : label is "soft_lutpair54";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rxsync_start_reg1_i_1__0\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1__0\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1__0\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1__0\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1__0\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2__0\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \txpmareset_i_2__0\ : label is "soft_lutpair62";
  attribute ASYNC_REG of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
begin
  GT_TXPMARESET092_out <= \^gt_txpmareset092_out\;
  Q(4 downto 0) <= \^q\(4 downto 0);
  QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0);
  QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0);
  RXRATE(2 downto 0) <= \^rxrate\(2 downto 0);
  RXSYSCLKSEL(1 downto 0) <= \^rxsysclksel\(1 downto 0);
  USER_PCLK_SEL <= \^user_pclk_sel\;
  p_0_in93_in <= \^p_0_in93_in\;
  p_0_in95_in <= \^p_0_in95_in\;
  rate_gen3(0) <= \^rate_gen3\(0);
cplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_CPLLLOCK,
      Q => cplllock_reg1,
      R => RST_CPLLRESET
    );
cplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => cplllock_reg1,
      Q => cplllock_reg2,
      R => RST_CPLLRESET
    );
\cpllpd_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^p_0_in95_in\,
      O => \cpllpd_i_1__0_n_0\
    );
\cpllpd_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000084"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(0),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => qpllpd
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllpd_i_1__0_n_0\,
      Q => \^p_0_in95_in\,
      R => RST_CPLLRESET
    );
\cpllreset_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^p_0_in93_in\,
      O => \cpllreset_i_1__1_n_0\
    );
\cpllreset_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"81000002"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => qpllreset
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllreset_i_1__1_n_0\,
      Q => \^p_0_in93_in\,
      R => RST_CPLLRESET
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_DRP_DONE,
      Q => drp_done_reg1,
      R => RST_CPLLRESET
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => RST_CPLLRESET
    );
\drp_start_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08200108"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => \^q\(1),
      O => \drp_start_i_1__0_n_0\
    );
drp_start_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_start_i_1__0_n_0\,
      Q => p_0_in101_in,
      R => RST_CPLLRESET
    );
\drp_x16_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20020006"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(4),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(0),
      O => \drp_x16_i_1__0_n_0\
    );
drp_x16_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16_i_1__0_n_0\,
      Q => p_0_in103_in,
      R => RST_CPLLRESET
    );
\drp_x16x20_mode_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20001584"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => \drp_x16x20_mode_i_1__0_n_0\
    );
drp_x16x20_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16x20_mode_i_1__0_n_0\,
      Q => p_0_in105_in,
      R => RST_CPLLRESET
    );
\fsm[0]_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \txdata_wait_cnt_reg__0__0\(3),
      I1 => \txdata_wait_cnt_reg__0__0\(2),
      I2 => \txdata_wait_cnt_reg__0__0\(0),
      I3 => \txdata_wait_cnt_reg__0__0\(1),
      O => \fsm[0]_i_10__0_n_0\
    );
\fsm[0]_i_11__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F404"
    )
        port map (
      I0 => rxpmaresetdone_reg2,
      I1 => mmcm_lock_reg2,
      I2 => \^q\(0),
      I3 => drp_done_reg2,
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \fsm[0]_i_11__0_n_0\
    );
\fsm[0]_i_12__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F737F4343404C"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => rxpmaresetdone_reg2,
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[0]_i_12__0_n_0\
    );
\fsm[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBB88888BBB8BBB8"
    )
        port map (
      I0 => \fsm_reg[0]_i_2__0_n_0\,
      I1 => \^q\(4),
      I2 => \fsm[0]_i_3__1_n_0\,
      I3 => \^q\(3),
      I4 => \fsm[0]_i_4__0_n_0\,
      I5 => \fsm[0]_i_5__0_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0344FF440344FF77"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => pll_lock,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \fsm[3]_i_9__0_n_0\,
      O => \fsm[0]_i_3__1_n_0\
    );
\fsm[0]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0000000F800F000"
    )
        port map (
      I0 => pll_lock,
      I1 => rst_idle_reg2,
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => drp_done_reg2,
      I5 => \^q\(0),
      O => \fsm[0]_i_4__0_n_0\
    );
\fsm[0]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCC8C0C8"
    )
        port map (
      I0 => \fsm[0]_i_8__0_n_0\,
      I1 => \^q\(3),
      I2 => \fsm[0]_i_9__0_n_0\,
      I3 => \^q\(0),
      I4 => \fsm[0]_i_10__0_n_0\,
      I5 => \fsm[0]_i_11__0_n_0\,
      O => \fsm[0]_i_5__0_n_0\
    );
\fsm[0]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0040"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \fsm[0]_i_12__0_n_0\,
      O => \fsm[0]_i_6__0_n_0\
    );
\fsm[0]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03880333"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[0]_i_7__0_n_0\
    );
\fsm[0]_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77770777"
    )
        port map (
      I0 => p_0_in7_in,
      I1 => p_1_in8_in,
      I2 => rxresetdone_reg2,
      I3 => txresetdone_reg2,
      I4 => phystatus_reg2,
      O => \fsm[0]_i_8__0_n_0\
    );
\fsm[0]_i_9__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      O => \fsm[0]_i_9__0_n_0\
    );
\fsm[1]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BBFC00"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_8__0_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_4__0_n_0\
    );
\fsm[1]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC88300000BB3000"
    )
        port map (
      I0 => \fsm[0]_i_10__0_n_0\,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_9__0_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[1]_i_5__0_n_0\
    );
\fsm[1]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70F040F0"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => drp_done_reg2,
      O => \fsm[1]_i_6__0_n_0\
    );
\fsm[1]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03777700"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_7__0_n_0\
    );
\fsm[1]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"53F5FFFFFFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => qplllock_reg2,
      I2 => rate_in_reg2(0),
      I3 => rate_in_reg2(1),
      I4 => rst_idle_reg2,
      I5 => \^q\(0),
      O => \fsm[1]_i_8__0_n_0\
    );
\fsm[1]_i_9__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF4575FFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      I3 => qplllock_reg2,
      I4 => rst_idle_reg2,
      I5 => drp_done_reg2,
      O => \fsm[1]_i_9__0_n_0\
    );
\fsm[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fsm[2]_i_2__0_n_0\,
      I1 => \fsm[2]_i_3__0_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[2]_i_4__0_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[2]_i_5__0_n_0\,
      O => fsm(2)
    );
\fsm[2]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3C0C4040"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_done_reg2,
      I4 => \^q\(0),
      O => \fsm[2]_i_2__0_n_0\
    );
\fsm[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13CCD3CC1FCCDFCC"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => resetovrd_done_reg2,
      I5 => fsm1,
      O => \fsm[2]_i_3__0_n_0\
    );
\fsm[2]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BC0C"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \fsm[2]_i_4__0_n_0\
    );
\fsm[2]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4A4A4A4AAAAFAAAA"
    )
        port map (
      I0 => \^q\(2),
      I1 => pll_lock,
      I2 => \^q\(1),
      I3 => \fsm[3]_i_9__0_n_0\,
      I4 => \fsm[3]_i_8__0_n_0\,
      I5 => \^q\(0),
      O => \fsm[2]_i_5__0_n_0\
    );
\fsm[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFE0EFEFEFE0E0E0"
    )
        port map (
      I0 => \fsm[3]_i_2__0_n_0\,
      I1 => \fsm[3]_i_3__0_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[3]_i_4__0_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[3]_i_5__0_n_0\,
      O => fsm(3)
    );
\fsm[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22AA2A22"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => rxsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[3]_i_2__0_n_0\
    );
\fsm[3]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3020002000000000"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => resetovrd_done_reg2,
      I5 => \^q\(0),
      O => \fsm[3]_i_3__0_n_0\
    );
\fsm[3]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F545F555FFFFFFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rst_idle_reg2,
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => pll_lock,
      I5 => \^q\(1),
      O => \fsm[3]_i_4__0_n_0\
    );
\fsm[3]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80808180"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \fsm[3]_i_8__0_n_0\,
      I4 => \fsm[3]_i_9__0_n_0\,
      O => \fsm[3]_i_5__0_n_0\
    );
\fsm[3]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF8F8FFF8"
    )
        port map (
      I0 => p_1_in8_in,
      I1 => p_0_in7_in,
      I2 => ratedone_reg_n_0,
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg2(0),
      I5 => gen3_exit,
      O => fsm1
    );
\fsm[3]_i_7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => cplllock_reg2,
      O => pll_lock
    );
\fsm[3]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg1(1),
      O => \fsm[3]_i_8__0_n_0\
    );
\fsm[3]_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rate_in_reg1(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(1),
      I3 => rate_in_reg2(1),
      O => \fsm[3]_i_9__0_n_0\
    );
\fsm[4]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08880000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \fsm[4]_i_2__0_n_0\
    );
\fsm[4]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5F75FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rxsync_done_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \fsm[4]_i_3__0_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\fsm_reg[0]_i_2__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[0]_i_6__0_n_0\,
      I1 => \fsm[0]_i_7__0_n_0\,
      O => \fsm_reg[0]_i_2__0_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      S => RST_CPLLRESET
    );
\fsm_reg[1]_i_1__0\: unisim.vcomponents.MUXF8
     port map (
      I0 => \fsm_reg[1]_i_2__0_n_0\,
      I1 => \fsm_reg[1]_i_3__0_n_0\,
      O => fsm(1),
      S => \^q\(4)
    );
\fsm_reg[1]_i_2__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_4__0_n_0\,
      I1 => \fsm[1]_i_5__0_n_0\,
      O => \fsm_reg[1]_i_2__0_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]_i_3__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_6__0_n_0\,
      I1 => \fsm[1]_i_7__0_n_0\,
      O => \fsm_reg[1]_i_3__0_n_0\,
      S => \^q\(3)
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\fsm_reg[4]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[4]_i_2__0_n_0\,
      I1 => \fsm[4]_i_3__0_n_0\,
      O => fsm(4),
      S => \^q\(4)
    );
\gen3_exit_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_exit_i_2__0_n_0\,
      I4 => gen3_exit,
      O => \gen3_exit_i_1__0_n_0\
    );
\gen3_exit_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000000000001"
    )
        port map (
      I0 => \fsm[3]_i_9__0_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => \gen3_exit_i_2__0_n_0\
    );
gen3_exit_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_exit_i_1__0_n_0\,
      Q => gen3_exit,
      R => RST_CPLLRESET
    );
\gen3_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_i_2__0_n_0\,
      I4 => \^rate_gen3\(0),
      O => \gen3_i_1__0_n_0\
    );
\gen3_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000008"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(1),
      O => \gen3_i_2__0_n_0\
    );
gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_i_1__0_n_0\,
      Q => \^rate_gen3\(0),
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_6__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[1]_0\
    );
\gtx_channel.gtxe2_channel_i_i_7__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[1]\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
\pclk_sel_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06FF0600"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \pclk_sel_i_2__0_n_0\,
      I4 => \^user_pclk_sel\,
      O => \pclk_sel_i_1__1_n_0\
    );
\pclk_sel_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80040800"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \pclk_sel_i_2__0_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pclk_sel_i_1__1_n_0\,
      Q => \^user_pclk_sel\,
      R => RST_CPLLRESET
    );
\phystatus_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \txratedone_i_2__0_n_0\,
      I2 => phystatus_reg_n_0,
      O => \phystatus_i_1__0_n_0\
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \phystatus_i_1__0_n_0\,
      Q => phystatus_reg_n_0,
      R => '0'
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_PHYSTATUS,
      Q => phystatus_reg1,
      R => RST_CPLLRESET
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => RST_CPLLRESET
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_QPLLLOCK,
      Q => qplllock_reg1,
      R => RST_CPLLRESET
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => RST_CPLLRESET
    );
\qpllpd_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^qrst_qpllpd_in\(0),
      O => \qpllpd_i_1__1_n_0\
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllpd_i_1__1_n_0\,
      Q => \^qrst_qpllpd_in\(0),
      R => RST_CPLLRESET
    );
\qpllreset_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^qrst_qpllreset_in\(0),
      O => \qpllreset_i_1__1_n_0\
    );
qpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllreset_i_1__1_n_0\,
      Q => \^qrst_qpllreset_in\(0),
      R => RST_CPLLRESET
    );
\rate_done_reg1_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => USER_RATE_DONE
    );
\rate_idle_reg1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => RST_RATE_IDLE(0)
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_in_reg1(0),
      R => RST_CPLLRESET
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => RST_CPLLRESET
    );
\rate_out[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      I2 => \^q\(1),
      I3 => \rate_out[2]_i_2__0_n_0\,
      I4 => \^rxrate\(0),
      O => \rate_out[0]_i_1__0_n_0\
    );
\rate_out[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__0_n_0\,
      I1 => \^rxrate\(1),
      O => \rate_out[1]_i_1__0_n_0\
    );
\rate_out[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__0_n_0\,
      I1 => \^rxrate\(2),
      O => \rate_out[2]_i_1__0_n_0\
    );
\rate_out[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000002080000220"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \rate_out[2]_i_3__0_n_0\,
      O => \rate_out[2]_i_2__0_n_0\
    );
\rate_out[2]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => gen3_exit,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      O => \rate_out[2]_i_3__0_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[0]_i_1__0_n_0\,
      Q => \^rxrate\(0),
      R => RST_CPLLRESET
    );
\rate_out_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[1]_i_1__0_n_0\,
      Q => \^rxrate\(1),
      R => RST_CPLLRESET
    );
\rate_out_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[2]_i_1__0_n_0\,
      Q => \^rxrate\(2),
      R => RST_CPLLRESET
    );
\rate_rxsync_reg1_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => USER_RATE_RXSYNC
    );
\ratedone_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF008000"
    )
        port map (
      I0 => rxratedone_reg_n_0,
      I1 => txratedone_reg_n_0,
      I2 => phystatus_reg_n_0,
      I3 => \txratedone_i_2__0_n_0\,
      I4 => ratedone_reg_n_0,
      O => \ratedone_i_1__0_n_0\
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \ratedone_i_1__0_n_0\,
      Q => ratedone_reg_n_0,
      R => '0'
    );
resetovrd_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RESETOVRD_DONE,
      Q => resetovrd_done_reg1,
      R => RST_CPLLRESET
    );
resetovrd_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => resetovrd_done_reg1,
      Q => resetovrd_done_reg2,
      R => RST_CPLLRESET
    );
\resetovrd_start_reg1_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(4),
      I4 => \^q\(2),
      O => USER_RESETOVRD_START
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => out1(1),
      Q => rst_idle_reg1,
      R => RST_CPLLRESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => RST_CPLLRESET
    );
\rxratedone_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \txratedone_i_2__0_n_0\,
      I2 => rxratedone_reg_n_0,
      O => \rxratedone_i_1__0_n_0\
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rxratedone_i_1__0_n_0\,
      Q => rxratedone_reg_n_0,
      R => '0'
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RXRATEDONE,
      Q => rxratedone_reg1,
      R => RST_CPLLRESET
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => SYNC_RXSYNC_DONE,
      Q => rxsync_done_reg1,
      R => RST_CPLLRESET
    );
rxsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxsync_done_reg1,
      Q => rxsync_done_reg2,
      R => RST_CPLLRESET
    );
\rxsync_start_reg1_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => SYNC_RXSYNC_START
    );
\start_reg1_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in101_in,
      I1 => RST_DRP_START,
      O => DRP_START0102_out
    );
\sysclksel[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF3EFF00000200"
    )
        port map (
      I0 => \sysclksel[0]_i_2__0_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \sysclksel[0]_i_3__0_n_0\,
      I5 => \^rxsysclksel\(0),
      O => \sysclksel[0]_i_1__0_n_0\
    );
\sysclksel[0]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      O => \sysclksel[0]_i_2__0_n_0\
    );
\sysclksel[0]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      O => \sysclksel[0]_i_3__0_n_0\
    );
\sysclksel[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FFFFFFF00000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^rxsysclksel\(1),
      O => \sysclksel[1]_i_1__0_n_0\
    );
\sysclksel_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[0]_i_1__0_n_0\,
      Q => \^rxsysclksel\(0),
      R => RST_CPLLRESET
    );
\sysclksel_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[1]_i_1__0_n_0\,
      Q => \^rxsysclksel\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__0_n_0\,
      I1 => \txdata_wait_cnt_reg__0__0\(3),
      I2 => \txdata_wait_cnt_reg__0__0\(2),
      I3 => \txdata_wait_cnt_reg__0__0\(0),
      I4 => \txdata_wait_cnt_reg__0__0\(1),
      O => \p_0_in__0\(0)
    );
\txdata_wait_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__0_n_0\,
      I1 => \txdata_wait_cnt_reg__0__0\(0),
      I2 => \txdata_wait_cnt_reg__0__0\(1),
      I3 => \txdata_wait_cnt_reg__0__0\(3),
      I4 => \txdata_wait_cnt_reg__0__0\(2),
      O => \p_0_in__0\(1)
    );
\txdata_wait_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AA0A0A0"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__0_n_0\,
      I1 => \txdata_wait_cnt_reg__0__0\(3),
      I2 => \txdata_wait_cnt_reg__0__0\(2),
      I3 => \txdata_wait_cnt_reg__0__0\(0),
      I4 => \txdata_wait_cnt_reg__0__0\(1),
      O => \p_0_in__0\(2)
    );
\txdata_wait_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__0_n_0\,
      I1 => \txdata_wait_cnt_reg__0__0\(2),
      I2 => \txdata_wait_cnt_reg__0__0\(1),
      I3 => \txdata_wait_cnt_reg__0__0\(0),
      I4 => \txdata_wait_cnt_reg__0__0\(3),
      O => \p_0_in__0\(3)
    );
\txdata_wait_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \txdata_wait_cnt[3]_i_2__0_n_0\
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \txdata_wait_cnt_reg__0__0\(0),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \txdata_wait_cnt_reg__0__0\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \txdata_wait_cnt_reg__0__0\(2),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \txdata_wait_cnt_reg__0__0\(3),
      R => RST_CPLLRESET
    );
\txpmareset_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5504FFFF55040000"
    )
        port map (
      I0 => \^q\(3),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => gen3_exit,
      I4 => \txpmareset_i_2__0_n_0\,
      I5 => \^gt_txpmareset092_out\,
      O => \txpmareset_i_1__0_n_0\
    );
\txpmareset_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82000400"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \txpmareset_i_2__0_n_0\
    );
txpmareset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txpmareset_i_1__0_n_0\,
      Q => \^gt_txpmareset092_out\,
      R => RST_CPLLRESET
    );
\txratedone_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \txratedone_i_2__0_n_0\,
      I2 => txratedone_reg_n_0,
      O => \txratedone_i_1__0_n_0\
    );
\txratedone_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => RST_CPLLRESET,
      O => \txratedone_i_2__0_n_0\
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txratedone_i_1__0_n_0\,
      Q => txratedone_reg_n_0,
      R => '0'
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXRATEDONE,
      Q => txratedone_reg1,
      R => RST_CPLLRESET
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => RST_CPLLRESET
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXSYNC_DONE,
      Q => txsync_done_reg1,
      R => RST_CPLLRESET
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => RST_CPLLRESET
    );
\txsync_start_reg1_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAA"
    )
        port map (
      I0 => out1(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => SYNC_TXSYNC_START
    );
\x16_reg1_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in103_in,
      I1 => RST_DRP_X16,
      O => DRP_X160104_out
    );
\x16x20_mode_reg1_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in105_in,
      I1 => RST_DRP_X16X20_MODE,
      O => DRP_X16X20_MODE0106_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_38 is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RESETOVRD_START : out STD_LOGIC;
    RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_TXSYNC_START : out STD_LOGIC;
    DRP_X16X20_MODE0114_out : out STD_LOGIC;
    DRP_X160112_out : out STD_LOGIC;
    DRP_START0110_out : out STD_LOGIC;
    \cplllock_reg1_reg[2]\ : out STD_LOGIC;
    rate_gen3 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[2]_0\ : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_RATE_DONE : out STD_LOGIC;
    USER_RATE_RXSYNC : out STD_LOGIC;
    SYNC_RXSYNC_START : out STD_LOGIC;
    RST_RATE_IDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    GT_TXPMARESET0120_out : out STD_LOGIC;
    USER_PCLK_SEL : out STD_LOGIC;
    QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in121_in : out STD_LOGIC;
    QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in123_in : out STD_LOGIC;
    out1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RST_DRP_X16X20_MODE : in STD_LOGIC;
    RST_DRP_X16 : in STD_LOGIC;
    RST_DRP_START : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg_0 : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_CPLLLOCK : in STD_LOGIC;
    RATE_QPLLLOCK : in STD_LOGIC;
    RATE_DRP_DONE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    RATE_PHYSTATUS : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    USER_RXRESETDONE : in STD_LOGIC;
    RATE_TXRATEDONE : in STD_LOGIC;
    RATE_RXRATEDONE : in STD_LOGIC;
    RATE_RESETOVRD_DONE : in STD_LOGIC;
    RATE_TXSYNC_DONE : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    p_0_in7_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_38 : entity is "PCIeGen1x8If64_pipe_rate";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_38;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_38 is
  signal \^gt_txpmareset0120_out\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^user_pclk_sel\ : STD_LOGIC;
  signal cplllock_reg1 : STD_LOGIC;
  signal cplllock_reg2 : STD_LOGIC;
  signal \cpllpd_i_1__1_n_0\ : STD_LOGIC;
  signal \cpllreset_i_1__2_n_0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC;
  signal drp_done_reg2 : STD_LOGIC;
  signal \drp_start_i_1__1_n_0\ : STD_LOGIC;
  signal \drp_x16_i_1__1_n_0\ : STD_LOGIC;
  signal \drp_x16x20_mode_i_1__1_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal \fsm[0]_i_10__1_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_11__1_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_12__1_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_3__3_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_4__1_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_5__1_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_6__1_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_7__1_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_8__1_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_9__1_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_4__1_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_5__1_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_6__1_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_7__1_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_8__1_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_9__1_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_3__1_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_4__1_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_5__1_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_3__1_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_4__1_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_5__1_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_8__1_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_9__1_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_3__1_n_0\ : STD_LOGIC;
  signal \fsm_reg[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_3__1_n_0\ : STD_LOGIC;
  signal gen3_exit : STD_LOGIC;
  signal \gen3_exit_i_1__1_n_0\ : STD_LOGIC;
  signal \gen3_exit_i_2__1_n_0\ : STD_LOGIC;
  signal \gen3_i_1__1_n_0\ : STD_LOGIC;
  signal \gen3_i_2__1_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal p_0_in109_in : STD_LOGIC;
  signal p_0_in111_in : STD_LOGIC;
  signal p_0_in113_in : STD_LOGIC;
  signal \^p_0_in121_in\ : STD_LOGIC;
  signal \^p_0_in123_in\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pclk_sel_i_1__2_n_0\ : STD_LOGIC;
  signal \pclk_sel_i_2__1_n_0\ : STD_LOGIC;
  signal \phystatus_i_1__1_n_0\ : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  signal phystatus_reg2 : STD_LOGIC;
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal pll_lock : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  signal qplllock_reg2 : STD_LOGIC;
  signal qpllpd : STD_LOGIC;
  signal \qpllpd_i_1__2_n_0\ : STD_LOGIC;
  signal qpllreset : STD_LOGIC;
  signal \qpllreset_i_1__2_n_0\ : STD_LOGIC;
  signal \^rate_gen3\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rate_out[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \rate_out[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_3__1_n_0\ : STD_LOGIC;
  signal \ratedone_i_1__1_n_0\ : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal resetovrd_done_reg1 : STD_LOGIC;
  signal resetovrd_done_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  signal \rxratedone_i_1__1_n_0\ : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  signal rxratedone_reg2 : STD_LOGIC;
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxsync_done_reg1 : STD_LOGIC;
  signal rxsync_done_reg2 : STD_LOGIC;
  signal \sysclksel[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_3__1_n_0\ : STD_LOGIC;
  signal \sysclksel[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txpmareset_i_1__1_n_0\ : STD_LOGIC;
  signal \txpmareset_i_2__1_n_0\ : STD_LOGIC;
  signal \txratedone_i_1__1_n_0\ : STD_LOGIC;
  signal \txratedone_i_2__1_n_0\ : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  signal txratedone_reg2 : STD_LOGIC;
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC;
  signal txsync_done_reg2 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of cplllock_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of cplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of cplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of cplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cpllpd_i_2__1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \cpllreset_i_2__1\ : label is "soft_lutpair82";
  attribute ASYNC_REG of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \drp_start_i_1__1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \drp_x16_i_1__1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__1\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \fsm[0]_i_9__1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \fsm[3]_i_5__1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \gen3_i_2__1\ : label is "soft_lutpair85";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \pclk_sel_i_2__1\ : label is "soft_lutpair82";
  attribute ASYNC_REG of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rate_done_reg1_i_1__1\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \rate_idle_reg1[2]_i_1\ : label is "soft_lutpair85";
  attribute ASYNC_REG of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SOFT_HLUTNM of \rate_out[1]_i_1__1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \rate_out[2]_i_1__1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \rate_rxsync_reg1_i_1__1\ : label is "soft_lutpair77";
  attribute ASYNC_REG of resetovrd_done_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_done_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_start_reg1_i_1__1\ : label is "soft_lutpair76";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rxsync_start_reg1_i_1__1\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1__1\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1__1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1__1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1__1\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2__1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \txpmareset_i_2__1\ : label is "soft_lutpair84";
  attribute ASYNC_REG of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
begin
  GT_TXPMARESET0120_out <= \^gt_txpmareset0120_out\;
  Q(4 downto 0) <= \^q\(4 downto 0);
  QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0);
  QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0);
  RXRATE(2 downto 0) <= \^rxrate\(2 downto 0);
  RXSYSCLKSEL(1 downto 0) <= \^rxsysclksel\(1 downto 0);
  USER_PCLK_SEL <= \^user_pclk_sel\;
  p_0_in121_in <= \^p_0_in121_in\;
  p_0_in123_in <= \^p_0_in123_in\;
  rate_gen3(0) <= \^rate_gen3\(0);
cplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_CPLLLOCK,
      Q => cplllock_reg1,
      R => RST_CPLLRESET
    );
cplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => cplllock_reg1,
      Q => cplllock_reg2,
      R => RST_CPLLRESET
    );
\cpllpd_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^p_0_in123_in\,
      O => \cpllpd_i_1__1_n_0\
    );
\cpllpd_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000084"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(0),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => qpllpd
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllpd_i_1__1_n_0\,
      Q => \^p_0_in123_in\,
      R => RST_CPLLRESET
    );
\cpllreset_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^p_0_in121_in\,
      O => \cpllreset_i_1__2_n_0\
    );
\cpllreset_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"81000002"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => qpllreset
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllreset_i_1__2_n_0\,
      Q => \^p_0_in121_in\,
      R => RST_CPLLRESET
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_DRP_DONE,
      Q => drp_done_reg1,
      R => RST_CPLLRESET
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => RST_CPLLRESET
    );
\drp_start_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08200108"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => \^q\(1),
      O => \drp_start_i_1__1_n_0\
    );
drp_start_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_start_i_1__1_n_0\,
      Q => p_0_in109_in,
      R => RST_CPLLRESET
    );
\drp_x16_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20020006"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(4),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(0),
      O => \drp_x16_i_1__1_n_0\
    );
drp_x16_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16_i_1__1_n_0\,
      Q => p_0_in111_in,
      R => RST_CPLLRESET
    );
\drp_x16x20_mode_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20001584"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => \drp_x16x20_mode_i_1__1_n_0\
    );
drp_x16x20_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16x20_mode_i_1__1_n_0\,
      Q => p_0_in113_in,
      R => RST_CPLLRESET
    );
\fsm[0]_i_10__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \txdata_wait_cnt_reg__0\(3),
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(0),
      I3 => \txdata_wait_cnt_reg__0\(1),
      O => \fsm[0]_i_10__1_n_0\
    );
\fsm[0]_i_11__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F404"
    )
        port map (
      I0 => rxpmaresetdone_reg2,
      I1 => mmcm_lock_reg2,
      I2 => \^q\(0),
      I3 => drp_done_reg2,
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \fsm[0]_i_11__1_n_0\
    );
\fsm[0]_i_12__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F737F4343404C"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => rxpmaresetdone_reg2,
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[0]_i_12__1_n_0\
    );
\fsm[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBB88888BBB8BBB8"
    )
        port map (
      I0 => \fsm_reg[0]_i_2__1_n_0\,
      I1 => \^q\(4),
      I2 => \fsm[0]_i_3__3_n_0\,
      I3 => \^q\(3),
      I4 => \fsm[0]_i_4__1_n_0\,
      I5 => \fsm[0]_i_5__1_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0344FF440344FF77"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => pll_lock,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \fsm[3]_i_9__1_n_0\,
      O => \fsm[0]_i_3__3_n_0\
    );
\fsm[0]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0000000F800F000"
    )
        port map (
      I0 => pll_lock,
      I1 => rst_idle_reg2,
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => drp_done_reg2,
      I5 => \^q\(0),
      O => \fsm[0]_i_4__1_n_0\
    );
\fsm[0]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCC8C0C8"
    )
        port map (
      I0 => \fsm[0]_i_8__1_n_0\,
      I1 => \^q\(3),
      I2 => \fsm[0]_i_9__1_n_0\,
      I3 => \^q\(0),
      I4 => \fsm[0]_i_10__1_n_0\,
      I5 => \fsm[0]_i_11__1_n_0\,
      O => \fsm[0]_i_5__1_n_0\
    );
\fsm[0]_i_6__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0040"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \fsm[0]_i_12__1_n_0\,
      O => \fsm[0]_i_6__1_n_0\
    );
\fsm[0]_i_7__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03880333"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[0]_i_7__1_n_0\
    );
\fsm[0]_i_8__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77770777"
    )
        port map (
      I0 => p_0_in7_in,
      I1 => p_1_in8_in,
      I2 => rxresetdone_reg2,
      I3 => txresetdone_reg2,
      I4 => phystatus_reg2,
      O => \fsm[0]_i_8__1_n_0\
    );
\fsm[0]_i_9__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      O => \fsm[0]_i_9__1_n_0\
    );
\fsm[1]_i_4__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BBFC00"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_8__1_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_4__1_n_0\
    );
\fsm[1]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC88300000BB3000"
    )
        port map (
      I0 => \fsm[0]_i_10__1_n_0\,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_9__1_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[1]_i_5__1_n_0\
    );
\fsm[1]_i_6__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70F040F0"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => drp_done_reg2,
      O => \fsm[1]_i_6__1_n_0\
    );
\fsm[1]_i_7__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03777700"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_7__1_n_0\
    );
\fsm[1]_i_8__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"53F5FFFFFFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => qplllock_reg2,
      I2 => rate_in_reg2(0),
      I3 => rate_in_reg2(1),
      I4 => rst_idle_reg2,
      I5 => \^q\(0),
      O => \fsm[1]_i_8__1_n_0\
    );
\fsm[1]_i_9__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF4575FFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      I3 => qplllock_reg2,
      I4 => rst_idle_reg2,
      I5 => drp_done_reg2,
      O => \fsm[1]_i_9__1_n_0\
    );
\fsm[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fsm[2]_i_2__1_n_0\,
      I1 => \fsm[2]_i_3__1_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[2]_i_4__1_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[2]_i_5__1_n_0\,
      O => fsm(2)
    );
\fsm[2]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3C0C4040"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_done_reg2,
      I4 => \^q\(0),
      O => \fsm[2]_i_2__1_n_0\
    );
\fsm[2]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13CCD3CC1FCCDFCC"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => resetovrd_done_reg2,
      I5 => fsm1,
      O => \fsm[2]_i_3__1_n_0\
    );
\fsm[2]_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BC0C"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \fsm[2]_i_4__1_n_0\
    );
\fsm[2]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4A4A4A4AAAAFAAAA"
    )
        port map (
      I0 => \^q\(2),
      I1 => pll_lock,
      I2 => \^q\(1),
      I3 => \fsm[3]_i_9__1_n_0\,
      I4 => \fsm[3]_i_8__1_n_0\,
      I5 => \^q\(0),
      O => \fsm[2]_i_5__1_n_0\
    );
\fsm[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFE0EFEFEFE0E0E0"
    )
        port map (
      I0 => \fsm[3]_i_2__1_n_0\,
      I1 => \fsm[3]_i_3__1_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[3]_i_4__1_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[3]_i_5__1_n_0\,
      O => fsm(3)
    );
\fsm[3]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22AA2A22"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => rxsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[3]_i_2__1_n_0\
    );
\fsm[3]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3020002000000000"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => resetovrd_done_reg2,
      I5 => \^q\(0),
      O => \fsm[3]_i_3__1_n_0\
    );
\fsm[3]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F545F555FFFFFFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rst_idle_reg2,
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => pll_lock,
      I5 => \^q\(1),
      O => \fsm[3]_i_4__1_n_0\
    );
\fsm[3]_i_5__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80808180"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \fsm[3]_i_8__1_n_0\,
      I4 => \fsm[3]_i_9__1_n_0\,
      O => \fsm[3]_i_5__1_n_0\
    );
\fsm[3]_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF8F8FFF8"
    )
        port map (
      I0 => p_1_in8_in,
      I1 => p_0_in7_in,
      I2 => ratedone_reg_n_0,
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg2(0),
      I5 => gen3_exit,
      O => fsm1
    );
\fsm[3]_i_7__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => cplllock_reg2,
      O => pll_lock
    );
\fsm[3]_i_8__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg1(1),
      O => \fsm[3]_i_8__1_n_0\
    );
\fsm[3]_i_9__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rate_in_reg1(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(1),
      I3 => rate_in_reg2(1),
      O => \fsm[3]_i_9__1_n_0\
    );
\fsm[4]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08880000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \fsm[4]_i_2__1_n_0\
    );
\fsm[4]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5F75FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rxsync_done_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \fsm[4]_i_3__1_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\fsm_reg[0]_i_2__1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[0]_i_6__1_n_0\,
      I1 => \fsm[0]_i_7__1_n_0\,
      O => \fsm_reg[0]_i_2__1_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      S => RST_CPLLRESET
    );
\fsm_reg[1]_i_1__1\: unisim.vcomponents.MUXF8
     port map (
      I0 => \fsm_reg[1]_i_2__1_n_0\,
      I1 => \fsm_reg[1]_i_3__1_n_0\,
      O => fsm(1),
      S => \^q\(4)
    );
\fsm_reg[1]_i_2__1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_4__1_n_0\,
      I1 => \fsm[1]_i_5__1_n_0\,
      O => \fsm_reg[1]_i_2__1_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]_i_3__1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_6__1_n_0\,
      I1 => \fsm[1]_i_7__1_n_0\,
      O => \fsm_reg[1]_i_3__1_n_0\,
      S => \^q\(3)
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\fsm_reg[4]_i_1__1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[4]_i_2__1_n_0\,
      I1 => \fsm[4]_i_3__1_n_0\,
      O => fsm(4),
      S => \^q\(4)
    );
\gen3_exit_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_exit_i_2__1_n_0\,
      I4 => gen3_exit,
      O => \gen3_exit_i_1__1_n_0\
    );
\gen3_exit_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000000000001"
    )
        port map (
      I0 => \fsm[3]_i_9__1_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => \gen3_exit_i_2__1_n_0\
    );
gen3_exit_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_exit_i_1__1_n_0\,
      Q => gen3_exit,
      R => RST_CPLLRESET
    );
\gen3_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_i_2__1_n_0\,
      I4 => \^rate_gen3\(0),
      O => \gen3_i_1__1_n_0\
    );
\gen3_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000008"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(1),
      O => \gen3_i_2__1_n_0\
    );
gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_i_1__1_n_0\,
      Q => \^rate_gen3\(0),
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_6__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[2]_0\
    );
\gtx_channel.gtxe2_channel_i_i_7__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[2]\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
\pclk_sel_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06FF0600"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \pclk_sel_i_2__1_n_0\,
      I4 => \^user_pclk_sel\,
      O => \pclk_sel_i_1__2_n_0\
    );
\pclk_sel_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80040800"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \pclk_sel_i_2__1_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pclk_sel_i_1__2_n_0\,
      Q => \^user_pclk_sel\,
      R => RST_CPLLRESET
    );
\phystatus_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \txratedone_i_2__1_n_0\,
      I2 => phystatus_reg_n_0,
      O => \phystatus_i_1__1_n_0\
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \phystatus_i_1__1_n_0\,
      Q => phystatus_reg_n_0,
      R => '0'
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_PHYSTATUS,
      Q => phystatus_reg1,
      R => RST_CPLLRESET
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => RST_CPLLRESET
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_QPLLLOCK,
      Q => qplllock_reg1,
      R => RST_CPLLRESET
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => RST_CPLLRESET
    );
\qpllpd_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^qrst_qpllpd_in\(0),
      O => \qpllpd_i_1__2_n_0\
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllpd_i_1__2_n_0\,
      Q => \^qrst_qpllpd_in\(0),
      R => RST_CPLLRESET
    );
\qpllreset_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^qrst_qpllreset_in\(0),
      O => \qpllreset_i_1__2_n_0\
    );
qpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllreset_i_1__2_n_0\,
      Q => \^qrst_qpllreset_in\(0),
      R => RST_CPLLRESET
    );
\rate_done_reg1_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => USER_RATE_DONE
    );
\rate_idle_reg1[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => RST_RATE_IDLE(0)
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_in_reg1(0),
      R => RST_CPLLRESET
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => RST_CPLLRESET
    );
\rate_out[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      I2 => \^q\(1),
      I3 => \rate_out[2]_i_2__1_n_0\,
      I4 => \^rxrate\(0),
      O => \rate_out[0]_i_1__1_n_0\
    );
\rate_out[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__1_n_0\,
      I1 => \^rxrate\(1),
      O => \rate_out[1]_i_1__1_n_0\
    );
\rate_out[2]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__1_n_0\,
      I1 => \^rxrate\(2),
      O => \rate_out[2]_i_1__1_n_0\
    );
\rate_out[2]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000002080000220"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \rate_out[2]_i_3__1_n_0\,
      O => \rate_out[2]_i_2__1_n_0\
    );
\rate_out[2]_i_3__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => gen3_exit,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      O => \rate_out[2]_i_3__1_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[0]_i_1__1_n_0\,
      Q => \^rxrate\(0),
      R => RST_CPLLRESET
    );
\rate_out_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[1]_i_1__1_n_0\,
      Q => \^rxrate\(1),
      R => RST_CPLLRESET
    );
\rate_out_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[2]_i_1__1_n_0\,
      Q => \^rxrate\(2),
      R => RST_CPLLRESET
    );
\rate_rxsync_reg1_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => USER_RATE_RXSYNC
    );
\ratedone_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF008000"
    )
        port map (
      I0 => rxratedone_reg_n_0,
      I1 => txratedone_reg_n_0,
      I2 => phystatus_reg_n_0,
      I3 => \txratedone_i_2__1_n_0\,
      I4 => ratedone_reg_n_0,
      O => \ratedone_i_1__1_n_0\
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \ratedone_i_1__1_n_0\,
      Q => ratedone_reg_n_0,
      R => '0'
    );
resetovrd_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RESETOVRD_DONE,
      Q => resetovrd_done_reg1,
      R => RST_CPLLRESET
    );
resetovrd_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => resetovrd_done_reg1,
      Q => resetovrd_done_reg2,
      R => RST_CPLLRESET
    );
\resetovrd_start_reg1_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(4),
      I4 => \^q\(2),
      O => USER_RESETOVRD_START
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => out1(1),
      Q => rst_idle_reg1,
      R => RST_CPLLRESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => RST_CPLLRESET
    );
\rxratedone_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \txratedone_i_2__1_n_0\,
      I2 => rxratedone_reg_n_0,
      O => \rxratedone_i_1__1_n_0\
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rxratedone_i_1__1_n_0\,
      Q => rxratedone_reg_n_0,
      R => '0'
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RXRATEDONE,
      Q => rxratedone_reg1,
      R => RST_CPLLRESET
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => SYNC_RXSYNC_DONE,
      Q => rxsync_done_reg1,
      R => RST_CPLLRESET
    );
rxsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxsync_done_reg1,
      Q => rxsync_done_reg2,
      R => RST_CPLLRESET
    );
\rxsync_start_reg1_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => SYNC_RXSYNC_START
    );
\start_reg1_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in109_in,
      I1 => RST_DRP_START,
      O => DRP_START0110_out
    );
\sysclksel[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF3EFF00000200"
    )
        port map (
      I0 => \sysclksel[0]_i_2__1_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \sysclksel[0]_i_3__1_n_0\,
      I5 => \^rxsysclksel\(0),
      O => \sysclksel[0]_i_1__1_n_0\
    );
\sysclksel[0]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      O => \sysclksel[0]_i_2__1_n_0\
    );
\sysclksel[0]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      O => \sysclksel[0]_i_3__1_n_0\
    );
\sysclksel[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FFFFFFF00000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^rxsysclksel\(1),
      O => \sysclksel[1]_i_1__1_n_0\
    );
\sysclksel_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[0]_i_1__1_n_0\,
      Q => \^rxsysclksel\(0),
      R => RST_CPLLRESET
    );
\sysclksel_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[1]_i_1__1_n_0\,
      Q => \^rxsysclksel\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__1_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(0)
    );
\txdata_wait_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__1_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(0),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(3),
      I4 => \txdata_wait_cnt_reg__0\(2),
      O => \p_0_in__0\(1)
    );
\txdata_wait_cnt[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AA0A0A0"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__1_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(2)
    );
\txdata_wait_cnt[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__1_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(3),
      O => \p_0_in__0\(3)
    );
\txdata_wait_cnt[3]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \txdata_wait_cnt[3]_i_2__1_n_0\
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \txdata_wait_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \txdata_wait_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \txdata_wait_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \txdata_wait_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\txpmareset_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5504FFFF55040000"
    )
        port map (
      I0 => \^q\(3),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => gen3_exit,
      I4 => \txpmareset_i_2__1_n_0\,
      I5 => \^gt_txpmareset0120_out\,
      O => \txpmareset_i_1__1_n_0\
    );
\txpmareset_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82000400"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \txpmareset_i_2__1_n_0\
    );
txpmareset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txpmareset_i_1__1_n_0\,
      Q => \^gt_txpmareset0120_out\,
      R => RST_CPLLRESET
    );
\txratedone_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \txratedone_i_2__1_n_0\,
      I2 => txratedone_reg_n_0,
      O => \txratedone_i_1__1_n_0\
    );
\txratedone_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => RST_CPLLRESET,
      O => \txratedone_i_2__1_n_0\
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txratedone_i_1__1_n_0\,
      Q => txratedone_reg_n_0,
      R => '0'
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXRATEDONE,
      Q => txratedone_reg1,
      R => RST_CPLLRESET
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => RST_CPLLRESET
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXSYNC_DONE,
      Q => txsync_done_reg1,
      R => RST_CPLLRESET
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => RST_CPLLRESET
    );
\txsync_start_reg1_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAA"
    )
        port map (
      I0 => out1(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => SYNC_TXSYNC_START
    );
\x16_reg1_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in111_in,
      I1 => RST_DRP_X16,
      O => DRP_X160112_out
    );
\x16x20_mode_reg1_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in113_in,
      I1 => RST_DRP_X16X20_MODE,
      O => DRP_X16X20_MODE0114_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_44 is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RESETOVRD_START : out STD_LOGIC;
    RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_TXSYNC_START : out STD_LOGIC;
    DRP_X16X20_MODE086_out : out STD_LOGIC;
    DRP_X16084_out : out STD_LOGIC;
    DRP_START082_out : out STD_LOGIC;
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    rate_gen3 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[3]_0\ : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_RATE_DONE : out STD_LOGIC;
    USER_RATE_RXSYNC : out STD_LOGIC;
    SYNC_RXSYNC_START : out STD_LOGIC;
    RST_RATE_IDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    GT_TXPMARESET074_out : out STD_LOGIC;
    USER_PCLK_SEL : out STD_LOGIC;
    QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in75_in : out STD_LOGIC;
    QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in77_in : out STD_LOGIC;
    out1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RST_DRP_X16X20_MODE : in STD_LOGIC;
    RST_DRP_X16 : in STD_LOGIC;
    RST_DRP_START : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg_0 : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_CPLLLOCK : in STD_LOGIC;
    qpllpd_reg_0 : in STD_LOGIC;
    RATE_DRP_DONE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    RATE_PHYSTATUS : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    USER_RXRESETDONE : in STD_LOGIC;
    RATE_TXRATEDONE : in STD_LOGIC;
    RATE_RXRATEDONE : in STD_LOGIC;
    RATE_RESETOVRD_DONE : in STD_LOGIC;
    RATE_TXSYNC_DONE : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    p_0_in7_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_44 : entity is "PCIeGen1x8If64_pipe_rate";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_44;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_44 is
  signal \^gt_txpmareset074_out\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^user_pclk_sel\ : STD_LOGIC;
  signal cplllock_reg1 : STD_LOGIC;
  signal cplllock_reg2 : STD_LOGIC;
  signal \cpllpd_i_1__2_n_0\ : STD_LOGIC;
  signal \cpllreset_i_1__3_n_0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC;
  signal drp_done_reg2 : STD_LOGIC;
  signal \drp_start_i_1__2_n_0\ : STD_LOGIC;
  signal \drp_x16_i_1__2_n_0\ : STD_LOGIC;
  signal \drp_x16x20_mode_i_1__2_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal \fsm[0]_i_10__2_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_11__2_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_12__2_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_3__5_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_4__2_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_5__2_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_6__2_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_7__2_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_8__2_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_9__2_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_4__2_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_5__2_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_6__2_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_7__2_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_8__2_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_9__2_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_3__2_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_4__2_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_5__2_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_3__2_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_4__2_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_5__2_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_8__2_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_9__2_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_3__2_n_0\ : STD_LOGIC;
  signal \fsm_reg[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_3__2_n_0\ : STD_LOGIC;
  signal gen3_exit : STD_LOGIC;
  signal \gen3_exit_i_1__2_n_0\ : STD_LOGIC;
  signal \gen3_exit_i_2__2_n_0\ : STD_LOGIC;
  signal \gen3_i_1__2_n_0\ : STD_LOGIC;
  signal \gen3_i_2__2_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^p_0_in75_in\ : STD_LOGIC;
  signal \^p_0_in77_in\ : STD_LOGIC;
  signal p_0_in81_in : STD_LOGIC;
  signal p_0_in83_in : STD_LOGIC;
  signal p_0_in85_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pclk_sel_i_1__3_n_0\ : STD_LOGIC;
  signal \pclk_sel_i_2__2_n_0\ : STD_LOGIC;
  signal \phystatus_i_1__2_n_0\ : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  signal phystatus_reg2 : STD_LOGIC;
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal pll_lock : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  signal qplllock_reg2 : STD_LOGIC;
  signal qpllpd : STD_LOGIC;
  signal \qpllpd_i_1__3_n_0\ : STD_LOGIC;
  signal qpllreset : STD_LOGIC;
  signal \qpllreset_i_1__3_n_0\ : STD_LOGIC;
  signal \^rate_gen3\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rate_out[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \rate_out[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_3__2_n_0\ : STD_LOGIC;
  signal \ratedone_i_1__2_n_0\ : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal resetovrd_done_reg1 : STD_LOGIC;
  signal resetovrd_done_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  signal \rxratedone_i_1__2_n_0\ : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  signal rxratedone_reg2 : STD_LOGIC;
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxsync_done_reg1 : STD_LOGIC;
  signal rxsync_done_reg2 : STD_LOGIC;
  signal \sysclksel[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_3__2_n_0\ : STD_LOGIC;
  signal \sysclksel[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txpmareset_i_1__2_n_0\ : STD_LOGIC;
  signal \txpmareset_i_2__2_n_0\ : STD_LOGIC;
  signal \txratedone_i_1__2_n_0\ : STD_LOGIC;
  signal \txratedone_i_2__2_n_0\ : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  signal txratedone_reg2 : STD_LOGIC;
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC;
  signal txsync_done_reg2 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of cplllock_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of cplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of cplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of cplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cpllpd_i_2__2\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \cpllreset_i_2__2\ : label is "soft_lutpair104";
  attribute ASYNC_REG of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \drp_start_i_1__2\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \drp_x16_i_1__2\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__2\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \fsm[0]_i_9__2\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \fsm[3]_i_5__2\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \gen3_i_2__2\ : label is "soft_lutpair107";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \pclk_sel_i_2__2\ : label is "soft_lutpair104";
  attribute ASYNC_REG of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rate_done_reg1_i_1__2\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \rate_idle_reg1[3]_i_1\ : label is "soft_lutpair107";
  attribute ASYNC_REG of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SOFT_HLUTNM of \rate_out[1]_i_1__2\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \rate_out[2]_i_1__2\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \rate_rxsync_reg1_i_1__2\ : label is "soft_lutpair99";
  attribute ASYNC_REG of resetovrd_done_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_done_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_start_reg1_i_1__2\ : label is "soft_lutpair98";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rxsync_start_reg1_i_1__2\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1__2\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1__2\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1__2\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1__2\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2__2\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \txpmareset_i_2__2\ : label is "soft_lutpair106";
  attribute ASYNC_REG of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
begin
  GT_TXPMARESET074_out <= \^gt_txpmareset074_out\;
  Q(4 downto 0) <= \^q\(4 downto 0);
  QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0);
  QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0);
  RXRATE(2 downto 0) <= \^rxrate\(2 downto 0);
  RXSYSCLKSEL(1 downto 0) <= \^rxsysclksel\(1 downto 0);
  USER_PCLK_SEL <= \^user_pclk_sel\;
  p_0_in75_in <= \^p_0_in75_in\;
  p_0_in77_in <= \^p_0_in77_in\;
  rate_gen3(0) <= \^rate_gen3\(0);
cplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_CPLLLOCK,
      Q => cplllock_reg1,
      R => RST_CPLLRESET
    );
cplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => cplllock_reg1,
      Q => cplllock_reg2,
      R => RST_CPLLRESET
    );
\cpllpd_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^p_0_in77_in\,
      O => \cpllpd_i_1__2_n_0\
    );
\cpllpd_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000084"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(0),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => qpllpd
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllpd_i_1__2_n_0\,
      Q => \^p_0_in77_in\,
      R => RST_CPLLRESET
    );
\cpllreset_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^p_0_in75_in\,
      O => \cpllreset_i_1__3_n_0\
    );
\cpllreset_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"81000002"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => qpllreset
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllreset_i_1__3_n_0\,
      Q => \^p_0_in75_in\,
      R => RST_CPLLRESET
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_DRP_DONE,
      Q => drp_done_reg1,
      R => RST_CPLLRESET
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => RST_CPLLRESET
    );
\drp_start_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08200108"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => \^q\(1),
      O => \drp_start_i_1__2_n_0\
    );
drp_start_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_start_i_1__2_n_0\,
      Q => p_0_in81_in,
      R => RST_CPLLRESET
    );
\drp_x16_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20020006"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(4),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(0),
      O => \drp_x16_i_1__2_n_0\
    );
drp_x16_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16_i_1__2_n_0\,
      Q => p_0_in83_in,
      R => RST_CPLLRESET
    );
\drp_x16x20_mode_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20001584"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => \drp_x16x20_mode_i_1__2_n_0\
    );
drp_x16x20_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16x20_mode_i_1__2_n_0\,
      Q => p_0_in85_in,
      R => RST_CPLLRESET
    );
\fsm[0]_i_10__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \txdata_wait_cnt_reg__0\(3),
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(0),
      I3 => \txdata_wait_cnt_reg__0\(1),
      O => \fsm[0]_i_10__2_n_0\
    );
\fsm[0]_i_11__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F404"
    )
        port map (
      I0 => rxpmaresetdone_reg2,
      I1 => mmcm_lock_reg2,
      I2 => \^q\(0),
      I3 => drp_done_reg2,
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \fsm[0]_i_11__2_n_0\
    );
\fsm[0]_i_12__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F737F4343404C"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => rxpmaresetdone_reg2,
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[0]_i_12__2_n_0\
    );
\fsm[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBB88888BBB8BBB8"
    )
        port map (
      I0 => \fsm_reg[0]_i_2__2_n_0\,
      I1 => \^q\(4),
      I2 => \fsm[0]_i_3__5_n_0\,
      I3 => \^q\(3),
      I4 => \fsm[0]_i_4__2_n_0\,
      I5 => \fsm[0]_i_5__2_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0344FF440344FF77"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => pll_lock,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \fsm[3]_i_9__2_n_0\,
      O => \fsm[0]_i_3__5_n_0\
    );
\fsm[0]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0000000F800F000"
    )
        port map (
      I0 => pll_lock,
      I1 => rst_idle_reg2,
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => drp_done_reg2,
      I5 => \^q\(0),
      O => \fsm[0]_i_4__2_n_0\
    );
\fsm[0]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCC8C0C8"
    )
        port map (
      I0 => \fsm[0]_i_8__2_n_0\,
      I1 => \^q\(3),
      I2 => \fsm[0]_i_9__2_n_0\,
      I3 => \^q\(0),
      I4 => \fsm[0]_i_10__2_n_0\,
      I5 => \fsm[0]_i_11__2_n_0\,
      O => \fsm[0]_i_5__2_n_0\
    );
\fsm[0]_i_6__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0040"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \fsm[0]_i_12__2_n_0\,
      O => \fsm[0]_i_6__2_n_0\
    );
\fsm[0]_i_7__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03880333"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[0]_i_7__2_n_0\
    );
\fsm[0]_i_8__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77770777"
    )
        port map (
      I0 => p_0_in7_in,
      I1 => p_1_in8_in,
      I2 => rxresetdone_reg2,
      I3 => txresetdone_reg2,
      I4 => phystatus_reg2,
      O => \fsm[0]_i_8__2_n_0\
    );
\fsm[0]_i_9__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      O => \fsm[0]_i_9__2_n_0\
    );
\fsm[1]_i_4__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BBFC00"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_8__2_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_4__2_n_0\
    );
\fsm[1]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC88300000BB3000"
    )
        port map (
      I0 => \fsm[0]_i_10__2_n_0\,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_9__2_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[1]_i_5__2_n_0\
    );
\fsm[1]_i_6__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70F040F0"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => drp_done_reg2,
      O => \fsm[1]_i_6__2_n_0\
    );
\fsm[1]_i_7__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03777700"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_7__2_n_0\
    );
\fsm[1]_i_8__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"53F5FFFFFFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => qplllock_reg2,
      I2 => rate_in_reg2(0),
      I3 => rate_in_reg2(1),
      I4 => rst_idle_reg2,
      I5 => \^q\(0),
      O => \fsm[1]_i_8__2_n_0\
    );
\fsm[1]_i_9__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF4575FFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      I3 => qplllock_reg2,
      I4 => rst_idle_reg2,
      I5 => drp_done_reg2,
      O => \fsm[1]_i_9__2_n_0\
    );
\fsm[2]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fsm[2]_i_2__2_n_0\,
      I1 => \fsm[2]_i_3__2_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[2]_i_4__2_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[2]_i_5__2_n_0\,
      O => fsm(2)
    );
\fsm[2]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3C0C4040"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_done_reg2,
      I4 => \^q\(0),
      O => \fsm[2]_i_2__2_n_0\
    );
\fsm[2]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13CCD3CC1FCCDFCC"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => resetovrd_done_reg2,
      I5 => fsm1,
      O => \fsm[2]_i_3__2_n_0\
    );
\fsm[2]_i_4__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BC0C"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \fsm[2]_i_4__2_n_0\
    );
\fsm[2]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4A4A4A4AAAAFAAAA"
    )
        port map (
      I0 => \^q\(2),
      I1 => pll_lock,
      I2 => \^q\(1),
      I3 => \fsm[3]_i_9__2_n_0\,
      I4 => \fsm[3]_i_8__2_n_0\,
      I5 => \^q\(0),
      O => \fsm[2]_i_5__2_n_0\
    );
\fsm[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFE0EFEFEFE0E0E0"
    )
        port map (
      I0 => \fsm[3]_i_2__2_n_0\,
      I1 => \fsm[3]_i_3__2_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[3]_i_4__2_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[3]_i_5__2_n_0\,
      O => fsm(3)
    );
\fsm[3]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22AA2A22"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => rxsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[3]_i_2__2_n_0\
    );
\fsm[3]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3020002000000000"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => resetovrd_done_reg2,
      I5 => \^q\(0),
      O => \fsm[3]_i_3__2_n_0\
    );
\fsm[3]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F545F555FFFFFFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rst_idle_reg2,
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => pll_lock,
      I5 => \^q\(1),
      O => \fsm[3]_i_4__2_n_0\
    );
\fsm[3]_i_5__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80808180"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \fsm[3]_i_8__2_n_0\,
      I4 => \fsm[3]_i_9__2_n_0\,
      O => \fsm[3]_i_5__2_n_0\
    );
\fsm[3]_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF8F8FFF8"
    )
        port map (
      I0 => p_1_in8_in,
      I1 => p_0_in7_in,
      I2 => ratedone_reg_n_0,
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg2(0),
      I5 => gen3_exit,
      O => fsm1
    );
\fsm[3]_i_7__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => cplllock_reg2,
      O => pll_lock
    );
\fsm[3]_i_8__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg1(1),
      O => \fsm[3]_i_8__2_n_0\
    );
\fsm[3]_i_9__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rate_in_reg1(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(1),
      I3 => rate_in_reg2(1),
      O => \fsm[3]_i_9__2_n_0\
    );
\fsm[4]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08880000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \fsm[4]_i_2__2_n_0\
    );
\fsm[4]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5F75FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rxsync_done_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \fsm[4]_i_3__2_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\fsm_reg[0]_i_2__2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[0]_i_6__2_n_0\,
      I1 => \fsm[0]_i_7__2_n_0\,
      O => \fsm_reg[0]_i_2__2_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      S => RST_CPLLRESET
    );
\fsm_reg[1]_i_1__2\: unisim.vcomponents.MUXF8
     port map (
      I0 => \fsm_reg[1]_i_2__2_n_0\,
      I1 => \fsm_reg[1]_i_3__2_n_0\,
      O => fsm(1),
      S => \^q\(4)
    );
\fsm_reg[1]_i_2__2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_4__2_n_0\,
      I1 => \fsm[1]_i_5__2_n_0\,
      O => \fsm_reg[1]_i_2__2_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]_i_3__2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_6__2_n_0\,
      I1 => \fsm[1]_i_7__2_n_0\,
      O => \fsm_reg[1]_i_3__2_n_0\,
      S => \^q\(3)
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\fsm_reg[4]_i_1__2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[4]_i_2__2_n_0\,
      I1 => \fsm[4]_i_3__2_n_0\,
      O => fsm(4),
      S => \^q\(4)
    );
\gen3_exit_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_exit_i_2__2_n_0\,
      I4 => gen3_exit,
      O => \gen3_exit_i_1__2_n_0\
    );
\gen3_exit_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000000000001"
    )
        port map (
      I0 => \fsm[3]_i_9__2_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => \gen3_exit_i_2__2_n_0\
    );
gen3_exit_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_exit_i_1__2_n_0\,
      Q => gen3_exit,
      R => RST_CPLLRESET
    );
\gen3_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_i_2__2_n_0\,
      I4 => \^rate_gen3\(0),
      O => \gen3_i_1__2_n_0\
    );
\gen3_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000008"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(1),
      O => \gen3_i_2__2_n_0\
    );
gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_i_1__2_n_0\,
      Q => \^rate_gen3\(0),
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_6__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[3]_0\
    );
\gtx_channel.gtxe2_channel_i_i_7__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[3]\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
\pclk_sel_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06FF0600"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \pclk_sel_i_2__2_n_0\,
      I4 => \^user_pclk_sel\,
      O => \pclk_sel_i_1__3_n_0\
    );
\pclk_sel_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80040800"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \pclk_sel_i_2__2_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pclk_sel_i_1__3_n_0\,
      Q => \^user_pclk_sel\,
      R => RST_CPLLRESET
    );
\phystatus_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \txratedone_i_2__2_n_0\,
      I2 => phystatus_reg_n_0,
      O => \phystatus_i_1__2_n_0\
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \phystatus_i_1__2_n_0\,
      Q => phystatus_reg_n_0,
      R => '0'
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_PHYSTATUS,
      Q => phystatus_reg1,
      R => RST_CPLLRESET
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => RST_CPLLRESET
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => qpllpd_reg_0,
      Q => qplllock_reg1,
      R => RST_CPLLRESET
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => RST_CPLLRESET
    );
\qpllpd_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^qrst_qpllpd_in\(0),
      O => \qpllpd_i_1__3_n_0\
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllpd_i_1__3_n_0\,
      Q => \^qrst_qpllpd_in\(0),
      R => RST_CPLLRESET
    );
\qpllreset_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^qrst_qpllreset_in\(0),
      O => \qpllreset_i_1__3_n_0\
    );
qpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllreset_i_1__3_n_0\,
      Q => \^qrst_qpllreset_in\(0),
      R => RST_CPLLRESET
    );
\rate_done_reg1_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => USER_RATE_DONE
    );
\rate_idle_reg1[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => RST_RATE_IDLE(0)
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_in_reg1(0),
      R => RST_CPLLRESET
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => RST_CPLLRESET
    );
\rate_out[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      I2 => \^q\(1),
      I3 => \rate_out[2]_i_2__2_n_0\,
      I4 => \^rxrate\(0),
      O => \rate_out[0]_i_1__2_n_0\
    );
\rate_out[1]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__2_n_0\,
      I1 => \^rxrate\(1),
      O => \rate_out[1]_i_1__2_n_0\
    );
\rate_out[2]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__2_n_0\,
      I1 => \^rxrate\(2),
      O => \rate_out[2]_i_1__2_n_0\
    );
\rate_out[2]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000002080000220"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \rate_out[2]_i_3__2_n_0\,
      O => \rate_out[2]_i_2__2_n_0\
    );
\rate_out[2]_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => gen3_exit,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      O => \rate_out[2]_i_3__2_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[0]_i_1__2_n_0\,
      Q => \^rxrate\(0),
      R => RST_CPLLRESET
    );
\rate_out_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[1]_i_1__2_n_0\,
      Q => \^rxrate\(1),
      R => RST_CPLLRESET
    );
\rate_out_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[2]_i_1__2_n_0\,
      Q => \^rxrate\(2),
      R => RST_CPLLRESET
    );
\rate_rxsync_reg1_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => USER_RATE_RXSYNC
    );
\ratedone_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF008000"
    )
        port map (
      I0 => rxratedone_reg_n_0,
      I1 => txratedone_reg_n_0,
      I2 => phystatus_reg_n_0,
      I3 => \txratedone_i_2__2_n_0\,
      I4 => ratedone_reg_n_0,
      O => \ratedone_i_1__2_n_0\
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \ratedone_i_1__2_n_0\,
      Q => ratedone_reg_n_0,
      R => '0'
    );
resetovrd_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RESETOVRD_DONE,
      Q => resetovrd_done_reg1,
      R => RST_CPLLRESET
    );
resetovrd_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => resetovrd_done_reg1,
      Q => resetovrd_done_reg2,
      R => RST_CPLLRESET
    );
\resetovrd_start_reg1_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(4),
      I4 => \^q\(2),
      O => USER_RESETOVRD_START
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => out1(1),
      Q => rst_idle_reg1,
      R => RST_CPLLRESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => RST_CPLLRESET
    );
\rxratedone_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \txratedone_i_2__2_n_0\,
      I2 => rxratedone_reg_n_0,
      O => \rxratedone_i_1__2_n_0\
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rxratedone_i_1__2_n_0\,
      Q => rxratedone_reg_n_0,
      R => '0'
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RXRATEDONE,
      Q => rxratedone_reg1,
      R => RST_CPLLRESET
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => SYNC_RXSYNC_DONE,
      Q => rxsync_done_reg1,
      R => RST_CPLLRESET
    );
rxsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxsync_done_reg1,
      Q => rxsync_done_reg2,
      R => RST_CPLLRESET
    );
\rxsync_start_reg1_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => SYNC_RXSYNC_START
    );
\start_reg1_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in81_in,
      I1 => RST_DRP_START,
      O => DRP_START082_out
    );
\sysclksel[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF3EFF00000200"
    )
        port map (
      I0 => \sysclksel[0]_i_2__2_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \sysclksel[0]_i_3__2_n_0\,
      I5 => \^rxsysclksel\(0),
      O => \sysclksel[0]_i_1__2_n_0\
    );
\sysclksel[0]_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      O => \sysclksel[0]_i_2__2_n_0\
    );
\sysclksel[0]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      O => \sysclksel[0]_i_3__2_n_0\
    );
\sysclksel[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FFFFFFF00000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^rxsysclksel\(1),
      O => \sysclksel[1]_i_1__2_n_0\
    );
\sysclksel_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[0]_i_1__2_n_0\,
      Q => \^rxsysclksel\(0),
      R => RST_CPLLRESET
    );
\sysclksel_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[1]_i_1__2_n_0\,
      Q => \^rxsysclksel\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__2_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(0)
    );
\txdata_wait_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__2_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(0),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(3),
      I4 => \txdata_wait_cnt_reg__0\(2),
      O => \p_0_in__0\(1)
    );
\txdata_wait_cnt[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AA0A0A0"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__2_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(2)
    );
\txdata_wait_cnt[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__2_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(3),
      O => \p_0_in__0\(3)
    );
\txdata_wait_cnt[3]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \txdata_wait_cnt[3]_i_2__2_n_0\
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \txdata_wait_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \txdata_wait_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \txdata_wait_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \txdata_wait_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\txpmareset_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5504FFFF55040000"
    )
        port map (
      I0 => \^q\(3),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => gen3_exit,
      I4 => \txpmareset_i_2__2_n_0\,
      I5 => \^gt_txpmareset074_out\,
      O => \txpmareset_i_1__2_n_0\
    );
\txpmareset_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82000400"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \txpmareset_i_2__2_n_0\
    );
txpmareset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txpmareset_i_1__2_n_0\,
      Q => \^gt_txpmareset074_out\,
      R => RST_CPLLRESET
    );
\txratedone_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \txratedone_i_2__2_n_0\,
      I2 => txratedone_reg_n_0,
      O => \txratedone_i_1__2_n_0\
    );
\txratedone_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => RST_CPLLRESET,
      O => \txratedone_i_2__2_n_0\
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txratedone_i_1__2_n_0\,
      Q => txratedone_reg_n_0,
      R => '0'
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXRATEDONE,
      Q => txratedone_reg1,
      R => RST_CPLLRESET
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => RST_CPLLRESET
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXSYNC_DONE,
      Q => txsync_done_reg1,
      R => RST_CPLLRESET
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => RST_CPLLRESET
    );
\txsync_start_reg1_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAA"
    )
        port map (
      I0 => out1(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => SYNC_TXSYNC_START
    );
\x16_reg1_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in83_in,
      I1 => RST_DRP_X16,
      O => DRP_X16084_out
    );
\x16x20_mode_reg1_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in85_in,
      I1 => RST_DRP_X16X20_MODE,
      O => DRP_X16X20_MODE086_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_51 is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RESETOVRD_START : out STD_LOGIC;
    RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_TXSYNC_START : out STD_LOGIC;
    DRP_X16X20_MODE0134_out : out STD_LOGIC;
    DRP_X160132_out : out STD_LOGIC;
    DRP_START0130_out : out STD_LOGIC;
    \cplllock_reg1_reg[4]\ : out STD_LOGIC;
    rate_gen3 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[4]_0\ : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_RATE_DONE : out STD_LOGIC;
    USER_RATE_RXSYNC : out STD_LOGIC;
    SYNC_RXSYNC_START : out STD_LOGIC;
    RST_RATE_IDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    GT_TXPMARESET064_out : out STD_LOGIC;
    USER_PCLK_SEL : out STD_LOGIC;
    QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in65_in : out STD_LOGIC;
    QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in67_in : out STD_LOGIC;
    out1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RST_DRP_X16X20_MODE : in STD_LOGIC;
    RST_DRP_X16 : in STD_LOGIC;
    RST_DRP_START : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg_0 : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_CPLLLOCK : in STD_LOGIC;
    RATE_QPLLLOCK : in STD_LOGIC;
    RATE_DRP_DONE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    RATE_PHYSTATUS : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    USER_RXRESETDONE : in STD_LOGIC;
    RATE_TXRATEDONE : in STD_LOGIC;
    RATE_RXRATEDONE : in STD_LOGIC;
    RATE_RESETOVRD_DONE : in STD_LOGIC;
    RATE_TXSYNC_DONE : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    p_0_in7_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_51 : entity is "PCIeGen1x8If64_pipe_rate";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_51;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_51 is
  signal \^gt_txpmareset064_out\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^user_pclk_sel\ : STD_LOGIC;
  signal cplllock_reg1 : STD_LOGIC;
  signal cplllock_reg2 : STD_LOGIC;
  signal \cpllpd_i_1__3_n_0\ : STD_LOGIC;
  signal \cpllreset_i_1__4_n_0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC;
  signal drp_done_reg2 : STD_LOGIC;
  signal \drp_start_i_1__3_n_0\ : STD_LOGIC;
  signal \drp_x16_i_1__3_n_0\ : STD_LOGIC;
  signal \drp_x16x20_mode_i_1__3_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal \fsm[0]_i_10__3_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_11__3_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_12__3_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_3__7_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_4__3_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_5__3_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_6__3_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_7__3_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_8__3_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_9__3_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_4__3_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_5__3_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_6__3_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_7__3_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_8__3_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_9__3_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_2__3_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_3__3_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_4__3_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_5__3_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_2__3_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_3__3_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_4__3_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_5__3_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_8__3_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_9__3_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_3__3_n_0\ : STD_LOGIC;
  signal \fsm_reg[0]_i_2__3_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_2__3_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_3__3_n_0\ : STD_LOGIC;
  signal gen3_exit : STD_LOGIC;
  signal \gen3_exit_i_1__3_n_0\ : STD_LOGIC;
  signal \gen3_exit_i_2__3_n_0\ : STD_LOGIC;
  signal \gen3_i_1__3_n_0\ : STD_LOGIC;
  signal \gen3_i_2__3_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal p_0_in129_in : STD_LOGIC;
  signal p_0_in131_in : STD_LOGIC;
  signal p_0_in133_in : STD_LOGIC;
  signal \^p_0_in65_in\ : STD_LOGIC;
  signal \^p_0_in67_in\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pclk_sel_i_1__4_n_0\ : STD_LOGIC;
  signal \pclk_sel_i_2__3_n_0\ : STD_LOGIC;
  signal \phystatus_i_1__3_n_0\ : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  signal phystatus_reg2 : STD_LOGIC;
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal pll_lock : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  signal qplllock_reg2 : STD_LOGIC;
  signal qpllpd : STD_LOGIC;
  signal \qpllpd_i_1__4_n_0\ : STD_LOGIC;
  signal qpllreset : STD_LOGIC;
  signal \qpllreset_i_1__4_n_0\ : STD_LOGIC;
  signal \^rate_gen3\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rate_out[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \rate_out[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_2__3_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_3__3_n_0\ : STD_LOGIC;
  signal \ratedone_i_1__3_n_0\ : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal resetovrd_done_reg1 : STD_LOGIC;
  signal resetovrd_done_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  signal \rxratedone_i_1__3_n_0\ : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  signal rxratedone_reg2 : STD_LOGIC;
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxsync_done_reg1 : STD_LOGIC;
  signal rxsync_done_reg2 : STD_LOGIC;
  signal \sysclksel[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_2__3_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_3__3_n_0\ : STD_LOGIC;
  signal \sysclksel[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt[3]_i_2__3_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txpmareset_i_1__3_n_0\ : STD_LOGIC;
  signal \txpmareset_i_2__3_n_0\ : STD_LOGIC;
  signal \txratedone_i_1__3_n_0\ : STD_LOGIC;
  signal \txratedone_i_2__3_n_0\ : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  signal txratedone_reg2 : STD_LOGIC;
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC;
  signal txsync_done_reg2 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of cplllock_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of cplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of cplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of cplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cpllpd_i_2__3\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \cpllreset_i_2__3\ : label is "soft_lutpair140";
  attribute ASYNC_REG of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \drp_start_i_1__3\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \drp_x16_i_1__3\ : label is "soft_lutpair142";
  attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__3\ : label is "soft_lutpair139";
  attribute SOFT_HLUTNM of \fsm[0]_i_9__3\ : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of \fsm[3]_i_5__3\ : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of \gen3_i_2__3\ : label is "soft_lutpair143";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \pclk_sel_i_2__3\ : label is "soft_lutpair140";
  attribute ASYNC_REG of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of pipe_rate_idle_INST_0_i_2 : label is "soft_lutpair143";
  attribute ASYNC_REG of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rate_done_reg1_i_1__3\ : label is "soft_lutpair135";
  attribute ASYNC_REG of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SOFT_HLUTNM of \rate_out[1]_i_1__3\ : label is "soft_lutpair144";
  attribute SOFT_HLUTNM of \rate_out[2]_i_1__3\ : label is "soft_lutpair144";
  attribute SOFT_HLUTNM of \rate_rxsync_reg1_i_1__3\ : label is "soft_lutpair135";
  attribute ASYNC_REG of resetovrd_done_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_done_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_start_reg1_i_1__3\ : label is "soft_lutpair134";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rxsync_start_reg1_i_1__3\ : label is "soft_lutpair139";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1__3\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1__3\ : label is "soft_lutpair141";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1__3\ : label is "soft_lutpair141";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1__3\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2__3\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \txpmareset_i_2__3\ : label is "soft_lutpair142";
  attribute ASYNC_REG of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
begin
  GT_TXPMARESET064_out <= \^gt_txpmareset064_out\;
  Q(4 downto 0) <= \^q\(4 downto 0);
  QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0);
  QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0);
  RXRATE(2 downto 0) <= \^rxrate\(2 downto 0);
  RXSYSCLKSEL(1 downto 0) <= \^rxsysclksel\(1 downto 0);
  USER_PCLK_SEL <= \^user_pclk_sel\;
  p_0_in65_in <= \^p_0_in65_in\;
  p_0_in67_in <= \^p_0_in67_in\;
  rate_gen3(0) <= \^rate_gen3\(0);
cplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_CPLLLOCK,
      Q => cplllock_reg1,
      R => RST_CPLLRESET
    );
cplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => cplllock_reg1,
      Q => cplllock_reg2,
      R => RST_CPLLRESET
    );
\cpllpd_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^p_0_in67_in\,
      O => \cpllpd_i_1__3_n_0\
    );
\cpllpd_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000084"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(0),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => qpllpd
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllpd_i_1__3_n_0\,
      Q => \^p_0_in67_in\,
      R => RST_CPLLRESET
    );
\cpllreset_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^p_0_in65_in\,
      O => \cpllreset_i_1__4_n_0\
    );
\cpllreset_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"81000002"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => qpllreset
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllreset_i_1__4_n_0\,
      Q => \^p_0_in65_in\,
      R => RST_CPLLRESET
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_DRP_DONE,
      Q => drp_done_reg1,
      R => RST_CPLLRESET
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => RST_CPLLRESET
    );
\drp_start_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08200108"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => \^q\(1),
      O => \drp_start_i_1__3_n_0\
    );
drp_start_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_start_i_1__3_n_0\,
      Q => p_0_in129_in,
      R => RST_CPLLRESET
    );
\drp_x16_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20020006"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(4),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(0),
      O => \drp_x16_i_1__3_n_0\
    );
drp_x16_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16_i_1__3_n_0\,
      Q => p_0_in131_in,
      R => RST_CPLLRESET
    );
\drp_x16x20_mode_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20001584"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => \drp_x16x20_mode_i_1__3_n_0\
    );
drp_x16x20_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16x20_mode_i_1__3_n_0\,
      Q => p_0_in133_in,
      R => RST_CPLLRESET
    );
\fsm[0]_i_10__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \txdata_wait_cnt_reg__0\(3),
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(0),
      I3 => \txdata_wait_cnt_reg__0\(1),
      O => \fsm[0]_i_10__3_n_0\
    );
\fsm[0]_i_11__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F404"
    )
        port map (
      I0 => rxpmaresetdone_reg2,
      I1 => mmcm_lock_reg2,
      I2 => \^q\(0),
      I3 => drp_done_reg2,
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \fsm[0]_i_11__3_n_0\
    );
\fsm[0]_i_12__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F737F4343404C"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => rxpmaresetdone_reg2,
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[0]_i_12__3_n_0\
    );
\fsm[0]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBB88888BBB8BBB8"
    )
        port map (
      I0 => \fsm_reg[0]_i_2__3_n_0\,
      I1 => \^q\(4),
      I2 => \fsm[0]_i_3__7_n_0\,
      I3 => \^q\(3),
      I4 => \fsm[0]_i_4__3_n_0\,
      I5 => \fsm[0]_i_5__3_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_3__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0344FF440344FF77"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => pll_lock,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \fsm[3]_i_9__3_n_0\,
      O => \fsm[0]_i_3__7_n_0\
    );
\fsm[0]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0000000F800F000"
    )
        port map (
      I0 => pll_lock,
      I1 => rst_idle_reg2,
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => drp_done_reg2,
      I5 => \^q\(0),
      O => \fsm[0]_i_4__3_n_0\
    );
\fsm[0]_i_5__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCC8C0C8"
    )
        port map (
      I0 => \fsm[0]_i_8__3_n_0\,
      I1 => \^q\(3),
      I2 => \fsm[0]_i_9__3_n_0\,
      I3 => \^q\(0),
      I4 => \fsm[0]_i_10__3_n_0\,
      I5 => \fsm[0]_i_11__3_n_0\,
      O => \fsm[0]_i_5__3_n_0\
    );
\fsm[0]_i_6__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0040"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \fsm[0]_i_12__3_n_0\,
      O => \fsm[0]_i_6__3_n_0\
    );
\fsm[0]_i_7__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03880333"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[0]_i_7__3_n_0\
    );
\fsm[0]_i_8__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77770777"
    )
        port map (
      I0 => p_0_in7_in,
      I1 => p_1_in8_in,
      I2 => rxresetdone_reg2,
      I3 => txresetdone_reg2,
      I4 => phystatus_reg2,
      O => \fsm[0]_i_8__3_n_0\
    );
\fsm[0]_i_9__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      O => \fsm[0]_i_9__3_n_0\
    );
\fsm[1]_i_4__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BBFC00"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_8__3_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_4__3_n_0\
    );
\fsm[1]_i_5__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC88300000BB3000"
    )
        port map (
      I0 => \fsm[0]_i_10__3_n_0\,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_9__3_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[1]_i_5__3_n_0\
    );
\fsm[1]_i_6__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70F040F0"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => drp_done_reg2,
      O => \fsm[1]_i_6__3_n_0\
    );
\fsm[1]_i_7__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03777700"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_7__3_n_0\
    );
\fsm[1]_i_8__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"53F5FFFFFFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => qplllock_reg2,
      I2 => rate_in_reg2(0),
      I3 => rate_in_reg2(1),
      I4 => rst_idle_reg2,
      I5 => \^q\(0),
      O => \fsm[1]_i_8__3_n_0\
    );
\fsm[1]_i_9__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF4575FFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      I3 => qplllock_reg2,
      I4 => rst_idle_reg2,
      I5 => drp_done_reg2,
      O => \fsm[1]_i_9__3_n_0\
    );
\fsm[2]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fsm[2]_i_2__3_n_0\,
      I1 => \fsm[2]_i_3__3_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[2]_i_4__3_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[2]_i_5__3_n_0\,
      O => fsm(2)
    );
\fsm[2]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3C0C4040"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_done_reg2,
      I4 => \^q\(0),
      O => \fsm[2]_i_2__3_n_0\
    );
\fsm[2]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13CCD3CC1FCCDFCC"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => resetovrd_done_reg2,
      I5 => fsm1,
      O => \fsm[2]_i_3__3_n_0\
    );
\fsm[2]_i_4__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BC0C"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \fsm[2]_i_4__3_n_0\
    );
\fsm[2]_i_5__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4A4A4A4AAAAFAAAA"
    )
        port map (
      I0 => \^q\(2),
      I1 => pll_lock,
      I2 => \^q\(1),
      I3 => \fsm[3]_i_9__3_n_0\,
      I4 => \fsm[3]_i_8__3_n_0\,
      I5 => \^q\(0),
      O => \fsm[2]_i_5__3_n_0\
    );
\fsm[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFE0EFEFEFE0E0E0"
    )
        port map (
      I0 => \fsm[3]_i_2__3_n_0\,
      I1 => \fsm[3]_i_3__3_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[3]_i_4__3_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[3]_i_5__3_n_0\,
      O => fsm(3)
    );
\fsm[3]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22AA2A22"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => rxsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[3]_i_2__3_n_0\
    );
\fsm[3]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3020002000000000"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => resetovrd_done_reg2,
      I5 => \^q\(0),
      O => \fsm[3]_i_3__3_n_0\
    );
\fsm[3]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F545F555FFFFFFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rst_idle_reg2,
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => pll_lock,
      I5 => \^q\(1),
      O => \fsm[3]_i_4__3_n_0\
    );
\fsm[3]_i_5__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80808180"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \fsm[3]_i_8__3_n_0\,
      I4 => \fsm[3]_i_9__3_n_0\,
      O => \fsm[3]_i_5__3_n_0\
    );
\fsm[3]_i_6__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF8F8FFF8"
    )
        port map (
      I0 => p_1_in8_in,
      I1 => p_0_in7_in,
      I2 => ratedone_reg_n_0,
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg2(0),
      I5 => gen3_exit,
      O => fsm1
    );
\fsm[3]_i_7__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => cplllock_reg2,
      O => pll_lock
    );
\fsm[3]_i_8__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg1(1),
      O => \fsm[3]_i_8__3_n_0\
    );
\fsm[3]_i_9__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rate_in_reg1(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(1),
      I3 => rate_in_reg2(1),
      O => \fsm[3]_i_9__3_n_0\
    );
\fsm[4]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08880000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \fsm[4]_i_2__3_n_0\
    );
\fsm[4]_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5F75FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rxsync_done_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \fsm[4]_i_3__3_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\fsm_reg[0]_i_2__3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[0]_i_6__3_n_0\,
      I1 => \fsm[0]_i_7__3_n_0\,
      O => \fsm_reg[0]_i_2__3_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      S => RST_CPLLRESET
    );
\fsm_reg[1]_i_1__3\: unisim.vcomponents.MUXF8
     port map (
      I0 => \fsm_reg[1]_i_2__3_n_0\,
      I1 => \fsm_reg[1]_i_3__3_n_0\,
      O => fsm(1),
      S => \^q\(4)
    );
\fsm_reg[1]_i_2__3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_4__3_n_0\,
      I1 => \fsm[1]_i_5__3_n_0\,
      O => \fsm_reg[1]_i_2__3_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]_i_3__3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_6__3_n_0\,
      I1 => \fsm[1]_i_7__3_n_0\,
      O => \fsm_reg[1]_i_3__3_n_0\,
      S => \^q\(3)
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\fsm_reg[4]_i_1__3\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[4]_i_2__3_n_0\,
      I1 => \fsm[4]_i_3__3_n_0\,
      O => fsm(4),
      S => \^q\(4)
    );
\gen3_exit_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_exit_i_2__3_n_0\,
      I4 => gen3_exit,
      O => \gen3_exit_i_1__3_n_0\
    );
\gen3_exit_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000000000001"
    )
        port map (
      I0 => \fsm[3]_i_9__3_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => \gen3_exit_i_2__3_n_0\
    );
gen3_exit_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_exit_i_1__3_n_0\,
      Q => gen3_exit,
      R => RST_CPLLRESET
    );
\gen3_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_i_2__3_n_0\,
      I4 => \^rate_gen3\(0),
      O => \gen3_i_1__3_n_0\
    );
\gen3_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000008"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(1),
      O => \gen3_i_2__3_n_0\
    );
gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_i_1__3_n_0\,
      Q => \^rate_gen3\(0),
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_6__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[4]_0\
    );
\gtx_channel.gtxe2_channel_i_i_7__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[4]\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
\pclk_sel_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06FF0600"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \pclk_sel_i_2__3_n_0\,
      I4 => \^user_pclk_sel\,
      O => \pclk_sel_i_1__4_n_0\
    );
\pclk_sel_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80040800"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \pclk_sel_i_2__3_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pclk_sel_i_1__4_n_0\,
      Q => \^user_pclk_sel\,
      R => RST_CPLLRESET
    );
\phystatus_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \txratedone_i_2__3_n_0\,
      I2 => phystatus_reg_n_0,
      O => \phystatus_i_1__3_n_0\
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \phystatus_i_1__3_n_0\,
      Q => phystatus_reg_n_0,
      R => '0'
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_PHYSTATUS,
      Q => phystatus_reg1,
      R => RST_CPLLRESET
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => RST_CPLLRESET
    );
pipe_rate_idle_INST_0_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => RST_RATE_IDLE(0)
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_QPLLLOCK,
      Q => qplllock_reg1,
      R => RST_CPLLRESET
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => RST_CPLLRESET
    );
\qpllpd_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^qrst_qpllpd_in\(0),
      O => \qpllpd_i_1__4_n_0\
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllpd_i_1__4_n_0\,
      Q => \^qrst_qpllpd_in\(0),
      R => RST_CPLLRESET
    );
\qpllreset_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^qrst_qpllreset_in\(0),
      O => \qpllreset_i_1__4_n_0\
    );
qpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllreset_i_1__4_n_0\,
      Q => \^qrst_qpllreset_in\(0),
      R => RST_CPLLRESET
    );
\rate_done_reg1_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => USER_RATE_DONE
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_in_reg1(0),
      R => RST_CPLLRESET
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => RST_CPLLRESET
    );
\rate_out[0]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      I2 => \^q\(1),
      I3 => \rate_out[2]_i_2__3_n_0\,
      I4 => \^rxrate\(0),
      O => \rate_out[0]_i_1__3_n_0\
    );
\rate_out[1]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__3_n_0\,
      I1 => \^rxrate\(1),
      O => \rate_out[1]_i_1__3_n_0\
    );
\rate_out[2]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__3_n_0\,
      I1 => \^rxrate\(2),
      O => \rate_out[2]_i_1__3_n_0\
    );
\rate_out[2]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000002080000220"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \rate_out[2]_i_3__3_n_0\,
      O => \rate_out[2]_i_2__3_n_0\
    );
\rate_out[2]_i_3__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => gen3_exit,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      O => \rate_out[2]_i_3__3_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[0]_i_1__3_n_0\,
      Q => \^rxrate\(0),
      R => RST_CPLLRESET
    );
\rate_out_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[1]_i_1__3_n_0\,
      Q => \^rxrate\(1),
      R => RST_CPLLRESET
    );
\rate_out_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[2]_i_1__3_n_0\,
      Q => \^rxrate\(2),
      R => RST_CPLLRESET
    );
\rate_rxsync_reg1_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => USER_RATE_RXSYNC
    );
\ratedone_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF008000"
    )
        port map (
      I0 => rxratedone_reg_n_0,
      I1 => txratedone_reg_n_0,
      I2 => phystatus_reg_n_0,
      I3 => \txratedone_i_2__3_n_0\,
      I4 => ratedone_reg_n_0,
      O => \ratedone_i_1__3_n_0\
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \ratedone_i_1__3_n_0\,
      Q => ratedone_reg_n_0,
      R => '0'
    );
resetovrd_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RESETOVRD_DONE,
      Q => resetovrd_done_reg1,
      R => RST_CPLLRESET
    );
resetovrd_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => resetovrd_done_reg1,
      Q => resetovrd_done_reg2,
      R => RST_CPLLRESET
    );
\resetovrd_start_reg1_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(4),
      I4 => \^q\(2),
      O => USER_RESETOVRD_START
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => out1(1),
      Q => rst_idle_reg1,
      R => RST_CPLLRESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => RST_CPLLRESET
    );
\rxratedone_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \txratedone_i_2__3_n_0\,
      I2 => rxratedone_reg_n_0,
      O => \rxratedone_i_1__3_n_0\
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rxratedone_i_1__3_n_0\,
      Q => rxratedone_reg_n_0,
      R => '0'
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RXRATEDONE,
      Q => rxratedone_reg1,
      R => RST_CPLLRESET
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => SYNC_RXSYNC_DONE,
      Q => rxsync_done_reg1,
      R => RST_CPLLRESET
    );
rxsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxsync_done_reg1,
      Q => rxsync_done_reg2,
      R => RST_CPLLRESET
    );
\rxsync_start_reg1_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => SYNC_RXSYNC_START
    );
\start_reg1_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in129_in,
      I1 => RST_DRP_START,
      O => DRP_START0130_out
    );
\sysclksel[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF3EFF00000200"
    )
        port map (
      I0 => \sysclksel[0]_i_2__3_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \sysclksel[0]_i_3__3_n_0\,
      I5 => \^rxsysclksel\(0),
      O => \sysclksel[0]_i_1__3_n_0\
    );
\sysclksel[0]_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      O => \sysclksel[0]_i_2__3_n_0\
    );
\sysclksel[0]_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      O => \sysclksel[0]_i_3__3_n_0\
    );
\sysclksel[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FFFFFFF00000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^rxsysclksel\(1),
      O => \sysclksel[1]_i_1__3_n_0\
    );
\sysclksel_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[0]_i_1__3_n_0\,
      Q => \^rxsysclksel\(0),
      R => RST_CPLLRESET
    );
\sysclksel_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[1]_i_1__3_n_0\,
      Q => \^rxsysclksel\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt[0]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__3_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(0)
    );
\txdata_wait_cnt[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__3_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(0),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(3),
      I4 => \txdata_wait_cnt_reg__0\(2),
      O => \p_0_in__0\(1)
    );
\txdata_wait_cnt[2]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AA0A0A0"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__3_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(2)
    );
\txdata_wait_cnt[3]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__3_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(3),
      O => \p_0_in__0\(3)
    );
\txdata_wait_cnt[3]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \txdata_wait_cnt[3]_i_2__3_n_0\
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \txdata_wait_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \txdata_wait_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \txdata_wait_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \txdata_wait_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\txpmareset_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5504FFFF55040000"
    )
        port map (
      I0 => \^q\(3),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => gen3_exit,
      I4 => \txpmareset_i_2__3_n_0\,
      I5 => \^gt_txpmareset064_out\,
      O => \txpmareset_i_1__3_n_0\
    );
\txpmareset_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82000400"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \txpmareset_i_2__3_n_0\
    );
txpmareset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txpmareset_i_1__3_n_0\,
      Q => \^gt_txpmareset064_out\,
      R => RST_CPLLRESET
    );
\txratedone_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \txratedone_i_2__3_n_0\,
      I2 => txratedone_reg_n_0,
      O => \txratedone_i_1__3_n_0\
    );
\txratedone_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => RST_CPLLRESET,
      O => \txratedone_i_2__3_n_0\
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txratedone_i_1__3_n_0\,
      Q => txratedone_reg_n_0,
      R => '0'
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXRATEDONE,
      Q => txratedone_reg1,
      R => RST_CPLLRESET
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => RST_CPLLRESET
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXSYNC_DONE,
      Q => txsync_done_reg1,
      R => RST_CPLLRESET
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => RST_CPLLRESET
    );
\txsync_start_reg1_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAA"
    )
        port map (
      I0 => out1(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => SYNC_TXSYNC_START
    );
\x16_reg1_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in131_in,
      I1 => RST_DRP_X16,
      O => DRP_X160132_out
    );
\x16x20_mode_reg1_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in133_in,
      I1 => RST_DRP_X16X20_MODE,
      O => DRP_X16X20_MODE0134_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_57 is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RESETOVRD_START : out STD_LOGIC;
    RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_TXSYNC_START : out STD_LOGIC;
    DRP_X16X20_MODE058_out : out STD_LOGIC;
    DRP_X16056_out : out STD_LOGIC;
    DRP_START054_out : out STD_LOGIC;
    \cplllock_reg1_reg[5]\ : out STD_LOGIC;
    rate_gen3 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[5]_0\ : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_RATE_DONE : out STD_LOGIC;
    USER_RATE_RXSYNC : out STD_LOGIC;
    SYNC_RXSYNC_START : out STD_LOGIC;
    RST_RATE_IDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    GT_TXPMARESET046_out : out STD_LOGIC;
    USER_PCLK_SEL : out STD_LOGIC;
    QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in47_in : out STD_LOGIC;
    QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in49_in : out STD_LOGIC;
    out1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RST_DRP_X16X20_MODE : in STD_LOGIC;
    RST_DRP_X16 : in STD_LOGIC;
    RST_DRP_START : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg_0 : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_CPLLLOCK : in STD_LOGIC;
    RATE_QPLLLOCK : in STD_LOGIC;
    RATE_DRP_DONE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    RATE_PHYSTATUS : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    USER_RXRESETDONE : in STD_LOGIC;
    RATE_TXRATEDONE : in STD_LOGIC;
    RATE_RXRATEDONE : in STD_LOGIC;
    RATE_RESETOVRD_DONE : in STD_LOGIC;
    RATE_TXSYNC_DONE : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    p_0_in7_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_57 : entity is "PCIeGen1x8If64_pipe_rate";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_57;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_57 is
  signal \^gt_txpmareset046_out\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^user_pclk_sel\ : STD_LOGIC;
  signal cplllock_reg1 : STD_LOGIC;
  signal cplllock_reg2 : STD_LOGIC;
  signal \cpllpd_i_1__4_n_0\ : STD_LOGIC;
  signal \cpllreset_i_1__5_n_0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC;
  signal drp_done_reg2 : STD_LOGIC;
  signal \drp_start_i_1__4_n_0\ : STD_LOGIC;
  signal \drp_x16_i_1__4_n_0\ : STD_LOGIC;
  signal \drp_x16x20_mode_i_1__4_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal \fsm[0]_i_10__4_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_11__4_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_12__4_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_3__9_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_4__4_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_5__4_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_6__4_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_7__4_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_8__4_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_9__4_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_4__4_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_5__4_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_6__4_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_7__4_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_8__4_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_9__4_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_2__4_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_3__4_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_4__4_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_5__4_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_2__4_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_3__4_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_4__4_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_5__4_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_8__4_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_9__4_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_3__4_n_0\ : STD_LOGIC;
  signal \fsm_reg[0]_i_2__4_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_2__4_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_3__4_n_0\ : STD_LOGIC;
  signal gen3_exit : STD_LOGIC;
  signal \gen3_exit_i_1__4_n_0\ : STD_LOGIC;
  signal \gen3_exit_i_2__4_n_0\ : STD_LOGIC;
  signal \gen3_i_1__4_n_0\ : STD_LOGIC;
  signal \gen3_i_2__4_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^p_0_in47_in\ : STD_LOGIC;
  signal \^p_0_in49_in\ : STD_LOGIC;
  signal p_0_in53_in : STD_LOGIC;
  signal p_0_in55_in : STD_LOGIC;
  signal p_0_in57_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pclk_sel_i_1__5_n_0\ : STD_LOGIC;
  signal \pclk_sel_i_2__4_n_0\ : STD_LOGIC;
  signal \phystatus_i_1__4_n_0\ : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  signal phystatus_reg2 : STD_LOGIC;
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal pll_lock : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  signal qplllock_reg2 : STD_LOGIC;
  signal qpllpd : STD_LOGIC;
  signal \qpllpd_i_1__5_n_0\ : STD_LOGIC;
  signal qpllreset : STD_LOGIC;
  signal \qpllreset_i_1__5_n_0\ : STD_LOGIC;
  signal \^rate_gen3\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rate_out[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \rate_out[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_2__4_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_3__4_n_0\ : STD_LOGIC;
  signal \ratedone_i_1__4_n_0\ : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal resetovrd_done_reg1 : STD_LOGIC;
  signal resetovrd_done_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  signal \rxratedone_i_1__4_n_0\ : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  signal rxratedone_reg2 : STD_LOGIC;
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxsync_done_reg1 : STD_LOGIC;
  signal rxsync_done_reg2 : STD_LOGIC;
  signal \sysclksel[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_2__4_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_3__4_n_0\ : STD_LOGIC;
  signal \sysclksel[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt[3]_i_2__4_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txpmareset_i_1__4_n_0\ : STD_LOGIC;
  signal \txpmareset_i_2__4_n_0\ : STD_LOGIC;
  signal \txratedone_i_1__4_n_0\ : STD_LOGIC;
  signal \txratedone_i_2__4_n_0\ : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  signal txratedone_reg2 : STD_LOGIC;
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC;
  signal txsync_done_reg2 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of cplllock_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of cplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of cplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of cplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cpllpd_i_2__4\ : label is "soft_lutpair160";
  attribute SOFT_HLUTNM of \cpllreset_i_2__4\ : label is "soft_lutpair162";
  attribute ASYNC_REG of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \drp_start_i_1__4\ : label is "soft_lutpair156";
  attribute SOFT_HLUTNM of \drp_x16_i_1__4\ : label is "soft_lutpair164";
  attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__4\ : label is "soft_lutpair161";
  attribute SOFT_HLUTNM of \fsm[0]_i_9__4\ : label is "soft_lutpair159";
  attribute SOFT_HLUTNM of \fsm[3]_i_5__4\ : label is "soft_lutpair159";
  attribute SOFT_HLUTNM of \gen3_i_2__4\ : label is "soft_lutpair165";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \pclk_sel_i_2__4\ : label is "soft_lutpair162";
  attribute ASYNC_REG of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of pipe_rate_idle_INST_0_i_3 : label is "soft_lutpair165";
  attribute ASYNC_REG of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rate_done_reg1_i_1__4\ : label is "soft_lutpair157";
  attribute ASYNC_REG of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SOFT_HLUTNM of \rate_out[1]_i_1__4\ : label is "soft_lutpair166";
  attribute SOFT_HLUTNM of \rate_out[2]_i_1__4\ : label is "soft_lutpair166";
  attribute SOFT_HLUTNM of \rate_rxsync_reg1_i_1__4\ : label is "soft_lutpair157";
  attribute ASYNC_REG of resetovrd_done_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_done_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_start_reg1_i_1__4\ : label is "soft_lutpair156";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rxsync_start_reg1_i_1__4\ : label is "soft_lutpair161";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1__4\ : label is "soft_lutpair158";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1__4\ : label is "soft_lutpair163";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1__4\ : label is "soft_lutpair163";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1__4\ : label is "soft_lutpair158";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2__4\ : label is "soft_lutpair160";
  attribute SOFT_HLUTNM of \txpmareset_i_2__4\ : label is "soft_lutpair164";
  attribute ASYNC_REG of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
begin
  GT_TXPMARESET046_out <= \^gt_txpmareset046_out\;
  Q(4 downto 0) <= \^q\(4 downto 0);
  QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0);
  QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0);
  RXRATE(2 downto 0) <= \^rxrate\(2 downto 0);
  RXSYSCLKSEL(1 downto 0) <= \^rxsysclksel\(1 downto 0);
  USER_PCLK_SEL <= \^user_pclk_sel\;
  p_0_in47_in <= \^p_0_in47_in\;
  p_0_in49_in <= \^p_0_in49_in\;
  rate_gen3(0) <= \^rate_gen3\(0);
cplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_CPLLLOCK,
      Q => cplllock_reg1,
      R => RST_CPLLRESET
    );
cplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => cplllock_reg1,
      Q => cplllock_reg2,
      R => RST_CPLLRESET
    );
\cpllpd_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^p_0_in49_in\,
      O => \cpllpd_i_1__4_n_0\
    );
\cpllpd_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000084"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(0),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => qpllpd
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllpd_i_1__4_n_0\,
      Q => \^p_0_in49_in\,
      R => RST_CPLLRESET
    );
\cpllreset_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^p_0_in47_in\,
      O => \cpllreset_i_1__5_n_0\
    );
\cpllreset_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"81000002"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => qpllreset
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllreset_i_1__5_n_0\,
      Q => \^p_0_in47_in\,
      R => RST_CPLLRESET
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_DRP_DONE,
      Q => drp_done_reg1,
      R => RST_CPLLRESET
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => RST_CPLLRESET
    );
\drp_start_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08200108"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => \^q\(1),
      O => \drp_start_i_1__4_n_0\
    );
drp_start_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_start_i_1__4_n_0\,
      Q => p_0_in53_in,
      R => RST_CPLLRESET
    );
\drp_x16_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20020006"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(4),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(0),
      O => \drp_x16_i_1__4_n_0\
    );
drp_x16_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16_i_1__4_n_0\,
      Q => p_0_in55_in,
      R => RST_CPLLRESET
    );
\drp_x16x20_mode_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20001584"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => \drp_x16x20_mode_i_1__4_n_0\
    );
drp_x16x20_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16x20_mode_i_1__4_n_0\,
      Q => p_0_in57_in,
      R => RST_CPLLRESET
    );
\fsm[0]_i_10__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \txdata_wait_cnt_reg__0\(3),
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(0),
      I3 => \txdata_wait_cnt_reg__0\(1),
      O => \fsm[0]_i_10__4_n_0\
    );
\fsm[0]_i_11__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F404"
    )
        port map (
      I0 => rxpmaresetdone_reg2,
      I1 => mmcm_lock_reg2,
      I2 => \^q\(0),
      I3 => drp_done_reg2,
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \fsm[0]_i_11__4_n_0\
    );
\fsm[0]_i_12__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F737F4343404C"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => rxpmaresetdone_reg2,
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[0]_i_12__4_n_0\
    );
\fsm[0]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBB88888BBB8BBB8"
    )
        port map (
      I0 => \fsm_reg[0]_i_2__4_n_0\,
      I1 => \^q\(4),
      I2 => \fsm[0]_i_3__9_n_0\,
      I3 => \^q\(3),
      I4 => \fsm[0]_i_4__4_n_0\,
      I5 => \fsm[0]_i_5__4_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_3__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0344FF440344FF77"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => pll_lock,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \fsm[3]_i_9__4_n_0\,
      O => \fsm[0]_i_3__9_n_0\
    );
\fsm[0]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0000000F800F000"
    )
        port map (
      I0 => pll_lock,
      I1 => rst_idle_reg2,
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => drp_done_reg2,
      I5 => \^q\(0),
      O => \fsm[0]_i_4__4_n_0\
    );
\fsm[0]_i_5__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCC8C0C8"
    )
        port map (
      I0 => \fsm[0]_i_8__4_n_0\,
      I1 => \^q\(3),
      I2 => \fsm[0]_i_9__4_n_0\,
      I3 => \^q\(0),
      I4 => \fsm[0]_i_10__4_n_0\,
      I5 => \fsm[0]_i_11__4_n_0\,
      O => \fsm[0]_i_5__4_n_0\
    );
\fsm[0]_i_6__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0040"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \fsm[0]_i_12__4_n_0\,
      O => \fsm[0]_i_6__4_n_0\
    );
\fsm[0]_i_7__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03880333"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[0]_i_7__4_n_0\
    );
\fsm[0]_i_8__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77770777"
    )
        port map (
      I0 => p_0_in7_in,
      I1 => p_1_in8_in,
      I2 => rxresetdone_reg2,
      I3 => txresetdone_reg2,
      I4 => phystatus_reg2,
      O => \fsm[0]_i_8__4_n_0\
    );
\fsm[0]_i_9__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      O => \fsm[0]_i_9__4_n_0\
    );
\fsm[1]_i_4__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BBFC00"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_8__4_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_4__4_n_0\
    );
\fsm[1]_i_5__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC88300000BB3000"
    )
        port map (
      I0 => \fsm[0]_i_10__4_n_0\,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_9__4_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[1]_i_5__4_n_0\
    );
\fsm[1]_i_6__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70F040F0"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => drp_done_reg2,
      O => \fsm[1]_i_6__4_n_0\
    );
\fsm[1]_i_7__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03777700"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_7__4_n_0\
    );
\fsm[1]_i_8__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"53F5FFFFFFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => qplllock_reg2,
      I2 => rate_in_reg2(0),
      I3 => rate_in_reg2(1),
      I4 => rst_idle_reg2,
      I5 => \^q\(0),
      O => \fsm[1]_i_8__4_n_0\
    );
\fsm[1]_i_9__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF4575FFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      I3 => qplllock_reg2,
      I4 => rst_idle_reg2,
      I5 => drp_done_reg2,
      O => \fsm[1]_i_9__4_n_0\
    );
\fsm[2]_i_1__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fsm[2]_i_2__4_n_0\,
      I1 => \fsm[2]_i_3__4_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[2]_i_4__4_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[2]_i_5__4_n_0\,
      O => fsm(2)
    );
\fsm[2]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3C0C4040"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_done_reg2,
      I4 => \^q\(0),
      O => \fsm[2]_i_2__4_n_0\
    );
\fsm[2]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13CCD3CC1FCCDFCC"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => resetovrd_done_reg2,
      I5 => fsm1,
      O => \fsm[2]_i_3__4_n_0\
    );
\fsm[2]_i_4__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BC0C"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \fsm[2]_i_4__4_n_0\
    );
\fsm[2]_i_5__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4A4A4A4AAAAFAAAA"
    )
        port map (
      I0 => \^q\(2),
      I1 => pll_lock,
      I2 => \^q\(1),
      I3 => \fsm[3]_i_9__4_n_0\,
      I4 => \fsm[3]_i_8__4_n_0\,
      I5 => \^q\(0),
      O => \fsm[2]_i_5__4_n_0\
    );
\fsm[3]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFE0EFEFEFE0E0E0"
    )
        port map (
      I0 => \fsm[3]_i_2__4_n_0\,
      I1 => \fsm[3]_i_3__4_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[3]_i_4__4_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[3]_i_5__4_n_0\,
      O => fsm(3)
    );
\fsm[3]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22AA2A22"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => rxsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[3]_i_2__4_n_0\
    );
\fsm[3]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3020002000000000"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => resetovrd_done_reg2,
      I5 => \^q\(0),
      O => \fsm[3]_i_3__4_n_0\
    );
\fsm[3]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F545F555FFFFFFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rst_idle_reg2,
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => pll_lock,
      I5 => \^q\(1),
      O => \fsm[3]_i_4__4_n_0\
    );
\fsm[3]_i_5__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80808180"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \fsm[3]_i_8__4_n_0\,
      I4 => \fsm[3]_i_9__4_n_0\,
      O => \fsm[3]_i_5__4_n_0\
    );
\fsm[3]_i_6__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF8F8FFF8"
    )
        port map (
      I0 => p_1_in8_in,
      I1 => p_0_in7_in,
      I2 => ratedone_reg_n_0,
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg2(0),
      I5 => gen3_exit,
      O => fsm1
    );
\fsm[3]_i_7__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => cplllock_reg2,
      O => pll_lock
    );
\fsm[3]_i_8__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg1(1),
      O => \fsm[3]_i_8__4_n_0\
    );
\fsm[3]_i_9__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rate_in_reg1(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(1),
      I3 => rate_in_reg2(1),
      O => \fsm[3]_i_9__4_n_0\
    );
\fsm[4]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08880000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \fsm[4]_i_2__4_n_0\
    );
\fsm[4]_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5F75FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rxsync_done_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \fsm[4]_i_3__4_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\fsm_reg[0]_i_2__4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[0]_i_6__4_n_0\,
      I1 => \fsm[0]_i_7__4_n_0\,
      O => \fsm_reg[0]_i_2__4_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      S => RST_CPLLRESET
    );
\fsm_reg[1]_i_1__4\: unisim.vcomponents.MUXF8
     port map (
      I0 => \fsm_reg[1]_i_2__4_n_0\,
      I1 => \fsm_reg[1]_i_3__4_n_0\,
      O => fsm(1),
      S => \^q\(4)
    );
\fsm_reg[1]_i_2__4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_4__4_n_0\,
      I1 => \fsm[1]_i_5__4_n_0\,
      O => \fsm_reg[1]_i_2__4_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]_i_3__4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_6__4_n_0\,
      I1 => \fsm[1]_i_7__4_n_0\,
      O => \fsm_reg[1]_i_3__4_n_0\,
      S => \^q\(3)
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\fsm_reg[4]_i_1__4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[4]_i_2__4_n_0\,
      I1 => \fsm[4]_i_3__4_n_0\,
      O => fsm(4),
      S => \^q\(4)
    );
\gen3_exit_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_exit_i_2__4_n_0\,
      I4 => gen3_exit,
      O => \gen3_exit_i_1__4_n_0\
    );
\gen3_exit_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000000000001"
    )
        port map (
      I0 => \fsm[3]_i_9__4_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => \gen3_exit_i_2__4_n_0\
    );
gen3_exit_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_exit_i_1__4_n_0\,
      Q => gen3_exit,
      R => RST_CPLLRESET
    );
\gen3_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_i_2__4_n_0\,
      I4 => \^rate_gen3\(0),
      O => \gen3_i_1__4_n_0\
    );
\gen3_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000008"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(1),
      O => \gen3_i_2__4_n_0\
    );
gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_i_1__4_n_0\,
      Q => \^rate_gen3\(0),
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_6__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[5]_0\
    );
\gtx_channel.gtxe2_channel_i_i_7__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[5]\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
\pclk_sel_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06FF0600"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \pclk_sel_i_2__4_n_0\,
      I4 => \^user_pclk_sel\,
      O => \pclk_sel_i_1__5_n_0\
    );
\pclk_sel_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80040800"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \pclk_sel_i_2__4_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pclk_sel_i_1__5_n_0\,
      Q => \^user_pclk_sel\,
      R => RST_CPLLRESET
    );
\phystatus_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \txratedone_i_2__4_n_0\,
      I2 => phystatus_reg_n_0,
      O => \phystatus_i_1__4_n_0\
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \phystatus_i_1__4_n_0\,
      Q => phystatus_reg_n_0,
      R => '0'
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_PHYSTATUS,
      Q => phystatus_reg1,
      R => RST_CPLLRESET
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => RST_CPLLRESET
    );
pipe_rate_idle_INST_0_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => RST_RATE_IDLE(0)
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_QPLLLOCK,
      Q => qplllock_reg1,
      R => RST_CPLLRESET
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => RST_CPLLRESET
    );
\qpllpd_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^qrst_qpllpd_in\(0),
      O => \qpllpd_i_1__5_n_0\
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllpd_i_1__5_n_0\,
      Q => \^qrst_qpllpd_in\(0),
      R => RST_CPLLRESET
    );
\qpllreset_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^qrst_qpllreset_in\(0),
      O => \qpllreset_i_1__5_n_0\
    );
qpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllreset_i_1__5_n_0\,
      Q => \^qrst_qpllreset_in\(0),
      R => RST_CPLLRESET
    );
\rate_done_reg1_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => USER_RATE_DONE
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_in_reg1(0),
      R => RST_CPLLRESET
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => RST_CPLLRESET
    );
\rate_out[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      I2 => \^q\(1),
      I3 => \rate_out[2]_i_2__4_n_0\,
      I4 => \^rxrate\(0),
      O => \rate_out[0]_i_1__4_n_0\
    );
\rate_out[1]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__4_n_0\,
      I1 => \^rxrate\(1),
      O => \rate_out[1]_i_1__4_n_0\
    );
\rate_out[2]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__4_n_0\,
      I1 => \^rxrate\(2),
      O => \rate_out[2]_i_1__4_n_0\
    );
\rate_out[2]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000002080000220"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \rate_out[2]_i_3__4_n_0\,
      O => \rate_out[2]_i_2__4_n_0\
    );
\rate_out[2]_i_3__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => gen3_exit,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      O => \rate_out[2]_i_3__4_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[0]_i_1__4_n_0\,
      Q => \^rxrate\(0),
      R => RST_CPLLRESET
    );
\rate_out_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[1]_i_1__4_n_0\,
      Q => \^rxrate\(1),
      R => RST_CPLLRESET
    );
\rate_out_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[2]_i_1__4_n_0\,
      Q => \^rxrate\(2),
      R => RST_CPLLRESET
    );
\rate_rxsync_reg1_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => USER_RATE_RXSYNC
    );
\ratedone_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF008000"
    )
        port map (
      I0 => rxratedone_reg_n_0,
      I1 => txratedone_reg_n_0,
      I2 => phystatus_reg_n_0,
      I3 => \txratedone_i_2__4_n_0\,
      I4 => ratedone_reg_n_0,
      O => \ratedone_i_1__4_n_0\
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \ratedone_i_1__4_n_0\,
      Q => ratedone_reg_n_0,
      R => '0'
    );
resetovrd_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RESETOVRD_DONE,
      Q => resetovrd_done_reg1,
      R => RST_CPLLRESET
    );
resetovrd_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => resetovrd_done_reg1,
      Q => resetovrd_done_reg2,
      R => RST_CPLLRESET
    );
\resetovrd_start_reg1_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(4),
      I4 => \^q\(2),
      O => USER_RESETOVRD_START
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => out1(1),
      Q => rst_idle_reg1,
      R => RST_CPLLRESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => RST_CPLLRESET
    );
\rxratedone_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \txratedone_i_2__4_n_0\,
      I2 => rxratedone_reg_n_0,
      O => \rxratedone_i_1__4_n_0\
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rxratedone_i_1__4_n_0\,
      Q => rxratedone_reg_n_0,
      R => '0'
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RXRATEDONE,
      Q => rxratedone_reg1,
      R => RST_CPLLRESET
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => SYNC_RXSYNC_DONE,
      Q => rxsync_done_reg1,
      R => RST_CPLLRESET
    );
rxsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxsync_done_reg1,
      Q => rxsync_done_reg2,
      R => RST_CPLLRESET
    );
\rxsync_start_reg1_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => SYNC_RXSYNC_START
    );
\start_reg1_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in53_in,
      I1 => RST_DRP_START,
      O => DRP_START054_out
    );
\sysclksel[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF3EFF00000200"
    )
        port map (
      I0 => \sysclksel[0]_i_2__4_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \sysclksel[0]_i_3__4_n_0\,
      I5 => \^rxsysclksel\(0),
      O => \sysclksel[0]_i_1__4_n_0\
    );
\sysclksel[0]_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      O => \sysclksel[0]_i_2__4_n_0\
    );
\sysclksel[0]_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      O => \sysclksel[0]_i_3__4_n_0\
    );
\sysclksel[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FFFFFFF00000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^rxsysclksel\(1),
      O => \sysclksel[1]_i_1__4_n_0\
    );
\sysclksel_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[0]_i_1__4_n_0\,
      Q => \^rxsysclksel\(0),
      R => RST_CPLLRESET
    );
\sysclksel_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[1]_i_1__4_n_0\,
      Q => \^rxsysclksel\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__4_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(0)
    );
\txdata_wait_cnt[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__4_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(0),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(3),
      I4 => \txdata_wait_cnt_reg__0\(2),
      O => \p_0_in__0\(1)
    );
\txdata_wait_cnt[2]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AA0A0A0"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__4_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(2)
    );
\txdata_wait_cnt[3]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__4_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(3),
      O => \p_0_in__0\(3)
    );
\txdata_wait_cnt[3]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \txdata_wait_cnt[3]_i_2__4_n_0\
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \txdata_wait_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \txdata_wait_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \txdata_wait_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \txdata_wait_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\txpmareset_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5504FFFF55040000"
    )
        port map (
      I0 => \^q\(3),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => gen3_exit,
      I4 => \txpmareset_i_2__4_n_0\,
      I5 => \^gt_txpmareset046_out\,
      O => \txpmareset_i_1__4_n_0\
    );
\txpmareset_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82000400"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \txpmareset_i_2__4_n_0\
    );
txpmareset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txpmareset_i_1__4_n_0\,
      Q => \^gt_txpmareset046_out\,
      R => RST_CPLLRESET
    );
\txratedone_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \txratedone_i_2__4_n_0\,
      I2 => txratedone_reg_n_0,
      O => \txratedone_i_1__4_n_0\
    );
\txratedone_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => RST_CPLLRESET,
      O => \txratedone_i_2__4_n_0\
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txratedone_i_1__4_n_0\,
      Q => txratedone_reg_n_0,
      R => '0'
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXRATEDONE,
      Q => txratedone_reg1,
      R => RST_CPLLRESET
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => RST_CPLLRESET
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXSYNC_DONE,
      Q => txsync_done_reg1,
      R => RST_CPLLRESET
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => RST_CPLLRESET
    );
\txsync_start_reg1_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAA"
    )
        port map (
      I0 => out1(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => SYNC_TXSYNC_START
    );
\x16_reg1_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in55_in,
      I1 => RST_DRP_X16,
      O => DRP_X16056_out
    );
\x16x20_mode_reg1_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in57_in,
      I1 => RST_DRP_X16X20_MODE,
      O => DRP_X16X20_MODE058_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_63 is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RESETOVRD_START : out STD_LOGIC;
    RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_TXSYNC_START : out STD_LOGIC;
    DRP_X16X20_MODE029_out : out STD_LOGIC;
    DRP_X16027_out : out STD_LOGIC;
    DRP_START025_out : out STD_LOGIC;
    \cplllock_reg1_reg[6]\ : out STD_LOGIC;
    rate_gen3 : out STD_LOGIC_VECTOR ( 0 to 0 );
    gen3_reg1_reg : out STD_LOGIC;
    \cplllock_reg1_reg[6]_0\ : out STD_LOGIC;
    pipe_rate_idle : out STD_LOGIC;
    \rate_idle_reg1_reg[6]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    RXRATE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_RATE_DONE : out STD_LOGIC;
    USER_RATE_RXSYNC : out STD_LOGIC;
    SYNC_RXSYNC_START : out STD_LOGIC;
    GT_TXPMARESET035_out : out STD_LOGIC;
    USER_PCLK_SEL : out STD_LOGIC;
    QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in36_in : out STD_LOGIC;
    QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in38_in : out STD_LOGIC;
    out1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RST_DRP_X16X20_MODE : in STD_LOGIC;
    RST_DRP_X16 : in STD_LOGIC;
    RST_DRP_START : in STD_LOGIC;
    gen3_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
    gen3_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 6 downto 0 );
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg_0 : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_CPLLLOCK : in STD_LOGIC;
    RATE_QPLLLOCK : in STD_LOGIC;
    RATE_DRP_DONE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    RATE_PHYSTATUS : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    USER_RXRESETDONE : in STD_LOGIC;
    RATE_TXRATEDONE : in STD_LOGIC;
    RATE_RXRATEDONE : in STD_LOGIC;
    RATE_RESETOVRD_DONE : in STD_LOGIC;
    RATE_TXSYNC_DONE : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    p_0_in7_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_63 : entity is "PCIeGen1x8If64_pipe_rate";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_63;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_63 is
  signal \^gt_txpmareset035_out\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^user_pclk_sel\ : STD_LOGIC;
  signal cplllock_reg1 : STD_LOGIC;
  signal cplllock_reg2 : STD_LOGIC;
  signal \cpllpd_i_1__5_n_0\ : STD_LOGIC;
  signal \cpllreset_i_1__6_n_0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC;
  signal drp_done_reg2 : STD_LOGIC;
  signal \drp_start_i_1__5_n_0\ : STD_LOGIC;
  signal \drp_x16_i_1__5_n_0\ : STD_LOGIC;
  signal \drp_x16x20_mode_i_1__5_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal \fsm[0]_i_10__5_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_11__5_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_12__5_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_3__11_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_4__5_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_5__5_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_6__5_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_7__5_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_8__5_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_9__5_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_4__5_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_5__5_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_6__5_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_7__5_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_8__5_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_9__5_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_2__5_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_3__5_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_4__5_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_5__5_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_2__5_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_3__5_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_4__5_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_5__5_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_8__5_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_9__5_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_3__5_n_0\ : STD_LOGIC;
  signal \fsm_reg[0]_i_2__5_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_2__5_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_3__5_n_0\ : STD_LOGIC;
  signal gen3_exit : STD_LOGIC;
  signal \gen3_exit_i_1__5_n_0\ : STD_LOGIC;
  signal \gen3_exit_i_2__5_n_0\ : STD_LOGIC;
  signal \gen3_i_1__5_n_0\ : STD_LOGIC;
  signal \gen3_i_2__5_n_0\ : STD_LOGIC;
  signal gen3_reg1_i_2_n_0 : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal p_0_in24_in : STD_LOGIC;
  signal p_0_in26_in : STD_LOGIC;
  signal p_0_in28_in : STD_LOGIC;
  signal \^p_0_in36_in\ : STD_LOGIC;
  signal \^p_0_in38_in\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pclk_sel_i_1__6_n_0\ : STD_LOGIC;
  signal \pclk_sel_i_2__5_n_0\ : STD_LOGIC;
  signal \phystatus_i_1__5_n_0\ : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  signal phystatus_reg2 : STD_LOGIC;
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal pipe_rate_idle_INST_0_i_1_n_0 : STD_LOGIC;
  signal pll_lock : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  signal qplllock_reg2 : STD_LOGIC;
  signal qpllpd : STD_LOGIC;
  signal \qpllpd_i_1__6_n_0\ : STD_LOGIC;
  signal qpllreset : STD_LOGIC;
  signal \qpllreset_i_1__6_n_0\ : STD_LOGIC;
  signal \^rate_gen3\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rate_idle_reg1_reg[6]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rate_out[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \rate_out[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_2__5_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_3__5_n_0\ : STD_LOGIC;
  signal \ratedone_i_1__5_n_0\ : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal resetovrd_done_reg1 : STD_LOGIC;
  signal resetovrd_done_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  signal \rxratedone_i_1__5_n_0\ : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  signal rxratedone_reg2 : STD_LOGIC;
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxsync_done_reg1 : STD_LOGIC;
  signal rxsync_done_reg2 : STD_LOGIC;
  signal \sysclksel[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_2__5_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_3__5_n_0\ : STD_LOGIC;
  signal \sysclksel[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt[3]_i_2__5_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txpmareset_i_1__5_n_0\ : STD_LOGIC;
  signal \txpmareset_i_2__5_n_0\ : STD_LOGIC;
  signal \txratedone_i_1__5_n_0\ : STD_LOGIC;
  signal \txratedone_i_2__5_n_0\ : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  signal txratedone_reg2 : STD_LOGIC;
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC;
  signal txsync_done_reg2 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of cplllock_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of cplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of cplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of cplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cpllpd_i_2__5\ : label is "soft_lutpair179";
  attribute SOFT_HLUTNM of \cpllreset_i_2__5\ : label is "soft_lutpair181";
  attribute ASYNC_REG of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \drp_start_i_1__5\ : label is "soft_lutpair180";
  attribute SOFT_HLUTNM of \drp_x16_i_1__5\ : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__5\ : label is "soft_lutpair186";
  attribute SOFT_HLUTNM of \fsm[0]_i_9__5\ : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of \fsm[3]_i_5__5\ : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of \gen3_i_2__5\ : label is "soft_lutpair180";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \pclk_sel_i_2__5\ : label is "soft_lutpair186";
  attribute ASYNC_REG of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rate_done_reg1_i_1__5\ : label is "soft_lutpair181";
  attribute SOFT_HLUTNM of \rate_idle_reg1[6]_i_1\ : label is "soft_lutpair183";
  attribute ASYNC_REG of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SOFT_HLUTNM of \rate_out[1]_i_1__5\ : label is "soft_lutpair188";
  attribute SOFT_HLUTNM of \rate_out[2]_i_1__5\ : label is "soft_lutpair188";
  attribute SOFT_HLUTNM of \rate_rxsync_reg1_i_1__5\ : label is "soft_lutpair183";
  attribute ASYNC_REG of resetovrd_done_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_done_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_start_reg1_i_1__5\ : label is "soft_lutpair179";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rxsync_start_reg1_i_1__5\ : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1__5\ : label is "soft_lutpair178";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1__5\ : label is "soft_lutpair187";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1__5\ : label is "soft_lutpair187";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1__5\ : label is "soft_lutpair178";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2__5\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of \txpmareset_i_2__5\ : label is "soft_lutpair182";
  attribute ASYNC_REG of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
begin
  GT_TXPMARESET035_out <= \^gt_txpmareset035_out\;
  Q(4 downto 0) <= \^q\(4 downto 0);
  QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0);
  QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0);
  RXRATE(2 downto 0) <= \^rxrate\(2 downto 0);
  RXSYSCLKSEL(1 downto 0) <= \^rxsysclksel\(1 downto 0);
  USER_PCLK_SEL <= \^user_pclk_sel\;
  p_0_in36_in <= \^p_0_in36_in\;
  p_0_in38_in <= \^p_0_in38_in\;
  rate_gen3(0) <= \^rate_gen3\(0);
  \rate_idle_reg1_reg[6]\(0) <= \^rate_idle_reg1_reg[6]\(0);
cplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_CPLLLOCK,
      Q => cplllock_reg1,
      R => RST_CPLLRESET
    );
cplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => cplllock_reg1,
      Q => cplllock_reg2,
      R => RST_CPLLRESET
    );
\cpllpd_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^p_0_in38_in\,
      O => \cpllpd_i_1__5_n_0\
    );
\cpllpd_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000084"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(0),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => qpllpd
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllpd_i_1__5_n_0\,
      Q => \^p_0_in38_in\,
      R => RST_CPLLRESET
    );
\cpllreset_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^p_0_in36_in\,
      O => \cpllreset_i_1__6_n_0\
    );
\cpllreset_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"81000002"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => qpllreset
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllreset_i_1__6_n_0\,
      Q => \^p_0_in36_in\,
      R => RST_CPLLRESET
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_DRP_DONE,
      Q => drp_done_reg1,
      R => RST_CPLLRESET
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => RST_CPLLRESET
    );
\drp_start_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08200108"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => \^q\(1),
      O => \drp_start_i_1__5_n_0\
    );
drp_start_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_start_i_1__5_n_0\,
      Q => p_0_in24_in,
      R => RST_CPLLRESET
    );
\drp_x16_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20020006"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(4),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(0),
      O => \drp_x16_i_1__5_n_0\
    );
drp_x16_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16_i_1__5_n_0\,
      Q => p_0_in26_in,
      R => RST_CPLLRESET
    );
\drp_x16x20_mode_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20001584"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => \drp_x16x20_mode_i_1__5_n_0\
    );
drp_x16x20_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16x20_mode_i_1__5_n_0\,
      Q => p_0_in28_in,
      R => RST_CPLLRESET
    );
\fsm[0]_i_10__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \txdata_wait_cnt_reg__0\(3),
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(0),
      I3 => \txdata_wait_cnt_reg__0\(1),
      O => \fsm[0]_i_10__5_n_0\
    );
\fsm[0]_i_11__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F404"
    )
        port map (
      I0 => rxpmaresetdone_reg2,
      I1 => mmcm_lock_reg2,
      I2 => \^q\(0),
      I3 => drp_done_reg2,
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \fsm[0]_i_11__5_n_0\
    );
\fsm[0]_i_12__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F737F4343404C"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => rxpmaresetdone_reg2,
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[0]_i_12__5_n_0\
    );
\fsm[0]_i_1__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBB88888BBB8BBB8"
    )
        port map (
      I0 => \fsm_reg[0]_i_2__5_n_0\,
      I1 => \^q\(4),
      I2 => \fsm[0]_i_3__11_n_0\,
      I3 => \^q\(3),
      I4 => \fsm[0]_i_4__5_n_0\,
      I5 => \fsm[0]_i_5__5_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_3__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0344FF440344FF77"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => pll_lock,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \fsm[3]_i_9__5_n_0\,
      O => \fsm[0]_i_3__11_n_0\
    );
\fsm[0]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0000000F800F000"
    )
        port map (
      I0 => pll_lock,
      I1 => rst_idle_reg2,
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => drp_done_reg2,
      I5 => \^q\(0),
      O => \fsm[0]_i_4__5_n_0\
    );
\fsm[0]_i_5__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCC8C0C8"
    )
        port map (
      I0 => \fsm[0]_i_8__5_n_0\,
      I1 => \^q\(3),
      I2 => \fsm[0]_i_9__5_n_0\,
      I3 => \^q\(0),
      I4 => \fsm[0]_i_10__5_n_0\,
      I5 => \fsm[0]_i_11__5_n_0\,
      O => \fsm[0]_i_5__5_n_0\
    );
\fsm[0]_i_6__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0040"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \fsm[0]_i_12__5_n_0\,
      O => \fsm[0]_i_6__5_n_0\
    );
\fsm[0]_i_7__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03880333"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[0]_i_7__5_n_0\
    );
\fsm[0]_i_8__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77770777"
    )
        port map (
      I0 => p_0_in7_in,
      I1 => p_1_in8_in,
      I2 => rxresetdone_reg2,
      I3 => txresetdone_reg2,
      I4 => phystatus_reg2,
      O => \fsm[0]_i_8__5_n_0\
    );
\fsm[0]_i_9__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      O => \fsm[0]_i_9__5_n_0\
    );
\fsm[1]_i_4__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BBFC00"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_8__5_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_4__5_n_0\
    );
\fsm[1]_i_5__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC88300000BB3000"
    )
        port map (
      I0 => \fsm[0]_i_10__5_n_0\,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_9__5_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[1]_i_5__5_n_0\
    );
\fsm[1]_i_6__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70F040F0"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => drp_done_reg2,
      O => \fsm[1]_i_6__5_n_0\
    );
\fsm[1]_i_7__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03777700"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_7__5_n_0\
    );
\fsm[1]_i_8__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"53F5FFFFFFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => qplllock_reg2,
      I2 => rate_in_reg2(0),
      I3 => rate_in_reg2(1),
      I4 => rst_idle_reg2,
      I5 => \^q\(0),
      O => \fsm[1]_i_8__5_n_0\
    );
\fsm[1]_i_9__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF4575FFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      I3 => qplllock_reg2,
      I4 => rst_idle_reg2,
      I5 => drp_done_reg2,
      O => \fsm[1]_i_9__5_n_0\
    );
\fsm[2]_i_1__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fsm[2]_i_2__5_n_0\,
      I1 => \fsm[2]_i_3__5_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[2]_i_4__5_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[2]_i_5__5_n_0\,
      O => fsm(2)
    );
\fsm[2]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3C0C4040"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_done_reg2,
      I4 => \^q\(0),
      O => \fsm[2]_i_2__5_n_0\
    );
\fsm[2]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13CCD3CC1FCCDFCC"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => resetovrd_done_reg2,
      I5 => fsm1,
      O => \fsm[2]_i_3__5_n_0\
    );
\fsm[2]_i_4__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BC0C"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \fsm[2]_i_4__5_n_0\
    );
\fsm[2]_i_5__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4A4A4A4AAAAFAAAA"
    )
        port map (
      I0 => \^q\(2),
      I1 => pll_lock,
      I2 => \^q\(1),
      I3 => \fsm[3]_i_9__5_n_0\,
      I4 => \fsm[3]_i_8__5_n_0\,
      I5 => \^q\(0),
      O => \fsm[2]_i_5__5_n_0\
    );
\fsm[3]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFE0EFEFEFE0E0E0"
    )
        port map (
      I0 => \fsm[3]_i_2__5_n_0\,
      I1 => \fsm[3]_i_3__5_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[3]_i_4__5_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[3]_i_5__5_n_0\,
      O => fsm(3)
    );
\fsm[3]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22AA2A22"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => rxsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[3]_i_2__5_n_0\
    );
\fsm[3]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3020002000000000"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => resetovrd_done_reg2,
      I5 => \^q\(0),
      O => \fsm[3]_i_3__5_n_0\
    );
\fsm[3]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F545F555FFFFFFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rst_idle_reg2,
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => pll_lock,
      I5 => \^q\(1),
      O => \fsm[3]_i_4__5_n_0\
    );
\fsm[3]_i_5__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80808180"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \fsm[3]_i_8__5_n_0\,
      I4 => \fsm[3]_i_9__5_n_0\,
      O => \fsm[3]_i_5__5_n_0\
    );
\fsm[3]_i_6__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF8F8FFF8"
    )
        port map (
      I0 => p_1_in8_in,
      I1 => p_0_in7_in,
      I2 => ratedone_reg_n_0,
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg2(0),
      I5 => gen3_exit,
      O => fsm1
    );
\fsm[3]_i_7__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => cplllock_reg2,
      O => pll_lock
    );
\fsm[3]_i_8__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg1(1),
      O => \fsm[3]_i_8__5_n_0\
    );
\fsm[3]_i_9__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rate_in_reg1(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(1),
      I3 => rate_in_reg2(1),
      O => \fsm[3]_i_9__5_n_0\
    );
\fsm[4]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08880000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \fsm[4]_i_2__5_n_0\
    );
\fsm[4]_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5F75FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rxsync_done_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \fsm[4]_i_3__5_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\fsm_reg[0]_i_2__5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[0]_i_6__5_n_0\,
      I1 => \fsm[0]_i_7__5_n_0\,
      O => \fsm_reg[0]_i_2__5_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      S => RST_CPLLRESET
    );
\fsm_reg[1]_i_1__5\: unisim.vcomponents.MUXF8
     port map (
      I0 => \fsm_reg[1]_i_2__5_n_0\,
      I1 => \fsm_reg[1]_i_3__5_n_0\,
      O => fsm(1),
      S => \^q\(4)
    );
\fsm_reg[1]_i_2__5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_4__5_n_0\,
      I1 => \fsm[1]_i_5__5_n_0\,
      O => \fsm_reg[1]_i_2__5_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]_i_3__5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_6__5_n_0\,
      I1 => \fsm[1]_i_7__5_n_0\,
      O => \fsm_reg[1]_i_3__5_n_0\,
      S => \^q\(3)
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\fsm_reg[4]_i_1__5\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[4]_i_2__5_n_0\,
      I1 => \fsm[4]_i_3__5_n_0\,
      O => fsm(4),
      S => \^q\(4)
    );
\gen3_exit_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_exit_i_2__5_n_0\,
      I4 => gen3_exit,
      O => \gen3_exit_i_1__5_n_0\
    );
\gen3_exit_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000000000001"
    )
        port map (
      I0 => \fsm[3]_i_9__5_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => \gen3_exit_i_2__5_n_0\
    );
gen3_exit_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_exit_i_1__5_n_0\,
      Q => gen3_exit,
      R => RST_CPLLRESET
    );
\gen3_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_i_2__5_n_0\,
      I4 => \^rate_gen3\(0),
      O => \gen3_i_1__5_n_0\
    );
\gen3_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000008"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(1),
      O => \gen3_i_2__5_n_0\
    );
gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_i_1__5_n_0\,
      Q => \^rate_gen3\(0),
      R => RST_CPLLRESET
    );
gen3_reg1_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => gen3_reg1_i_2_n_0,
      I1 => gen3_reg_0(3),
      I2 => gen3_reg_0(4),
      O => gen3_reg1_reg
    );
gen3_reg1_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^rate_gen3\(0),
      I1 => gen3_reg_0(5),
      I2 => gen3_reg_0(0),
      I3 => gen3_reg_1(0),
      I4 => gen3_reg_0(2),
      I5 => gen3_reg_0(1),
      O => gen3_reg1_i_2_n_0
    );
\gtx_channel.gtxe2_channel_i_i_6__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[6]_0\
    );
\gtx_channel.gtxe2_channel_i_i_7__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3\(0),
      O => \cplllock_reg1_reg[6]\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
\pclk_sel_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06FF0600"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \pclk_sel_i_2__5_n_0\,
      I4 => \^user_pclk_sel\,
      O => \pclk_sel_i_1__6_n_0\
    );
\pclk_sel_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80040800"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \pclk_sel_i_2__5_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pclk_sel_i_1__6_n_0\,
      Q => \^user_pclk_sel\,
      R => RST_CPLLRESET
    );
\phystatus_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \txratedone_i_2__5_n_0\,
      I2 => phystatus_reg_n_0,
      O => \phystatus_i_1__5_n_0\
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \phystatus_i_1__5_n_0\,
      Q => phystatus_reg_n_0,
      R => '0'
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_PHYSTATUS,
      Q => phystatus_reg1,
      R => RST_CPLLRESET
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => RST_CPLLRESET
    );
pipe_rate_idle_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => pipe_rate_idle_INST_0_i_1_n_0,
      I1 => RST_RATE_IDLE(4),
      I2 => RST_RATE_IDLE(5),
      O => pipe_rate_idle
    );
pipe_rate_idle_INST_0_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^rate_idle_reg1_reg[6]\(0),
      I1 => RST_RATE_IDLE(6),
      I2 => RST_RATE_IDLE(1),
      I3 => RST_RATE_IDLE(0),
      I4 => RST_RATE_IDLE(3),
      I5 => RST_RATE_IDLE(2),
      O => pipe_rate_idle_INST_0_i_1_n_0
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_QPLLLOCK,
      Q => qplllock_reg1,
      R => RST_CPLLRESET
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => RST_CPLLRESET
    );
\qpllpd_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^qrst_qpllpd_in\(0),
      O => \qpllpd_i_1__6_n_0\
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllpd_i_1__6_n_0\,
      Q => \^qrst_qpllpd_in\(0),
      R => RST_CPLLRESET
    );
\qpllreset_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^qrst_qpllreset_in\(0),
      O => \qpllreset_i_1__6_n_0\
    );
qpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllreset_i_1__6_n_0\,
      Q => \^qrst_qpllreset_in\(0),
      R => RST_CPLLRESET
    );
\rate_done_reg1_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => USER_RATE_DONE
    );
\rate_idle_reg1[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \^rate_idle_reg1_reg[6]\(0)
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_in_reg1(0),
      R => RST_CPLLRESET
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => RST_CPLLRESET
    );
\rate_out[0]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      I2 => \^q\(1),
      I3 => \rate_out[2]_i_2__5_n_0\,
      I4 => \^rxrate\(0),
      O => \rate_out[0]_i_1__5_n_0\
    );
\rate_out[1]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__5_n_0\,
      I1 => \^rxrate\(1),
      O => \rate_out[1]_i_1__5_n_0\
    );
\rate_out[2]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__5_n_0\,
      I1 => \^rxrate\(2),
      O => \rate_out[2]_i_1__5_n_0\
    );
\rate_out[2]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000002080000220"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \rate_out[2]_i_3__5_n_0\,
      O => \rate_out[2]_i_2__5_n_0\
    );
\rate_out[2]_i_3__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => gen3_exit,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      O => \rate_out[2]_i_3__5_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[0]_i_1__5_n_0\,
      Q => \^rxrate\(0),
      R => RST_CPLLRESET
    );
\rate_out_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[1]_i_1__5_n_0\,
      Q => \^rxrate\(1),
      R => RST_CPLLRESET
    );
\rate_out_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[2]_i_1__5_n_0\,
      Q => \^rxrate\(2),
      R => RST_CPLLRESET
    );
\rate_rxsync_reg1_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => USER_RATE_RXSYNC
    );
\ratedone_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF008000"
    )
        port map (
      I0 => rxratedone_reg_n_0,
      I1 => txratedone_reg_n_0,
      I2 => phystatus_reg_n_0,
      I3 => \txratedone_i_2__5_n_0\,
      I4 => ratedone_reg_n_0,
      O => \ratedone_i_1__5_n_0\
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \ratedone_i_1__5_n_0\,
      Q => ratedone_reg_n_0,
      R => '0'
    );
resetovrd_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RESETOVRD_DONE,
      Q => resetovrd_done_reg1,
      R => RST_CPLLRESET
    );
resetovrd_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => resetovrd_done_reg1,
      Q => resetovrd_done_reg2,
      R => RST_CPLLRESET
    );
\resetovrd_start_reg1_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(4),
      I4 => \^q\(2),
      O => USER_RESETOVRD_START
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => out1(1),
      Q => rst_idle_reg1,
      R => RST_CPLLRESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => RST_CPLLRESET
    );
\rxratedone_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \txratedone_i_2__5_n_0\,
      I2 => rxratedone_reg_n_0,
      O => \rxratedone_i_1__5_n_0\
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rxratedone_i_1__5_n_0\,
      Q => rxratedone_reg_n_0,
      R => '0'
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RXRATEDONE,
      Q => rxratedone_reg1,
      R => RST_CPLLRESET
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => SYNC_RXSYNC_DONE,
      Q => rxsync_done_reg1,
      R => RST_CPLLRESET
    );
rxsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxsync_done_reg1,
      Q => rxsync_done_reg2,
      R => RST_CPLLRESET
    );
\rxsync_start_reg1_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => SYNC_RXSYNC_START
    );
\start_reg1_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in24_in,
      I1 => RST_DRP_START,
      O => DRP_START025_out
    );
\sysclksel[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF3EFF00000200"
    )
        port map (
      I0 => \sysclksel[0]_i_2__5_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \sysclksel[0]_i_3__5_n_0\,
      I5 => \^rxsysclksel\(0),
      O => \sysclksel[0]_i_1__5_n_0\
    );
\sysclksel[0]_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      O => \sysclksel[0]_i_2__5_n_0\
    );
\sysclksel[0]_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      O => \sysclksel[0]_i_3__5_n_0\
    );
\sysclksel[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FFFFFFF00000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^rxsysclksel\(1),
      O => \sysclksel[1]_i_1__5_n_0\
    );
\sysclksel_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[0]_i_1__5_n_0\,
      Q => \^rxsysclksel\(0),
      R => RST_CPLLRESET
    );
\sysclksel_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[1]_i_1__5_n_0\,
      Q => \^rxsysclksel\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt[0]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__5_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(0)
    );
\txdata_wait_cnt[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__5_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(0),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(3),
      I4 => \txdata_wait_cnt_reg__0\(2),
      O => \p_0_in__0\(1)
    );
\txdata_wait_cnt[2]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AA0A0A0"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__5_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(2)
    );
\txdata_wait_cnt[3]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__5_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(3),
      O => \p_0_in__0\(3)
    );
\txdata_wait_cnt[3]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \txdata_wait_cnt[3]_i_2__5_n_0\
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \txdata_wait_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \txdata_wait_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \txdata_wait_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \txdata_wait_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\txpmareset_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5504FFFF55040000"
    )
        port map (
      I0 => \^q\(3),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => gen3_exit,
      I4 => \txpmareset_i_2__5_n_0\,
      I5 => \^gt_txpmareset035_out\,
      O => \txpmareset_i_1__5_n_0\
    );
\txpmareset_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82000400"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \txpmareset_i_2__5_n_0\
    );
txpmareset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txpmareset_i_1__5_n_0\,
      Q => \^gt_txpmareset035_out\,
      R => RST_CPLLRESET
    );
\txratedone_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \txratedone_i_2__5_n_0\,
      I2 => txratedone_reg_n_0,
      O => \txratedone_i_1__5_n_0\
    );
\txratedone_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => RST_CPLLRESET,
      O => \txratedone_i_2__5_n_0\
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txratedone_i_1__5_n_0\,
      Q => txratedone_reg_n_0,
      R => '0'
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXRATEDONE,
      Q => txratedone_reg1,
      R => RST_CPLLRESET
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => RST_CPLLRESET
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXSYNC_DONE,
      Q => txsync_done_reg1,
      R => RST_CPLLRESET
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => RST_CPLLRESET
    );
\txsync_start_reg1_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAA"
    )
        port map (
      I0 => out1(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => SYNC_TXSYNC_START
    );
\x16_reg1_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in26_in,
      I1 => RST_DRP_X16,
      O => DRP_X16027_out
    );
\x16x20_mode_reg1_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in28_in,
      I1 => RST_DRP_X16X20_MODE,
      O => DRP_X16X20_MODE029_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_69 is
  port (
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RESETOVRD_START : out STD_LOGIC;
    RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_TXSYNC_START : out STD_LOGIC;
    DRP_X16X20_MODE0136_out : out STD_LOGIC;
    DRP_X16010_out : out STD_LOGIC;
    DRP_START08_out : out STD_LOGIC;
    \cplllock_reg1_reg[7]\ : out STD_LOGIC;
    rate_gen3_reg1_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[7]_0\ : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_RATE_DONE : out STD_LOGIC;
    USER_RATE_RXSYNC : out STD_LOGIC;
    SYNC_RXSYNC_START : out STD_LOGIC;
    SYNC_RATE_IDLE : out STD_LOGIC;
    GT_TXPMARESET017_out : out STD_LOGIC;
    USER_PCLK_SEL : out STD_LOGIC;
    QRST_QPLLRESET_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in18_in : out STD_LOGIC;
    QRST_QPLLPD_IN : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in20_in : out STD_LOGIC;
    out1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RST_DRP_X16X20_MODE : in STD_LOGIC;
    RST_DRP_X16 : in STD_LOGIC;
    RST_DRP_START : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg_0 : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_CPLLLOCK : in STD_LOGIC;
    qpllpd_reg_0 : in STD_LOGIC;
    RATE_DRP_DONE : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    RATE_PHYSTATUS : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    USER_RXRESETDONE : in STD_LOGIC;
    RATE_TXRATEDONE : in STD_LOGIC;
    RATE_RXRATEDONE : in STD_LOGIC;
    RATE_RESETOVRD_DONE : in STD_LOGIC;
    RATE_TXSYNC_DONE : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    p_0_in7_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_69 : entity is "PCIeGen1x8If64_pipe_rate";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_69;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_69 is
  signal \^gt_txpmareset017_out\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^qrst_qpllpd_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^qrst_qpllreset_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^user_pclk_sel\ : STD_LOGIC;
  signal cplllock_reg1 : STD_LOGIC;
  signal cplllock_reg2 : STD_LOGIC;
  signal \cpllpd_i_1__6_n_0\ : STD_LOGIC;
  signal \cpllreset_i_1__7_n_0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC;
  signal drp_done_reg2 : STD_LOGIC;
  signal \drp_start_i_1__6_n_0\ : STD_LOGIC;
  signal \drp_x16_i_1__6_n_0\ : STD_LOGIC;
  signal \drp_x16x20_mode_i_1__6_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal \fsm[0]_i_10__6_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_11__6_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_12__6_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_3__13_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_4__6_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_5__6_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_6__6_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_7__6_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_8__6_n_0\ : STD_LOGIC;
  signal \fsm[0]_i_9__6_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_4__6_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_5__6_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_6__6_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_7__6_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_8__6_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_9__6_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_2__6_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_3__6_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_4__6_n_0\ : STD_LOGIC;
  signal \fsm[2]_i_5__6_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_2__6_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_3__6_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_4__6_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_5__6_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_8__6_n_0\ : STD_LOGIC;
  signal \fsm[3]_i_9__6_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \fsm[4]_i_3__6_n_0\ : STD_LOGIC;
  signal \fsm_reg[0]_i_2__6_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_2__6_n_0\ : STD_LOGIC;
  signal \fsm_reg[1]_i_3__6_n_0\ : STD_LOGIC;
  signal gen3_exit : STD_LOGIC;
  signal \gen3_exit_i_1__6_n_0\ : STD_LOGIC;
  signal \gen3_exit_i_2__6_n_0\ : STD_LOGIC;
  signal \gen3_i_1__6_n_0\ : STD_LOGIC;
  signal \gen3_i_2__6_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal p_0_in135_in : STD_LOGIC;
  signal \^p_0_in18_in\ : STD_LOGIC;
  signal \^p_0_in20_in\ : STD_LOGIC;
  signal \p_0_in7_in__0\ : STD_LOGIC;
  signal p_0_in9_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pclk_sel_i_1__7_n_0\ : STD_LOGIC;
  signal \pclk_sel_i_2__6_n_0\ : STD_LOGIC;
  signal \phystatus_i_1__6_n_0\ : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  signal phystatus_reg2 : STD_LOGIC;
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal pll_lock : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  signal qplllock_reg2 : STD_LOGIC;
  signal qpllpd : STD_LOGIC;
  signal \qpllpd_i_1__7_n_0\ : STD_LOGIC;
  signal qpllreset : STD_LOGIC;
  signal \qpllreset_i_1__7_n_0\ : STD_LOGIC;
  signal \^rate_gen3_reg1_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \rate_out[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \rate_out[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_2__6_n_0\ : STD_LOGIC;
  signal \rate_out[2]_i_3__6_n_0\ : STD_LOGIC;
  signal \ratedone_i_1__6_n_0\ : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal resetovrd_done_reg1 : STD_LOGIC;
  signal resetovrd_done_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  signal \rxratedone_i_1__6_n_0\ : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  signal rxratedone_reg2 : STD_LOGIC;
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxsync_done_reg1 : STD_LOGIC;
  signal rxsync_done_reg2 : STD_LOGIC;
  signal \sysclksel[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_2__6_n_0\ : STD_LOGIC;
  signal \sysclksel[0]_i_3__6_n_0\ : STD_LOGIC;
  signal \sysclksel[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt[3]_i_2__6_n_0\ : STD_LOGIC;
  signal \txdata_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txpmareset_i_1__6_n_0\ : STD_LOGIC;
  signal \txpmareset_i_2__6_n_0\ : STD_LOGIC;
  signal \txratedone_i_1__6_n_0\ : STD_LOGIC;
  signal \txratedone_i_2__6_n_0\ : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  signal txratedone_reg2 : STD_LOGIC;
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC;
  signal txsync_done_reg2 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of cplllock_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of cplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of cplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of cplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cpllpd_i_2__6\ : label is "soft_lutpair206";
  attribute SOFT_HLUTNM of \cpllreset_i_2__6\ : label is "soft_lutpair208";
  attribute ASYNC_REG of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \drp_start_i_1__6\ : label is "soft_lutpair202";
  attribute SOFT_HLUTNM of \drp_x16_i_1__6\ : label is "soft_lutpair210";
  attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__6\ : label is "soft_lutpair207";
  attribute SOFT_HLUTNM of \fsm[0]_i_9__6\ : label is "soft_lutpair205";
  attribute SOFT_HLUTNM of \fsm[3]_i_5__6\ : label is "soft_lutpair205";
  attribute SOFT_HLUTNM of \gen3_i_2__6\ : label is "soft_lutpair211";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \pclk_sel_i_2__6\ : label is "soft_lutpair208";
  attribute ASYNC_REG of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rate_done_reg1_i_1__6\ : label is "soft_lutpair203";
  attribute SOFT_HLUTNM of \rate_idle_reg1[7]_i_1\ : label is "soft_lutpair211";
  attribute ASYNC_REG of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SOFT_HLUTNM of \rate_out[1]_i_1__6\ : label is "soft_lutpair212";
  attribute SOFT_HLUTNM of \rate_out[2]_i_1__6\ : label is "soft_lutpair212";
  attribute SOFT_HLUTNM of \rate_rxsync_reg1_i_1__6\ : label is "soft_lutpair203";
  attribute ASYNC_REG of resetovrd_done_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_done_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_start_reg1_i_1__6\ : label is "soft_lutpair202";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \rxsync_start_reg1_i_1__6\ : label is "soft_lutpair207";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1__6\ : label is "soft_lutpair204";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1__6\ : label is "soft_lutpair209";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1__6\ : label is "soft_lutpair209";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1__6\ : label is "soft_lutpair204";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_2__6\ : label is "soft_lutpair206";
  attribute SOFT_HLUTNM of \txpmareset_i_2__6\ : label is "soft_lutpair210";
  attribute ASYNC_REG of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
begin
  GT_TXPMARESET017_out <= \^gt_txpmareset017_out\;
  Q(4 downto 0) <= \^q\(4 downto 0);
  QRST_QPLLPD_IN(0) <= \^qrst_qpllpd_in\(0);
  QRST_QPLLRESET_IN(0) <= \^qrst_qpllreset_in\(0);
  RXRATE(2 downto 0) <= \^rxrate\(2 downto 0);
  RXSYSCLKSEL(1 downto 0) <= \^rxsysclksel\(1 downto 0);
  USER_PCLK_SEL <= \^user_pclk_sel\;
  p_0_in18_in <= \^p_0_in18_in\;
  p_0_in20_in <= \^p_0_in20_in\;
  rate_gen3_reg1_reg(0) <= \^rate_gen3_reg1_reg\(0);
cplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_CPLLLOCK,
      Q => cplllock_reg1,
      R => RST_CPLLRESET
    );
cplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => cplllock_reg1,
      Q => cplllock_reg2,
      R => RST_CPLLRESET
    );
\cpllpd_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^p_0_in20_in\,
      O => \cpllpd_i_1__6_n_0\
    );
\cpllpd_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000084"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(0),
      I2 => \^q\(3),
      I3 => \^q\(1),
      I4 => \^q\(2),
      O => qpllpd
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllpd_i_1__6_n_0\,
      Q => \^p_0_in20_in\,
      R => RST_CPLLRESET
    );
\cpllreset_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^p_0_in18_in\,
      O => \cpllreset_i_1__7_n_0\
    );
\cpllreset_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"81000002"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => qpllreset
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \cpllreset_i_1__7_n_0\,
      Q => \^p_0_in18_in\,
      R => RST_CPLLRESET
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_DRP_DONE,
      Q => drp_done_reg1,
      R => RST_CPLLRESET
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => RST_CPLLRESET
    );
\drp_start_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08200108"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => \^q\(1),
      O => \drp_start_i_1__6_n_0\
    );
drp_start_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_start_i_1__6_n_0\,
      Q => \p_0_in7_in__0\,
      R => RST_CPLLRESET
    );
\drp_x16_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20020006"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(4),
      I2 => \^q\(1),
      I3 => \^q\(3),
      I4 => \^q\(0),
      O => \drp_x16_i_1__6_n_0\
    );
drp_x16_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16_i_1__6_n_0\,
      Q => p_0_in9_in,
      R => RST_CPLLRESET
    );
\drp_x16x20_mode_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20001584"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(4),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => \^q\(3),
      O => \drp_x16x20_mode_i_1__6_n_0\
    );
drp_x16x20_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \drp_x16x20_mode_i_1__6_n_0\,
      Q => p_0_in135_in,
      R => RST_CPLLRESET
    );
\fsm[0]_i_10__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \txdata_wait_cnt_reg__0\(3),
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(0),
      I3 => \txdata_wait_cnt_reg__0\(1),
      O => \fsm[0]_i_10__6_n_0\
    );
\fsm[0]_i_11__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000F404"
    )
        port map (
      I0 => rxpmaresetdone_reg2,
      I1 => mmcm_lock_reg2,
      I2 => \^q\(0),
      I3 => drp_done_reg2,
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \fsm[0]_i_11__6_n_0\
    );
\fsm[0]_i_12__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F4F737F4343404C"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => rxpmaresetdone_reg2,
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[0]_i_12__6_n_0\
    );
\fsm[0]_i_1__13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBB88888BBB8BBB8"
    )
        port map (
      I0 => \fsm_reg[0]_i_2__6_n_0\,
      I1 => \^q\(4),
      I2 => \fsm[0]_i_3__13_n_0\,
      I3 => \^q\(3),
      I4 => \fsm[0]_i_4__6_n_0\,
      I5 => \fsm[0]_i_5__6_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_3__13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0344FF440344FF77"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => pll_lock,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \fsm[3]_i_9__6_n_0\,
      O => \fsm[0]_i_3__13_n_0\
    );
\fsm[0]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0000000F800F000"
    )
        port map (
      I0 => pll_lock,
      I1 => rst_idle_reg2,
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => drp_done_reg2,
      I5 => \^q\(0),
      O => \fsm[0]_i_4__6_n_0\
    );
\fsm[0]_i_5__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCC8C0C8"
    )
        port map (
      I0 => \fsm[0]_i_8__6_n_0\,
      I1 => \^q\(3),
      I2 => \fsm[0]_i_9__6_n_0\,
      I3 => \^q\(0),
      I4 => \fsm[0]_i_10__6_n_0\,
      I5 => \fsm[0]_i_11__6_n_0\,
      O => \fsm[0]_i_5__6_n_0\
    );
\fsm[0]_i_6__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0040"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(0),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \fsm[0]_i_12__6_n_0\,
      O => \fsm[0]_i_6__6_n_0\
    );
\fsm[0]_i_7__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03880333"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[0]_i_7__6_n_0\
    );
\fsm[0]_i_8__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77770777"
    )
        port map (
      I0 => p_0_in7_in,
      I1 => p_1_in8_in,
      I2 => rxresetdone_reg2,
      I3 => txresetdone_reg2,
      I4 => phystatus_reg2,
      O => \fsm[0]_i_8__6_n_0\
    );
\fsm[0]_i_9__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      O => \fsm[0]_i_9__6_n_0\
    );
\fsm[1]_i_4__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BBFC00"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_8__6_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_4__6_n_0\
    );
\fsm[1]_i_5__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CC88300000BB3000"
    )
        port map (
      I0 => \fsm[0]_i_10__6_n_0\,
      I1 => \^q\(2),
      I2 => \fsm[1]_i_9__6_n_0\,
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => drp_done_reg2,
      O => \fsm[1]_i_5__6_n_0\
    );
\fsm[1]_i_6__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70F040F0"
    )
        port map (
      I0 => resetovrd_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => drp_done_reg2,
      O => \fsm[1]_i_6__6_n_0\
    );
\fsm[1]_i_7__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03777700"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => txsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[1]_i_7__6_n_0\
    );
\fsm[1]_i_8__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"53F5FFFFFFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => qplllock_reg2,
      I2 => rate_in_reg2(0),
      I3 => rate_in_reg2(1),
      I4 => rst_idle_reg2,
      I5 => \^q\(0),
      O => \fsm[1]_i_8__6_n_0\
    );
\fsm[1]_i_9__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF4575FFFFFFFF"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      I3 => qplllock_reg2,
      I4 => rst_idle_reg2,
      I5 => drp_done_reg2,
      O => \fsm[1]_i_9__6_n_0\
    );
\fsm[2]_i_1__13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \fsm[2]_i_2__6_n_0\,
      I1 => \fsm[2]_i_3__6_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[2]_i_4__6_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[2]_i_5__6_n_0\,
      O => fsm(2)
    );
\fsm[2]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3C0C4040"
    )
        port map (
      I0 => rxsync_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_done_reg2,
      I4 => \^q\(0),
      O => \fsm[2]_i_2__6_n_0\
    );
\fsm[2]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13CCD3CC1FCCDFCC"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => resetovrd_done_reg2,
      I5 => fsm1,
      O => \fsm[2]_i_3__6_n_0\
    );
\fsm[2]_i_4__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BC0C"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => \^q\(0),
      O => \fsm[2]_i_4__6_n_0\
    );
\fsm[2]_i_5__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4A4A4A4AAAAFAAAA"
    )
        port map (
      I0 => \^q\(2),
      I1 => pll_lock,
      I2 => \^q\(1),
      I3 => \fsm[3]_i_9__6_n_0\,
      I4 => \fsm[3]_i_8__6_n_0\,
      I5 => \^q\(0),
      O => \fsm[2]_i_5__6_n_0\
    );
\fsm[3]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFE0EFEFEFE0E0E0"
    )
        port map (
      I0 => \fsm[3]_i_2__6_n_0\,
      I1 => \fsm[3]_i_3__6_n_0\,
      I2 => \^q\(4),
      I3 => \fsm[3]_i_4__6_n_0\,
      I4 => \^q\(3),
      I5 => \fsm[3]_i_5__6_n_0\,
      O => fsm(3)
    );
\fsm[3]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22AA2A22"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(2),
      I2 => rxsync_done_reg2,
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \fsm[3]_i_2__6_n_0\
    );
\fsm[3]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3020002000000000"
    )
        port map (
      I0 => fsm1,
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => resetovrd_done_reg2,
      I5 => \^q\(0),
      O => \fsm[3]_i_3__6_n_0\
    );
\fsm[3]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F545F555FFFFFFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rst_idle_reg2,
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => pll_lock,
      I5 => \^q\(1),
      O => \fsm[3]_i_4__6_n_0\
    );
\fsm[3]_i_5__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80808180"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \fsm[3]_i_8__6_n_0\,
      I4 => \fsm[3]_i_9__6_n_0\,
      O => \fsm[3]_i_5__6_n_0\
    );
\fsm[3]_i_6__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF8F8FFF8"
    )
        port map (
      I0 => p_1_in8_in,
      I1 => p_0_in7_in,
      I2 => ratedone_reg_n_0,
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg2(0),
      I5 => gen3_exit,
      O => fsm1
    );
\fsm[3]_i_7__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => cplllock_reg2,
      O => pll_lock
    );
\fsm[3]_i_8__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg1(1),
      O => \fsm[3]_i_8__6_n_0\
    );
\fsm[3]_i_9__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rate_in_reg1(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(1),
      I3 => rate_in_reg2(1),
      O => \fsm[3]_i_9__6_n_0\
    );
\fsm[4]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08880000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => drp_done_reg2,
      I3 => \^q\(0),
      I4 => \^q\(2),
      O => \fsm[4]_i_2__6_n_0\
    );
\fsm[4]_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5F75FFFF"
    )
        port map (
      I0 => \^q\(2),
      I1 => rxsync_done_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^q\(3),
      O => \fsm[4]_i_3__6_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\fsm_reg[0]_i_2__6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[0]_i_6__6_n_0\,
      I1 => \fsm[0]_i_7__6_n_0\,
      O => \fsm_reg[0]_i_2__6_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      S => RST_CPLLRESET
    );
\fsm_reg[1]_i_1__6\: unisim.vcomponents.MUXF8
     port map (
      I0 => \fsm_reg[1]_i_2__6_n_0\,
      I1 => \fsm_reg[1]_i_3__6_n_0\,
      O => fsm(1),
      S => \^q\(4)
    );
\fsm_reg[1]_i_2__6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_4__6_n_0\,
      I1 => \fsm[1]_i_5__6_n_0\,
      O => \fsm_reg[1]_i_2__6_n_0\,
      S => \^q\(3)
    );
\fsm_reg[1]_i_3__6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[1]_i_6__6_n_0\,
      I1 => \fsm[1]_i_7__6_n_0\,
      O => \fsm_reg[1]_i_3__6_n_0\,
      S => \^q\(3)
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => fsm(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\fsm_reg[4]_i_1__6\: unisim.vcomponents.MUXF7
     port map (
      I0 => \fsm[4]_i_2__6_n_0\,
      I1 => \fsm[4]_i_3__6_n_0\,
      O => fsm(4),
      S => \^q\(4)
    );
\gen3_exit_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_exit_i_2__6_n_0\,
      I4 => gen3_exit,
      O => \gen3_exit_i_1__6_n_0\
    );
\gen3_exit_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C000000000000001"
    )
        port map (
      I0 => \fsm[3]_i_9__6_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => \gen3_exit_i_2__6_n_0\
    );
gen3_exit_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_exit_i_1__6_n_0\,
      Q => gen3_exit,
      R => RST_CPLLRESET
    );
\gen3_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \gen3_i_2__6_n_0\,
      I4 => \^rate_gen3_reg1_reg\(0),
      O => \gen3_i_1__6_n_0\
    );
\gen3_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000008"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(4),
      I4 => \^q\(1),
      O => \gen3_i_2__6_n_0\
    );
gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \gen3_i_1__6_n_0\,
      Q => \^rate_gen3_reg1_reg\(0),
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3_reg1_reg\(0),
      O => \cplllock_reg1_reg[7]_0\
    );
\gtx_channel.gtxe2_channel_i_i_7__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3_reg1_reg\(0),
      O => \cplllock_reg1_reg[7]\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
\pclk_sel_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06FF0600"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \pclk_sel_i_2__6_n_0\,
      I4 => \^user_pclk_sel\,
      O => \pclk_sel_i_1__7_n_0\
    );
\pclk_sel_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80040800"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => \pclk_sel_i_2__6_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pclk_sel_i_1__7_n_0\,
      Q => \^user_pclk_sel\,
      R => RST_CPLLRESET
    );
\phystatus_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \txratedone_i_2__6_n_0\,
      I2 => phystatus_reg_n_0,
      O => \phystatus_i_1__6_n_0\
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \phystatus_i_1__6_n_0\,
      Q => phystatus_reg_n_0,
      R => '0'
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_PHYSTATUS,
      Q => phystatus_reg1,
      R => RST_CPLLRESET
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => RST_CPLLRESET
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => qpllpd_reg_0,
      Q => qplllock_reg1,
      R => RST_CPLLRESET
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => RST_CPLLRESET
    );
\qpllpd_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllpd,
      I5 => \^qrst_qpllpd_in\(0),
      O => \qpllpd_i_1__7_n_0\
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllpd_i_1__7_n_0\,
      Q => \^qrst_qpllpd_in\(0),
      R => RST_CPLLRESET
    );
\qpllreset_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0FFFF00B00000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \^q\(4),
      I3 => \^q\(2),
      I4 => qpllreset,
      I5 => \^qrst_qpllreset_in\(0),
      O => \qpllreset_i_1__7_n_0\
    );
qpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \qpllreset_i_1__7_n_0\,
      Q => \^qrst_qpllreset_in\(0),
      R => RST_CPLLRESET
    );
\rate_done_reg1_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => USER_RATE_DONE
    );
\rate_idle_reg1[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => SYNC_RATE_IDLE
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_in_reg1(0),
      R => RST_CPLLRESET
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => RST_CPLLRESET
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => RST_CPLLRESET
    );
\rate_out[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      I2 => \^q\(1),
      I3 => \rate_out[2]_i_2__6_n_0\,
      I4 => \^rxrate\(0),
      O => \rate_out[0]_i_1__6_n_0\
    );
\rate_out[1]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__6_n_0\,
      I1 => \^rxrate\(1),
      O => \rate_out[1]_i_1__6_n_0\
    );
\rate_out[2]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"4"
    )
        port map (
      I0 => \rate_out[2]_i_2__6_n_0\,
      I1 => \^rxrate\(2),
      O => \rate_out[2]_i_1__6_n_0\
    );
\rate_out[2]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000002080000220"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \rate_out[2]_i_3__6_n_0\,
      O => \rate_out[2]_i_2__6_n_0\
    );
\rate_out[2]_i_3__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => gen3_exit,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      O => \rate_out[2]_i_3__6_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[0]_i_1__6_n_0\,
      Q => \^rxrate\(0),
      R => RST_CPLLRESET
    );
\rate_out_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[1]_i_1__6_n_0\,
      Q => \^rxrate\(1),
      R => RST_CPLLRESET
    );
\rate_out_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rate_out[2]_i_1__6_n_0\,
      Q => \^rxrate\(2),
      R => RST_CPLLRESET
    );
\rate_rxsync_reg1_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00808000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(4),
      I2 => \^q\(2),
      I3 => \^q\(1),
      I4 => \^q\(0),
      O => USER_RATE_RXSYNC
    );
\ratedone_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF008000"
    )
        port map (
      I0 => rxratedone_reg_n_0,
      I1 => txratedone_reg_n_0,
      I2 => phystatus_reg_n_0,
      I3 => \txratedone_i_2__6_n_0\,
      I4 => ratedone_reg_n_0,
      O => \ratedone_i_1__6_n_0\
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \ratedone_i_1__6_n_0\,
      Q => ratedone_reg_n_0,
      R => '0'
    );
resetovrd_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RESETOVRD_DONE,
      Q => resetovrd_done_reg1,
      R => RST_CPLLRESET
    );
resetovrd_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => resetovrd_done_reg1,
      Q => resetovrd_done_reg2,
      R => RST_CPLLRESET
    );
\resetovrd_start_reg1_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(4),
      I4 => \^q\(2),
      O => USER_RESETOVRD_START
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => out1(1),
      Q => rst_idle_reg1,
      R => RST_CPLLRESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1,
      R => RST_CPLLRESET
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => RST_CPLLRESET
    );
\rxratedone_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \txratedone_i_2__6_n_0\,
      I2 => rxratedone_reg_n_0,
      O => \rxratedone_i_1__6_n_0\
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \rxratedone_i_1__6_n_0\,
      Q => rxratedone_reg_n_0,
      R => '0'
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_RXRATEDONE,
      Q => rxratedone_reg1,
      R => RST_CPLLRESET
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => SYNC_RXSYNC_DONE,
      Q => rxsync_done_reg1,
      R => RST_CPLLRESET
    );
rxsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => rxsync_done_reg1,
      Q => rxsync_done_reg2,
      R => RST_CPLLRESET
    );
\rxsync_start_reg1_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => SYNC_RXSYNC_START
    );
\start_reg1_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \p_0_in7_in__0\,
      I1 => RST_DRP_START,
      O => DRP_START08_out
    );
\sysclksel[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF3EFF00000200"
    )
        port map (
      I0 => \sysclksel[0]_i_2__6_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \sysclksel[0]_i_3__6_n_0\,
      I5 => \^rxsysclksel\(0),
      O => \sysclksel[0]_i_1__6_n_0\
    );
\sysclksel[0]_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      O => \sysclksel[0]_i_2__6_n_0\
    );
\sysclksel[0]_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      O => \sysclksel[0]_i_3__6_n_0\
    );
\sysclksel[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FFFFFFF00000000"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(2),
      I5 => \^rxsysclksel\(1),
      O => \sysclksel[1]_i_1__6_n_0\
    );
\sysclksel_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[0]_i_1__6_n_0\,
      Q => \^rxsysclksel\(0),
      R => RST_CPLLRESET
    );
\sysclksel_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \sysclksel[1]_i_1__6_n_0\,
      Q => \^rxsysclksel\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__6_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(0)
    );
\txdata_wait_cnt[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__6_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(0),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(3),
      I4 => \txdata_wait_cnt_reg__0\(2),
      O => \p_0_in__0\(1)
    );
\txdata_wait_cnt[2]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8AA0A0A0"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__6_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(3),
      I2 => \txdata_wait_cnt_reg__0\(2),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(1),
      O => \p_0_in__0\(2)
    );
\txdata_wait_cnt[3]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => \txdata_wait_cnt[3]_i_2__6_n_0\,
      I1 => \txdata_wait_cnt_reg__0\(2),
      I2 => \txdata_wait_cnt_reg__0\(1),
      I3 => \txdata_wait_cnt_reg__0\(0),
      I4 => \txdata_wait_cnt_reg__0\(3),
      O => \p_0_in__0\(3)
    );
\txdata_wait_cnt[3]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      O => \txdata_wait_cnt[3]_i_2__6_n_0\
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \txdata_wait_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \txdata_wait_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \txdata_wait_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \txdata_wait_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\txpmareset_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5504FFFF55040000"
    )
        port map (
      I0 => \^q\(3),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => gen3_exit,
      I4 => \txpmareset_i_2__6_n_0\,
      I5 => \^gt_txpmareset017_out\,
      O => \txpmareset_i_1__6_n_0\
    );
\txpmareset_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"82000400"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(4),
      I3 => \^q\(1),
      I4 => \^q\(3),
      O => \txpmareset_i_2__6_n_0\
    );
txpmareset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txpmareset_i_1__6_n_0\,
      Q => \^gt_txpmareset017_out\,
      R => RST_CPLLRESET
    );
\txratedone_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \txratedone_i_2__6_n_0\,
      I2 => txratedone_reg_n_0,
      O => \txratedone_i_1__6_n_0\
    );
\txratedone_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => RST_CPLLRESET,
      O => \txratedone_i_2__6_n_0\
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => \txratedone_i_1__6_n_0\,
      Q => txratedone_reg_n_0,
      R => '0'
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXRATEDONE,
      Q => txratedone_reg1,
      R => RST_CPLLRESET
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => RST_CPLLRESET
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => RATE_TXSYNC_DONE,
      Q => txsync_done_reg1,
      R => RST_CPLLRESET
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg_0,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => RST_CPLLRESET
    );
\txsync_start_reg1_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEAAA"
    )
        port map (
      I0 => out1(0),
      I1 => \^q\(1),
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(2),
      I5 => \^q\(0),
      O => SYNC_TXSYNC_START
    );
\x16_reg1_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in9_in,
      I1 => RST_DRP_X16,
      O => DRP_X16010_out
    );
\x16x20_mode_reg1_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in135_in,
      I1 => RST_DRP_X16X20_MODE,
      O => DRP_X16X20_MODE0136_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_reset is
  port (
    rst_cpllpd : out STD_LOGIC;
    \out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cfg_wait_cnt_reg[5]_0\ : out STD_LOGIC;
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    RST_CPLLRESET : out STD_LOGIC;
    RST_RXUSRCLK_RESET : out STD_LOGIC;
    RST_DCLK_RESET : out STD_LOGIC;
    RST_DRP_START : out STD_LOGIC;
    RST_DRP_X16X20_MODE : out STD_LOGIC;
    RST_DRP_X16 : out STD_LOGIC;
    rst_userrdy : out STD_LOGIC;
    rst_gtreset : out STD_LOGIC;
    userrdy_reg_rep_0 : out STD_LOGIC;
    \userrdy_reg_rep__0_0\ : out STD_LOGIC;
    \userrdy_reg_rep__1_0\ : out STD_LOGIC;
    \userrdy_reg_rep__2_0\ : out STD_LOGIC;
    \userrdy_reg_rep__3_0\ : out STD_LOGIC;
    \userrdy_reg_rep__4_0\ : out STD_LOGIC;
    \userrdy_reg_rep__5_0\ : out STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    rate_idle : in STD_LOGIC_VECTOR ( 7 downto 0 );
    done_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \txsync_fsm.txsync_done_reg\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \resetovrd_disble.reset_reg[4]_2\ : in STD_LOGIC;
    pipe_qrst_idle : in STD_LOGIC;
    \rxcdrlock_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    reset_n_reg2_reg : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_reset : entity is "PCIeGen1x8If64_pipe_reset";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_reset;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_reset is
  signal \FSM_onehot_fsm[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[14]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[14]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[14]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[14]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[14]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[15]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[16]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[16]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[16]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[16]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[16]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[16]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[16]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[16]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4__7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[5]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[5]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[8]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[10]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[10]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[11]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[11]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[12]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[12]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[13]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[13]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[14]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[14]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[4]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[5]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[5]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[6]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[6]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[7]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[7]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[8]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[8]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[9]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[9]\ : signal is "yes";
  signal RST_DRP_START0 : STD_LOGIC;
  signal RST_DRP_X16X20_MODE0 : STD_LOGIC;
  signal \cfg_wait_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \cfg_wait_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \^cfg_wait_cnt_reg[5]_0\ : STD_LOGIC;
  signal \cfg_wait_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal cplllock_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal cplllock_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \cpllpd_i_1__7_n_0\ : STD_LOGIC;
  signal cpllreset : STD_LOGIC;
  signal cpllreset_i_1_n_0 : STD_LOGIC;
  signal dclk_rst : STD_LOGIC;
  signal dclk_rst_reg1 : STD_LOGIC;
  signal dclk_rst_reg2 : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal drp_done_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal gtreset_i_1_n_0 : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute RTL_KEEP of \out\ : signal is "yes";
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_2_in : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal phystatus_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \pipe_rst_fsm[2]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal qpll_idle_reg1 : STD_LOGIC;
  signal qpll_idle_reg2 : STD_LOGIC;
  signal rate_idle_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rate_idle_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal resetdone_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal resetdone_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^rst_cpllpd\ : STD_LOGIC;
  signal \^rst_gtreset\ : STD_LOGIC;
  signal \^rst_userrdy\ : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rxcdrlock_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rxpmaresetdone_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rxpmaresetdone_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rxusrclk_rst_reg1 : STD_LOGIC;
  signal rxusrclk_rst_reg2 : STD_LOGIC;
  signal txsync_done_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal txsync_done_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal userrdy_i_1_n_0 : STD_LOGIC;
  signal \^userrdy_reg_rep_0\ : STD_LOGIC;
  signal \^userrdy_reg_rep__0_0\ : STD_LOGIC;
  signal \^userrdy_reg_rep__1_0\ : STD_LOGIC;
  signal \^userrdy_reg_rep__2_0\ : STD_LOGIC;
  signal \^userrdy_reg_rep__3_0\ : STD_LOGIC;
  signal \^userrdy_reg_rep__4_0\ : STD_LOGIC;
  signal \^userrdy_reg_rep__5_0\ : STD_LOGIC;
  signal \userrdy_rep_i_1__0_n_0\ : STD_LOGIC;
  signal \userrdy_rep_i_1__1_n_0\ : STD_LOGIC;
  signal \userrdy_rep_i_1__2_n_0\ : STD_LOGIC;
  signal \userrdy_rep_i_1__3_n_0\ : STD_LOGIC;
  signal \userrdy_rep_i_1__4_n_0\ : STD_LOGIC;
  signal \userrdy_rep_i_1__5_n_0\ : STD_LOGIC;
  signal userrdy_rep_i_1_n_0 : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[10]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[11]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[12]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[13]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[14]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[15]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[16]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[4]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[5]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[6]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[7]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[8]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \cfg_wait_cnt[3]_i_2\ : label is "soft_lutpair215";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[5]_i_2\ : label is "soft_lutpair215";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \cplllock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of dclk_rst_reg1_reg : label is std.standard.true;
  attribute KEEP of dclk_rst_reg1_reg : label is "yes";
  attribute ASYNC_REG of dclk_rst_reg2_reg : label is std.standard.true;
  attribute KEEP of dclk_rst_reg2_reg : label is "yes";
  attribute ASYNC_REG of \drp_done_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute ASYNC_REG of \phystatus_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \phystatus_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of qpll_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of qpll_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of qpll_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of qpll_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rate_idle_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \resetdone_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxcdrlock_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxpmaresetdone_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of rxusrclk_rst_reg1_reg : label is std.standard.true;
  attribute KEEP of rxusrclk_rst_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxusrclk_rst_reg2_reg : label is std.standard.true;
  attribute KEEP of rxusrclk_rst_reg2_reg : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txsync_done_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[7]\ : label is "yes";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of userrdy_reg : label is "userrdy_reg";
  attribute ORIG_CELL_NAME of userrdy_reg_rep : label is "userrdy_reg";
  attribute ORIG_CELL_NAME of \userrdy_reg_rep__0\ : label is "userrdy_reg";
  attribute ORIG_CELL_NAME of \userrdy_reg_rep__1\ : label is "userrdy_reg";
  attribute ORIG_CELL_NAME of \userrdy_reg_rep__2\ : label is "userrdy_reg";
  attribute ORIG_CELL_NAME of \userrdy_reg_rep__3\ : label is "userrdy_reg";
  attribute ORIG_CELL_NAME of \userrdy_reg_rep__4\ : label is "userrdy_reg";
  attribute ORIG_CELL_NAME of \userrdy_reg_rep__5\ : label is "userrdy_reg";
begin
  RST_CPLLRESET <= cpllreset;
  RST_DCLK_RESET <= dclk_rst_reg2;
  RST_RXUSRCLK_RESET <= rxusrclk_rst_reg2;
  \cfg_wait_cnt_reg[5]_0\ <= \^cfg_wait_cnt_reg[5]_0\;
  \out\(2 downto 0) <= \^out\(2 downto 0);
  rst_cpllpd <= \^rst_cpllpd\;
  rst_gtreset <= \^rst_gtreset\;
  rst_userrdy <= \^rst_userrdy\;
  userrdy_reg_rep_0 <= \^userrdy_reg_rep_0\;
  \userrdy_reg_rep__0_0\ <= \^userrdy_reg_rep__0_0\;
  \userrdy_reg_rep__1_0\ <= \^userrdy_reg_rep__1_0\;
  \userrdy_reg_rep__2_0\ <= \^userrdy_reg_rep__2_0\;
  \userrdy_reg_rep__3_0\ <= \^userrdy_reg_rep__3_0\;
  \userrdy_reg_rep__4_0\ <= \^userrdy_reg_rep__4_0\;
  \userrdy_reg_rep__5_0\ <= \^userrdy_reg_rep__5_0\;
\FSM_onehot_fsm[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"13101010"
    )
        port map (
      I0 => \FSM_onehot_fsm[1]_i_2_n_0\,
      I1 => \^out\(0),
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I4 => \FSM_onehot_fsm[0]_i_2_n_0\,
      O => \FSM_onehot_fsm[0]_i_1_n_0\
    );
\FSM_onehot_fsm[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF7"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_4_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_2_n_0\,
      I2 => cplllock_reg2(1),
      I3 => cplllock_reg2(0),
      I4 => cplllock_reg2(3),
      I5 => cplllock_reg2(2),
      O => \FSM_onehot_fsm[0]_i_2_n_0\
    );
\FSM_onehot_fsm[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A0C00000A000000"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm[13]_i_2_n_0\,
      I3 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I4 => \FSM_onehot_fsm[16]_i_4_n_0\,
      I5 => \FSM_onehot_fsm[13]_i_3_n_0\,
      O => \FSM_onehot_fsm[13]_i_1_n_0\
    );
\FSM_onehot_fsm[13]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[5]\,
      O => \FSM_onehot_fsm[13]_i_2_n_0\
    );
\FSM_onehot_fsm[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_fsm[14]_i_3_n_0\,
      I1 => phystatus_reg2(1),
      I2 => phystatus_reg2(0),
      I3 => phystatus_reg2(3),
      I4 => phystatus_reg2(2),
      I5 => \FSM_onehot_fsm[14]_i_5_n_0\,
      O => \FSM_onehot_fsm[13]_i_3_n_0\
    );
\FSM_onehot_fsm[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \FSM_onehot_fsm[14]_i_2_n_0\,
      I1 => \FSM_onehot_fsm[14]_i_3_n_0\,
      I2 => \FSM_onehot_fsm[14]_i_4_n_0\,
      I3 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I4 => \FSM_onehot_fsm[14]_i_5_n_0\,
      I5 => \FSM_onehot_fsm[16]_i_4_n_0\,
      O => \FSM_onehot_fsm[14]_i_1_n_0\
    );
\FSM_onehot_fsm[14]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[8]\,
      O => \FSM_onehot_fsm[14]_i_2_n_0\
    );
\FSM_onehot_fsm[14]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => resetdone_reg2(4),
      I1 => resetdone_reg2(5),
      I2 => resetdone_reg2(2),
      I3 => resetdone_reg2(3),
      I4 => resetdone_reg2(7),
      I5 => resetdone_reg2(6),
      O => \FSM_onehot_fsm[14]_i_3_n_0\
    );
\FSM_onehot_fsm[14]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => phystatus_reg2(1),
      I1 => phystatus_reg2(0),
      I2 => phystatus_reg2(3),
      I3 => phystatus_reg2(2),
      O => \FSM_onehot_fsm[14]_i_4_n_0\
    );
\FSM_onehot_fsm[14]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => phystatus_reg2(6),
      I1 => phystatus_reg2(7),
      I2 => phystatus_reg2(4),
      I3 => phystatus_reg2(5),
      I4 => resetdone_reg2(1),
      I5 => resetdone_reg2(0),
      O => \FSM_onehot_fsm[14]_i_5_n_0\
    );
\FSM_onehot_fsm[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55100000"
    )
        port map (
      I0 => \FSM_onehot_fsm[16]_i_6_n_0\,
      I1 => \FSM_onehot_fsm[16]_i_5_n_0\,
      I2 => \^out\(1),
      I3 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I4 => \FSM_onehot_fsm[16]_i_4_n_0\,
      O => \FSM_onehot_fsm[15]_i_1_n_0\
    );
\FSM_onehot_fsm[16]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => reset_n_reg2_reg,
      O => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000C0AA"
    )
        port map (
      I0 => \FSM_onehot_fsm[16]_i_3_n_0\,
      I1 => \FSM_onehot_fsm[16]_i_4_n_0\,
      I2 => \FSM_onehot_fsm[16]_i_5_n_0\,
      I3 => \^out\(1),
      I4 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I5 => \FSM_onehot_fsm[16]_i_6_n_0\,
      O => \FSM_onehot_fsm[16]_i_2_n_0\
    );
\FSM_onehot_fsm[16]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \FSM_onehot_fsm[16]_i_7_n_0\,
      I1 => \^out\(2),
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \^out\(0),
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => \FSM_onehot_fsm[16]_i_3_n_0\
    );
\FSM_onehot_fsm[16]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \^out\(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[16]_i_4_n_0\
    );
\FSM_onehot_fsm[16]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \FSM_onehot_fsm[16]_i_8_n_0\,
      I1 => txsync_done_reg2(5),
      I2 => txsync_done_reg2(4),
      O => \FSM_onehot_fsm[16]_i_5_n_0\
    );
\FSM_onehot_fsm[16]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[13]\,
      O => \FSM_onehot_fsm[16]_i_6_n_0\
    );
\FSM_onehot_fsm[16]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \FSM_onehot_fsm[16]_i_9_n_0\,
      I1 => txsync_done_reg2(4),
      I2 => txsync_done_reg2(5),
      O => \FSM_onehot_fsm[16]_i_7_n_0\
    );
\FSM_onehot_fsm[16]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => txsync_done_reg2(7),
      I1 => txsync_done_reg2(6),
      I2 => txsync_done_reg2(0),
      I3 => txsync_done_reg2(1),
      I4 => txsync_done_reg2(2),
      I5 => txsync_done_reg2(3),
      O => \FSM_onehot_fsm[16]_i_8_n_0\
    );
\FSM_onehot_fsm[16]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => txsync_done_reg2(6),
      I1 => txsync_done_reg2(7),
      I2 => txsync_done_reg2(1),
      I3 => txsync_done_reg2(0),
      I4 => txsync_done_reg2(3),
      I5 => txsync_done_reg2(2),
      O => \FSM_onehot_fsm[16]_i_9_n_0\
    );
\FSM_onehot_fsm[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \FSM_onehot_fsm[1]_i_2_n_0\,
      I1 => \^out\(0),
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[1]_i_1_n_0\
    );
\FSM_onehot_fsm[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \cfg_wait_cnt_reg__0\(4),
      I1 => \cfg_wait_cnt_reg__0\(5),
      I2 => \cfg_wait_cnt_reg__0\(2),
      I3 => \cfg_wait_cnt_reg__0\(3),
      I4 => \cfg_wait_cnt_reg__0\(1),
      I5 => \cfg_wait_cnt_reg__0\(0),
      O => \FSM_onehot_fsm[1]_i_2_n_0\
    );
\FSM_onehot_fsm[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \pipe_rst_fsm[2]_INST_0_i_1_n_0\,
      I1 => \FSM_onehot_fsm[2]_i_2_n_0\,
      I2 => \^out\(0),
      O => \FSM_onehot_fsm[2]_i_1_n_0\
    );
\FSM_onehot_fsm[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00020000"
    )
        port map (
      I0 => \FSM_onehot_fsm[16]_i_7_n_0\,
      I1 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => \^out\(2),
      O => \FSM_onehot_fsm[2]_i_2_n_0\
    );
\FSM_onehot_fsm[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02020202020F0202"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_3_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_3_n_0\,
      I3 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => \FSM_onehot_fsm[4]_i_2__7_n_0\,
      O => \FSM_onehot_fsm[3]_i_1_n_0\
    );
\FSM_onehot_fsm[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => resetdone_reg2(4),
      I1 => resetdone_reg2(5),
      I2 => resetdone_reg2(2),
      I3 => resetdone_reg2(3),
      I4 => resetdone_reg2(7),
      I5 => resetdone_reg2(6),
      O => \FSM_onehot_fsm[3]_i_2_n_0\
    );
\FSM_onehot_fsm[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF7"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_4_n_0\,
      I1 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I2 => cplllock_reg2(1),
      I3 => cplllock_reg2(0),
      I4 => cplllock_reg2(3),
      I5 => cplllock_reg2(2),
      O => \FSM_onehot_fsm[3]_i_3_n_0\
    );
\FSM_onehot_fsm[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => cplllock_reg2(6),
      I1 => cplllock_reg2(7),
      I2 => cplllock_reg2(4),
      I3 => cplllock_reg2(5),
      I4 => resetdone_reg2(1),
      I5 => resetdone_reg2(0),
      O => \FSM_onehot_fsm[3]_i_4_n_0\
    );
\FSM_onehot_fsm[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200020002030200"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_2__7_n_0\,
      I1 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm[4]_i_3_n_0\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm[5]_i_2_n_0\,
      O => \FSM_onehot_fsm[4]_i_1_n_0\
    );
\FSM_onehot_fsm[4]_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => cplllock_reg2(1),
      I1 => cplllock_reg2(0),
      I2 => \FSM_onehot_fsm[4]_i_4__7_n_0\,
      O => \FSM_onehot_fsm[4]_i_2__7_n_0\
    );
\FSM_onehot_fsm[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \^out\(0),
      O => \FSM_onehot_fsm[4]_i_3_n_0\
    );
\FSM_onehot_fsm[4]_i_4__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => cplllock_reg2(3),
      I1 => cplllock_reg2(2),
      I2 => cplllock_reg2(6),
      I3 => cplllock_reg2(7),
      I4 => cplllock_reg2(4),
      I5 => cplllock_reg2(5),
      O => \FSM_onehot_fsm[4]_i_4__7_n_0\
    );
\FSM_onehot_fsm[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm[5]_i_2_n_0\,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \^out\(0),
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => \FSM_onehot_fsm[5]_i_1_n_0\
    );
\FSM_onehot_fsm[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \FSM_onehot_fsm[5]_i_3_n_0\,
      I1 => rate_idle_reg2(4),
      I2 => rate_idle_reg2(5),
      O => \FSM_onehot_fsm[5]_i_2_n_0\
    );
\FSM_onehot_fsm[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => rate_idle_reg2(6),
      I1 => rate_idle_reg2(7),
      I2 => rate_idle_reg2(1),
      I3 => rate_idle_reg2(0),
      I4 => rate_idle_reg2(3),
      I5 => rate_idle_reg2(2),
      O => \FSM_onehot_fsm[5]_i_3_n_0\
    );
\FSM_onehot_fsm[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55100000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => mmcm_lock_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm[16]_i_4_n_0\,
      O => \FSM_onehot_fsm[8]_i_1_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[0]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[10]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[11]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[12]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[13]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[13]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[14]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[14]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[15]_i_1_n_0\,
      Q => \^out\(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[16]_i_2_n_0\,
      Q => \^out\(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1_n_0\,
      Q => \^out\(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[5]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[5]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[6]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[7]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[8]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[8]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\FSM_onehot_fsm_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[9]\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
RST_DRP_START_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[11]\,
      O => RST_DRP_START0
    );
RST_DRP_START_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_DRP_START0,
      Q => RST_DRP_START,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
RST_DRP_X16X20_MODE_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[11]\,
      O => RST_DRP_X16X20_MODE0
    );
RST_DRP_X16X20_MODE_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_DRP_X16X20_MODE0,
      Q => RST_DRP_X16X20_MODE,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
RST_DRP_X16_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[7]\,
      O => p_2_in
    );
RST_DRP_X16_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => p_2_in,
      Q => RST_DRP_X16,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cfg_wait_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2000AAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \cfg_wait_cnt[5]_i_2_n_0\,
      I2 => \cfg_wait_cnt_reg__0\(5),
      I3 => \cfg_wait_cnt_reg__0\(4),
      I4 => \cfg_wait_cnt_reg__0\(0),
      O => \p_0_in__0\(0)
    );
\cfg_wait_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"28AA282828282828"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \cfg_wait_cnt_reg__0\(0),
      I2 => \cfg_wait_cnt_reg__0\(1),
      I3 => \cfg_wait_cnt[5]_i_2_n_0\,
      I4 => \cfg_wait_cnt_reg__0\(5),
      I5 => \cfg_wait_cnt_reg__0\(4),
      O => \p_0_in__0\(1)
    );
\cfg_wait_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88A2882288228822"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \cfg_wait_cnt_reg__0\(2),
      I2 => \cfg_wait_cnt_reg__0\(3),
      I3 => \cfg_wait_cnt[3]_i_2_n_0\,
      I4 => \cfg_wait_cnt_reg__0\(5),
      I5 => \cfg_wait_cnt_reg__0\(4),
      O => \p_0_in__0\(2)
    );
\cfg_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A88828882888288"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \cfg_wait_cnt_reg__0\(3),
      I2 => \cfg_wait_cnt[3]_i_2_n_0\,
      I3 => \cfg_wait_cnt_reg__0\(2),
      I4 => \cfg_wait_cnt_reg__0\(5),
      I5 => \cfg_wait_cnt_reg__0\(4),
      O => \p_0_in__0\(3)
    );
\cfg_wait_cnt[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \cfg_wait_cnt_reg__0\(0),
      I1 => \cfg_wait_cnt_reg__0\(1),
      O => \cfg_wait_cnt[3]_i_2_n_0\
    );
\cfg_wait_cnt[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C80C"
    )
        port map (
      I0 => \cfg_wait_cnt_reg__0\(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \cfg_wait_cnt[5]_i_2_n_0\,
      I3 => \cfg_wait_cnt_reg__0\(4),
      O => \p_0_in__0\(4)
    );
\cfg_wait_cnt[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8A88"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \cfg_wait_cnt_reg__0\(5),
      I2 => \cfg_wait_cnt[5]_i_2_n_0\,
      I3 => \cfg_wait_cnt_reg__0\(4),
      O => \p_0_in__0\(5)
    );
\cfg_wait_cnt[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \cfg_wait_cnt_reg__0\(1),
      I1 => \cfg_wait_cnt_reg__0\(0),
      I2 => \cfg_wait_cnt_reg__0\(3),
      I3 => \cfg_wait_cnt_reg__0\(2),
      O => \cfg_wait_cnt[5]_i_2_n_0\
    );
\cfg_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \cfg_wait_cnt_reg__0\(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cfg_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \cfg_wait_cnt_reg__0\(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cfg_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \cfg_wait_cnt_reg__0\(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cfg_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \cfg_wait_cnt_reg__0\(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cfg_wait_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(4),
      Q => \cfg_wait_cnt_reg__0\(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cfg_wait_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(5),
      Q => \cfg_wait_cnt_reg__0\(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\(0),
      Q => cplllock_reg1(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\(1),
      Q => cplllock_reg1(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\(2),
      Q => cplllock_reg1(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\(3),
      Q => cplllock_reg1(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\(4),
      Q => cplllock_reg1(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\(5),
      Q => cplllock_reg1(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\(6),
      Q => cplllock_reg1(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\(7),
      Q => cplllock_reg1(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(0),
      Q => cplllock_reg2(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(1),
      Q => cplllock_reg2(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(2),
      Q => cplllock_reg2(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(3),
      Q => cplllock_reg2(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(4),
      Q => cplllock_reg2(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(5),
      Q => cplllock_reg2(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(6),
      Q => cplllock_reg2(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cplllock_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(7),
      Q => cplllock_reg2(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\cpllpd_i_1__7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^rst_cpllpd\,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      O => \cpllpd_i_1__7_n_0\
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \cpllpd_i_1__7_n_0\,
      Q => \^rst_cpllpd\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
cpllreset_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF00FFFEFF00"
    )
        port map (
      I0 => \pipe_rst_fsm[2]_INST_0_i_1_n_0\,
      I1 => \^out\(0),
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I4 => cpllreset,
      I5 => \^out\(2),
      O => cpllreset_i_1_n_0
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cpllreset_i_1_n_0,
      Q => cpllreset,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
dclk_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[1]\,
      Q => dclk_rst,
      R => '0'
    );
dclk_rst_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]_2\,
      CE => '1',
      D => dclk_rst,
      Q => dclk_rst_reg1,
      R => '0'
    );
dclk_rst_reg2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]_2\,
      CE => '1',
      D => dclk_rst_reg1,
      Q => dclk_rst_reg2,
      R => '0'
    );
\drp_done_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => done_reg(0),
      Q => drp_done_reg1(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => done_reg(1),
      Q => drp_done_reg1(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => done_reg(2),
      Q => drp_done_reg1(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => done_reg(3),
      Q => drp_done_reg1(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => done_reg(4),
      Q => drp_done_reg1(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => done_reg(5),
      Q => drp_done_reg1(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => done_reg(6),
      Q => drp_done_reg1(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => done_reg(7),
      Q => drp_done_reg1(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => drp_done_reg1(0),
      Q => drp_done_reg2(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => drp_done_reg1(1),
      Q => drp_done_reg2(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => drp_done_reg1(2),
      Q => drp_done_reg2(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => drp_done_reg1(3),
      Q => drp_done_reg2(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => drp_done_reg1(4),
      Q => drp_done_reg2(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => drp_done_reg1(5),
      Q => drp_done_reg2(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => drp_done_reg1(6),
      Q => drp_done_reg2(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\drp_done_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => drp_done_reg1(7),
      Q => drp_done_reg2(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
gtreset_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I2 => \^rst_gtreset\,
      O => gtreset_i_1_n_0
    );
gtreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gtreset_i_1_n_0,
      Q => \^rst_gtreset\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\(0),
      Q => phystatus_reg1(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\(1),
      Q => phystatus_reg1(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\(2),
      Q => phystatus_reg1(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\(3),
      Q => phystatus_reg1(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\(4),
      Q => phystatus_reg1(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\(5),
      Q => phystatus_reg1(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\(6),
      Q => phystatus_reg1(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\(7),
      Q => phystatus_reg1(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => phystatus_reg1(0),
      Q => phystatus_reg2(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => phystatus_reg1(1),
      Q => phystatus_reg2(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => phystatus_reg1(2),
      Q => phystatus_reg2(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => phystatus_reg1(3),
      Q => phystatus_reg2(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => phystatus_reg1(4),
      Q => phystatus_reg2(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => phystatus_reg1(5),
      Q => phystatus_reg2(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => phystatus_reg1(6),
      Q => phystatus_reg2(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\phystatus_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => phystatus_reg1(7),
      Q => phystatus_reg2(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\pipe_rst_fsm[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I2 => \^out\(1),
      I3 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => pipe_rst_fsm(0)
    );
\pipe_rst_fsm[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I1 => \^out\(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => pipe_rst_fsm(1)
    );
\pipe_rst_fsm[2]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \pipe_rst_fsm[2]_INST_0_i_1_n_0\,
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => pipe_rst_fsm(2)
    );
\pipe_rst_fsm[2]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \^out\(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[8]\,
      O => \pipe_rst_fsm[2]_INST_0_i_1_n_0\
    );
\pipe_rst_fsm[3]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I1 => \^out\(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[8]\,
      O => pipe_rst_fsm(3)
    );
qpll_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pipe_qrst_idle,
      Q => qpll_idle_reg1,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
qpll_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpll_idle_reg1,
      Q => qpll_idle_reg2,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle(0),
      Q => rate_idle_reg1(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle(1),
      Q => rate_idle_reg1(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle(2),
      Q => rate_idle_reg1(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle(3),
      Q => rate_idle_reg1(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle(4),
      Q => rate_idle_reg1(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle(5),
      Q => rate_idle_reg1(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle(6),
      Q => rate_idle_reg1(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle(7),
      Q => rate_idle_reg1(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1(0),
      Q => rate_idle_reg2(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1(1),
      Q => rate_idle_reg2(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1(2),
      Q => rate_idle_reg2(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1(3),
      Q => rate_idle_reg2(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1(4),
      Q => rate_idle_reg2(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1(5),
      Q => rate_idle_reg2(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1(6),
      Q => rate_idle_reg2(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rate_idle_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1(7),
      Q => rate_idle_reg2(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(0),
      Q => resetdone_reg1(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(1),
      Q => resetdone_reg1(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(2),
      Q => resetdone_reg1(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(3),
      Q => resetdone_reg1(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(4),
      Q => resetdone_reg1(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(5),
      Q => resetdone_reg1(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(6),
      Q => resetdone_reg1(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(7),
      Q => resetdone_reg1(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetdone_reg1(0),
      Q => resetdone_reg2(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetdone_reg1(1),
      Q => resetdone_reg2(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetdone_reg1(2),
      Q => resetdone_reg2(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetdone_reg1(3),
      Q => resetdone_reg2(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetdone_reg1(4),
      Q => resetdone_reg2(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetdone_reg1(5),
      Q => resetdone_reg2(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetdone_reg1(6),
      Q => resetdone_reg2(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\resetdone_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetdone_reg1(7),
      Q => resetdone_reg2(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxcdrlock_cnt_reg[3]\(0),
      Q => rxcdrlock_reg1(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxcdrlock_cnt_reg[3]\(1),
      Q => rxcdrlock_reg1(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxcdrlock_cnt_reg[3]\(2),
      Q => rxcdrlock_reg1(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxcdrlock_cnt_reg[3]\(3),
      Q => rxcdrlock_reg1(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxcdrlock_cnt_reg[3]\(4),
      Q => rxcdrlock_reg1(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxcdrlock_cnt_reg[3]\(5),
      Q => rxcdrlock_reg1(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxcdrlock_cnt_reg[3]\(6),
      Q => rxcdrlock_reg1(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxcdrlock_cnt_reg[3]\(7),
      Q => rxcdrlock_reg1(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1(0),
      Q => rxcdrlock_reg2(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1(1),
      Q => rxcdrlock_reg2(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1(2),
      Q => rxcdrlock_reg2(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1(3),
      Q => rxcdrlock_reg2(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1(4),
      Q => rxcdrlock_reg2(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1(5),
      Q => rxcdrlock_reg2(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1(6),
      Q => rxcdrlock_reg2(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxcdrlock_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1(7),
      Q => rxcdrlock_reg2(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxpmaresetdone_reg1(0),
      Q => rxpmaresetdone_reg2(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxpmaresetdone_reg1(1),
      Q => rxpmaresetdone_reg2(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxpmaresetdone_reg1(2),
      Q => rxpmaresetdone_reg2(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxpmaresetdone_reg1(3),
      Q => rxpmaresetdone_reg2(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxpmaresetdone_reg1(4),
      Q => rxpmaresetdone_reg2(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxpmaresetdone_reg1(5),
      Q => rxpmaresetdone_reg2(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxpmaresetdone_reg1(6),
      Q => rxpmaresetdone_reg2(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\rxpmaresetdone_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxpmaresetdone_reg1(7),
      Q => rxpmaresetdone_reg2(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
rxusrclk_rst_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cpllreset,
      Q => rxusrclk_rst_reg1,
      R => '0'
    );
rxusrclk_rst_reg2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxusrclk_rst_reg1,
      Q => rxusrclk_rst_reg2,
      R => '0'
    );
\txsync_done_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_reg\(0),
      Q => txsync_done_reg1(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_reg\(1),
      Q => txsync_done_reg1(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_reg\(2),
      Q => txsync_done_reg1(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_reg\(3),
      Q => txsync_done_reg1(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_reg\(4),
      Q => txsync_done_reg1(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_reg\(5),
      Q => txsync_done_reg1(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_reg\(6),
      Q => txsync_done_reg1(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_reg\(7),
      Q => txsync_done_reg1(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_done_reg1(0),
      Q => txsync_done_reg2(0),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_done_reg1(1),
      Q => txsync_done_reg2(1),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_done_reg1(2),
      Q => txsync_done_reg2(2),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_done_reg1(3),
      Q => txsync_done_reg2(3),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_done_reg1(4),
      Q => txsync_done_reg2(4),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_done_reg1(5),
      Q => txsync_done_reg2(5),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_done_reg1(6),
      Q => txsync_done_reg2(6),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\txsync_done_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_done_reg1(7),
      Q => txsync_done_reg2(7),
      R => \^cfg_wait_cnt_reg[5]_0\
    );
userrdy_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I2 => \^rst_userrdy\,
      O => userrdy_i_1_n_0
    );
userrdy_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => userrdy_i_1_n_0,
      Q => \^rst_userrdy\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
userrdy_reg_rep: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => userrdy_rep_i_1_n_0,
      Q => \^userrdy_reg_rep_0\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\userrdy_reg_rep__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \userrdy_rep_i_1__0_n_0\,
      Q => \^userrdy_reg_rep__0_0\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\userrdy_reg_rep__1\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \userrdy_rep_i_1__1_n_0\,
      Q => \^userrdy_reg_rep__1_0\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\userrdy_reg_rep__2\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \userrdy_rep_i_1__2_n_0\,
      Q => \^userrdy_reg_rep__2_0\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\userrdy_reg_rep__3\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \userrdy_rep_i_1__3_n_0\,
      Q => \^userrdy_reg_rep__3_0\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\userrdy_reg_rep__4\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \userrdy_rep_i_1__4_n_0\,
      Q => \^userrdy_reg_rep__4_0\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
\userrdy_reg_rep__5\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \userrdy_rep_i_1__5_n_0\,
      Q => \^userrdy_reg_rep__5_0\,
      R => \^cfg_wait_cnt_reg[5]_0\
    );
userrdy_rep_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I2 => \^userrdy_reg_rep_0\,
      O => userrdy_rep_i_1_n_0
    );
\userrdy_rep_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I2 => \^userrdy_reg_rep__0_0\,
      O => \userrdy_rep_i_1__0_n_0\
    );
\userrdy_rep_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I2 => \^userrdy_reg_rep__1_0\,
      O => \userrdy_rep_i_1__1_n_0\
    );
\userrdy_rep_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I2 => \^userrdy_reg_rep__2_0\,
      O => \userrdy_rep_i_1__2_n_0\
    );
\userrdy_rep_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I2 => \^userrdy_reg_rep__3_0\,
      O => \userrdy_rep_i_1__3_n_0\
    );
\userrdy_rep_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I2 => \^userrdy_reg_rep__4_0\,
      O => \userrdy_rep_i_1__4_n_0\
    );
\userrdy_rep_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I2 => \^userrdy_reg_rep__5_0\,
      O => \userrdy_rep_i_1__5_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 6 downto 0 );
    SYNC_RXSYNC_DONEM_IN : out STD_LOGIC;
    SYNC_RXDLYEN : out STD_LOGIC;
    \cplllock_reg1_reg[0]\ : out STD_LOGIC;
    \cplllock_reg1_reg[0]_0\ : out STD_LOGIC;
    \cplllock_reg1_reg[0]_1\ : out STD_LOGIC;
    \cplllock_reg1_reg[0]_2\ : out STD_LOGIC;
    \cplllock_reg1_reg[0]_3\ : out STD_LOGIC;
    \txsync_fsm.txdlyen_reg_0\ : out STD_LOGIC;
    user_active_lane : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST_CPLLRESET : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    RATE_MMCM_LOCK : in STD_LOGIC;
    SYNC_TXDLYSRESETDONE0 : in STD_LOGIC;
    SYNC_TXPHINITDONE : in STD_LOGIC;
    SYNC_TXPHALIGNDONE : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_RXSYNC_START : in STD_LOGIC;
    SYNC_RXDLYSRESETDONE0 : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_M : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_S : in STD_LOGIC;
    p_0_in7_in : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync : entity is "PCIeGen1x8If64_pipe_sync";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^sync_rxsync_donem_in\ : STD_LOGIC;
  signal fsm_tx : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fsm_tx1 : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_56_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^pipe_sync_fsm_rx\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  signal rxelecidle_reg1 : STD_LOGIC;
  signal rxelecidle_reg2 : STD_LOGIC;
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  signal rxsync_donem_reg1 : STD_LOGIC;
  signal rxsync_donem_reg2 : STD_LOGIC;
  signal rxsync_start_reg1 : STD_LOGIC;
  signal rxsync_start_reg2 : STD_LOGIC;
  signal rxsyncdone_reg1 : STD_LOGIC;
  signal rxsyncdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg1 : STD_LOGIC;
  signal txdlysresetdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg3 : STD_LOGIC;
  signal txphaligndone_reg1 : STD_LOGIC;
  signal txphaligndone_reg2 : STD_LOGIC;
  signal txphaligndone_reg3 : STD_LOGIC;
  signal txphinitdone_reg1 : STD_LOGIC;
  signal txphinitdone_reg2 : STD_LOGIC;
  signal txphinitdone_reg3 : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_2_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[5]_i_2_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_1_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_2_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_3_n_0\ : STD_LOGIC;
  signal \^txsync_fsm.txdlyen_reg_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_1__6_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_2_n_0\ : STD_LOGIC;
  signal txsync_start_reg1 : STD_LOGIC;
  signal txsync_start_reg2 : STD_LOGIC;
  signal txsync_start_reg3 : STD_LOGIC;
  signal txsyncdone_reg1 : STD_LOGIC;
  signal txsyncdone_reg2 : STD_LOGIC;
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_8\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_9\ : label is "soft_lutpair42";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
  RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0);
  SYNC_RXSYNC_DONEM_IN <= \^sync_rxsync_donem_in\;
  pipe_sync_fsm_rx(6 downto 0) <= \^pipe_sync_fsm_rx\(6 downto 0);
  \txsync_fsm.txdlyen_reg_0\ <= \^txsync_fsm.txdlyen_reg_0\;
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => \cplllock_reg1_reg[0]\
    );
\gtx_channel.gtxe2_channel_i_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[0]_1\
    );
\gtx_channel.gtxe2_channel_i_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[0]_0\
    );
\gtx_channel.gtxe2_channel_i_i_56\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(0),
      I1 => \^pipe_sync_fsm_rx\(1),
      I2 => \^pipe_sync_fsm_rx\(6),
      I3 => \^pipe_sync_fsm_rx\(4),
      O => \gtx_channel.gtxe2_channel_i_i_56_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(2),
      I1 => \^pipe_sync_fsm_rx\(3),
      I2 => \^pipe_sync_fsm_rx\(5),
      I3 => \gtx_channel.gtxe2_channel_i_i_56_n_0\,
      O => \cplllock_reg1_reg[0]_3\
    );
\gtx_channel.gtxe2_channel_i_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(2),
      I1 => \^pipe_sync_fsm_rx\(3),
      I2 => \^pipe_sync_fsm_rx\(5),
      I3 => \gtx_channel.gtxe2_channel_i_i_56_n_0\,
      O => \cplllock_reg1_reg[0]_2\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RATE_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_CPLLRESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_CPLLRESET
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXDLYSRESETDONE0,
      Q => rxdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gt_rx_elec_idle_wire_filter(0),
      Q => rxelecidle_reg1,
      R => RST_CPLLRESET
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXPHALIGNDONE_M,
      Q => rxphaligndone_m_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXPHALIGNDONE_S,
      Q => rxphaligndone_s_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => RST_CPLLRESET
    );
rxsync_donem_reg1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(2),
      I1 => \^pipe_sync_fsm_rx\(5),
      I2 => \^pipe_sync_fsm_rx\(3),
      I3 => \gtx_channel.gtxe2_channel_i_i_56_n_0\,
      O => \^sync_rxsync_donem_in\
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \^sync_rxsync_donem_in\,
      Q => rxsync_donem_reg1,
      R => RST_CPLLRESET
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => RST_CPLLRESET
    );
\rxsync_fsm_disable.fsm_rx_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '1',
      Q => \^pipe_sync_fsm_rx\(0),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(1),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(2),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(3),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(4),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(5),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(6),
      R => '0'
    );
\rxsync_fsm_disable.rxdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => SYNC_RXDLYEN,
      R => '0'
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_START,
      Q => rxsync_start_reg1,
      R => RST_CPLLRESET
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => RST_CPLLRESET
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxsyncdone_reg1,
      R => RST_CPLLRESET
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXDLYSRESETDONE0,
      Q => txdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXPHALIGNDONE,
      Q => txphaligndone_reg1,
      R => RST_CPLLRESET
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => RST_CPLLRESET
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXPHINITDONE,
      Q => txphinitdone_reg1,
      R => RST_CPLLRESET
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => RST_CPLLRESET
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F222FFFF"
    )
        port map (
      I0 => \^q\(0),
      I1 => txsync_start_reg2,
      I2 => fsm_tx1,
      I3 => \^q\(5),
      I4 => \txsync_fsm.fsm_tx[5]_i_2_n_0\,
      O => fsm_tx(0)
    );
\txsync_fsm.fsm_tx[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2_n_0\,
      I1 => \^q\(0),
      I2 => txsync_start_reg2,
      I3 => \^q\(1),
      I4 => mmcm_lock_reg2,
      O => fsm_tx(1)
    );
\txsync_fsm.fsm_tx[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA80AA80808080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2_n_0\,
      I1 => \^q\(1),
      I2 => mmcm_lock_reg2,
      I3 => txdlysresetdone_reg2,
      I4 => txdlysresetdone_reg3,
      I5 => \^q\(2),
      O => fsm_tx(2)
    );
\txsync_fsm.fsm_tx[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00800080AAAA0080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2_n_0\,
      I1 => \^q\(2),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(3),
      I5 => \txsync_fsm.fsm_tx[4]_i_2_n_0\,
      O => fsm_tx(3)
    );
\txsync_fsm.fsm_tx[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2_n_0\,
      I1 => \txsync_fsm.fsm_tx[4]_i_2_n_0\,
      I2 => \^q\(3),
      I3 => \^q\(4),
      I4 => fsm_tx1,
      O => fsm_tx(4)
    );
\txsync_fsm.fsm_tx[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F222"
    )
        port map (
      I0 => txphinitdone_reg2,
      I1 => txphinitdone_reg3,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_2_n_0\
    );
\txsync_fsm.fsm_tx[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => txphaligndone_reg3,
      I1 => txphaligndone_reg2,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => fsm_tx1
    );
\txsync_fsm.fsm_tx[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8AAA8A80800080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2_n_0\,
      I1 => \^q\(5),
      I2 => user_active_lane(0),
      I3 => txphaligndone_reg2,
      I4 => txphaligndone_reg3,
      I5 => \^q\(4),
      O => fsm_tx(5)
    );
\txsync_fsm.fsm_tx[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => \txsync_fsm.fsm_tx[5]_i_2_n_0\
    );
\txsync_fsm.fsm_tx_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(1),
      Q => \^q\(1),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(5),
      Q => \^q\(5),
      R => RST_CPLLRESET
    );
\txsync_fsm.txdlyen_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAA8"
    )
        port map (
      I0 => \txsync_fsm.txdlyen_i_2_n_0\,
      I1 => \txsync_fsm.txdlyen_i_3_n_0\,
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^txsync_fsm.txdlyen_reg_0\,
      O => \txsync_fsm.txdlyen_i_1_n_0\
    );
\txsync_fsm.txdlyen_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => \txsync_fsm.txdlyen_i_2_n_0\
    );
\txsync_fsm.txdlyen_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_start_reg2,
      O => \txsync_fsm.txdlyen_i_3_n_0\
    );
\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txdlyen_i_1_n_0\,
      Q => \^txsync_fsm.txdlyen_reg_0\,
      R => RST_CPLLRESET
    );
\txsync_fsm.txsync_done_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0301000103000000"
    )
        port map (
      I0 => \txsync_fsm.txdlyen_i_3_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(5),
      I4 => \txsync_fsm.txsync_done_i_2_n_0\,
      I5 => \^rst_txsync_done\(0),
      O => \txsync_fsm.txsync_done_i_1__6_n_0\
    );
\txsync_fsm.txsync_done_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001055"
    )
        port map (
      I0 => \^q\(0),
      I1 => txphaligndone_reg3,
      I2 => txphaligndone_reg2,
      I3 => user_active_lane(0),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \txsync_fsm.txsync_done_i_2_n_0\
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1__6_n_0\,
      Q => \^rst_txsync_done\(0),
      R => RST_CPLLRESET
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => RST_CPLLRESET
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => RST_CPLLRESET
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => RST_CPLLRESET
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txsyncdone_reg1,
      R => RST_CPLLRESET
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => RST_CPLLRESET
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_33 is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \txsync_fsm.txdlyen_reg_0\ : out STD_LOGIC;
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 6 downto 0 );
    SYNC_RXDLYEN : out STD_LOGIC;
    \cplllock_reg1_reg[1]\ : out STD_LOGIC;
    \cplllock_reg1_reg[1]_0\ : out STD_LOGIC;
    \cplllock_reg1_reg[1]_1\ : out STD_LOGIC;
    \cplllock_reg1_reg[1]_2\ : out STD_LOGIC;
    \cplllock_reg1_reg[1]_3\ : out STD_LOGIC;
    RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in7_in : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    SYNC_TXDLYSRESETDONE0 : in STD_LOGIC;
    SYNC_TXPHINITDONE : in STD_LOGIC;
    SYNC_TXPHALIGNDONE : in STD_LOGIC;
    SYNC_RXSYNC_DONEM_IN : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC;
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_RXSYNC_START : in STD_LOGIC;
    SYNC_RXDLYSRESETDONE0 : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_M : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_S : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_33 : entity is "PCIeGen1x8If64_pipe_sync";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_33;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_33 is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal fsm_tx : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_56__0_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^pipe_sync_fsm_rx\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  signal rxelecidle_reg1 : STD_LOGIC;
  signal rxelecidle_reg2 : STD_LOGIC;
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  signal rxsync_donem_reg1 : STD_LOGIC;
  signal rxsync_donem_reg2 : STD_LOGIC;
  signal rxsync_start_reg1 : STD_LOGIC;
  signal rxsync_start_reg2 : STD_LOGIC;
  signal rxsyncdone_reg1 : STD_LOGIC;
  signal rxsyncdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg1 : STD_LOGIC;
  signal txdlysresetdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg3 : STD_LOGIC;
  signal txphaligndone_reg1 : STD_LOGIC;
  signal txphaligndone_reg2 : STD_LOGIC;
  signal txphaligndone_reg3 : STD_LOGIC;
  signal txphinitdone_reg1 : STD_LOGIC;
  signal txphinitdone_reg2 : STD_LOGIC;
  signal txphinitdone_reg3 : STD_LOGIC;
  signal txsync_done : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_1__0_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_2__0_n_0\ : STD_LOGIC;
  signal \^txsync_fsm.txdlyen_reg_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_1_n_0\ : STD_LOGIC;
  signal txsync_start_reg1 : STD_LOGIC;
  signal txsync_start_reg2 : STD_LOGIC;
  signal txsync_start_reg3 : STD_LOGIC;
  signal txsyncdone_reg1 : STD_LOGIC;
  signal txsyncdone_reg2 : STD_LOGIC;
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
  RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0);
  pipe_sync_fsm_rx(6 downto 0) <= \^pipe_sync_fsm_rx\(6 downto 0);
  \txsync_fsm.txdlyen_reg_0\ <= \^txsync_fsm.txdlyen_reg_0\;
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_11__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => \cplllock_reg1_reg[1]\
    );
\gtx_channel.gtxe2_channel_i_i_12__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[1]_1\
    );
\gtx_channel.gtxe2_channel_i_i_13__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[1]_0\
    );
\gtx_channel.gtxe2_channel_i_i_56__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(0),
      I1 => \^pipe_sync_fsm_rx\(1),
      I2 => \^pipe_sync_fsm_rx\(6),
      I3 => \^pipe_sync_fsm_rx\(4),
      O => \gtx_channel.gtxe2_channel_i_i_56__0_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(2),
      I1 => \^pipe_sync_fsm_rx\(3),
      I2 => \^pipe_sync_fsm_rx\(5),
      I3 => \gtx_channel.gtxe2_channel_i_i_56__0_n_0\,
      O => \cplllock_reg1_reg[1]_3\
    );
\gtx_channel.gtxe2_channel_i_i_9__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => rxsync_donem_reg2,
      I1 => \^pipe_sync_fsm_rx\(5),
      I2 => \^pipe_sync_fsm_rx\(3),
      I3 => \^pipe_sync_fsm_rx\(2),
      I4 => \gtx_channel.gtxe2_channel_i_i_56__0_n_0\,
      O => \cplllock_reg1_reg[1]_2\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_CPLLRESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_CPLLRESET
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXDLYSRESETDONE0,
      Q => rxdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gt_rx_elec_idle_wire_filter(0),
      Q => rxelecidle_reg1,
      R => RST_CPLLRESET
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXPHALIGNDONE_M,
      Q => rxphaligndone_m_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXPHALIGNDONE_S,
      Q => rxphaligndone_s_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => RST_CPLLRESET
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_DONEM_IN,
      Q => rxsync_donem_reg1,
      R => RST_CPLLRESET
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => RST_CPLLRESET
    );
\rxsync_fsm_disable.fsm_rx_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '1',
      Q => \^pipe_sync_fsm_rx\(0),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(1),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(2),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(3),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(4),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(5),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(6),
      R => '0'
    );
\rxsync_fsm_disable.rxdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => SYNC_RXDLYEN,
      R => '0'
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_START,
      Q => rxsync_start_reg1,
      R => RST_CPLLRESET
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => RST_CPLLRESET
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxsyncdone_reg1,
      R => RST_CPLLRESET
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXDLYSRESETDONE0,
      Q => txdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXPHALIGNDONE,
      Q => txphaligndone_reg1,
      R => RST_CPLLRESET
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => RST_CPLLRESET
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXPHINITDONE,
      Q => txphinitdone_reg1,
      R => RST_CPLLRESET
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => RST_CPLLRESET
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F2FF"
    )
        port map (
      I0 => \^q\(0),
      I1 => txsync_start_reg2,
      I2 => \^q\(5),
      I3 => \txsync_fsm.fsm_tx[5]_i_2__0_n_0\,
      O => fsm_tx(0)
    );
\txsync_fsm.fsm_tx[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__0_n_0\,
      I1 => \^q\(0),
      I2 => txsync_start_reg2,
      I3 => \^q\(1),
      I4 => mmcm_lock_reg2,
      O => fsm_tx(1)
    );
\txsync_fsm.fsm_tx[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA80AA80808080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__0_n_0\,
      I1 => \^q\(1),
      I2 => mmcm_lock_reg2,
      I3 => txdlysresetdone_reg2,
      I4 => txdlysresetdone_reg3,
      I5 => \^q\(2),
      O => fsm_tx(2)
    );
\txsync_fsm.fsm_tx[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00800080AAAA0080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__0_n_0\,
      I1 => \^q\(2),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(3),
      I5 => \txsync_fsm.fsm_tx[4]_i_2__0_n_0\,
      O => fsm_tx(3)
    );
\txsync_fsm.fsm_tx[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__0_n_0\,
      I1 => \txsync_fsm.fsm_tx[4]_i_2__0_n_0\,
      I2 => \^q\(3),
      I3 => \^q\(4),
      I4 => \txsync_fsm.fsm_tx[4]_i_3__0_n_0\,
      O => fsm_tx(4)
    );
\txsync_fsm.fsm_tx[4]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F222"
    )
        port map (
      I0 => txphinitdone_reg2,
      I1 => txphinitdone_reg3,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_2__0_n_0\
    );
\txsync_fsm.fsm_tx[4]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => txphaligndone_reg3,
      I1 => txphaligndone_reg2,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_3__0_n_0\
    );
\txsync_fsm.fsm_tx[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA20202000000000"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__0_n_0\,
      I1 => txphaligndone_reg3,
      I2 => txphaligndone_reg2,
      I3 => p_0_in7_in,
      I4 => p_1_in8_in,
      I5 => \^q\(4),
      O => fsm_tx(5)
    );
\txsync_fsm.fsm_tx[5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => \txsync_fsm.fsm_tx[5]_i_2__0_n_0\
    );
\txsync_fsm.fsm_tx_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(1),
      Q => \^q\(1),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(5),
      Q => \^q\(5),
      R => RST_CPLLRESET
    );
\txsync_fsm.txdlyen_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \txsync_fsm.txdlyen_i_2__0_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(5),
      I4 => \^txsync_fsm.txdlyen_reg_0\,
      O => \txsync_fsm.txdlyen_i_1__0_n_0\
    );
\txsync_fsm.txdlyen_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_start_reg2,
      O => \txsync_fsm.txdlyen_i_2__0_n_0\
    );
\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txdlyen_i_1__0_n_0\,
      Q => \^txsync_fsm.txdlyen_reg_0\,
      R => RST_CPLLRESET
    );
\txsync_fsm.txsync_done_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAA8"
    )
        port map (
      I0 => txsync_done,
      I1 => \txsync_fsm.txdlyen_i_2__0_n_0\,
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^rst_txsync_done\(0),
      O => \txsync_fsm.txsync_done_i_1_n_0\
    );
\txsync_fsm.txsync_done_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => txsync_done
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1_n_0\,
      Q => \^rst_txsync_done\(0),
      R => RST_CPLLRESET
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => RST_CPLLRESET
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => RST_CPLLRESET
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => RST_CPLLRESET
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txsyncdone_reg1,
      R => RST_CPLLRESET
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => RST_CPLLRESET
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_39 is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \txsync_fsm.txdlyen_reg_0\ : out STD_LOGIC;
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 6 downto 0 );
    SYNC_RXDLYEN : out STD_LOGIC;
    \cplllock_reg1_reg[2]\ : out STD_LOGIC;
    \cplllock_reg1_reg[2]_0\ : out STD_LOGIC;
    \cplllock_reg1_reg[2]_1\ : out STD_LOGIC;
    \cplllock_reg1_reg[2]_2\ : out STD_LOGIC;
    \cplllock_reg1_reg[2]_3\ : out STD_LOGIC;
    RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in7_in : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    SYNC_TXDLYSRESETDONE0 : in STD_LOGIC;
    SYNC_TXPHINITDONE : in STD_LOGIC;
    SYNC_TXPHALIGNDONE : in STD_LOGIC;
    SYNC_RXSYNC_DONEM_IN : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC;
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_RXSYNC_START : in STD_LOGIC;
    SYNC_RXDLYSRESETDONE0 : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_M : in STD_LOGIC;
    SYNC_RXPHALIGNDONE_S : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_39 : entity is "PCIeGen1x8If64_pipe_sync";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_39;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_39 is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal fsm_tx : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_57_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^pipe_sync_fsm_rx\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  signal rxelecidle_reg1 : STD_LOGIC;
  signal rxelecidle_reg2 : STD_LOGIC;
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  signal rxsync_donem_reg1 : STD_LOGIC;
  signal rxsync_donem_reg2 : STD_LOGIC;
  signal rxsync_start_reg1 : STD_LOGIC;
  signal rxsync_start_reg2 : STD_LOGIC;
  signal rxsyncdone_reg1 : STD_LOGIC;
  signal rxsyncdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg1 : STD_LOGIC;
  signal txdlysresetdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg3 : STD_LOGIC;
  signal txphaligndone_reg1 : STD_LOGIC;
  signal txphaligndone_reg2 : STD_LOGIC;
  signal txphaligndone_reg3 : STD_LOGIC;
  signal txphinitdone_reg1 : STD_LOGIC;
  signal txphinitdone_reg2 : STD_LOGIC;
  signal txphinitdone_reg3 : STD_LOGIC;
  signal txsync_done : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_3__1_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[5]_i_2__1_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_1__1_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_2__1_n_0\ : STD_LOGIC;
  signal \^txsync_fsm.txdlyen_reg_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_1__0_n_0\ : STD_LOGIC;
  signal txsync_start_reg1 : STD_LOGIC;
  signal txsync_start_reg2 : STD_LOGIC;
  signal txsync_start_reg3 : STD_LOGIC;
  signal txsyncdone_reg1 : STD_LOGIC;
  signal txsyncdone_reg2 : STD_LOGIC;
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
  RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0);
  pipe_sync_fsm_rx(6 downto 0) <= \^pipe_sync_fsm_rx\(6 downto 0);
  \txsync_fsm.txdlyen_reg_0\ <= \^txsync_fsm.txdlyen_reg_0\;
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => rxsync_donem_reg2,
      I1 => \^pipe_sync_fsm_rx\(5),
      I2 => \^pipe_sync_fsm_rx\(3),
      I3 => \^pipe_sync_fsm_rx\(2),
      I4 => \gtx_channel.gtxe2_channel_i_i_57_n_0\,
      O => \cplllock_reg1_reg[2]_2\
    );
\gtx_channel.gtxe2_channel_i_i_12__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => \cplllock_reg1_reg[2]\
    );
\gtx_channel.gtxe2_channel_i_i_13__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[2]_1\
    );
\gtx_channel.gtxe2_channel_i_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[2]_0\
    );
\gtx_channel.gtxe2_channel_i_i_57\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(0),
      I1 => \^pipe_sync_fsm_rx\(1),
      I2 => \^pipe_sync_fsm_rx\(6),
      I3 => \^pipe_sync_fsm_rx\(4),
      O => \gtx_channel.gtxe2_channel_i_i_57_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_9__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(2),
      I1 => \^pipe_sync_fsm_rx\(3),
      I2 => \^pipe_sync_fsm_rx\(5),
      I3 => \gtx_channel.gtxe2_channel_i_i_57_n_0\,
      O => \cplllock_reg1_reg[2]_3\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_CPLLRESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_CPLLRESET
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXDLYSRESETDONE0,
      Q => rxdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gt_rx_elec_idle_wire_filter(0),
      Q => rxelecidle_reg1,
      R => RST_CPLLRESET
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXPHALIGNDONE_M,
      Q => rxphaligndone_m_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXPHALIGNDONE_S,
      Q => rxphaligndone_s_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => RST_CPLLRESET
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_DONEM_IN,
      Q => rxsync_donem_reg1,
      R => RST_CPLLRESET
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => RST_CPLLRESET
    );
\rxsync_fsm_disable.fsm_rx_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '1',
      Q => \^pipe_sync_fsm_rx\(0),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(1),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(2),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(3),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(4),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(5),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(6),
      R => '0'
    );
\rxsync_fsm_disable.rxdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => SYNC_RXDLYEN,
      R => '0'
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_START,
      Q => rxsync_start_reg1,
      R => RST_CPLLRESET
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => RST_CPLLRESET
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxsyncdone_reg1,
      R => RST_CPLLRESET
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXDLYSRESETDONE0,
      Q => txdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXPHALIGNDONE,
      Q => txphaligndone_reg1,
      R => RST_CPLLRESET
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => RST_CPLLRESET
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXPHINITDONE,
      Q => txphinitdone_reg1,
      R => RST_CPLLRESET
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => RST_CPLLRESET
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F2FF"
    )
        port map (
      I0 => \^q\(0),
      I1 => txsync_start_reg2,
      I2 => \^q\(5),
      I3 => \txsync_fsm.fsm_tx[5]_i_2__1_n_0\,
      O => fsm_tx(0)
    );
\txsync_fsm.fsm_tx[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__1_n_0\,
      I1 => \^q\(0),
      I2 => txsync_start_reg2,
      I3 => \^q\(1),
      I4 => mmcm_lock_reg2,
      O => fsm_tx(1)
    );
\txsync_fsm.fsm_tx[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA80AA80808080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__1_n_0\,
      I1 => \^q\(1),
      I2 => mmcm_lock_reg2,
      I3 => txdlysresetdone_reg2,
      I4 => txdlysresetdone_reg3,
      I5 => \^q\(2),
      O => fsm_tx(2)
    );
\txsync_fsm.fsm_tx[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00800080AAAA0080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__1_n_0\,
      I1 => \^q\(2),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(3),
      I5 => \txsync_fsm.fsm_tx[4]_i_2__1_n_0\,
      O => fsm_tx(3)
    );
\txsync_fsm.fsm_tx[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__1_n_0\,
      I1 => \txsync_fsm.fsm_tx[4]_i_2__1_n_0\,
      I2 => \^q\(3),
      I3 => \^q\(4),
      I4 => \txsync_fsm.fsm_tx[4]_i_3__1_n_0\,
      O => fsm_tx(4)
    );
\txsync_fsm.fsm_tx[4]_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F222"
    )
        port map (
      I0 => txphinitdone_reg2,
      I1 => txphinitdone_reg3,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_2__1_n_0\
    );
\txsync_fsm.fsm_tx[4]_i_3__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => txphaligndone_reg3,
      I1 => txphaligndone_reg2,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_3__1_n_0\
    );
\txsync_fsm.fsm_tx[5]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA20202000000000"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__1_n_0\,
      I1 => txphaligndone_reg3,
      I2 => txphaligndone_reg2,
      I3 => p_0_in7_in,
      I4 => p_1_in8_in,
      I5 => \^q\(4),
      O => fsm_tx(5)
    );
\txsync_fsm.fsm_tx[5]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => \txsync_fsm.fsm_tx[5]_i_2__1_n_0\
    );
\txsync_fsm.fsm_tx_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(1),
      Q => \^q\(1),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(5),
      Q => \^q\(5),
      R => RST_CPLLRESET
    );
\txsync_fsm.txdlyen_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \txsync_fsm.txdlyen_i_2__1_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(5),
      I4 => \^txsync_fsm.txdlyen_reg_0\,
      O => \txsync_fsm.txdlyen_i_1__1_n_0\
    );
\txsync_fsm.txdlyen_i_2__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_start_reg2,
      O => \txsync_fsm.txdlyen_i_2__1_n_0\
    );
\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txdlyen_i_1__1_n_0\,
      Q => \^txsync_fsm.txdlyen_reg_0\,
      R => RST_CPLLRESET
    );
\txsync_fsm.txsync_done_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAA8"
    )
        port map (
      I0 => txsync_done,
      I1 => \txsync_fsm.txdlyen_i_2__1_n_0\,
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^rst_txsync_done\(0),
      O => \txsync_fsm.txsync_done_i_1__0_n_0\
    );
\txsync_fsm.txsync_done_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => txsync_done
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1__0_n_0\,
      Q => \^rst_txsync_done\(0),
      R => RST_CPLLRESET
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => RST_CPLLRESET
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => RST_CPLLRESET
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => RST_CPLLRESET
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txsyncdone_reg1,
      R => RST_CPLLRESET
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => RST_CPLLRESET
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_45 is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \txsync_fsm.txdlyen_reg_0\ : out STD_LOGIC;
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 6 downto 0 );
    SYNC_RXDLYEN : out STD_LOGIC;
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    \cplllock_reg1_reg[3]_0\ : out STD_LOGIC;
    \cplllock_reg1_reg[3]_1\ : out STD_LOGIC;
    \cplllock_reg1_reg[3]_2\ : out STD_LOGIC;
    \cplllock_reg1_reg[3]_3\ : out STD_LOGIC;
    RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in7_in : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    SYNC_TXDLYSRESETDONE0 : in STD_LOGIC;
    txelecidle_reg2_reg : in STD_LOGIC;
    txsyncallin : in STD_LOGIC;
    SYNC_RXSYNC_DONEM_IN : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC;
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_RXSYNC_START : in STD_LOGIC;
    SYNC_RXDLYSRESETDONE0 : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_45 : entity is "PCIeGen1x8If64_pipe_sync";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_45;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_45 is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal fsm_tx : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_57__0_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^pipe_sync_fsm_rx\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  signal rxelecidle_reg1 : STD_LOGIC;
  signal rxelecidle_reg2 : STD_LOGIC;
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  signal rxsync_donem_reg1 : STD_LOGIC;
  signal rxsync_donem_reg2 : STD_LOGIC;
  signal rxsync_start_reg1 : STD_LOGIC;
  signal rxsync_start_reg2 : STD_LOGIC;
  signal rxsyncdone_reg1 : STD_LOGIC;
  signal rxsyncdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg1 : STD_LOGIC;
  signal txdlysresetdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg3 : STD_LOGIC;
  signal txphaligndone_reg1 : STD_LOGIC;
  signal txphaligndone_reg2 : STD_LOGIC;
  signal txphaligndone_reg3 : STD_LOGIC;
  signal txphinitdone_reg1 : STD_LOGIC;
  signal txphinitdone_reg2 : STD_LOGIC;
  signal txphinitdone_reg3 : STD_LOGIC;
  signal txsync_done : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_3__2_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[5]_i_2__2_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_1__2_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_2__2_n_0\ : STD_LOGIC;
  signal \^txsync_fsm.txdlyen_reg_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_1__1_n_0\ : STD_LOGIC;
  signal txsync_start_reg1 : STD_LOGIC;
  signal txsync_start_reg2 : STD_LOGIC;
  signal txsync_start_reg3 : STD_LOGIC;
  signal txsyncdone_reg1 : STD_LOGIC;
  signal txsyncdone_reg2 : STD_LOGIC;
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
  RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0);
  pipe_sync_fsm_rx(6 downto 0) <= \^pipe_sync_fsm_rx\(6 downto 0);
  \txsync_fsm.txdlyen_reg_0\ <= \^txsync_fsm.txdlyen_reg_0\;
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_10__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => rxsync_donem_reg2,
      I1 => \^pipe_sync_fsm_rx\(5),
      I2 => \^pipe_sync_fsm_rx\(3),
      I3 => \^pipe_sync_fsm_rx\(2),
      I4 => \gtx_channel.gtxe2_channel_i_i_57__0_n_0\,
      O => \cplllock_reg1_reg[3]_2\
    );
\gtx_channel.gtxe2_channel_i_i_12__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => \cplllock_reg1_reg[3]\
    );
\gtx_channel.gtxe2_channel_i_i_13__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[3]_1\
    );
\gtx_channel.gtxe2_channel_i_i_14__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[3]_0\
    );
\gtx_channel.gtxe2_channel_i_i_57__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(0),
      I1 => \^pipe_sync_fsm_rx\(1),
      I2 => \^pipe_sync_fsm_rx\(6),
      I3 => \^pipe_sync_fsm_rx\(4),
      O => \gtx_channel.gtxe2_channel_i_i_57__0_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_9__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(2),
      I1 => \^pipe_sync_fsm_rx\(3),
      I2 => \^pipe_sync_fsm_rx\(5),
      I3 => \gtx_channel.gtxe2_channel_i_i_57__0_n_0\,
      O => \cplllock_reg1_reg[3]_3\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_CPLLRESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_CPLLRESET
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXDLYSRESETDONE0,
      Q => rxdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gt_rx_elec_idle_wire_filter(0),
      Q => rxelecidle_reg1,
      R => RST_CPLLRESET
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxphaligndone_m_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxphaligndone_s_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => RST_CPLLRESET
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_DONEM_IN,
      Q => rxsync_donem_reg1,
      R => RST_CPLLRESET
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => RST_CPLLRESET
    );
\rxsync_fsm_disable.fsm_rx_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '1',
      Q => \^pipe_sync_fsm_rx\(0),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(1),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(2),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(3),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(4),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(5),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(6),
      R => '0'
    );
\rxsync_fsm_disable.rxdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => SYNC_RXDLYEN,
      R => '0'
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_START,
      Q => rxsync_start_reg1,
      R => RST_CPLLRESET
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => RST_CPLLRESET
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxsyncdone_reg1,
      R => RST_CPLLRESET
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXDLYSRESETDONE0,
      Q => txdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncallin,
      Q => txphaligndone_reg1,
      R => RST_CPLLRESET
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => RST_CPLLRESET
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg2_reg,
      Q => txphinitdone_reg1,
      R => RST_CPLLRESET
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => RST_CPLLRESET
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F2FF"
    )
        port map (
      I0 => \^q\(0),
      I1 => txsync_start_reg2,
      I2 => \^q\(5),
      I3 => \txsync_fsm.fsm_tx[5]_i_2__2_n_0\,
      O => fsm_tx(0)
    );
\txsync_fsm.fsm_tx[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__2_n_0\,
      I1 => \^q\(0),
      I2 => txsync_start_reg2,
      I3 => \^q\(1),
      I4 => mmcm_lock_reg2,
      O => fsm_tx(1)
    );
\txsync_fsm.fsm_tx[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA80AA80808080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__2_n_0\,
      I1 => \^q\(1),
      I2 => mmcm_lock_reg2,
      I3 => txdlysresetdone_reg2,
      I4 => txdlysresetdone_reg3,
      I5 => \^q\(2),
      O => fsm_tx(2)
    );
\txsync_fsm.fsm_tx[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00800080AAAA0080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__2_n_0\,
      I1 => \^q\(2),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(3),
      I5 => \txsync_fsm.fsm_tx[4]_i_2__2_n_0\,
      O => fsm_tx(3)
    );
\txsync_fsm.fsm_tx[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__2_n_0\,
      I1 => \txsync_fsm.fsm_tx[4]_i_2__2_n_0\,
      I2 => \^q\(3),
      I3 => \^q\(4),
      I4 => \txsync_fsm.fsm_tx[4]_i_3__2_n_0\,
      O => fsm_tx(4)
    );
\txsync_fsm.fsm_tx[4]_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F222"
    )
        port map (
      I0 => txphinitdone_reg2,
      I1 => txphinitdone_reg3,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_2__2_n_0\
    );
\txsync_fsm.fsm_tx[4]_i_3__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => txphaligndone_reg3,
      I1 => txphaligndone_reg2,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_3__2_n_0\
    );
\txsync_fsm.fsm_tx[5]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA20202000000000"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__2_n_0\,
      I1 => txphaligndone_reg3,
      I2 => txphaligndone_reg2,
      I3 => p_0_in7_in,
      I4 => p_1_in8_in,
      I5 => \^q\(4),
      O => fsm_tx(5)
    );
\txsync_fsm.fsm_tx[5]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => \txsync_fsm.fsm_tx[5]_i_2__2_n_0\
    );
\txsync_fsm.fsm_tx_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(1),
      Q => \^q\(1),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(5),
      Q => \^q\(5),
      R => RST_CPLLRESET
    );
\txsync_fsm.txdlyen_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \txsync_fsm.txdlyen_i_2__2_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(5),
      I4 => \^txsync_fsm.txdlyen_reg_0\,
      O => \txsync_fsm.txdlyen_i_1__2_n_0\
    );
\txsync_fsm.txdlyen_i_2__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_start_reg2,
      O => \txsync_fsm.txdlyen_i_2__2_n_0\
    );
\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txdlyen_i_1__2_n_0\,
      Q => \^txsync_fsm.txdlyen_reg_0\,
      R => RST_CPLLRESET
    );
\txsync_fsm.txsync_done_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAA8"
    )
        port map (
      I0 => txsync_done,
      I1 => \txsync_fsm.txdlyen_i_2__2_n_0\,
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^rst_txsync_done\(0),
      O => \txsync_fsm.txsync_done_i_1__1_n_0\
    );
\txsync_fsm.txsync_done_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => txsync_done
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1__1_n_0\,
      Q => \^rst_txsync_done\(0),
      R => RST_CPLLRESET
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => RST_CPLLRESET
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => RST_CPLLRESET
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => RST_CPLLRESET
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txsyncdone_reg1,
      R => RST_CPLLRESET
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => RST_CPLLRESET
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_52 is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \txsync_fsm.txdlyen_reg_0\ : out STD_LOGIC;
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 6 downto 0 );
    SYNC_RXDLYEN : out STD_LOGIC;
    \cplllock_reg1_reg[4]\ : out STD_LOGIC;
    \cplllock_reg1_reg[4]_0\ : out STD_LOGIC;
    \cplllock_reg1_reg[4]_1\ : out STD_LOGIC;
    \cplllock_reg1_reg[4]_2\ : out STD_LOGIC;
    \cplllock_reg1_reg[4]_3\ : out STD_LOGIC;
    RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in7_in : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    SYNC_TXDLYSRESETDONE0 : in STD_LOGIC;
    txelecidle_reg2_reg : in STD_LOGIC;
    txsyncallin : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]_0\ : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC;
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_RXSYNC_START : in STD_LOGIC;
    SYNC_RXDLYSRESETDONE0 : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_52 : entity is "PCIeGen1x8If64_pipe_sync";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_52;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_52 is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal fsm_tx : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_56__1_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^pipe_sync_fsm_rx\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  signal rxelecidle_reg1 : STD_LOGIC;
  signal rxelecidle_reg2 : STD_LOGIC;
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  signal rxsync_donem_reg1 : STD_LOGIC;
  signal rxsync_donem_reg2 : STD_LOGIC;
  signal rxsync_start_reg1 : STD_LOGIC;
  signal rxsync_start_reg2 : STD_LOGIC;
  signal rxsyncdone_reg1 : STD_LOGIC;
  signal rxsyncdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg1 : STD_LOGIC;
  signal txdlysresetdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg3 : STD_LOGIC;
  signal txphaligndone_reg1 : STD_LOGIC;
  signal txphaligndone_reg2 : STD_LOGIC;
  signal txphaligndone_reg3 : STD_LOGIC;
  signal txphinitdone_reg1 : STD_LOGIC;
  signal txphinitdone_reg2 : STD_LOGIC;
  signal txphinitdone_reg3 : STD_LOGIC;
  signal txsync_done : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_3__3_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[5]_i_2__3_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_1__3_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_2__3_n_0\ : STD_LOGIC;
  signal \^txsync_fsm.txdlyen_reg_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_1__2_n_0\ : STD_LOGIC;
  signal txsync_start_reg1 : STD_LOGIC;
  signal txsync_start_reg2 : STD_LOGIC;
  signal txsync_start_reg3 : STD_LOGIC;
  signal txsyncdone_reg1 : STD_LOGIC;
  signal txsyncdone_reg2 : STD_LOGIC;
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
  RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0);
  pipe_sync_fsm_rx(6 downto 0) <= \^pipe_sync_fsm_rx\(6 downto 0);
  \txsync_fsm.txdlyen_reg_0\ <= \^txsync_fsm.txdlyen_reg_0\;
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_11__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => \cplllock_reg1_reg[4]\
    );
\gtx_channel.gtxe2_channel_i_i_12__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[4]_1\
    );
\gtx_channel.gtxe2_channel_i_i_13__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[4]_0\
    );
\gtx_channel.gtxe2_channel_i_i_56__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(0),
      I1 => \^pipe_sync_fsm_rx\(1),
      I2 => \^pipe_sync_fsm_rx\(6),
      I3 => \^pipe_sync_fsm_rx\(4),
      O => \gtx_channel.gtxe2_channel_i_i_56__1_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_8__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(2),
      I1 => \^pipe_sync_fsm_rx\(3),
      I2 => \^pipe_sync_fsm_rx\(5),
      I3 => \gtx_channel.gtxe2_channel_i_i_56__1_n_0\,
      O => \cplllock_reg1_reg[4]_3\
    );
\gtx_channel.gtxe2_channel_i_i_9__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => rxsync_donem_reg2,
      I1 => \^pipe_sync_fsm_rx\(5),
      I2 => \^pipe_sync_fsm_rx\(3),
      I3 => \^pipe_sync_fsm_rx\(2),
      I4 => \gtx_channel.gtxe2_channel_i_i_56__1_n_0\,
      O => \cplllock_reg1_reg[4]_2\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_CPLLRESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_CPLLRESET
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXDLYSRESETDONE0,
      Q => rxdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gt_rx_elec_idle_wire_filter(0),
      Q => rxelecidle_reg1,
      R => RST_CPLLRESET
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxphaligndone_m_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxphaligndone_s_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => RST_CPLLRESET
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxsync_fsm_disable.fsm_rx_reg[2]_0\,
      Q => rxsync_donem_reg1,
      R => RST_CPLLRESET
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => RST_CPLLRESET
    );
\rxsync_fsm_disable.fsm_rx_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '1',
      Q => \^pipe_sync_fsm_rx\(0),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(1),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(2),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(3),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(4),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(5),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(6),
      R => '0'
    );
\rxsync_fsm_disable.rxdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => SYNC_RXDLYEN,
      R => '0'
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_START,
      Q => rxsync_start_reg1,
      R => RST_CPLLRESET
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => RST_CPLLRESET
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxsyncdone_reg1,
      R => RST_CPLLRESET
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXDLYSRESETDONE0,
      Q => txdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncallin,
      Q => txphaligndone_reg1,
      R => RST_CPLLRESET
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => RST_CPLLRESET
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg2_reg,
      Q => txphinitdone_reg1,
      R => RST_CPLLRESET
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => RST_CPLLRESET
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx[0]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F2FF"
    )
        port map (
      I0 => \^q\(0),
      I1 => txsync_start_reg2,
      I2 => \^q\(5),
      I3 => \txsync_fsm.fsm_tx[5]_i_2__3_n_0\,
      O => fsm_tx(0)
    );
\txsync_fsm.fsm_tx[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__3_n_0\,
      I1 => \^q\(0),
      I2 => txsync_start_reg2,
      I3 => \^q\(1),
      I4 => mmcm_lock_reg2,
      O => fsm_tx(1)
    );
\txsync_fsm.fsm_tx[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA80AA80808080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__3_n_0\,
      I1 => \^q\(1),
      I2 => mmcm_lock_reg2,
      I3 => txdlysresetdone_reg2,
      I4 => txdlysresetdone_reg3,
      I5 => \^q\(2),
      O => fsm_tx(2)
    );
\txsync_fsm.fsm_tx[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00800080AAAA0080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__3_n_0\,
      I1 => \^q\(2),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(3),
      I5 => \txsync_fsm.fsm_tx[4]_i_2__3_n_0\,
      O => fsm_tx(3)
    );
\txsync_fsm.fsm_tx[4]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__3_n_0\,
      I1 => \txsync_fsm.fsm_tx[4]_i_2__3_n_0\,
      I2 => \^q\(3),
      I3 => \^q\(4),
      I4 => \txsync_fsm.fsm_tx[4]_i_3__3_n_0\,
      O => fsm_tx(4)
    );
\txsync_fsm.fsm_tx[4]_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F222"
    )
        port map (
      I0 => txphinitdone_reg2,
      I1 => txphinitdone_reg3,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_2__3_n_0\
    );
\txsync_fsm.fsm_tx[4]_i_3__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => txphaligndone_reg3,
      I1 => txphaligndone_reg2,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_3__3_n_0\
    );
\txsync_fsm.fsm_tx[5]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA20202000000000"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__3_n_0\,
      I1 => txphaligndone_reg3,
      I2 => txphaligndone_reg2,
      I3 => p_0_in7_in,
      I4 => p_1_in8_in,
      I5 => \^q\(4),
      O => fsm_tx(5)
    );
\txsync_fsm.fsm_tx[5]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => \txsync_fsm.fsm_tx[5]_i_2__3_n_0\
    );
\txsync_fsm.fsm_tx_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(1),
      Q => \^q\(1),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(5),
      Q => \^q\(5),
      R => RST_CPLLRESET
    );
\txsync_fsm.txdlyen_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \txsync_fsm.txdlyen_i_2__3_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(5),
      I4 => \^txsync_fsm.txdlyen_reg_0\,
      O => \txsync_fsm.txdlyen_i_1__3_n_0\
    );
\txsync_fsm.txdlyen_i_2__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_start_reg2,
      O => \txsync_fsm.txdlyen_i_2__3_n_0\
    );
\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txdlyen_i_1__3_n_0\,
      Q => \^txsync_fsm.txdlyen_reg_0\,
      R => RST_CPLLRESET
    );
\txsync_fsm.txsync_done_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAA8"
    )
        port map (
      I0 => txsync_done,
      I1 => \txsync_fsm.txdlyen_i_2__3_n_0\,
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^rst_txsync_done\(0),
      O => \txsync_fsm.txsync_done_i_1__2_n_0\
    );
\txsync_fsm.txsync_done_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => txsync_done
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1__2_n_0\,
      Q => \^rst_txsync_done\(0),
      R => RST_CPLLRESET
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => RST_CPLLRESET
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => RST_CPLLRESET
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => RST_CPLLRESET
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txsyncdone_reg1,
      R => RST_CPLLRESET
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => RST_CPLLRESET
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_58 is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \txsync_fsm.txdlyen_reg_0\ : out STD_LOGIC;
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 6 downto 0 );
    SYNC_RXDLYEN : out STD_LOGIC;
    \cplllock_reg1_reg[5]\ : out STD_LOGIC;
    \cplllock_reg1_reg[5]_0\ : out STD_LOGIC;
    \cplllock_reg1_reg[5]_1\ : out STD_LOGIC;
    \cplllock_reg1_reg[5]_2\ : out STD_LOGIC;
    \cplllock_reg1_reg[5]_3\ : out STD_LOGIC;
    RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in7_in : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    SYNC_TXDLYSRESETDONE0 : in STD_LOGIC;
    txelecidle_reg2_reg : in STD_LOGIC;
    txsyncallin : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]_0\ : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC;
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_RXSYNC_START : in STD_LOGIC;
    SYNC_RXDLYSRESETDONE0 : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_58 : entity is "PCIeGen1x8If64_pipe_sync";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_58;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_58 is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal fsm_tx : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_56__2_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^pipe_sync_fsm_rx\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  signal rxelecidle_reg1 : STD_LOGIC;
  signal rxelecidle_reg2 : STD_LOGIC;
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  signal rxsync_donem_reg1 : STD_LOGIC;
  signal rxsync_donem_reg2 : STD_LOGIC;
  signal rxsync_start_reg1 : STD_LOGIC;
  signal rxsync_start_reg2 : STD_LOGIC;
  signal rxsyncdone_reg1 : STD_LOGIC;
  signal rxsyncdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg1 : STD_LOGIC;
  signal txdlysresetdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg3 : STD_LOGIC;
  signal txphaligndone_reg1 : STD_LOGIC;
  signal txphaligndone_reg2 : STD_LOGIC;
  signal txphaligndone_reg3 : STD_LOGIC;
  signal txphinitdone_reg1 : STD_LOGIC;
  signal txphinitdone_reg2 : STD_LOGIC;
  signal txphinitdone_reg3 : STD_LOGIC;
  signal txsync_done : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_3__4_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[5]_i_2__4_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_1__4_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_2__4_n_0\ : STD_LOGIC;
  signal \^txsync_fsm.txdlyen_reg_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_1__3_n_0\ : STD_LOGIC;
  signal txsync_start_reg1 : STD_LOGIC;
  signal txsync_start_reg2 : STD_LOGIC;
  signal txsync_start_reg3 : STD_LOGIC;
  signal txsyncdone_reg1 : STD_LOGIC;
  signal txsyncdone_reg2 : STD_LOGIC;
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
  RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0);
  pipe_sync_fsm_rx(6 downto 0) <= \^pipe_sync_fsm_rx\(6 downto 0);
  \txsync_fsm.txdlyen_reg_0\ <= \^txsync_fsm.txdlyen_reg_0\;
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_11__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => \cplllock_reg1_reg[5]\
    );
\gtx_channel.gtxe2_channel_i_i_12__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[5]_1\
    );
\gtx_channel.gtxe2_channel_i_i_13__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[5]_0\
    );
\gtx_channel.gtxe2_channel_i_i_56__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(0),
      I1 => \^pipe_sync_fsm_rx\(1),
      I2 => \^pipe_sync_fsm_rx\(6),
      I3 => \^pipe_sync_fsm_rx\(4),
      O => \gtx_channel.gtxe2_channel_i_i_56__2_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_8__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(2),
      I1 => \^pipe_sync_fsm_rx\(3),
      I2 => \^pipe_sync_fsm_rx\(5),
      I3 => \gtx_channel.gtxe2_channel_i_i_56__2_n_0\,
      O => \cplllock_reg1_reg[5]_3\
    );
\gtx_channel.gtxe2_channel_i_i_9__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => rxsync_donem_reg2,
      I1 => \^pipe_sync_fsm_rx\(5),
      I2 => \^pipe_sync_fsm_rx\(3),
      I3 => \^pipe_sync_fsm_rx\(2),
      I4 => \gtx_channel.gtxe2_channel_i_i_56__2_n_0\,
      O => \cplllock_reg1_reg[5]_2\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_CPLLRESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_CPLLRESET
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXDLYSRESETDONE0,
      Q => rxdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gt_rx_elec_idle_wire_filter(0),
      Q => rxelecidle_reg1,
      R => RST_CPLLRESET
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxphaligndone_m_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxphaligndone_s_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => RST_CPLLRESET
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxsync_fsm_disable.fsm_rx_reg[2]_0\,
      Q => rxsync_donem_reg1,
      R => RST_CPLLRESET
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => RST_CPLLRESET
    );
\rxsync_fsm_disable.fsm_rx_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '1',
      Q => \^pipe_sync_fsm_rx\(0),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(1),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(2),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(3),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(4),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(5),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(6),
      R => '0'
    );
\rxsync_fsm_disable.rxdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => SYNC_RXDLYEN,
      R => '0'
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_START,
      Q => rxsync_start_reg1,
      R => RST_CPLLRESET
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => RST_CPLLRESET
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxsyncdone_reg1,
      R => RST_CPLLRESET
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXDLYSRESETDONE0,
      Q => txdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncallin,
      Q => txphaligndone_reg1,
      R => RST_CPLLRESET
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => RST_CPLLRESET
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg2_reg,
      Q => txphinitdone_reg1,
      R => RST_CPLLRESET
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => RST_CPLLRESET
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx[0]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F2FF"
    )
        port map (
      I0 => \^q\(0),
      I1 => txsync_start_reg2,
      I2 => \^q\(5),
      I3 => \txsync_fsm.fsm_tx[5]_i_2__4_n_0\,
      O => fsm_tx(0)
    );
\txsync_fsm.fsm_tx[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__4_n_0\,
      I1 => \^q\(0),
      I2 => txsync_start_reg2,
      I3 => \^q\(1),
      I4 => mmcm_lock_reg2,
      O => fsm_tx(1)
    );
\txsync_fsm.fsm_tx[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA80AA80808080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__4_n_0\,
      I1 => \^q\(1),
      I2 => mmcm_lock_reg2,
      I3 => txdlysresetdone_reg2,
      I4 => txdlysresetdone_reg3,
      I5 => \^q\(2),
      O => fsm_tx(2)
    );
\txsync_fsm.fsm_tx[3]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00800080AAAA0080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__4_n_0\,
      I1 => \^q\(2),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(3),
      I5 => \txsync_fsm.fsm_tx[4]_i_2__4_n_0\,
      O => fsm_tx(3)
    );
\txsync_fsm.fsm_tx[4]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__4_n_0\,
      I1 => \txsync_fsm.fsm_tx[4]_i_2__4_n_0\,
      I2 => \^q\(3),
      I3 => \^q\(4),
      I4 => \txsync_fsm.fsm_tx[4]_i_3__4_n_0\,
      O => fsm_tx(4)
    );
\txsync_fsm.fsm_tx[4]_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F222"
    )
        port map (
      I0 => txphinitdone_reg2,
      I1 => txphinitdone_reg3,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_2__4_n_0\
    );
\txsync_fsm.fsm_tx[4]_i_3__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => txphaligndone_reg3,
      I1 => txphaligndone_reg2,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_3__4_n_0\
    );
\txsync_fsm.fsm_tx[5]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA20202000000000"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__4_n_0\,
      I1 => txphaligndone_reg3,
      I2 => txphaligndone_reg2,
      I3 => p_0_in7_in,
      I4 => p_1_in8_in,
      I5 => \^q\(4),
      O => fsm_tx(5)
    );
\txsync_fsm.fsm_tx[5]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => \txsync_fsm.fsm_tx[5]_i_2__4_n_0\
    );
\txsync_fsm.fsm_tx_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(1),
      Q => \^q\(1),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(5),
      Q => \^q\(5),
      R => RST_CPLLRESET
    );
\txsync_fsm.txdlyen_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \txsync_fsm.txdlyen_i_2__4_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(5),
      I4 => \^txsync_fsm.txdlyen_reg_0\,
      O => \txsync_fsm.txdlyen_i_1__4_n_0\
    );
\txsync_fsm.txdlyen_i_2__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_start_reg2,
      O => \txsync_fsm.txdlyen_i_2__4_n_0\
    );
\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txdlyen_i_1__4_n_0\,
      Q => \^txsync_fsm.txdlyen_reg_0\,
      R => RST_CPLLRESET
    );
\txsync_fsm.txsync_done_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAA8"
    )
        port map (
      I0 => txsync_done,
      I1 => \txsync_fsm.txdlyen_i_2__4_n_0\,
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^rst_txsync_done\(0),
      O => \txsync_fsm.txsync_done_i_1__3_n_0\
    );
\txsync_fsm.txsync_done_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => txsync_done
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1__3_n_0\,
      Q => \^rst_txsync_done\(0),
      R => RST_CPLLRESET
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => RST_CPLLRESET
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => RST_CPLLRESET
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => RST_CPLLRESET
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txsyncdone_reg1,
      R => RST_CPLLRESET
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => RST_CPLLRESET
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_64 is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \txsync_fsm.txdlyen_reg_0\ : out STD_LOGIC;
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 6 downto 0 );
    SYNC_RXDLYEN : out STD_LOGIC;
    \cplllock_reg1_reg[6]\ : out STD_LOGIC;
    \cplllock_reg1_reg[6]_0\ : out STD_LOGIC;
    \cplllock_reg1_reg[6]_1\ : out STD_LOGIC;
    \cplllock_reg1_reg[6]_2\ : out STD_LOGIC;
    \cplllock_reg1_reg[6]_3\ : out STD_LOGIC;
    RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in7_in : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    txelecidle_reg2_reg : in STD_LOGIC;
    txsyncallin : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]_0\ : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC;
    SYNC_RATE_IDLE : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_RXSYNC_START : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_2\ : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_64 : entity is "PCIeGen1x8If64_pipe_sync";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_64;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_64 is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal fsm_tx : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_57__1_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^pipe_sync_fsm_rx\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  signal rxelecidle_reg1 : STD_LOGIC;
  signal rxelecidle_reg2 : STD_LOGIC;
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  signal rxsync_donem_reg1 : STD_LOGIC;
  signal rxsync_donem_reg2 : STD_LOGIC;
  signal rxsync_start_reg1 : STD_LOGIC;
  signal rxsync_start_reg2 : STD_LOGIC;
  signal rxsyncdone_reg1 : STD_LOGIC;
  signal rxsyncdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg1 : STD_LOGIC;
  signal txdlysresetdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg3 : STD_LOGIC;
  signal txphaligndone_reg1 : STD_LOGIC;
  signal txphaligndone_reg2 : STD_LOGIC;
  signal txphaligndone_reg3 : STD_LOGIC;
  signal txphinitdone_reg1 : STD_LOGIC;
  signal txphinitdone_reg2 : STD_LOGIC;
  signal txphinitdone_reg3 : STD_LOGIC;
  signal txsync_done : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_3__5_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[5]_i_2__5_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_1__5_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_2__5_n_0\ : STD_LOGIC;
  signal \^txsync_fsm.txdlyen_reg_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_1__4_n_0\ : STD_LOGIC;
  signal txsync_start_reg1 : STD_LOGIC;
  signal txsync_start_reg2 : STD_LOGIC;
  signal txsync_start_reg3 : STD_LOGIC;
  signal txsyncdone_reg1 : STD_LOGIC;
  signal txsyncdone_reg2 : STD_LOGIC;
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
  RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0);
  pipe_sync_fsm_rx(6 downto 0) <= \^pipe_sync_fsm_rx\(6 downto 0);
  \txsync_fsm.txdlyen_reg_0\ <= \^txsync_fsm.txdlyen_reg_0\;
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_10__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => rxsync_donem_reg2,
      I1 => \^pipe_sync_fsm_rx\(5),
      I2 => \^pipe_sync_fsm_rx\(3),
      I3 => \^pipe_sync_fsm_rx\(2),
      I4 => \gtx_channel.gtxe2_channel_i_i_57__1_n_0\,
      O => \cplllock_reg1_reg[6]_2\
    );
\gtx_channel.gtxe2_channel_i_i_12__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => \cplllock_reg1_reg[6]\
    );
\gtx_channel.gtxe2_channel_i_i_13__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[6]_1\
    );
\gtx_channel.gtxe2_channel_i_i_14__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[6]_0\
    );
\gtx_channel.gtxe2_channel_i_i_57__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(0),
      I1 => \^pipe_sync_fsm_rx\(1),
      I2 => \^pipe_sync_fsm_rx\(6),
      I3 => \^pipe_sync_fsm_rx\(4),
      O => \gtx_channel.gtxe2_channel_i_i_57__1_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_9__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(2),
      I1 => \^pipe_sync_fsm_rx\(3),
      I2 => \^pipe_sync_fsm_rx\(5),
      I3 => \gtx_channel.gtxe2_channel_i_i_57__1_n_0\,
      O => \cplllock_reg1_reg[6]_3\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RATE_IDLE,
      Q => rate_idle_reg1,
      R => RST_CPLLRESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_CPLLRESET
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gt_rx_elec_idle_wire_filter(0),
      Q => rxelecidle_reg1,
      R => RST_CPLLRESET
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_2\,
      Q => rxphaligndone_m_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_3\,
      Q => rxphaligndone_s_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => RST_CPLLRESET
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxsync_fsm_disable.fsm_rx_reg[2]_0\,
      Q => rxsync_donem_reg1,
      R => RST_CPLLRESET
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => RST_CPLLRESET
    );
\rxsync_fsm_disable.fsm_rx_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '1',
      Q => \^pipe_sync_fsm_rx\(0),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(1),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(2),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(3),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(4),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(5),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(6),
      R => '0'
    );
\rxsync_fsm_disable.rxdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => SYNC_RXDLYEN,
      R => '0'
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_START,
      Q => rxsync_start_reg1,
      R => RST_CPLLRESET
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => RST_CPLLRESET
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxsyncdone_reg1,
      R => RST_CPLLRESET
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => txdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncallin,
      Q => txphaligndone_reg1,
      R => RST_CPLLRESET
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => RST_CPLLRESET
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg2_reg,
      Q => txphinitdone_reg1,
      R => RST_CPLLRESET
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => RST_CPLLRESET
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx[0]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F2FF"
    )
        port map (
      I0 => \^q\(0),
      I1 => txsync_start_reg2,
      I2 => \^q\(5),
      I3 => \txsync_fsm.fsm_tx[5]_i_2__5_n_0\,
      O => fsm_tx(0)
    );
\txsync_fsm.fsm_tx[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__5_n_0\,
      I1 => \^q\(0),
      I2 => txsync_start_reg2,
      I3 => \^q\(1),
      I4 => mmcm_lock_reg2,
      O => fsm_tx(1)
    );
\txsync_fsm.fsm_tx[2]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA80AA80808080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__5_n_0\,
      I1 => \^q\(1),
      I2 => mmcm_lock_reg2,
      I3 => txdlysresetdone_reg2,
      I4 => txdlysresetdone_reg3,
      I5 => \^q\(2),
      O => fsm_tx(2)
    );
\txsync_fsm.fsm_tx[3]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00800080AAAA0080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__5_n_0\,
      I1 => \^q\(2),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(3),
      I5 => \txsync_fsm.fsm_tx[4]_i_2__5_n_0\,
      O => fsm_tx(3)
    );
\txsync_fsm.fsm_tx[4]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__5_n_0\,
      I1 => \txsync_fsm.fsm_tx[4]_i_2__5_n_0\,
      I2 => \^q\(3),
      I3 => \^q\(4),
      I4 => \txsync_fsm.fsm_tx[4]_i_3__5_n_0\,
      O => fsm_tx(4)
    );
\txsync_fsm.fsm_tx[4]_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F222"
    )
        port map (
      I0 => txphinitdone_reg2,
      I1 => txphinitdone_reg3,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_2__5_n_0\
    );
\txsync_fsm.fsm_tx[4]_i_3__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => txphaligndone_reg3,
      I1 => txphaligndone_reg2,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_3__5_n_0\
    );
\txsync_fsm.fsm_tx[5]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA20202000000000"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__5_n_0\,
      I1 => txphaligndone_reg3,
      I2 => txphaligndone_reg2,
      I3 => p_0_in7_in,
      I4 => p_1_in8_in,
      I5 => \^q\(4),
      O => fsm_tx(5)
    );
\txsync_fsm.fsm_tx[5]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => \txsync_fsm.fsm_tx[5]_i_2__5_n_0\
    );
\txsync_fsm.fsm_tx_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(1),
      Q => \^q\(1),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(5),
      Q => \^q\(5),
      R => RST_CPLLRESET
    );
\txsync_fsm.txdlyen_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \txsync_fsm.txdlyen_i_2__5_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(5),
      I4 => \^txsync_fsm.txdlyen_reg_0\,
      O => \txsync_fsm.txdlyen_i_1__5_n_0\
    );
\txsync_fsm.txdlyen_i_2__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_start_reg2,
      O => \txsync_fsm.txdlyen_i_2__5_n_0\
    );
\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txdlyen_i_1__5_n_0\,
      Q => \^txsync_fsm.txdlyen_reg_0\,
      R => RST_CPLLRESET
    );
\txsync_fsm.txsync_done_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAA8"
    )
        port map (
      I0 => txsync_done,
      I1 => \txsync_fsm.txdlyen_i_2__5_n_0\,
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^rst_txsync_done\(0),
      O => \txsync_fsm.txsync_done_i_1__4_n_0\
    );
\txsync_fsm.txsync_done_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => txsync_done
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1__4_n_0\,
      Q => \^rst_txsync_done\(0),
      R => RST_CPLLRESET
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => RST_CPLLRESET
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => RST_CPLLRESET
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => RST_CPLLRESET
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txsyncdone_reg1,
      R => RST_CPLLRESET
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => RST_CPLLRESET
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_70 is
  port (
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \txsync_fsm.txdlyen_reg_0\ : out STD_LOGIC;
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 6 downto 0 );
    SYNC_RXDLYEN : out STD_LOGIC;
    \cplllock_reg1_reg[7]\ : out STD_LOGIC;
    \cplllock_reg1_reg[7]_0\ : out STD_LOGIC;
    \cplllock_reg1_reg[7]_1\ : out STD_LOGIC;
    \cplllock_reg1_reg[7]_2\ : out STD_LOGIC;
    \cplllock_reg1_reg[7]_3\ : out STD_LOGIC;
    RST_TXSYNC_DONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_0_in7_in : in STD_LOGIC;
    p_1_in8_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    txelecidle_reg2_reg : in STD_LOGIC;
    txsyncallin : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]_0\ : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC;
    SYNC_RATE_IDLE : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_RXSYNC_START : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_2\ : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_70 : entity is "PCIeGen1x8If64_pipe_sync";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_70;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_70 is
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rst_txsync_done\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal fsm_tx : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_60_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^pipe_sync_fsm_rx\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  signal rxelecidle_reg1 : STD_LOGIC;
  signal rxelecidle_reg2 : STD_LOGIC;
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  signal rxsync_donem_reg1 : STD_LOGIC;
  signal rxsync_donem_reg2 : STD_LOGIC;
  signal rxsync_start_reg1 : STD_LOGIC;
  signal rxsync_start_reg2 : STD_LOGIC;
  signal rxsyncdone_reg1 : STD_LOGIC;
  signal rxsyncdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg1 : STD_LOGIC;
  signal txdlysresetdone_reg2 : STD_LOGIC;
  signal txdlysresetdone_reg3 : STD_LOGIC;
  signal txphaligndone_reg1 : STD_LOGIC;
  signal txphaligndone_reg2 : STD_LOGIC;
  signal txphaligndone_reg3 : STD_LOGIC;
  signal txphinitdone_reg1 : STD_LOGIC;
  signal txphinitdone_reg2 : STD_LOGIC;
  signal txphinitdone_reg3 : STD_LOGIC;
  signal txsync_done : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[4]_i_3__6_n_0\ : STD_LOGIC;
  signal \txsync_fsm.fsm_tx[5]_i_2__6_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_1__6_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txdlyen_i_2__6_n_0\ : STD_LOGIC;
  signal \^txsync_fsm.txdlyen_reg_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_1__5_n_0\ : STD_LOGIC;
  signal txsync_start_reg1 : STD_LOGIC;
  signal txsync_start_reg2 : STD_LOGIC;
  signal txsync_start_reg3 : STD_LOGIC;
  signal txsyncdone_reg1 : STD_LOGIC;
  signal txsyncdone_reg2 : STD_LOGIC;
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
begin
  Q(5 downto 0) <= \^q\(5 downto 0);
  RST_TXSYNC_DONE(0) <= \^rst_txsync_done\(0);
  pipe_sync_fsm_rx(6 downto 0) <= \^pipe_sync_fsm_rx\(6 downto 0);
  \txsync_fsm.txdlyen_reg_0\ <= \^txsync_fsm.txdlyen_reg_0\;
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_10__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => rxsync_donem_reg2,
      I1 => \^pipe_sync_fsm_rx\(5),
      I2 => \^pipe_sync_fsm_rx\(3),
      I3 => \^pipe_sync_fsm_rx\(2),
      I4 => \gtx_channel.gtxe2_channel_i_i_60_n_0\,
      O => \cplllock_reg1_reg[7]_2\
    );
\gtx_channel.gtxe2_channel_i_i_12__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(3),
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => \cplllock_reg1_reg[7]\
    );
\gtx_channel.gtxe2_channel_i_i_13__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(0),
      I3 => \^q\(3),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[7]_1\
    );
\gtx_channel.gtxe2_channel_i_i_14__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(5),
      I2 => \^q\(3),
      I3 => \^q\(0),
      I4 => \^q\(1),
      I5 => \^q\(2),
      O => \cplllock_reg1_reg[7]_0\
    );
\gtx_channel.gtxe2_channel_i_i_60\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(0),
      I1 => \^pipe_sync_fsm_rx\(1),
      I2 => \^pipe_sync_fsm_rx\(6),
      I3 => \^pipe_sync_fsm_rx\(4),
      O => \gtx_channel.gtxe2_channel_i_i_60_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_9__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^pipe_sync_fsm_rx\(2),
      I1 => \^pipe_sync_fsm_rx\(3),
      I2 => \^pipe_sync_fsm_rx\(5),
      I3 => \gtx_channel.gtxe2_channel_i_i_60_n_0\,
      O => \cplllock_reg1_reg[7]_3\
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\,
      Q => mmcm_lock_reg1,
      R => RST_CPLLRESET
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => RST_CPLLRESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RATE_IDLE,
      Q => rate_idle_reg1,
      R => RST_CPLLRESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_CPLLRESET
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gt_rx_elec_idle_wire_filter(0),
      Q => rxelecidle_reg1,
      R => RST_CPLLRESET
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_2\,
      Q => rxphaligndone_m_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_3\,
      Q => rxphaligndone_s_reg1,
      R => RST_CPLLRESET
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => RST_CPLLRESET
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxsync_fsm_disable.fsm_rx_reg[2]_0\,
      Q => rxsync_donem_reg1,
      R => RST_CPLLRESET
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => RST_CPLLRESET
    );
\rxsync_fsm_disable.fsm_rx_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '1',
      Q => \^pipe_sync_fsm_rx\(0),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(1),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(2),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(3),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(4),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(5),
      R => '0'
    );
\rxsync_fsm_disable.fsm_rx_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \^pipe_sync_fsm_rx\(6),
      R => '0'
    );
\rxsync_fsm_disable.rxdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => SYNC_RXDLYEN,
      R => '0'
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_RXSYNC_START,
      Q => rxsync_start_reg1,
      R => RST_CPLLRESET
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => RST_CPLLRESET
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxsyncdone_reg1,
      R => RST_CPLLRESET
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => txdlysresetdone_reg1,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => RST_CPLLRESET
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncallin,
      Q => txphaligndone_reg1,
      R => RST_CPLLRESET
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => RST_CPLLRESET
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg2_reg,
      Q => txphinitdone_reg1,
      R => RST_CPLLRESET
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => RST_CPLLRESET
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx[0]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F2FF"
    )
        port map (
      I0 => \^q\(0),
      I1 => txsync_start_reg2,
      I2 => \^q\(5),
      I3 => \txsync_fsm.fsm_tx[5]_i_2__6_n_0\,
      O => fsm_tx(0)
    );
\txsync_fsm.fsm_tx[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__6_n_0\,
      I1 => \^q\(0),
      I2 => txsync_start_reg2,
      I3 => \^q\(1),
      I4 => mmcm_lock_reg2,
      O => fsm_tx(1)
    );
\txsync_fsm.fsm_tx[2]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA80AA80808080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__6_n_0\,
      I1 => \^q\(1),
      I2 => mmcm_lock_reg2,
      I3 => txdlysresetdone_reg2,
      I4 => txdlysresetdone_reg3,
      I5 => \^q\(2),
      O => fsm_tx(2)
    );
\txsync_fsm.fsm_tx[3]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00800080AAAA0080"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__6_n_0\,
      I1 => \^q\(2),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(3),
      I5 => \txsync_fsm.fsm_tx[4]_i_2__6_n_0\,
      O => fsm_tx(3)
    );
\txsync_fsm.fsm_tx[4]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080AA80"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__6_n_0\,
      I1 => \txsync_fsm.fsm_tx[4]_i_2__6_n_0\,
      I2 => \^q\(3),
      I3 => \^q\(4),
      I4 => \txsync_fsm.fsm_tx[4]_i_3__6_n_0\,
      O => fsm_tx(4)
    );
\txsync_fsm.fsm_tx[4]_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F222"
    )
        port map (
      I0 => txphinitdone_reg2,
      I1 => txphinitdone_reg3,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_2__6_n_0\
    );
\txsync_fsm.fsm_tx[4]_i_3__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => txphaligndone_reg3,
      I1 => txphaligndone_reg2,
      I2 => p_0_in7_in,
      I3 => p_1_in8_in,
      O => \txsync_fsm.fsm_tx[4]_i_3__6_n_0\
    );
\txsync_fsm.fsm_tx[5]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA20202000000000"
    )
        port map (
      I0 => \txsync_fsm.fsm_tx[5]_i_2__6_n_0\,
      I1 => txphaligndone_reg3,
      I2 => txphaligndone_reg2,
      I3 => p_0_in7_in,
      I4 => p_1_in8_in,
      I5 => \^q\(4),
      O => fsm_tx(5)
    );
\txsync_fsm.fsm_tx[5]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010116"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(1),
      I2 => \^q\(2),
      I3 => \^q\(3),
      I4 => \^q\(4),
      I5 => \^q\(5),
      O => \txsync_fsm.fsm_tx[5]_i_2__6_n_0\
    );
\txsync_fsm.fsm_tx_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(0),
      Q => \^q\(0),
      S => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(1),
      Q => \^q\(1),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(2),
      Q => \^q\(2),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(3),
      Q => \^q\(3),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(4),
      Q => \^q\(4),
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fsm_tx(5),
      Q => \^q\(5),
      R => RST_CPLLRESET
    );
\txsync_fsm.txdlyen_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \txsync_fsm.txdlyen_i_2__6_n_0\,
      I1 => \^q\(4),
      I2 => \^q\(3),
      I3 => \^q\(5),
      I4 => \^txsync_fsm.txdlyen_reg_0\,
      O => \txsync_fsm.txdlyen_i_1__6_n_0\
    );
\txsync_fsm.txdlyen_i_2__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => \^q\(1),
      I3 => txsync_start_reg2,
      O => \txsync_fsm.txdlyen_i_2__6_n_0\
    );
\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txdlyen_i_1__6_n_0\,
      Q => \^txsync_fsm.txdlyen_reg_0\,
      R => RST_CPLLRESET
    );
\txsync_fsm.txsync_done_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAA8"
    )
        port map (
      I0 => txsync_done,
      I1 => \txsync_fsm.txdlyen_i_2__6_n_0\,
      I2 => \^q\(4),
      I3 => \^q\(3),
      I4 => \^q\(5),
      I5 => \^rst_txsync_done\(0),
      O => \txsync_fsm.txsync_done_i_1__5_n_0\
    );
\txsync_fsm.txsync_done_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(5),
      I5 => \^q\(4),
      O => txsync_done
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1__5_n_0\,
      Q => \^rst_txsync_done\(0),
      R => RST_CPLLRESET
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => RST_CPLLRESET
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => RST_CPLLRESET
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => RST_CPLLRESET
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txsyncdone_reg1,
      R => RST_CPLLRESET
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => RST_CPLLRESET
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_user is
  port (
    txphinitdone_reg1_reg : out STD_LOGIC;
    p_1_in8_in : out STD_LOGIC;
    p_0_in7_in : out STD_LOGIC;
    gt_rxvalid_q_reg : out STD_LOGIC;
    p_2_in : out STD_LOGIC;
    USER_OOBCLK : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_rx_converge : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[0]\ : out STD_LOGIC;
    resetovrd_done_reg1_reg : out STD_LOGIC;
    RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_active_lane : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : in STD_LOGIC_VECTOR ( 0 to 0 );
    p_1_in8_in_0 : in STD_LOGIC;
    p_0_in7_in_1 : in STD_LOGIC;
    txelecidle_reg2_reg_0 : in STD_LOGIC;
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    CLK_PCLK_SEL : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXRESETDONE : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC;
    RST_RXUSRCLK_RESET : in STD_LOGIC;
    pipe_rxstatus : in STD_LOGIC_VECTOR ( 0 to 0 );
    out1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RATE_RXSYNC : in STD_LOGIC;
    USER_RATE_DONE : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    USER_RESETOVRD_START : in STD_LOGIC;
    RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user : entity is "PCIeGen1x8If64_pipe_user";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_user;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user is
  signal \converge_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_4_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_5_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_6_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_7_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_8_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_9_n_0\ : STD_LOGIC;
  signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_2_n_0\ : STD_LOGIC;
  signal converge_gen3_i_1_n_0 : STD_LOGIC;
  signal converge_gen3_reg_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal gt_rxvalid_q_i_6_n_0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_74_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_75_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_83_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1_n_0\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  signal pclk_sel_reg2 : STD_LOGIC;
  signal rate_done_reg1 : STD_LOGIC;
  signal rate_done_reg2 : STD_LOGIC;
  signal rate_gen3_reg1 : STD_LOGIC;
  signal rate_gen3_reg2 : STD_LOGIC;
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rate_rxsync_reg1 : STD_LOGIC;
  signal rate_rxsync_reg2 : STD_LOGIC;
  signal resetovrd_start_reg1 : STD_LOGIC;
  signal resetovrd_start_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal \rxcdrlock_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxstatus_reg1 : STD_LOGIC;
  signal rxstatus_reg2 : STD_LOGIC;
  signal \rxvalid_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  signal rxvalid_reg2 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal txcompliance_reg1 : STD_LOGIC;
  signal txcompliance_reg2 : STD_LOGIC;
  signal txelecidle_reg1 : STD_LOGIC;
  signal txelecidle_reg2 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal \NLW_converge_cnt_reg[21]_i_2_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_converge_cnt_reg[21]_i_2_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[13]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[13]_i_2_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[17]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[17]_i_2_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[1]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[1]_i_2_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[21]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[21]_i_2_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[5]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[5]_i_2_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[9]_i_2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[9]_i_2_CARRY4\ : label is "LO:O";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_5\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1\ : label is "soft_lutpair43";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute ASYNC_REG of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of resetovrd_done_reg1_i_1 : label is "soft_lutpair44";
  attribute ASYNC_REG of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
begin
  p_0_in7_in <= txcompliance_reg2;
  p_1_in8_in <= txelecidle_reg2;
  p_2_in <= rst_idle_reg2;
\converge_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => RST_CPLLRESET,
      I3 => rate_gen3_reg2,
      O => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5D555D"
    )
        port map (
      I0 => converge_cnt_reg(21),
      I1 => \converge_cnt[0]_i_4_n_0\,
      I2 => converge_cnt_reg(20),
      I3 => \converge_cnt[0]_i_5_n_0\,
      I4 => \converge_cnt[0]_i_6_n_0\,
      O => sel
    );
\converge_cnt[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => converge_cnt_reg(13),
      I3 => converge_cnt_reg(16),
      I4 => converge_cnt_reg(15),
      I5 => \converge_cnt[0]_i_8_n_0\,
      O => \converge_cnt[0]_i_4_n_0\
    );
\converge_cnt[0]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \converge_cnt[0]_i_8_n_0\,
      I1 => converge_cnt_reg(16),
      I2 => converge_cnt_reg(15),
      I3 => converge_cnt_reg(13),
      I4 => converge_cnt_reg(11),
      O => \converge_cnt[0]_i_5_n_0\
    );
\converge_cnt[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(3),
      I1 => converge_cnt_reg(6),
      I2 => \converge_cnt[0]_i_9_n_0\,
      I3 => converge_cnt_reg(10),
      I4 => converge_cnt_reg(8),
      I5 => converge_cnt_reg(9),
      O => \converge_cnt[0]_i_6_n_0\
    );
\converge_cnt[0]_i_7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => converge_cnt_reg(0),
      O => \converge_cnt[0]_i_7_n_0\
    );
\converge_cnt[0]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => converge_cnt_reg(17),
      I1 => converge_cnt_reg(18),
      I2 => converge_cnt_reg(19),
      O => \converge_cnt[0]_i_8_n_0\
    );
\converge_cnt[0]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => converge_cnt_reg(4),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(7),
      O => \converge_cnt[0]_i_9_n_0\
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3_n_0\,
      Q => converge_cnt_reg(0),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[10]_i_1_n_0\,
      Q => converge_cnt_reg(10),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[11]_i_1_n_0\,
      Q => converge_cnt_reg(11),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1_n_0\,
      Q => converge_cnt_reg(12),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[13]_i_1_n_0\,
      Q => converge_cnt_reg(13),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[13]_i_2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2_n_0\,
      CO(1) => \converge_cnt_reg[14]_i_2_n_0\,
      CO(0) => \converge_cnt_reg[13]_i_2_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[15]_i_1_n_0\,
      O(2) => \converge_cnt_reg[14]_i_1_n_0\,
      O(1) => \converge_cnt_reg[13]_i_1_n_0\,
      O(0) => \converge_cnt_reg[12]_i_1_n_0\,
      S(3 downto 0) => converge_cnt_reg(15 downto 12)
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[14]_i_1_n_0\,
      Q => converge_cnt_reg(14),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[15]_i_1_n_0\,
      Q => converge_cnt_reg(15),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1_n_0\,
      Q => converge_cnt_reg(16),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[17]_i_1_n_0\,
      Q => converge_cnt_reg(17),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[17]_i_2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[20]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2_n_0\,
      CO(1) => \converge_cnt_reg[18]_i_2_n_0\,
      CO(0) => \converge_cnt_reg[17]_i_2_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[19]_i_1_n_0\,
      O(2) => \converge_cnt_reg[18]_i_1_n_0\,
      O(1) => \converge_cnt_reg[17]_i_1_n_0\,
      O(0) => \converge_cnt_reg[16]_i_1_n_0\,
      S(3 downto 0) => converge_cnt_reg(19 downto 16)
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[18]_i_1_n_0\,
      Q => converge_cnt_reg(18),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[19]_i_1_n_0\,
      Q => converge_cnt_reg(19),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[1]_i_1_n_0\,
      Q => converge_cnt_reg(1),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[1]_i_2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[4]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2_n_0\,
      CO(1) => \converge_cnt_reg[2]_i_2_n_0\,
      CO(0) => \converge_cnt_reg[1]_i_2_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '1',
      O(3) => \converge_cnt_reg[3]_i_1_n_0\,
      O(2) => \converge_cnt_reg[2]_i_1_n_0\,
      O(1) => \converge_cnt_reg[1]_i_1_n_0\,
      O(0) => \converge_cnt_reg[0]_i_3_n_0\,
      S(3 downto 1) => converge_cnt_reg(3 downto 1),
      S(0) => \converge_cnt[0]_i_7_n_0\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1_n_0\,
      Q => converge_cnt_reg(20),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[21]_i_1_n_0\,
      Q => converge_cnt_reg(21),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[21]_i_2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[20]_i_2_n_0\,
      CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2_CARRY4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2_CARRY4_DI_UNCONNECTED\(3 downto 1),
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2_CARRY4_O_UNCONNECTED\(3 downto 2),
      O(1) => \converge_cnt_reg[21]_i_1_n_0\,
      O(0) => \converge_cnt_reg[20]_i_1_n_0\,
      S(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2_CARRY4_S_UNCONNECTED\(3 downto 2),
      S(1 downto 0) => converge_cnt_reg(21 downto 20)
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[2]_i_1_n_0\,
      Q => converge_cnt_reg(2),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[3]_i_1_n_0\,
      Q => converge_cnt_reg(3),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1_n_0\,
      Q => converge_cnt_reg(4),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[5]_i_1_n_0\,
      Q => converge_cnt_reg(5),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[5]_i_2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2_n_0\,
      CO(1) => \converge_cnt_reg[6]_i_2_n_0\,
      CO(0) => \converge_cnt_reg[5]_i_2_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[7]_i_1_n_0\,
      O(2) => \converge_cnt_reg[6]_i_1_n_0\,
      O(1) => \converge_cnt_reg[5]_i_1_n_0\,
      O(0) => \converge_cnt_reg[4]_i_1_n_0\,
      S(3 downto 0) => converge_cnt_reg(7 downto 4)
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[6]_i_1_n_0\,
      Q => converge_cnt_reg(6),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[7]_i_1_n_0\,
      Q => converge_cnt_reg(7),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1_n_0\,
      Q => converge_cnt_reg(8),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[9]_i_1_n_0\,
      Q => converge_cnt_reg(9),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[9]_i_2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2_n_0\,
      CO(1) => \converge_cnt_reg[10]_i_2_n_0\,
      CO(0) => \converge_cnt_reg[9]_i_2_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[11]_i_1_n_0\,
      O(2) => \converge_cnt_reg[10]_i_1_n_0\,
      O(1) => \converge_cnt_reg[9]_i_1_n_0\,
      O(0) => \converge_cnt_reg[8]_i_1_n_0\,
      S(3 downto 0) => converge_cnt_reg(11 downto 8)
    );
converge_gen3_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0C08"
    )
        port map (
      I0 => rxeq_adapt_done_reg2,
      I1 => rate_gen3_reg2,
      I2 => RST_CPLLRESET,
      I3 => converge_gen3_reg_n_0,
      O => converge_gen3_i_1_n_0
    );
converge_gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_gen3_i_1_n_0,
      Q => converge_gen3_reg_n_0,
      R => '0'
    );
gt_rx_phy_status_q_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => RST_PHYSTATUS(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => gt_rx_phy_status_wire_filter(0)
    );
gt_rxvalid_q_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4500000000000000"
    )
        port map (
      I0 => gt_rxvalid_q_i_6_n_0,
      I1 => gt_rxvalid_q_reg_0,
      I2 => gt_rx_elec_idle_wire_filter(0),
      I3 => rst_idle_reg2,
      I4 => rate_idle_reg2,
      I5 => \resetovrd_disble.reset_reg[4]_0\,
      O => gt_rxvalid_q_reg
    );
gt_rxvalid_q_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(1),
      O => gt_rxvalid_q_i_6_n_0
    );
\gtx_channel.gtxe2_channel_i_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => \cplllock_reg1_reg[0]\
    );
\gtx_channel.gtxe2_channel_i_i_64\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAEAAAAAAAA"
    )
        port map (
      I0 => converge_gen3_reg_n_0,
      I1 => \gtx_channel.gtxe2_channel_i_i_74_n_0\,
      I2 => \gtx_channel.gtxe2_channel_i_i_75_n_0\,
      I3 => converge_cnt_reg(14),
      I4 => converge_cnt_reg(12),
      I5 => \converge_cnt[0]_i_5_n_0\,
      O => user_rx_converge(0)
    );
\gtx_channel.gtxe2_channel_i_i_74\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001000000"
    )
        port map (
      I0 => converge_cnt_reg(7),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(4),
      I3 => \gtx_channel.gtxe2_channel_i_i_83_n_0\,
      I4 => converge_cnt_reg(21),
      I5 => converge_cnt_reg(0),
      O => \gtx_channel.gtxe2_channel_i_i_74_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_75\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => converge_cnt_reg(8),
      I1 => converge_cnt_reg(9),
      O => \gtx_channel.gtxe2_channel_i_i_75_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_83\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => converge_cnt_reg(6),
      I1 => converge_cnt_reg(1),
      I2 => converge_cnt_reg(3),
      I3 => converge_cnt_reg(20),
      I4 => converge_cnt_reg(10),
      I5 => converge_cnt_reg(2),
      O => \gtx_channel.gtxe2_channel_i_i_83_n_0\
    );
\oobclk_div.oobclk_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \oobclk_div.oobclk_i_1_n_0\,
      Q => USER_OOBCLK,
      R => RST_CPLLRESET
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => CLK_PCLK_SEL(0),
      Q => pclk_sel_reg1,
      R => RST_CPLLRESET
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => RST_CPLLRESET
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_DONE,
      Q => rate_done_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => rate_gen3_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_RXSYNC,
      Q => rate_rxsync_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => RST_RXUSRCLK_RESET
    );
\resetdone_reg1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txresetdone_reg2,
      I1 => rxresetdone_reg2,
      O => RST_RESETDONE(0)
    );
\resetovrd_disble.fsm_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(0),
      R => '0'
    );
\resetovrd_disble.fsm_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(0),
      R => '0'
    );
\resetovrd_disble.reset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(2),
      R => '0'
    );
\resetovrd_disble.reset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(3),
      R => '0'
    );
\resetovrd_disble.reset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(4),
      R => '0'
    );
\resetovrd_disble.reset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(5),
      R => '0'
    );
\resetovrd_disble.reset_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(6),
      R => '0'
    );
resetovrd_done_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => resetovrd_done_reg1_reg
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RESETOVRD_START,
      Q => resetovrd_start_reg1,
      R => RST_CPLLRESET
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => RST_CPLLRESET
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => out1(0),
      Q => rst_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxcdrlock_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(2),
      I2 => \rxcdrlock_cnt_reg__0\(0),
      I3 => \rxcdrlock_cnt_reg__0\(1),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(0)
    );
\rxcdrlock_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(0),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(2),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(1)
    );
\rxcdrlock_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8CCCC000"
    )
        port map (
      I0 => \rxcdrlock_cnt_reg__0\(3),
      I1 => rxcdrlock_reg2,
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(2)
    );
\rxcdrlock_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \rxcdrlock_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \rxcdrlock_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \rxcdrlock_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \rxcdrlock_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\rxcdrlock_reg1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \resetovrd_disble.reset_reg[4]_1\,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => RST_RXCDRLOCK(0)
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXEQ_ADAPT_DONE,
      Q => rxeq_adapt_done_reg1,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pipe_rxstatus(0),
      Q => rxstatus_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(1),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => \rxvalid_cnt_reg__0\(0),
      O => \p_0_in__0__0\(0)
    );
\rxvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000E6660000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(0),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(1)
    );
\rxvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000EA6A0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(2),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(2)
    );
\rxvalid_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D444444400000000"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => \rxvalid_cnt_reg__0\(3),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(0),
      I4 => \rxvalid_cnt_reg__0\(1),
      I5 => rxvalid_reg2,
      O => \p_0_in__0__0\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(0),
      Q => \rxvalid_cnt_reg__0\(0),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(1),
      Q => \rxvalid_cnt_reg__0\(1),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(2),
      Q => \rxvalid_cnt_reg__0\(2),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(3),
      Q => \rxvalid_cnt_reg__0\(3),
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxvalid_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => RST_RXUSRCLK_RESET
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXCOMPLIANCE(0),
      Q => txcompliance_reg1,
      R => RST_CPLLRESET
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => RST_CPLLRESET
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXELECIDLE(0),
      Q => txelecidle_reg1,
      R => RST_CPLLRESET
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => RST_CPLLRESET
    );
txphinitdone_reg1_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000088808080"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      I2 => pipe_txphinitdone(0),
      I3 => p_1_in8_in_0,
      I4 => p_0_in7_in_1,
      I5 => txelecidle_reg2_reg_0,
      O => txphinitdone_reg1_reg
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
\txsync_fsm.fsm_tx[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      O => user_active_lane(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_34 is
  port (
    txphaligndone_reg1_reg : out STD_LOGIC;
    p_1_in8_in : out STD_LOGIC;
    p_0_in7_in : out STD_LOGIC;
    txphaligndone_reg1_reg_0 : out STD_LOGIC;
    txphinitdone_reg1_reg : out STD_LOGIC;
    gt_rxvalid_q_reg : out STD_LOGIC;
    p_2_in : out STD_LOGIC;
    USER_OOBCLK : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_rx_converge : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[1]\ : out STD_LOGIC;
    resetovrd_done_reg1_reg : out STD_LOGIC;
    RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_active_lane : in STD_LOGIC_VECTOR ( 0 to 0 );
    txelecidle_reg2_reg_0 : in STD_LOGIC;
    pipe_txphaligndone : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphinitdone : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_1_in8_in_0 : in STD_LOGIC;
    p_0_in7_in_1 : in STD_LOGIC;
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    CLK_PCLK_SEL : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXRESETDONE : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC;
    RST_RXUSRCLK_RESET : in STD_LOGIC;
    pipe_rxstatus : in STD_LOGIC_VECTOR ( 0 to 0 );
    out1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RATE_RXSYNC : in STD_LOGIC;
    USER_RATE_DONE : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    USER_RESETOVRD_START : in STD_LOGIC;
    RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_34 : entity is "PCIeGen1x8If64_pipe_user";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_34;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_34 is
  signal \converge_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_7__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_8__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_9__0_n_0\ : STD_LOGIC;
  signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_gen3_i_1__0_n_0\ : STD_LOGIC;
  signal converge_gen3_reg_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gt_rxvalid_q_i_6__0_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_73_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_82_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1__0_n_0\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  signal pclk_sel_reg2 : STD_LOGIC;
  signal rate_done_reg1 : STD_LOGIC;
  signal rate_done_reg2 : STD_LOGIC;
  signal rate_gen3_reg1 : STD_LOGIC;
  signal rate_gen3_reg2 : STD_LOGIC;
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rate_rxsync_reg1 : STD_LOGIC;
  signal rate_rxsync_reg2 : STD_LOGIC;
  signal resetovrd_start_reg1 : STD_LOGIC;
  signal resetovrd_start_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal \rxcdrlock_cnt_reg__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxstatus_reg1 : STD_LOGIC;
  signal rxstatus_reg2 : STD_LOGIC;
  signal \rxvalid_cnt_reg__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  signal rxvalid_reg2 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal txcompliance_reg1 : STD_LOGIC;
  signal txcompliance_reg2 : STD_LOGIC;
  signal txelecidle_reg1 : STD_LOGIC;
  signal txelecidle_reg2 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal \NLW_converge_cnt_reg[21]_i_2__0_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__0_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__0_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_converge_cnt_reg[21]_i_2__0_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[13]_i_2__0_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[13]_i_2__0_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[17]_i_2__0_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[17]_i_2__0_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[1]_i_2__0_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[1]_i_2__0_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[21]_i_2__0_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[21]_i_2__0_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[5]_i_2__0_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[5]_i_2__0_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[9]_i_2__0_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[9]_i_2__0_CARRY4\ : label is "LO:O";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_5__0\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1__0\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1__0\ : label is "soft_lutpair65";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute ASYNC_REG of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_done_reg1_i_1__0\ : label is "soft_lutpair66";
  attribute ASYNC_REG of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
begin
  p_0_in7_in <= txcompliance_reg2;
  p_1_in8_in <= txelecidle_reg2;
  p_2_in <= rst_idle_reg2;
\converge_cnt[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => RST_CPLLRESET,
      I3 => rate_gen3_reg2,
      O => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5D555D"
    )
        port map (
      I0 => converge_cnt_reg(21),
      I1 => \converge_cnt[0]_i_4__0_n_0\,
      I2 => converge_cnt_reg(20),
      I3 => \converge_cnt[0]_i_5__0_n_0\,
      I4 => \converge_cnt[0]_i_6__0_n_0\,
      O => sel
    );
\converge_cnt[0]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => converge_cnt_reg(13),
      I3 => converge_cnt_reg(16),
      I4 => converge_cnt_reg(15),
      I5 => \converge_cnt[0]_i_8__0_n_0\,
      O => \converge_cnt[0]_i_4__0_n_0\
    );
\converge_cnt[0]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \converge_cnt[0]_i_8__0_n_0\,
      I1 => converge_cnt_reg(16),
      I2 => converge_cnt_reg(15),
      I3 => converge_cnt_reg(13),
      I4 => converge_cnt_reg(11),
      O => \converge_cnt[0]_i_5__0_n_0\
    );
\converge_cnt[0]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(3),
      I1 => converge_cnt_reg(6),
      I2 => \converge_cnt[0]_i_9__0_n_0\,
      I3 => converge_cnt_reg(10),
      I4 => converge_cnt_reg(8),
      I5 => converge_cnt_reg(9),
      O => \converge_cnt[0]_i_6__0_n_0\
    );
\converge_cnt[0]_i_7__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => converge_cnt_reg(0),
      O => \converge_cnt[0]_i_7__0_n_0\
    );
\converge_cnt[0]_i_8__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => converge_cnt_reg(17),
      I1 => converge_cnt_reg(18),
      I2 => converge_cnt_reg(19),
      O => \converge_cnt[0]_i_8__0_n_0\
    );
\converge_cnt[0]_i_9__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => converge_cnt_reg(4),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(7),
      O => \converge_cnt[0]_i_9__0_n_0\
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__0_n_0\,
      Q => converge_cnt_reg(0),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[10]_i_1__0_n_0\,
      Q => converge_cnt_reg(10),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[11]_i_1__0_n_0\,
      Q => converge_cnt_reg(11),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__0_n_0\,
      Q => converge_cnt_reg(12),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[13]_i_1__0_n_0\,
      Q => converge_cnt_reg(13),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[13]_i_2__0_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__0_n_0\,
      CO(1) => \converge_cnt_reg[14]_i_2__0_n_0\,
      CO(0) => \converge_cnt_reg[13]_i_2__0_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[15]_i_1__0_n_0\,
      O(2) => \converge_cnt_reg[14]_i_1__0_n_0\,
      O(1) => \converge_cnt_reg[13]_i_1__0_n_0\,
      O(0) => \converge_cnt_reg[12]_i_1__0_n_0\,
      S(3 downto 0) => converge_cnt_reg(15 downto 12)
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[14]_i_1__0_n_0\,
      Q => converge_cnt_reg(14),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[15]_i_1__0_n_0\,
      Q => converge_cnt_reg(15),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__0_n_0\,
      Q => converge_cnt_reg(16),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[17]_i_1__0_n_0\,
      Q => converge_cnt_reg(17),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[17]_i_2__0_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[20]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__0_n_0\,
      CO(1) => \converge_cnt_reg[18]_i_2__0_n_0\,
      CO(0) => \converge_cnt_reg[17]_i_2__0_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[19]_i_1__0_n_0\,
      O(2) => \converge_cnt_reg[18]_i_1__0_n_0\,
      O(1) => \converge_cnt_reg[17]_i_1__0_n_0\,
      O(0) => \converge_cnt_reg[16]_i_1__0_n_0\,
      S(3 downto 0) => converge_cnt_reg(19 downto 16)
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[18]_i_1__0_n_0\,
      Q => converge_cnt_reg(18),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[19]_i_1__0_n_0\,
      Q => converge_cnt_reg(19),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[1]_i_1__0_n_0\,
      Q => converge_cnt_reg(1),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[1]_i_2__0_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[4]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__0_n_0\,
      CO(1) => \converge_cnt_reg[2]_i_2__0_n_0\,
      CO(0) => \converge_cnt_reg[1]_i_2__0_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '1',
      O(3) => \converge_cnt_reg[3]_i_1__0_n_0\,
      O(2) => \converge_cnt_reg[2]_i_1__0_n_0\,
      O(1) => \converge_cnt_reg[1]_i_1__0_n_0\,
      O(0) => \converge_cnt_reg[0]_i_3__0_n_0\,
      S(3 downto 1) => converge_cnt_reg(3 downto 1),
      S(0) => \converge_cnt[0]_i_7__0_n_0\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1__0_n_0\,
      Q => converge_cnt_reg(20),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[21]_i_1__0_n_0\,
      Q => converge_cnt_reg(21),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[21]_i_2__0_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[20]_i_2__0_n_0\,
      CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__0_CARRY4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__0_CARRY4_DI_UNCONNECTED\(3 downto 1),
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__0_CARRY4_O_UNCONNECTED\(3 downto 2),
      O(1) => \converge_cnt_reg[21]_i_1__0_n_0\,
      O(0) => \converge_cnt_reg[20]_i_1__0_n_0\,
      S(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__0_CARRY4_S_UNCONNECTED\(3 downto 2),
      S(1 downto 0) => converge_cnt_reg(21 downto 20)
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[2]_i_1__0_n_0\,
      Q => converge_cnt_reg(2),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[3]_i_1__0_n_0\,
      Q => converge_cnt_reg(3),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__0_n_0\,
      Q => converge_cnt_reg(4),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[5]_i_1__0_n_0\,
      Q => converge_cnt_reg(5),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[5]_i_2__0_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__0_n_0\,
      CO(1) => \converge_cnt_reg[6]_i_2__0_n_0\,
      CO(0) => \converge_cnt_reg[5]_i_2__0_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[7]_i_1__0_n_0\,
      O(2) => \converge_cnt_reg[6]_i_1__0_n_0\,
      O(1) => \converge_cnt_reg[5]_i_1__0_n_0\,
      O(0) => \converge_cnt_reg[4]_i_1__0_n_0\,
      S(3 downto 0) => converge_cnt_reg(7 downto 4)
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[6]_i_1__0_n_0\,
      Q => converge_cnt_reg(6),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[7]_i_1__0_n_0\,
      Q => converge_cnt_reg(7),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__0_n_0\,
      Q => converge_cnt_reg(8),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[9]_i_1__0_n_0\,
      Q => converge_cnt_reg(9),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[9]_i_2__0_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__0_n_0\,
      CO(1) => \converge_cnt_reg[10]_i_2__0_n_0\,
      CO(0) => \converge_cnt_reg[9]_i_2__0_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[11]_i_1__0_n_0\,
      O(2) => \converge_cnt_reg[10]_i_1__0_n_0\,
      O(1) => \converge_cnt_reg[9]_i_1__0_n_0\,
      O(0) => \converge_cnt_reg[8]_i_1__0_n_0\,
      S(3 downto 0) => converge_cnt_reg(11 downto 8)
    );
\converge_gen3_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0C08"
    )
        port map (
      I0 => rxeq_adapt_done_reg2,
      I1 => rate_gen3_reg2,
      I2 => RST_CPLLRESET,
      I3 => converge_gen3_reg_n_0,
      O => \converge_gen3_i_1__0_n_0\
    );
converge_gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \converge_gen3_i_1__0_n_0\,
      Q => converge_gen3_reg_n_0,
      R => '0'
    );
\gt_rx_phy_status_q_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => RST_PHYSTATUS(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => gt_rx_phy_status_wire_filter(0)
    );
\gt_rxvalid_q_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4500000000000000"
    )
        port map (
      I0 => \gt_rxvalid_q_i_6__0_n_0\,
      I1 => gt_rxvalid_q_reg_0,
      I2 => gt_rx_elec_idle_wire_filter(0),
      I3 => rst_idle_reg2,
      I4 => rate_idle_reg2,
      I5 => \resetovrd_disble.reset_reg[4]_0\,
      O => gt_rxvalid_q_reg
    );
\gt_rxvalid_q_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0__0\(3),
      I1 => \rxvalid_cnt_reg__0__0\(2),
      I2 => \rxvalid_cnt_reg__0__0\(0),
      I3 => \rxvalid_cnt_reg__0__0\(1),
      O => \gt_rxvalid_q_i_6__0_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => \cplllock_reg1_reg[1]\
    );
\gtx_channel.gtxe2_channel_i_i_63\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => converge_gen3_reg_n_0,
      I1 => \gtx_channel.gtxe2_channel_i_i_73_n_0\,
      I2 => converge_cnt_reg(8),
      I3 => converge_cnt_reg(9),
      I4 => \converge_cnt[0]_i_9__0_n_0\,
      I5 => \converge_cnt[0]_i_5__0_n_0\,
      O => user_rx_converge(0)
    );
\gtx_channel.gtxe2_channel_i_i_73\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => \gtx_channel.gtxe2_channel_i_i_82_n_0\,
      I3 => converge_cnt_reg(2),
      I4 => converge_cnt_reg(6),
      O => \gtx_channel.gtxe2_channel_i_i_73_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_82\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => converge_cnt_reg(20),
      I1 => converge_cnt_reg(3),
      I2 => converge_cnt_reg(0),
      I3 => converge_cnt_reg(1),
      I4 => converge_cnt_reg(10),
      I5 => converge_cnt_reg(21),
      O => \gtx_channel.gtxe2_channel_i_i_82_n_0\
    );
\oobclk_div.oobclk_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1__0_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \oobclk_div.oobclk_i_1__0_n_0\,
      Q => USER_OOBCLK,
      R => RST_CPLLRESET
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => CLK_PCLK_SEL(0),
      Q => pclk_sel_reg1,
      R => RST_CPLLRESET
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => RST_CPLLRESET
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_DONE,
      Q => rate_done_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => rate_gen3_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_RXSYNC,
      Q => rate_rxsync_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => RST_RXUSRCLK_RESET
    );
\resetdone_reg1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txresetdone_reg2,
      I1 => rxresetdone_reg2,
      O => RST_RESETDONE(0)
    );
\resetovrd_disble.fsm_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(0),
      R => '0'
    );
\resetovrd_disble.fsm_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(0),
      R => '0'
    );
\resetovrd_disble.reset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(2),
      R => '0'
    );
\resetovrd_disble.reset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(3),
      R => '0'
    );
\resetovrd_disble.reset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(4),
      R => '0'
    );
\resetovrd_disble.reset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(5),
      R => '0'
    );
\resetovrd_disble.reset_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(6),
      R => '0'
    );
\resetovrd_done_reg1_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => resetovrd_done_reg1_reg
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RESETOVRD_START,
      Q => resetovrd_start_reg1,
      R => RST_CPLLRESET
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => RST_CPLLRESET
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => out1(0),
      Q => rst_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxcdrlock_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0__0\(2),
      I2 => \rxcdrlock_cnt_reg__0__0\(0),
      I3 => \rxcdrlock_cnt_reg__0__0\(1),
      I4 => \rxcdrlock_cnt_reg__0__0\(3),
      O => \p_0_in__0\(0)
    );
\rxcdrlock_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0__0\(0),
      I2 => \rxcdrlock_cnt_reg__0__0\(1),
      I3 => \rxcdrlock_cnt_reg__0__0\(2),
      I4 => \rxcdrlock_cnt_reg__0__0\(3),
      O => \p_0_in__0\(1)
    );
\rxcdrlock_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8CCCC000"
    )
        port map (
      I0 => \rxcdrlock_cnt_reg__0__0\(3),
      I1 => rxcdrlock_reg2,
      I2 => \rxcdrlock_cnt_reg__0__0\(1),
      I3 => \rxcdrlock_cnt_reg__0__0\(0),
      I4 => \rxcdrlock_cnt_reg__0__0\(2),
      O => \p_0_in__0\(2)
    );
\rxcdrlock_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0__0\(3),
      I2 => \rxcdrlock_cnt_reg__0__0\(1),
      I3 => \rxcdrlock_cnt_reg__0__0\(0),
      I4 => \rxcdrlock_cnt_reg__0__0\(2),
      O => \p_0_in__0\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \rxcdrlock_cnt_reg__0__0\(0),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \rxcdrlock_cnt_reg__0__0\(1),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \rxcdrlock_cnt_reg__0__0\(2),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \rxcdrlock_cnt_reg__0__0\(3),
      R => RST_CPLLRESET
    );
\rxcdrlock_reg1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \resetovrd_disble.reset_reg[4]_1\,
      I1 => \rxcdrlock_cnt_reg__0__0\(3),
      I2 => \rxcdrlock_cnt_reg__0__0\(1),
      I3 => \rxcdrlock_cnt_reg__0__0\(0),
      I4 => \rxcdrlock_cnt_reg__0__0\(2),
      O => RST_RXCDRLOCK(0)
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXEQ_ADAPT_DONE,
      Q => rxeq_adapt_done_reg1,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pipe_rxstatus(0),
      Q => rxstatus_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0__0\(3),
      I1 => \rxvalid_cnt_reg__0__0\(2),
      I2 => \rxvalid_cnt_reg__0__0\(1),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => \rxvalid_cnt_reg__0__0\(0),
      O => \p_0_in__0__0\(0)
    );
\rxvalid_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000E6660000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0__0\(0),
      I1 => \rxvalid_cnt_reg__0__0\(1),
      I2 => \rxvalid_cnt_reg__0__0\(2),
      I3 => \rxvalid_cnt_reg__0__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(1)
    );
\rxvalid_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000EA6A0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0__0\(2),
      I1 => \rxvalid_cnt_reg__0__0\(1),
      I2 => \rxvalid_cnt_reg__0__0\(0),
      I3 => \rxvalid_cnt_reg__0__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(2)
    );
\rxvalid_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D444444400000000"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => \rxvalid_cnt_reg__0__0\(3),
      I2 => \rxvalid_cnt_reg__0__0\(2),
      I3 => \rxvalid_cnt_reg__0__0\(0),
      I4 => \rxvalid_cnt_reg__0__0\(1),
      I5 => rxvalid_reg2,
      O => \p_0_in__0__0\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(0),
      Q => \rxvalid_cnt_reg__0__0\(0),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(1),
      Q => \rxvalid_cnt_reg__0__0\(1),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(2),
      Q => \rxvalid_cnt_reg__0__0\(2),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(3),
      Q => \rxvalid_cnt_reg__0__0\(3),
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxvalid_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => RST_RXUSRCLK_RESET
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXCOMPLIANCE(0),
      Q => txcompliance_reg1,
      R => RST_CPLLRESET
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => RST_CPLLRESET
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXELECIDLE(0),
      Q => txelecidle_reg1,
      R => RST_CPLLRESET
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8A8AAA8AAA8AAA"
    )
        port map (
      I0 => user_active_lane(0),
      I1 => txelecidle_reg2_reg_0,
      I2 => pipe_txphaligndone(1),
      I3 => pipe_txphaligndone(0),
      I4 => txelecidle_reg2,
      I5 => txcompliance_reg2,
      O => txphaligndone_reg1_reg
    );
txphaligndone_reg1_i_9: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => txcompliance_reg2,
      I1 => txelecidle_reg2,
      I2 => pipe_txphaligndone(0),
      O => txphaligndone_reg1_reg_0
    );
txphinitdone_reg1_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8000000"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      I2 => pipe_txphinitdone(0),
      I3 => p_1_in8_in_0,
      I4 => p_0_in7_in_1,
      I5 => pipe_txphinitdone(1),
      O => txphinitdone_reg1_reg
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_40 is
  port (
    txphaligndone_reg1_reg : out STD_LOGIC;
    p_1_in8_in : out STD_LOGIC;
    p_0_in7_in : out STD_LOGIC;
    txphinitdone_reg1_reg : out STD_LOGIC;
    txphinitdone_reg1_reg_0 : out STD_LOGIC;
    gt_rxvalid_q_reg : out STD_LOGIC;
    p_2_in : out STD_LOGIC;
    USER_OOBCLK : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_rx_converge : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[2]\ : out STD_LOGIC;
    resetovrd_done_reg1_reg : out STD_LOGIC;
    RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_active_lane : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphaligndone : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_1_in8_in_0 : in STD_LOGIC;
    p_0_in7_in_1 : in STD_LOGIC;
    pipe_txphinitdone : in STD_LOGIC_VECTOR ( 2 downto 0 );
    txelecidle_reg2_reg_0 : in STD_LOGIC;
    p_1_in8_in_2 : in STD_LOGIC;
    p_0_in7_in_3 : in STD_LOGIC;
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    CLK_PCLK_SEL : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXRESETDONE : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC;
    RST_RXUSRCLK_RESET : in STD_LOGIC;
    pipe_rxstatus : in STD_LOGIC_VECTOR ( 0 to 0 );
    out1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RATE_RXSYNC : in STD_LOGIC;
    USER_RATE_DONE : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    USER_RESETOVRD_START : in STD_LOGIC;
    RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_40 : entity is "PCIeGen1x8If64_pipe_user";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_40;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_40 is
  signal \converge_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_4__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_5__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_6__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_7__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_8__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_9__1_n_0\ : STD_LOGIC;
  signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[0]_i_3__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_1__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_gen3_i_1__1_n_0\ : STD_LOGIC;
  signal converge_gen3_reg_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gt_rxvalid_q_i_6__1_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_77_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_85_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1__1_n_0\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  signal pclk_sel_reg2 : STD_LOGIC;
  signal rate_done_reg1 : STD_LOGIC;
  signal rate_done_reg2 : STD_LOGIC;
  signal rate_gen3_reg1 : STD_LOGIC;
  signal rate_gen3_reg2 : STD_LOGIC;
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rate_rxsync_reg1 : STD_LOGIC;
  signal rate_rxsync_reg2 : STD_LOGIC;
  signal resetovrd_start_reg1 : STD_LOGIC;
  signal resetovrd_start_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal \rxcdrlock_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxstatus_reg1 : STD_LOGIC;
  signal rxstatus_reg2 : STD_LOGIC;
  signal \rxvalid_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  signal rxvalid_reg2 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal txcompliance_reg1 : STD_LOGIC;
  signal txcompliance_reg2 : STD_LOGIC;
  signal txelecidle_reg1 : STD_LOGIC;
  signal txelecidle_reg2 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal \NLW_converge_cnt_reg[21]_i_2__1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__1_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_converge_cnt_reg[21]_i_2__1_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[13]_i_2__1_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[13]_i_2__1_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[17]_i_2__1_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[17]_i_2__1_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[1]_i_2__1_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[1]_i_2__1_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[21]_i_2__1_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[21]_i_2__1_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[5]_i_2__1_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[5]_i_2__1_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[9]_i_2__1_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[9]_i_2__1_CARRY4\ : label is "LO:O";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_5__1\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1__1\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1__1\ : label is "soft_lutpair87";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute ASYNC_REG of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_done_reg1_i_1__1\ : label is "soft_lutpair88";
  attribute ASYNC_REG of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
begin
  p_0_in7_in <= txcompliance_reg2;
  p_1_in8_in <= txelecidle_reg2;
  p_2_in <= rst_idle_reg2;
\converge_cnt[0]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => RST_CPLLRESET,
      I3 => rate_gen3_reg2,
      O => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt[0]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5D555D"
    )
        port map (
      I0 => converge_cnt_reg(21),
      I1 => \converge_cnt[0]_i_4__1_n_0\,
      I2 => converge_cnt_reg(20),
      I3 => \converge_cnt[0]_i_5__1_n_0\,
      I4 => \converge_cnt[0]_i_6__1_n_0\,
      O => sel
    );
\converge_cnt[0]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => converge_cnt_reg(13),
      I3 => converge_cnt_reg(16),
      I4 => converge_cnt_reg(15),
      I5 => \converge_cnt[0]_i_8__1_n_0\,
      O => \converge_cnt[0]_i_4__1_n_0\
    );
\converge_cnt[0]_i_5__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \converge_cnt[0]_i_8__1_n_0\,
      I1 => converge_cnt_reg(16),
      I2 => converge_cnt_reg(15),
      I3 => converge_cnt_reg(13),
      I4 => converge_cnt_reg(11),
      O => \converge_cnt[0]_i_5__1_n_0\
    );
\converge_cnt[0]_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(3),
      I1 => converge_cnt_reg(6),
      I2 => \converge_cnt[0]_i_9__1_n_0\,
      I3 => converge_cnt_reg(10),
      I4 => converge_cnt_reg(8),
      I5 => converge_cnt_reg(9),
      O => \converge_cnt[0]_i_6__1_n_0\
    );
\converge_cnt[0]_i_7__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => converge_cnt_reg(0),
      O => \converge_cnt[0]_i_7__1_n_0\
    );
\converge_cnt[0]_i_8__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => converge_cnt_reg(17),
      I1 => converge_cnt_reg(18),
      I2 => converge_cnt_reg(19),
      O => \converge_cnt[0]_i_8__1_n_0\
    );
\converge_cnt[0]_i_9__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => converge_cnt_reg(4),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(7),
      O => \converge_cnt[0]_i_9__1_n_0\
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__1_n_0\,
      Q => converge_cnt_reg(0),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[10]_i_1__1_n_0\,
      Q => converge_cnt_reg(10),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[11]_i_1__1_n_0\,
      Q => converge_cnt_reg(11),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__1_n_0\,
      Q => converge_cnt_reg(12),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[13]_i_1__1_n_0\,
      Q => converge_cnt_reg(13),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[13]_i_2__1_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_2__1_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_2__1_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__1_n_0\,
      CO(1) => \converge_cnt_reg[14]_i_2__1_n_0\,
      CO(0) => \converge_cnt_reg[13]_i_2__1_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[15]_i_1__1_n_0\,
      O(2) => \converge_cnt_reg[14]_i_1__1_n_0\,
      O(1) => \converge_cnt_reg[13]_i_1__1_n_0\,
      O(0) => \converge_cnt_reg[12]_i_1__1_n_0\,
      S(3 downto 0) => converge_cnt_reg(15 downto 12)
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[14]_i_1__1_n_0\,
      Q => converge_cnt_reg(14),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[15]_i_1__1_n_0\,
      Q => converge_cnt_reg(15),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__1_n_0\,
      Q => converge_cnt_reg(16),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[17]_i_1__1_n_0\,
      Q => converge_cnt_reg(17),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[17]_i_2__1_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_2__1_n_0\,
      CO(3) => \converge_cnt_reg[20]_i_2__1_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__1_n_0\,
      CO(1) => \converge_cnt_reg[18]_i_2__1_n_0\,
      CO(0) => \converge_cnt_reg[17]_i_2__1_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[19]_i_1__1_n_0\,
      O(2) => \converge_cnt_reg[18]_i_1__1_n_0\,
      O(1) => \converge_cnt_reg[17]_i_1__1_n_0\,
      O(0) => \converge_cnt_reg[16]_i_1__1_n_0\,
      S(3 downto 0) => converge_cnt_reg(19 downto 16)
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[18]_i_1__1_n_0\,
      Q => converge_cnt_reg(18),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[19]_i_1__1_n_0\,
      Q => converge_cnt_reg(19),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[1]_i_1__1_n_0\,
      Q => converge_cnt_reg(1),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[1]_i_2__1_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[4]_i_2__1_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__1_n_0\,
      CO(1) => \converge_cnt_reg[2]_i_2__1_n_0\,
      CO(0) => \converge_cnt_reg[1]_i_2__1_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '1',
      O(3) => \converge_cnt_reg[3]_i_1__1_n_0\,
      O(2) => \converge_cnt_reg[2]_i_1__1_n_0\,
      O(1) => \converge_cnt_reg[1]_i_1__1_n_0\,
      O(0) => \converge_cnt_reg[0]_i_3__1_n_0\,
      S(3 downto 1) => converge_cnt_reg(3 downto 1),
      S(0) => \converge_cnt[0]_i_7__1_n_0\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1__1_n_0\,
      Q => converge_cnt_reg(20),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[21]_i_1__1_n_0\,
      Q => converge_cnt_reg(21),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[21]_i_2__1_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[20]_i_2__1_n_0\,
      CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__1_CARRY4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__1_CARRY4_DI_UNCONNECTED\(3 downto 1),
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__1_CARRY4_O_UNCONNECTED\(3 downto 2),
      O(1) => \converge_cnt_reg[21]_i_1__1_n_0\,
      O(0) => \converge_cnt_reg[20]_i_1__1_n_0\,
      S(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__1_CARRY4_S_UNCONNECTED\(3 downto 2),
      S(1 downto 0) => converge_cnt_reg(21 downto 20)
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[2]_i_1__1_n_0\,
      Q => converge_cnt_reg(2),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[3]_i_1__1_n_0\,
      Q => converge_cnt_reg(3),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__1_n_0\,
      Q => converge_cnt_reg(4),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[5]_i_1__1_n_0\,
      Q => converge_cnt_reg(5),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[5]_i_2__1_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_2__1_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_2__1_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__1_n_0\,
      CO(1) => \converge_cnt_reg[6]_i_2__1_n_0\,
      CO(0) => \converge_cnt_reg[5]_i_2__1_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[7]_i_1__1_n_0\,
      O(2) => \converge_cnt_reg[6]_i_1__1_n_0\,
      O(1) => \converge_cnt_reg[5]_i_1__1_n_0\,
      O(0) => \converge_cnt_reg[4]_i_1__1_n_0\,
      S(3 downto 0) => converge_cnt_reg(7 downto 4)
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[6]_i_1__1_n_0\,
      Q => converge_cnt_reg(6),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[7]_i_1__1_n_0\,
      Q => converge_cnt_reg(7),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__1_n_0\,
      Q => converge_cnt_reg(8),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[9]_i_1__1_n_0\,
      Q => converge_cnt_reg(9),
      R => \converge_cnt[0]_i_1__1_n_0\
    );
\converge_cnt_reg[9]_i_2__1_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_2__1_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_2__1_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__1_n_0\,
      CO(1) => \converge_cnt_reg[10]_i_2__1_n_0\,
      CO(0) => \converge_cnt_reg[9]_i_2__1_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[11]_i_1__1_n_0\,
      O(2) => \converge_cnt_reg[10]_i_1__1_n_0\,
      O(1) => \converge_cnt_reg[9]_i_1__1_n_0\,
      O(0) => \converge_cnt_reg[8]_i_1__1_n_0\,
      S(3 downto 0) => converge_cnt_reg(11 downto 8)
    );
\converge_gen3_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0C08"
    )
        port map (
      I0 => rxeq_adapt_done_reg2,
      I1 => rate_gen3_reg2,
      I2 => RST_CPLLRESET,
      I3 => converge_gen3_reg_n_0,
      O => \converge_gen3_i_1__1_n_0\
    );
converge_gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \converge_gen3_i_1__1_n_0\,
      Q => converge_gen3_reg_n_0,
      R => '0'
    );
\gt_rx_phy_status_q_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => RST_PHYSTATUS(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => gt_rx_phy_status_wire_filter(0)
    );
\gt_rxvalid_q_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4500000000000000"
    )
        port map (
      I0 => \gt_rxvalid_q_i_6__1_n_0\,
      I1 => gt_rxvalid_q_reg_0,
      I2 => gt_rx_elec_idle_wire_filter(0),
      I3 => rst_idle_reg2,
      I4 => rate_idle_reg2,
      I5 => \resetovrd_disble.reset_reg[4]_0\,
      O => gt_rxvalid_q_reg
    );
\gt_rxvalid_q_i_6__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(1),
      O => \gt_rxvalid_q_i_6__1_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_5__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => \cplllock_reg1_reg[2]\
    );
\gtx_channel.gtxe2_channel_i_i_66\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => converge_gen3_reg_n_0,
      I1 => \gtx_channel.gtxe2_channel_i_i_77_n_0\,
      I2 => converge_cnt_reg(8),
      I3 => converge_cnt_reg(9),
      I4 => \converge_cnt[0]_i_9__1_n_0\,
      I5 => \converge_cnt[0]_i_5__1_n_0\,
      O => user_rx_converge(0)
    );
\gtx_channel.gtxe2_channel_i_i_77\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => \gtx_channel.gtxe2_channel_i_i_85_n_0\,
      I3 => converge_cnt_reg(2),
      I4 => converge_cnt_reg(6),
      O => \gtx_channel.gtxe2_channel_i_i_77_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_85\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => converge_cnt_reg(20),
      I1 => converge_cnt_reg(3),
      I2 => converge_cnt_reg(0),
      I3 => converge_cnt_reg(1),
      I4 => converge_cnt_reg(10),
      I5 => converge_cnt_reg(21),
      O => \gtx_channel.gtxe2_channel_i_i_85_n_0\
    );
\oobclk_div.oobclk_cnt[0]_i_1__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1__1_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \oobclk_div.oobclk_i_1__1_n_0\,
      Q => USER_OOBCLK,
      R => RST_CPLLRESET
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => CLK_PCLK_SEL(0),
      Q => pclk_sel_reg1,
      R => RST_CPLLRESET
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => RST_CPLLRESET
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_DONE,
      Q => rate_done_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => rate_gen3_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_RXSYNC,
      Q => rate_rxsync_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => RST_RXUSRCLK_RESET
    );
\resetdone_reg1[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txresetdone_reg2,
      I1 => rxresetdone_reg2,
      O => RST_RESETDONE(0)
    );
\resetovrd_disble.fsm_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(0),
      R => '0'
    );
\resetovrd_disble.fsm_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(0),
      R => '0'
    );
\resetovrd_disble.reset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(2),
      R => '0'
    );
\resetovrd_disble.reset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(3),
      R => '0'
    );
\resetovrd_disble.reset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(4),
      R => '0'
    );
\resetovrd_disble.reset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(5),
      R => '0'
    );
\resetovrd_disble.reset_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(6),
      R => '0'
    );
\resetovrd_done_reg1_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => resetovrd_done_reg1_reg
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RESETOVRD_START,
      Q => resetovrd_start_reg1,
      R => RST_CPLLRESET
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => RST_CPLLRESET
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => out1(0),
      Q => rst_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxcdrlock_cnt[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(2),
      I2 => \rxcdrlock_cnt_reg__0\(0),
      I3 => \rxcdrlock_cnt_reg__0\(1),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(0)
    );
\rxcdrlock_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(0),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(2),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(1)
    );
\rxcdrlock_cnt[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8CCCC000"
    )
        port map (
      I0 => \rxcdrlock_cnt_reg__0\(3),
      I1 => rxcdrlock_reg2,
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(2)
    );
\rxcdrlock_cnt[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \rxcdrlock_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \rxcdrlock_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \rxcdrlock_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \rxcdrlock_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\rxcdrlock_reg1[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \resetovrd_disble.reset_reg[4]_1\,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => RST_RXCDRLOCK(0)
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXEQ_ADAPT_DONE,
      Q => rxeq_adapt_done_reg1,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pipe_rxstatus(0),
      Q => rxstatus_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(1),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => \rxvalid_cnt_reg__0\(0),
      O => \p_0_in__0__0\(0)
    );
\rxvalid_cnt[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000E6660000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(0),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(1)
    );
\rxvalid_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000EA6A0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(2),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(2)
    );
\rxvalid_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D444444400000000"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => \rxvalid_cnt_reg__0\(3),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(0),
      I4 => \rxvalid_cnt_reg__0\(1),
      I5 => rxvalid_reg2,
      O => \p_0_in__0__0\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(0),
      Q => \rxvalid_cnt_reg__0\(0),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(1),
      Q => \rxvalid_cnt_reg__0\(1),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(2),
      Q => \rxvalid_cnt_reg__0\(2),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(3),
      Q => \rxvalid_cnt_reg__0\(3),
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxvalid_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => RST_RXUSRCLK_RESET
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXCOMPLIANCE(0),
      Q => txcompliance_reg1,
      R => RST_CPLLRESET
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => RST_CPLLRESET
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXELECIDLE(0),
      Q => txelecidle_reg1,
      R => RST_CPLLRESET
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_i_10: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      O => user_active_lane(0)
    );
txphaligndone_reg1_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0707070707FFFFFF"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      I2 => pipe_txphaligndone(1),
      I3 => p_1_in8_in_0,
      I4 => p_0_in7_in_1,
      I5 => pipe_txphaligndone(0),
      O => txphaligndone_reg1_reg
    );
txphinitdone_reg1_i_7: unisim.vcomponents.LUT5
    generic map(
      INIT => X"002AAAAA"
    )
        port map (
      I0 => pipe_txphinitdone(0),
      I1 => txcompliance_reg2,
      I2 => txelecidle_reg2,
      I3 => pipe_txphinitdone(1),
      I4 => txelecidle_reg2_reg_0,
      O => txphinitdone_reg1_reg
    );
txphinitdone_reg1_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"151515FF15FF15FF"
    )
        port map (
      I0 => pipe_txphinitdone(1),
      I1 => txelecidle_reg2,
      I2 => txcompliance_reg2,
      I3 => pipe_txphinitdone(2),
      I4 => p_1_in8_in_2,
      I5 => p_0_in7_in_3,
      O => txphinitdone_reg1_reg_0
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_46 is
  port (
    txphaligndone_reg1_reg : out STD_LOGIC;
    user_active_lane : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg : out STD_LOGIC;
    p_2_in : out STD_LOGIC;
    p_0_in7_in : out STD_LOGIC;
    p_1_in8_in : out STD_LOGIC;
    USER_OOBCLK : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_rx_converge : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    resetovrd_done_reg1_reg : out STD_LOGIC;
    RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    txcompliance_reg2_reg_0 : in STD_LOGIC;
    txelecidle_reg2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphaligndone : in STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    CLK_PCLK_SEL : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXRESETDONE : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC;
    RST_RXUSRCLK_RESET : in STD_LOGIC;
    pipe_rxstatus : in STD_LOGIC_VECTOR ( 0 to 0 );
    out1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RATE_RXSYNC : in STD_LOGIC;
    USER_RATE_DONE : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    USER_RESETOVRD_START : in STD_LOGIC;
    RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_46 : entity is "PCIeGen1x8If64_pipe_user";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_46;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_46 is
  signal \converge_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_4__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_5__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_6__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_7__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_8__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_9__2_n_0\ : STD_LOGIC;
  signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[0]_i_3__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_1__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_gen3_i_1__2_n_0\ : STD_LOGIC;
  signal converge_gen3_reg_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gt_rxvalid_q_i_6__2_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_76_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_84_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1__2_n_0\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  signal pclk_sel_reg2 : STD_LOGIC;
  signal rate_done_reg1 : STD_LOGIC;
  signal rate_done_reg2 : STD_LOGIC;
  signal rate_gen3_reg1 : STD_LOGIC;
  signal rate_gen3_reg2 : STD_LOGIC;
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rate_rxsync_reg1 : STD_LOGIC;
  signal rate_rxsync_reg2 : STD_LOGIC;
  signal resetovrd_start_reg1 : STD_LOGIC;
  signal resetovrd_start_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal \rxcdrlock_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxstatus_reg1 : STD_LOGIC;
  signal rxstatus_reg2 : STD_LOGIC;
  signal \rxvalid_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  signal rxvalid_reg2 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal txcompliance_reg1 : STD_LOGIC;
  signal txcompliance_reg2 : STD_LOGIC;
  signal txelecidle_reg1 : STD_LOGIC;
  signal txelecidle_reg2 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal \^user_active_lane\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__2_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__2_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__2_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_converge_cnt_reg[21]_i_2__2_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[13]_i_2__2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[13]_i_2__2_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[17]_i_2__2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[17]_i_2__2_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[1]_i_2__2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[1]_i_2__2_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[21]_i_2__2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[21]_i_2__2_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[5]_i_2__2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[5]_i_2__2_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[9]_i_2__2_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[9]_i_2__2_CARRY4\ : label is "LO:O";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_5__2\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1__2\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1__2\ : label is "soft_lutpair110";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute ASYNC_REG of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_done_reg1_i_1__2\ : label is "soft_lutpair109";
  attribute ASYNC_REG of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
begin
  p_0_in7_in <= txcompliance_reg2;
  p_1_in8_in <= txelecidle_reg2;
  p_2_in <= rst_idle_reg2;
  user_active_lane(0) <= \^user_active_lane\(0);
\converge_cnt[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => RST_CPLLRESET,
      I3 => rate_gen3_reg2,
      O => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt[0]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5D555D"
    )
        port map (
      I0 => converge_cnt_reg(21),
      I1 => \converge_cnt[0]_i_4__2_n_0\,
      I2 => converge_cnt_reg(20),
      I3 => \converge_cnt[0]_i_5__2_n_0\,
      I4 => \converge_cnt[0]_i_6__2_n_0\,
      O => sel
    );
\converge_cnt[0]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => converge_cnt_reg(13),
      I3 => converge_cnt_reg(16),
      I4 => converge_cnt_reg(15),
      I5 => \converge_cnt[0]_i_8__2_n_0\,
      O => \converge_cnt[0]_i_4__2_n_0\
    );
\converge_cnt[0]_i_5__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \converge_cnt[0]_i_8__2_n_0\,
      I1 => converge_cnt_reg(16),
      I2 => converge_cnt_reg(15),
      I3 => converge_cnt_reg(13),
      I4 => converge_cnt_reg(11),
      O => \converge_cnt[0]_i_5__2_n_0\
    );
\converge_cnt[0]_i_6__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(3),
      I1 => converge_cnt_reg(6),
      I2 => \converge_cnt[0]_i_9__2_n_0\,
      I3 => converge_cnt_reg(10),
      I4 => converge_cnt_reg(8),
      I5 => converge_cnt_reg(9),
      O => \converge_cnt[0]_i_6__2_n_0\
    );
\converge_cnt[0]_i_7__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => converge_cnt_reg(0),
      O => \converge_cnt[0]_i_7__2_n_0\
    );
\converge_cnt[0]_i_8__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => converge_cnt_reg(17),
      I1 => converge_cnt_reg(18),
      I2 => converge_cnt_reg(19),
      O => \converge_cnt[0]_i_8__2_n_0\
    );
\converge_cnt[0]_i_9__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => converge_cnt_reg(4),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(7),
      O => \converge_cnt[0]_i_9__2_n_0\
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__2_n_0\,
      Q => converge_cnt_reg(0),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[10]_i_1__2_n_0\,
      Q => converge_cnt_reg(10),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[11]_i_1__2_n_0\,
      Q => converge_cnt_reg(11),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__2_n_0\,
      Q => converge_cnt_reg(12),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[13]_i_1__2_n_0\,
      Q => converge_cnt_reg(13),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[13]_i_2__2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_2__2_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_2__2_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__2_n_0\,
      CO(1) => \converge_cnt_reg[14]_i_2__2_n_0\,
      CO(0) => \converge_cnt_reg[13]_i_2__2_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[15]_i_1__2_n_0\,
      O(2) => \converge_cnt_reg[14]_i_1__2_n_0\,
      O(1) => \converge_cnt_reg[13]_i_1__2_n_0\,
      O(0) => \converge_cnt_reg[12]_i_1__2_n_0\,
      S(3 downto 0) => converge_cnt_reg(15 downto 12)
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[14]_i_1__2_n_0\,
      Q => converge_cnt_reg(14),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[15]_i_1__2_n_0\,
      Q => converge_cnt_reg(15),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__2_n_0\,
      Q => converge_cnt_reg(16),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[17]_i_1__2_n_0\,
      Q => converge_cnt_reg(17),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[17]_i_2__2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_2__2_n_0\,
      CO(3) => \converge_cnt_reg[20]_i_2__2_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__2_n_0\,
      CO(1) => \converge_cnt_reg[18]_i_2__2_n_0\,
      CO(0) => \converge_cnt_reg[17]_i_2__2_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[19]_i_1__2_n_0\,
      O(2) => \converge_cnt_reg[18]_i_1__2_n_0\,
      O(1) => \converge_cnt_reg[17]_i_1__2_n_0\,
      O(0) => \converge_cnt_reg[16]_i_1__2_n_0\,
      S(3 downto 0) => converge_cnt_reg(19 downto 16)
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[18]_i_1__2_n_0\,
      Q => converge_cnt_reg(18),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[19]_i_1__2_n_0\,
      Q => converge_cnt_reg(19),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[1]_i_1__2_n_0\,
      Q => converge_cnt_reg(1),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[1]_i_2__2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[4]_i_2__2_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__2_n_0\,
      CO(1) => \converge_cnt_reg[2]_i_2__2_n_0\,
      CO(0) => \converge_cnt_reg[1]_i_2__2_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '1',
      O(3) => \converge_cnt_reg[3]_i_1__2_n_0\,
      O(2) => \converge_cnt_reg[2]_i_1__2_n_0\,
      O(1) => \converge_cnt_reg[1]_i_1__2_n_0\,
      O(0) => \converge_cnt_reg[0]_i_3__2_n_0\,
      S(3 downto 1) => converge_cnt_reg(3 downto 1),
      S(0) => \converge_cnt[0]_i_7__2_n_0\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1__2_n_0\,
      Q => converge_cnt_reg(20),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[21]_i_1__2_n_0\,
      Q => converge_cnt_reg(21),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[21]_i_2__2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[20]_i_2__2_n_0\,
      CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__2_CARRY4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__2_CARRY4_DI_UNCONNECTED\(3 downto 1),
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__2_CARRY4_O_UNCONNECTED\(3 downto 2),
      O(1) => \converge_cnt_reg[21]_i_1__2_n_0\,
      O(0) => \converge_cnt_reg[20]_i_1__2_n_0\,
      S(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__2_CARRY4_S_UNCONNECTED\(3 downto 2),
      S(1 downto 0) => converge_cnt_reg(21 downto 20)
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[2]_i_1__2_n_0\,
      Q => converge_cnt_reg(2),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[3]_i_1__2_n_0\,
      Q => converge_cnt_reg(3),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__2_n_0\,
      Q => converge_cnt_reg(4),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[5]_i_1__2_n_0\,
      Q => converge_cnt_reg(5),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[5]_i_2__2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_2__2_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_2__2_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__2_n_0\,
      CO(1) => \converge_cnt_reg[6]_i_2__2_n_0\,
      CO(0) => \converge_cnt_reg[5]_i_2__2_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[7]_i_1__2_n_0\,
      O(2) => \converge_cnt_reg[6]_i_1__2_n_0\,
      O(1) => \converge_cnt_reg[5]_i_1__2_n_0\,
      O(0) => \converge_cnt_reg[4]_i_1__2_n_0\,
      S(3 downto 0) => converge_cnt_reg(7 downto 4)
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[6]_i_1__2_n_0\,
      Q => converge_cnt_reg(6),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[7]_i_1__2_n_0\,
      Q => converge_cnt_reg(7),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__2_n_0\,
      Q => converge_cnt_reg(8),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[9]_i_1__2_n_0\,
      Q => converge_cnt_reg(9),
      R => \converge_cnt[0]_i_1__2_n_0\
    );
\converge_cnt_reg[9]_i_2__2_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_2__2_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_2__2_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__2_n_0\,
      CO(1) => \converge_cnt_reg[10]_i_2__2_n_0\,
      CO(0) => \converge_cnt_reg[9]_i_2__2_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[11]_i_1__2_n_0\,
      O(2) => \converge_cnt_reg[10]_i_1__2_n_0\,
      O(1) => \converge_cnt_reg[9]_i_1__2_n_0\,
      O(0) => \converge_cnt_reg[8]_i_1__2_n_0\,
      S(3 downto 0) => converge_cnt_reg(11 downto 8)
    );
\converge_gen3_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0C08"
    )
        port map (
      I0 => rxeq_adapt_done_reg2,
      I1 => rate_gen3_reg2,
      I2 => RST_CPLLRESET,
      I3 => converge_gen3_reg_n_0,
      O => \converge_gen3_i_1__2_n_0\
    );
converge_gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \converge_gen3_i_1__2_n_0\,
      Q => converge_gen3_reg_n_0,
      R => '0'
    );
\gt_rx_phy_status_q_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => RST_PHYSTATUS(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => gt_rx_phy_status_wire_filter(0)
    );
\gt_rxvalid_q_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4500000000000000"
    )
        port map (
      I0 => \gt_rxvalid_q_i_6__2_n_0\,
      I1 => gt_rxvalid_q_reg_0,
      I2 => gt_rx_elec_idle_wire_filter(0),
      I3 => rst_idle_reg2,
      I4 => rate_idle_reg2,
      I5 => \resetovrd_disble.reset_reg[4]_0\,
      O => gt_rxvalid_q_reg
    );
\gt_rxvalid_q_i_6__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(1),
      O => \gt_rxvalid_q_i_6__2_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => \cplllock_reg1_reg[3]\
    );
\gtx_channel.gtxe2_channel_i_i_65\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => converge_gen3_reg_n_0,
      I1 => \gtx_channel.gtxe2_channel_i_i_76_n_0\,
      I2 => converge_cnt_reg(8),
      I3 => converge_cnt_reg(9),
      I4 => \converge_cnt[0]_i_9__2_n_0\,
      I5 => \converge_cnt[0]_i_5__2_n_0\,
      O => user_rx_converge(0)
    );
\gtx_channel.gtxe2_channel_i_i_76\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => \gtx_channel.gtxe2_channel_i_i_84_n_0\,
      I3 => converge_cnt_reg(2),
      I4 => converge_cnt_reg(6),
      O => \gtx_channel.gtxe2_channel_i_i_76_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_84\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => converge_cnt_reg(20),
      I1 => converge_cnt_reg(3),
      I2 => converge_cnt_reg(0),
      I3 => converge_cnt_reg(1),
      I4 => converge_cnt_reg(10),
      I5 => converge_cnt_reg(21),
      O => \gtx_channel.gtxe2_channel_i_i_84_n_0\
    );
\oobclk_div.oobclk_cnt[0]_i_1__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1__2_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \oobclk_div.oobclk_i_1__2_n_0\,
      Q => USER_OOBCLK,
      R => RST_CPLLRESET
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => CLK_PCLK_SEL(0),
      Q => pclk_sel_reg1,
      R => RST_CPLLRESET
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => RST_CPLLRESET
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_DONE,
      Q => rate_done_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => rate_gen3_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_RXSYNC,
      Q => rate_rxsync_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => RST_RXUSRCLK_RESET
    );
\resetdone_reg1[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txresetdone_reg2,
      I1 => rxresetdone_reg2,
      O => RST_RESETDONE(0)
    );
\resetovrd_disble.fsm_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(0),
      R => '0'
    );
\resetovrd_disble.fsm_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(0),
      R => '0'
    );
\resetovrd_disble.reset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(2),
      R => '0'
    );
\resetovrd_disble.reset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(3),
      R => '0'
    );
\resetovrd_disble.reset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(4),
      R => '0'
    );
\resetovrd_disble.reset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(5),
      R => '0'
    );
\resetovrd_disble.reset_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(6),
      R => '0'
    );
\resetovrd_done_reg1_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => resetovrd_done_reg1_reg
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RESETOVRD_START,
      Q => resetovrd_start_reg1,
      R => RST_CPLLRESET
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => RST_CPLLRESET
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => out1(0),
      Q => rst_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxcdrlock_cnt[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(2),
      I2 => \rxcdrlock_cnt_reg__0\(0),
      I3 => \rxcdrlock_cnt_reg__0\(1),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(0)
    );
\rxcdrlock_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(0),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(2),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(1)
    );
\rxcdrlock_cnt[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8CCCC000"
    )
        port map (
      I0 => \rxcdrlock_cnt_reg__0\(3),
      I1 => rxcdrlock_reg2,
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(2)
    );
\rxcdrlock_cnt[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \rxcdrlock_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \rxcdrlock_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \rxcdrlock_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \rxcdrlock_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\rxcdrlock_reg1[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \resetovrd_disble.reset_reg[4]_1\,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => RST_RXCDRLOCK(0)
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXEQ_ADAPT_DONE,
      Q => rxeq_adapt_done_reg1,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pipe_rxstatus(0),
      Q => rxstatus_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(1),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => \rxvalid_cnt_reg__0\(0),
      O => \p_0_in__0__0\(0)
    );
\rxvalid_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000E6660000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(0),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(1)
    );
\rxvalid_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000EA6A0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(2),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(2)
    );
\rxvalid_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D444444400000000"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => \rxvalid_cnt_reg__0\(3),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(0),
      I4 => \rxvalid_cnt_reg__0\(1),
      I5 => rxvalid_reg2,
      O => \p_0_in__0__0\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(0),
      Q => \rxvalid_cnt_reg__0\(0),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(1),
      Q => \rxvalid_cnt_reg__0\(1),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(2),
      Q => \rxvalid_cnt_reg__0\(2),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(3),
      Q => \rxvalid_cnt_reg__0\(3),
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxvalid_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => RST_RXUSRCLK_RESET
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXCOMPLIANCE(0),
      Q => txcompliance_reg1,
      R => RST_CPLLRESET
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => RST_CPLLRESET
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXELECIDLE(0),
      Q => txelecidle_reg1,
      R => RST_CPLLRESET
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBABBBABAAAABBAB"
    )
        port map (
      I0 => \^user_active_lane\(0),
      I1 => txcompliance_reg2_reg_0,
      I2 => txelecidle_reg2_reg_0(0),
      I3 => pipe_txphaligndone(0),
      I4 => txelecidle_reg2_reg_0(1),
      I5 => pipe_txphaligndone(1),
      O => txphaligndone_reg1_reg
    );
txphaligndone_reg1_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      O => \^user_active_lane\(0)
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_53 is
  port (
    txphinitdone_reg1_reg : out STD_LOGIC;
    p_0_in7_in : out STD_LOGIC;
    p_1_in8_in : out STD_LOGIC;
    txphaligndone_reg1_reg : out STD_LOGIC;
    gt_rxvalid_q_reg : out STD_LOGIC;
    p_2_in : out STD_LOGIC;
    USER_OOBCLK : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_216_out : out STD_LOGIC;
    \cplllock_reg1_reg[4]\ : out STD_LOGIC;
    resetovrd_done_reg1_reg : out STD_LOGIC;
    RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    txelecidle_reg2_reg_0 : in STD_LOGIC;
    txelecidle_reg2_reg_1 : in STD_LOGIC;
    pipe_txphinitdone : in STD_LOGIC_VECTOR ( 2 downto 0 );
    user_active_lane : in STD_LOGIC_VECTOR ( 0 to 0 );
    txcompliance_reg2_reg_0 : in STD_LOGIC;
    pipe_txphaligndone : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_1_in8_in_0 : in STD_LOGIC;
    p_0_in7_in_1 : in STD_LOGIC;
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    CLK_PCLK_SEL : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXRESETDONE : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC;
    RST_RXUSRCLK_RESET : in STD_LOGIC;
    pipe_rxstatus : in STD_LOGIC_VECTOR ( 0 to 0 );
    out1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RATE_RXSYNC : in STD_LOGIC;
    USER_RATE_DONE : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    USER_RESETOVRD_START : in STD_LOGIC;
    RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_53 : entity is "PCIeGen1x8If64_pipe_user";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_53;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_53 is
  signal \converge_cnt[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_4__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_5__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_6__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_7__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_8__3_n_0\ : STD_LOGIC;
  signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[0]_i_3__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_1__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_gen3_i_1__3_n_0\ : STD_LOGIC;
  signal converge_gen3_reg_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gt_rxvalid_q_i_6__3_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_67_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_68_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_78_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1__3_n_0\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  signal pclk_sel_reg2 : STD_LOGIC;
  signal rate_done_reg1 : STD_LOGIC;
  signal rate_done_reg2 : STD_LOGIC;
  signal rate_gen3_reg1 : STD_LOGIC;
  signal rate_gen3_reg2 : STD_LOGIC;
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rate_rxsync_reg1 : STD_LOGIC;
  signal rate_rxsync_reg2 : STD_LOGIC;
  signal resetovrd_start_reg1 : STD_LOGIC;
  signal resetovrd_start_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal \rxcdrlock_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxstatus_reg1 : STD_LOGIC;
  signal rxstatus_reg2 : STD_LOGIC;
  signal \rxvalid_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  signal rxvalid_reg2 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal txcompliance_reg1 : STD_LOGIC;
  signal txcompliance_reg2 : STD_LOGIC;
  signal txelecidle_reg1 : STD_LOGIC;
  signal txelecidle_reg2 : STD_LOGIC;
  signal txphinitdone_reg1_i_3_n_0 : STD_LOGIC;
  signal txphinitdone_reg1_i_5_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal \NLW_converge_cnt_reg[21]_i_2__3_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__3_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__3_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_converge_cnt_reg[21]_i_2__3_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[13]_i_2__3_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[13]_i_2__3_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[17]_i_2__3_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[17]_i_2__3_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[1]_i_2__3_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[1]_i_2__3_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[21]_i_2__3_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[21]_i_2__3_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[5]_i_2__3_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[5]_i_2__3_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[9]_i_2__3_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[9]_i_2__3_CARRY4\ : label is "LO:O";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_5__3\ : label is "soft_lutpair145";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1__3\ : label is "soft_lutpair146";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1__3\ : label is "soft_lutpair146";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute ASYNC_REG of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_done_reg1_i_1__3\ : label is "soft_lutpair145";
  attribute ASYNC_REG of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
begin
  p_0_in7_in <= txcompliance_reg2;
  p_1_in8_in <= txelecidle_reg2;
  p_2_in <= rst_idle_reg2;
\converge_cnt[0]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => RST_CPLLRESET,
      I3 => rate_gen3_reg2,
      O => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt[0]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5D555D"
    )
        port map (
      I0 => converge_cnt_reg(21),
      I1 => \converge_cnt[0]_i_4__3_n_0\,
      I2 => converge_cnt_reg(20),
      I3 => \converge_cnt[0]_i_5__3_n_0\,
      I4 => \converge_cnt[0]_i_6__3_n_0\,
      O => sel
    );
\converge_cnt[0]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => converge_cnt_reg(13),
      I3 => converge_cnt_reg(16),
      I4 => converge_cnt_reg(15),
      I5 => \converge_cnt[0]_i_8__3_n_0\,
      O => \converge_cnt[0]_i_4__3_n_0\
    );
\converge_cnt[0]_i_5__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \converge_cnt[0]_i_8__3_n_0\,
      I1 => converge_cnt_reg(16),
      I2 => converge_cnt_reg(15),
      I3 => converge_cnt_reg(13),
      I4 => converge_cnt_reg(11),
      O => \converge_cnt[0]_i_5__3_n_0\
    );
\converge_cnt[0]_i_6__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(3),
      I1 => converge_cnt_reg(6),
      I2 => \gtx_channel.gtxe2_channel_i_i_68_n_0\,
      I3 => converge_cnt_reg(10),
      I4 => converge_cnt_reg(8),
      I5 => converge_cnt_reg(9),
      O => \converge_cnt[0]_i_6__3_n_0\
    );
\converge_cnt[0]_i_7__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => converge_cnt_reg(0),
      O => \converge_cnt[0]_i_7__3_n_0\
    );
\converge_cnt[0]_i_8__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => converge_cnt_reg(17),
      I1 => converge_cnt_reg(18),
      I2 => converge_cnt_reg(19),
      O => \converge_cnt[0]_i_8__3_n_0\
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__3_n_0\,
      Q => converge_cnt_reg(0),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[10]_i_1__3_n_0\,
      Q => converge_cnt_reg(10),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[11]_i_1__3_n_0\,
      Q => converge_cnt_reg(11),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__3_n_0\,
      Q => converge_cnt_reg(12),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[13]_i_1__3_n_0\,
      Q => converge_cnt_reg(13),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[13]_i_2__3_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_2__3_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_2__3_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__3_n_0\,
      CO(1) => \converge_cnt_reg[14]_i_2__3_n_0\,
      CO(0) => \converge_cnt_reg[13]_i_2__3_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[15]_i_1__3_n_0\,
      O(2) => \converge_cnt_reg[14]_i_1__3_n_0\,
      O(1) => \converge_cnt_reg[13]_i_1__3_n_0\,
      O(0) => \converge_cnt_reg[12]_i_1__3_n_0\,
      S(3 downto 0) => converge_cnt_reg(15 downto 12)
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[14]_i_1__3_n_0\,
      Q => converge_cnt_reg(14),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[15]_i_1__3_n_0\,
      Q => converge_cnt_reg(15),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__3_n_0\,
      Q => converge_cnt_reg(16),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[17]_i_1__3_n_0\,
      Q => converge_cnt_reg(17),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[17]_i_2__3_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_2__3_n_0\,
      CO(3) => \converge_cnt_reg[20]_i_2__3_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__3_n_0\,
      CO(1) => \converge_cnt_reg[18]_i_2__3_n_0\,
      CO(0) => \converge_cnt_reg[17]_i_2__3_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[19]_i_1__3_n_0\,
      O(2) => \converge_cnt_reg[18]_i_1__3_n_0\,
      O(1) => \converge_cnt_reg[17]_i_1__3_n_0\,
      O(0) => \converge_cnt_reg[16]_i_1__3_n_0\,
      S(3 downto 0) => converge_cnt_reg(19 downto 16)
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[18]_i_1__3_n_0\,
      Q => converge_cnt_reg(18),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[19]_i_1__3_n_0\,
      Q => converge_cnt_reg(19),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[1]_i_1__3_n_0\,
      Q => converge_cnt_reg(1),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[1]_i_2__3_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[4]_i_2__3_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__3_n_0\,
      CO(1) => \converge_cnt_reg[2]_i_2__3_n_0\,
      CO(0) => \converge_cnt_reg[1]_i_2__3_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '1',
      O(3) => \converge_cnt_reg[3]_i_1__3_n_0\,
      O(2) => \converge_cnt_reg[2]_i_1__3_n_0\,
      O(1) => \converge_cnt_reg[1]_i_1__3_n_0\,
      O(0) => \converge_cnt_reg[0]_i_3__3_n_0\,
      S(3 downto 1) => converge_cnt_reg(3 downto 1),
      S(0) => \converge_cnt[0]_i_7__3_n_0\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1__3_n_0\,
      Q => converge_cnt_reg(20),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[21]_i_1__3_n_0\,
      Q => converge_cnt_reg(21),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[21]_i_2__3_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[20]_i_2__3_n_0\,
      CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__3_CARRY4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__3_CARRY4_DI_UNCONNECTED\(3 downto 1),
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__3_CARRY4_O_UNCONNECTED\(3 downto 2),
      O(1) => \converge_cnt_reg[21]_i_1__3_n_0\,
      O(0) => \converge_cnt_reg[20]_i_1__3_n_0\,
      S(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__3_CARRY4_S_UNCONNECTED\(3 downto 2),
      S(1 downto 0) => converge_cnt_reg(21 downto 20)
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[2]_i_1__3_n_0\,
      Q => converge_cnt_reg(2),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[3]_i_1__3_n_0\,
      Q => converge_cnt_reg(3),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__3_n_0\,
      Q => converge_cnt_reg(4),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[5]_i_1__3_n_0\,
      Q => converge_cnt_reg(5),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[5]_i_2__3_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_2__3_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_2__3_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__3_n_0\,
      CO(1) => \converge_cnt_reg[6]_i_2__3_n_0\,
      CO(0) => \converge_cnt_reg[5]_i_2__3_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[7]_i_1__3_n_0\,
      O(2) => \converge_cnt_reg[6]_i_1__3_n_0\,
      O(1) => \converge_cnt_reg[5]_i_1__3_n_0\,
      O(0) => \converge_cnt_reg[4]_i_1__3_n_0\,
      S(3 downto 0) => converge_cnt_reg(7 downto 4)
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[6]_i_1__3_n_0\,
      Q => converge_cnt_reg(6),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[7]_i_1__3_n_0\,
      Q => converge_cnt_reg(7),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__3_n_0\,
      Q => converge_cnt_reg(8),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[9]_i_1__3_n_0\,
      Q => converge_cnt_reg(9),
      R => \converge_cnt[0]_i_1__3_n_0\
    );
\converge_cnt_reg[9]_i_2__3_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_2__3_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_2__3_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__3_n_0\,
      CO(1) => \converge_cnt_reg[10]_i_2__3_n_0\,
      CO(0) => \converge_cnt_reg[9]_i_2__3_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[11]_i_1__3_n_0\,
      O(2) => \converge_cnt_reg[10]_i_1__3_n_0\,
      O(1) => \converge_cnt_reg[9]_i_1__3_n_0\,
      O(0) => \converge_cnt_reg[8]_i_1__3_n_0\,
      S(3 downto 0) => converge_cnt_reg(11 downto 8)
    );
\converge_gen3_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0C08"
    )
        port map (
      I0 => rxeq_adapt_done_reg2,
      I1 => rate_gen3_reg2,
      I2 => RST_CPLLRESET,
      I3 => converge_gen3_reg_n_0,
      O => \converge_gen3_i_1__3_n_0\
    );
converge_gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \converge_gen3_i_1__3_n_0\,
      Q => converge_gen3_reg_n_0,
      R => '0'
    );
\gt_rx_phy_status_q_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => RST_PHYSTATUS(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => gt_rx_phy_status_wire_filter(0)
    );
\gt_rxvalid_q_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4500000000000000"
    )
        port map (
      I0 => \gt_rxvalid_q_i_6__3_n_0\,
      I1 => gt_rxvalid_q_reg_0,
      I2 => gt_rx_elec_idle_wire_filter(0),
      I3 => rst_idle_reg2,
      I4 => rate_idle_reg2,
      I5 => \resetovrd_disble.reset_reg[4]_0\,
      O => gt_rxvalid_q_reg
    );
\gt_rxvalid_q_i_6__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(1),
      O => \gt_rxvalid_q_i_6__3_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_58\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => converge_gen3_reg_n_0,
      I1 => \gtx_channel.gtxe2_channel_i_i_67_n_0\,
      I2 => converge_cnt_reg(8),
      I3 => converge_cnt_reg(9),
      I4 => \gtx_channel.gtxe2_channel_i_i_68_n_0\,
      I5 => \converge_cnt[0]_i_5__3_n_0\,
      O => p_216_out
    );
\gtx_channel.gtxe2_channel_i_i_5__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => \cplllock_reg1_reg[4]\
    );
\gtx_channel.gtxe2_channel_i_i_67\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => \gtx_channel.gtxe2_channel_i_i_78_n_0\,
      I3 => converge_cnt_reg(2),
      I4 => converge_cnt_reg(6),
      O => \gtx_channel.gtxe2_channel_i_i_67_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_68\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => converge_cnt_reg(4),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(7),
      O => \gtx_channel.gtxe2_channel_i_i_68_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_78\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => converge_cnt_reg(20),
      I1 => converge_cnt_reg(3),
      I2 => converge_cnt_reg(0),
      I3 => converge_cnt_reg(1),
      I4 => converge_cnt_reg(10),
      I5 => converge_cnt_reg(21),
      O => \gtx_channel.gtxe2_channel_i_i_78_n_0\
    );
\oobclk_div.oobclk_cnt[0]_i_1__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1__3_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \oobclk_div.oobclk_i_1__3_n_0\,
      Q => USER_OOBCLK,
      R => RST_CPLLRESET
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => CLK_PCLK_SEL(0),
      Q => pclk_sel_reg1,
      R => RST_CPLLRESET
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => RST_CPLLRESET
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_DONE,
      Q => rate_done_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => rate_gen3_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_RXSYNC,
      Q => rate_rxsync_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => RST_RXUSRCLK_RESET
    );
\resetdone_reg1[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txresetdone_reg2,
      I1 => rxresetdone_reg2,
      O => RST_RESETDONE(0)
    );
\resetovrd_disble.fsm_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(0),
      R => '0'
    );
\resetovrd_disble.fsm_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(0),
      R => '0'
    );
\resetovrd_disble.reset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(2),
      R => '0'
    );
\resetovrd_disble.reset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(3),
      R => '0'
    );
\resetovrd_disble.reset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(4),
      R => '0'
    );
\resetovrd_disble.reset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(5),
      R => '0'
    );
\resetovrd_disble.reset_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(6),
      R => '0'
    );
\resetovrd_done_reg1_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => resetovrd_done_reg1_reg
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RESETOVRD_START,
      Q => resetovrd_start_reg1,
      R => RST_CPLLRESET
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => RST_CPLLRESET
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => out1(0),
      Q => rst_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxcdrlock_cnt[0]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(2),
      I2 => \rxcdrlock_cnt_reg__0\(0),
      I3 => \rxcdrlock_cnt_reg__0\(1),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(0)
    );
\rxcdrlock_cnt[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(0),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(2),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(1)
    );
\rxcdrlock_cnt[2]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8CCCC000"
    )
        port map (
      I0 => \rxcdrlock_cnt_reg__0\(3),
      I1 => rxcdrlock_reg2,
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(2)
    );
\rxcdrlock_cnt[3]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \rxcdrlock_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \rxcdrlock_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \rxcdrlock_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \rxcdrlock_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\rxcdrlock_reg1[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \resetovrd_disble.reset_reg[4]_1\,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => RST_RXCDRLOCK(0)
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXEQ_ADAPT_DONE,
      Q => rxeq_adapt_done_reg1,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pipe_rxstatus(0),
      Q => rxstatus_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(1),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => \rxvalid_cnt_reg__0\(0),
      O => \p_0_in__0__0\(0)
    );
\rxvalid_cnt[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000E6660000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(0),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(1)
    );
\rxvalid_cnt[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000EA6A0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(2),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(2)
    );
\rxvalid_cnt[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D444444400000000"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => \rxvalid_cnt_reg__0\(3),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(0),
      I4 => \rxvalid_cnt_reg__0\(1),
      I5 => rxvalid_reg2,
      O => \p_0_in__0__0\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(0),
      Q => \rxvalid_cnt_reg__0\(0),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(1),
      Q => \rxvalid_cnt_reg__0\(1),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(2),
      Q => \rxvalid_cnt_reg__0\(2),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(3),
      Q => \rxvalid_cnt_reg__0\(3),
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxvalid_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => RST_RXUSRCLK_RESET
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXCOMPLIANCE(0),
      Q => txcompliance_reg1,
      R => RST_CPLLRESET
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => RST_CPLLRESET
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXELECIDLE(0),
      Q => txelecidle_reg1,
      R => RST_CPLLRESET
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F800F800F800"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      I2 => pipe_txphaligndone(0),
      I3 => pipe_txphaligndone(1),
      I4 => p_1_in8_in_0,
      I5 => p_0_in7_in_1,
      O => txphaligndone_reg1_reg
    );
txphinitdone_reg1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1110111000005550"
    )
        port map (
      I0 => txelecidle_reg2_reg_0,
      I1 => txphinitdone_reg1_i_3_n_0,
      I2 => txelecidle_reg2_reg_1,
      I3 => pipe_txphinitdone(0),
      I4 => txphinitdone_reg1_i_5_n_0,
      I5 => user_active_lane(0),
      O => txphinitdone_reg1_reg
    );
txphinitdone_reg1_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF557F"
    )
        port map (
      I0 => pipe_txphinitdone(2),
      I1 => txcompliance_reg2,
      I2 => txelecidle_reg2,
      I3 => pipe_txphinitdone(1),
      I4 => txcompliance_reg2_reg_0,
      O => txphinitdone_reg1_i_3_n_0
    );
txphinitdone_reg1_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF15"
    )
        port map (
      I0 => pipe_txphinitdone(1),
      I1 => txelecidle_reg2,
      I2 => txcompliance_reg2,
      I3 => txcompliance_reg2_reg_0,
      O => txphinitdone_reg1_i_5_n_0
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_59 is
  port (
    gt_rxvalid_q_reg : out STD_LOGIC;
    D : out STD_LOGIC;
    p_0_in7_in : out STD_LOGIC;
    p_1_in8_in : out STD_LOGIC;
    USER_OOBCLK : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_159_out : out STD_LOGIC;
    \cplllock_reg1_reg[5]\ : out STD_LOGIC;
    resetovrd_done_reg1_reg : out STD_LOGIC;
    RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_active_lane : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    p_2_in : in STD_LOGIC;
    rst_idle_reg2_reg_0 : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    CLK_PCLK_SEL : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXRESETDONE : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC;
    RST_RXUSRCLK_RESET : in STD_LOGIC;
    pipe_rxstatus : in STD_LOGIC_VECTOR ( 0 to 0 );
    out1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    RST_RATE_IDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RATE_RXSYNC : in STD_LOGIC;
    USER_RATE_DONE : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    USER_RESETOVRD_START : in STD_LOGIC;
    RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_59 : entity is "PCIeGen1x8If64_pipe_user";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_59;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_59 is
  signal \converge_cnt[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_4__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_5__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_6__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_7__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_8__4_n_0\ : STD_LOGIC;
  signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[0]_i_3__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_1__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_gen3_i_1__4_n_0\ : STD_LOGIC;
  signal converge_gen3_reg_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gt_rxvalid_q_i_6__4_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_69_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_70_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_79_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1__4_n_0\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  signal pclk_sel_reg2 : STD_LOGIC;
  signal rate_done_reg1 : STD_LOGIC;
  signal rate_done_reg2 : STD_LOGIC;
  signal rate_gen3_reg1 : STD_LOGIC;
  signal rate_gen3_reg2 : STD_LOGIC;
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rate_rxsync_reg1 : STD_LOGIC;
  signal rate_rxsync_reg2 : STD_LOGIC;
  signal resetovrd_start_reg1 : STD_LOGIC;
  signal resetovrd_start_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal \rxcdrlock_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxstatus_reg1 : STD_LOGIC;
  signal rxstatus_reg2 : STD_LOGIC;
  signal \rxvalid_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  signal rxvalid_reg2 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal txcompliance_reg1 : STD_LOGIC;
  signal txcompliance_reg2 : STD_LOGIC;
  signal txelecidle_reg1 : STD_LOGIC;
  signal txelecidle_reg2 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal \NLW_converge_cnt_reg[21]_i_2__4_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__4_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__4_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_converge_cnt_reg[21]_i_2__4_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[13]_i_2__4_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[13]_i_2__4_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[17]_i_2__4_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[17]_i_2__4_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[1]_i_2__4_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[1]_i_2__4_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[21]_i_2__4_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[21]_i_2__4_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[5]_i_2__4_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[5]_i_2__4_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[9]_i_2__4_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[9]_i_2__4_CARRY4\ : label is "LO:O";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_5__4\ : label is "soft_lutpair168";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1__4\ : label is "soft_lutpair167";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1__4\ : label is "soft_lutpair167";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute ASYNC_REG of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_done_reg1_i_1__4\ : label is "soft_lutpair168";
  attribute ASYNC_REG of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
begin
  p_0_in7_in <= txcompliance_reg2;
  p_1_in8_in <= txelecidle_reg2;
\converge_cnt[0]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => RST_CPLLRESET,
      I3 => rate_gen3_reg2,
      O => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt[0]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5D555D"
    )
        port map (
      I0 => converge_cnt_reg(21),
      I1 => \converge_cnt[0]_i_4__4_n_0\,
      I2 => converge_cnt_reg(20),
      I3 => \converge_cnt[0]_i_5__4_n_0\,
      I4 => \converge_cnt[0]_i_6__4_n_0\,
      O => sel
    );
\converge_cnt[0]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => converge_cnt_reg(13),
      I3 => converge_cnt_reg(16),
      I4 => converge_cnt_reg(15),
      I5 => \converge_cnt[0]_i_8__4_n_0\,
      O => \converge_cnt[0]_i_4__4_n_0\
    );
\converge_cnt[0]_i_5__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \converge_cnt[0]_i_8__4_n_0\,
      I1 => converge_cnt_reg(16),
      I2 => converge_cnt_reg(15),
      I3 => converge_cnt_reg(13),
      I4 => converge_cnt_reg(11),
      O => \converge_cnt[0]_i_5__4_n_0\
    );
\converge_cnt[0]_i_6__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(3),
      I1 => converge_cnt_reg(6),
      I2 => \gtx_channel.gtxe2_channel_i_i_70_n_0\,
      I3 => converge_cnt_reg(10),
      I4 => converge_cnt_reg(8),
      I5 => converge_cnt_reg(9),
      O => \converge_cnt[0]_i_6__4_n_0\
    );
\converge_cnt[0]_i_7__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => converge_cnt_reg(0),
      O => \converge_cnt[0]_i_7__4_n_0\
    );
\converge_cnt[0]_i_8__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => converge_cnt_reg(17),
      I1 => converge_cnt_reg(18),
      I2 => converge_cnt_reg(19),
      O => \converge_cnt[0]_i_8__4_n_0\
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__4_n_0\,
      Q => converge_cnt_reg(0),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[10]_i_1__4_n_0\,
      Q => converge_cnt_reg(10),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[11]_i_1__4_n_0\,
      Q => converge_cnt_reg(11),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__4_n_0\,
      Q => converge_cnt_reg(12),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[13]_i_1__4_n_0\,
      Q => converge_cnt_reg(13),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[13]_i_2__4_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_2__4_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_2__4_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__4_n_0\,
      CO(1) => \converge_cnt_reg[14]_i_2__4_n_0\,
      CO(0) => \converge_cnt_reg[13]_i_2__4_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[15]_i_1__4_n_0\,
      O(2) => \converge_cnt_reg[14]_i_1__4_n_0\,
      O(1) => \converge_cnt_reg[13]_i_1__4_n_0\,
      O(0) => \converge_cnt_reg[12]_i_1__4_n_0\,
      S(3 downto 0) => converge_cnt_reg(15 downto 12)
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[14]_i_1__4_n_0\,
      Q => converge_cnt_reg(14),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[15]_i_1__4_n_0\,
      Q => converge_cnt_reg(15),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__4_n_0\,
      Q => converge_cnt_reg(16),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[17]_i_1__4_n_0\,
      Q => converge_cnt_reg(17),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[17]_i_2__4_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_2__4_n_0\,
      CO(3) => \converge_cnt_reg[20]_i_2__4_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__4_n_0\,
      CO(1) => \converge_cnt_reg[18]_i_2__4_n_0\,
      CO(0) => \converge_cnt_reg[17]_i_2__4_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[19]_i_1__4_n_0\,
      O(2) => \converge_cnt_reg[18]_i_1__4_n_0\,
      O(1) => \converge_cnt_reg[17]_i_1__4_n_0\,
      O(0) => \converge_cnt_reg[16]_i_1__4_n_0\,
      S(3 downto 0) => converge_cnt_reg(19 downto 16)
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[18]_i_1__4_n_0\,
      Q => converge_cnt_reg(18),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[19]_i_1__4_n_0\,
      Q => converge_cnt_reg(19),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[1]_i_1__4_n_0\,
      Q => converge_cnt_reg(1),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[1]_i_2__4_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[4]_i_2__4_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__4_n_0\,
      CO(1) => \converge_cnt_reg[2]_i_2__4_n_0\,
      CO(0) => \converge_cnt_reg[1]_i_2__4_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '1',
      O(3) => \converge_cnt_reg[3]_i_1__4_n_0\,
      O(2) => \converge_cnt_reg[2]_i_1__4_n_0\,
      O(1) => \converge_cnt_reg[1]_i_1__4_n_0\,
      O(0) => \converge_cnt_reg[0]_i_3__4_n_0\,
      S(3 downto 1) => converge_cnt_reg(3 downto 1),
      S(0) => \converge_cnt[0]_i_7__4_n_0\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1__4_n_0\,
      Q => converge_cnt_reg(20),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[21]_i_1__4_n_0\,
      Q => converge_cnt_reg(21),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[21]_i_2__4_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[20]_i_2__4_n_0\,
      CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__4_CARRY4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__4_CARRY4_DI_UNCONNECTED\(3 downto 1),
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__4_CARRY4_O_UNCONNECTED\(3 downto 2),
      O(1) => \converge_cnt_reg[21]_i_1__4_n_0\,
      O(0) => \converge_cnt_reg[20]_i_1__4_n_0\,
      S(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__4_CARRY4_S_UNCONNECTED\(3 downto 2),
      S(1 downto 0) => converge_cnt_reg(21 downto 20)
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[2]_i_1__4_n_0\,
      Q => converge_cnt_reg(2),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[3]_i_1__4_n_0\,
      Q => converge_cnt_reg(3),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__4_n_0\,
      Q => converge_cnt_reg(4),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[5]_i_1__4_n_0\,
      Q => converge_cnt_reg(5),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[5]_i_2__4_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_2__4_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_2__4_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__4_n_0\,
      CO(1) => \converge_cnt_reg[6]_i_2__4_n_0\,
      CO(0) => \converge_cnt_reg[5]_i_2__4_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[7]_i_1__4_n_0\,
      O(2) => \converge_cnt_reg[6]_i_1__4_n_0\,
      O(1) => \converge_cnt_reg[5]_i_1__4_n_0\,
      O(0) => \converge_cnt_reg[4]_i_1__4_n_0\,
      S(3 downto 0) => converge_cnt_reg(7 downto 4)
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[6]_i_1__4_n_0\,
      Q => converge_cnt_reg(6),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[7]_i_1__4_n_0\,
      Q => converge_cnt_reg(7),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__4_n_0\,
      Q => converge_cnt_reg(8),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[9]_i_1__4_n_0\,
      Q => converge_cnt_reg(9),
      R => \converge_cnt[0]_i_1__4_n_0\
    );
\converge_cnt_reg[9]_i_2__4_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_2__4_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_2__4_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__4_n_0\,
      CO(1) => \converge_cnt_reg[10]_i_2__4_n_0\,
      CO(0) => \converge_cnt_reg[9]_i_2__4_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[11]_i_1__4_n_0\,
      O(2) => \converge_cnt_reg[10]_i_1__4_n_0\,
      O(1) => \converge_cnt_reg[9]_i_1__4_n_0\,
      O(0) => \converge_cnt_reg[8]_i_1__4_n_0\,
      S(3 downto 0) => converge_cnt_reg(11 downto 8)
    );
\converge_gen3_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0C08"
    )
        port map (
      I0 => rxeq_adapt_done_reg2,
      I1 => rate_gen3_reg2,
      I2 => RST_CPLLRESET,
      I3 => converge_gen3_reg_n_0,
      O => \converge_gen3_i_1__4_n_0\
    );
converge_gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \converge_gen3_i_1__4_n_0\,
      Q => converge_gen3_reg_n_0,
      R => '0'
    );
\gt_rx_phy_status_q_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => RST_PHYSTATUS(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => gt_rx_phy_status_wire_filter(0)
    );
\gt_rxvalid_q_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4500000000000000"
    )
        port map (
      I0 => \gt_rxvalid_q_i_6__4_n_0\,
      I1 => gt_rxvalid_q_reg_0,
      I2 => gt_rx_elec_idle_wire_filter(0),
      I3 => rst_idle_reg2,
      I4 => rate_idle_reg2,
      I5 => \resetovrd_disble.reset_reg[4]_0\,
      O => gt_rxvalid_q_reg
    );
\gt_rxvalid_q_i_6__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(1),
      O => \gt_rxvalid_q_i_6__4_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_59\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => converge_gen3_reg_n_0,
      I1 => \gtx_channel.gtxe2_channel_i_i_69_n_0\,
      I2 => converge_cnt_reg(8),
      I3 => converge_cnt_reg(9),
      I4 => \gtx_channel.gtxe2_channel_i_i_70_n_0\,
      I5 => \converge_cnt[0]_i_5__4_n_0\,
      O => p_159_out
    );
\gtx_channel.gtxe2_channel_i_i_5__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => \cplllock_reg1_reg[5]\
    );
\gtx_channel.gtxe2_channel_i_i_69\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => \gtx_channel.gtxe2_channel_i_i_79_n_0\,
      I3 => converge_cnt_reg(2),
      I4 => converge_cnt_reg(6),
      O => \gtx_channel.gtxe2_channel_i_i_69_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_70\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => converge_cnt_reg(4),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(7),
      O => \gtx_channel.gtxe2_channel_i_i_70_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_79\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => converge_cnt_reg(20),
      I1 => converge_cnt_reg(3),
      I2 => converge_cnt_reg(0),
      I3 => converge_cnt_reg(1),
      I4 => converge_cnt_reg(10),
      I5 => converge_cnt_reg(21),
      O => \gtx_channel.gtxe2_channel_i_i_79_n_0\
    );
\oobclk_div.oobclk_cnt[0]_i_1__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1__4_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \oobclk_div.oobclk_i_1__4_n_0\,
      Q => USER_OOBCLK,
      R => RST_CPLLRESET
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => CLK_PCLK_SEL(0),
      Q => pclk_sel_reg1,
      R => RST_CPLLRESET
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => RST_CPLLRESET
    );
phy_rdy_n_int_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => rst_idle_reg2,
      I1 => p_2_in,
      I2 => rst_idle_reg2_reg_0,
      O => D
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_DONE,
      Q => rate_done_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => rate_gen3_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => RST_RATE_IDLE(0),
      Q => rate_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_RXSYNC,
      Q => rate_rxsync_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => RST_RXUSRCLK_RESET
    );
\resetdone_reg1[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txresetdone_reg2,
      I1 => rxresetdone_reg2,
      O => RST_RESETDONE(0)
    );
\resetovrd_disble.fsm_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(0),
      R => '0'
    );
\resetovrd_disble.fsm_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(0),
      R => '0'
    );
\resetovrd_disble.reset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(2),
      R => '0'
    );
\resetovrd_disble.reset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(3),
      R => '0'
    );
\resetovrd_disble.reset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(4),
      R => '0'
    );
\resetovrd_disble.reset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(5),
      R => '0'
    );
\resetovrd_disble.reset_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(6),
      R => '0'
    );
\resetovrd_done_reg1_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => resetovrd_done_reg1_reg
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RESETOVRD_START,
      Q => resetovrd_start_reg1,
      R => RST_CPLLRESET
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => RST_CPLLRESET
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => out1(0),
      Q => rst_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxcdrlock_cnt[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(2),
      I2 => \rxcdrlock_cnt_reg__0\(0),
      I3 => \rxcdrlock_cnt_reg__0\(1),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(0)
    );
\rxcdrlock_cnt[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(0),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(2),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(1)
    );
\rxcdrlock_cnt[2]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8CCCC000"
    )
        port map (
      I0 => \rxcdrlock_cnt_reg__0\(3),
      I1 => rxcdrlock_reg2,
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(2)
    );
\rxcdrlock_cnt[3]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \rxcdrlock_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \rxcdrlock_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \rxcdrlock_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \rxcdrlock_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\rxcdrlock_reg1[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \resetovrd_disble.reset_reg[4]_1\,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => RST_RXCDRLOCK(0)
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXEQ_ADAPT_DONE,
      Q => rxeq_adapt_done_reg1,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pipe_rxstatus(0),
      Q => rxstatus_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(1),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => \rxvalid_cnt_reg__0\(0),
      O => \p_0_in__0__0\(0)
    );
\rxvalid_cnt[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000E6660000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(0),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(1)
    );
\rxvalid_cnt[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000EA6A0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(2),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(2)
    );
\rxvalid_cnt[3]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D444444400000000"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => \rxvalid_cnt_reg__0\(3),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(0),
      I4 => \rxvalid_cnt_reg__0\(1),
      I5 => rxvalid_reg2,
      O => \p_0_in__0__0\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(0),
      Q => \rxvalid_cnt_reg__0\(0),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(1),
      Q => \rxvalid_cnt_reg__0\(1),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(2),
      Q => \rxvalid_cnt_reg__0\(2),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(3),
      Q => \rxvalid_cnt_reg__0\(3),
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxvalid_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => RST_RXUSRCLK_RESET
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXCOMPLIANCE(0),
      Q => txcompliance_reg1,
      R => RST_CPLLRESET
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => RST_CPLLRESET
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXELECIDLE(0),
      Q => txelecidle_reg1,
      R => RST_CPLLRESET
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => RST_CPLLRESET
    );
txphinitdone_reg1_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      O => user_active_lane(0)
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_65 is
  port (
    txsyncallin : out STD_LOGIC;
    gt_rxvalid_q_reg : out STD_LOGIC;
    p_2_in : out STD_LOGIC;
    GT_RX_CONVERGE0 : out STD_LOGIC;
    \cplllock_reg1_reg[2]\ : out STD_LOGIC;
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    \cplllock_reg1_reg[7]\ : out STD_LOGIC;
    p_0_in7_in : out STD_LOGIC;
    p_1_in8_in : out STD_LOGIC;
    USER_OOBCLK : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[6]\ : out STD_LOGIC;
    resetovrd_done_reg1_reg : out STD_LOGIC;
    RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    txelecidle_reg2_reg_0 : in STD_LOGIC;
    pipe_txphaligndone : in STD_LOGIC_VECTOR ( 0 to 0 );
    txelecidle_reg2_reg_1 : in STD_LOGIC;
    txelecidle_reg2_reg_2 : in STD_LOGIC;
    txcompliance_reg2_reg_0 : in STD_LOGIC;
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    p_216_out : in STD_LOGIC;
    p_159_out : in STD_LOGIC;
    user_rx_converge : in STD_LOGIC_VECTOR ( 4 downto 0 );
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    CLK_PCLK_SEL : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXRESETDONE : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC;
    RST_RXUSRCLK_RESET : in STD_LOGIC;
    pipe_rxstatus : in STD_LOGIC_VECTOR ( 0 to 0 );
    out1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RATE_IDLE : in STD_LOGIC;
    USER_RATE_RXSYNC : in STD_LOGIC;
    USER_RATE_DONE : in STD_LOGIC;
    USER_RATE_GEN3 : in STD_LOGIC;
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    USER_RESETOVRD_START : in STD_LOGIC;
    RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_65 : entity is "PCIeGen1x8If64_pipe_user";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_65;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_65 is
  signal \converge_cnt[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_4__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_5__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_6__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_7__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_8__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_9__3_n_0\ : STD_LOGIC;
  signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[0]_i_3__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_1__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_gen3_i_1__5_n_0\ : STD_LOGIC;
  signal converge_gen3_reg_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gt_rxvalid_q_i_6__5_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_57__2_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_71_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_80_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1__5_n_0\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal p_106_out : STD_LOGIC;
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  signal pclk_sel_reg2 : STD_LOGIC;
  signal rate_done_reg1 : STD_LOGIC;
  signal rate_done_reg2 : STD_LOGIC;
  signal rate_gen3_reg1 : STD_LOGIC;
  signal rate_gen3_reg2 : STD_LOGIC;
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rate_rxsync_reg1 : STD_LOGIC;
  signal rate_rxsync_reg2 : STD_LOGIC;
  signal resetovrd_start_reg1 : STD_LOGIC;
  signal resetovrd_start_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal \rxcdrlock_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxstatus_reg1 : STD_LOGIC;
  signal rxstatus_reg2 : STD_LOGIC;
  signal \rxvalid_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  signal rxvalid_reg2 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal txcompliance_reg1 : STD_LOGIC;
  signal txcompliance_reg2 : STD_LOGIC;
  signal txelecidle_reg1 : STD_LOGIC;
  signal txelecidle_reg2 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal user_active_lane : STD_LOGIC_VECTOR ( 6 to 6 );
  signal \NLW_converge_cnt_reg[21]_i_2__5_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__5_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__5_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_converge_cnt_reg[21]_i_2__5_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[13]_i_2__5_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[13]_i_2__5_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[17]_i_2__5_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[17]_i_2__5_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[1]_i_2__5_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[1]_i_2__5_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[21]_i_2__5_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[21]_i_2__5_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[5]_i_2__5_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[5]_i_2__5_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[9]_i_2__5_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[9]_i_2__5_CARRY4\ : label is "LO:O";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_5__5\ : label is "soft_lutpair192";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_8__3\ : label is "soft_lutpair189";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_8__4\ : label is "soft_lutpair189";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_8__5\ : label is "soft_lutpair190";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_8__6\ : label is "soft_lutpair190";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1__5\ : label is "soft_lutpair191";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1__5\ : label is "soft_lutpair191";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute ASYNC_REG of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_done_reg1_i_1__5\ : label is "soft_lutpair192";
  attribute ASYNC_REG of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
begin
  p_0_in7_in <= txcompliance_reg2;
  p_1_in8_in <= txelecidle_reg2;
  p_2_in <= rst_idle_reg2;
\converge_cnt[0]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => RST_CPLLRESET,
      I3 => rate_gen3_reg2,
      O => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt[0]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5D555D"
    )
        port map (
      I0 => converge_cnt_reg(21),
      I1 => \converge_cnt[0]_i_4__5_n_0\,
      I2 => converge_cnt_reg(20),
      I3 => \converge_cnt[0]_i_5__5_n_0\,
      I4 => \converge_cnt[0]_i_6__5_n_0\,
      O => sel
    );
\converge_cnt[0]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => converge_cnt_reg(13),
      I3 => converge_cnt_reg(16),
      I4 => converge_cnt_reg(15),
      I5 => \converge_cnt[0]_i_8__5_n_0\,
      O => \converge_cnt[0]_i_4__5_n_0\
    );
\converge_cnt[0]_i_5__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \converge_cnt[0]_i_8__5_n_0\,
      I1 => converge_cnt_reg(16),
      I2 => converge_cnt_reg(15),
      I3 => converge_cnt_reg(13),
      I4 => converge_cnt_reg(11),
      O => \converge_cnt[0]_i_5__5_n_0\
    );
\converge_cnt[0]_i_6__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(3),
      I1 => converge_cnt_reg(6),
      I2 => \converge_cnt[0]_i_9__3_n_0\,
      I3 => converge_cnt_reg(10),
      I4 => converge_cnt_reg(8),
      I5 => converge_cnt_reg(9),
      O => \converge_cnt[0]_i_6__5_n_0\
    );
\converge_cnt[0]_i_7__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => converge_cnt_reg(0),
      O => \converge_cnt[0]_i_7__5_n_0\
    );
\converge_cnt[0]_i_8__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => converge_cnt_reg(17),
      I1 => converge_cnt_reg(18),
      I2 => converge_cnt_reg(19),
      O => \converge_cnt[0]_i_8__5_n_0\
    );
\converge_cnt[0]_i_9__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => converge_cnt_reg(4),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(7),
      O => \converge_cnt[0]_i_9__3_n_0\
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__5_n_0\,
      Q => converge_cnt_reg(0),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[10]_i_1__5_n_0\,
      Q => converge_cnt_reg(10),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[11]_i_1__5_n_0\,
      Q => converge_cnt_reg(11),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__5_n_0\,
      Q => converge_cnt_reg(12),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[13]_i_1__5_n_0\,
      Q => converge_cnt_reg(13),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[13]_i_2__5_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_2__5_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_2__5_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__5_n_0\,
      CO(1) => \converge_cnt_reg[14]_i_2__5_n_0\,
      CO(0) => \converge_cnt_reg[13]_i_2__5_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[15]_i_1__5_n_0\,
      O(2) => \converge_cnt_reg[14]_i_1__5_n_0\,
      O(1) => \converge_cnt_reg[13]_i_1__5_n_0\,
      O(0) => \converge_cnt_reg[12]_i_1__5_n_0\,
      S(3 downto 0) => converge_cnt_reg(15 downto 12)
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[14]_i_1__5_n_0\,
      Q => converge_cnt_reg(14),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[15]_i_1__5_n_0\,
      Q => converge_cnt_reg(15),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__5_n_0\,
      Q => converge_cnt_reg(16),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[17]_i_1__5_n_0\,
      Q => converge_cnt_reg(17),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[17]_i_2__5_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_2__5_n_0\,
      CO(3) => \converge_cnt_reg[20]_i_2__5_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__5_n_0\,
      CO(1) => \converge_cnt_reg[18]_i_2__5_n_0\,
      CO(0) => \converge_cnt_reg[17]_i_2__5_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[19]_i_1__5_n_0\,
      O(2) => \converge_cnt_reg[18]_i_1__5_n_0\,
      O(1) => \converge_cnt_reg[17]_i_1__5_n_0\,
      O(0) => \converge_cnt_reg[16]_i_1__5_n_0\,
      S(3 downto 0) => converge_cnt_reg(19 downto 16)
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[18]_i_1__5_n_0\,
      Q => converge_cnt_reg(18),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[19]_i_1__5_n_0\,
      Q => converge_cnt_reg(19),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[1]_i_1__5_n_0\,
      Q => converge_cnt_reg(1),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[1]_i_2__5_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[4]_i_2__5_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__5_n_0\,
      CO(1) => \converge_cnt_reg[2]_i_2__5_n_0\,
      CO(0) => \converge_cnt_reg[1]_i_2__5_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '1',
      O(3) => \converge_cnt_reg[3]_i_1__5_n_0\,
      O(2) => \converge_cnt_reg[2]_i_1__5_n_0\,
      O(1) => \converge_cnt_reg[1]_i_1__5_n_0\,
      O(0) => \converge_cnt_reg[0]_i_3__5_n_0\,
      S(3 downto 1) => converge_cnt_reg(3 downto 1),
      S(0) => \converge_cnt[0]_i_7__5_n_0\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1__5_n_0\,
      Q => converge_cnt_reg(20),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[21]_i_1__5_n_0\,
      Q => converge_cnt_reg(21),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[21]_i_2__5_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[20]_i_2__5_n_0\,
      CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__5_CARRY4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__5_CARRY4_DI_UNCONNECTED\(3 downto 1),
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__5_CARRY4_O_UNCONNECTED\(3 downto 2),
      O(1) => \converge_cnt_reg[21]_i_1__5_n_0\,
      O(0) => \converge_cnt_reg[20]_i_1__5_n_0\,
      S(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__5_CARRY4_S_UNCONNECTED\(3 downto 2),
      S(1 downto 0) => converge_cnt_reg(21 downto 20)
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[2]_i_1__5_n_0\,
      Q => converge_cnt_reg(2),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[3]_i_1__5_n_0\,
      Q => converge_cnt_reg(3),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__5_n_0\,
      Q => converge_cnt_reg(4),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[5]_i_1__5_n_0\,
      Q => converge_cnt_reg(5),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[5]_i_2__5_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_2__5_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_2__5_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__5_n_0\,
      CO(1) => \converge_cnt_reg[6]_i_2__5_n_0\,
      CO(0) => \converge_cnt_reg[5]_i_2__5_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[7]_i_1__5_n_0\,
      O(2) => \converge_cnt_reg[6]_i_1__5_n_0\,
      O(1) => \converge_cnt_reg[5]_i_1__5_n_0\,
      O(0) => \converge_cnt_reg[4]_i_1__5_n_0\,
      S(3 downto 0) => converge_cnt_reg(7 downto 4)
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[6]_i_1__5_n_0\,
      Q => converge_cnt_reg(6),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[7]_i_1__5_n_0\,
      Q => converge_cnt_reg(7),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__5_n_0\,
      Q => converge_cnt_reg(8),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[9]_i_1__5_n_0\,
      Q => converge_cnt_reg(9),
      R => \converge_cnt[0]_i_1__5_n_0\
    );
\converge_cnt_reg[9]_i_2__5_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_2__5_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_2__5_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__5_n_0\,
      CO(1) => \converge_cnt_reg[10]_i_2__5_n_0\,
      CO(0) => \converge_cnt_reg[9]_i_2__5_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[11]_i_1__5_n_0\,
      O(2) => \converge_cnt_reg[10]_i_1__5_n_0\,
      O(1) => \converge_cnt_reg[9]_i_1__5_n_0\,
      O(0) => \converge_cnt_reg[8]_i_1__5_n_0\,
      S(3 downto 0) => converge_cnt_reg(11 downto 8)
    );
\converge_gen3_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0C08"
    )
        port map (
      I0 => rxeq_adapt_done_reg2,
      I1 => rate_gen3_reg2,
      I2 => RST_CPLLRESET,
      I3 => converge_gen3_reg_n_0,
      O => \converge_gen3_i_1__5_n_0\
    );
converge_gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \converge_gen3_i_1__5_n_0\,
      Q => converge_gen3_reg_n_0,
      R => '0'
    );
\gt_rx_phy_status_q_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => RST_PHYSTATUS(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => gt_rx_phy_status_wire_filter(0)
    );
\gt_rxvalid_q_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4500000000000000"
    )
        port map (
      I0 => \gt_rxvalid_q_i_6__5_n_0\,
      I1 => gt_rxvalid_q_reg_0,
      I2 => gt_rx_elec_idle_wire_filter(0),
      I3 => rst_idle_reg2,
      I4 => rate_idle_reg2,
      I5 => \resetovrd_disble.reset_reg[4]_0\,
      O => gt_rxvalid_q_reg
    );
\gt_rxvalid_q_i_6__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(1),
      O => \gt_rxvalid_q_i_6__5_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_57__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => p_106_out,
      I1 => user_rx_converge(4),
      I2 => user_rx_converge(1),
      I3 => user_rx_converge(0),
      I4 => user_rx_converge(3),
      I5 => user_rx_converge(2),
      O => \gtx_channel.gtxe2_channel_i_i_57__2_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_5__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => \cplllock_reg1_reg[6]\
    );
\gtx_channel.gtxe2_channel_i_i_61\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => converge_gen3_reg_n_0,
      I1 => \gtx_channel.gtxe2_channel_i_i_71_n_0\,
      I2 => converge_cnt_reg(8),
      I3 => converge_cnt_reg(9),
      I4 => \converge_cnt[0]_i_9__3_n_0\,
      I5 => \converge_cnt[0]_i_5__5_n_0\,
      O => p_106_out
    );
\gtx_channel.gtxe2_channel_i_i_71\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => \gtx_channel.gtxe2_channel_i_i_80_n_0\,
      I3 => converge_cnt_reg(2),
      I4 => converge_cnt_reg(6),
      O => \gtx_channel.gtxe2_channel_i_i_71_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_80\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => converge_cnt_reg(20),
      I1 => converge_cnt_reg(3),
      I2 => converge_cnt_reg(0),
      I3 => converge_cnt_reg(1),
      I4 => converge_cnt_reg(10),
      I5 => converge_cnt_reg(21),
      O => \gtx_channel.gtxe2_channel_i_i_80_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_8__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gtx_channel.gtxe2_channel_i_i_57__2_n_0\,
      I1 => p_216_out,
      I2 => p_159_out,
      O => GT_RX_CONVERGE0
    );
\gtx_channel.gtxe2_channel_i_i_8__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gtx_channel.gtxe2_channel_i_i_57__2_n_0\,
      I1 => p_216_out,
      I2 => p_159_out,
      O => \cplllock_reg1_reg[2]\
    );
\gtx_channel.gtxe2_channel_i_i_8__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gtx_channel.gtxe2_channel_i_i_57__2_n_0\,
      I1 => p_216_out,
      I2 => p_159_out,
      O => \cplllock_reg1_reg[3]\
    );
\gtx_channel.gtxe2_channel_i_i_8__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \gtx_channel.gtxe2_channel_i_i_57__2_n_0\,
      I1 => p_216_out,
      I2 => p_159_out,
      O => \cplllock_reg1_reg[7]\
    );
\oobclk_div.oobclk_cnt[0]_i_1__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1__5_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \oobclk_div.oobclk_i_1__5_n_0\,
      Q => USER_OOBCLK,
      R => RST_CPLLRESET
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => CLK_PCLK_SEL(0),
      Q => pclk_sel_reg1,
      R => RST_CPLLRESET
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => RST_CPLLRESET
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_DONE,
      Q => rate_done_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_GEN3,
      Q => rate_gen3_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_IDLE,
      Q => rate_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_RXSYNC,
      Q => rate_rxsync_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => RST_RXUSRCLK_RESET
    );
\resetdone_reg1[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txresetdone_reg2,
      I1 => rxresetdone_reg2,
      O => RST_RESETDONE(0)
    );
\resetovrd_disble.fsm_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(0),
      R => '0'
    );
\resetovrd_disble.fsm_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(0),
      R => '0'
    );
\resetovrd_disble.reset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(2),
      R => '0'
    );
\resetovrd_disble.reset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(3),
      R => '0'
    );
\resetovrd_disble.reset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(4),
      R => '0'
    );
\resetovrd_disble.reset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(5),
      R => '0'
    );
\resetovrd_disble.reset_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(6),
      R => '0'
    );
\resetovrd_done_reg1_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => resetovrd_done_reg1_reg
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RESETOVRD_START,
      Q => resetovrd_start_reg1,
      R => RST_CPLLRESET
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => RST_CPLLRESET
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => out1(0),
      Q => rst_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxcdrlock_cnt[0]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(2),
      I2 => \rxcdrlock_cnt_reg__0\(0),
      I3 => \rxcdrlock_cnt_reg__0\(1),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(0)
    );
\rxcdrlock_cnt[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(0),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(2),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(1)
    );
\rxcdrlock_cnt[2]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8CCCC000"
    )
        port map (
      I0 => \rxcdrlock_cnt_reg__0\(3),
      I1 => rxcdrlock_reg2,
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(2)
    );
\rxcdrlock_cnt[3]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \rxcdrlock_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \rxcdrlock_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \rxcdrlock_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \rxcdrlock_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\rxcdrlock_reg1[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \resetovrd_disble.reset_reg[4]_1\,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => RST_RXCDRLOCK(0)
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXEQ_ADAPT_DONE,
      Q => rxeq_adapt_done_reg1,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pipe_rxstatus(0),
      Q => rxstatus_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(1),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => \rxvalid_cnt_reg__0\(0),
      O => \p_0_in__0__0\(0)
    );
\rxvalid_cnt[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000E6660000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(0),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(1)
    );
\rxvalid_cnt[2]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000EA6A0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(2),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(2)
    );
\rxvalid_cnt[3]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D444444400000000"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => \rxvalid_cnt_reg__0\(3),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(0),
      I4 => \rxvalid_cnt_reg__0\(1),
      I5 => rxvalid_reg2,
      O => \p_0_in__0__0\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(0),
      Q => \rxvalid_cnt_reg__0\(0),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(1),
      Q => \rxvalid_cnt_reg__0\(1),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(2),
      Q => \rxvalid_cnt_reg__0\(2),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(3),
      Q => \rxvalid_cnt_reg__0\(3),
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxvalid_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => RST_RXUSRCLK_RESET
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXCOMPLIANCE(0),
      Q => txcompliance_reg1,
      R => RST_CPLLRESET
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => RST_CPLLRESET
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXELECIDLE(0),
      Q => txelecidle_reg1,
      R => RST_CPLLRESET
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000031000000"
    )
        port map (
      I0 => user_active_lane(6),
      I1 => txelecidle_reg2_reg_0,
      I2 => pipe_txphaligndone(0),
      I3 => txelecidle_reg2_reg_1,
      I4 => txelecidle_reg2_reg_2,
      I5 => txcompliance_reg2_reg_0,
      O => txsyncallin
    );
txphaligndone_reg1_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      O => user_active_lane(6)
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_71 is
  port (
    txphinitdone_reg1_reg : out STD_LOGIC;
    p_1_in8_in : out STD_LOGIC;
    p_0_in7_in : out STD_LOGIC;
    txphaligndone_reg1_reg : out STD_LOGIC;
    gt_rxvalid_q_reg : out STD_LOGIC;
    phy_rdy_n_int_reg : out STD_LOGIC;
    USER_OOBCLK : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
    RST_RXCDRLOCK : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    user_rx_converge : out STD_LOGIC_VECTOR ( 0 to 0 );
    \cplllock_reg1_reg[7]\ : out STD_LOGIC;
    resetovrd_done_reg1_reg : out STD_LOGIC;
    RST_RESETDONE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : in STD_LOGIC_VECTOR ( 1 downto 0 );
    p_0_in7_in_0 : in STD_LOGIC;
    p_1_in8_in_1 : in STD_LOGIC;
    pipe_txphaligndone : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    gt_rx_elec_idle_wire_filter : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC;
    p_2_in : in STD_LOGIC;
    p_2_in_2 : in STD_LOGIC;
    p_2_in_3 : in STD_LOGIC;
    p_2_in_4 : in STD_LOGIC;
    p_2_in_5 : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    CLK_PCLK_SEL : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXRESETDONE : in STD_LOGIC;
    USER_TXRESETDONE : in STD_LOGIC;
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC;
    RST_RXUSRCLK_RESET : in STD_LOGIC;
    pipe_rxstatus : in STD_LOGIC_VECTOR ( 0 to 0 );
    out1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RATE_IDLE : in STD_LOGIC;
    USER_RATE_RXSYNC : in STD_LOGIC;
    USER_RATE_DONE : in STD_LOGIC;
    gen3_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    USER_RESETOVRD_START : in STD_LOGIC;
    RST_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_71 : entity is "PCIeGen1x8If64_pipe_user";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_71;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_71 is
  signal \converge_cnt[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_4__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_5__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_6__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_7__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_8__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_9__4_n_0\ : STD_LOGIC;
  signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[0]_i_3__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[10]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[13]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[14]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[17]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[18]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[1]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[2]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[5]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[6]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_1__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[9]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_gen3_i_1__6_n_0\ : STD_LOGIC;
  signal converge_gen3_reg_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gt_rxvalid_q_i_6__6_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_72_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_81_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1__6_n_0\ : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  signal pclk_sel_reg2 : STD_LOGIC;
  signal rate_done_reg1 : STD_LOGIC;
  signal rate_done_reg2 : STD_LOGIC;
  signal rate_gen3_reg1 : STD_LOGIC;
  signal rate_gen3_reg2 : STD_LOGIC;
  signal rate_idle_reg1 : STD_LOGIC;
  signal rate_idle_reg2 : STD_LOGIC;
  signal rate_rxsync_reg1 : STD_LOGIC;
  signal rate_rxsync_reg2 : STD_LOGIC;
  signal resetovrd_start_reg1 : STD_LOGIC;
  signal resetovrd_start_reg2 : STD_LOGIC;
  signal rst_idle_reg1 : STD_LOGIC;
  signal rst_idle_reg2 : STD_LOGIC;
  signal \rxcdrlock_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  signal rxcdrlock_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  signal rxresetdone_reg2 : STD_LOGIC;
  signal rxstatus_reg1 : STD_LOGIC;
  signal rxstatus_reg2 : STD_LOGIC;
  signal \rxvalid_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  signal rxvalid_reg2 : STD_LOGIC;
  signal sel : STD_LOGIC;
  signal txcompliance_reg1 : STD_LOGIC;
  signal txcompliance_reg2 : STD_LOGIC;
  signal txelecidle_reg1 : STD_LOGIC;
  signal txelecidle_reg2 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  signal txresetdone_reg2 : STD_LOGIC;
  signal \NLW_converge_cnt_reg[21]_i_2__6_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__6_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__6_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_converge_cnt_reg[21]_i_2__6_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[13]_i_2__6_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[13]_i_2__6_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[17]_i_2__6_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[17]_i_2__6_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[1]_i_2__6_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[1]_i_2__6_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[21]_i_2__6_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[21]_i_2__6_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[5]_i_2__6_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[5]_i_2__6_CARRY4\ : label is "LO:O";
  attribute XILINX_LEGACY_PRIM of \converge_cnt_reg[9]_i_2__6_CARRY4\ : label is "(MUXCY,XORCY)";
  attribute XILINX_TRANSFORM_PINMAP of \converge_cnt_reg[9]_i_2__6_CARRY4\ : label is "LO:O";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_5__6\ : label is "soft_lutpair214";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1__6\ : label is "soft_lutpair213";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1__6\ : label is "soft_lutpair213";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute ASYNC_REG of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute ASYNC_REG of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \resetovrd_done_reg1_i_1__6\ : label is "soft_lutpair214";
  attribute ASYNC_REG of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute ASYNC_REG of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute ASYNC_REG of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute ASYNC_REG of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute ASYNC_REG of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute ASYNC_REG of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
begin
  p_0_in7_in <= txcompliance_reg2;
  p_1_in8_in <= txelecidle_reg2;
\converge_cnt[0]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => RST_CPLLRESET,
      I3 => rate_gen3_reg2,
      O => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt[0]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5D5D555D"
    )
        port map (
      I0 => converge_cnt_reg(21),
      I1 => \converge_cnt[0]_i_4__6_n_0\,
      I2 => converge_cnt_reg(20),
      I3 => \converge_cnt[0]_i_5__6_n_0\,
      I4 => \converge_cnt[0]_i_6__6_n_0\,
      O => sel
    );
\converge_cnt[0]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"13FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => converge_cnt_reg(13),
      I3 => converge_cnt_reg(16),
      I4 => converge_cnt_reg(15),
      I5 => \converge_cnt[0]_i_8__6_n_0\,
      O => \converge_cnt[0]_i_4__6_n_0\
    );
\converge_cnt[0]_i_5__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \converge_cnt[0]_i_8__6_n_0\,
      I1 => converge_cnt_reg(16),
      I2 => converge_cnt_reg(15),
      I3 => converge_cnt_reg(13),
      I4 => converge_cnt_reg(11),
      O => \converge_cnt[0]_i_5__6_n_0\
    );
\converge_cnt[0]_i_6__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10FFFFFFFFFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(3),
      I1 => converge_cnt_reg(6),
      I2 => \converge_cnt[0]_i_9__4_n_0\,
      I3 => converge_cnt_reg(10),
      I4 => converge_cnt_reg(8),
      I5 => converge_cnt_reg(9),
      O => \converge_cnt[0]_i_6__6_n_0\
    );
\converge_cnt[0]_i_7__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => converge_cnt_reg(0),
      O => \converge_cnt[0]_i_7__6_n_0\
    );
\converge_cnt[0]_i_8__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => converge_cnt_reg(17),
      I1 => converge_cnt_reg(18),
      I2 => converge_cnt_reg(19),
      O => \converge_cnt[0]_i_8__6_n_0\
    );
\converge_cnt[0]_i_9__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => converge_cnt_reg(4),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(7),
      O => \converge_cnt[0]_i_9__4_n_0\
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__6_n_0\,
      Q => converge_cnt_reg(0),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[10]_i_1__6_n_0\,
      Q => converge_cnt_reg(10),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[11]_i_1__6_n_0\,
      Q => converge_cnt_reg(11),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__6_n_0\,
      Q => converge_cnt_reg(12),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[13]_i_1__6_n_0\,
      Q => converge_cnt_reg(13),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[13]_i_2__6_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_2__6_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_2__6_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__6_n_0\,
      CO(1) => \converge_cnt_reg[14]_i_2__6_n_0\,
      CO(0) => \converge_cnt_reg[13]_i_2__6_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[15]_i_1__6_n_0\,
      O(2) => \converge_cnt_reg[14]_i_1__6_n_0\,
      O(1) => \converge_cnt_reg[13]_i_1__6_n_0\,
      O(0) => \converge_cnt_reg[12]_i_1__6_n_0\,
      S(3 downto 0) => converge_cnt_reg(15 downto 12)
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[14]_i_1__6_n_0\,
      Q => converge_cnt_reg(14),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[15]_i_1__6_n_0\,
      Q => converge_cnt_reg(15),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__6_n_0\,
      Q => converge_cnt_reg(16),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[17]_i_1__6_n_0\,
      Q => converge_cnt_reg(17),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[17]_i_2__6_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_2__6_n_0\,
      CO(3) => \converge_cnt_reg[20]_i_2__6_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__6_n_0\,
      CO(1) => \converge_cnt_reg[18]_i_2__6_n_0\,
      CO(0) => \converge_cnt_reg[17]_i_2__6_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[19]_i_1__6_n_0\,
      O(2) => \converge_cnt_reg[18]_i_1__6_n_0\,
      O(1) => \converge_cnt_reg[17]_i_1__6_n_0\,
      O(0) => \converge_cnt_reg[16]_i_1__6_n_0\,
      S(3 downto 0) => converge_cnt_reg(19 downto 16)
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[18]_i_1__6_n_0\,
      Q => converge_cnt_reg(18),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[19]_i_1__6_n_0\,
      Q => converge_cnt_reg(19),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[1]_i_1__6_n_0\,
      Q => converge_cnt_reg(1),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[1]_i_2__6_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[4]_i_2__6_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__6_n_0\,
      CO(1) => \converge_cnt_reg[2]_i_2__6_n_0\,
      CO(0) => \converge_cnt_reg[1]_i_2__6_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '1',
      O(3) => \converge_cnt_reg[3]_i_1__6_n_0\,
      O(2) => \converge_cnt_reg[2]_i_1__6_n_0\,
      O(1) => \converge_cnt_reg[1]_i_1__6_n_0\,
      O(0) => \converge_cnt_reg[0]_i_3__6_n_0\,
      S(3 downto 1) => converge_cnt_reg(3 downto 1),
      S(0) => \converge_cnt[0]_i_7__6_n_0\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1__6_n_0\,
      Q => converge_cnt_reg(20),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[21]_i_1__6_n_0\,
      Q => converge_cnt_reg(21),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[21]_i_2__6_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[20]_i_2__6_n_0\,
      CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__6_CARRY4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__6_CARRY4_DI_UNCONNECTED\(3 downto 1),
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__6_CARRY4_O_UNCONNECTED\(3 downto 2),
      O(1) => \converge_cnt_reg[21]_i_1__6_n_0\,
      O(0) => \converge_cnt_reg[20]_i_1__6_n_0\,
      S(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__6_CARRY4_S_UNCONNECTED\(3 downto 2),
      S(1 downto 0) => converge_cnt_reg(21 downto 20)
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[2]_i_1__6_n_0\,
      Q => converge_cnt_reg(2),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[3]_i_1__6_n_0\,
      Q => converge_cnt_reg(3),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__6_n_0\,
      Q => converge_cnt_reg(4),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[5]_i_1__6_n_0\,
      Q => converge_cnt_reg(5),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[5]_i_2__6_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_2__6_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_2__6_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__6_n_0\,
      CO(1) => \converge_cnt_reg[6]_i_2__6_n_0\,
      CO(0) => \converge_cnt_reg[5]_i_2__6_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[7]_i_1__6_n_0\,
      O(2) => \converge_cnt_reg[6]_i_1__6_n_0\,
      O(1) => \converge_cnt_reg[5]_i_1__6_n_0\,
      O(0) => \converge_cnt_reg[4]_i_1__6_n_0\,
      S(3 downto 0) => converge_cnt_reg(7 downto 4)
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[6]_i_1__6_n_0\,
      Q => converge_cnt_reg(6),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[7]_i_1__6_n_0\,
      Q => converge_cnt_reg(7),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__6_n_0\,
      Q => converge_cnt_reg(8),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => sel,
      D => \converge_cnt_reg[9]_i_1__6_n_0\,
      Q => converge_cnt_reg(9),
      R => \converge_cnt[0]_i_1__6_n_0\
    );
\converge_cnt_reg[9]_i_2__6_CARRY4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_2__6_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_2__6_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__6_n_0\,
      CO(1) => \converge_cnt_reg[10]_i_2__6_n_0\,
      CO(0) => \converge_cnt_reg[9]_i_2__6_n_0\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3) => \converge_cnt_reg[11]_i_1__6_n_0\,
      O(2) => \converge_cnt_reg[10]_i_1__6_n_0\,
      O(1) => \converge_cnt_reg[9]_i_1__6_n_0\,
      O(0) => \converge_cnt_reg[8]_i_1__6_n_0\,
      S(3 downto 0) => converge_cnt_reg(11 downto 8)
    );
\converge_gen3_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0C08"
    )
        port map (
      I0 => rxeq_adapt_done_reg2,
      I1 => rate_gen3_reg2,
      I2 => RST_CPLLRESET,
      I3 => converge_gen3_reg_n_0,
      O => \converge_gen3_i_1__6_n_0\
    );
converge_gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \converge_gen3_i_1__6_n_0\,
      Q => converge_gen3_reg_n_0,
      R => '0'
    );
\gt_rx_phy_status_q_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => RST_PHYSTATUS(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => gt_rx_phy_status_wire_filter(0)
    );
\gt_rxvalid_q_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4500000000000000"
    )
        port map (
      I0 => \gt_rxvalid_q_i_6__6_n_0\,
      I1 => gt_rxvalid_q_reg_0,
      I2 => gt_rx_elec_idle_wire_filter(0),
      I3 => rst_idle_reg2,
      I4 => rate_idle_reg2,
      I5 => \resetovrd_disble.reset_reg[4]_0\,
      O => gt_rxvalid_q_reg
    );
\gt_rxvalid_q_i_6__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(1),
      O => \gt_rxvalid_q_i_6__6_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_5__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => \cplllock_reg1_reg[7]\
    );
\gtx_channel.gtxe2_channel_i_i_62\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => converge_gen3_reg_n_0,
      I1 => \gtx_channel.gtxe2_channel_i_i_72_n_0\,
      I2 => converge_cnt_reg(8),
      I3 => converge_cnt_reg(9),
      I4 => \converge_cnt[0]_i_9__4_n_0\,
      I5 => \converge_cnt[0]_i_5__6_n_0\,
      O => user_rx_converge(0)
    );
\gtx_channel.gtxe2_channel_i_i_72\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => converge_cnt_reg(12),
      I1 => converge_cnt_reg(14),
      I2 => \gtx_channel.gtxe2_channel_i_i_81_n_0\,
      I3 => converge_cnt_reg(2),
      I4 => converge_cnt_reg(6),
      O => \gtx_channel.gtxe2_channel_i_i_72_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_81\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000000000000"
    )
        port map (
      I0 => converge_cnt_reg(20),
      I1 => converge_cnt_reg(3),
      I2 => converge_cnt_reg(0),
      I3 => converge_cnt_reg(1),
      I4 => converge_cnt_reg(10),
      I5 => converge_cnt_reg(21),
      O => \gtx_channel.gtxe2_channel_i_i_81_n_0\
    );
\oobclk_div.oobclk_cnt[0]_i_1__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => RST_CPLLRESET
    );
\oobclk_div.oobclk_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1__6_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \oobclk_div.oobclk_i_1__6_n_0\,
      Q => USER_OOBCLK,
      R => RST_CPLLRESET
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => CLK_PCLK_SEL(0),
      Q => pclk_sel_reg1,
      R => RST_CPLLRESET
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => RST_CPLLRESET
    );
phy_rdy_n_int_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => rst_idle_reg2,
      I1 => p_2_in,
      I2 => p_2_in_2,
      I3 => p_2_in_3,
      I4 => p_2_in_4,
      I5 => p_2_in_5,
      O => phy_rdy_n_int_reg
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_DONE,
      Q => rate_done_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg(0),
      Q => rate_gen3_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_IDLE,
      Q => rate_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RATE_RXSYNC,
      Q => rate_rxsync_reg1,
      R => RST_RXUSRCLK_RESET
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => RST_RXUSRCLK_RESET
    );
\resetdone_reg1[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txresetdone_reg2,
      I1 => rxresetdone_reg2,
      O => RST_RESETDONE(0)
    );
\resetovrd_disble.fsm_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(0),
      R => '0'
    );
\resetovrd_disble.fsm_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => fsm(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(0),
      R => '0'
    );
\resetovrd_disble.reset_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(1),
      R => '0'
    );
\resetovrd_disble.reset_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(2),
      R => '0'
    );
\resetovrd_disble.reset_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(3),
      R => '0'
    );
\resetovrd_disble.reset_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(4),
      R => '0'
    );
\resetovrd_disble.reset_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(5),
      R => '0'
    );
\resetovrd_disble.reset_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => Q(6),
      R => '0'
    );
\resetovrd_done_reg1_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fsm(1),
      I1 => fsm(0),
      O => resetovrd_done_reg1_reg
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RESETOVRD_START,
      Q => resetovrd_start_reg1,
      R => RST_CPLLRESET
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => RST_CPLLRESET
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => out1(0),
      Q => rst_idle_reg1,
      R => RST_RXUSRCLK_RESET
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxcdrlock_cnt[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(2),
      I2 => \rxcdrlock_cnt_reg__0\(0),
      I3 => \rxcdrlock_cnt_reg__0\(1),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(0)
    );
\rxcdrlock_cnt[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(0),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(2),
      I4 => \rxcdrlock_cnt_reg__0\(3),
      O => \p_0_in__0\(1)
    );
\rxcdrlock_cnt[2]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8CCCC000"
    )
        port map (
      I0 => \rxcdrlock_cnt_reg__0\(3),
      I1 => rxcdrlock_reg2,
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(2)
    );
\rxcdrlock_cnt[3]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => \p_0_in__0\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \rxcdrlock_cnt_reg__0\(0),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \rxcdrlock_cnt_reg__0\(1),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \rxcdrlock_cnt_reg__0\(2),
      R => RST_CPLLRESET
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \rxcdrlock_cnt_reg__0\(3),
      R => RST_CPLLRESET
    );
\rxcdrlock_reg1[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \resetovrd_disble.reset_reg[4]_1\,
      I1 => \rxcdrlock_cnt_reg__0\(3),
      I2 => \rxcdrlock_cnt_reg__0\(1),
      I3 => \rxcdrlock_cnt_reg__0\(0),
      I4 => \rxcdrlock_cnt_reg__0\(2),
      O => RST_RXCDRLOCK(0)
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_1\,
      Q => rxcdrlock_reg1,
      R => RST_CPLLRESET
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXEQ_ADAPT_DONE,
      Q => rxeq_adapt_done_reg1,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => RST_CPLLRESET
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_RXRESETDONE,
      Q => rxresetdone_reg1,
      R => RST_CPLLRESET
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => RST_CPLLRESET
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => pipe_rxstatus(0),
      Q => rxstatus_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(3),
      I1 => \rxvalid_cnt_reg__0\(2),
      I2 => \rxvalid_cnt_reg__0\(1),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => \rxvalid_cnt_reg__0\(0),
      O => \p_0_in__0__0\(0)
    );
\rxvalid_cnt[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000E6660000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(0),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(1)
    );
\rxvalid_cnt[2]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000EA6A0000"
    )
        port map (
      I0 => \rxvalid_cnt_reg__0\(2),
      I1 => \rxvalid_cnt_reg__0\(1),
      I2 => \rxvalid_cnt_reg__0\(0),
      I3 => \rxvalid_cnt_reg__0\(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__0__0\(2)
    );
\rxvalid_cnt[3]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D444444400000000"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => \rxvalid_cnt_reg__0\(3),
      I2 => \rxvalid_cnt_reg__0\(2),
      I3 => \rxvalid_cnt_reg__0\(0),
      I4 => \rxvalid_cnt_reg__0\(1),
      I5 => rxvalid_reg2,
      O => \p_0_in__0__0\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(0),
      Q => \rxvalid_cnt_reg__0\(0),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(1),
      Q => \rxvalid_cnt_reg__0\(1),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(2),
      Q => \rxvalid_cnt_reg__0\(2),
      R => RST_RXUSRCLK_RESET
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \p_0_in__0__0\(3),
      Q => \rxvalid_cnt_reg__0\(3),
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => rxvalid_reg1,
      R => RST_RXUSRCLK_RESET
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => RST_RXUSRCLK_RESET
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXCOMPLIANCE(0),
      Q => txcompliance_reg1,
      R => RST_CPLLRESET
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => RST_CPLLRESET
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => PIPE_TXELECIDLE(0),
      Q => txelecidle_reg1,
      R => RST_CPLLRESET
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => RST_CPLLRESET
    );
txphaligndone_reg1_i_6: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => txcompliance_reg2,
      I1 => txelecidle_reg2,
      I2 => pipe_txphaligndone(0),
      O => txphaligndone_reg1_reg
    );
txphinitdone_reg1_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1515151515FFFFFF"
    )
        port map (
      I0 => pipe_txphinitdone(1),
      I1 => txelecidle_reg2,
      I2 => txcompliance_reg2,
      I3 => p_0_in7_in_0,
      I4 => p_1_in8_in_1,
      I5 => pipe_txphinitdone(0),
      O => txphinitdone_reg1_reg
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => USER_TXRESETDONE,
      Q => txresetdone_reg1,
      R => RST_CPLLRESET
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp is
  port (
    QPLL_QPLLRESET0 : out STD_LOGIC;
    DRP_ADDR : out STD_LOGIC_VECTOR ( 7 downto 0 );
    DRP_DI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_DONE : out STD_LOGIC;
    qpll_drp_en : out STD_LOGIC;
    qpll_drp_we : out STD_LOGIC;
    qrst_qpllreset : in STD_LOGIC;
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    DRP_RDY : in STD_LOGIC;
    RATE_QPLLLOCK : in STD_LOGIC;
    DRP_DO : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_GEN3 : in STD_LOGIC;
    DRP_OVRD : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp : entity is "PCIeGen1x8If64_qpll_drp";
end PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp is
  signal addr : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \crscode[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \crscode[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \crscode[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \crscode[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \crscode[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \crscode[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \crscode[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \crscode_reg_n_0_[0]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[1]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[2]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[3]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[4]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[5]\ : STD_LOGIC;
  signal di : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \di[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \di[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \di[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \di[15]_i_2__0_n_0\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal done : STD_LOGIC;
  signal \done_i_2__0_n_0\ : STD_LOGIC;
  signal \done_i_3__0_n_0\ : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal \fsm[0]_i_2__8_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \fsm[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \fsm[8]_i_3__0_n_0\ : STD_LOGIC;
  signal \fsm[8]_i_4__0_n_0\ : STD_LOGIC;
  signal \fsm[8]_i_5__0_n_0\ : STD_LOGIC;
  signal \fsm[8]_i_6__0_n_0\ : STD_LOGIC;
  signal \fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[5]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[6]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[7]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[8]\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_4__0_n_0\ : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_5__0_n_0\ : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_6__0_n_0\ : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_7__0_n_0\ : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_8__0_n_0\ : STD_LOGIC;
  signal \index[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \index[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \index[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \index[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \index[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \index[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \index[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \index[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \index[2]_i_4__0_n_0\ : STD_LOGIC;
  signal \index[2]_i_5__0_n_0\ : STD_LOGIC;
  signal \index[2]_i_6__0_n_0\ : STD_LOGIC;
  signal \index_reg_n_0_[0]\ : STD_LOGIC;
  signal \index_reg_n_0_[1]\ : STD_LOGIC;
  signal \index_reg_n_0_[2]\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \load_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \load_cnt[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \load_cnt[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \mode_i_1__8_n_0\ : STD_LOGIC;
  signal \mode_i_2__8_n_0\ : STD_LOGIC;
  signal \mode_i_3__0_n_0\ : STD_LOGIC;
  signal \mode_i_4__0_n_0\ : STD_LOGIC;
  signal \mode_i_5__0_n_0\ : STD_LOGIC;
  signal \mode_i_6__0_n_0\ : STD_LOGIC;
  signal \mode_i_7__0_n_0\ : STD_LOGIC;
  signal \mode_i_8__0_n_0\ : STD_LOGIC;
  signal \mode_i_9__0_n_0\ : STD_LOGIC;
  signal mode_reg_n_0 : STD_LOGIC;
  signal ovrd_reg1 : STD_LOGIC;
  signal ovrd_reg2 : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  signal qplllock_reg2 : STD_LOGIC;
  signal rdy_reg1 : STD_LOGIC;
  signal rdy_reg2 : STD_LOGIC;
  signal start_reg1 : STD_LOGIC;
  signal start_reg2 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \addr[0]_i_1__0\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \addr[1]_i_1__0\ : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of \addr[2]_i_1__0\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \addr[3]_i_1__0\ : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \addr[5]_i_1__0\ : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of \addr[7]_i_1__0\ : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \di[12]_i_2__0\ : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \di[14]_i_2__0\ : label is "soft_lutpair122";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \done_i_1__8\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \done_i_3__0\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \fsm[0]_i_2__8\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \fsm[7]_i_2__0\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \fsm[8]_i_3__0\ : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of \fsm[8]_i_4__0\ : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of \fsm[8]_i_5__0\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \fsm[8]_i_6__0\ : label is "soft_lutpair124";
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \gtx_common.gtxe2_common_i_i_4__0\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \gtx_common.gtxe2_common_i_i_5__0\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \gtx_common.gtxe2_common_i_i_8__0\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \index[0]_i_3__0\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \index[0]_i_4__0\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \index[1]_i_3__0\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \index[2]_i_2__0\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \index[2]_i_3__0\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \index[2]_i_4__0\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \load_cnt[1]_i_2__0\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \load_cnt[1]_i_3__0\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \mode_i_4__0\ : label is "soft_lutpair121";
  attribute ASYNC_REG of ovrd_reg1_reg : label is std.standard.true;
  attribute KEEP of ovrd_reg1_reg : label is "yes";
  attribute ASYNC_REG of ovrd_reg2_reg : label is std.standard.true;
  attribute KEEP of ovrd_reg2_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute ASYNC_REG of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute ASYNC_REG of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
begin
\addr[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      O => addr(0)
    );
\addr[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[1]\,
      O => addr(1)
    );
\addr[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2B"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      O => addr(2)
    );
\addr[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      O => addr(3)
    );
\addr[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      O => addr(4)
    );
\addr[5]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      O => addr(5)
    );
\addr[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      O => addr(7)
    );
\addr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(0),
      Q => DRP_ADDR(0),
      R => RST_DCLK_RESET
    );
\addr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(1),
      Q => DRP_ADDR(1),
      R => RST_DCLK_RESET
    );
\addr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(2),
      Q => DRP_ADDR(2),
      R => RST_DCLK_RESET
    );
\addr_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(3),
      Q => DRP_ADDR(3),
      R => RST_DCLK_RESET
    );
\addr_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(4),
      Q => DRP_ADDR(4),
      R => RST_DCLK_RESET
    );
\addr_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(5),
      Q => DRP_ADDR(5),
      R => RST_DCLK_RESET
    );
\addr_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => DRP_ADDR(6),
      R => RST_DCLK_RESET
    );
\addr_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(7),
      Q => DRP_ADDR(7),
      R => RST_DCLK_RESET
    );
\crscode[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(1),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[0]_i_1__0_n_0\
    );
\crscode[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(2),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[1]_i_1__0_n_0\
    );
\crscode[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(3),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[2]_i_1__0_n_0\
    );
\crscode[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(4),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[3]_i_1__0_n_0\
    );
\crscode[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(5),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[4]_i_1__0_n_0\
    );
\crscode[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => ovrd_reg2,
      I3 => \index_reg_n_0_[1]\,
      O => \crscode[5]_i_1__0_n_0\
    );
\crscode[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(6),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[5]_i_2__0_n_0\
    );
\crscode_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1__0_n_0\,
      D => \crscode[0]_i_1__0_n_0\,
      Q => \crscode_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\crscode_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1__0_n_0\,
      D => \crscode[1]_i_1__0_n_0\,
      Q => \crscode_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\crscode_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1__0_n_0\,
      D => \crscode[2]_i_1__0_n_0\,
      Q => \crscode_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\crscode_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1__0_n_0\,
      D => \crscode[3]_i_1__0_n_0\,
      Q => \crscode_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\crscode_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1__0_n_0\,
      D => \crscode[4]_i_1__0_n_0\,
      Q => \crscode_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\crscode_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1__0_n_0\,
      D => \crscode[5]_i_2__0_n_0\,
      Q => \crscode_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\di[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(0),
      O => di(0)
    );
\di[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5FBF0010"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[1]\,
      I4 => do_reg2(10),
      O => di(10)
    );
\di[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBB8B88"
    )
        port map (
      I0 => \di[11]_i_2__0_n_0\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => \index_reg_n_0_[1]\,
      I4 => do_reg2(11),
      O => di(11)
    );
\di[11]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F909"
    )
        port map (
      I0 => \crscode_reg_n_0_[1]\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => ovrd_reg2,
      I4 => \index_reg_n_0_[1]\,
      O => \di[11]_i_2__0_n_0\
    );
\di[12]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F00FF9F00000090"
    )
        port map (
      I0 => \crscode_reg_n_0_[2]\,
      I1 => \di[12]_i_2__0_n_0\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[0]\,
      I4 => \index_reg_n_0_[1]\,
      I5 => do_reg2(12),
      O => di(12)
    );
\di[12]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \crscode_reg_n_0_[0]\,
      I1 => \crscode_reg_n_0_[1]\,
      O => \di[12]_i_2__0_n_0\
    );
\di[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3FBB0388"
    )
        port map (
      I0 => \di[13]_i_2__0_n_0\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => \index_reg_n_0_[1]\,
      I4 => do_reg2(13),
      O => di(13)
    );
\di[13]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBB88888888B"
    )
        port map (
      I0 => do_reg2(13),
      I1 => \index_reg_n_0_[0]\,
      I2 => \crscode_reg_n_0_[2]\,
      I3 => \crscode_reg_n_0_[0]\,
      I4 => \crscode_reg_n_0_[1]\,
      I5 => \crscode_reg_n_0_[3]\,
      O => \di[13]_i_2__0_n_0\
    );
\di[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3FFB0308"
    )
        port map (
      I0 => \di[14]_i_2__0_n_0\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => \index_reg_n_0_[1]\,
      I4 => do_reg2(14),
      O => di(14)
    );
\di[14]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => \crscode_reg_n_0_[1]\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \crscode_reg_n_0_[2]\,
      I3 => \crscode_reg_n_0_[3]\,
      I4 => \crscode_reg_n_0_[4]\,
      O => \di[14]_i_2__0_n_0\
    );
\di[15]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5FEF0040"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \di[15]_i_2__0_n_0\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[1]\,
      I4 => do_reg2(15),
      O => di(15)
    );
\di[15]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \crscode_reg_n_0_[5]\,
      I1 => \crscode_reg_n_0_[1]\,
      I2 => \crscode_reg_n_0_[0]\,
      I3 => \crscode_reg_n_0_[3]\,
      I4 => \crscode_reg_n_0_[2]\,
      I5 => \crscode_reg_n_0_[4]\,
      O => \di[15]_i_2__0_n_0\
    );
\di[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(1),
      O => di(1)
    );
\di[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(2),
      O => di(2)
    );
\di[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(3),
      O => di(3)
    );
\di[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"70E070E070F170E0"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => do_reg2(4),
      I3 => \index_reg_n_0_[0]\,
      I4 => mode_reg_n_0,
      I5 => gen3_reg2,
      O => di(4)
    );
\di[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"70F1"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => do_reg2(5),
      I3 => \index_reg_n_0_[0]\,
      O => di(5)
    );
\di[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4DC84DCD4DC84DC8"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => do_reg2(6),
      I2 => \index_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[0]\,
      I4 => gen3_reg2,
      I5 => mode_reg_n_0,
      O => di(6)
    );
\di[7]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(7),
      O => di(7)
    );
\di[8]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"70F1"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => do_reg2(8),
      I3 => \index_reg_n_0_[0]\,
      O => di(8)
    );
\di[9]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(9),
      O => di(9)
    );
\di_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(0),
      Q => DRP_DI(0),
      R => RST_DCLK_RESET
    );
\di_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(10),
      Q => DRP_DI(10),
      R => RST_DCLK_RESET
    );
\di_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(11),
      Q => DRP_DI(11),
      R => RST_DCLK_RESET
    );
\di_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(12),
      Q => DRP_DI(12),
      R => RST_DCLK_RESET
    );
\di_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(13),
      Q => DRP_DI(13),
      R => RST_DCLK_RESET
    );
\di_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(14),
      Q => DRP_DI(14),
      R => RST_DCLK_RESET
    );
\di_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(15),
      Q => DRP_DI(15),
      R => RST_DCLK_RESET
    );
\di_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(1),
      Q => DRP_DI(1),
      R => RST_DCLK_RESET
    );
\di_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(2),
      Q => DRP_DI(2),
      R => RST_DCLK_RESET
    );
\di_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(3),
      Q => DRP_DI(3),
      R => RST_DCLK_RESET
    );
\di_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(4),
      Q => DRP_DI(4),
      R => RST_DCLK_RESET
    );
\di_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(5),
      Q => DRP_DI(5),
      R => RST_DCLK_RESET
    );
\di_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(6),
      Q => DRP_DI(6),
      R => RST_DCLK_RESET
    );
\di_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(7),
      Q => DRP_DI(7),
      R => RST_DCLK_RESET
    );
\di_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(8),
      Q => DRP_DI(8),
      R => RST_DCLK_RESET
    );
\di_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(9),
      Q => DRP_DI(9),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(0),
      Q => do_reg1(0),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(10),
      Q => do_reg1(10),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(11),
      Q => do_reg1(11),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(12),
      Q => do_reg1(12),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(13),
      Q => do_reg1(13),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(14),
      Q => do_reg1(14),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(15),
      Q => do_reg1(15),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(1),
      Q => do_reg1(1),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(2),
      Q => do_reg1(2),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(3),
      Q => do_reg1(3),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(4),
      Q => do_reg1(4),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(5),
      Q => do_reg1(5),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(6),
      Q => do_reg1(6),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(7),
      Q => do_reg1(7),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(8),
      Q => do_reg1(8),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(9),
      Q => do_reg1(9),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => RST_DCLK_RESET
    );
\done_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8088"
    )
        port map (
      I0 => \done_i_2__0_n_0\,
      I1 => \done_i_3__0_n_0\,
      I2 => \fsm_reg_n_0_[4]\,
      I3 => \fsm_reg_n_0_[3]\,
      O => done
    );
\done_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[8]\,
      I3 => start_reg2,
      I4 => \fsm_reg_n_0_[7]\,
      I5 => \fsm_reg_n_0_[4]\,
      O => \done_i_2__0_n_0\
    );
\done_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0E0E000E"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => \fsm_reg_n_0_[7]\,
      O => \done_i_3__0_n_0\
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => done,
      Q => DRP_DONE,
      R => RST_DCLK_RESET
    );
\fsm[0]_i_1__16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8FFF8FFFFFFFF"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => \fsm_reg_n_0_[8]\,
      I2 => \fsm[0]_i_2__8_n_0\,
      I3 => \fsm_reg_n_0_[0]\,
      I4 => start_reg2,
      I5 => \fsm[8]_i_2__0_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => mode_reg_n_0,
      O => \fsm[0]_i_2__8_n_0\
    );
\fsm[1]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => \fsm[8]_i_2__0_n_0\,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => fsm1,
      I3 => \fsm[1]_i_2__0_n_0\,
      O => fsm(1)
    );
\fsm[1]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8FFF8888"
    )
        port map (
      I0 => start_reg2,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => load_cnt(0),
      I3 => load_cnt(1),
      I4 => \fsm_reg_n_0_[1]\,
      O => \fsm[1]_i_2__0_n_0\
    );
\fsm[2]_i_1__16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \fsm[8]_i_2__0_n_0\,
      I1 => load_cnt(0),
      I2 => load_cnt(1),
      I3 => \fsm_reg_n_0_[1]\,
      O => fsm(2)
    );
\fsm[3]_i_1__8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => \fsm[8]_i_2__0_n_0\,
      I1 => \fsm_reg_n_0_[3]\,
      I2 => rdy_reg2,
      I3 => \fsm_reg_n_0_[2]\,
      O => fsm(3)
    );
\fsm[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \fsm[8]_i_2__0_n_0\,
      I1 => rdy_reg2,
      I2 => \fsm_reg_n_0_[3]\,
      O => fsm(4)
    );
\fsm[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => \fsm[8]_i_2__0_n_0\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => rdy_reg2,
      I3 => \fsm_reg_n_0_[4]\,
      O => fsm(5)
    );
\fsm[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \fsm[8]_i_2__0_n_0\,
      I1 => rdy_reg2,
      I2 => \fsm_reg_n_0_[5]\,
      O => fsm(6)
    );
\fsm[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA80808080808080"
    )
        port map (
      I0 => \fsm[8]_i_2__0_n_0\,
      I1 => \fsm_reg_n_0_[7]\,
      I2 => qplllock_reg2,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => fsm1,
      I5 => mode_reg_n_0,
      O => fsm(7)
    );
\fsm[7]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E0"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => mode_reg_n_0,
      I2 => \index_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[0]\,
      O => fsm1
    );
\fsm[8]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0A08"
    )
        port map (
      I0 => \fsm[8]_i_2__0_n_0\,
      I1 => \fsm_reg_n_0_[8]\,
      I2 => qplllock_reg2,
      I3 => \fsm_reg_n_0_[7]\,
      O => fsm(8)
    );
\fsm[8]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0012"
    )
        port map (
      I0 => \fsm[8]_i_3__0_n_0\,
      I1 => \fsm[8]_i_4__0_n_0\,
      I2 => \fsm[8]_i_5__0_n_0\,
      I3 => \fsm[8]_i_6__0_n_0\,
      O => \fsm[8]_i_2__0_n_0\
    );
\fsm[8]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[3]\,
      O => \fsm[8]_i_3__0_n_0\
    );
\fsm[8]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEE8"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[3]\,
      O => \fsm[8]_i_4__0_n_0\
    );
\fsm[8]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[6]\,
      I3 => \fsm_reg_n_0_[7]\,
      I4 => \fsm_reg_n_0_[8]\,
      O => \fsm[8]_i_5__0_n_0\
    );
\fsm[8]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFEE8"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[6]\,
      I3 => \fsm_reg_n_0_[7]\,
      I4 => \fsm_reg_n_0_[8]\,
      O => \fsm[8]_i_6__0_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(0),
      Q => \fsm_reg_n_0_[0]\,
      S => RST_DCLK_RESET
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(1),
      Q => \fsm_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(2),
      Q => \fsm_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(3),
      Q => \fsm_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(4),
      Q => \fsm_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(5),
      Q => \fsm_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(6),
      Q => \fsm_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(7),
      Q => \fsm_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(8),
      Q => \fsm_reg_n_0_[8]\,
      R => RST_DCLK_RESET
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_GEN3,
      Q => gen3_reg1,
      R => RST_DCLK_RESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_DCLK_RESET
    );
\gtx_common.gtxe2_common_i_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010100"
    )
        port map (
      I0 => \gtx_common.gtxe2_common_i_i_4__0_n_0\,
      I1 => \gtx_common.gtxe2_common_i_i_5__0_n_0\,
      I2 => \gtx_common.gtxe2_common_i_i_6__0_n_0\,
      I3 => \fsm_reg_n_0_[4]\,
      I4 => \fsm_reg_n_0_[2]\,
      I5 => \fsm_reg_n_0_[1]\,
      O => qpll_drp_en
    );
\gtx_common.gtxe2_common_i_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[4]\,
      I3 => \gtx_common.gtxe2_common_i_i_7__0_n_0\,
      O => qpll_drp_we
    );
\gtx_common.gtxe2_common_i_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000010"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \gtx_common.gtxe2_common_i_i_8__0_n_0\,
      I3 => \fsm_reg_n_0_[5]\,
      I4 => \fsm_reg_n_0_[8]\,
      I5 => qrst_qpllreset,
      O => QPLL_QPLLRESET0
    );
\gtx_common.gtxe2_common_i_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[6]\,
      I1 => \fsm_reg_n_0_[7]\,
      O => \gtx_common.gtxe2_common_i_i_4__0_n_0\
    );
\gtx_common.gtxe2_common_i_i_5__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[8]\,
      I1 => \fsm_reg_n_0_[5]\,
      O => \gtx_common.gtxe2_common_i_i_5__0_n_0\
    );
\gtx_common.gtxe2_common_i_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[0]\,
      O => \gtx_common.gtxe2_common_i_i_6__0_n_0\
    );
\gtx_common.gtxe2_common_i_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[6]\,
      I1 => \fsm_reg_n_0_[7]\,
      I2 => \fsm_reg_n_0_[8]\,
      I3 => \fsm_reg_n_0_[5]\,
      I4 => \fsm_reg_n_0_[0]\,
      I5 => \fsm_reg_n_0_[3]\,
      O => \gtx_common.gtxe2_common_i_i_7__0_n_0\
    );
\gtx_common.gtxe2_common_i_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \fsm_reg_n_0_[7]\,
      I1 => \fsm_reg_n_0_[4]\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => \fsm_reg_n_0_[2]\,
      O => \gtx_common.gtxe2_common_i_i_8__0_n_0\
    );
\index[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200FFFF02000000"
    )
        port map (
      I0 => \index[0]_i_2__0_n_0\,
      I1 => \index[0]_i_3__0_n_0\,
      I2 => \index[0]_i_4__0_n_0\,
      I3 => \index[0]_i_5__0_n_0\,
      I4 => \index[2]_i_4__0_n_0\,
      I5 => \index_reg_n_0_[0]\,
      O => \index[0]_i_1__0_n_0\
    );
\index[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[7]\,
      I1 => \fsm_reg_n_0_[8]\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => \index_reg_n_0_[0]\,
      I5 => fsm1,
      O => \index[0]_i_2__0_n_0\
    );
\index[0]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      O => \index[0]_i_3__0_n_0\
    );
\index[0]_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[0]\,
      O => \index[0]_i_4__0_n_0\
    );
\index[0]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F2F200F2"
    )
        port map (
      I0 => \fsm_reg_n_0_[6]\,
      I1 => \fsm_reg_n_0_[7]\,
      I2 => \fsm_reg_n_0_[8]\,
      I3 => \fsm_reg_n_0_[3]\,
      I4 => \fsm_reg_n_0_[4]\,
      I5 => \fsm_reg_n_0_[5]\,
      O => \index[0]_i_5__0_n_0\
    );
\index[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF80000000"
    )
        port map (
      I0 => \index[1]_i_2__0_n_0\,
      I1 => \index[1]_i_3__0_n_0\,
      I2 => \index[2]_i_3__0_n_0\,
      I3 => \index_reg_n_0_[0]\,
      I4 => \index[2]_i_4__0_n_0\,
      I5 => \index_reg_n_0_[1]\,
      O => \index[1]_i_1__0_n_0\
    );
\index[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => fsm1,
      I4 => \fsm_reg_n_0_[7]\,
      I5 => \fsm_reg_n_0_[8]\,
      O => \index[1]_i_2__0_n_0\
    );
\index[1]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[4]\,
      O => \index[1]_i_3__0_n_0\
    );
\index[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A00FFFF80000000"
    )
        port map (
      I0 => \index[2]_i_2__0_n_0\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => \index[2]_i_3__0_n_0\,
      I4 => \index[2]_i_4__0_n_0\,
      I5 => \index_reg_n_0_[2]\,
      O => \index[2]_i_1__0_n_0\
    );
\index[2]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => \index[2]_i_5__0_n_0\,
      O => \index[2]_i_2__0_n_0\
    );
\index[2]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \fsm_reg_n_0_[8]\,
      I1 => \fsm_reg_n_0_[7]\,
      I2 => \fsm_reg_n_0_[6]\,
      O => \index[2]_i_3__0_n_0\
    );
\index[2]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \index[2]_i_6__0_n_0\,
      I1 => \fsm_reg_n_0_[7]\,
      I2 => \fsm_reg_n_0_[8]\,
      I3 => \fsm_reg_n_0_[6]\,
      O => \index[2]_i_4__0_n_0\
    );
\index[2]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => fsm1,
      I4 => \fsm_reg_n_0_[7]\,
      I5 => \fsm_reg_n_0_[8]\,
      O => \index[2]_i_5__0_n_0\
    );
\index[2]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFEE9"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => \fsm_reg_n_0_[1]\,
      I5 => \fsm_reg_n_0_[0]\,
      O => \index[2]_i_6__0_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \index[0]_i_1__0_n_0\,
      Q => \index_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \index[1]_i_1__0_n_0\,
      Q => \index_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \index[2]_i_1__0_n_0\,
      Q => \index_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\load_cnt[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000200020"
    )
        port map (
      I0 => \load_cnt[1]_i_2__0_n_0\,
      I1 => \load_cnt[1]_i_3__0_n_0\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => load_cnt(1),
      I5 => load_cnt(0),
      O => \load_cnt[0]_i_1__5_n_0\
    );
\load_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020002000200000"
    )
        port map (
      I0 => \load_cnt[1]_i_2__0_n_0\,
      I1 => \load_cnt[1]_i_3__0_n_0\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => load_cnt(1),
      I5 => load_cnt(0),
      O => \load_cnt[1]_i_1__0_n_0\
    );
\load_cnt[1]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[3]\,
      I2 => \fsm_reg_n_0_[4]\,
      O => \load_cnt[1]_i_2__0_n_0\
    );
\load_cnt[1]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \fsm_reg_n_0_[7]\,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => \fsm_reg_n_0_[5]\,
      I3 => \fsm_reg_n_0_[8]\,
      O => \load_cnt[1]_i_3__0_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[0]_i_1__5_n_0\,
      Q => load_cnt(0),
      R => RST_DCLK_RESET
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[1]_i_1__0_n_0\,
      Q => load_cnt(1),
      R => RST_DCLK_RESET
    );
\mode_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200A2A"
    )
        port map (
      I0 => mode_reg_n_0,
      I1 => \mode_i_2__8_n_0\,
      I2 => \fsm_reg_n_0_[8]\,
      I3 => \fsm_reg_n_0_[7]\,
      I4 => \mode_i_3__0_n_0\,
      O => \mode_i_1__8_n_0\
    );
\mode_i_2__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF5D5DFF5D"
    )
        port map (
      I0 => \fsm_reg_n_0_[8]\,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => \fsm_reg_n_0_[7]\,
      I3 => \fsm_reg_n_0_[0]\,
      I4 => \fsm_reg_n_0_[1]\,
      I5 => \mode_i_4__0_n_0\,
      O => \mode_i_2__8_n_0\
    );
\mode_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F4FFF400"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \mode_i_5__0_n_0\,
      I3 => \fsm_reg_n_0_[7]\,
      I4 => \mode_i_6__0_n_0\,
      O => \mode_i_3__0_n_0\
    );
\mode_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[4]\,
      I2 => \fsm_reg_n_0_[5]\,
      I3 => \fsm_reg_n_0_[1]\,
      I4 => \fsm_reg_n_0_[2]\,
      O => \mode_i_4__0_n_0\
    );
\mode_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[4]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[5]\,
      I4 => \fsm_reg_n_0_[6]\,
      I5 => \fsm_reg_n_0_[1]\,
      O => \mode_i_5__0_n_0\
    );
\mode_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8B88"
    )
        port map (
      I0 => \mode_i_7__0_n_0\,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => \mode_i_8__0_n_0\,
      I3 => \mode_i_9__0_n_0\,
      O => \mode_i_6__0_n_0\
    );
\mode_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[5]\,
      I4 => \fsm_reg_n_0_[4]\,
      I5 => \fsm_reg_n_0_[3]\,
      O => \mode_i_7__0_n_0\
    );
\mode_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \fsm_reg_n_0_[5]\,
      I1 => \fsm_reg_n_0_[4]\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => \fsm_reg_n_0_[0]\,
      I4 => \fsm_reg_n_0_[1]\,
      I5 => \fsm_reg_n_0_[2]\,
      O => \mode_i_8__0_n_0\
    );
\mode_i_9__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFEED"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[4]\,
      I4 => \fsm_reg_n_0_[5]\,
      I5 => \fsm_reg_n_0_[3]\,
      O => \mode_i_9__0_n_0\
    );
mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \mode_i_1__8_n_0\,
      Q => mode_reg_n_0,
      R => RST_DCLK_RESET
    );
ovrd_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_OVRD,
      Q => ovrd_reg1,
      R => RST_DCLK_RESET
    );
ovrd_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ovrd_reg1,
      Q => ovrd_reg2,
      R => RST_DCLK_RESET
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => RATE_QPLLLOCK,
      Q => qplllock_reg1,
      R => RST_DCLK_RESET
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => RST_DCLK_RESET
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_RDY,
      Q => rdy_reg1,
      R => RST_DCLK_RESET
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => RST_DCLK_RESET
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_START,
      Q => start_reg1,
      R => RST_DCLK_RESET
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => RST_DCLK_RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp_84 is
  port (
    QPLL_QPLLRESET0126_out : out STD_LOGIC;
    DRP_ADDR : out STD_LOGIC_VECTOR ( 7 downto 0 );
    DRP_DI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_DONE : out STD_LOGIC;
    qpll_drp_en : out STD_LOGIC;
    qpll_drp_we : out STD_LOGIC;
    qrst_qpllreset : in STD_LOGIC;
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    DRP_RDY : in STD_LOGIC;
    RATE_QPLLLOCK : in STD_LOGIC;
    DRP_DO : in STD_LOGIC_VECTOR ( 15 downto 0 );
    O1687 : in STD_LOGIC;
    DRP_OVRD : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp_84 : entity is "PCIeGen1x8If64_qpll_drp";
end PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp_84;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp_84 is
  signal addr : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \crscode[0]_i_1_n_0\ : STD_LOGIC;
  signal \crscode[1]_i_1_n_0\ : STD_LOGIC;
  signal \crscode[2]_i_1_n_0\ : STD_LOGIC;
  signal \crscode[3]_i_1_n_0\ : STD_LOGIC;
  signal \crscode[4]_i_1_n_0\ : STD_LOGIC;
  signal \crscode[5]_i_1_n_0\ : STD_LOGIC;
  signal \crscode[5]_i_2_n_0\ : STD_LOGIC;
  signal \crscode_reg_n_0_[0]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[1]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[2]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[3]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[4]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[5]\ : STD_LOGIC;
  signal di : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di[11]_i_2_n_0\ : STD_LOGIC;
  signal \di[12]_i_2_n_0\ : STD_LOGIC;
  signal \di[13]_i_2_n_0\ : STD_LOGIC;
  signal \di[14]_i_2_n_0\ : STD_LOGIC;
  signal \di[15]_i_2_n_0\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal done : STD_LOGIC;
  signal done_i_2_n_0 : STD_LOGIC;
  signal done_i_3_n_0 : STD_LOGIC;
  signal fsm : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal \fsm[0]_i_2__7_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_2_n_0\ : STD_LOGIC;
  signal \fsm[8]_i_2_n_0\ : STD_LOGIC;
  signal \fsm[8]_i_3_n_0\ : STD_LOGIC;
  signal \fsm[8]_i_4_n_0\ : STD_LOGIC;
  signal \fsm[8]_i_5_n_0\ : STD_LOGIC;
  signal \fsm[8]_i_6_n_0\ : STD_LOGIC;
  signal \fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[5]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[6]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[7]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[8]\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_4_n_0\ : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_5_n_0\ : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_6_n_0\ : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_7_n_0\ : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_8_n_0\ : STD_LOGIC;
  signal \index[0]_i_1_n_0\ : STD_LOGIC;
  signal \index[0]_i_2_n_0\ : STD_LOGIC;
  signal \index[0]_i_3_n_0\ : STD_LOGIC;
  signal \index[0]_i_4_n_0\ : STD_LOGIC;
  signal \index[0]_i_5_n_0\ : STD_LOGIC;
  signal \index[1]_i_1_n_0\ : STD_LOGIC;
  signal \index[1]_i_2_n_0\ : STD_LOGIC;
  signal \index[1]_i_3_n_0\ : STD_LOGIC;
  signal \index[2]_i_1_n_0\ : STD_LOGIC;
  signal \index[2]_i_2_n_0\ : STD_LOGIC;
  signal \index[2]_i_3_n_0\ : STD_LOGIC;
  signal \index[2]_i_4_n_0\ : STD_LOGIC;
  signal \index[2]_i_5_n_0\ : STD_LOGIC;
  signal \index[2]_i_6_n_0\ : STD_LOGIC;
  signal \index_reg_n_0_[0]\ : STD_LOGIC;
  signal \index_reg_n_0_[1]\ : STD_LOGIC;
  signal \index_reg_n_0_[2]\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \load_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \load_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \load_cnt[1]_i_3_n_0\ : STD_LOGIC;
  signal \mode_i_1__7_n_0\ : STD_LOGIC;
  signal \mode_i_2__7_n_0\ : STD_LOGIC;
  signal mode_i_3_n_0 : STD_LOGIC;
  signal mode_i_4_n_0 : STD_LOGIC;
  signal mode_i_5_n_0 : STD_LOGIC;
  signal mode_i_6_n_0 : STD_LOGIC;
  signal mode_i_7_n_0 : STD_LOGIC;
  signal mode_i_8_n_0 : STD_LOGIC;
  signal mode_i_9_n_0 : STD_LOGIC;
  signal mode_reg_n_0 : STD_LOGIC;
  signal ovrd_reg1 : STD_LOGIC;
  signal ovrd_reg2 : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  signal qplllock_reg2 : STD_LOGIC;
  signal rdy_reg1 : STD_LOGIC;
  signal rdy_reg2 : STD_LOGIC;
  signal start_reg1 : STD_LOGIC;
  signal start_reg2 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \addr[0]_i_1\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \addr[1]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \addr[2]_i_1\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \addr[3]_i_1\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \addr[5]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \addr[7]_i_1\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \di[12]_i_2\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \di[14]_i_2\ : label is "soft_lutpair19";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SOFT_HLUTNM of \done_i_1__7\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of done_i_3 : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \fsm[0]_i_2__7\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \fsm[7]_i_2\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \fsm[8]_i_3\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \fsm[8]_i_4\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \fsm[8]_i_5\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \fsm[8]_i_6\ : label is "soft_lutpair21";
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM of \gtx_common.gtxe2_common_i_i_4\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \gtx_common.gtxe2_common_i_i_5\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \gtx_common.gtxe2_common_i_i_8\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \index[0]_i_3\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \index[0]_i_4\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \index[1]_i_3\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \index[2]_i_2\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \index[2]_i_3\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \index[2]_i_4\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \load_cnt[1]_i_2\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \load_cnt[1]_i_3\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of mode_i_4 : label is "soft_lutpair18";
  attribute ASYNC_REG of ovrd_reg1_reg : label is std.standard.true;
  attribute KEEP of ovrd_reg1_reg : label is "yes";
  attribute ASYNC_REG of ovrd_reg2_reg : label is std.standard.true;
  attribute KEEP of ovrd_reg2_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute ASYNC_REG of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute ASYNC_REG of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute ASYNC_REG of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute ASYNC_REG of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
begin
\addr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      O => addr(0)
    );
\addr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[1]\,
      O => addr(1)
    );
\addr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2B"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      O => addr(2)
    );
\addr[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      O => addr(3)
    );
\addr[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      O => addr(4)
    );
\addr[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      O => addr(5)
    );
\addr[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      O => addr(7)
    );
\addr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(0),
      Q => DRP_ADDR(0),
      R => RST_DCLK_RESET
    );
\addr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(1),
      Q => DRP_ADDR(1),
      R => RST_DCLK_RESET
    );
\addr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(2),
      Q => DRP_ADDR(2),
      R => RST_DCLK_RESET
    );
\addr_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(3),
      Q => DRP_ADDR(3),
      R => RST_DCLK_RESET
    );
\addr_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(4),
      Q => DRP_ADDR(4),
      R => RST_DCLK_RESET
    );
\addr_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(5),
      Q => DRP_ADDR(5),
      R => RST_DCLK_RESET
    );
\addr_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => '0',
      Q => DRP_ADDR(6),
      R => RST_DCLK_RESET
    );
\addr_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => addr(7),
      Q => DRP_ADDR(7),
      R => RST_DCLK_RESET
    );
\crscode[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(1),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[0]_i_1_n_0\
    );
\crscode[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(2),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[1]_i_1_n_0\
    );
\crscode[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(3),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[2]_i_1_n_0\
    );
\crscode[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(4),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[3]_i_1_n_0\
    );
\crscode[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(5),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[4]_i_1_n_0\
    );
\crscode[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A800"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => ovrd_reg2,
      I3 => \index_reg_n_0_[1]\,
      O => \crscode[5]_i_1_n_0\
    );
\crscode[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(6),
      I1 => \index_reg_n_0_[2]\,
      O => \crscode[5]_i_2_n_0\
    );
\crscode_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1_n_0\,
      D => \crscode[0]_i_1_n_0\,
      Q => \crscode_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\crscode_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1_n_0\,
      D => \crscode[1]_i_1_n_0\,
      Q => \crscode_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\crscode_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1_n_0\,
      D => \crscode[2]_i_1_n_0\,
      Q => \crscode_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\crscode_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1_n_0\,
      D => \crscode[3]_i_1_n_0\,
      Q => \crscode_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\crscode_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1_n_0\,
      D => \crscode[4]_i_1_n_0\,
      Q => \crscode_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\crscode_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => \crscode[5]_i_1_n_0\,
      D => \crscode[5]_i_2_n_0\,
      Q => \crscode_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\di[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(0),
      O => di(0)
    );
\di[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5FBF0010"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[1]\,
      I4 => do_reg2(10),
      O => di(10)
    );
\di[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBB8B88"
    )
        port map (
      I0 => \di[11]_i_2_n_0\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => \index_reg_n_0_[1]\,
      I4 => do_reg2(11),
      O => di(11)
    );
\di[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F909"
    )
        port map (
      I0 => \crscode_reg_n_0_[1]\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => ovrd_reg2,
      I4 => \index_reg_n_0_[1]\,
      O => \di[11]_i_2_n_0\
    );
\di[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F00FF9F00000090"
    )
        port map (
      I0 => \crscode_reg_n_0_[2]\,
      I1 => \di[12]_i_2_n_0\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[0]\,
      I4 => \index_reg_n_0_[1]\,
      I5 => do_reg2(12),
      O => di(12)
    );
\di[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \crscode_reg_n_0_[0]\,
      I1 => \crscode_reg_n_0_[1]\,
      O => \di[12]_i_2_n_0\
    );
\di[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3FBB0388"
    )
        port map (
      I0 => \di[13]_i_2_n_0\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => \index_reg_n_0_[1]\,
      I4 => do_reg2(13),
      O => di(13)
    );
\di[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBB88888888B"
    )
        port map (
      I0 => do_reg2(13),
      I1 => \index_reg_n_0_[0]\,
      I2 => \crscode_reg_n_0_[2]\,
      I3 => \crscode_reg_n_0_[0]\,
      I4 => \crscode_reg_n_0_[1]\,
      I5 => \crscode_reg_n_0_[3]\,
      O => \di[13]_i_2_n_0\
    );
\di[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"3FFB0308"
    )
        port map (
      I0 => \di[14]_i_2_n_0\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => \index_reg_n_0_[1]\,
      I4 => do_reg2(14),
      O => di(14)
    );
\di[14]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => \crscode_reg_n_0_[1]\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \crscode_reg_n_0_[2]\,
      I3 => \crscode_reg_n_0_[3]\,
      I4 => \crscode_reg_n_0_[4]\,
      O => \di[14]_i_2_n_0\
    );
\di[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5FEF0040"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \di[15]_i_2_n_0\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[1]\,
      I4 => do_reg2(15),
      O => di(15)
    );
\di[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \crscode_reg_n_0_[5]\,
      I1 => \crscode_reg_n_0_[1]\,
      I2 => \crscode_reg_n_0_[0]\,
      I3 => \crscode_reg_n_0_[3]\,
      I4 => \crscode_reg_n_0_[2]\,
      I5 => \crscode_reg_n_0_[4]\,
      O => \di[15]_i_2_n_0\
    );
\di[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(1),
      O => di(1)
    );
\di[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(2),
      O => di(2)
    );
\di[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(3),
      O => di(3)
    );
\di[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"70E070E070F170E0"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => do_reg2(4),
      I3 => \index_reg_n_0_[0]\,
      I4 => mode_reg_n_0,
      I5 => gen3_reg2,
      O => di(4)
    );
\di[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"70F1"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => do_reg2(5),
      I3 => \index_reg_n_0_[0]\,
      O => di(5)
    );
\di[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4DC84DCD4DC84DC8"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => do_reg2(6),
      I2 => \index_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[0]\,
      I4 => gen3_reg2,
      I5 => mode_reg_n_0,
      O => di(6)
    );
\di[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(7),
      O => di(7)
    );
\di[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"70F1"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => do_reg2(8),
      I3 => \index_reg_n_0_[0]\,
      O => di(8)
    );
\di[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => do_reg2(9),
      O => di(9)
    );
\di_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(0),
      Q => DRP_DI(0),
      R => RST_DCLK_RESET
    );
\di_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(10),
      Q => DRP_DI(10),
      R => RST_DCLK_RESET
    );
\di_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(11),
      Q => DRP_DI(11),
      R => RST_DCLK_RESET
    );
\di_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(12),
      Q => DRP_DI(12),
      R => RST_DCLK_RESET
    );
\di_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(13),
      Q => DRP_DI(13),
      R => RST_DCLK_RESET
    );
\di_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(14),
      Q => DRP_DI(14),
      R => RST_DCLK_RESET
    );
\di_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(15),
      Q => DRP_DI(15),
      R => RST_DCLK_RESET
    );
\di_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(1),
      Q => DRP_DI(1),
      R => RST_DCLK_RESET
    );
\di_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(2),
      Q => DRP_DI(2),
      R => RST_DCLK_RESET
    );
\di_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(3),
      Q => DRP_DI(3),
      R => RST_DCLK_RESET
    );
\di_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(4),
      Q => DRP_DI(4),
      R => RST_DCLK_RESET
    );
\di_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(5),
      Q => DRP_DI(5),
      R => RST_DCLK_RESET
    );
\di_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(6),
      Q => DRP_DI(6),
      R => RST_DCLK_RESET
    );
\di_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(7),
      Q => DRP_DI(7),
      R => RST_DCLK_RESET
    );
\di_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(8),
      Q => DRP_DI(8),
      R => RST_DCLK_RESET
    );
\di_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => di(9),
      Q => DRP_DI(9),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(0),
      Q => do_reg1(0),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(10),
      Q => do_reg1(10),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(11),
      Q => do_reg1(11),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(12),
      Q => do_reg1(12),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(13),
      Q => do_reg1(13),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(14),
      Q => do_reg1(14),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(15),
      Q => do_reg1(15),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(1),
      Q => do_reg1(1),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(2),
      Q => do_reg1(2),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(3),
      Q => do_reg1(3),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(4),
      Q => do_reg1(4),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(5),
      Q => do_reg1(5),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(6),
      Q => do_reg1(6),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(7),
      Q => do_reg1(7),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(8),
      Q => do_reg1(8),
      R => RST_DCLK_RESET
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_DO(9),
      Q => do_reg1(9),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => RST_DCLK_RESET
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => RST_DCLK_RESET
    );
\done_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8088"
    )
        port map (
      I0 => done_i_2_n_0,
      I1 => done_i_3_n_0,
      I2 => \fsm_reg_n_0_[4]\,
      I3 => \fsm_reg_n_0_[3]\,
      O => done
    );
done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[8]\,
      I3 => start_reg2,
      I4 => \fsm_reg_n_0_[7]\,
      I5 => \fsm_reg_n_0_[4]\,
      O => done_i_2_n_0
    );
done_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0E0E000E"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => \fsm_reg_n_0_[7]\,
      O => done_i_3_n_0
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => done,
      Q => DRP_DONE,
      R => RST_DCLK_RESET
    );
\fsm[0]_i_1__15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8FFF8FFFFFFFF"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => \fsm_reg_n_0_[8]\,
      I2 => \fsm[0]_i_2__7_n_0\,
      I3 => \fsm_reg_n_0_[0]\,
      I4 => start_reg2,
      I5 => \fsm[8]_i_2_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => mode_reg_n_0,
      O => \fsm[0]_i_2__7_n_0\
    );
\fsm[1]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => \fsm[8]_i_2_n_0\,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => fsm1,
      I3 => \fsm[1]_i_2_n_0\,
      O => fsm(1)
    );
\fsm[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8FFF8888"
    )
        port map (
      I0 => start_reg2,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => load_cnt(0),
      I3 => load_cnt(1),
      I4 => \fsm_reg_n_0_[1]\,
      O => \fsm[1]_i_2_n_0\
    );
\fsm[2]_i_1__15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \fsm[8]_i_2_n_0\,
      I1 => load_cnt(0),
      I2 => load_cnt(1),
      I3 => \fsm_reg_n_0_[1]\,
      O => fsm(2)
    );
\fsm[3]_i_1__7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => \fsm[8]_i_2_n_0\,
      I1 => \fsm_reg_n_0_[3]\,
      I2 => rdy_reg2,
      I3 => \fsm_reg_n_0_[2]\,
      O => fsm(3)
    );
\fsm[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \fsm[8]_i_2_n_0\,
      I1 => rdy_reg2,
      I2 => \fsm_reg_n_0_[3]\,
      O => fsm(4)
    );
\fsm[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => \fsm[8]_i_2_n_0\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => rdy_reg2,
      I3 => \fsm_reg_n_0_[4]\,
      O => fsm(5)
    );
\fsm[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \fsm[8]_i_2_n_0\,
      I1 => rdy_reg2,
      I2 => \fsm_reg_n_0_[5]\,
      O => fsm(6)
    );
\fsm[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA80808080808080"
    )
        port map (
      I0 => \fsm[8]_i_2_n_0\,
      I1 => \fsm_reg_n_0_[7]\,
      I2 => qplllock_reg2,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => fsm1,
      I5 => mode_reg_n_0,
      O => fsm(7)
    );
\fsm[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E0"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => mode_reg_n_0,
      I2 => \index_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[0]\,
      O => fsm1
    );
\fsm[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0A08"
    )
        port map (
      I0 => \fsm[8]_i_2_n_0\,
      I1 => \fsm_reg_n_0_[8]\,
      I2 => qplllock_reg2,
      I3 => \fsm_reg_n_0_[7]\,
      O => fsm(8)
    );
\fsm[8]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0012"
    )
        port map (
      I0 => \fsm[8]_i_3_n_0\,
      I1 => \fsm[8]_i_4_n_0\,
      I2 => \fsm[8]_i_5_n_0\,
      I3 => \fsm[8]_i_6_n_0\,
      O => \fsm[8]_i_2_n_0\
    );
\fsm[8]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[3]\,
      O => \fsm[8]_i_3_n_0\
    );
\fsm[8]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEE8"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[3]\,
      O => \fsm[8]_i_4_n_0\
    );
\fsm[8]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010116"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[6]\,
      I3 => \fsm_reg_n_0_[7]\,
      I4 => \fsm_reg_n_0_[8]\,
      O => \fsm[8]_i_5_n_0\
    );
\fsm[8]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFEE8"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[6]\,
      I3 => \fsm_reg_n_0_[7]\,
      I4 => \fsm_reg_n_0_[8]\,
      O => \fsm[8]_i_6_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(0),
      Q => \fsm_reg_n_0_[0]\,
      S => RST_DCLK_RESET
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(1),
      Q => \fsm_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(2),
      Q => \fsm_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(3),
      Q => \fsm_reg_n_0_[3]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(4),
      Q => \fsm_reg_n_0_[4]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(5),
      Q => \fsm_reg_n_0_[5]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(6),
      Q => \fsm_reg_n_0_[6]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(7),
      Q => \fsm_reg_n_0_[7]\,
      R => RST_DCLK_RESET
    );
\fsm_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => fsm(8),
      Q => \fsm_reg_n_0_[8]\,
      R => RST_DCLK_RESET
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => O1687,
      Q => gen3_reg1,
      R => RST_DCLK_RESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_DCLK_RESET
    );
\gtx_common.gtxe2_common_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010100"
    )
        port map (
      I0 => \gtx_common.gtxe2_common_i_i_4_n_0\,
      I1 => \gtx_common.gtxe2_common_i_i_5_n_0\,
      I2 => \gtx_common.gtxe2_common_i_i_6_n_0\,
      I3 => \fsm_reg_n_0_[4]\,
      I4 => \fsm_reg_n_0_[2]\,
      I5 => \fsm_reg_n_0_[1]\,
      O => qpll_drp_en
    );
\gtx_common.gtxe2_common_i_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[4]\,
      I3 => \gtx_common.gtxe2_common_i_i_7_n_0\,
      O => qpll_drp_we
    );
\gtx_common.gtxe2_common_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000010"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \gtx_common.gtxe2_common_i_i_8_n_0\,
      I3 => \fsm_reg_n_0_[5]\,
      I4 => \fsm_reg_n_0_[8]\,
      I5 => qrst_qpllreset,
      O => QPLL_QPLLRESET0126_out
    );
\gtx_common.gtxe2_common_i_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[6]\,
      I1 => \fsm_reg_n_0_[7]\,
      O => \gtx_common.gtxe2_common_i_i_4_n_0\
    );
\gtx_common.gtxe2_common_i_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[8]\,
      I1 => \fsm_reg_n_0_[5]\,
      O => \gtx_common.gtxe2_common_i_i_5_n_0\
    );
\gtx_common.gtxe2_common_i_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[0]\,
      O => \gtx_common.gtxe2_common_i_i_6_n_0\
    );
\gtx_common.gtxe2_common_i_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[6]\,
      I1 => \fsm_reg_n_0_[7]\,
      I2 => \fsm_reg_n_0_[8]\,
      I3 => \fsm_reg_n_0_[5]\,
      I4 => \fsm_reg_n_0_[0]\,
      I5 => \fsm_reg_n_0_[3]\,
      O => \gtx_common.gtxe2_common_i_i_7_n_0\
    );
\gtx_common.gtxe2_common_i_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \fsm_reg_n_0_[7]\,
      I1 => \fsm_reg_n_0_[4]\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => \fsm_reg_n_0_[2]\,
      O => \gtx_common.gtxe2_common_i_i_8_n_0\
    );
\index[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200FFFF02000000"
    )
        port map (
      I0 => \index[0]_i_2_n_0\,
      I1 => \index[0]_i_3_n_0\,
      I2 => \index[0]_i_4_n_0\,
      I3 => \index[0]_i_5_n_0\,
      I4 => \index[2]_i_4_n_0\,
      I5 => \index_reg_n_0_[0]\,
      O => \index[0]_i_1_n_0\
    );
\index[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[7]\,
      I1 => \fsm_reg_n_0_[8]\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => \index_reg_n_0_[0]\,
      I5 => fsm1,
      O => \index[0]_i_2_n_0\
    );
\index[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      O => \index[0]_i_3_n_0\
    );
\index[0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[0]\,
      O => \index[0]_i_4_n_0\
    );
\index[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F2F200F2"
    )
        port map (
      I0 => \fsm_reg_n_0_[6]\,
      I1 => \fsm_reg_n_0_[7]\,
      I2 => \fsm_reg_n_0_[8]\,
      I3 => \fsm_reg_n_0_[3]\,
      I4 => \fsm_reg_n_0_[4]\,
      I5 => \fsm_reg_n_0_[5]\,
      O => \index[0]_i_5_n_0\
    );
\index[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF80000000"
    )
        port map (
      I0 => \index[1]_i_2_n_0\,
      I1 => \index[1]_i_3_n_0\,
      I2 => \index[2]_i_3_n_0\,
      I3 => \index_reg_n_0_[0]\,
      I4 => \index[2]_i_4_n_0\,
      I5 => \index_reg_n_0_[1]\,
      O => \index[1]_i_1_n_0\
    );
\index[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => fsm1,
      I4 => \fsm_reg_n_0_[7]\,
      I5 => \fsm_reg_n_0_[8]\,
      O => \index[1]_i_2_n_0\
    );
\index[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[4]\,
      O => \index[1]_i_3_n_0\
    );
\index[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A00FFFF80000000"
    )
        port map (
      I0 => \index[2]_i_2_n_0\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => \index[2]_i_3_n_0\,
      I4 => \index[2]_i_4_n_0\,
      I5 => \index_reg_n_0_[2]\,
      O => \index[2]_i_1_n_0\
    );
\index[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => \index[2]_i_5_n_0\,
      O => \index[2]_i_2_n_0\
    );
\index[2]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \fsm_reg_n_0_[8]\,
      I1 => \fsm_reg_n_0_[7]\,
      I2 => \fsm_reg_n_0_[6]\,
      O => \index[2]_i_3_n_0\
    );
\index[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \index[2]_i_6_n_0\,
      I1 => \fsm_reg_n_0_[7]\,
      I2 => \fsm_reg_n_0_[8]\,
      I3 => \fsm_reg_n_0_[6]\,
      O => \index[2]_i_4_n_0\
    );
\index[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => fsm1,
      I4 => \fsm_reg_n_0_[7]\,
      I5 => \fsm_reg_n_0_[8]\,
      O => \index[2]_i_5_n_0\
    );
\index[2]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFEE9"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => \fsm_reg_n_0_[1]\,
      I5 => \fsm_reg_n_0_[0]\,
      O => \index[2]_i_6_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \index[0]_i_1_n_0\,
      Q => \index_reg_n_0_[0]\,
      R => RST_DCLK_RESET
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \index[1]_i_1_n_0\,
      Q => \index_reg_n_0_[1]\,
      R => RST_DCLK_RESET
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \index[2]_i_1_n_0\,
      Q => \index_reg_n_0_[2]\,
      R => RST_DCLK_RESET
    );
\load_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020000000200020"
    )
        port map (
      I0 => \load_cnt[1]_i_2_n_0\,
      I1 => \load_cnt[1]_i_3_n_0\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => load_cnt(1),
      I5 => load_cnt(0),
      O => \load_cnt[0]_i_1__0_n_0\
    );
\load_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020002000200000"
    )
        port map (
      I0 => \load_cnt[1]_i_2_n_0\,
      I1 => \load_cnt[1]_i_3_n_0\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => load_cnt(1),
      I5 => load_cnt(0),
      O => \load_cnt[1]_i_1_n_0\
    );
\load_cnt[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[3]\,
      I2 => \fsm_reg_n_0_[4]\,
      O => \load_cnt[1]_i_2_n_0\
    );
\load_cnt[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \fsm_reg_n_0_[7]\,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => \fsm_reg_n_0_[5]\,
      I3 => \fsm_reg_n_0_[8]\,
      O => \load_cnt[1]_i_3_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[0]_i_1__0_n_0\,
      Q => load_cnt(0),
      R => RST_DCLK_RESET
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \load_cnt[1]_i_1_n_0\,
      Q => load_cnt(1),
      R => RST_DCLK_RESET
    );
\mode_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00200A2A"
    )
        port map (
      I0 => mode_reg_n_0,
      I1 => \mode_i_2__7_n_0\,
      I2 => \fsm_reg_n_0_[8]\,
      I3 => \fsm_reg_n_0_[7]\,
      I4 => mode_i_3_n_0,
      O => \mode_i_1__7_n_0\
    );
\mode_i_2__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF5D5DFF5D"
    )
        port map (
      I0 => \fsm_reg_n_0_[8]\,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => \fsm_reg_n_0_[7]\,
      I3 => \fsm_reg_n_0_[0]\,
      I4 => \fsm_reg_n_0_[1]\,
      I5 => mode_i_4_n_0,
      O => \mode_i_2__7_n_0\
    );
mode_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F4FFF400"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => mode_i_5_n_0,
      I3 => \fsm_reg_n_0_[7]\,
      I4 => mode_i_6_n_0,
      O => mode_i_3_n_0
    );
mode_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[4]\,
      I2 => \fsm_reg_n_0_[5]\,
      I3 => \fsm_reg_n_0_[1]\,
      I4 => \fsm_reg_n_0_[2]\,
      O => mode_i_4_n_0
    );
mode_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[4]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[5]\,
      I4 => \fsm_reg_n_0_[6]\,
      I5 => \fsm_reg_n_0_[1]\,
      O => mode_i_5_n_0
    );
mode_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8B88"
    )
        port map (
      I0 => mode_i_7_n_0,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => mode_i_8_n_0,
      I3 => mode_i_9_n_0,
      O => mode_i_6_n_0
    );
mode_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[2]\,
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[5]\,
      I4 => \fsm_reg_n_0_[4]\,
      I5 => \fsm_reg_n_0_[3]\,
      O => mode_i_7_n_0
    );
mode_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \fsm_reg_n_0_[5]\,
      I1 => \fsm_reg_n_0_[4]\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => \fsm_reg_n_0_[0]\,
      I4 => \fsm_reg_n_0_[1]\,
      I5 => \fsm_reg_n_0_[2]\,
      O => mode_i_8_n_0
    );
mode_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFEED"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[4]\,
      I4 => \fsm_reg_n_0_[5]\,
      I5 => \fsm_reg_n_0_[3]\,
      O => mode_i_9_n_0
    );
mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => \mode_i_1__7_n_0\,
      Q => mode_reg_n_0,
      R => RST_DCLK_RESET
    );
ovrd_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_OVRD,
      Q => ovrd_reg1,
      R => RST_DCLK_RESET
    );
ovrd_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => ovrd_reg1,
      Q => ovrd_reg2,
      R => RST_DCLK_RESET
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => RATE_QPLLLOCK,
      Q => qplllock_reg1,
      R => RST_DCLK_RESET
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => RST_DCLK_RESET
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_RDY,
      Q => rdy_reg1,
      R => RST_DCLK_RESET
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => RST_DCLK_RESET
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => DRP_START,
      Q => start_reg1,
      R => RST_DCLK_RESET
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \resetovrd_disble.reset_reg[4]\,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => RST_DCLK_RESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_qpll_reset is
  port (
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    start_reg1_reg : out STD_LOGIC;
    pipe_qrst_idle : out STD_LOGIC;
    qpllpd : out STD_LOGIC;
    qrst_qpllreset : out STD_LOGIC;
    qrst_ovrd : out STD_LOGIC;
    reset_n_reg2_reg : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    done_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpllreset_reg_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
    qpllpd_reg_0 : in STD_LOGIC;
    qpllpd_reg_1 : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_qpll_reset : entity is "PCIeGen1x8If64_qpll_reset";
end PCIeGen1x8If64_PCIeGen1x8If64_qpll_reset;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_qpll_reset is
  signal \FSM_sequential_fsm[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm[0]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm[0]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_sequential_fsm_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_fsm_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_reg_n_0_[2]\ : signal is "yes";
  signal cplllock_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal cplllock_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal drp_done_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal drp_done_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal mmcm_lock_reg1 : STD_LOGIC;
  signal mmcm_lock_reg2 : STD_LOGIC;
  signal \^pipe_qrst_fsm\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal qplllock_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal qplllock_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^qpllpd\ : STD_LOGIC;
  signal qpllpd_i_1_n_0 : STD_LOGIC;
  signal qpllpd_i_2_n_0 : STD_LOGIC;
  signal qpllpd_i_3_n_0 : STD_LOGIC;
  signal qpllpd_in_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal qpllpd_in_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal qpllreset_i_1_n_0 : STD_LOGIC;
  signal qpllreset_i_2_n_0 : STD_LOGIC;
  signal qpllreset_i_3_n_0 : STD_LOGIC;
  signal qpllreset_i_4_n_0 : STD_LOGIC;
  signal qpllreset_in_reg1 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal qpllreset_in_reg2 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^qrst_ovrd\ : STD_LOGIC;
  signal \^qrst_qpllreset\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute KEEP : string;
  attribute KEEP of \FSM_sequential_fsm_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_reg[2]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \cplllock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \cplllock_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \drp_done_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute ASYNC_REG of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute ASYNC_REG of \qplllock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qplllock_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \qplllock_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qplllock_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \qplllock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qplllock_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \qplllock_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qplllock_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \qpllpd_in_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \qpllreset_in_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
begin
  pipe_qrst_fsm(3 downto 0) <= \^pipe_qrst_fsm\(3 downto 0);
  qpllpd <= \^qpllpd\;
  qrst_ovrd <= \^qrst_ovrd\;
  qrst_qpllreset <= \^qrst_qpllreset\;
\FSM_sequential_fsm[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BABB"
    )
        port map (
      I0 => \FSM_sequential_fsm[0]_i_2_n_0\,
      I1 => \FSM_sequential_fsm[0]_i_3_n_0\,
      I2 => \FSM_sequential_fsm[1]_i_2_n_0\,
      I3 => \^pipe_qrst_fsm\(0),
      O => \FSM_sequential_fsm[0]_i_1_n_0\
    );
\FSM_sequential_fsm[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA2A02"
    )
        port map (
      I0 => \FSM_sequential_fsm_reg_n_0_[1]\,
      I1 => drp_done_reg2(1),
      I2 => drp_done_reg2(0),
      I3 => \^pipe_qrst_fsm\(0),
      I4 => \FSM_sequential_fsm_reg_n_0_[2]\,
      O => \FSM_sequential_fsm[0]_i_2_n_0\
    );
\FSM_sequential_fsm[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"77FF77F0"
    )
        port map (
      I0 => qplllock_reg2(0),
      I1 => qplllock_reg2(1),
      I2 => \FSM_sequential_fsm[0]_i_4_n_0\,
      I3 => \FSM_sequential_fsm_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_reg_n_0_[1]\,
      O => \FSM_sequential_fsm[0]_i_3_n_0\
    );
\FSM_sequential_fsm[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555551"
    )
        port map (
      I0 => \^pipe_qrst_fsm\(0),
      I1 => \FSM_sequential_fsm[0]_i_5_n_0\,
      I2 => qplllock_reg2(1),
      I3 => qplllock_reg2(0),
      I4 => cplllock_reg2(3),
      I5 => cplllock_reg2(1),
      O => \FSM_sequential_fsm[0]_i_4_n_0\
    );
\FSM_sequential_fsm[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => cplllock_reg2(0),
      I1 => cplllock_reg2(7),
      I2 => cplllock_reg2(6),
      I3 => cplllock_reg2(4),
      I4 => cplllock_reg2(5),
      I5 => cplllock_reg2(2),
      O => \FSM_sequential_fsm[0]_i_5_n_0\
    );
\FSM_sequential_fsm[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF1FFF44444444"
    )
        port map (
      I0 => \FSM_sequential_fsm[1]_i_2_n_0\,
      I1 => \^pipe_qrst_fsm\(0),
      I2 => drp_done_reg2(1),
      I3 => drp_done_reg2(0),
      I4 => \FSM_sequential_fsm_reg_n_0_[2]\,
      I5 => \FSM_sequential_fsm_reg_n_0_[1]\,
      O => \FSM_sequential_fsm[1]_i_1_n_0\
    );
\FSM_sequential_fsm[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0111111111111111"
    )
        port map (
      I0 => \FSM_sequential_fsm_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm[1]_i_3_n_0\,
      I3 => cplllock_reg2(1),
      I4 => cplllock_reg2(7),
      I5 => cplllock_reg2(3),
      O => \FSM_sequential_fsm[1]_i_2_n_0\
    );
\FSM_sequential_fsm[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => cplllock_reg2(5),
      I1 => cplllock_reg2(0),
      I2 => mmcm_lock_reg2,
      I3 => cplllock_reg2(4),
      I4 => cplllock_reg2(2),
      I5 => cplllock_reg2(6),
      O => \FSM_sequential_fsm[1]_i_3_n_0\
    );
\FSM_sequential_fsm[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAAAAAA"
    )
        port map (
      I0 => \FSM_sequential_fsm_reg_n_0_[2]\,
      I1 => \^pipe_qrst_fsm\(0),
      I2 => drp_done_reg2(1),
      I3 => drp_done_reg2(0),
      I4 => \FSM_sequential_fsm_reg_n_0_[1]\,
      O => \FSM_sequential_fsm[2]_i_1_n_0\
    );
\FSM_sequential_fsm_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_sequential_fsm[0]_i_1_n_0\,
      Q => \^pipe_qrst_fsm\(0),
      R => reset_n_reg2_reg
    );
\FSM_sequential_fsm_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_sequential_fsm[1]_i_1_n_0\,
      Q => \FSM_sequential_fsm_reg_n_0_[1]\,
      R => reset_n_reg2_reg
    );
\FSM_sequential_fsm_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_sequential_fsm[2]_i_1_n_0\,
      Q => \FSM_sequential_fsm_reg_n_0_[2]\,
      R => reset_n_reg2_reg
    );
\cplllock_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\(0),
      Q => cplllock_reg1(0),
      S => reset_n_reg2_reg
    );
\cplllock_reg1_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\(1),
      Q => cplllock_reg1(1),
      S => reset_n_reg2_reg
    );
\cplllock_reg1_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\(2),
      Q => cplllock_reg1(2),
      S => reset_n_reg2_reg
    );
\cplllock_reg1_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\(3),
      Q => cplllock_reg1(3),
      S => reset_n_reg2_reg
    );
\cplllock_reg1_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\(4),
      Q => cplllock_reg1(4),
      S => reset_n_reg2_reg
    );
\cplllock_reg1_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\(5),
      Q => cplllock_reg1(5),
      S => reset_n_reg2_reg
    );
\cplllock_reg1_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\(6),
      Q => cplllock_reg1(6),
      S => reset_n_reg2_reg
    );
\cplllock_reg1_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]\(7),
      Q => cplllock_reg1(7),
      S => reset_n_reg2_reg
    );
\cplllock_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(0),
      Q => cplllock_reg2(0),
      S => reset_n_reg2_reg
    );
\cplllock_reg2_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(1),
      Q => cplllock_reg2(1),
      S => reset_n_reg2_reg
    );
\cplllock_reg2_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(2),
      Q => cplllock_reg2(2),
      S => reset_n_reg2_reg
    );
\cplllock_reg2_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(3),
      Q => cplllock_reg2(3),
      S => reset_n_reg2_reg
    );
\cplllock_reg2_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(4),
      Q => cplllock_reg2(4),
      S => reset_n_reg2_reg
    );
\cplllock_reg2_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(5),
      Q => cplllock_reg2(5),
      S => reset_n_reg2_reg
    );
\cplllock_reg2_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(6),
      Q => cplllock_reg2(6),
      S => reset_n_reg2_reg
    );
\cplllock_reg2_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => cplllock_reg1(7),
      Q => cplllock_reg2(7),
      S => reset_n_reg2_reg
    );
\drp_done_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => done_reg(0),
      Q => drp_done_reg1(0),
      R => reset_n_reg2_reg
    );
\drp_done_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => done_reg(1),
      Q => drp_done_reg1(1),
      R => reset_n_reg2_reg
    );
\drp_done_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => drp_done_reg1(0),
      Q => drp_done_reg2(0),
      R => reset_n_reg2_reg
    );
\drp_done_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => drp_done_reg1(1),
      Q => drp_done_reg2(1),
      R => reset_n_reg2_reg
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \resetovrd_disble.reset_reg[4]_0\,
      Q => mmcm_lock_reg1,
      R => reset_n_reg2_reg
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => reset_n_reg2_reg
    );
ovrd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \^qrst_ovrd\,
      Q => \^qrst_ovrd\,
      R => reset_n_reg2_reg
    );
\pipe_qrst_fsm[1]_INST_0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_sequential_fsm_reg_n_0_[1]\,
      O => \^pipe_qrst_fsm\(1)
    );
\pipe_qrst_fsm[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"5C"
    )
        port map (
      I0 => \^pipe_qrst_fsm\(0),
      I1 => \FSM_sequential_fsm_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_reg_n_0_[2]\,
      O => \^pipe_qrst_fsm\(2)
    );
\pipe_qrst_fsm[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \^pipe_qrst_fsm\(0),
      I1 => \FSM_sequential_fsm_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_reg_n_0_[2]\,
      O => \^pipe_qrst_fsm\(3)
    );
pipe_qrst_idle_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \FSM_sequential_fsm_reg_n_0_[1]\,
      I1 => \^pipe_qrst_fsm\(0),
      I2 => \FSM_sequential_fsm_reg_n_0_[2]\,
      O => pipe_qrst_idle
    );
\qplllock_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_reg_1,
      Q => qplllock_reg1(0),
      R => reset_n_reg2_reg
    );
\qplllock_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_reg_0,
      Q => qplllock_reg1(1),
      R => reset_n_reg2_reg
    );
\qplllock_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qplllock_reg1(0),
      Q => qplllock_reg2(0),
      R => reset_n_reg2_reg
    );
\qplllock_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qplllock_reg1(1),
      Q => qplllock_reg2(1),
      R => reset_n_reg2_reg
    );
qpllpd_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFFFFFB8000000"
    )
        port map (
      I0 => qpllpd_i_2_n_0,
      I1 => \^pipe_qrst_fsm\(0),
      I2 => qpllreset_i_2_n_0,
      I3 => \FSM_sequential_fsm_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_reg_n_0_[1]\,
      I5 => \^qpllpd\,
      O => qpllpd_i_1_n_0
    );
qpllpd_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => qpllpd_i_3_n_0,
      I1 => qpllpd_in_reg2(4),
      I2 => qpllpd_in_reg2(5),
      O => qpllpd_i_2_n_0
    );
qpllpd_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => qpllpd_in_reg2(6),
      I1 => qpllpd_in_reg2(7),
      I2 => qpllpd_in_reg2(1),
      I3 => qpllpd_in_reg2(0),
      I4 => qpllpd_in_reg2(3),
      I5 => qpllpd_in_reg2(2),
      O => qpllpd_i_3_n_0
    );
\qpllpd_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(0),
      Q => qpllpd_in_reg1(0),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(1),
      Q => qpllpd_in_reg1(1),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(2),
      Q => qpllpd_in_reg1(2),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(3),
      Q => qpllpd_in_reg1(3),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(4),
      Q => qpllpd_in_reg1(4),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(5),
      Q => qpllpd_in_reg1(5),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(6),
      Q => qpllpd_in_reg1(6),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => D(7),
      Q => qpllpd_in_reg1(7),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_in_reg1(0),
      Q => qpllpd_in_reg2(0),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_in_reg1(1),
      Q => qpllpd_in_reg2(1),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_in_reg1(2),
      Q => qpllpd_in_reg2(2),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_in_reg1(3),
      Q => qpllpd_in_reg2(3),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_in_reg1(4),
      Q => qpllpd_in_reg2(4),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_in_reg1(5),
      Q => qpllpd_in_reg2(5),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_in_reg1(6),
      Q => qpllpd_in_reg2(6),
      R => reset_n_reg2_reg
    );
\qpllpd_in_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_in_reg1(7),
      Q => qpllpd_in_reg2(7),
      R => reset_n_reg2_reg
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllpd_i_1_n_0,
      Q => \^qpllpd\,
      R => reset_n_reg2_reg
    );
qpllreset_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CAF0FFFFCA000000"
    )
        port map (
      I0 => qpllreset_i_2_n_0,
      I1 => qpllreset_i_3_n_0,
      I2 => \FSM_sequential_fsm_reg_n_0_[1]\,
      I3 => \^pipe_qrst_fsm\(0),
      I4 => \FSM_sequential_fsm_reg_n_0_[2]\,
      I5 => \^qrst_qpllreset\,
      O => qpllreset_i_1_n_0
    );
qpllreset_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => qpllreset_i_2_n_0
    );
qpllreset_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => qpllreset_i_4_n_0,
      I1 => qpllreset_in_reg2(4),
      I2 => qpllreset_in_reg2(5),
      O => qpllreset_i_3_n_0
    );
qpllreset_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => qpllreset_in_reg2(6),
      I1 => qpllreset_in_reg2(7),
      I2 => qpllreset_in_reg2(1),
      I3 => qpllreset_in_reg2(0),
      I4 => qpllreset_in_reg2(3),
      I5 => qpllreset_in_reg2(2),
      O => qpllreset_i_4_n_0
    );
\qpllreset_in_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_reg_0(0),
      Q => qpllreset_in_reg1(0),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg1_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_reg_0(1),
      Q => qpllreset_in_reg1(1),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg1_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_reg_0(2),
      Q => qpllreset_in_reg1(2),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg1_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_reg_0(3),
      Q => qpllreset_in_reg1(3),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg1_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_reg_0(4),
      Q => qpllreset_in_reg1(4),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg1_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_reg_0(5),
      Q => qpllreset_in_reg1(5),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg1_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_reg_0(6),
      Q => qpllreset_in_reg1(6),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg1_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_reg_0(7),
      Q => qpllreset_in_reg1(7),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_in_reg1(0),
      Q => qpllreset_in_reg2(0),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg2_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_in_reg1(1),
      Q => qpllreset_in_reg2(1),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg2_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_in_reg1(2),
      Q => qpllreset_in_reg2(2),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg2_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_in_reg1(3),
      Q => qpllreset_in_reg2(3),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg2_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_in_reg1(4),
      Q => qpllreset_in_reg2(4),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg2_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_in_reg1(5),
      Q => qpllreset_in_reg2(5),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg2_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_in_reg1(6),
      Q => qpllreset_in_reg2(6),
      S => reset_n_reg2_reg
    );
\qpllreset_in_reg2_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_in_reg1(7),
      Q => qpllreset_in_reg2(7),
      S => reset_n_reg2_reg
    );
qpllreset_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => qpllreset_i_1_n_0,
      Q => \^qrst_qpllreset\,
      S => reset_n_reg2_reg
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      Q => rate_reg1(0),
      R => reset_n_reg2_reg
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => reset_n_reg2_reg
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => reset_n_reg2_reg
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => reset_n_reg2_reg
    );
\start_reg1_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \FSM_sequential_fsm_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_reg_n_0_[1]\,
      I2 => \^pipe_qrst_fsm\(0),
      O => start_reg1_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper is
  port (
    qpll_drp_rdy : out STD_LOGIC;
    RATE_QPLLLOCK : out STD_LOGIC;
    \cplllock_reg1_reg[7]\ : out STD_LOGIC;
    \cplllock_reg1_reg[7]_0\ : out STD_LOGIC;
    DRP_DO : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    qpll_drp_en : in STD_LOGIC;
    qpll_drp_we : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    qpllpd : in STD_LOGIC;
    QPLL_QPLLRESET0 : in STD_LOGIC;
    DRP_DI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_ADDR : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper : entity is "PCIeGen1x8If64_qpll_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper is
  signal \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_common.gtxe2_common_i\ : label is "PRIMITIVE";
begin
\gtx_common.gtxe2_common_i\: unisim.vcomponents.GTXE2_COMMON
    generic map(
      BIAS_CFG => X"0000040000001000",
      COMMON_CFG => X"00000000",
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_QPLLLOCKDETCLK_INVERTED => '0',
      QPLL_CFG => X"06801C1",
      QPLL_CLKOUT_CFG => B"0000",
      QPLL_COARSE_FREQ_OVRD => B"010000",
      QPLL_COARSE_FREQ_OVRD_EN => '0',
      QPLL_CP => B"0000011111",
      QPLL_CP_MONITOR_EN => '0',
      QPLL_DMONITOR_SEL => '0',
      QPLL_FBDIV => B"0100100000",
      QPLL_FBDIV_MONITOR_EN => '0',
      QPLL_FBDIV_RATIO => '1',
      QPLL_INIT_CFG => X"000006",
      QPLL_LOCK_CFG => X"21E8",
      QPLL_LPF => B"1101",
      QPLL_REFCLK_DIV => 1,
      SIM_QPLLREFCLK_SEL => B"001",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_VERSION => "3.0"
    )
        port map (
      BGBYPASSB => '1',
      BGMONITORENB => '1',
      BGPDB => '1',
      BGRCALOVRD(4) => '1',
      BGRCALOVRD(3) => '1',
      BGRCALOVRD(2) => '1',
      BGRCALOVRD(1) => '1',
      BGRCALOVRD(0) => '1',
      DRPADDR(7 downto 0) => DRP_ADDR(7 downto 0),
      DRPCLK => \resetovrd_disble.reset_reg[4]\,
      DRPDI(15 downto 0) => DRP_DI(15 downto 0),
      DRPDO(15 downto 0) => DRP_DO(15 downto 0),
      DRPEN => qpll_drp_en,
      DRPRDY => qpll_drp_rdy,
      DRPWE => qpll_drp_we,
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      PMARSVD(7) => '0',
      PMARSVD(6) => '0',
      PMARSVD(5) => '0',
      PMARSVD(4) => '0',
      PMARSVD(3) => '0',
      PMARSVD(2) => '0',
      PMARSVD(1) => '0',
      PMARSVD(0) => '0',
      QPLLDMONITOR(7 downto 0) => \NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED\(7 downto 0),
      QPLLFBCLKLOST => \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED\,
      QPLLLOCK => RATE_QPLLLOCK,
      QPLLLOCKDETCLK => '0',
      QPLLLOCKEN => '1',
      QPLLOUTCLK => \cplllock_reg1_reg[7]\,
      QPLLOUTREFCLK => \cplllock_reg1_reg[7]_0\,
      QPLLOUTRESET => '0',
      QPLLPD => qpllpd,
      QPLLREFCLKLOST => \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED\,
      QPLLREFCLKSEL(2) => '0',
      QPLLREFCLKSEL(1) => '0',
      QPLLREFCLKSEL(0) => '1',
      QPLLRESET => QPLL_QPLLRESET0,
      QPLLRSVD1(15) => '0',
      QPLLRSVD1(14) => '0',
      QPLLRSVD1(13) => '0',
      QPLLRSVD1(12) => '0',
      QPLLRSVD1(11) => '0',
      QPLLRSVD1(10) => '0',
      QPLLRSVD1(9) => '0',
      QPLLRSVD1(8) => '0',
      QPLLRSVD1(7) => '0',
      QPLLRSVD1(6) => '0',
      QPLLRSVD1(5) => '0',
      QPLLRSVD1(4) => '0',
      QPLLRSVD1(3) => '0',
      QPLLRSVD1(2) => '0',
      QPLLRSVD1(1) => '0',
      QPLLRSVD1(0) => '0',
      QPLLRSVD2(4) => '1',
      QPLLRSVD2(3) => '1',
      QPLLRSVD2(2) => '1',
      QPLLRSVD2(1) => '1',
      QPLLRSVD2(0) => '1',
      RCALENB => '1',
      REFCLKOUTMONITOR => \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper_85 is
  port (
    qpll_drp_rdy : out STD_LOGIC;
    RATE_QPLLLOCK : out STD_LOGIC;
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    \cplllock_reg1_reg[3]_0\ : out STD_LOGIC;
    DRP_DO : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    qpll_drp_en : in STD_LOGIC;
    qpll_drp_we : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    qpllpd : in STD_LOGIC;
    QPLL_QPLLRESET0126_out : in STD_LOGIC;
    DRP_DI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    DRP_ADDR : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper_85 : entity is "PCIeGen1x8If64_qpll_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper_85;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper_85 is
  signal \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_common.gtxe2_common_i\ : label is "PRIMITIVE";
begin
\gtx_common.gtxe2_common_i\: unisim.vcomponents.GTXE2_COMMON
    generic map(
      BIAS_CFG => X"0000040000001000",
      COMMON_CFG => X"00000000",
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_QPLLLOCKDETCLK_INVERTED => '0',
      QPLL_CFG => X"06801C1",
      QPLL_CLKOUT_CFG => B"0000",
      QPLL_COARSE_FREQ_OVRD => B"010000",
      QPLL_COARSE_FREQ_OVRD_EN => '0',
      QPLL_CP => B"0000011111",
      QPLL_CP_MONITOR_EN => '0',
      QPLL_DMONITOR_SEL => '0',
      QPLL_FBDIV => B"0100100000",
      QPLL_FBDIV_MONITOR_EN => '0',
      QPLL_FBDIV_RATIO => '1',
      QPLL_INIT_CFG => X"000006",
      QPLL_LOCK_CFG => X"21E8",
      QPLL_LPF => B"1101",
      QPLL_REFCLK_DIV => 1,
      SIM_QPLLREFCLK_SEL => B"001",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_VERSION => "3.0"
    )
        port map (
      BGBYPASSB => '1',
      BGMONITORENB => '1',
      BGPDB => '1',
      BGRCALOVRD(4) => '1',
      BGRCALOVRD(3) => '1',
      BGRCALOVRD(2) => '1',
      BGRCALOVRD(1) => '1',
      BGRCALOVRD(0) => '1',
      DRPADDR(7 downto 0) => DRP_ADDR(7 downto 0),
      DRPCLK => \resetovrd_disble.reset_reg[4]\,
      DRPDI(15 downto 0) => DRP_DI(15 downto 0),
      DRPDO(15 downto 0) => DRP_DO(15 downto 0),
      DRPEN => qpll_drp_en,
      DRPRDY => qpll_drp_rdy,
      DRPWE => qpll_drp_we,
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      PMARSVD(7) => '0',
      PMARSVD(6) => '0',
      PMARSVD(5) => '0',
      PMARSVD(4) => '0',
      PMARSVD(3) => '0',
      PMARSVD(2) => '0',
      PMARSVD(1) => '0',
      PMARSVD(0) => '0',
      QPLLDMONITOR(7 downto 0) => \NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED\(7 downto 0),
      QPLLFBCLKLOST => \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED\,
      QPLLLOCK => RATE_QPLLLOCK,
      QPLLLOCKDETCLK => '0',
      QPLLLOCKEN => '1',
      QPLLOUTCLK => \cplllock_reg1_reg[3]\,
      QPLLOUTREFCLK => \cplllock_reg1_reg[3]_0\,
      QPLLOUTRESET => '0',
      QPLLPD => qpllpd,
      QPLLREFCLKLOST => \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED\,
      QPLLREFCLKSEL(2) => '0',
      QPLLREFCLKSEL(1) => '0',
      QPLLREFCLKSEL(0) => '1',
      QPLLRESET => QPLL_QPLLRESET0126_out,
      QPLLRSVD1(15) => '0',
      QPLLRSVD1(14) => '0',
      QPLLRSVD1(13) => '0',
      QPLLRSVD1(12) => '0',
      QPLLRSVD1(11) => '0',
      QPLLRSVD1(10) => '0',
      QPLLRSVD1(9) => '0',
      QPLLRSVD1(8) => '0',
      QPLLRSVD1(7) => '0',
      QPLLRSVD1(6) => '0',
      QPLLRSVD1(5) => '0',
      QPLLRSVD1(4) => '0',
      QPLLRSVD1(3) => '0',
      QPLLRSVD1(2) => '0',
      QPLLRSVD1(1) => '0',
      QPLLRSVD1(0) => '0',
      QPLLRSVD2(4) => '1',
      QPLLRSVD2(3) => '1',
      QPLLRSVD2(2) => '1',
      QPLLRSVD2(1) => '1',
      QPLLRSVD2(0) => '1',
      RCALENB => '1',
      REFCLKOUTMONITOR => \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req_reg : out STD_LOGIC;
    rxeq_adapt_done_reg : out STD_LOGIC;
    rxeq_adapt_done_reg_reg : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    rxeq_new_txcoeff_req_reg_0 : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rxeq_preset_valid_reg : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_sequential_fsm_rx_reg[0]\ : in STD_LOGIC;
    \rxeq_cnt_reg[1]\ : in STD_LOGIC;
    \FSM_sequential_fsm_rx_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rxeq_cnt_reg[1]_0\ : in STD_LOGIC;
    \rxeq_control_reg2_reg[0]\ : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    \rxeq_preset_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rxeq_txcoeff_reg[17]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \rxeq_fs_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rxeq_lf_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan : entity is "PCIeGen1x8If64_rxeq_scan";
end PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan is
  signal \FSM_onehot_fsm[1]_i_1__7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2__7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_3__7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_4__7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_5__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_7__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_8__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3__7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[4]\ : signal is "yes";
  signal adapt_done : STD_LOGIC;
  signal adapt_done_cnt : STD_LOGIC;
  signal \adapt_done_cnt_i_1__6_n_0\ : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt[11]_i_3__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_4__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_5__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_6__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_3__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_4__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_5__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_6__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_3__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_4__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_5__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_6__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_3__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_4__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_3__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_4__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_5__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_6__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_3__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_4__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_5__6_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_6__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__6_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__6_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__6_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__6_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__6_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__6_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__6_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__6_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__6_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_2__6_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__6_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__6_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__6_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__6_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__6_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__6_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[16]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[17]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[18]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[19]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[20]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[21]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  signal preset_done : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_valid_reg1 : STD_LOGIC;
  signal preset_valid_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg0 : STD_LOGIC;
  signal \rxeq_adapt_done_reg_i_2__6_n_0\ : STD_LOGIC;
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal rxeqscan_preset_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[4]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute ASYNC_REG of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rxeq_adapt_done_i_2__6\ : label is "soft_lutpair201";
  attribute SOFT_HLUTNM of \rxeq_adapt_done_reg_i_1__6\ : label is "soft_lutpair201";
  attribute ASYNC_REG of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
begin
\FSM_onehot_fsm[1]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000073333FF07"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => preset_valid_reg2,
      O => \FSM_onehot_fsm[1]_i_1__7_n_0\
    );
\FSM_onehot_fsm[2]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__7_n_0\
    );
\FSM_onehot_fsm[3]_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA8A8AA"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2__7_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_3__7_n_0\,
      I2 => \FSM_onehot_fsm[3]_i_4__7_n_0\,
      I3 => \converge_cnt_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm[3]_i_5__6_n_0\,
      O => \FSM_onehot_fsm[3]_i_1__7_n_0\
    );
\FSM_onehot_fsm[3]_i_2__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202020202F20"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => fsm1,
      I5 => \FSM_onehot_fsm_reg_n_0_[2]\,
      O => \FSM_onehot_fsm[3]_i_2__7_n_0\
    );
\FSM_onehot_fsm[3]_i_3__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6FFFFFFFF6FFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      I1 => \converge_cnt_reg_n_0_[2]\,
      I2 => \converge_cnt_reg_n_0_[10]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[20]\,
      O => \FSM_onehot_fsm[3]_i_3__7_n_0\
    );
\FSM_onehot_fsm[3]_i_4__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7E7EFFFF7EFF7E"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[8]\,
      I3 => \converge_cnt_reg_n_0_[21]\,
      I4 => \out\(0),
      I5 => \out\(1),
      O => \FSM_onehot_fsm[3]_i_4__7_n_0\
    );
\FSM_onehot_fsm[3]_i_5__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF9"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      I1 => \converge_cnt_reg_n_0_[21]\,
      I2 => \converge_cnt_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[7]\,
      I4 => \FSM_onehot_fsm[3]_i_7__6_n_0\,
      I5 => \FSM_onehot_fsm[3]_i_8__6_n_0\,
      O => \FSM_onehot_fsm[3]_i_5__6_n_0\
    );
\FSM_onehot_fsm[3]_i_6__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      O => fsm1
    );
\FSM_onehot_fsm[3]_i_7__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[16]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[3]_i_7__6_n_0\
    );
\FSM_onehot_fsm[3]_i_8__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFDFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      I1 => \converge_cnt_reg_n_0_[4]\,
      I2 => \converge_cnt_reg_n_0_[12]\,
      I3 => \converge_cnt_reg_n_0_[9]\,
      I4 => \converge_cnt_reg_n_0_[5]\,
      I5 => \converge_cnt_reg_n_0_[6]\,
      O => \FSM_onehot_fsm[3]_i_8__6_n_0\
    );
\FSM_onehot_fsm[4]_i_1__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm[4]_i_2__6_n_0\,
      O => \FSM_onehot_fsm[4]_i_1__7_n_0\
    );
\FSM_onehot_fsm[4]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3__7_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4__6_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_5__6_n_0\,
      I3 => \FSM_onehot_fsm[4]_i_6__6_n_0\,
      I4 => \FSM_onehot_fsm[4]_i_7__6_n_0\,
      I5 => \FSM_onehot_fsm[4]_i_8__6_n_0\,
      O => \FSM_onehot_fsm[4]_i_2__6_n_0\
    );
\FSM_onehot_fsm[4]_i_3__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02020202FF000000"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_3__7_n_0\
    );
\FSM_onehot_fsm[4]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00004B00004B0000"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \converge_cnt_reg_n_0_[21]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[10]\,
      O => \FSM_onehot_fsm[4]_i_4__6_n_0\
    );
\FSM_onehot_fsm[4]_i_5__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000810000810000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[8]\,
      I2 => \converge_cnt_reg_n_0_[3]\,
      I3 => \converge_cnt_reg_n_0_[20]\,
      I4 => \converge_cnt_reg_n_0_[21]\,
      I5 => \converge_cnt_reg_n_0_[14]\,
      O => \FSM_onehot_fsm[4]_i_5__6_n_0\
    );
\FSM_onehot_fsm[4]_i_6__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000024"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[0]\,
      I3 => \converge_cnt_reg_n_0_[5]\,
      I4 => \converge_cnt_reg_n_0_[4]\,
      O => \FSM_onehot_fsm[4]_i_6__6_n_0\
    );
\FSM_onehot_fsm[4]_i_7__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \converge_cnt_reg_n_0_[11]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[9]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[4]_i_7__6_n_0\
    );
\FSM_onehot_fsm[4]_i_8__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      I1 => \converge_cnt_reg_n_0_[6]\,
      I2 => \converge_cnt_reg_n_0_[16]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[19]\,
      I5 => \converge_cnt_reg_n_0_[7]\,
      O => \FSM_onehot_fsm[4]_i_8__6_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__7_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__7_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__7_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__7_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEEEEEE"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[0]\,
      I1 => \rxeq_cnt_reg[1]\,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      O => D(0)
    );
\FSM_sequential_fsm_rx[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0CAF0CA0FF000F00"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => \rxeq_cnt_reg[1]_0\,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \rxeq_control_reg2_reg[0]\,
      I5 => \FSM_sequential_fsm_rx_reg[2]\(0),
      O => D(1)
    );
\FSM_sequential_fsm_rx[2]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F083FC8330833C8"
    )
        port map (
      I0 => rxeqscan_preset_done,
      I1 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I4 => \rxeq_cnt_reg[1]_0\,
      I5 => \rxeq_control_reg2_reg[0]\,
      O => D(2)
    );
\adapt_done_cnt_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF2A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \out\(0),
      I2 => \out\(1),
      I3 => adapt_done_cnt,
      I4 => adapt_done_cnt_reg_n_0,
      O => \adapt_done_cnt_i_1__6_n_0\
    );
\adapt_done_cnt_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF444744444447"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => fsm1,
      O => adapt_done_cnt
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \adapt_done_cnt_i_1__6_n_0\,
      Q => adapt_done_cnt_reg_n_0,
      R => RST_CPLLRESET
    );
\adapt_done_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(1),
      I3 => \out\(0),
      I4 => new_txcoeff_req_reg2,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => RST_CPLLRESET
    );
\converge_cnt[0]_i_1__14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(0)
    );
\converge_cnt[10]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(10)
    );
\converge_cnt[11]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(11)
    );
\converge_cnt[11]_i_3__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      O => \converge_cnt[11]_i_3__6_n_0\
    );
\converge_cnt[11]_i_4__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      O => \converge_cnt[11]_i_4__6_n_0\
    );
\converge_cnt[11]_i_5__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[9]\,
      O => \converge_cnt[11]_i_5__6_n_0\
    );
\converge_cnt[11]_i_6__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[8]\,
      O => \converge_cnt[11]_i_6__6_n_0\
    );
\converge_cnt[12]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(12)
    );
\converge_cnt[13]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(13)
    );
\converge_cnt[14]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(14)
    );
\converge_cnt[15]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(15)
    );
\converge_cnt[15]_i_3__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[15]\,
      O => \converge_cnt[15]_i_3__6_n_0\
    );
\converge_cnt[15]_i_4__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[14]\,
      O => \converge_cnt[15]_i_4__6_n_0\
    );
\converge_cnt[15]_i_5__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[13]\,
      O => \converge_cnt[15]_i_5__6_n_0\
    );
\converge_cnt[15]_i_6__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      O => \converge_cnt[15]_i_6__6_n_0\
    );
\converge_cnt[16]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(16)
    );
\converge_cnt[17]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(17)
    );
\converge_cnt[18]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(18)
    );
\converge_cnt[19]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(19)
    );
\converge_cnt[19]_i_3__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      O => \converge_cnt[19]_i_3__6_n_0\
    );
\converge_cnt[19]_i_4__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[18]\,
      O => \converge_cnt[19]_i_4__6_n_0\
    );
\converge_cnt[19]_i_5__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[17]\,
      O => \converge_cnt[19]_i_5__6_n_0\
    );
\converge_cnt[19]_i_6__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[16]\,
      O => \converge_cnt[19]_i_6__6_n_0\
    );
\converge_cnt[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(1)
    );
\converge_cnt[20]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(20)
    );
\converge_cnt[21]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(21)
    );
\converge_cnt[21]_i_3__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[21]\,
      O => \converge_cnt[21]_i_3__6_n_0\
    );
\converge_cnt[21]_i_4__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      O => \converge_cnt[21]_i_4__6_n_0\
    );
\converge_cnt[2]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(2)
    );
\converge_cnt[3]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(3)
    );
\converge_cnt[3]_i_3__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[3]\,
      O => \converge_cnt[3]_i_3__6_n_0\
    );
\converge_cnt[3]_i_4__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      O => \converge_cnt[3]_i_4__6_n_0\
    );
\converge_cnt[3]_i_5__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      O => \converge_cnt[3]_i_5__6_n_0\
    );
\converge_cnt[3]_i_6__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      O => \converge_cnt[3]_i_6__6_n_0\
    );
\converge_cnt[4]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(4)
    );
\converge_cnt[5]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(5)
    );
\converge_cnt[6]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(6)
    );
\converge_cnt[7]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(7)
    );
\converge_cnt[7]_i_3__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[7]\,
      O => \converge_cnt[7]_i_3__6_n_0\
    );
\converge_cnt[7]_i_4__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[6]\,
      O => \converge_cnt[7]_i_4__6_n_0\
    );
\converge_cnt[7]_i_5__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[5]\,
      O => \converge_cnt[7]_i_5__6_n_0\
    );
\converge_cnt[7]_i_6__6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[4]\,
      O => \converge_cnt[7]_i_6__6_n_0\
    );
\converge_cnt[8]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(8)
    );
\converge_cnt[9]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(0),
      Q => \converge_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(10),
      Q => \converge_cnt_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(11),
      Q => \converge_cnt_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]_i_2__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[7]_i_2__6_n_0\,
      CO(3) => \converge_cnt_reg[11]_i_2__6_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__6_n_1\,
      CO(1) => \converge_cnt_reg[11]_i_2__6_n_2\,
      CO(0) => \converge_cnt_reg[11]_i_2__6_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(11 downto 8),
      S(3) => \converge_cnt[11]_i_3__6_n_0\,
      S(2) => \converge_cnt[11]_i_4__6_n_0\,
      S(1) => \converge_cnt[11]_i_5__6_n_0\,
      S(0) => \converge_cnt[11]_i_6__6_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(12),
      Q => \converge_cnt_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(13),
      Q => \converge_cnt_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(14),
      Q => \converge_cnt_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(15),
      Q => \converge_cnt_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]_i_2__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[11]_i_2__6_n_0\,
      CO(3) => \converge_cnt_reg[15]_i_2__6_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__6_n_1\,
      CO(1) => \converge_cnt_reg[15]_i_2__6_n_2\,
      CO(0) => \converge_cnt_reg[15]_i_2__6_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(15 downto 12),
      S(3) => \converge_cnt[15]_i_3__6_n_0\,
      S(2) => \converge_cnt[15]_i_4__6_n_0\,
      S(1) => \converge_cnt[15]_i_5__6_n_0\,
      S(0) => \converge_cnt[15]_i_6__6_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(16),
      Q => \converge_cnt_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(17),
      Q => \converge_cnt_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(18),
      Q => \converge_cnt_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(19),
      Q => \converge_cnt_reg_n_0_[19]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]_i_2__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[15]_i_2__6_n_0\,
      CO(3) => \converge_cnt_reg[19]_i_2__6_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__6_n_1\,
      CO(1) => \converge_cnt_reg[19]_i_2__6_n_2\,
      CO(0) => \converge_cnt_reg[19]_i_2__6_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(19 downto 16),
      S(3) => \converge_cnt[19]_i_3__6_n_0\,
      S(2) => \converge_cnt[19]_i_4__6_n_0\,
      S(1) => \converge_cnt[19]_i_5__6_n_0\,
      S(0) => \converge_cnt[19]_i_6__6_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(1),
      Q => \converge_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(20),
      Q => \converge_cnt_reg_n_0_[20]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(21),
      Q => \converge_cnt_reg_n_0_[21]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]_i_2__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[19]_i_2__6_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__6_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[21]_i_2__6_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__6_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => converge_cnt0(21 downto 20),
      S(3) => '0',
      S(2) => '0',
      S(1) => \converge_cnt[21]_i_3__6_n_0\,
      S(0) => \converge_cnt[21]_i_4__6_n_0\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(2),
      Q => \converge_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(3),
      Q => \converge_cnt_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]_i_2__6\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[3]_i_2__6_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__6_n_1\,
      CO(1) => \converge_cnt_reg[3]_i_2__6_n_2\,
      CO(0) => \converge_cnt_reg[3]_i_2__6_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => \converge_cnt_reg_n_0_[0]\,
      O(3 downto 0) => converge_cnt0(3 downto 0),
      S(3) => \converge_cnt[3]_i_3__6_n_0\,
      S(2) => \converge_cnt[3]_i_4__6_n_0\,
      S(1) => \converge_cnt[3]_i_5__6_n_0\,
      S(0) => \converge_cnt[3]_i_6__6_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(4),
      Q => \converge_cnt_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(5),
      Q => \converge_cnt_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(6),
      Q => \converge_cnt_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(7),
      Q => \converge_cnt_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]_i_2__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[3]_i_2__6_n_0\,
      CO(3) => \converge_cnt_reg[7]_i_2__6_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__6_n_1\,
      CO(1) => \converge_cnt_reg[7]_i_2__6_n_2\,
      CO(0) => \converge_cnt_reg[7]_i_2__6_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(7 downto 4),
      S(3) => \converge_cnt[7]_i_3__6_n_0\,
      S(2) => \converge_cnt[7]_i_4__6_n_0\,
      S(1) => \converge_cnt[7]_i_5__6_n_0\,
      S(0) => \converge_cnt[7]_i_6__6_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(8),
      Q => \converge_cnt_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(9),
      Q => \converge_cnt_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(0),
      Q => fs_reg1(0),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(1),
      Q => fs_reg1(1),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(2),
      Q => fs_reg1(2),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(3),
      Q => fs_reg1(3),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(4),
      Q => fs_reg1(4),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(5),
      Q => fs_reg1(5),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(0),
      Q => lf_reg1(0),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(1),
      Q => lf_reg1(1),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(2),
      Q => lf_reg1(2),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(3),
      Q => lf_reg1(3),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(4),
      Q => lf_reg1(4),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(5),
      Q => lf_reg1(5),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => RST_CPLLRESET
    );
\new_txcoeff_done_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_new_txcoeff_req_reg_0,
      Q => new_txcoeff_req_reg1,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => RST_CPLLRESET
    );
\preset_done_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => preset_done
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_done,
      Q => rxeqscan_preset_done,
      R => RST_CPLLRESET
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(0),
      Q => preset_reg1(0),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(1),
      Q => preset_reg1(1),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(2),
      Q => preset_reg1(2),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => RST_CPLLRESET
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid_reg,
      Q => preset_valid_reg1,
      R => RST_CPLLRESET
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => RST_CPLLRESET
    );
\rxeq_adapt_done_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080F00000800000"
    )
        port map (
      I0 => rxeq_adapt_done_reg0,
      I1 => rxeqscan_new_txcoeff_done,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I5 => USER_RXEQ_ADAPT_DONE,
      O => rxeq_adapt_done_reg
    );
\rxeq_adapt_done_i_2__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg0
    );
\rxeq_adapt_done_reg_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44FF4000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => rxeqscan_adapt_done,
      I3 => \rxeq_adapt_done_reg_i_2__6_n_0\,
      I4 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg_reg
    );
\rxeq_adapt_done_reg_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0002FF000002F"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I5 => rxeqscan_new_txcoeff_done,
      O => \rxeq_adapt_done_reg_i_2__6_n_0\
    );
\rxeq_new_txcoeff_req_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I3 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req_reg
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(0),
      Q => txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(10),
      Q => txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(11),
      Q => txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(12),
      Q => txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(13),
      Q => txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(14),
      Q => txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(15),
      Q => txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(16),
      Q => txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(17),
      Q => txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(1),
      Q => txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(2),
      Q => txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(3),
      Q => txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(4),
      Q => txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(5),
      Q => txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(6),
      Q => txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(7),
      Q => txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(8),
      Q => txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(9),
      Q => txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(0),
      Q => txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(1),
      Q => txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(2),
      Q => txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(3),
      Q => txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_72 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req_reg : out STD_LOGIC;
    rxeq_adapt_done_reg : out STD_LOGIC;
    rxeq_adapt_done_reg_reg : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    rxeq_new_txcoeff_req_reg_0 : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rxeq_preset_valid_reg : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_sequential_fsm_rx_reg[0]\ : in STD_LOGIC;
    \rxeq_cnt_reg[1]\ : in STD_LOGIC;
    \FSM_sequential_fsm_rx_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rxeq_cnt_reg[1]_0\ : in STD_LOGIC;
    \rxeq_control_reg2_reg[0]\ : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    \rxeq_preset_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rxeq_txcoeff_reg[17]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \rxeq_fs_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rxeq_lf_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_72 : entity is "PCIeGen1x8If64_rxeq_scan";
end PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_72;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_72 is
  signal \FSM_onehot_fsm[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_3__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_4__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_5__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_7__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_8__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[4]\ : signal is "yes";
  signal adapt_done : STD_LOGIC;
  signal adapt_done_cnt : STD_LOGIC;
  signal \adapt_done_cnt_i_1__5_n_0\ : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt[11]_i_3__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_4__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_5__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_6__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_3__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_4__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_5__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_6__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_3__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_4__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_5__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_6__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_3__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_4__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_3__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_4__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_5__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_6__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_3__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_4__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_5__5_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_6__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__5_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__5_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__5_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__5_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__5_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__5_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__5_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__5_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__5_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_2__5_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__5_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__5_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__5_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__5_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__5_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__5_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__5_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[16]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[17]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[18]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[19]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[20]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[21]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  signal preset_done : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_valid_reg1 : STD_LOGIC;
  signal preset_valid_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg0 : STD_LOGIC;
  signal \rxeq_adapt_done_reg_i_2__5_n_0\ : STD_LOGIC;
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal rxeqscan_preset_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[4]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute ASYNC_REG of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rxeq_adapt_done_i_2__5\ : label is "soft_lutpair177";
  attribute SOFT_HLUTNM of \rxeq_adapt_done_reg_i_1__5\ : label is "soft_lutpair177";
  attribute ASYNC_REG of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
begin
\FSM_onehot_fsm[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000073333FF07"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => preset_valid_reg2,
      O => \FSM_onehot_fsm[1]_i_1__6_n_0\
    );
\FSM_onehot_fsm[2]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__6_n_0\
    );
\FSM_onehot_fsm[3]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA8A8AA"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2__6_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_3__6_n_0\,
      I2 => \FSM_onehot_fsm[3]_i_4__6_n_0\,
      I3 => \converge_cnt_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm[3]_i_5__5_n_0\,
      O => \FSM_onehot_fsm[3]_i_1__6_n_0\
    );
\FSM_onehot_fsm[3]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202020202F20"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => fsm1,
      I5 => \FSM_onehot_fsm_reg_n_0_[2]\,
      O => \FSM_onehot_fsm[3]_i_2__6_n_0\
    );
\FSM_onehot_fsm[3]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6FFFFFFFF6FFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      I1 => \converge_cnt_reg_n_0_[2]\,
      I2 => \converge_cnt_reg_n_0_[10]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[20]\,
      O => \FSM_onehot_fsm[3]_i_3__6_n_0\
    );
\FSM_onehot_fsm[3]_i_4__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7E7EFFFF7EFF7E"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[8]\,
      I3 => \converge_cnt_reg_n_0_[21]\,
      I4 => \out\(0),
      I5 => \out\(1),
      O => \FSM_onehot_fsm[3]_i_4__6_n_0\
    );
\FSM_onehot_fsm[3]_i_5__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF9"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      I1 => \converge_cnt_reg_n_0_[21]\,
      I2 => \converge_cnt_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[7]\,
      I4 => \FSM_onehot_fsm[3]_i_7__5_n_0\,
      I5 => \FSM_onehot_fsm[3]_i_8__5_n_0\,
      O => \FSM_onehot_fsm[3]_i_5__5_n_0\
    );
\FSM_onehot_fsm[3]_i_6__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      O => fsm1
    );
\FSM_onehot_fsm[3]_i_7__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[16]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[3]_i_7__5_n_0\
    );
\FSM_onehot_fsm[3]_i_8__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFDFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      I1 => \converge_cnt_reg_n_0_[4]\,
      I2 => \converge_cnt_reg_n_0_[12]\,
      I3 => \converge_cnt_reg_n_0_[9]\,
      I4 => \converge_cnt_reg_n_0_[5]\,
      I5 => \converge_cnt_reg_n_0_[6]\,
      O => \FSM_onehot_fsm[3]_i_8__5_n_0\
    );
\FSM_onehot_fsm[4]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm[4]_i_2__5_n_0\,
      O => \FSM_onehot_fsm[4]_i_1__6_n_0\
    );
\FSM_onehot_fsm[4]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3__6_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4__5_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_5__5_n_0\,
      I3 => \FSM_onehot_fsm[4]_i_6__5_n_0\,
      I4 => \FSM_onehot_fsm[4]_i_7__5_n_0\,
      I5 => \FSM_onehot_fsm[4]_i_8__5_n_0\,
      O => \FSM_onehot_fsm[4]_i_2__5_n_0\
    );
\FSM_onehot_fsm[4]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02020202FF000000"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_3__6_n_0\
    );
\FSM_onehot_fsm[4]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00004B00004B0000"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \converge_cnt_reg_n_0_[21]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[10]\,
      O => \FSM_onehot_fsm[4]_i_4__5_n_0\
    );
\FSM_onehot_fsm[4]_i_5__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000810000810000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[8]\,
      I2 => \converge_cnt_reg_n_0_[3]\,
      I3 => \converge_cnt_reg_n_0_[20]\,
      I4 => \converge_cnt_reg_n_0_[21]\,
      I5 => \converge_cnt_reg_n_0_[14]\,
      O => \FSM_onehot_fsm[4]_i_5__5_n_0\
    );
\FSM_onehot_fsm[4]_i_6__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000024"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[0]\,
      I3 => \converge_cnt_reg_n_0_[5]\,
      I4 => \converge_cnt_reg_n_0_[4]\,
      O => \FSM_onehot_fsm[4]_i_6__5_n_0\
    );
\FSM_onehot_fsm[4]_i_7__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \converge_cnt_reg_n_0_[11]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[9]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[4]_i_7__5_n_0\
    );
\FSM_onehot_fsm[4]_i_8__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      I1 => \converge_cnt_reg_n_0_[6]\,
      I2 => \converge_cnt_reg_n_0_[16]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[19]\,
      I5 => \converge_cnt_reg_n_0_[7]\,
      O => \FSM_onehot_fsm[4]_i_8__5_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__6_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__6_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__6_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__6_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEEEEEE"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[0]\,
      I1 => \rxeq_cnt_reg[1]\,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      O => D(0)
    );
\FSM_sequential_fsm_rx[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0CAF0CA0FF000F00"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => \rxeq_cnt_reg[1]_0\,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \rxeq_control_reg2_reg[0]\,
      I5 => \FSM_sequential_fsm_rx_reg[2]\(0),
      O => D(1)
    );
\FSM_sequential_fsm_rx[2]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F083FC8330833C8"
    )
        port map (
      I0 => rxeqscan_preset_done,
      I1 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I4 => \rxeq_cnt_reg[1]_0\,
      I5 => \rxeq_control_reg2_reg[0]\,
      O => D(2)
    );
\adapt_done_cnt_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF2A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \out\(0),
      I2 => \out\(1),
      I3 => adapt_done_cnt,
      I4 => adapt_done_cnt_reg_n_0,
      O => \adapt_done_cnt_i_1__5_n_0\
    );
\adapt_done_cnt_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF444744444447"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => fsm1,
      O => adapt_done_cnt
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \adapt_done_cnt_i_1__5_n_0\,
      Q => adapt_done_cnt_reg_n_0,
      R => RST_CPLLRESET
    );
\adapt_done_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(1),
      I3 => \out\(0),
      I4 => new_txcoeff_req_reg2,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => RST_CPLLRESET
    );
\converge_cnt[0]_i_1__13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(0)
    );
\converge_cnt[10]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(10)
    );
\converge_cnt[11]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(11)
    );
\converge_cnt[11]_i_3__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      O => \converge_cnt[11]_i_3__5_n_0\
    );
\converge_cnt[11]_i_4__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      O => \converge_cnt[11]_i_4__5_n_0\
    );
\converge_cnt[11]_i_5__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[9]\,
      O => \converge_cnt[11]_i_5__5_n_0\
    );
\converge_cnt[11]_i_6__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[8]\,
      O => \converge_cnt[11]_i_6__5_n_0\
    );
\converge_cnt[12]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(12)
    );
\converge_cnt[13]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(13)
    );
\converge_cnt[14]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(14)
    );
\converge_cnt[15]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(15)
    );
\converge_cnt[15]_i_3__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[15]\,
      O => \converge_cnt[15]_i_3__5_n_0\
    );
\converge_cnt[15]_i_4__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[14]\,
      O => \converge_cnt[15]_i_4__5_n_0\
    );
\converge_cnt[15]_i_5__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[13]\,
      O => \converge_cnt[15]_i_5__5_n_0\
    );
\converge_cnt[15]_i_6__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      O => \converge_cnt[15]_i_6__5_n_0\
    );
\converge_cnt[16]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(16)
    );
\converge_cnt[17]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(17)
    );
\converge_cnt[18]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(18)
    );
\converge_cnt[19]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(19)
    );
\converge_cnt[19]_i_3__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      O => \converge_cnt[19]_i_3__5_n_0\
    );
\converge_cnt[19]_i_4__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[18]\,
      O => \converge_cnt[19]_i_4__5_n_0\
    );
\converge_cnt[19]_i_5__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[17]\,
      O => \converge_cnt[19]_i_5__5_n_0\
    );
\converge_cnt[19]_i_6__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[16]\,
      O => \converge_cnt[19]_i_6__5_n_0\
    );
\converge_cnt[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(1)
    );
\converge_cnt[20]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(20)
    );
\converge_cnt[21]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(21)
    );
\converge_cnt[21]_i_3__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[21]\,
      O => \converge_cnt[21]_i_3__5_n_0\
    );
\converge_cnt[21]_i_4__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      O => \converge_cnt[21]_i_4__5_n_0\
    );
\converge_cnt[2]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(2)
    );
\converge_cnt[3]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(3)
    );
\converge_cnt[3]_i_3__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[3]\,
      O => \converge_cnt[3]_i_3__5_n_0\
    );
\converge_cnt[3]_i_4__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      O => \converge_cnt[3]_i_4__5_n_0\
    );
\converge_cnt[3]_i_5__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      O => \converge_cnt[3]_i_5__5_n_0\
    );
\converge_cnt[3]_i_6__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      O => \converge_cnt[3]_i_6__5_n_0\
    );
\converge_cnt[4]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(4)
    );
\converge_cnt[5]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(5)
    );
\converge_cnt[6]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(6)
    );
\converge_cnt[7]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(7)
    );
\converge_cnt[7]_i_3__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[7]\,
      O => \converge_cnt[7]_i_3__5_n_0\
    );
\converge_cnt[7]_i_4__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[6]\,
      O => \converge_cnt[7]_i_4__5_n_0\
    );
\converge_cnt[7]_i_5__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[5]\,
      O => \converge_cnt[7]_i_5__5_n_0\
    );
\converge_cnt[7]_i_6__5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[4]\,
      O => \converge_cnt[7]_i_6__5_n_0\
    );
\converge_cnt[8]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(8)
    );
\converge_cnt[9]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(0),
      Q => \converge_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(10),
      Q => \converge_cnt_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(11),
      Q => \converge_cnt_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]_i_2__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[7]_i_2__5_n_0\,
      CO(3) => \converge_cnt_reg[11]_i_2__5_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__5_n_1\,
      CO(1) => \converge_cnt_reg[11]_i_2__5_n_2\,
      CO(0) => \converge_cnt_reg[11]_i_2__5_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(11 downto 8),
      S(3) => \converge_cnt[11]_i_3__5_n_0\,
      S(2) => \converge_cnt[11]_i_4__5_n_0\,
      S(1) => \converge_cnt[11]_i_5__5_n_0\,
      S(0) => \converge_cnt[11]_i_6__5_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(12),
      Q => \converge_cnt_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(13),
      Q => \converge_cnt_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(14),
      Q => \converge_cnt_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(15),
      Q => \converge_cnt_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]_i_2__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[11]_i_2__5_n_0\,
      CO(3) => \converge_cnt_reg[15]_i_2__5_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__5_n_1\,
      CO(1) => \converge_cnt_reg[15]_i_2__5_n_2\,
      CO(0) => \converge_cnt_reg[15]_i_2__5_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(15 downto 12),
      S(3) => \converge_cnt[15]_i_3__5_n_0\,
      S(2) => \converge_cnt[15]_i_4__5_n_0\,
      S(1) => \converge_cnt[15]_i_5__5_n_0\,
      S(0) => \converge_cnt[15]_i_6__5_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(16),
      Q => \converge_cnt_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(17),
      Q => \converge_cnt_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(18),
      Q => \converge_cnt_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(19),
      Q => \converge_cnt_reg_n_0_[19]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]_i_2__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[15]_i_2__5_n_0\,
      CO(3) => \converge_cnt_reg[19]_i_2__5_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__5_n_1\,
      CO(1) => \converge_cnt_reg[19]_i_2__5_n_2\,
      CO(0) => \converge_cnt_reg[19]_i_2__5_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(19 downto 16),
      S(3) => \converge_cnt[19]_i_3__5_n_0\,
      S(2) => \converge_cnt[19]_i_4__5_n_0\,
      S(1) => \converge_cnt[19]_i_5__5_n_0\,
      S(0) => \converge_cnt[19]_i_6__5_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(1),
      Q => \converge_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(20),
      Q => \converge_cnt_reg_n_0_[20]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(21),
      Q => \converge_cnt_reg_n_0_[21]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]_i_2__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[19]_i_2__5_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__5_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[21]_i_2__5_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__5_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => converge_cnt0(21 downto 20),
      S(3) => '0',
      S(2) => '0',
      S(1) => \converge_cnt[21]_i_3__5_n_0\,
      S(0) => \converge_cnt[21]_i_4__5_n_0\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(2),
      Q => \converge_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(3),
      Q => \converge_cnt_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]_i_2__5\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[3]_i_2__5_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__5_n_1\,
      CO(1) => \converge_cnt_reg[3]_i_2__5_n_2\,
      CO(0) => \converge_cnt_reg[3]_i_2__5_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => \converge_cnt_reg_n_0_[0]\,
      O(3 downto 0) => converge_cnt0(3 downto 0),
      S(3) => \converge_cnt[3]_i_3__5_n_0\,
      S(2) => \converge_cnt[3]_i_4__5_n_0\,
      S(1) => \converge_cnt[3]_i_5__5_n_0\,
      S(0) => \converge_cnt[3]_i_6__5_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(4),
      Q => \converge_cnt_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(5),
      Q => \converge_cnt_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(6),
      Q => \converge_cnt_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(7),
      Q => \converge_cnt_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]_i_2__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[3]_i_2__5_n_0\,
      CO(3) => \converge_cnt_reg[7]_i_2__5_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__5_n_1\,
      CO(1) => \converge_cnt_reg[7]_i_2__5_n_2\,
      CO(0) => \converge_cnt_reg[7]_i_2__5_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(7 downto 4),
      S(3) => \converge_cnt[7]_i_3__5_n_0\,
      S(2) => \converge_cnt[7]_i_4__5_n_0\,
      S(1) => \converge_cnt[7]_i_5__5_n_0\,
      S(0) => \converge_cnt[7]_i_6__5_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(8),
      Q => \converge_cnt_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(9),
      Q => \converge_cnt_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(0),
      Q => fs_reg1(0),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(1),
      Q => fs_reg1(1),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(2),
      Q => fs_reg1(2),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(3),
      Q => fs_reg1(3),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(4),
      Q => fs_reg1(4),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(5),
      Q => fs_reg1(5),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(0),
      Q => lf_reg1(0),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(1),
      Q => lf_reg1(1),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(2),
      Q => lf_reg1(2),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(3),
      Q => lf_reg1(3),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(4),
      Q => lf_reg1(4),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(5),
      Q => lf_reg1(5),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => RST_CPLLRESET
    );
\new_txcoeff_done_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_new_txcoeff_req_reg_0,
      Q => new_txcoeff_req_reg1,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => RST_CPLLRESET
    );
\preset_done_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => preset_done
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_done,
      Q => rxeqscan_preset_done,
      R => RST_CPLLRESET
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(0),
      Q => preset_reg1(0),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(1),
      Q => preset_reg1(1),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(2),
      Q => preset_reg1(2),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => RST_CPLLRESET
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid_reg,
      Q => preset_valid_reg1,
      R => RST_CPLLRESET
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => RST_CPLLRESET
    );
\rxeq_adapt_done_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080F00000800000"
    )
        port map (
      I0 => rxeq_adapt_done_reg0,
      I1 => rxeqscan_new_txcoeff_done,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I5 => USER_RXEQ_ADAPT_DONE,
      O => rxeq_adapt_done_reg
    );
\rxeq_adapt_done_i_2__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg0
    );
\rxeq_adapt_done_reg_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44FF4000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => rxeqscan_adapt_done,
      I3 => \rxeq_adapt_done_reg_i_2__5_n_0\,
      I4 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg_reg
    );
\rxeq_adapt_done_reg_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0002FF000002F"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I5 => rxeqscan_new_txcoeff_done,
      O => \rxeq_adapt_done_reg_i_2__5_n_0\
    );
\rxeq_new_txcoeff_req_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I3 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req_reg
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(0),
      Q => txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(10),
      Q => txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(11),
      Q => txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(12),
      Q => txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(13),
      Q => txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(14),
      Q => txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(15),
      Q => txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(16),
      Q => txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(17),
      Q => txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(1),
      Q => txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(2),
      Q => txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(3),
      Q => txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(4),
      Q => txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(5),
      Q => txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(6),
      Q => txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(7),
      Q => txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(8),
      Q => txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(9),
      Q => txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(0),
      Q => txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(1),
      Q => txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(2),
      Q => txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(3),
      Q => txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_74 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req_reg : out STD_LOGIC;
    rxeq_adapt_done_reg : out STD_LOGIC;
    rxeq_adapt_done_reg_reg : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    rxeq_new_txcoeff_req_reg_0 : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rxeq_preset_valid_reg : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_sequential_fsm_rx_reg[0]\ : in STD_LOGIC;
    \rxeq_cnt_reg[1]\ : in STD_LOGIC;
    \FSM_sequential_fsm_rx_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rxeq_cnt_reg[1]_0\ : in STD_LOGIC;
    \rxeq_control_reg2_reg[0]\ : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    \rxeq_preset_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rxeq_txcoeff_reg[17]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \rxeq_fs_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rxeq_lf_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_74 : entity is "PCIeGen1x8If64_rxeq_scan";
end PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_74;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_74 is
  signal \FSM_onehot_fsm[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_3__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_4__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_5__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_7__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_8__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[4]\ : signal is "yes";
  signal adapt_done : STD_LOGIC;
  signal adapt_done_cnt : STD_LOGIC;
  signal \adapt_done_cnt_i_1__4_n_0\ : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt[11]_i_3__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_4__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_5__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_6__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_3__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_4__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_5__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_6__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_3__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_4__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_5__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_6__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_3__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_4__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_3__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_4__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_5__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_6__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_3__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_4__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_5__4_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_6__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__4_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__4_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__4_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__4_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__4_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__4_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__4_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__4_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__4_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_2__4_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__4_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__4_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__4_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__4_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__4_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__4_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__4_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[16]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[17]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[18]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[19]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[20]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[21]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  signal preset_done : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_valid_reg1 : STD_LOGIC;
  signal preset_valid_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg0 : STD_LOGIC;
  signal \rxeq_adapt_done_reg_i_2__4_n_0\ : STD_LOGIC;
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal rxeqscan_preset_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[4]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute ASYNC_REG of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rxeq_adapt_done_i_2__4\ : label is "soft_lutpair155";
  attribute SOFT_HLUTNM of \rxeq_adapt_done_reg_i_1__4\ : label is "soft_lutpair155";
  attribute ASYNC_REG of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
begin
\FSM_onehot_fsm[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000073333FF07"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => preset_valid_reg2,
      O => \FSM_onehot_fsm[1]_i_1__5_n_0\
    );
\FSM_onehot_fsm[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__5_n_0\
    );
\FSM_onehot_fsm[3]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA8A8AA"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2__5_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_3__5_n_0\,
      I2 => \FSM_onehot_fsm[3]_i_4__5_n_0\,
      I3 => \converge_cnt_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm[3]_i_5__4_n_0\,
      O => \FSM_onehot_fsm[3]_i_1__5_n_0\
    );
\FSM_onehot_fsm[3]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202020202F20"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => fsm1,
      I5 => \FSM_onehot_fsm_reg_n_0_[2]\,
      O => \FSM_onehot_fsm[3]_i_2__5_n_0\
    );
\FSM_onehot_fsm[3]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6FFFFFFFF6FFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      I1 => \converge_cnt_reg_n_0_[2]\,
      I2 => \converge_cnt_reg_n_0_[10]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[20]\,
      O => \FSM_onehot_fsm[3]_i_3__5_n_0\
    );
\FSM_onehot_fsm[3]_i_4__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7E7EFFFF7EFF7E"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[8]\,
      I3 => \converge_cnt_reg_n_0_[21]\,
      I4 => \out\(0),
      I5 => \out\(1),
      O => \FSM_onehot_fsm[3]_i_4__5_n_0\
    );
\FSM_onehot_fsm[3]_i_5__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF9"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      I1 => \converge_cnt_reg_n_0_[21]\,
      I2 => \converge_cnt_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[7]\,
      I4 => \FSM_onehot_fsm[3]_i_7__4_n_0\,
      I5 => \FSM_onehot_fsm[3]_i_8__4_n_0\,
      O => \FSM_onehot_fsm[3]_i_5__4_n_0\
    );
\FSM_onehot_fsm[3]_i_6__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      O => fsm1
    );
\FSM_onehot_fsm[3]_i_7__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[16]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[3]_i_7__4_n_0\
    );
\FSM_onehot_fsm[3]_i_8__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFDFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      I1 => \converge_cnt_reg_n_0_[4]\,
      I2 => \converge_cnt_reg_n_0_[12]\,
      I3 => \converge_cnt_reg_n_0_[9]\,
      I4 => \converge_cnt_reg_n_0_[5]\,
      I5 => \converge_cnt_reg_n_0_[6]\,
      O => \FSM_onehot_fsm[3]_i_8__4_n_0\
    );
\FSM_onehot_fsm[4]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm[4]_i_2__4_n_0\,
      O => \FSM_onehot_fsm[4]_i_1__5_n_0\
    );
\FSM_onehot_fsm[4]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3__5_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4__4_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_5__4_n_0\,
      I3 => \FSM_onehot_fsm[4]_i_6__4_n_0\,
      I4 => \FSM_onehot_fsm[4]_i_7__4_n_0\,
      I5 => \FSM_onehot_fsm[4]_i_8__4_n_0\,
      O => \FSM_onehot_fsm[4]_i_2__4_n_0\
    );
\FSM_onehot_fsm[4]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02020202FF000000"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_3__5_n_0\
    );
\FSM_onehot_fsm[4]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00004B00004B0000"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \converge_cnt_reg_n_0_[21]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[10]\,
      O => \FSM_onehot_fsm[4]_i_4__4_n_0\
    );
\FSM_onehot_fsm[4]_i_5__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000810000810000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[8]\,
      I2 => \converge_cnt_reg_n_0_[3]\,
      I3 => \converge_cnt_reg_n_0_[20]\,
      I4 => \converge_cnt_reg_n_0_[21]\,
      I5 => \converge_cnt_reg_n_0_[14]\,
      O => \FSM_onehot_fsm[4]_i_5__4_n_0\
    );
\FSM_onehot_fsm[4]_i_6__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000024"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[0]\,
      I3 => \converge_cnt_reg_n_0_[5]\,
      I4 => \converge_cnt_reg_n_0_[4]\,
      O => \FSM_onehot_fsm[4]_i_6__4_n_0\
    );
\FSM_onehot_fsm[4]_i_7__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \converge_cnt_reg_n_0_[11]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[9]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[4]_i_7__4_n_0\
    );
\FSM_onehot_fsm[4]_i_8__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      I1 => \converge_cnt_reg_n_0_[6]\,
      I2 => \converge_cnt_reg_n_0_[16]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[19]\,
      I5 => \converge_cnt_reg_n_0_[7]\,
      O => \FSM_onehot_fsm[4]_i_8__4_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__5_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__5_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__5_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__5_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEEEEEE"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[0]\,
      I1 => \rxeq_cnt_reg[1]\,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      O => D(0)
    );
\FSM_sequential_fsm_rx[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0CAF0CA0FF000F00"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => \rxeq_cnt_reg[1]_0\,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \rxeq_control_reg2_reg[0]\,
      I5 => \FSM_sequential_fsm_rx_reg[2]\(0),
      O => D(1)
    );
\FSM_sequential_fsm_rx[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F083FC8330833C8"
    )
        port map (
      I0 => rxeqscan_preset_done,
      I1 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I4 => \rxeq_cnt_reg[1]_0\,
      I5 => \rxeq_control_reg2_reg[0]\,
      O => D(2)
    );
\adapt_done_cnt_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF2A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \out\(0),
      I2 => \out\(1),
      I3 => adapt_done_cnt,
      I4 => adapt_done_cnt_reg_n_0,
      O => \adapt_done_cnt_i_1__4_n_0\
    );
\adapt_done_cnt_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF444744444447"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => fsm1,
      O => adapt_done_cnt
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \adapt_done_cnt_i_1__4_n_0\,
      Q => adapt_done_cnt_reg_n_0,
      R => RST_CPLLRESET
    );
\adapt_done_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(1),
      I3 => \out\(0),
      I4 => new_txcoeff_req_reg2,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => RST_CPLLRESET
    );
\converge_cnt[0]_i_1__12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(0)
    );
\converge_cnt[10]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(10)
    );
\converge_cnt[11]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(11)
    );
\converge_cnt[11]_i_3__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      O => \converge_cnt[11]_i_3__4_n_0\
    );
\converge_cnt[11]_i_4__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      O => \converge_cnt[11]_i_4__4_n_0\
    );
\converge_cnt[11]_i_5__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[9]\,
      O => \converge_cnt[11]_i_5__4_n_0\
    );
\converge_cnt[11]_i_6__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[8]\,
      O => \converge_cnt[11]_i_6__4_n_0\
    );
\converge_cnt[12]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(12)
    );
\converge_cnt[13]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(13)
    );
\converge_cnt[14]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(14)
    );
\converge_cnt[15]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(15)
    );
\converge_cnt[15]_i_3__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[15]\,
      O => \converge_cnt[15]_i_3__4_n_0\
    );
\converge_cnt[15]_i_4__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[14]\,
      O => \converge_cnt[15]_i_4__4_n_0\
    );
\converge_cnt[15]_i_5__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[13]\,
      O => \converge_cnt[15]_i_5__4_n_0\
    );
\converge_cnt[15]_i_6__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      O => \converge_cnt[15]_i_6__4_n_0\
    );
\converge_cnt[16]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(16)
    );
\converge_cnt[17]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(17)
    );
\converge_cnt[18]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(18)
    );
\converge_cnt[19]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(19)
    );
\converge_cnt[19]_i_3__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      O => \converge_cnt[19]_i_3__4_n_0\
    );
\converge_cnt[19]_i_4__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[18]\,
      O => \converge_cnt[19]_i_4__4_n_0\
    );
\converge_cnt[19]_i_5__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[17]\,
      O => \converge_cnt[19]_i_5__4_n_0\
    );
\converge_cnt[19]_i_6__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[16]\,
      O => \converge_cnt[19]_i_6__4_n_0\
    );
\converge_cnt[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(1)
    );
\converge_cnt[20]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(20)
    );
\converge_cnt[21]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(21)
    );
\converge_cnt[21]_i_3__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[21]\,
      O => \converge_cnt[21]_i_3__4_n_0\
    );
\converge_cnt[21]_i_4__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      O => \converge_cnt[21]_i_4__4_n_0\
    );
\converge_cnt[2]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(2)
    );
\converge_cnt[3]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(3)
    );
\converge_cnt[3]_i_3__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[3]\,
      O => \converge_cnt[3]_i_3__4_n_0\
    );
\converge_cnt[3]_i_4__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      O => \converge_cnt[3]_i_4__4_n_0\
    );
\converge_cnt[3]_i_5__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      O => \converge_cnt[3]_i_5__4_n_0\
    );
\converge_cnt[3]_i_6__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      O => \converge_cnt[3]_i_6__4_n_0\
    );
\converge_cnt[4]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(4)
    );
\converge_cnt[5]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(5)
    );
\converge_cnt[6]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(6)
    );
\converge_cnt[7]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(7)
    );
\converge_cnt[7]_i_3__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[7]\,
      O => \converge_cnt[7]_i_3__4_n_0\
    );
\converge_cnt[7]_i_4__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[6]\,
      O => \converge_cnt[7]_i_4__4_n_0\
    );
\converge_cnt[7]_i_5__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[5]\,
      O => \converge_cnt[7]_i_5__4_n_0\
    );
\converge_cnt[7]_i_6__4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[4]\,
      O => \converge_cnt[7]_i_6__4_n_0\
    );
\converge_cnt[8]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(8)
    );
\converge_cnt[9]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(0),
      Q => \converge_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(10),
      Q => \converge_cnt_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(11),
      Q => \converge_cnt_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]_i_2__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[7]_i_2__4_n_0\,
      CO(3) => \converge_cnt_reg[11]_i_2__4_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__4_n_1\,
      CO(1) => \converge_cnt_reg[11]_i_2__4_n_2\,
      CO(0) => \converge_cnt_reg[11]_i_2__4_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(11 downto 8),
      S(3) => \converge_cnt[11]_i_3__4_n_0\,
      S(2) => \converge_cnt[11]_i_4__4_n_0\,
      S(1) => \converge_cnt[11]_i_5__4_n_0\,
      S(0) => \converge_cnt[11]_i_6__4_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(12),
      Q => \converge_cnt_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(13),
      Q => \converge_cnt_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(14),
      Q => \converge_cnt_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(15),
      Q => \converge_cnt_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]_i_2__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[11]_i_2__4_n_0\,
      CO(3) => \converge_cnt_reg[15]_i_2__4_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__4_n_1\,
      CO(1) => \converge_cnt_reg[15]_i_2__4_n_2\,
      CO(0) => \converge_cnt_reg[15]_i_2__4_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(15 downto 12),
      S(3) => \converge_cnt[15]_i_3__4_n_0\,
      S(2) => \converge_cnt[15]_i_4__4_n_0\,
      S(1) => \converge_cnt[15]_i_5__4_n_0\,
      S(0) => \converge_cnt[15]_i_6__4_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(16),
      Q => \converge_cnt_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(17),
      Q => \converge_cnt_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(18),
      Q => \converge_cnt_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(19),
      Q => \converge_cnt_reg_n_0_[19]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]_i_2__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[15]_i_2__4_n_0\,
      CO(3) => \converge_cnt_reg[19]_i_2__4_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__4_n_1\,
      CO(1) => \converge_cnt_reg[19]_i_2__4_n_2\,
      CO(0) => \converge_cnt_reg[19]_i_2__4_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(19 downto 16),
      S(3) => \converge_cnt[19]_i_3__4_n_0\,
      S(2) => \converge_cnt[19]_i_4__4_n_0\,
      S(1) => \converge_cnt[19]_i_5__4_n_0\,
      S(0) => \converge_cnt[19]_i_6__4_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(1),
      Q => \converge_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(20),
      Q => \converge_cnt_reg_n_0_[20]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(21),
      Q => \converge_cnt_reg_n_0_[21]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]_i_2__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[19]_i_2__4_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__4_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[21]_i_2__4_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__4_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => converge_cnt0(21 downto 20),
      S(3) => '0',
      S(2) => '0',
      S(1) => \converge_cnt[21]_i_3__4_n_0\,
      S(0) => \converge_cnt[21]_i_4__4_n_0\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(2),
      Q => \converge_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(3),
      Q => \converge_cnt_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]_i_2__4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[3]_i_2__4_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__4_n_1\,
      CO(1) => \converge_cnt_reg[3]_i_2__4_n_2\,
      CO(0) => \converge_cnt_reg[3]_i_2__4_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => \converge_cnt_reg_n_0_[0]\,
      O(3 downto 0) => converge_cnt0(3 downto 0),
      S(3) => \converge_cnt[3]_i_3__4_n_0\,
      S(2) => \converge_cnt[3]_i_4__4_n_0\,
      S(1) => \converge_cnt[3]_i_5__4_n_0\,
      S(0) => \converge_cnt[3]_i_6__4_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(4),
      Q => \converge_cnt_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(5),
      Q => \converge_cnt_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(6),
      Q => \converge_cnt_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(7),
      Q => \converge_cnt_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]_i_2__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[3]_i_2__4_n_0\,
      CO(3) => \converge_cnt_reg[7]_i_2__4_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__4_n_1\,
      CO(1) => \converge_cnt_reg[7]_i_2__4_n_2\,
      CO(0) => \converge_cnt_reg[7]_i_2__4_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(7 downto 4),
      S(3) => \converge_cnt[7]_i_3__4_n_0\,
      S(2) => \converge_cnt[7]_i_4__4_n_0\,
      S(1) => \converge_cnt[7]_i_5__4_n_0\,
      S(0) => \converge_cnt[7]_i_6__4_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(8),
      Q => \converge_cnt_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(9),
      Q => \converge_cnt_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(0),
      Q => fs_reg1(0),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(1),
      Q => fs_reg1(1),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(2),
      Q => fs_reg1(2),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(3),
      Q => fs_reg1(3),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(4),
      Q => fs_reg1(4),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(5),
      Q => fs_reg1(5),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(0),
      Q => lf_reg1(0),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(1),
      Q => lf_reg1(1),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(2),
      Q => lf_reg1(2),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(3),
      Q => lf_reg1(3),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(4),
      Q => lf_reg1(4),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(5),
      Q => lf_reg1(5),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => RST_CPLLRESET
    );
\new_txcoeff_done_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_new_txcoeff_req_reg_0,
      Q => new_txcoeff_req_reg1,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => RST_CPLLRESET
    );
\preset_done_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => preset_done
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_done,
      Q => rxeqscan_preset_done,
      R => RST_CPLLRESET
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(0),
      Q => preset_reg1(0),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(1),
      Q => preset_reg1(1),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(2),
      Q => preset_reg1(2),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => RST_CPLLRESET
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid_reg,
      Q => preset_valid_reg1,
      R => RST_CPLLRESET
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => RST_CPLLRESET
    );
\rxeq_adapt_done_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080F00000800000"
    )
        port map (
      I0 => rxeq_adapt_done_reg0,
      I1 => rxeqscan_new_txcoeff_done,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I5 => USER_RXEQ_ADAPT_DONE,
      O => rxeq_adapt_done_reg
    );
\rxeq_adapt_done_i_2__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg0
    );
\rxeq_adapt_done_reg_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44FF4000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => rxeqscan_adapt_done,
      I3 => \rxeq_adapt_done_reg_i_2__4_n_0\,
      I4 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg_reg
    );
\rxeq_adapt_done_reg_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0002FF000002F"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I5 => rxeqscan_new_txcoeff_done,
      O => \rxeq_adapt_done_reg_i_2__4_n_0\
    );
\rxeq_new_txcoeff_req_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I3 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req_reg
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(0),
      Q => txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(10),
      Q => txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(11),
      Q => txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(12),
      Q => txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(13),
      Q => txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(14),
      Q => txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(15),
      Q => txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(16),
      Q => txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(17),
      Q => txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(1),
      Q => txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(2),
      Q => txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(3),
      Q => txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(4),
      Q => txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(5),
      Q => txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(6),
      Q => txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(7),
      Q => txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(8),
      Q => txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(9),
      Q => txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(0),
      Q => txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(1),
      Q => txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(2),
      Q => txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(3),
      Q => txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_76 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req_reg : out STD_LOGIC;
    rxeq_adapt_done_reg : out STD_LOGIC;
    rxeq_adapt_done_reg_reg : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    rxeq_new_txcoeff_req_reg_0 : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rxeq_preset_valid_reg : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_sequential_fsm_rx_reg[0]\ : in STD_LOGIC;
    \rxeq_cnt_reg[1]\ : in STD_LOGIC;
    \FSM_sequential_fsm_rx_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rxeq_cnt_reg[1]_0\ : in STD_LOGIC;
    \rxeq_control_reg2_reg[0]\ : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    \rxeq_preset_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rxeq_txcoeff_reg[17]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \rxeq_fs_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rxeq_lf_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_76 : entity is "PCIeGen1x8If64_rxeq_scan";
end PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_76;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_76 is
  signal \FSM_onehot_fsm[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_3__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_4__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_5__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_7__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_8__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[4]\ : signal is "yes";
  signal adapt_done : STD_LOGIC;
  signal adapt_done_cnt : STD_LOGIC;
  signal \adapt_done_cnt_i_1__3_n_0\ : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt[11]_i_3__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_4__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_5__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_6__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_3__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_4__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_5__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_6__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_3__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_4__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_5__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_6__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_3__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_4__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_3__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_4__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_5__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_6__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_3__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_4__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_5__3_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_6__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__3_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__3_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__3_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__3_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__3_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__3_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__3_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__3_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__3_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_2__3_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__3_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__3_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__3_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__3_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__3_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__3_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[16]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[17]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[18]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[19]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[20]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[21]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  signal preset_done : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_valid_reg1 : STD_LOGIC;
  signal preset_valid_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg0 : STD_LOGIC;
  signal \rxeq_adapt_done_reg_i_2__3_n_0\ : STD_LOGIC;
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal rxeqscan_preset_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[4]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute ASYNC_REG of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rxeq_adapt_done_i_2__3\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \rxeq_adapt_done_reg_i_1__3\ : label is "soft_lutpair119";
  attribute ASYNC_REG of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
begin
\FSM_onehot_fsm[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000073333FF07"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => preset_valid_reg2,
      O => \FSM_onehot_fsm[1]_i_1__4_n_0\
    );
\FSM_onehot_fsm[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__4_n_0\
    );
\FSM_onehot_fsm[3]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA8A8AA"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2__4_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_3__4_n_0\,
      I2 => \FSM_onehot_fsm[3]_i_4__4_n_0\,
      I3 => \converge_cnt_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm[3]_i_5__3_n_0\,
      O => \FSM_onehot_fsm[3]_i_1__4_n_0\
    );
\FSM_onehot_fsm[3]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202020202F20"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => fsm1,
      I5 => \FSM_onehot_fsm_reg_n_0_[2]\,
      O => \FSM_onehot_fsm[3]_i_2__4_n_0\
    );
\FSM_onehot_fsm[3]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6FFFFFFFF6FFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      I1 => \converge_cnt_reg_n_0_[2]\,
      I2 => \converge_cnt_reg_n_0_[10]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[20]\,
      O => \FSM_onehot_fsm[3]_i_3__4_n_0\
    );
\FSM_onehot_fsm[3]_i_4__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7E7EFFFF7EFF7E"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[8]\,
      I3 => \converge_cnt_reg_n_0_[21]\,
      I4 => \out\(0),
      I5 => \out\(1),
      O => \FSM_onehot_fsm[3]_i_4__4_n_0\
    );
\FSM_onehot_fsm[3]_i_5__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF9"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      I1 => \converge_cnt_reg_n_0_[21]\,
      I2 => \converge_cnt_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[7]\,
      I4 => \FSM_onehot_fsm[3]_i_7__3_n_0\,
      I5 => \FSM_onehot_fsm[3]_i_8__3_n_0\,
      O => \FSM_onehot_fsm[3]_i_5__3_n_0\
    );
\FSM_onehot_fsm[3]_i_6__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      O => fsm1
    );
\FSM_onehot_fsm[3]_i_7__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[16]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[3]_i_7__3_n_0\
    );
\FSM_onehot_fsm[3]_i_8__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFDFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      I1 => \converge_cnt_reg_n_0_[4]\,
      I2 => \converge_cnt_reg_n_0_[12]\,
      I3 => \converge_cnt_reg_n_0_[9]\,
      I4 => \converge_cnt_reg_n_0_[5]\,
      I5 => \converge_cnt_reg_n_0_[6]\,
      O => \FSM_onehot_fsm[3]_i_8__3_n_0\
    );
\FSM_onehot_fsm[4]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm[4]_i_2__3_n_0\,
      O => \FSM_onehot_fsm[4]_i_1__4_n_0\
    );
\FSM_onehot_fsm[4]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3__4_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4__3_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_5__3_n_0\,
      I3 => \FSM_onehot_fsm[4]_i_6__3_n_0\,
      I4 => \FSM_onehot_fsm[4]_i_7__3_n_0\,
      I5 => \FSM_onehot_fsm[4]_i_8__3_n_0\,
      O => \FSM_onehot_fsm[4]_i_2__3_n_0\
    );
\FSM_onehot_fsm[4]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02020202FF000000"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_3__4_n_0\
    );
\FSM_onehot_fsm[4]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00004B00004B0000"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \converge_cnt_reg_n_0_[21]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[10]\,
      O => \FSM_onehot_fsm[4]_i_4__3_n_0\
    );
\FSM_onehot_fsm[4]_i_5__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000810000810000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[8]\,
      I2 => \converge_cnt_reg_n_0_[3]\,
      I3 => \converge_cnt_reg_n_0_[20]\,
      I4 => \converge_cnt_reg_n_0_[21]\,
      I5 => \converge_cnt_reg_n_0_[14]\,
      O => \FSM_onehot_fsm[4]_i_5__3_n_0\
    );
\FSM_onehot_fsm[4]_i_6__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000024"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[0]\,
      I3 => \converge_cnt_reg_n_0_[5]\,
      I4 => \converge_cnt_reg_n_0_[4]\,
      O => \FSM_onehot_fsm[4]_i_6__3_n_0\
    );
\FSM_onehot_fsm[4]_i_7__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \converge_cnt_reg_n_0_[11]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[9]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[4]_i_7__3_n_0\
    );
\FSM_onehot_fsm[4]_i_8__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      I1 => \converge_cnt_reg_n_0_[6]\,
      I2 => \converge_cnt_reg_n_0_[16]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[19]\,
      I5 => \converge_cnt_reg_n_0_[7]\,
      O => \FSM_onehot_fsm[4]_i_8__3_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__4_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__4_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__4_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__4_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEEEEEE"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[0]\,
      I1 => \rxeq_cnt_reg[1]\,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      O => D(0)
    );
\FSM_sequential_fsm_rx[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0CAF0CA0FF000F00"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => \rxeq_cnt_reg[1]_0\,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \rxeq_control_reg2_reg[0]\,
      I5 => \FSM_sequential_fsm_rx_reg[2]\(0),
      O => D(1)
    );
\FSM_sequential_fsm_rx[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F083FC8330833C8"
    )
        port map (
      I0 => rxeqscan_preset_done,
      I1 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I4 => \rxeq_cnt_reg[1]_0\,
      I5 => \rxeq_control_reg2_reg[0]\,
      O => D(2)
    );
\adapt_done_cnt_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF2A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \out\(0),
      I2 => \out\(1),
      I3 => adapt_done_cnt,
      I4 => adapt_done_cnt_reg_n_0,
      O => \adapt_done_cnt_i_1__3_n_0\
    );
\adapt_done_cnt_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF444744444447"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => fsm1,
      O => adapt_done_cnt
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \adapt_done_cnt_i_1__3_n_0\,
      Q => adapt_done_cnt_reg_n_0,
      R => RST_CPLLRESET
    );
\adapt_done_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(1),
      I3 => \out\(0),
      I4 => new_txcoeff_req_reg2,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => RST_CPLLRESET
    );
\converge_cnt[0]_i_1__11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(0)
    );
\converge_cnt[10]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(10)
    );
\converge_cnt[11]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(11)
    );
\converge_cnt[11]_i_3__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      O => \converge_cnt[11]_i_3__3_n_0\
    );
\converge_cnt[11]_i_4__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      O => \converge_cnt[11]_i_4__3_n_0\
    );
\converge_cnt[11]_i_5__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[9]\,
      O => \converge_cnt[11]_i_5__3_n_0\
    );
\converge_cnt[11]_i_6__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[8]\,
      O => \converge_cnt[11]_i_6__3_n_0\
    );
\converge_cnt[12]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(12)
    );
\converge_cnt[13]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(13)
    );
\converge_cnt[14]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(14)
    );
\converge_cnt[15]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(15)
    );
\converge_cnt[15]_i_3__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[15]\,
      O => \converge_cnt[15]_i_3__3_n_0\
    );
\converge_cnt[15]_i_4__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[14]\,
      O => \converge_cnt[15]_i_4__3_n_0\
    );
\converge_cnt[15]_i_5__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[13]\,
      O => \converge_cnt[15]_i_5__3_n_0\
    );
\converge_cnt[15]_i_6__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      O => \converge_cnt[15]_i_6__3_n_0\
    );
\converge_cnt[16]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(16)
    );
\converge_cnt[17]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(17)
    );
\converge_cnt[18]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(18)
    );
\converge_cnt[19]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(19)
    );
\converge_cnt[19]_i_3__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      O => \converge_cnt[19]_i_3__3_n_0\
    );
\converge_cnt[19]_i_4__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[18]\,
      O => \converge_cnt[19]_i_4__3_n_0\
    );
\converge_cnt[19]_i_5__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[17]\,
      O => \converge_cnt[19]_i_5__3_n_0\
    );
\converge_cnt[19]_i_6__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[16]\,
      O => \converge_cnt[19]_i_6__3_n_0\
    );
\converge_cnt[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(1)
    );
\converge_cnt[20]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(20)
    );
\converge_cnt[21]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(21)
    );
\converge_cnt[21]_i_3__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[21]\,
      O => \converge_cnt[21]_i_3__3_n_0\
    );
\converge_cnt[21]_i_4__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      O => \converge_cnt[21]_i_4__3_n_0\
    );
\converge_cnt[2]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(2)
    );
\converge_cnt[3]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(3)
    );
\converge_cnt[3]_i_3__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[3]\,
      O => \converge_cnt[3]_i_3__3_n_0\
    );
\converge_cnt[3]_i_4__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      O => \converge_cnt[3]_i_4__3_n_0\
    );
\converge_cnt[3]_i_5__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      O => \converge_cnt[3]_i_5__3_n_0\
    );
\converge_cnt[3]_i_6__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      O => \converge_cnt[3]_i_6__3_n_0\
    );
\converge_cnt[4]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(4)
    );
\converge_cnt[5]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(5)
    );
\converge_cnt[6]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(6)
    );
\converge_cnt[7]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(7)
    );
\converge_cnt[7]_i_3__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[7]\,
      O => \converge_cnt[7]_i_3__3_n_0\
    );
\converge_cnt[7]_i_4__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[6]\,
      O => \converge_cnt[7]_i_4__3_n_0\
    );
\converge_cnt[7]_i_5__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[5]\,
      O => \converge_cnt[7]_i_5__3_n_0\
    );
\converge_cnt[7]_i_6__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[4]\,
      O => \converge_cnt[7]_i_6__3_n_0\
    );
\converge_cnt[8]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(8)
    );
\converge_cnt[9]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(0),
      Q => \converge_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(10),
      Q => \converge_cnt_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(11),
      Q => \converge_cnt_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]_i_2__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[7]_i_2__3_n_0\,
      CO(3) => \converge_cnt_reg[11]_i_2__3_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__3_n_1\,
      CO(1) => \converge_cnt_reg[11]_i_2__3_n_2\,
      CO(0) => \converge_cnt_reg[11]_i_2__3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(11 downto 8),
      S(3) => \converge_cnt[11]_i_3__3_n_0\,
      S(2) => \converge_cnt[11]_i_4__3_n_0\,
      S(1) => \converge_cnt[11]_i_5__3_n_0\,
      S(0) => \converge_cnt[11]_i_6__3_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(12),
      Q => \converge_cnt_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(13),
      Q => \converge_cnt_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(14),
      Q => \converge_cnt_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(15),
      Q => \converge_cnt_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]_i_2__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[11]_i_2__3_n_0\,
      CO(3) => \converge_cnt_reg[15]_i_2__3_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__3_n_1\,
      CO(1) => \converge_cnt_reg[15]_i_2__3_n_2\,
      CO(0) => \converge_cnt_reg[15]_i_2__3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(15 downto 12),
      S(3) => \converge_cnt[15]_i_3__3_n_0\,
      S(2) => \converge_cnt[15]_i_4__3_n_0\,
      S(1) => \converge_cnt[15]_i_5__3_n_0\,
      S(0) => \converge_cnt[15]_i_6__3_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(16),
      Q => \converge_cnt_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(17),
      Q => \converge_cnt_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(18),
      Q => \converge_cnt_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(19),
      Q => \converge_cnt_reg_n_0_[19]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]_i_2__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[15]_i_2__3_n_0\,
      CO(3) => \converge_cnt_reg[19]_i_2__3_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__3_n_1\,
      CO(1) => \converge_cnt_reg[19]_i_2__3_n_2\,
      CO(0) => \converge_cnt_reg[19]_i_2__3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(19 downto 16),
      S(3) => \converge_cnt[19]_i_3__3_n_0\,
      S(2) => \converge_cnt[19]_i_4__3_n_0\,
      S(1) => \converge_cnt[19]_i_5__3_n_0\,
      S(0) => \converge_cnt[19]_i_6__3_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(1),
      Q => \converge_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(20),
      Q => \converge_cnt_reg_n_0_[20]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(21),
      Q => \converge_cnt_reg_n_0_[21]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]_i_2__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[19]_i_2__3_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__3_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[21]_i_2__3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__3_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => converge_cnt0(21 downto 20),
      S(3) => '0',
      S(2) => '0',
      S(1) => \converge_cnt[21]_i_3__3_n_0\,
      S(0) => \converge_cnt[21]_i_4__3_n_0\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(2),
      Q => \converge_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(3),
      Q => \converge_cnt_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]_i_2__3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[3]_i_2__3_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__3_n_1\,
      CO(1) => \converge_cnt_reg[3]_i_2__3_n_2\,
      CO(0) => \converge_cnt_reg[3]_i_2__3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => \converge_cnt_reg_n_0_[0]\,
      O(3 downto 0) => converge_cnt0(3 downto 0),
      S(3) => \converge_cnt[3]_i_3__3_n_0\,
      S(2) => \converge_cnt[3]_i_4__3_n_0\,
      S(1) => \converge_cnt[3]_i_5__3_n_0\,
      S(0) => \converge_cnt[3]_i_6__3_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(4),
      Q => \converge_cnt_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(5),
      Q => \converge_cnt_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(6),
      Q => \converge_cnt_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(7),
      Q => \converge_cnt_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]_i_2__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[3]_i_2__3_n_0\,
      CO(3) => \converge_cnt_reg[7]_i_2__3_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__3_n_1\,
      CO(1) => \converge_cnt_reg[7]_i_2__3_n_2\,
      CO(0) => \converge_cnt_reg[7]_i_2__3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(7 downto 4),
      S(3) => \converge_cnt[7]_i_3__3_n_0\,
      S(2) => \converge_cnt[7]_i_4__3_n_0\,
      S(1) => \converge_cnt[7]_i_5__3_n_0\,
      S(0) => \converge_cnt[7]_i_6__3_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(8),
      Q => \converge_cnt_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(9),
      Q => \converge_cnt_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(0),
      Q => fs_reg1(0),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(1),
      Q => fs_reg1(1),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(2),
      Q => fs_reg1(2),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(3),
      Q => fs_reg1(3),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(4),
      Q => fs_reg1(4),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(5),
      Q => fs_reg1(5),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(0),
      Q => lf_reg1(0),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(1),
      Q => lf_reg1(1),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(2),
      Q => lf_reg1(2),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(3),
      Q => lf_reg1(3),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(4),
      Q => lf_reg1(4),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(5),
      Q => lf_reg1(5),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => RST_CPLLRESET
    );
\new_txcoeff_done_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_new_txcoeff_req_reg_0,
      Q => new_txcoeff_req_reg1,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => RST_CPLLRESET
    );
\preset_done_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => preset_done
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_done,
      Q => rxeqscan_preset_done,
      R => RST_CPLLRESET
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(0),
      Q => preset_reg1(0),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(1),
      Q => preset_reg1(1),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(2),
      Q => preset_reg1(2),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => RST_CPLLRESET
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid_reg,
      Q => preset_valid_reg1,
      R => RST_CPLLRESET
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => RST_CPLLRESET
    );
\rxeq_adapt_done_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080F00000800000"
    )
        port map (
      I0 => rxeq_adapt_done_reg0,
      I1 => rxeqscan_new_txcoeff_done,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I5 => USER_RXEQ_ADAPT_DONE,
      O => rxeq_adapt_done_reg
    );
\rxeq_adapt_done_i_2__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg0
    );
\rxeq_adapt_done_reg_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44FF4000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => rxeqscan_adapt_done,
      I3 => \rxeq_adapt_done_reg_i_2__3_n_0\,
      I4 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg_reg
    );
\rxeq_adapt_done_reg_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0002FF000002F"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I5 => rxeqscan_new_txcoeff_done,
      O => \rxeq_adapt_done_reg_i_2__3_n_0\
    );
\rxeq_new_txcoeff_req_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I3 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req_reg
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(0),
      Q => txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(10),
      Q => txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(11),
      Q => txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(12),
      Q => txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(13),
      Q => txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(14),
      Q => txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(15),
      Q => txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(16),
      Q => txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(17),
      Q => txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(1),
      Q => txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(2),
      Q => txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(3),
      Q => txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(4),
      Q => txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(5),
      Q => txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(6),
      Q => txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(7),
      Q => txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(8),
      Q => txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(9),
      Q => txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(0),
      Q => txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(1),
      Q => txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(2),
      Q => txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(3),
      Q => txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_78 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req_reg : out STD_LOGIC;
    rxeq_adapt_done_reg : out STD_LOGIC;
    rxeq_adapt_done_reg_reg : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    rxeq_new_txcoeff_req_reg_0 : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rxeq_preset_valid_reg : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_sequential_fsm_rx_reg[0]\ : in STD_LOGIC;
    \rxeq_cnt_reg[1]\ : in STD_LOGIC;
    \FSM_sequential_fsm_rx_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rxeq_cnt_reg[1]_0\ : in STD_LOGIC;
    \rxeq_control_reg2_reg[0]\ : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    \rxeq_preset_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rxeq_txcoeff_reg[17]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \rxeq_fs_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rxeq_lf_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_78 : entity is "PCIeGen1x8If64_rxeq_scan";
end PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_78;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_78 is
  signal \FSM_onehot_fsm[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_3__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_4__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_5__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_7__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_8__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[4]\ : signal is "yes";
  signal adapt_done : STD_LOGIC;
  signal adapt_done_cnt : STD_LOGIC;
  signal \adapt_done_cnt_i_1__2_n_0\ : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt[11]_i_3__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_4__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_5__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_6__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_3__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_4__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_5__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_6__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_3__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_4__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_5__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_6__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_3__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_4__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_3__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_4__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_5__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_6__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_3__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_4__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_5__2_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_6__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_2__2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[16]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[17]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[18]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[19]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[20]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[21]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  signal preset_done : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_valid_reg1 : STD_LOGIC;
  signal preset_valid_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg0 : STD_LOGIC;
  signal \rxeq_adapt_done_reg_i_2__2_n_0\ : STD_LOGIC;
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal rxeqscan_preset_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[4]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute ASYNC_REG of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rxeq_adapt_done_i_2__2\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \rxeq_adapt_done_reg_i_1__2\ : label is "soft_lutpair97";
  attribute ASYNC_REG of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
begin
\FSM_onehot_fsm[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000073333FF07"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => preset_valid_reg2,
      O => \FSM_onehot_fsm[1]_i_1__3_n_0\
    );
\FSM_onehot_fsm[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__3_n_0\
    );
\FSM_onehot_fsm[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA8A8AA"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2__3_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_3__3_n_0\,
      I2 => \FSM_onehot_fsm[3]_i_4__3_n_0\,
      I3 => \converge_cnt_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm[3]_i_5__2_n_0\,
      O => \FSM_onehot_fsm[3]_i_1__3_n_0\
    );
\FSM_onehot_fsm[3]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202020202F20"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => fsm1,
      I5 => \FSM_onehot_fsm_reg_n_0_[2]\,
      O => \FSM_onehot_fsm[3]_i_2__3_n_0\
    );
\FSM_onehot_fsm[3]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6FFFFFFFF6FFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      I1 => \converge_cnt_reg_n_0_[2]\,
      I2 => \converge_cnt_reg_n_0_[10]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[20]\,
      O => \FSM_onehot_fsm[3]_i_3__3_n_0\
    );
\FSM_onehot_fsm[3]_i_4__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7E7EFFFF7EFF7E"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[8]\,
      I3 => \converge_cnt_reg_n_0_[21]\,
      I4 => \out\(0),
      I5 => \out\(1),
      O => \FSM_onehot_fsm[3]_i_4__3_n_0\
    );
\FSM_onehot_fsm[3]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF9"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      I1 => \converge_cnt_reg_n_0_[21]\,
      I2 => \converge_cnt_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[7]\,
      I4 => \FSM_onehot_fsm[3]_i_7__2_n_0\,
      I5 => \FSM_onehot_fsm[3]_i_8__2_n_0\,
      O => \FSM_onehot_fsm[3]_i_5__2_n_0\
    );
\FSM_onehot_fsm[3]_i_6__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      O => fsm1
    );
\FSM_onehot_fsm[3]_i_7__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[16]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[3]_i_7__2_n_0\
    );
\FSM_onehot_fsm[3]_i_8__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFDFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      I1 => \converge_cnt_reg_n_0_[4]\,
      I2 => \converge_cnt_reg_n_0_[12]\,
      I3 => \converge_cnt_reg_n_0_[9]\,
      I4 => \converge_cnt_reg_n_0_[5]\,
      I5 => \converge_cnt_reg_n_0_[6]\,
      O => \FSM_onehot_fsm[3]_i_8__2_n_0\
    );
\FSM_onehot_fsm[4]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm[4]_i_2__2_n_0\,
      O => \FSM_onehot_fsm[4]_i_1__3_n_0\
    );
\FSM_onehot_fsm[4]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3__3_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4__2_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_5__2_n_0\,
      I3 => \FSM_onehot_fsm[4]_i_6__2_n_0\,
      I4 => \FSM_onehot_fsm[4]_i_7__2_n_0\,
      I5 => \FSM_onehot_fsm[4]_i_8__2_n_0\,
      O => \FSM_onehot_fsm[4]_i_2__2_n_0\
    );
\FSM_onehot_fsm[4]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02020202FF000000"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_3__3_n_0\
    );
\FSM_onehot_fsm[4]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00004B00004B0000"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \converge_cnt_reg_n_0_[21]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[10]\,
      O => \FSM_onehot_fsm[4]_i_4__2_n_0\
    );
\FSM_onehot_fsm[4]_i_5__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000810000810000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[8]\,
      I2 => \converge_cnt_reg_n_0_[3]\,
      I3 => \converge_cnt_reg_n_0_[20]\,
      I4 => \converge_cnt_reg_n_0_[21]\,
      I5 => \converge_cnt_reg_n_0_[14]\,
      O => \FSM_onehot_fsm[4]_i_5__2_n_0\
    );
\FSM_onehot_fsm[4]_i_6__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000024"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[0]\,
      I3 => \converge_cnt_reg_n_0_[5]\,
      I4 => \converge_cnt_reg_n_0_[4]\,
      O => \FSM_onehot_fsm[4]_i_6__2_n_0\
    );
\FSM_onehot_fsm[4]_i_7__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \converge_cnt_reg_n_0_[11]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[9]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[4]_i_7__2_n_0\
    );
\FSM_onehot_fsm[4]_i_8__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      I1 => \converge_cnt_reg_n_0_[6]\,
      I2 => \converge_cnt_reg_n_0_[16]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[19]\,
      I5 => \converge_cnt_reg_n_0_[7]\,
      O => \FSM_onehot_fsm[4]_i_8__2_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEEEEEE"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[0]\,
      I1 => \rxeq_cnt_reg[1]\,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      O => D(0)
    );
\FSM_sequential_fsm_rx[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0CAF0CA0FF000F00"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => \rxeq_cnt_reg[1]_0\,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \rxeq_control_reg2_reg[0]\,
      I5 => \FSM_sequential_fsm_rx_reg[2]\(0),
      O => D(1)
    );
\FSM_sequential_fsm_rx[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F083FC8330833C8"
    )
        port map (
      I0 => rxeqscan_preset_done,
      I1 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I4 => \rxeq_cnt_reg[1]_0\,
      I5 => \rxeq_control_reg2_reg[0]\,
      O => D(2)
    );
\adapt_done_cnt_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF2A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \out\(0),
      I2 => \out\(1),
      I3 => adapt_done_cnt,
      I4 => adapt_done_cnt_reg_n_0,
      O => \adapt_done_cnt_i_1__2_n_0\
    );
\adapt_done_cnt_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF444744444447"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => fsm1,
      O => adapt_done_cnt
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \adapt_done_cnt_i_1__2_n_0\,
      Q => adapt_done_cnt_reg_n_0,
      R => RST_CPLLRESET
    );
\adapt_done_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(1),
      I3 => \out\(0),
      I4 => new_txcoeff_req_reg2,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => RST_CPLLRESET
    );
\converge_cnt[0]_i_1__10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(0)
    );
\converge_cnt[10]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(10)
    );
\converge_cnt[11]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(11)
    );
\converge_cnt[11]_i_3__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      O => \converge_cnt[11]_i_3__2_n_0\
    );
\converge_cnt[11]_i_4__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      O => \converge_cnt[11]_i_4__2_n_0\
    );
\converge_cnt[11]_i_5__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[9]\,
      O => \converge_cnt[11]_i_5__2_n_0\
    );
\converge_cnt[11]_i_6__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[8]\,
      O => \converge_cnt[11]_i_6__2_n_0\
    );
\converge_cnt[12]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(12)
    );
\converge_cnt[13]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(13)
    );
\converge_cnt[14]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(14)
    );
\converge_cnt[15]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(15)
    );
\converge_cnt[15]_i_3__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[15]\,
      O => \converge_cnt[15]_i_3__2_n_0\
    );
\converge_cnt[15]_i_4__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[14]\,
      O => \converge_cnt[15]_i_4__2_n_0\
    );
\converge_cnt[15]_i_5__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[13]\,
      O => \converge_cnt[15]_i_5__2_n_0\
    );
\converge_cnt[15]_i_6__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      O => \converge_cnt[15]_i_6__2_n_0\
    );
\converge_cnt[16]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(16)
    );
\converge_cnt[17]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(17)
    );
\converge_cnt[18]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(18)
    );
\converge_cnt[19]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(19)
    );
\converge_cnt[19]_i_3__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      O => \converge_cnt[19]_i_3__2_n_0\
    );
\converge_cnt[19]_i_4__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[18]\,
      O => \converge_cnt[19]_i_4__2_n_0\
    );
\converge_cnt[19]_i_5__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[17]\,
      O => \converge_cnt[19]_i_5__2_n_0\
    );
\converge_cnt[19]_i_6__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[16]\,
      O => \converge_cnt[19]_i_6__2_n_0\
    );
\converge_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(1)
    );
\converge_cnt[20]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(20)
    );
\converge_cnt[21]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(21)
    );
\converge_cnt[21]_i_3__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[21]\,
      O => \converge_cnt[21]_i_3__2_n_0\
    );
\converge_cnt[21]_i_4__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      O => \converge_cnt[21]_i_4__2_n_0\
    );
\converge_cnt[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(2)
    );
\converge_cnt[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(3)
    );
\converge_cnt[3]_i_3__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[3]\,
      O => \converge_cnt[3]_i_3__2_n_0\
    );
\converge_cnt[3]_i_4__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      O => \converge_cnt[3]_i_4__2_n_0\
    );
\converge_cnt[3]_i_5__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      O => \converge_cnt[3]_i_5__2_n_0\
    );
\converge_cnt[3]_i_6__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      O => \converge_cnt[3]_i_6__2_n_0\
    );
\converge_cnt[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(4)
    );
\converge_cnt[5]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(5)
    );
\converge_cnt[6]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(6)
    );
\converge_cnt[7]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(7)
    );
\converge_cnt[7]_i_3__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[7]\,
      O => \converge_cnt[7]_i_3__2_n_0\
    );
\converge_cnt[7]_i_4__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[6]\,
      O => \converge_cnt[7]_i_4__2_n_0\
    );
\converge_cnt[7]_i_5__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[5]\,
      O => \converge_cnt[7]_i_5__2_n_0\
    );
\converge_cnt[7]_i_6__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[4]\,
      O => \converge_cnt[7]_i_6__2_n_0\
    );
\converge_cnt[8]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(8)
    );
\converge_cnt[9]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(0),
      Q => \converge_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(10),
      Q => \converge_cnt_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(11),
      Q => \converge_cnt_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]_i_2__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[7]_i_2__2_n_0\,
      CO(3) => \converge_cnt_reg[11]_i_2__2_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__2_n_1\,
      CO(1) => \converge_cnt_reg[11]_i_2__2_n_2\,
      CO(0) => \converge_cnt_reg[11]_i_2__2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(11 downto 8),
      S(3) => \converge_cnt[11]_i_3__2_n_0\,
      S(2) => \converge_cnt[11]_i_4__2_n_0\,
      S(1) => \converge_cnt[11]_i_5__2_n_0\,
      S(0) => \converge_cnt[11]_i_6__2_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(12),
      Q => \converge_cnt_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(13),
      Q => \converge_cnt_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(14),
      Q => \converge_cnt_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(15),
      Q => \converge_cnt_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]_i_2__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[11]_i_2__2_n_0\,
      CO(3) => \converge_cnt_reg[15]_i_2__2_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__2_n_1\,
      CO(1) => \converge_cnt_reg[15]_i_2__2_n_2\,
      CO(0) => \converge_cnt_reg[15]_i_2__2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(15 downto 12),
      S(3) => \converge_cnt[15]_i_3__2_n_0\,
      S(2) => \converge_cnt[15]_i_4__2_n_0\,
      S(1) => \converge_cnt[15]_i_5__2_n_0\,
      S(0) => \converge_cnt[15]_i_6__2_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(16),
      Q => \converge_cnt_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(17),
      Q => \converge_cnt_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(18),
      Q => \converge_cnt_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(19),
      Q => \converge_cnt_reg_n_0_[19]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]_i_2__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[15]_i_2__2_n_0\,
      CO(3) => \converge_cnt_reg[19]_i_2__2_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__2_n_1\,
      CO(1) => \converge_cnt_reg[19]_i_2__2_n_2\,
      CO(0) => \converge_cnt_reg[19]_i_2__2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(19 downto 16),
      S(3) => \converge_cnt[19]_i_3__2_n_0\,
      S(2) => \converge_cnt[19]_i_4__2_n_0\,
      S(1) => \converge_cnt[19]_i_5__2_n_0\,
      S(0) => \converge_cnt[19]_i_6__2_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(1),
      Q => \converge_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(20),
      Q => \converge_cnt_reg_n_0_[20]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(21),
      Q => \converge_cnt_reg_n_0_[21]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]_i_2__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[19]_i_2__2_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__2_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[21]_i_2__2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__2_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => converge_cnt0(21 downto 20),
      S(3) => '0',
      S(2) => '0',
      S(1) => \converge_cnt[21]_i_3__2_n_0\,
      S(0) => \converge_cnt[21]_i_4__2_n_0\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(2),
      Q => \converge_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(3),
      Q => \converge_cnt_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]_i_2__2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[3]_i_2__2_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__2_n_1\,
      CO(1) => \converge_cnt_reg[3]_i_2__2_n_2\,
      CO(0) => \converge_cnt_reg[3]_i_2__2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => \converge_cnt_reg_n_0_[0]\,
      O(3 downto 0) => converge_cnt0(3 downto 0),
      S(3) => \converge_cnt[3]_i_3__2_n_0\,
      S(2) => \converge_cnt[3]_i_4__2_n_0\,
      S(1) => \converge_cnt[3]_i_5__2_n_0\,
      S(0) => \converge_cnt[3]_i_6__2_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(4),
      Q => \converge_cnt_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(5),
      Q => \converge_cnt_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(6),
      Q => \converge_cnt_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(7),
      Q => \converge_cnt_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]_i_2__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[3]_i_2__2_n_0\,
      CO(3) => \converge_cnt_reg[7]_i_2__2_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__2_n_1\,
      CO(1) => \converge_cnt_reg[7]_i_2__2_n_2\,
      CO(0) => \converge_cnt_reg[7]_i_2__2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(7 downto 4),
      S(3) => \converge_cnt[7]_i_3__2_n_0\,
      S(2) => \converge_cnt[7]_i_4__2_n_0\,
      S(1) => \converge_cnt[7]_i_5__2_n_0\,
      S(0) => \converge_cnt[7]_i_6__2_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(8),
      Q => \converge_cnt_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(9),
      Q => \converge_cnt_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(0),
      Q => fs_reg1(0),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(1),
      Q => fs_reg1(1),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(2),
      Q => fs_reg1(2),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(3),
      Q => fs_reg1(3),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(4),
      Q => fs_reg1(4),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(5),
      Q => fs_reg1(5),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(0),
      Q => lf_reg1(0),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(1),
      Q => lf_reg1(1),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(2),
      Q => lf_reg1(2),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(3),
      Q => lf_reg1(3),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(4),
      Q => lf_reg1(4),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(5),
      Q => lf_reg1(5),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => RST_CPLLRESET
    );
\new_txcoeff_done_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_new_txcoeff_req_reg_0,
      Q => new_txcoeff_req_reg1,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => RST_CPLLRESET
    );
\preset_done_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => preset_done
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_done,
      Q => rxeqscan_preset_done,
      R => RST_CPLLRESET
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(0),
      Q => preset_reg1(0),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(1),
      Q => preset_reg1(1),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(2),
      Q => preset_reg1(2),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => RST_CPLLRESET
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid_reg,
      Q => preset_valid_reg1,
      R => RST_CPLLRESET
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => RST_CPLLRESET
    );
\rxeq_adapt_done_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080F00000800000"
    )
        port map (
      I0 => rxeq_adapt_done_reg0,
      I1 => rxeqscan_new_txcoeff_done,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I5 => USER_RXEQ_ADAPT_DONE,
      O => rxeq_adapt_done_reg
    );
\rxeq_adapt_done_i_2__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg0
    );
\rxeq_adapt_done_reg_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44FF4000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => rxeqscan_adapt_done,
      I3 => \rxeq_adapt_done_reg_i_2__2_n_0\,
      I4 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg_reg
    );
\rxeq_adapt_done_reg_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0002FF000002F"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I5 => rxeqscan_new_txcoeff_done,
      O => \rxeq_adapt_done_reg_i_2__2_n_0\
    );
\rxeq_new_txcoeff_req_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I3 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req_reg
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(0),
      Q => txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(10),
      Q => txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(11),
      Q => txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(12),
      Q => txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(13),
      Q => txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(14),
      Q => txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(15),
      Q => txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(16),
      Q => txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(17),
      Q => txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(1),
      Q => txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(2),
      Q => txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(3),
      Q => txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(4),
      Q => txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(5),
      Q => txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(6),
      Q => txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(7),
      Q => txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(8),
      Q => txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(9),
      Q => txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(0),
      Q => txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(1),
      Q => txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(2),
      Q => txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(3),
      Q => txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_80 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req_reg : out STD_LOGIC;
    rxeq_adapt_done_reg : out STD_LOGIC;
    rxeq_adapt_done_reg_reg : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    rxeq_new_txcoeff_req_reg_0 : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rxeq_preset_valid_reg : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_sequential_fsm_rx_reg[0]\ : in STD_LOGIC;
    \rxeq_cnt_reg[1]\ : in STD_LOGIC;
    \FSM_sequential_fsm_rx_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rxeq_cnt_reg[1]_0\ : in STD_LOGIC;
    \rxeq_control_reg2_reg[0]\ : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    \rxeq_preset_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rxeq_txcoeff_reg[17]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \rxeq_fs_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rxeq_lf_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_80 : entity is "PCIeGen1x8If64_rxeq_scan";
end PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_80;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_80 is
  signal \FSM_onehot_fsm[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_3__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_4__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_5__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_7__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_8__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[4]\ : signal is "yes";
  signal adapt_done : STD_LOGIC;
  signal adapt_done_cnt : STD_LOGIC;
  signal \adapt_done_cnt_i_1__1_n_0\ : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt[11]_i_3__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_4__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_5__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_6__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_3__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_4__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_5__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_6__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_3__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_4__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_5__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_6__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_3__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_4__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_3__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_4__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_5__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_6__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_3__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_4__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_5__1_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_6__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__1_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__1_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__1_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__1_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__1_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__1_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_2__1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__1_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__1_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__1_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__1_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[16]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[17]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[18]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[19]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[20]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[21]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  signal preset_done : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_valid_reg1 : STD_LOGIC;
  signal preset_valid_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg0 : STD_LOGIC;
  signal \rxeq_adapt_done_reg_i_2__1_n_0\ : STD_LOGIC;
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal rxeqscan_preset_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[4]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute ASYNC_REG of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rxeq_adapt_done_i_2__1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \rxeq_adapt_done_reg_i_1__1\ : label is "soft_lutpair75";
  attribute ASYNC_REG of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
begin
\FSM_onehot_fsm[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000073333FF07"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => preset_valid_reg2,
      O => \FSM_onehot_fsm[1]_i_1__2_n_0\
    );
\FSM_onehot_fsm[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__2_n_0\
    );
\FSM_onehot_fsm[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA8A8AA"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2__2_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_3__2_n_0\,
      I2 => \FSM_onehot_fsm[3]_i_4__2_n_0\,
      I3 => \converge_cnt_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm[3]_i_5__1_n_0\,
      O => \FSM_onehot_fsm[3]_i_1__2_n_0\
    );
\FSM_onehot_fsm[3]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202020202F20"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => fsm1,
      I5 => \FSM_onehot_fsm_reg_n_0_[2]\,
      O => \FSM_onehot_fsm[3]_i_2__2_n_0\
    );
\FSM_onehot_fsm[3]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6FFFFFFFF6FFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      I1 => \converge_cnt_reg_n_0_[2]\,
      I2 => \converge_cnt_reg_n_0_[10]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[20]\,
      O => \FSM_onehot_fsm[3]_i_3__2_n_0\
    );
\FSM_onehot_fsm[3]_i_4__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7E7EFFFF7EFF7E"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[8]\,
      I3 => \converge_cnt_reg_n_0_[21]\,
      I4 => \out\(0),
      I5 => \out\(1),
      O => \FSM_onehot_fsm[3]_i_4__2_n_0\
    );
\FSM_onehot_fsm[3]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF9"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      I1 => \converge_cnt_reg_n_0_[21]\,
      I2 => \converge_cnt_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[7]\,
      I4 => \FSM_onehot_fsm[3]_i_7__1_n_0\,
      I5 => \FSM_onehot_fsm[3]_i_8__1_n_0\,
      O => \FSM_onehot_fsm[3]_i_5__1_n_0\
    );
\FSM_onehot_fsm[3]_i_6__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      O => fsm1
    );
\FSM_onehot_fsm[3]_i_7__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[16]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[3]_i_7__1_n_0\
    );
\FSM_onehot_fsm[3]_i_8__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFDFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      I1 => \converge_cnt_reg_n_0_[4]\,
      I2 => \converge_cnt_reg_n_0_[12]\,
      I3 => \converge_cnt_reg_n_0_[9]\,
      I4 => \converge_cnt_reg_n_0_[5]\,
      I5 => \converge_cnt_reg_n_0_[6]\,
      O => \FSM_onehot_fsm[3]_i_8__1_n_0\
    );
\FSM_onehot_fsm[4]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm[4]_i_2__1_n_0\,
      O => \FSM_onehot_fsm[4]_i_1__2_n_0\
    );
\FSM_onehot_fsm[4]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3__2_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4__1_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_5__1_n_0\,
      I3 => \FSM_onehot_fsm[4]_i_6__1_n_0\,
      I4 => \FSM_onehot_fsm[4]_i_7__1_n_0\,
      I5 => \FSM_onehot_fsm[4]_i_8__1_n_0\,
      O => \FSM_onehot_fsm[4]_i_2__1_n_0\
    );
\FSM_onehot_fsm[4]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02020202FF000000"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_3__2_n_0\
    );
\FSM_onehot_fsm[4]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00004B00004B0000"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \converge_cnt_reg_n_0_[21]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[10]\,
      O => \FSM_onehot_fsm[4]_i_4__1_n_0\
    );
\FSM_onehot_fsm[4]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000810000810000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[8]\,
      I2 => \converge_cnt_reg_n_0_[3]\,
      I3 => \converge_cnt_reg_n_0_[20]\,
      I4 => \converge_cnt_reg_n_0_[21]\,
      I5 => \converge_cnt_reg_n_0_[14]\,
      O => \FSM_onehot_fsm[4]_i_5__1_n_0\
    );
\FSM_onehot_fsm[4]_i_6__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000024"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[0]\,
      I3 => \converge_cnt_reg_n_0_[5]\,
      I4 => \converge_cnt_reg_n_0_[4]\,
      O => \FSM_onehot_fsm[4]_i_6__1_n_0\
    );
\FSM_onehot_fsm[4]_i_7__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \converge_cnt_reg_n_0_[11]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[9]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[4]_i_7__1_n_0\
    );
\FSM_onehot_fsm[4]_i_8__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      I1 => \converge_cnt_reg_n_0_[6]\,
      I2 => \converge_cnt_reg_n_0_[16]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[19]\,
      I5 => \converge_cnt_reg_n_0_[7]\,
      O => \FSM_onehot_fsm[4]_i_8__1_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEEEEEE"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[0]\,
      I1 => \rxeq_cnt_reg[1]\,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      O => D(0)
    );
\FSM_sequential_fsm_rx[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0CAF0CA0FF000F00"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => \rxeq_cnt_reg[1]_0\,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \rxeq_control_reg2_reg[0]\,
      I5 => \FSM_sequential_fsm_rx_reg[2]\(0),
      O => D(1)
    );
\FSM_sequential_fsm_rx[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F083FC8330833C8"
    )
        port map (
      I0 => rxeqscan_preset_done,
      I1 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I4 => \rxeq_cnt_reg[1]_0\,
      I5 => \rxeq_control_reg2_reg[0]\,
      O => D(2)
    );
\adapt_done_cnt_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF2A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \out\(0),
      I2 => \out\(1),
      I3 => adapt_done_cnt,
      I4 => adapt_done_cnt_reg_n_0,
      O => \adapt_done_cnt_i_1__1_n_0\
    );
\adapt_done_cnt_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF444744444447"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => fsm1,
      O => adapt_done_cnt
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \adapt_done_cnt_i_1__1_n_0\,
      Q => adapt_done_cnt_reg_n_0,
      R => RST_CPLLRESET
    );
\adapt_done_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(1),
      I3 => \out\(0),
      I4 => new_txcoeff_req_reg2,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => RST_CPLLRESET
    );
\converge_cnt[0]_i_1__9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(0)
    );
\converge_cnt[10]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(10)
    );
\converge_cnt[11]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(11)
    );
\converge_cnt[11]_i_3__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      O => \converge_cnt[11]_i_3__1_n_0\
    );
\converge_cnt[11]_i_4__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      O => \converge_cnt[11]_i_4__1_n_0\
    );
\converge_cnt[11]_i_5__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[9]\,
      O => \converge_cnt[11]_i_5__1_n_0\
    );
\converge_cnt[11]_i_6__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[8]\,
      O => \converge_cnt[11]_i_6__1_n_0\
    );
\converge_cnt[12]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(12)
    );
\converge_cnt[13]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(13)
    );
\converge_cnt[14]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(14)
    );
\converge_cnt[15]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(15)
    );
\converge_cnt[15]_i_3__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[15]\,
      O => \converge_cnt[15]_i_3__1_n_0\
    );
\converge_cnt[15]_i_4__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[14]\,
      O => \converge_cnt[15]_i_4__1_n_0\
    );
\converge_cnt[15]_i_5__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[13]\,
      O => \converge_cnt[15]_i_5__1_n_0\
    );
\converge_cnt[15]_i_6__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      O => \converge_cnt[15]_i_6__1_n_0\
    );
\converge_cnt[16]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(16)
    );
\converge_cnt[17]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(17)
    );
\converge_cnt[18]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(18)
    );
\converge_cnt[19]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(19)
    );
\converge_cnt[19]_i_3__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      O => \converge_cnt[19]_i_3__1_n_0\
    );
\converge_cnt[19]_i_4__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[18]\,
      O => \converge_cnt[19]_i_4__1_n_0\
    );
\converge_cnt[19]_i_5__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[17]\,
      O => \converge_cnt[19]_i_5__1_n_0\
    );
\converge_cnt[19]_i_6__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[16]\,
      O => \converge_cnt[19]_i_6__1_n_0\
    );
\converge_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(1)
    );
\converge_cnt[20]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(20)
    );
\converge_cnt[21]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(21)
    );
\converge_cnt[21]_i_3__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[21]\,
      O => \converge_cnt[21]_i_3__1_n_0\
    );
\converge_cnt[21]_i_4__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      O => \converge_cnt[21]_i_4__1_n_0\
    );
\converge_cnt[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(2)
    );
\converge_cnt[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(3)
    );
\converge_cnt[3]_i_3__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[3]\,
      O => \converge_cnt[3]_i_3__1_n_0\
    );
\converge_cnt[3]_i_4__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      O => \converge_cnt[3]_i_4__1_n_0\
    );
\converge_cnt[3]_i_5__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      O => \converge_cnt[3]_i_5__1_n_0\
    );
\converge_cnt[3]_i_6__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      O => \converge_cnt[3]_i_6__1_n_0\
    );
\converge_cnt[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(4)
    );
\converge_cnt[5]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(5)
    );
\converge_cnt[6]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(6)
    );
\converge_cnt[7]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(7)
    );
\converge_cnt[7]_i_3__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[7]\,
      O => \converge_cnt[7]_i_3__1_n_0\
    );
\converge_cnt[7]_i_4__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[6]\,
      O => \converge_cnt[7]_i_4__1_n_0\
    );
\converge_cnt[7]_i_5__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[5]\,
      O => \converge_cnt[7]_i_5__1_n_0\
    );
\converge_cnt[7]_i_6__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[4]\,
      O => \converge_cnt[7]_i_6__1_n_0\
    );
\converge_cnt[8]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(8)
    );
\converge_cnt[9]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(0),
      Q => \converge_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(10),
      Q => \converge_cnt_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(11),
      Q => \converge_cnt_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]_i_2__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[7]_i_2__1_n_0\,
      CO(3) => \converge_cnt_reg[11]_i_2__1_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__1_n_1\,
      CO(1) => \converge_cnt_reg[11]_i_2__1_n_2\,
      CO(0) => \converge_cnt_reg[11]_i_2__1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(11 downto 8),
      S(3) => \converge_cnt[11]_i_3__1_n_0\,
      S(2) => \converge_cnt[11]_i_4__1_n_0\,
      S(1) => \converge_cnt[11]_i_5__1_n_0\,
      S(0) => \converge_cnt[11]_i_6__1_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(12),
      Q => \converge_cnt_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(13),
      Q => \converge_cnt_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(14),
      Q => \converge_cnt_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(15),
      Q => \converge_cnt_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]_i_2__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[11]_i_2__1_n_0\,
      CO(3) => \converge_cnt_reg[15]_i_2__1_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__1_n_1\,
      CO(1) => \converge_cnt_reg[15]_i_2__1_n_2\,
      CO(0) => \converge_cnt_reg[15]_i_2__1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(15 downto 12),
      S(3) => \converge_cnt[15]_i_3__1_n_0\,
      S(2) => \converge_cnt[15]_i_4__1_n_0\,
      S(1) => \converge_cnt[15]_i_5__1_n_0\,
      S(0) => \converge_cnt[15]_i_6__1_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(16),
      Q => \converge_cnt_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(17),
      Q => \converge_cnt_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(18),
      Q => \converge_cnt_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(19),
      Q => \converge_cnt_reg_n_0_[19]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]_i_2__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[15]_i_2__1_n_0\,
      CO(3) => \converge_cnt_reg[19]_i_2__1_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__1_n_1\,
      CO(1) => \converge_cnt_reg[19]_i_2__1_n_2\,
      CO(0) => \converge_cnt_reg[19]_i_2__1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(19 downto 16),
      S(3) => \converge_cnt[19]_i_3__1_n_0\,
      S(2) => \converge_cnt[19]_i_4__1_n_0\,
      S(1) => \converge_cnt[19]_i_5__1_n_0\,
      S(0) => \converge_cnt[19]_i_6__1_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(1),
      Q => \converge_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(20),
      Q => \converge_cnt_reg_n_0_[20]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(21),
      Q => \converge_cnt_reg_n_0_[21]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]_i_2__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[19]_i_2__1_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[21]_i_2__1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => converge_cnt0(21 downto 20),
      S(3) => '0',
      S(2) => '0',
      S(1) => \converge_cnt[21]_i_3__1_n_0\,
      S(0) => \converge_cnt[21]_i_4__1_n_0\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(2),
      Q => \converge_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(3),
      Q => \converge_cnt_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]_i_2__1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[3]_i_2__1_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__1_n_1\,
      CO(1) => \converge_cnt_reg[3]_i_2__1_n_2\,
      CO(0) => \converge_cnt_reg[3]_i_2__1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => \converge_cnt_reg_n_0_[0]\,
      O(3 downto 0) => converge_cnt0(3 downto 0),
      S(3) => \converge_cnt[3]_i_3__1_n_0\,
      S(2) => \converge_cnt[3]_i_4__1_n_0\,
      S(1) => \converge_cnt[3]_i_5__1_n_0\,
      S(0) => \converge_cnt[3]_i_6__1_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(4),
      Q => \converge_cnt_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(5),
      Q => \converge_cnt_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(6),
      Q => \converge_cnt_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(7),
      Q => \converge_cnt_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]_i_2__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[3]_i_2__1_n_0\,
      CO(3) => \converge_cnt_reg[7]_i_2__1_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__1_n_1\,
      CO(1) => \converge_cnt_reg[7]_i_2__1_n_2\,
      CO(0) => \converge_cnt_reg[7]_i_2__1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(7 downto 4),
      S(3) => \converge_cnt[7]_i_3__1_n_0\,
      S(2) => \converge_cnt[7]_i_4__1_n_0\,
      S(1) => \converge_cnt[7]_i_5__1_n_0\,
      S(0) => \converge_cnt[7]_i_6__1_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(8),
      Q => \converge_cnt_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(9),
      Q => \converge_cnt_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(0),
      Q => fs_reg1(0),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(1),
      Q => fs_reg1(1),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(2),
      Q => fs_reg1(2),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(3),
      Q => fs_reg1(3),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(4),
      Q => fs_reg1(4),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(5),
      Q => fs_reg1(5),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(0),
      Q => lf_reg1(0),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(1),
      Q => lf_reg1(1),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(2),
      Q => lf_reg1(2),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(3),
      Q => lf_reg1(3),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(4),
      Q => lf_reg1(4),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(5),
      Q => lf_reg1(5),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => RST_CPLLRESET
    );
\new_txcoeff_done_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_new_txcoeff_req_reg_0,
      Q => new_txcoeff_req_reg1,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => RST_CPLLRESET
    );
\preset_done_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => preset_done
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_done,
      Q => rxeqscan_preset_done,
      R => RST_CPLLRESET
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(0),
      Q => preset_reg1(0),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(1),
      Q => preset_reg1(1),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(2),
      Q => preset_reg1(2),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => RST_CPLLRESET
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid_reg,
      Q => preset_valid_reg1,
      R => RST_CPLLRESET
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => RST_CPLLRESET
    );
\rxeq_adapt_done_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080F00000800000"
    )
        port map (
      I0 => rxeq_adapt_done_reg0,
      I1 => rxeqscan_new_txcoeff_done,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I5 => USER_RXEQ_ADAPT_DONE,
      O => rxeq_adapt_done_reg
    );
\rxeq_adapt_done_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg0
    );
\rxeq_adapt_done_reg_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44FF4000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => rxeqscan_adapt_done,
      I3 => \rxeq_adapt_done_reg_i_2__1_n_0\,
      I4 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg_reg
    );
\rxeq_adapt_done_reg_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0002FF000002F"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I5 => rxeqscan_new_txcoeff_done,
      O => \rxeq_adapt_done_reg_i_2__1_n_0\
    );
\rxeq_new_txcoeff_req_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I3 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req_reg
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(0),
      Q => txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(10),
      Q => txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(11),
      Q => txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(12),
      Q => txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(13),
      Q => txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(14),
      Q => txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(15),
      Q => txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(16),
      Q => txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(17),
      Q => txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(1),
      Q => txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(2),
      Q => txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(3),
      Q => txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(4),
      Q => txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(5),
      Q => txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(6),
      Q => txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(7),
      Q => txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(8),
      Q => txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(9),
      Q => txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(0),
      Q => txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(1),
      Q => txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(2),
      Q => txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(3),
      Q => txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_82 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req_reg : out STD_LOGIC;
    rxeq_adapt_done_reg : out STD_LOGIC;
    rxeq_adapt_done_reg_reg : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    rxeq_new_txcoeff_req_reg_0 : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rxeq_preset_valid_reg : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_sequential_fsm_rx_reg[0]\ : in STD_LOGIC;
    \rxeq_cnt_reg[1]\ : in STD_LOGIC;
    \FSM_sequential_fsm_rx_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rxeq_cnt_reg[1]_0\ : in STD_LOGIC;
    \rxeq_control_reg2_reg[0]\ : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    \rxeq_preset_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rxeq_txcoeff_reg[17]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \rxeq_fs_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rxeq_lf_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_82 : entity is "PCIeGen1x8If64_rxeq_scan";
end PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_82;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_82 is
  signal \FSM_onehot_fsm[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_3__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_4__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_5__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_7__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_8__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[4]\ : signal is "yes";
  signal adapt_done : STD_LOGIC;
  signal adapt_done_cnt : STD_LOGIC;
  signal \adapt_done_cnt_i_1__0_n_0\ : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt[11]_i_3__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_4__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_5__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_6__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_3__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_4__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_5__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_6__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_3__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_4__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_5__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_6__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_3__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_4__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_5__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_6__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_4__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_5__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_6__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[16]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[17]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[18]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[19]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[20]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[21]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  signal preset_done : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_valid_reg1 : STD_LOGIC;
  signal preset_valid_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg0 : STD_LOGIC;
  signal \rxeq_adapt_done_reg_i_2__0_n_0\ : STD_LOGIC;
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal rxeqscan_preset_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[4]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute ASYNC_REG of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \rxeq_adapt_done_i_2__0\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \rxeq_adapt_done_reg_i_1__0\ : label is "soft_lutpair53";
  attribute ASYNC_REG of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
begin
\FSM_onehot_fsm[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000073333FF07"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => preset_valid_reg2,
      O => \FSM_onehot_fsm[1]_i_1__1_n_0\
    );
\FSM_onehot_fsm[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__1_n_0\
    );
\FSM_onehot_fsm[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA8A8AA"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2__1_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_3__1_n_0\,
      I2 => \FSM_onehot_fsm[3]_i_4__1_n_0\,
      I3 => \converge_cnt_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm[3]_i_5__0_n_0\,
      O => \FSM_onehot_fsm[3]_i_1__1_n_0\
    );
\FSM_onehot_fsm[3]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202020202F20"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => fsm1,
      I5 => \FSM_onehot_fsm_reg_n_0_[2]\,
      O => \FSM_onehot_fsm[3]_i_2__1_n_0\
    );
\FSM_onehot_fsm[3]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6FFFFFFFF6FFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      I1 => \converge_cnt_reg_n_0_[2]\,
      I2 => \converge_cnt_reg_n_0_[10]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[20]\,
      O => \FSM_onehot_fsm[3]_i_3__1_n_0\
    );
\FSM_onehot_fsm[3]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7E7EFFFF7EFF7E"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[8]\,
      I3 => \converge_cnt_reg_n_0_[21]\,
      I4 => \out\(0),
      I5 => \out\(1),
      O => \FSM_onehot_fsm[3]_i_4__1_n_0\
    );
\FSM_onehot_fsm[3]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF9"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      I1 => \converge_cnt_reg_n_0_[21]\,
      I2 => \converge_cnt_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[7]\,
      I4 => \FSM_onehot_fsm[3]_i_7__0_n_0\,
      I5 => \FSM_onehot_fsm[3]_i_8__0_n_0\,
      O => \FSM_onehot_fsm[3]_i_5__0_n_0\
    );
\FSM_onehot_fsm[3]_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      O => fsm1
    );
\FSM_onehot_fsm[3]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[16]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[3]_i_7__0_n_0\
    );
\FSM_onehot_fsm[3]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFDFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      I1 => \converge_cnt_reg_n_0_[4]\,
      I2 => \converge_cnt_reg_n_0_[12]\,
      I3 => \converge_cnt_reg_n_0_[9]\,
      I4 => \converge_cnt_reg_n_0_[5]\,
      I5 => \converge_cnt_reg_n_0_[6]\,
      O => \FSM_onehot_fsm[3]_i_8__0_n_0\
    );
\FSM_onehot_fsm[4]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm[4]_i_2__0_n_0\,
      O => \FSM_onehot_fsm[4]_i_1__1_n_0\
    );
\FSM_onehot_fsm[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3__1_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4__0_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_5__0_n_0\,
      I3 => \FSM_onehot_fsm[4]_i_6__0_n_0\,
      I4 => \FSM_onehot_fsm[4]_i_7__0_n_0\,
      I5 => \FSM_onehot_fsm[4]_i_8__0_n_0\,
      O => \FSM_onehot_fsm[4]_i_2__0_n_0\
    );
\FSM_onehot_fsm[4]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02020202FF000000"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_3__1_n_0\
    );
\FSM_onehot_fsm[4]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00004B00004B0000"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \converge_cnt_reg_n_0_[21]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[10]\,
      O => \FSM_onehot_fsm[4]_i_4__0_n_0\
    );
\FSM_onehot_fsm[4]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000810000810000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[8]\,
      I2 => \converge_cnt_reg_n_0_[3]\,
      I3 => \converge_cnt_reg_n_0_[20]\,
      I4 => \converge_cnt_reg_n_0_[21]\,
      I5 => \converge_cnt_reg_n_0_[14]\,
      O => \FSM_onehot_fsm[4]_i_5__0_n_0\
    );
\FSM_onehot_fsm[4]_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000024"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[0]\,
      I3 => \converge_cnt_reg_n_0_[5]\,
      I4 => \converge_cnt_reg_n_0_[4]\,
      O => \FSM_onehot_fsm[4]_i_6__0_n_0\
    );
\FSM_onehot_fsm[4]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \converge_cnt_reg_n_0_[11]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[9]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[4]_i_7__0_n_0\
    );
\FSM_onehot_fsm[4]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      I1 => \converge_cnt_reg_n_0_[6]\,
      I2 => \converge_cnt_reg_n_0_[16]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[19]\,
      I5 => \converge_cnt_reg_n_0_[7]\,
      O => \FSM_onehot_fsm[4]_i_8__0_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEEEEEE"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[0]\,
      I1 => \rxeq_cnt_reg[1]\,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      O => D(0)
    );
\FSM_sequential_fsm_rx[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0CAF0CA0FF000F00"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => \rxeq_cnt_reg[1]_0\,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \rxeq_control_reg2_reg[0]\,
      I5 => \FSM_sequential_fsm_rx_reg[2]\(0),
      O => D(1)
    );
\FSM_sequential_fsm_rx[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F083FC8330833C8"
    )
        port map (
      I0 => rxeqscan_preset_done,
      I1 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I4 => \rxeq_cnt_reg[1]_0\,
      I5 => \rxeq_control_reg2_reg[0]\,
      O => D(2)
    );
\adapt_done_cnt_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF2A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \out\(0),
      I2 => \out\(1),
      I3 => adapt_done_cnt,
      I4 => adapt_done_cnt_reg_n_0,
      O => \adapt_done_cnt_i_1__0_n_0\
    );
\adapt_done_cnt_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF444744444447"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => fsm1,
      O => adapt_done_cnt
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \adapt_done_cnt_i_1__0_n_0\,
      Q => adapt_done_cnt_reg_n_0,
      R => RST_CPLLRESET
    );
\adapt_done_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(1),
      I3 => \out\(0),
      I4 => new_txcoeff_req_reg2,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => RST_CPLLRESET
    );
\converge_cnt[0]_i_1__8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(0)
    );
\converge_cnt[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(10)
    );
\converge_cnt[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(11)
    );
\converge_cnt[11]_i_3__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      O => \converge_cnt[11]_i_3__0_n_0\
    );
\converge_cnt[11]_i_4__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      O => \converge_cnt[11]_i_4__0_n_0\
    );
\converge_cnt[11]_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[9]\,
      O => \converge_cnt[11]_i_5__0_n_0\
    );
\converge_cnt[11]_i_6__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[8]\,
      O => \converge_cnt[11]_i_6__0_n_0\
    );
\converge_cnt[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(12)
    );
\converge_cnt[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(13)
    );
\converge_cnt[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(14)
    );
\converge_cnt[15]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(15)
    );
\converge_cnt[15]_i_3__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[15]\,
      O => \converge_cnt[15]_i_3__0_n_0\
    );
\converge_cnt[15]_i_4__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[14]\,
      O => \converge_cnt[15]_i_4__0_n_0\
    );
\converge_cnt[15]_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[13]\,
      O => \converge_cnt[15]_i_5__0_n_0\
    );
\converge_cnt[15]_i_6__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      O => \converge_cnt[15]_i_6__0_n_0\
    );
\converge_cnt[16]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(16)
    );
\converge_cnt[17]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(17)
    );
\converge_cnt[18]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(18)
    );
\converge_cnt[19]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(19)
    );
\converge_cnt[19]_i_3__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      O => \converge_cnt[19]_i_3__0_n_0\
    );
\converge_cnt[19]_i_4__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[18]\,
      O => \converge_cnt[19]_i_4__0_n_0\
    );
\converge_cnt[19]_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[17]\,
      O => \converge_cnt[19]_i_5__0_n_0\
    );
\converge_cnt[19]_i_6__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[16]\,
      O => \converge_cnt[19]_i_6__0_n_0\
    );
\converge_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(1)
    );
\converge_cnt[20]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(20)
    );
\converge_cnt[21]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(21)
    );
\converge_cnt[21]_i_3__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[21]\,
      O => \converge_cnt[21]_i_3__0_n_0\
    );
\converge_cnt[21]_i_4__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      O => \converge_cnt[21]_i_4__0_n_0\
    );
\converge_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(2)
    );
\converge_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(3)
    );
\converge_cnt[3]_i_3__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[3]\,
      O => \converge_cnt[3]_i_3__0_n_0\
    );
\converge_cnt[3]_i_4__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      O => \converge_cnt[3]_i_4__0_n_0\
    );
\converge_cnt[3]_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      O => \converge_cnt[3]_i_5__0_n_0\
    );
\converge_cnt[3]_i_6__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      O => \converge_cnt[3]_i_6__0_n_0\
    );
\converge_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(4)
    );
\converge_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(5)
    );
\converge_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(6)
    );
\converge_cnt[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(7)
    );
\converge_cnt[7]_i_3__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[7]\,
      O => \converge_cnt[7]_i_3__0_n_0\
    );
\converge_cnt[7]_i_4__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[6]\,
      O => \converge_cnt[7]_i_4__0_n_0\
    );
\converge_cnt[7]_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[5]\,
      O => \converge_cnt[7]_i_5__0_n_0\
    );
\converge_cnt[7]_i_6__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[4]\,
      O => \converge_cnt[7]_i_6__0_n_0\
    );
\converge_cnt[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(8)
    );
\converge_cnt[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(0),
      Q => \converge_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(10),
      Q => \converge_cnt_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(11),
      Q => \converge_cnt_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[7]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[11]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[11]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[11]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(11 downto 8),
      S(3) => \converge_cnt[11]_i_3__0_n_0\,
      S(2) => \converge_cnt[11]_i_4__0_n_0\,
      S(1) => \converge_cnt[11]_i_5__0_n_0\,
      S(0) => \converge_cnt[11]_i_6__0_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(12),
      Q => \converge_cnt_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(13),
      Q => \converge_cnt_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(14),
      Q => \converge_cnt_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(15),
      Q => \converge_cnt_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[11]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[15]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[15]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[15]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(15 downto 12),
      S(3) => \converge_cnt[15]_i_3__0_n_0\,
      S(2) => \converge_cnt[15]_i_4__0_n_0\,
      S(1) => \converge_cnt[15]_i_5__0_n_0\,
      S(0) => \converge_cnt[15]_i_6__0_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(16),
      Q => \converge_cnt_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(17),
      Q => \converge_cnt_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(18),
      Q => \converge_cnt_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(19),
      Q => \converge_cnt_reg_n_0_[19]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[15]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[19]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[19]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[19]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(19 downto 16),
      S(3) => \converge_cnt[19]_i_3__0_n_0\,
      S(2) => \converge_cnt[19]_i_4__0_n_0\,
      S(1) => \converge_cnt[19]_i_5__0_n_0\,
      S(0) => \converge_cnt[19]_i_6__0_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(1),
      Q => \converge_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(20),
      Q => \converge_cnt_reg_n_0_[20]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(21),
      Q => \converge_cnt_reg_n_0_[21]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[19]_i_2__0_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[21]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => converge_cnt0(21 downto 20),
      S(3) => '0',
      S(2) => '0',
      S(1) => \converge_cnt[21]_i_3__0_n_0\,
      S(0) => \converge_cnt[21]_i_4__0_n_0\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(2),
      Q => \converge_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(3),
      Q => \converge_cnt_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[3]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[3]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[3]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => \converge_cnt_reg_n_0_[0]\,
      O(3 downto 0) => converge_cnt0(3 downto 0),
      S(3) => \converge_cnt[3]_i_3__0_n_0\,
      S(2) => \converge_cnt[3]_i_4__0_n_0\,
      S(1) => \converge_cnt[3]_i_5__0_n_0\,
      S(0) => \converge_cnt[3]_i_6__0_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(4),
      Q => \converge_cnt_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(5),
      Q => \converge_cnt_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(6),
      Q => \converge_cnt_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(7),
      Q => \converge_cnt_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[3]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[7]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[7]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[7]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(7 downto 4),
      S(3) => \converge_cnt[7]_i_3__0_n_0\,
      S(2) => \converge_cnt[7]_i_4__0_n_0\,
      S(1) => \converge_cnt[7]_i_5__0_n_0\,
      S(0) => \converge_cnt[7]_i_6__0_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(8),
      Q => \converge_cnt_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => converge_cnt(9),
      Q => \converge_cnt_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(0),
      Q => fs_reg1(0),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(1),
      Q => fs_reg1(1),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(2),
      Q => fs_reg1(2),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(3),
      Q => fs_reg1(3),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(4),
      Q => fs_reg1(4),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_fs_reg[5]\(5),
      Q => fs_reg1(5),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(0),
      Q => lf_reg1(0),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(1),
      Q => lf_reg1(1),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(2),
      Q => lf_reg1(2),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(3),
      Q => lf_reg1(3),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(4),
      Q => lf_reg1(4),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_lf_reg[5]\(5),
      Q => lf_reg1(5),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => RST_CPLLRESET
    );
\new_txcoeff_done_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_new_txcoeff_req_reg_0,
      Q => new_txcoeff_req_reg1,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => RST_CPLLRESET
    );
\preset_done_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => preset_done
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_done,
      Q => rxeqscan_preset_done,
      R => RST_CPLLRESET
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(0),
      Q => preset_reg1(0),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(1),
      Q => preset_reg1(1),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset_reg[2]\(2),
      Q => preset_reg1(2),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => RST_CPLLRESET
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid_reg,
      Q => preset_valid_reg1,
      R => RST_CPLLRESET
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => RST_CPLLRESET
    );
\rxeq_adapt_done_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080F00000800000"
    )
        port map (
      I0 => rxeq_adapt_done_reg0,
      I1 => rxeqscan_new_txcoeff_done,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I5 => USER_RXEQ_ADAPT_DONE,
      O => rxeq_adapt_done_reg
    );
\rxeq_adapt_done_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg0
    );
\rxeq_adapt_done_reg_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44FF4000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => rxeqscan_adapt_done,
      I3 => \rxeq_adapt_done_reg_i_2__0_n_0\,
      I4 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg_reg
    );
\rxeq_adapt_done_reg_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0002FF000002F"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I5 => rxeqscan_new_txcoeff_done,
      O => \rxeq_adapt_done_reg_i_2__0_n_0\
    );
\rxeq_new_txcoeff_req_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I3 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req_reg
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(0),
      Q => txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(10),
      Q => txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(11),
      Q => txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(12),
      Q => txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(13),
      Q => txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(14),
      Q => txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(15),
      Q => txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(16),
      Q => txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(17),
      Q => txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(1),
      Q => txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(2),
      Q => txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(3),
      Q => txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(4),
      Q => txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(5),
      Q => txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(6),
      Q => txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(7),
      Q => txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(8),
      Q => txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(9),
      Q => txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(0),
      Q => txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(1),
      Q => txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(2),
      Q => txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => Q(3),
      Q => txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_86 is
  port (
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req_reg : out STD_LOGIC;
    rxeq_adapt_done_reg : out STD_LOGIC;
    rxeq_adapt_done_reg_reg : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    rxeq_new_txcoeff_req_reg_0 : in STD_LOGIC;
    CLK : in STD_LOGIC;
    rxeq_preset_valid_reg : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_sequential_fsm_rx_reg[0]\ : in STD_LOGIC;
    \rxeq_cnt_reg[1]\ : in STD_LOGIC;
    \FSM_sequential_fsm_rx_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \rxeq_cnt_reg[1]_0\ : in STD_LOGIC;
    \rxeq_control_reg2_reg[0]\ : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    USER_RXEQ_ADAPT_DONE : in STD_LOGIC;
    \rxeq_preset_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \rxeq_txcoeff_reg[17]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \rxeq_fs_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \rxeq_lf_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_86 : entity is "PCIeGen1x8If64_rxeq_scan";
end PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_86;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_86 is
  signal \FSM_onehot_fsm[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_reg_n_0_[4]\ : signal is "yes";
  signal adapt_done : STD_LOGIC;
  signal adapt_done_cnt : STD_LOGIC;
  signal adapt_done_cnt_i_1_n_0 : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt[11]_i_3_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_4_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_5_n_0\ : STD_LOGIC;
  signal \converge_cnt[11]_i_6_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_3_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_4_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_5_n_0\ : STD_LOGIC;
  signal \converge_cnt[15]_i_6_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_3_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_4_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_5_n_0\ : STD_LOGIC;
  signal \converge_cnt[19]_i_6_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_3_n_0\ : STD_LOGIC;
  signal \converge_cnt[21]_i_4_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_4_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_5_n_0\ : STD_LOGIC;
  signal \converge_cnt[3]_i_6_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_3_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_4_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_5_n_0\ : STD_LOGIC;
  signal \converge_cnt[7]_i_6_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[15]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[19]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[21]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[3]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[10]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[11]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[12]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[13]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[14]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[15]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[16]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[17]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[18]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[19]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[20]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[21]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \converge_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal fsm1 : STD_LOGIC;
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  signal preset_done : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal preset_valid_reg1 : STD_LOGIC;
  signal preset_valid_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg0 : STD_LOGIC;
  signal rxeq_adapt_done_reg_i_2_n_0 : STD_LOGIC;
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal rxeqscan_preset_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_reg[4]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute ASYNC_REG of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute ASYNC_REG of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of rxeq_adapt_done_i_2 : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of rxeq_adapt_done_reg_i_1 : label is "soft_lutpair16";
  attribute ASYNC_REG of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
begin
\FSM_onehot_fsm[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000073333FF07"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I5 => preset_valid_reg2,
      O => \FSM_onehot_fsm[1]_i_1__0_n_0\
    );
\FSM_onehot_fsm[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__0_n_0\
    );
\FSM_onehot_fsm[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA8A8AA"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2__0_n_0\,
      I1 => \FSM_onehot_fsm[3]_i_3__0_n_0\,
      I2 => \FSM_onehot_fsm[3]_i_4__0_n_0\,
      I3 => \converge_cnt_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[2]\,
      I5 => \FSM_onehot_fsm[3]_i_5_n_0\,
      O => \FSM_onehot_fsm[3]_i_1__0_n_0\
    );
\FSM_onehot_fsm[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020202020202F20"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => fsm1,
      I5 => \FSM_onehot_fsm_reg_n_0_[2]\,
      O => \FSM_onehot_fsm[3]_i_2__0_n_0\
    );
\FSM_onehot_fsm[3]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF6FFFFFFFF6FFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      I1 => \converge_cnt_reg_n_0_[2]\,
      I2 => \converge_cnt_reg_n_0_[10]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[20]\,
      O => \FSM_onehot_fsm[3]_i_3__0_n_0\
    );
\FSM_onehot_fsm[3]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7E7EFFFF7EFF7E"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[8]\,
      I3 => \converge_cnt_reg_n_0_[21]\,
      I4 => \out\(0),
      I5 => \out\(1),
      O => \FSM_onehot_fsm[3]_i_4__0_n_0\
    );
\FSM_onehot_fsm[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF9"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      I1 => \converge_cnt_reg_n_0_[21]\,
      I2 => \converge_cnt_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[7]\,
      I4 => \FSM_onehot_fsm[3]_i_7_n_0\,
      I5 => \FSM_onehot_fsm[3]_i_8_n_0\,
      O => \FSM_onehot_fsm[3]_i_5_n_0\
    );
\FSM_onehot_fsm[3]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      O => fsm1
    );
\FSM_onehot_fsm[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[16]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[3]_i_7_n_0\
    );
\FSM_onehot_fsm[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFDFF"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      I1 => \converge_cnt_reg_n_0_[4]\,
      I2 => \converge_cnt_reg_n_0_[12]\,
      I3 => \converge_cnt_reg_n_0_[9]\,
      I4 => \converge_cnt_reg_n_0_[5]\,
      I5 => \converge_cnt_reg_n_0_[6]\,
      O => \FSM_onehot_fsm[3]_i_8_n_0\
    );
\FSM_onehot_fsm[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm[4]_i_2_n_0\,
      O => \FSM_onehot_fsm[4]_i_1__0_n_0\
    );
\FSM_onehot_fsm[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3__0_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_5_n_0\,
      I3 => \FSM_onehot_fsm[4]_i_6_n_0\,
      I4 => \FSM_onehot_fsm[4]_i_7_n_0\,
      I5 => \FSM_onehot_fsm[4]_i_8_n_0\,
      O => \FSM_onehot_fsm[4]_i_2_n_0\
    );
\FSM_onehot_fsm[4]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02020202FF000000"
    )
        port map (
      I0 => \out\(1),
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(0),
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[4]_i_3__0_n_0\
    );
\FSM_onehot_fsm[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00004B00004B0000"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \converge_cnt_reg_n_0_[21]\,
      I3 => \converge_cnt_reg_n_0_[13]\,
      I4 => \converge_cnt_reg_n_0_[14]\,
      I5 => \converge_cnt_reg_n_0_[10]\,
      O => \FSM_onehot_fsm[4]_i_4_n_0\
    );
\FSM_onehot_fsm[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000810000810000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      I1 => \converge_cnt_reg_n_0_[8]\,
      I2 => \converge_cnt_reg_n_0_[3]\,
      I3 => \converge_cnt_reg_n_0_[20]\,
      I4 => \converge_cnt_reg_n_0_[21]\,
      I5 => \converge_cnt_reg_n_0_[14]\,
      O => \FSM_onehot_fsm[4]_i_5_n_0\
    );
\FSM_onehot_fsm[4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000024"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      I1 => \converge_cnt_reg_n_0_[3]\,
      I2 => \converge_cnt_reg_n_0_[0]\,
      I3 => \converge_cnt_reg_n_0_[5]\,
      I4 => \converge_cnt_reg_n_0_[4]\,
      O => \FSM_onehot_fsm[4]_i_6_n_0\
    );
\FSM_onehot_fsm[4]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      I1 => \converge_cnt_reg_n_0_[18]\,
      I2 => \converge_cnt_reg_n_0_[11]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I4 => \converge_cnt_reg_n_0_[9]\,
      I5 => \converge_cnt_reg_n_0_[15]\,
      O => \FSM_onehot_fsm[4]_i_7_n_0\
    );
\FSM_onehot_fsm[4]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      I1 => \converge_cnt_reg_n_0_[6]\,
      I2 => \converge_cnt_reg_n_0_[16]\,
      I3 => \converge_cnt_reg_n_0_[17]\,
      I4 => \converge_cnt_reg_n_0_[19]\,
      I5 => \converge_cnt_reg_n_0_[7]\,
      O => \FSM_onehot_fsm[4]_i_8_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFEEEEEE"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[0]\,
      I1 => \rxeq_cnt_reg[1]\,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      O => D(0)
    );
\FSM_sequential_fsm_rx[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0CAF0CA0FF000F00"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => \rxeq_cnt_reg[1]_0\,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \rxeq_control_reg2_reg[0]\,
      I5 => \FSM_sequential_fsm_rx_reg[2]\(0),
      O => D(1)
    );
\FSM_sequential_fsm_rx[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F083FC8330833C8"
    )
        port map (
      I0 => rxeqscan_preset_done,
      I1 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I4 => \rxeq_cnt_reg[1]_0\,
      I5 => \rxeq_control_reg2_reg[0]\,
      O => D(2)
    );
adapt_done_cnt_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF2A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \out\(0),
      I2 => \out\(1),
      I3 => adapt_done_cnt,
      I4 => adapt_done_cnt_reg_n_0,
      O => adapt_done_cnt_i_1_n_0
    );
adapt_done_cnt_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF444744444447"
    )
        port map (
      I0 => new_txcoeff_req_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => fsm1,
      O => adapt_done_cnt
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => adapt_done_cnt_i_1_n_0,
      Q => adapt_done_cnt_reg_n_0,
      R => RST_CPLLRESET
    );
adapt_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => adapt_done_cnt_reg_n_0,
      I2 => \out\(1),
      I3 => \out\(0),
      I4 => new_txcoeff_req_reg2,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => RST_CPLLRESET
    );
\converge_cnt[0]_i_1__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(0)
    );
\converge_cnt[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(10)
    );
\converge_cnt[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(11)
    );
\converge_cnt[11]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[11]\,
      O => \converge_cnt[11]_i_3_n_0\
    );
\converge_cnt[11]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[10]\,
      O => \converge_cnt[11]_i_4_n_0\
    );
\converge_cnt[11]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[9]\,
      O => \converge_cnt[11]_i_5_n_0\
    );
\converge_cnt[11]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[8]\,
      O => \converge_cnt[11]_i_6_n_0\
    );
\converge_cnt[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(12)
    );
\converge_cnt[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(13)
    );
\converge_cnt[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(14)
    );
\converge_cnt[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(15)
    );
\converge_cnt[15]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[15]\,
      O => \converge_cnt[15]_i_3_n_0\
    );
\converge_cnt[15]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[14]\,
      O => \converge_cnt[15]_i_4_n_0\
    );
\converge_cnt[15]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[13]\,
      O => \converge_cnt[15]_i_5_n_0\
    );
\converge_cnt[15]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[12]\,
      O => \converge_cnt[15]_i_6_n_0\
    );
\converge_cnt[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(16)
    );
\converge_cnt[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(17)
    );
\converge_cnt[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(18)
    );
\converge_cnt[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(19)
    );
\converge_cnt[19]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[19]\,
      O => \converge_cnt[19]_i_3_n_0\
    );
\converge_cnt[19]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[18]\,
      O => \converge_cnt[19]_i_4_n_0\
    );
\converge_cnt[19]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[17]\,
      O => \converge_cnt[19]_i_5_n_0\
    );
\converge_cnt[19]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[16]\,
      O => \converge_cnt[19]_i_6_n_0\
    );
\converge_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(1)
    );
\converge_cnt[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(20)
    );
\converge_cnt[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(21)
    );
\converge_cnt[21]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[21]\,
      O => \converge_cnt[21]_i_3_n_0\
    );
\converge_cnt[21]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[20]\,
      O => \converge_cnt[21]_i_4_n_0\
    );
\converge_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(2)
    );
\converge_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(3)
    );
\converge_cnt[3]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[3]\,
      O => \converge_cnt[3]_i_3_n_0\
    );
\converge_cnt[3]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[2]\,
      O => \converge_cnt[3]_i_4_n_0\
    );
\converge_cnt[3]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[1]\,
      O => \converge_cnt[3]_i_5_n_0\
    );
\converge_cnt[3]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[0]\,
      O => \converge_cnt[3]_i_6_n_0\
    );
\converge_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(4)
    );
\converge_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(5)
    );
\converge_cnt[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(6)
    );
\converge_cnt[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(7)
    );
\converge_cnt[7]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[7]\,
      O => \converge_cnt[7]_i_3_n_0\
    );
\converge_cnt[7]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[6]\,
      O => \converge_cnt[7]_i_4_n_0\
    );
\converge_cnt[7]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[5]\,
      O => \converge_cnt[7]_i_5_n_0\
    );
\converge_cnt[7]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \converge_cnt_reg_n_0_[4]\,
      O => \converge_cnt[7]_i_6_n_0\
    );
\converge_cnt[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(8)
    );
\converge_cnt[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888808"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \out\(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \out\(0),
      O => converge_cnt(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(0),
      Q => \converge_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(10),
      Q => \converge_cnt_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(11),
      Q => \converge_cnt_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[11]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[7]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[11]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[11]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[11]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[11]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(11 downto 8),
      S(3) => \converge_cnt[11]_i_3_n_0\,
      S(2) => \converge_cnt[11]_i_4_n_0\,
      S(1) => \converge_cnt[11]_i_5_n_0\,
      S(0) => \converge_cnt[11]_i_6_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(12),
      Q => \converge_cnt_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(13),
      Q => \converge_cnt_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(14),
      Q => \converge_cnt_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(15),
      Q => \converge_cnt_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[15]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[11]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[15]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[15]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[15]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[15]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(15 downto 12),
      S(3) => \converge_cnt[15]_i_3_n_0\,
      S(2) => \converge_cnt[15]_i_4_n_0\,
      S(1) => \converge_cnt[15]_i_5_n_0\,
      S(0) => \converge_cnt[15]_i_6_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(16),
      Q => \converge_cnt_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(17),
      Q => \converge_cnt_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(18),
      Q => \converge_cnt_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(19),
      Q => \converge_cnt_reg_n_0_[19]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[19]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[15]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[19]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[19]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[19]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[19]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(19 downto 16),
      S(3) => \converge_cnt[19]_i_3_n_0\,
      S(2) => \converge_cnt[19]_i_4_n_0\,
      S(1) => \converge_cnt[19]_i_5_n_0\,
      S(0) => \converge_cnt[19]_i_6_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(1),
      Q => \converge_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(20),
      Q => \converge_cnt_reg_n_0_[20]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(21),
      Q => \converge_cnt_reg_n_0_[21]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[21]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[19]_i_2_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[21]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 2) => \NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => converge_cnt0(21 downto 20),
      S(3) => '0',
      S(2) => '0',
      S(1) => \converge_cnt[21]_i_3_n_0\,
      S(0) => \converge_cnt[21]_i_4_n_0\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(2),
      Q => \converge_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(3),
      Q => \converge_cnt_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[3]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[3]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[3]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[3]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[3]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => \converge_cnt_reg_n_0_[0]\,
      O(3 downto 0) => converge_cnt0(3 downto 0),
      S(3) => \converge_cnt[3]_i_3_n_0\,
      S(2) => \converge_cnt[3]_i_4_n_0\,
      S(1) => \converge_cnt[3]_i_5_n_0\,
      S(0) => \converge_cnt[3]_i_6_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(4),
      Q => \converge_cnt_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(5),
      Q => \converge_cnt_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(6),
      Q => \converge_cnt_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(7),
      Q => \converge_cnt_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[3]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[7]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[7]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[7]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[7]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => '0',
      DI(1) => '0',
      DI(0) => '0',
      O(3 downto 0) => converge_cnt0(7 downto 4),
      S(3) => \converge_cnt[7]_i_3_n_0\,
      S(2) => \converge_cnt[7]_i_4_n_0\,
      S(1) => \converge_cnt[7]_i_5_n_0\,
      S(0) => \converge_cnt[7]_i_6_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(8),
      Q => \converge_cnt_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => converge_cnt(9),
      Q => \converge_cnt_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_fs_reg[5]\(0),
      Q => fs_reg1(0),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_fs_reg[5]\(1),
      Q => fs_reg1(1),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_fs_reg[5]\(2),
      Q => fs_reg1(2),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_fs_reg[5]\(3),
      Q => fs_reg1(3),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_fs_reg[5]\(4),
      Q => fs_reg1(4),
      R => RST_CPLLRESET
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_fs_reg[5]\(5),
      Q => fs_reg1(5),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => RST_CPLLRESET
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_lf_reg[5]\(0),
      Q => lf_reg1(0),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_lf_reg[5]\(1),
      Q => lf_reg1(1),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_lf_reg[5]\(2),
      Q => lf_reg1(2),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_lf_reg[5]\(3),
      Q => lf_reg1(3),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_lf_reg[5]\(4),
      Q => lf_reg1(4),
      R => RST_CPLLRESET
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_lf_reg[5]\(5),
      Q => lf_reg1(5),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => RST_CPLLRESET
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => RST_CPLLRESET
    );
new_txcoeff_done_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_new_txcoeff_req_reg_0,
      Q => new_txcoeff_req_reg1,
      R => RST_CPLLRESET
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => RST_CPLLRESET
    );
preset_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => preset_valid_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => preset_done
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => preset_done,
      Q => rxeqscan_preset_done,
      R => RST_CPLLRESET
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_preset_reg[2]\(0),
      Q => preset_reg1(0),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_preset_reg[2]\(1),
      Q => preset_reg1(1),
      R => RST_CPLLRESET
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_preset_reg[2]\(2),
      Q => preset_reg1(2),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => RST_CPLLRESET
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => RST_CPLLRESET
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_preset_valid_reg,
      Q => preset_valid_reg1,
      R => RST_CPLLRESET
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080F00000800000"
    )
        port map (
      I0 => rxeq_adapt_done_reg0,
      I1 => rxeqscan_new_txcoeff_done,
      I2 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I5 => USER_RXEQ_ADAPT_DONE,
      O => rxeq_adapt_done_reg
    );
rxeq_adapt_done_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg0
    );
rxeq_adapt_done_reg_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44FF4000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => rxeqscan_adapt_done,
      I3 => rxeq_adapt_done_reg_i_2_n_0,
      I4 => rxeq_adapt_done_reg_reg_0,
      O => rxeq_adapt_done_reg_reg
    );
rxeq_adapt_done_reg_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0002FF000002F"
    )
        port map (
      I0 => \out\(0),
      I1 => \out\(1),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I3 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I4 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I5 => rxeqscan_new_txcoeff_done,
      O => rxeq_adapt_done_reg_i_2_n_0
    );
rxeq_new_txcoeff_req_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg[2]\(0),
      I1 => \FSM_sequential_fsm_rx_reg[2]\(2),
      I2 => \FSM_sequential_fsm_rx_reg[2]\(1),
      I3 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req_reg
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(0),
      Q => txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(10),
      Q => txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(11),
      Q => txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(12),
      Q => txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(13),
      Q => txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(14),
      Q => txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(15),
      Q => txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(16),
      Q => txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(17),
      Q => txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(1),
      Q => txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(2),
      Q => txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(3),
      Q => txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(4),
      Q => txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(5),
      Q => txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(6),
      Q => txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(7),
      Q => txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(8),
      Q => txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => \rxeq_txcoeff_reg[17]\(9),
      Q => txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => Q(0),
      Q => txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => Q(1),
      Q => txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => Q(2),
      Q => txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => Q(3),
      Q => txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO is
  port (
    rdata : out STD_LOGIC_VECTOR ( 14 downto 0 );
    mim_tx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 14 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO : entity is "unimacro_BRAM_TDP_MACRO";
end PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO;

architecture STRUCTURE of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_52\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_53\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_74\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3) => '1',
      ADDRARDADDR(2) => '1',
      ADDRARDADDR(1) => '1',
      ADDRARDADDR(0) => '1',
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3) => '1',
      ADDRBWRADDR(2) => '1',
      ADDRBWRADDR(1) => '1',
      ADDRBWRADDR(0) => '1',
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => user_clk,
      CLKBWRCLK => user_clk,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31) => '0',
      DIADI(30) => '0',
      DIADI(29) => '0',
      DIADI(28) => '0',
      DIADI(27) => '0',
      DIADI(26) => '0',
      DIADI(25) => '0',
      DIADI(24) => '0',
      DIADI(23) => '0',
      DIADI(22) => '0',
      DIADI(21) => '0',
      DIADI(20) => '0',
      DIADI(19) => '0',
      DIADI(18) => '0',
      DIADI(17) => '0',
      DIADI(16) => '0',
      DIADI(15) => '0',
      DIADI(14) => '0',
      DIADI(13 downto 8) => wdata(14 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31) => '0',
      DIBDI(30) => '0',
      DIBDI(29) => '0',
      DIBDI(28) => '0',
      DIBDI(27) => '0',
      DIBDI(26) => '0',
      DIBDI(25) => '0',
      DIBDI(24) => '0',
      DIBDI(23) => '0',
      DIBDI(22) => '0',
      DIBDI(21) => '0',
      DIBDI(20) => '0',
      DIBDI(19) => '0',
      DIBDI(18) => '0',
      DIBDI(17) => '0',
      DIBDI(16) => '0',
      DIBDI(15) => '0',
      DIBDI(14) => '0',
      DIBDI(13) => '0',
      DIBDI(12) => '0',
      DIBDI(11) => '0',
      DIBDI(10) => '0',
      DIBDI(9) => '0',
      DIBDI(8) => '0',
      DIBDI(7) => '0',
      DIBDI(6) => '0',
      DIBDI(5) => '0',
      DIBDI(4) => '0',
      DIBDI(3) => '0',
      DIBDI(2) => '0',
      DIBDI(1) => '0',
      DIBDI(0) => '0',
      DIPADIP(3) => '0',
      DIPADIP(2) => '0',
      DIPADIP(1) => '0',
      DIPADIP(0) => wdata(8),
      DIPBDIP(3) => '0',
      DIPBDIP(2) => '0',
      DIPBDIP(1) => '0',
      DIPBDIP(0) => '0',
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_52\,
      DOBDO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_53\,
      DOBDO(13 downto 8) => rdata(14 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_74\,
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3) => '1',
      WEA(2) => '1',
      WEA(1) => '1',
      WEA(0) => '1',
      WEBWE(7) => '0',
      WEBWE(6) => '0',
      WEBWE(5) => '0',
      WEBWE(4) => '0',
      WEBWE(3) => '0',
      WEBWE(2) => '0',
      WEBWE(1) => '0',
      WEBWE(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_11 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_tx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_11 : entity is "unimacro_BRAM_TDP_MACRO";
end PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_11;

architecture STRUCTURE of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_11 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
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      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3) => '1',
      ADDRARDADDR(2) => '1',
      ADDRARDADDR(1) => '1',
      ADDRARDADDR(0) => '1',
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3) => '1',
      ADDRBWRADDR(2) => '1',
      ADDRBWRADDR(1) => '1',
      ADDRBWRADDR(0) => '1',
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => user_clk,
      CLKBWRCLK => user_clk,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31) => '0',
      DIADI(30) => '0',
      DIADI(29) => '0',
      DIADI(28) => '0',
      DIADI(27) => '0',
      DIADI(26) => '0',
      DIADI(25) => '0',
      DIADI(24) => '0',
      DIADI(23) => '0',
      DIADI(22) => '0',
      DIADI(21) => '0',
      DIADI(20) => '0',
      DIADI(19) => '0',
      DIADI(18) => '0',
      DIADI(17) => '0',
      DIADI(16) => '0',
      DIADI(15 downto 8) => wdata(16 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31) => '0',
      DIBDI(30) => '0',
      DIBDI(29) => '0',
      DIBDI(28) => '0',
      DIBDI(27) => '0',
      DIBDI(26) => '0',
      DIBDI(25) => '0',
      DIBDI(24) => '0',
      DIBDI(23) => '0',
      DIBDI(22) => '0',
      DIBDI(21) => '0',
      DIBDI(20) => '0',
      DIBDI(19) => '0',
      DIBDI(18) => '0',
      DIBDI(17) => '0',
      DIBDI(16) => '0',
      DIBDI(15) => '0',
      DIBDI(14) => '0',
      DIBDI(13) => '0',
      DIBDI(12) => '0',
      DIBDI(11) => '0',
      DIBDI(10) => '0',
      DIBDI(9) => '0',
      DIBDI(8) => '0',
      DIBDI(7) => '0',
      DIBDI(6) => '0',
      DIBDI(5) => '0',
      DIBDI(4) => '0',
      DIBDI(3) => '0',
      DIBDI(2) => '0',
      DIBDI(1) => '0',
      DIBDI(0) => '0',
      DIPADIP(3) => '0',
      DIPADIP(2) => '0',
      DIPADIP(1) => wdata(17),
      DIPADIP(0) => wdata(8),
      DIPBDIP(3) => '0',
      DIPBDIP(2) => '0',
      DIPBDIP(1) => '0',
      DIPBDIP(0) => '0',
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => rdata(16 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => rdata(17),
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3) => '1',
      WEA(2) => '1',
      WEA(1) => '1',
      WEA(0) => '1',
      WEBWE(7) => '0',
      WEBWE(6) => '0',
      WEBWE(5) => '0',
      WEBWE(4) => '0',
      WEBWE(3) => '0',
      WEBWE(2) => '0',
      WEBWE(1) => '0',
      WEBWE(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_12 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_tx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_12 : entity is "unimacro_BRAM_TDP_MACRO";
end PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_12;

architecture STRUCTURE of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_12 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3) => '1',
      ADDRARDADDR(2) => '1',
      ADDRARDADDR(1) => '1',
      ADDRARDADDR(0) => '1',
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3) => '1',
      ADDRBWRADDR(2) => '1',
      ADDRBWRADDR(1) => '1',
      ADDRBWRADDR(0) => '1',
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => user_clk,
      CLKBWRCLK => user_clk,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31) => '0',
      DIADI(30) => '0',
      DIADI(29) => '0',
      DIADI(28) => '0',
      DIADI(27) => '0',
      DIADI(26) => '0',
      DIADI(25) => '0',
      DIADI(24) => '0',
      DIADI(23) => '0',
      DIADI(22) => '0',
      DIADI(21) => '0',
      DIADI(20) => '0',
      DIADI(19) => '0',
      DIADI(18) => '0',
      DIADI(17) => '0',
      DIADI(16) => '0',
      DIADI(15 downto 8) => wdata(16 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31) => '0',
      DIBDI(30) => '0',
      DIBDI(29) => '0',
      DIBDI(28) => '0',
      DIBDI(27) => '0',
      DIBDI(26) => '0',
      DIBDI(25) => '0',
      DIBDI(24) => '0',
      DIBDI(23) => '0',
      DIBDI(22) => '0',
      DIBDI(21) => '0',
      DIBDI(20) => '0',
      DIBDI(19) => '0',
      DIBDI(18) => '0',
      DIBDI(17) => '0',
      DIBDI(16) => '0',
      DIBDI(15) => '0',
      DIBDI(14) => '0',
      DIBDI(13) => '0',
      DIBDI(12) => '0',
      DIBDI(11) => '0',
      DIBDI(10) => '0',
      DIBDI(9) => '0',
      DIBDI(8) => '0',
      DIBDI(7) => '0',
      DIBDI(6) => '0',
      DIBDI(5) => '0',
      DIBDI(4) => '0',
      DIBDI(3) => '0',
      DIBDI(2) => '0',
      DIBDI(1) => '0',
      DIBDI(0) => '0',
      DIPADIP(3) => '0',
      DIPADIP(2) => '0',
      DIPADIP(1) => wdata(17),
      DIPADIP(0) => wdata(8),
      DIPBDIP(3) => '0',
      DIPBDIP(2) => '0',
      DIPBDIP(1) => '0',
      DIPBDIP(0) => '0',
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => rdata(16 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => rdata(17),
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3) => '1',
      WEA(2) => '1',
      WEA(1) => '1',
      WEA(0) => '1',
      WEBWE(7) => '0',
      WEBWE(6) => '0',
      WEBWE(5) => '0',
      WEBWE(4) => '0',
      WEBWE(3) => '0',
      WEBWE(2) => '0',
      WEBWE(1) => '0',
      WEBWE(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_13 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_tx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_13 : entity is "unimacro_BRAM_TDP_MACRO";
end PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_13;

architecture STRUCTURE of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_13 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
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      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3) => '1',
      ADDRARDADDR(2) => '1',
      ADDRARDADDR(1) => '1',
      ADDRARDADDR(0) => '1',
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3) => '1',
      ADDRBWRADDR(2) => '1',
      ADDRBWRADDR(1) => '1',
      ADDRBWRADDR(0) => '1',
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => user_clk,
      CLKBWRCLK => user_clk,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31) => '0',
      DIADI(30) => '0',
      DIADI(29) => '0',
      DIADI(28) => '0',
      DIADI(27) => '0',
      DIADI(26) => '0',
      DIADI(25) => '0',
      DIADI(24) => '0',
      DIADI(23) => '0',
      DIADI(22) => '0',
      DIADI(21) => '0',
      DIADI(20) => '0',
      DIADI(19) => '0',
      DIADI(18) => '0',
      DIADI(17) => '0',
      DIADI(16) => '0',
      DIADI(15 downto 8) => wdata(16 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31) => '0',
      DIBDI(30) => '0',
      DIBDI(29) => '0',
      DIBDI(28) => '0',
      DIBDI(27) => '0',
      DIBDI(26) => '0',
      DIBDI(25) => '0',
      DIBDI(24) => '0',
      DIBDI(23) => '0',
      DIBDI(22) => '0',
      DIBDI(21) => '0',
      DIBDI(20) => '0',
      DIBDI(19) => '0',
      DIBDI(18) => '0',
      DIBDI(17) => '0',
      DIBDI(16) => '0',
      DIBDI(15) => '0',
      DIBDI(14) => '0',
      DIBDI(13) => '0',
      DIBDI(12) => '0',
      DIBDI(11) => '0',
      DIBDI(10) => '0',
      DIBDI(9) => '0',
      DIBDI(8) => '0',
      DIBDI(7) => '0',
      DIBDI(6) => '0',
      DIBDI(5) => '0',
      DIBDI(4) => '0',
      DIBDI(3) => '0',
      DIBDI(2) => '0',
      DIBDI(1) => '0',
      DIBDI(0) => '0',
      DIPADIP(3) => '0',
      DIPADIP(2) => '0',
      DIPADIP(1) => wdata(17),
      DIPADIP(0) => wdata(8),
      DIPBDIP(3) => '0',
      DIPBDIP(2) => '0',
      DIPBDIP(1) => '0',
      DIPBDIP(0) => '0',
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => rdata(16 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => rdata(17),
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3) => '1',
      WEA(2) => '1',
      WEA(1) => '1',
      WEA(0) => '1',
      WEBWE(7) => '0',
      WEBWE(6) => '0',
      WEBWE(5) => '0',
      WEBWE(4) => '0',
      WEBWE(3) => '0',
      WEBWE(2) => '0',
      WEBWE(1) => '0',
      WEBWE(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_18 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_18 : entity is "unimacro_BRAM_TDP_MACRO";
end PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_18;

architecture STRUCTURE of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_18 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_52\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_53\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_54\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_74\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3) => '1',
      ADDRARDADDR(2) => '1',
      ADDRARDADDR(1) => '1',
      ADDRARDADDR(0) => '1',
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3) => '1',
      ADDRBWRADDR(2) => '1',
      ADDRBWRADDR(1) => '1',
      ADDRBWRADDR(0) => '1',
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => user_clk,
      CLKBWRCLK => user_clk,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31) => '0',
      DIADI(30) => '0',
      DIADI(29) => '0',
      DIADI(28) => '0',
      DIADI(27) => '0',
      DIADI(26) => '0',
      DIADI(25) => '0',
      DIADI(24) => '0',
      DIADI(23) => '0',
      DIADI(22) => '0',
      DIADI(21) => '0',
      DIADI(20) => '0',
      DIADI(19) => '0',
      DIADI(18) => '0',
      DIADI(17) => '0',
      DIADI(16) => '0',
      DIADI(15) => '0',
      DIADI(14) => '0',
      DIADI(13) => '0',
      DIADI(12 downto 8) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(13 downto 9),
      DIADI(7 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(7 downto 0),
      DIBDI(31) => '0',
      DIBDI(30) => '0',
      DIBDI(29) => '0',
      DIBDI(28) => '0',
      DIBDI(27) => '0',
      DIBDI(26) => '0',
      DIBDI(25) => '0',
      DIBDI(24) => '0',
      DIBDI(23) => '0',
      DIBDI(22) => '0',
      DIBDI(21) => '0',
      DIBDI(20) => '0',
      DIBDI(19) => '0',
      DIBDI(18) => '0',
      DIBDI(17) => '0',
      DIBDI(16) => '0',
      DIBDI(15) => '0',
      DIBDI(14) => '0',
      DIBDI(13) => '0',
      DIBDI(12) => '0',
      DIBDI(11) => '0',
      DIBDI(10) => '0',
      DIBDI(9) => '0',
      DIBDI(8) => '0',
      DIBDI(7) => '0',
      DIBDI(6) => '0',
      DIBDI(5) => '0',
      DIBDI(4) => '0',
      DIBDI(3) => '0',
      DIBDI(2) => '0',
      DIBDI(1) => '0',
      DIBDI(0) => '0',
      DIPADIP(3) => '0',
      DIPADIP(2) => '0',
      DIPADIP(1) => '0',
      DIPADIP(0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(8),
      DIPBDIP(3) => '0',
      DIPBDIP(2) => '0',
      DIPBDIP(1) => '0',
      DIPBDIP(0) => '0',
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_52\,
      DOBDO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_53\,
      DOBDO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_54\,
      DOBDO(12 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13 downto 9),
      DOBDO(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_74\,
      DOPBDOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3) => '1',
      WEA(2) => '1',
      WEA(1) => '1',
      WEA(0) => '1',
      WEBWE(7) => '0',
      WEBWE(6) => '0',
      WEBWE(5) => '0',
      WEBWE(4) => '0',
      WEBWE(3) => '0',
      WEBWE(2) => '0',
      WEBWE(1) => '0',
      WEBWE(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_19 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_19 : entity is "unimacro_BRAM_TDP_MACRO";
end PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_19;

architecture STRUCTURE of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_19 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
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      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3) => '1',
      ADDRARDADDR(2) => '1',
      ADDRARDADDR(1) => '1',
      ADDRARDADDR(0) => '1',
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3) => '1',
      ADDRBWRADDR(2) => '1',
      ADDRBWRADDR(1) => '1',
      ADDRBWRADDR(0) => '1',
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => user_clk,
      CLKBWRCLK => user_clk,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31) => '0',
      DIADI(30) => '0',
      DIADI(29) => '0',
      DIADI(28) => '0',
      DIADI(27) => '0',
      DIADI(26) => '0',
      DIADI(25) => '0',
      DIADI(24) => '0',
      DIADI(23) => '0',
      DIADI(22) => '0',
      DIADI(21) => '0',
      DIADI(20) => '0',
      DIADI(19) => '0',
      DIADI(18) => '0',
      DIADI(17) => '0',
      DIADI(16) => '0',
      DIADI(15 downto 8) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(16 downto 9),
      DIADI(7 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(7 downto 0),
      DIBDI(31) => '0',
      DIBDI(30) => '0',
      DIBDI(29) => '0',
      DIBDI(28) => '0',
      DIBDI(27) => '0',
      DIBDI(26) => '0',
      DIBDI(25) => '0',
      DIBDI(24) => '0',
      DIBDI(23) => '0',
      DIBDI(22) => '0',
      DIBDI(21) => '0',
      DIBDI(20) => '0',
      DIBDI(19) => '0',
      DIBDI(18) => '0',
      DIBDI(17) => '0',
      DIBDI(16) => '0',
      DIBDI(15) => '0',
      DIBDI(14) => '0',
      DIBDI(13) => '0',
      DIBDI(12) => '0',
      DIBDI(11) => '0',
      DIBDI(10) => '0',
      DIBDI(9) => '0',
      DIBDI(8) => '0',
      DIBDI(7) => '0',
      DIBDI(6) => '0',
      DIBDI(5) => '0',
      DIBDI(4) => '0',
      DIBDI(3) => '0',
      DIBDI(2) => '0',
      DIBDI(1) => '0',
      DIBDI(0) => '0',
      DIPADIP(3) => '0',
      DIPADIP(2) => '0',
      DIPADIP(1) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17),
      DIPADIP(0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(8),
      DIPBDIP(3) => '0',
      DIPBDIP(2) => '0',
      DIPBDIP(1) => '0',
      DIPBDIP(0) => '0',
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(16 downto 9),
      DOBDO(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17),
      DOPBDOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3) => '1',
      WEA(2) => '1',
      WEA(1) => '1',
      WEA(0) => '1',
      WEBWE(7) => '0',
      WEBWE(6) => '0',
      WEBWE(5) => '0',
      WEBWE(4) => '0',
      WEBWE(3) => '0',
      WEBWE(2) => '0',
      WEBWE(1) => '0',
      WEBWE(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_20 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_20 : entity is "unimacro_BRAM_TDP_MACRO";
end PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_20;

architecture STRUCTURE of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_20 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3) => '1',
      ADDRARDADDR(2) => '1',
      ADDRARDADDR(1) => '1',
      ADDRARDADDR(0) => '1',
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3) => '1',
      ADDRBWRADDR(2) => '1',
      ADDRBWRADDR(1) => '1',
      ADDRBWRADDR(0) => '1',
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => user_clk,
      CLKBWRCLK => user_clk,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31) => '0',
      DIADI(30) => '0',
      DIADI(29) => '0',
      DIADI(28) => '0',
      DIADI(27) => '0',
      DIADI(26) => '0',
      DIADI(25) => '0',
      DIADI(24) => '0',
      DIADI(23) => '0',
      DIADI(22) => '0',
      DIADI(21) => '0',
      DIADI(20) => '0',
      DIADI(19) => '0',
      DIADI(18) => '0',
      DIADI(17) => '0',
      DIADI(16) => '0',
      DIADI(15 downto 8) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(16 downto 9),
      DIADI(7 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(7 downto 0),
      DIBDI(31) => '0',
      DIBDI(30) => '0',
      DIBDI(29) => '0',
      DIBDI(28) => '0',
      DIBDI(27) => '0',
      DIBDI(26) => '0',
      DIBDI(25) => '0',
      DIBDI(24) => '0',
      DIBDI(23) => '0',
      DIBDI(22) => '0',
      DIBDI(21) => '0',
      DIBDI(20) => '0',
      DIBDI(19) => '0',
      DIBDI(18) => '0',
      DIBDI(17) => '0',
      DIBDI(16) => '0',
      DIBDI(15) => '0',
      DIBDI(14) => '0',
      DIBDI(13) => '0',
      DIBDI(12) => '0',
      DIBDI(11) => '0',
      DIBDI(10) => '0',
      DIBDI(9) => '0',
      DIBDI(8) => '0',
      DIBDI(7) => '0',
      DIBDI(6) => '0',
      DIBDI(5) => '0',
      DIBDI(4) => '0',
      DIBDI(3) => '0',
      DIBDI(2) => '0',
      DIBDI(1) => '0',
      DIBDI(0) => '0',
      DIPADIP(3) => '0',
      DIPADIP(2) => '0',
      DIPADIP(1) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17),
      DIPADIP(0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(8),
      DIPBDIP(3) => '0',
      DIPBDIP(2) => '0',
      DIPBDIP(1) => '0',
      DIPBDIP(0) => '0',
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(16 downto 9),
      DOBDO(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17),
      DOPBDOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3) => '1',
      WEA(2) => '1',
      WEA(1) => '1',
      WEA(0) => '1',
      WEBWE(7) => '0',
      WEBWE(6) => '0',
      WEBWE(5) => '0',
      WEBWE(4) => '0',
      WEBWE(3) => '0',
      WEBWE(2) => '0',
      WEBWE(1) => '0',
      WEBWE(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_21 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_21 : entity is "unimacro_BRAM_TDP_MACRO";
end PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_21;

architecture STRUCTURE of PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_21 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
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      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3) => '1',
      ADDRARDADDR(2) => '1',
      ADDRARDADDR(1) => '1',
      ADDRARDADDR(0) => '1',
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3) => '1',
      ADDRBWRADDR(2) => '1',
      ADDRBWRADDR(1) => '1',
      ADDRBWRADDR(0) => '1',
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => user_clk,
      CLKBWRCLK => user_clk,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31) => '0',
      DIADI(30) => '0',
      DIADI(29) => '0',
      DIADI(28) => '0',
      DIADI(27) => '0',
      DIADI(26) => '0',
      DIADI(25) => '0',
      DIADI(24) => '0',
      DIADI(23) => '0',
      DIADI(22) => '0',
      DIADI(21) => '0',
      DIADI(20) => '0',
      DIADI(19) => '0',
      DIADI(18) => '0',
      DIADI(17) => '0',
      DIADI(16) => '0',
      DIADI(15 downto 8) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(16 downto 9),
      DIADI(7 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(7 downto 0),
      DIBDI(31) => '0',
      DIBDI(30) => '0',
      DIBDI(29) => '0',
      DIBDI(28) => '0',
      DIBDI(27) => '0',
      DIBDI(26) => '0',
      DIBDI(25) => '0',
      DIBDI(24) => '0',
      DIBDI(23) => '0',
      DIBDI(22) => '0',
      DIBDI(21) => '0',
      DIBDI(20) => '0',
      DIBDI(19) => '0',
      DIBDI(18) => '0',
      DIBDI(17) => '0',
      DIBDI(16) => '0',
      DIBDI(15) => '0',
      DIBDI(14) => '0',
      DIBDI(13) => '0',
      DIBDI(12) => '0',
      DIBDI(11) => '0',
      DIBDI(10) => '0',
      DIBDI(9) => '0',
      DIBDI(8) => '0',
      DIBDI(7) => '0',
      DIBDI(6) => '0',
      DIBDI(5) => '0',
      DIBDI(4) => '0',
      DIBDI(3) => '0',
      DIBDI(2) => '0',
      DIBDI(1) => '0',
      DIBDI(0) => '0',
      DIPADIP(3) => '0',
      DIPADIP(2) => '0',
      DIPADIP(1) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17),
      DIPADIP(0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(8),
      DIPBDIP(3) => '0',
      DIPBDIP(2) => '0',
      DIPBDIP(1) => '0',
      DIPBDIP(0) => '0',
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(16 downto 9),
      DOBDO(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17),
      DOPBDOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3) => '1',
      WEA(2) => '1',
      WEA(1) => '1',
      WEA(0) => '1',
      WEBWE(7) => '0',
      WEBWE(6) => '0',
      WEBWE(5) => '0',
      WEBWE(4) => '0',
      WEBWE(3) => '0',
      WEBWE(2) => '0',
      WEBWE(1) => '0',
      WEBWE(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tvalid : out STD_LOGIC;
    m_axis_rx_tlast : out STD_LOGIC;
    trn_in_packet_reg : out STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    user_reset_out_reg : in STD_LOGIC;
    trn_rsrc_dsc : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    rsrc_rdy_filtered10_out : in STD_LOGIC;
    trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 );
    trn_reof : in STD_LOGIC;
    trn_rsof : in STD_LOGIC;
    trn_recrc_err : in STD_LOGIC;
    trn_rerrfwd : in STD_LOGIC;
    user_reset_out_reg_0 : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    trn_rdst_rdy_xhdl4_reg : in STD_LOGIC;
    trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 );
    trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx : entity is "PCIeGen1x8If64_axi_basic_rx";
end PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx is
  signal \^m_axis_rx_tuser\ : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \^m_axis_rx_tvalid\ : STD_LOGIC;
  signal null_mux_sel : STD_LOGIC;
  signal payload_len : STD_LOGIC_VECTOR ( 9 downto 5 );
  signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal rx_null_gen_inst_n_0 : STD_LOGIC;
  signal rx_null_gen_inst_n_1 : STD_LOGIC;
  signal rx_null_gen_inst_n_2 : STD_LOGIC;
  signal rx_null_gen_inst_n_3 : STD_LOGIC;
  signal rx_null_gen_inst_n_4 : STD_LOGIC;
  signal rx_null_gen_inst_n_5 : STD_LOGIC;
  signal rx_null_gen_inst_n_6 : STD_LOGIC;
  signal rx_null_gen_inst_n_7 : STD_LOGIC;
  signal rx_null_gen_inst_n_8 : STD_LOGIC;
  signal rx_pipeline_inst_n_5 : STD_LOGIC;
  signal rx_pipeline_inst_n_6 : STD_LOGIC;
  signal rx_pipeline_inst_n_7 : STD_LOGIC;
  signal rx_pipeline_inst_n_8 : STD_LOGIC;
  signal rx_pipeline_inst_n_9 : STD_LOGIC;
begin
  m_axis_rx_tuser(21 downto 0) <= \^m_axis_rx_tuser\(21 downto 0);
  m_axis_rx_tvalid <= \^m_axis_rx_tvalid\;
rx_null_gen_inst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_null_gen
     port map (
      D(3) => rx_null_gen_inst_n_3,
      D(2) => rx_null_gen_inst_n_4,
      D(1) => rx_null_gen_inst_n_5,
      D(0) => rx_null_gen_inst_n_6,
      data_prev_reg => rx_pipeline_inst_n_7,
      data_prev_reg_0 => rx_pipeline_inst_n_8,
      in0(4 downto 0) => plusOp(4 downto 0),
      \m_axis_rx_tdata_xhdl0_reg[30]\(4 downto 0) => payload_len(9 downto 5),
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(0) => \^m_axis_rx_tuser\(21),
      \m_axis_rx_tuser_xhdl1_reg[19]\ => rx_null_gen_inst_n_8,
      \m_axis_rx_tuser_xhdl1_reg[21]\ => rx_null_gen_inst_n_2,
      m_axis_rx_tvalid_xhdl2_reg => \^m_axis_rx_tvalid\,
      null_mux_sel => null_mux_sel,
      null_mux_sel_reg => rx_null_gen_inst_n_0,
      null_mux_sel_reg_0 => rx_pipeline_inst_n_6,
      reg_tlast_reg => rx_null_gen_inst_n_7,
      trn_rdst_rdy_xhdl4_reg => rx_null_gen_inst_n_1,
      \trn_rrem_prev_reg[0]\ => rx_pipeline_inst_n_9,
      user_clk => user_clk,
      user_reset_out_reg => user_reset_out_reg,
      user_reset_out_reg_0 => rx_pipeline_inst_n_5
    );
rx_pipeline_inst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_pipeline
     port map (
      D(3) => rx_null_gen_inst_n_3,
      D(2) => rx_null_gen_inst_n_4,
      D(1) => rx_null_gen_inst_n_5,
      D(0) => rx_null_gen_inst_n_6,
      E(0) => E(0),
      data_prev_reg_0 => rx_null_gen_inst_n_7,
      data_prev_reg_1 => rx_null_gen_inst_n_2,
      in0(4 downto 0) => plusOp(4 downto 0),
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(7 downto 0) => m_axis_rx_tkeep(7 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(21 downto 0) => \^m_axis_rx_tuser\(21 downto 0),
      \m_axis_rx_tuser_xhdl1_reg[19]_0\ => rx_pipeline_inst_n_9,
      \m_axis_rx_tuser_xhdl1_reg[21]_0\ => rx_pipeline_inst_n_7,
      m_axis_rx_tvalid => \^m_axis_rx_tvalid\,
      null_mux_sel => null_mux_sel,
      null_mux_sel_reg_0 => rx_pipeline_inst_n_5,
      null_mux_sel_reg_1 => rx_null_gen_inst_n_1,
      null_mux_sel_reg_2 => rx_null_gen_inst_n_8,
      \reg_pkt_len_counter_reg[0]\ => rx_null_gen_inst_n_0,
      \reg_pkt_len_counter_reg[9]\(4 downto 0) => payload_len(9 downto 5),
      reg_tlast_reg_0 => rx_pipeline_inst_n_8,
      rsrc_rdy_filtered10_out => rsrc_rdy_filtered10_out,
      trn_in_packet_reg_0 => trn_in_packet_reg,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_rdst_rdy_xhdl4_reg_0 => rx_pipeline_inst_n_6,
      trn_rdst_rdy_xhdl4_reg_1 => trn_rdst_rdy_xhdl4_reg,
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem(0),
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      user_clk => user_clk,
      user_reset_out_reg => user_reset_out_reg,
      user_reset_out_reg_0 => user_reset_out_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx is
  port (
    trn_teof : out STD_LOGIC;
    trn_tsrc_rdy : out STD_LOGIC;
    trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tx_tready : out STD_LOGIC;
    tbuf_av_gap_thrtl_reg : out STD_LOGIC;
    tbuf_av_gap_thrtl_reg_0 : out STD_LOGIC;
    trn_tcfg_gnt : out STD_LOGIC;
    cfg_pm_turnoff_ok_n : out STD_LOGIC;
    trn_tsof : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    user_reset_out_reg : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_cfg_gnt : in STD_LOGIC;
    trn_tcfg_req : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    tbuf_av_min_trig : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC;
    user_lnk_up_int_reg : in STD_LOGIC;
    cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 );
    user_reset_out_reg_0 : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC;
    \tcfg_req_cnt_reg[1]\ : in STD_LOGIC;
    trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_to_turnoff : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx : entity is "PCIeGen1x8If64_axi_basic_tx";
end PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx is
  signal p_5_out : STD_LOGIC;
  signal tx_pipeline_inst_n_3 : STD_LOGIC;
  signal tx_pipeline_inst_n_4 : STD_LOGIC;
  signal \xhdl12.tx_thrl_ctl_inst_n_1\ : STD_LOGIC;
  signal \xhdl12.tx_thrl_ctl_inst_n_4\ : STD_LOGIC;
begin
tx_pipeline_inst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_pipeline
     port map (
      Q(63 downto 0) => Q(63 downto 0),
      \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0\ => tx_pipeline_inst_n_3,
      \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_1\ => tx_pipeline_inst_n_4,
      p_5_out => p_5_out,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(3 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(3 downto 0),
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      tready_thrtl_xhdl1_reg => \xhdl12.tx_thrl_ctl_inst_n_1\,
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem(0),
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy,
      user_clk => user_clk,
      user_lnk_up_int_reg => user_lnk_up_int_reg,
      user_reset_out_reg => user_reset_out_reg,
      user_reset_out_reg_0 => \xhdl12.tx_thrl_ctl_inst_n_4\
    );
\xhdl12.tx_thrl_ctl_inst\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_thrtl_ctl
     port map (
      \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg\ => tx_pipeline_inst_n_4,
      axi_in_packet_reg => \xhdl12.tx_thrl_ctl_inst_n_4\,
      axi_in_packet_reg_0 => tx_pipeline_inst_n_3,
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      cfg_pm_turnoff_ok_n => cfg_pm_turnoff_ok_n,
      cfg_to_turnoff => cfg_to_turnoff,
      cfg_turnoff_ok => cfg_turnoff_ok,
      p_5_out => p_5_out,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\,
      s_axis_tx_tdata(3 downto 2) => s_axis_tx_tdata(30 downto 29),
      s_axis_tx_tdata(1) => s_axis_tx_tdata(15),
      s_axis_tx_tdata(0) => s_axis_tx_tdata(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => s_axis_tx_tready,
      s_axis_tx_tuser(0) => s_axis_tx_tuser(0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      tbuf_av_gap_thrtl_reg_0 => tbuf_av_gap_thrtl_reg,
      tbuf_av_gap_thrtl_reg_1 => tbuf_av_gap_thrtl_reg_0,
      tbuf_av_min_trig => tbuf_av_min_trig,
      \tcfg_req_cnt_reg[1]_0\ => \tcfg_req_cnt_reg[1]\,
      tready_thrtl_xhdl1_reg_0 => \xhdl12.tx_thrl_ctl_inst_n_1\,
      trn_tbuf_av(5 downto 0) => trn_tbuf_av(5 downto 0),
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => trn_tcfg_req,
      trn_tdst_rdy => trn_tdst_rdy,
      tx_cfg_gnt => tx_cfg_gnt,
      user_clk => user_clk,
      user_lnk_up_int_reg => user_lnk_up_int_reg,
      user_reset_out_reg => user_reset_out_reg,
      user_reset_out_reg_0 => user_reset_out_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_common is
  port (
    RATE_QPLLLOCK : out STD_LOGIC;
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    \cplllock_reg1_reg[3]_0\ : out STD_LOGIC;
    DRP_DONE : out STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    qpllpd : in STD_LOGIC;
    qrst_qpllreset : in STD_LOGIC;
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    O1687 : in STD_LOGIC;
    DRP_OVRD : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_common : entity is "PCIeGen1x8If64_gt_common";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_common;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_common is
  signal QPLL_QPLLRESET0126_out : STD_LOGIC;
  signal \^rate_qplllock\ : STD_LOGIC;
  signal qpll_drp_addr : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal qpll_drp_di : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal qpll_drp_do : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal qpll_drp_en : STD_LOGIC;
  signal qpll_drp_rdy : STD_LOGIC;
  signal qpll_drp_we : STD_LOGIC;
begin
  RATE_QPLLLOCK <= \^rate_qplllock\;
qpll_drp_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp_84
     port map (
      DRP_ADDR(7 downto 0) => qpll_drp_addr(7 downto 0),
      DRP_DI(15 downto 0) => qpll_drp_di(15 downto 0),
      DRP_DO(15 downto 0) => qpll_drp_do(15 downto 0),
      DRP_DONE => DRP_DONE,
      DRP_OVRD => DRP_OVRD,
      DRP_RDY => qpll_drp_rdy,
      DRP_START => DRP_START,
      O1687 => O1687,
      QPLL_QPLLRESET0126_out => QPLL_QPLLRESET0126_out,
      RATE_QPLLLOCK => \^rate_qplllock\,
      RST_DCLK_RESET => RST_DCLK_RESET,
      qpll_drp_en => qpll_drp_en,
      qpll_drp_we => qpll_drp_we,
      qrst_qpllreset => qrst_qpllreset,
      \resetovrd_disble.reset_reg[4]\ => \resetovrd_disble.reset_reg[4]\
    );
qpll_wrapper_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper_85
     port map (
      DRP_ADDR(7 downto 0) => qpll_drp_addr(7 downto 0),
      DRP_DI(15 downto 0) => qpll_drp_di(15 downto 0),
      DRP_DO(15 downto 0) => qpll_drp_do(15 downto 0),
      QPLL_QPLLRESET0126_out => QPLL_QPLLRESET0126_out,
      RATE_QPLLLOCK => \^rate_qplllock\,
      \cplllock_reg1_reg[3]\ => \cplllock_reg1_reg[3]\,
      \cplllock_reg1_reg[3]_0\ => \cplllock_reg1_reg[3]_0\,
      qpll_drp_en => qpll_drp_en,
      qpll_drp_rdy => qpll_drp_rdy,
      qpll_drp_we => qpll_drp_we,
      qpllpd => qpllpd,
      \resetovrd_disble.reset_reg[4]\ => \resetovrd_disble.reset_reg[4]\,
      sys_clk => sys_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_common_50 is
  port (
    RATE_QPLLLOCK : out STD_LOGIC;
    \cplllock_reg1_reg[7]\ : out STD_LOGIC;
    \cplllock_reg1_reg[7]_0\ : out STD_LOGIC;
    DRP_DONE : out STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    qpllpd : in STD_LOGIC;
    qrst_qpllreset : in STD_LOGIC;
    RST_DCLK_RESET : in STD_LOGIC;
    DRP_START : in STD_LOGIC;
    DRP_GEN3 : in STD_LOGIC;
    DRP_OVRD : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_common_50 : entity is "PCIeGen1x8If64_gt_common";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_common_50;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_common_50 is
  signal QPLL_QPLLRESET0 : STD_LOGIC;
  signal \^rate_qplllock\ : STD_LOGIC;
  signal qpll_drp_addr : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal qpll_drp_di : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal qpll_drp_do : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal qpll_drp_en : STD_LOGIC;
  signal qpll_drp_rdy : STD_LOGIC;
  signal qpll_drp_we : STD_LOGIC;
begin
  RATE_QPLLLOCK <= \^rate_qplllock\;
qpll_drp_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp
     port map (
      DRP_ADDR(7 downto 0) => qpll_drp_addr(7 downto 0),
      DRP_DI(15 downto 0) => qpll_drp_di(15 downto 0),
      DRP_DO(15 downto 0) => qpll_drp_do(15 downto 0),
      DRP_DONE => DRP_DONE,
      DRP_GEN3 => DRP_GEN3,
      DRP_OVRD => DRP_OVRD,
      DRP_RDY => qpll_drp_rdy,
      DRP_START => DRP_START,
      QPLL_QPLLRESET0 => QPLL_QPLLRESET0,
      RATE_QPLLLOCK => \^rate_qplllock\,
      RST_DCLK_RESET => RST_DCLK_RESET,
      qpll_drp_en => qpll_drp_en,
      qpll_drp_we => qpll_drp_we,
      qrst_qpllreset => qrst_qpllreset,
      \resetovrd_disble.reset_reg[4]\ => \resetovrd_disble.reset_reg[4]\
    );
qpll_wrapper_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper
     port map (
      DRP_ADDR(7 downto 0) => qpll_drp_addr(7 downto 0),
      DRP_DI(15 downto 0) => qpll_drp_di(15 downto 0),
      DRP_DO(15 downto 0) => qpll_drp_do(15 downto 0),
      QPLL_QPLLRESET0 => QPLL_QPLLRESET0,
      RATE_QPLLLOCK => \^rate_qplllock\,
      \cplllock_reg1_reg[7]\ => \cplllock_reg1_reg[7]\,
      \cplllock_reg1_reg[7]_0\ => \cplllock_reg1_reg[7]_0\,
      qpll_drp_en => qpll_drp_en,
      qpll_drp_rdy => qpll_drp_rdy,
      qpll_drp_we => qpll_drp_we,
      qpllpd => qpllpd,
      \resetovrd_disble.reset_reg[4]\ => \resetovrd_disble.reset_reg[4]\,
      sys_clk => sys_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper is
  port (
    RATE_CPLLLOCK : out STD_LOGIC;
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_PHYSTATUS : out STD_LOGIC;
    rxcdrlock_reg1_reg : out STD_LOGIC;
    PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXPHALIGNDONE_M : out STD_LOGIC;
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_RXRATEDONE : out STD_LOGIC;
    USER_RXRESETDONE : out STD_LOGIC;
    rxvalid_reg1_reg : out STD_LOGIC;
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txoutclk_out : out STD_LOGIC;
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_TXRATEDONE : out STD_LOGIC;
    USER_TXRESETDONE : out STD_LOGIC;
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    RXCHBONDO : out STD_LOGIC_VECTOR ( 4 downto 0 );
    PIPE_RXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_RXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    CLK : in STD_LOGIC;
    \fsm_reg[2]\ : in STD_LOGIC;
    \fsm_reg[0]\ : in STD_LOGIC;
    USER_EYESCANRESET : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    DRP_GTXRESET : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpllpd_reg : in STD_LOGIC;
    qpllpd_reg_0 : in STD_LOGIC;
    \resetovrd_disble.fsm_reg[1]\ : in STD_LOGIC;
    gen3_reg : in STD_LOGIC;
    USER_RXBUFRESET : in STD_LOGIC;
    USER_RXCDRFREQRESET : in STD_LOGIC;
    USER_RXCDRRESET : in STD_LOGIC;
    O1671 : in STD_LOGIC;
    converge_gen3_reg : in STD_LOGIC;
    USER_RXDFELPMRESET : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]\ : in STD_LOGIC;
    USER_RXPCSRESET : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]_0\ : in STD_LOGIC;
    GT_RXPMARESET0 : in STD_LOGIC;
    PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 );
    \userrdy_reg_rep__5\ : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    PIPE_TXDEEMPH : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\ : in STD_LOGIC;
    \txsync_fsm.txdlyen_reg\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[2]\ : in STD_LOGIC;
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    GT_TXPMARESET0 : in STD_LOGIC;
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 2 downto 0 );
    TXMARGIN : in STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_OOBCLK : in STD_LOGIC;
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 8 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    gt_rxvalid_q_reg : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in3_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in2_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper : entity is "PCIeGen1x8If64_gt_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper is
  signal CPLLPD0 : STD_LOGIC;
  signal CPLLRESET0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC;
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE";
begin
  pipe_rxstatus(2 downto 0) <= \^pipe_rxstatus\(2 downto 0);
cpllPDInst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_87
     port map (
      CPLLPD0 => CPLLPD0,
      CPLLRESET0 => CPLLRESET0,
      RST_CPLLRESET => RST_CPLLRESET,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      p_0_in2_in => p_0_in2_in,
      p_0_in3_in => p_0_in3_in,
      rst_cpllpd => rst_cpllpd
    );
\gt_rx_status_q[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(0),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(0)
    );
\gt_rx_status_q[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(1),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(1)
    );
\gt_rx_status_q[2]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(2),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(2)
    );
\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL
    generic map(
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"A407CC",
      CPLL_FBDIV => 5,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"0000000001CF",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => X"00018480",
      PMA_RSV2 => X"2050",
      PMA_RSV3 => B"00",
      PMA_RSV4 => X"00000000",
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"03000023FF10200020",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00000011110000",
      RXLPM_LF_CFG => B"00000011110000",
      RXOOB_CFG => B"0000110",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RX_BIAS_CFG => B"000000000100",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFE_GAIN_CFG => X"020FEA",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011110000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_KL_CFG => B"0000011111110",
      RX_DFE_KL_CFG2 => X"3290D86C",
      RX_DFE_LPM_CFG => X"0954",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '1',
      RX_DFE_UT_CFG => B"10001111000000000",
      RX_DFE_VP_CFG => B"00011111100000011",
      RX_DFE_XYD_CFG => B"0000000000000",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 4,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "3.0",
      TERM_RCAL_CFG => B"10000",
      TERM_RCAL_OVRD => '0',
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPMARESET_TIME => B"00011",
      TX_CLK25_DIV => 4,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"10100",
      TX_DEEMPH1 => B"01011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD(3) => '0',
      CLKRSVD(2) => '0',
      CLKRSVD(1) => '0',
      CLKRSVD(0) => USER_OOBCLK,
      CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\,
      CPLLLOCK => RATE_CPLLLOCK,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD0,
      CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\,
      CPLLREFCLKSEL(2) => '0',
      CPLLREFCLKSEL(1) => '0',
      CPLLREFCLKSEL(0) => '1',
      CPLLRESET => CPLLRESET0,
      DMONITOROUT(7 downto 0) => pipe_dmonitorout(7 downto 0),
      DRPADDR(8 downto 0) => DRPADDR(8 downto 0),
      DRPCLK => CLK,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => ext_ch_gt_drpdo(15 downto 0),
      DRPEN => \fsm_reg[2]\,
      DRPRDY => ext_ch_gt_drprdy(0),
      DRPWE => \fsm_reg[0]\,
      EYESCANDATAERROR => pipe_eyescandataerror(0),
      EYESCANMODE => '0',
      EYESCANRESET => USER_EYESCANRESET,
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\,
      GTRESETSEL => '0',
      GTRSVD(15) => '0',
      GTRSVD(14) => '0',
      GTRSVD(13) => '0',
      GTRSVD(12) => '0',
      GTRSVD(11) => '0',
      GTRSVD(10) => '0',
      GTRSVD(9) => '0',
      GTRSVD(8) => '0',
      GTRSVD(7) => '0',
      GTRSVD(6) => '0',
      GTRSVD(5) => '0',
      GTRSVD(4) => '0',
      GTRSVD(3) => '0',
      GTRSVD(2) => '0',
      GTRSVD(1) => '0',
      GTRSVD(0) => '0',
      GTRXRESET => DRP_GTXRESET,
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => DRP_GTXRESET,
      GTXRXN => pci_exp_rxn(0),
      GTXRXP => pci_exp_rxp(0),
      GTXTXN => pci_exp_txn(0),
      GTXTXP => pci_exp_txp(0),
      LOOPBACK(2) => '0',
      LOOPBACK(1) => '0',
      LOOPBACK(0) => '0',
      PCSRSVDIN(15) => '0',
      PCSRSVDIN(14) => '0',
      PCSRSVDIN(13) => '0',
      PCSRSVDIN(12) => '0',
      PCSRSVDIN(11) => '0',
      PCSRSVDIN(10) => '0',
      PCSRSVDIN(9) => '0',
      PCSRSVDIN(8) => '0',
      PCSRSVDIN(7) => '0',
      PCSRSVDIN(6) => '0',
      PCSRSVDIN(5) => '0',
      PCSRSVDIN(4) => '0',
      PCSRSVDIN(3) => '0',
      PCSRSVDIN(2) => '0',
      PCSRSVDIN(1) => '0',
      PCSRSVDIN(0) => '0',
      PCSRSVDIN2(4) => '0',
      PCSRSVDIN2(3) => '0',
      PCSRSVDIN2(2) => '0',
      PCSRSVDIN2(1) => '0',
      PCSRSVDIN2(0) => '0',
      PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => RATE_PHYSTATUS,
      PMARSVDIN(4) => '0',
      PMARSVDIN(3) => '0',
      PMARSVDIN(2) => '0',
      PMARSVDIN(1) => '0',
      PMARSVDIN(0) => '0',
      PMARSVDIN2(4) => '0',
      PMARSVDIN2(3) => '0',
      PMARSVDIN2(2) => '0',
      PMARSVDIN2(1) => '0',
      PMARSVDIN2(0) => '0',
      QPLLCLK => qpllpd_reg,
      QPLLREFCLK => qpllpd_reg_0,
      RESETOVRD => \resetovrd_disble.fsm_reg[1]\,
      RX8B10BEN => gen3_reg,
      RXBUFRESET => USER_RXBUFRESET,
      RXBUFSTATUS(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\,
      RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\,
      RXCDRFREQRESET => USER_RXCDRFREQRESET,
      RXCDRHOLD => '0',
      RXCDRLOCK => rxcdrlock_reg1_reg,
      RXCDROVRDEN => '0',
      RXCDRRESET => USER_RXCDRRESET,
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0),
      RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4),
      RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\,
      RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\,
      RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\,
      RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\,
      RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4),
      RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\,
      RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\,
      RXCHARISK(1 downto 0) => PIPE_RXDATAK(1 downto 0),
      RXCHBONDEN => gen3_reg,
      RXCHBONDI(4) => '0',
      RXCHBONDI(3) => '0',
      RXCHBONDI(2) => '0',
      RXCHBONDI(1) => '0',
      RXCHBONDI(0) => '0',
      RXCHBONDLEVEL(2) => '0',
      RXCHBONDLEVEL(1) => '0',
      RXCHBONDLEVEL(0) => '1',
      RXCHBONDMASTER => O1671,
      RXCHBONDO(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDSLAVE => '0',
      RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => pipe_rxcommadet(0),
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32),
      RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\,
      RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\,
      RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\,
      RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\,
      RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\,
      RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\,
      RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\,
      RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\,
      RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\,
      RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\,
      RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\,
      RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\,
      RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\,
      RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\,
      RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\,
      RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\,
      RXDATA(15 downto 0) => PIPE_RXDATA(15 downto 0),
      RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\,
      RXDDIEN => '0',
      RXDFEAGCHOLD => converge_gen3_reg,
      RXDFEAGCOVRDEN => '0',
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '1',
      RXDFELPMRESET => USER_RXDFELPMRESET,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '0',
      RXDFEXYDHOLD => '0',
      RXDFEXYDOVRDEN => '0',
      RXDISPERR(7 downto 0) => pipe_rxdisperr(7 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => SYNC_RXSYNC_DONE,
      RXDLYOVRDEN => '0',
      RXDLYSRESET => \rxsync_fsm_disable.fsm_rx_reg[2]\,
      RXDLYSRESETDONE => pipe_rxdlysresetdone(0),
      RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      RXELECIDLEMODE(1) => '0',
      RXELECIDLEMODE(0) => '0',
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMEN => O1671,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => gen3_reg,
      RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0),
      RXMONITORSEL(1) => '0',
      RXMONITORSEL(0) => '0',
      RXNOTINTABLE(7 downto 0) => pipe_rxnotintable(7 downto 0),
      RXOOBRESET => '0',
      RXOSHOLD => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => pipe_rxoutclk_out(0),
      RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2) => '0',
      RXOUTCLKSEL(1) => '0',
      RXOUTCLKSEL(0) => '0',
      RXPCOMMAALIGNEN => O1671,
      RXPCSRESET => USER_RXPCSRESET,
      RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      RXPHALIGN => \rxsync_fsm_disable.fsm_rx_reg[2]_0\,
      RXPHALIGNDONE => SYNC_RXPHALIGNDONE_M,
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => GT_RXPMARESET0,
      RXPOLARITY => PIPE_RXPOLARITY(0),
      RXPRBSCNTRESET => '0',
      RXPRBSERR => pipe_rxprbserr(0),
      RXPRBSSEL(2) => '0',
      RXPRBSSEL(1) => '0',
      RXPRBSSEL(0) => '0',
      RXQPIEN => '0',
      RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\,
      RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\,
      RXRATE(2 downto 0) => RXRATE(2 downto 0),
      RXRATEDONE => RATE_RXRATEDONE,
      RXRESETDONE => USER_RXRESETDONE,
      RXSLIDE => '0',
      RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\,
      RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      RXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      RXUSERRDY => \userrdy_reg_rep__5\,
      RXUSRCLK => pclk_sel_reg,
      RXUSRCLK2 => pclk_sel_reg,
      RXVALID => rxvalid_reg1_reg,
      SETERRSTATUS => '0',
      TSTIN(19) => '1',
      TSTIN(18) => '1',
      TSTIN(17) => '1',
      TSTIN(16) => '1',
      TSTIN(15) => '1',
      TSTIN(14) => '1',
      TSTIN(13) => '1',
      TSTIN(12) => '1',
      TSTIN(11) => '1',
      TSTIN(10) => '1',
      TSTIN(9) => '1',
      TSTIN(8) => '1',
      TSTIN(7) => '1',
      TSTIN(6) => '1',
      TSTIN(5) => '1',
      TSTIN(4) => '1',
      TSTIN(3) => '1',
      TSTIN(2) => '1',
      TSTIN(1) => '1',
      TSTIN(0) => '1',
      TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0),
      TX8B10BBYPASS(7) => '0',
      TX8B10BBYPASS(6) => '0',
      TX8B10BBYPASS(5) => '0',
      TX8B10BBYPASS(4) => '0',
      TX8B10BBYPASS(3) => '0',
      TX8B10BBYPASS(2) => '0',
      TX8B10BBYPASS(1) => '0',
      TX8B10BBYPASS(0) => '0',
      TX8B10BEN => O1671,
      TXBUFDIFFCTRL(2) => '1',
      TXBUFDIFFCTRL(1) => '0',
      TXBUFDIFFCTRL(0) => '0',
      TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(7) => '0',
      TXCHARDISPMODE(6) => '0',
      TXCHARDISPMODE(5) => '0',
      TXCHARDISPMODE(4) => '0',
      TXCHARDISPMODE(3) => '0',
      TXCHARDISPMODE(2) => '0',
      TXCHARDISPMODE(1) => '0',
      TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0),
      TXCHARDISPVAL(7) => '0',
      TXCHARDISPVAL(6) => '0',
      TXCHARDISPVAL(5) => '0',
      TXCHARDISPVAL(4) => '0',
      TXCHARDISPVAL(3) => '0',
      TXCHARDISPVAL(2) => '0',
      TXCHARDISPVAL(1) => '0',
      TXCHARDISPVAL(0) => '0',
      TXCHARISK(7) => '0',
      TXCHARISK(6) => '0',
      TXCHARISK(5) => '0',
      TXCHARISK(4) => '0',
      TXCHARISK(3) => '0',
      TXCHARISK(2) => '0',
      TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0),
      TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63) => '0',
      TXDATA(62) => '0',
      TXDATA(61) => '0',
      TXDATA(60) => '0',
      TXDATA(59) => '0',
      TXDATA(58) => '0',
      TXDATA(57) => '0',
      TXDATA(56) => '0',
      TXDATA(55) => '0',
      TXDATA(54) => '0',
      TXDATA(53) => '0',
      TXDATA(52) => '0',
      TXDATA(51) => '0',
      TXDATA(50) => '0',
      TXDATA(49) => '0',
      TXDATA(48) => '0',
      TXDATA(47) => '0',
      TXDATA(46) => '0',
      TXDATA(45) => '0',
      TXDATA(44) => '0',
      TXDATA(43) => '0',
      TXDATA(42) => '0',
      TXDATA(41) => '0',
      TXDATA(40) => '0',
      TXDATA(39) => '0',
      TXDATA(38) => '0',
      TXDATA(37) => '0',
      TXDATA(36) => '0',
      TXDATA(35) => '0',
      TXDATA(34) => '0',
      TXDATA(33) => '0',
      TXDATA(32) => '0',
      TXDATA(31) => '0',
      TXDATA(30) => '0',
      TXDATA(29) => '0',
      TXDATA(28) => '0',
      TXDATA(27) => '0',
      TXDATA(26) => '0',
      TXDATA(25) => '0',
      TXDATA(24) => '0',
      TXDATA(23) => '0',
      TXDATA(22) => '0',
      TXDATA(21) => '0',
      TXDATA(20) => '0',
      TXDATA(19) => '0',
      TXDATA(18) => '0',
      TXDATA(17) => '0',
      TXDATA(16) => '0',
      TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0),
      TXDEEMPH => PIPE_TXDEEMPH(0),
      TXDETECTRX => \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\,
      TXDIFFCTRL(3) => '1',
      TXDIFFCTRL(2) => '1',
      TXDIFFCTRL(1) => '0',
      TXDIFFCTRL(0) => '0',
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => \txsync_fsm.txdlyen_reg\,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => \txsync_fsm.fsm_tx_reg[2]\,
      TXDLYSRESETDONE => pipe_txdlysresetdone(0),
      TXDLYUPDOWN => '0',
      TXELECIDLE => PIPE_TXELECIDLE(0),
      TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2) => '0',
      TXHEADER(1) => '0',
      TXHEADER(0) => '0',
      TXINHIBIT => pipe_txinhibit(0),
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => TXMARGIN(2 downto 0),
      TXOUTCLK => pipe_txoutclk_out,
      TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2) => '0',
      TXOUTCLKSEL(1) => '1',
      TXOUTCLKSEL(0) => '1',
      TXPCSRESET => '0',
      TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => \txsync_fsm.fsm_tx_reg[4]\,
      TXPHALIGNDONE => pipe_txphaligndone(0),
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => \txsync_fsm.fsm_tx_reg[4]_0\,
      TXPHINITDONE => pipe_txphinitdone(0),
      TXPHOVRDEN => '0',
      TXPISOPD => '0',
      TXPMARESET => GT_TXPMARESET0,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2) => '0',
      TXPRBSSEL(1) => '0',
      TXPRBSSEL(0) => '0',
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\,
      TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => RXRATE(2 downto 0),
      TXRATEDONE => RATE_TXRATEDONE,
      TXRESETDONE => USER_TXRESETDONE,
      TXSEQUENCE(6) => '0',
      TXSEQUENCE(5) => '0',
      TXSEQUENCE(4) => '0',
      TXSEQUENCE(3) => '0',
      TXSEQUENCE(2) => '0',
      TXSEQUENCE(1) => '0',
      TXSEQUENCE(0) => '0',
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      TXUSERRDY => \userrdy_reg_rep__5\,
      TXUSRCLK => pclk_sel_reg,
      TXUSRCLK2 => pclk_sel_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_29 is
  port (
    RATE_CPLLLOCK : out STD_LOGIC;
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_PHYSTATUS : out STD_LOGIC;
    rxcdrlock_reg1_reg : out STD_LOGIC;
    PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_RXRATEDONE : out STD_LOGIC;
    USER_RXRESETDONE : out STD_LOGIC;
    rxvalid_reg1_reg : out STD_LOGIC;
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_TXRATEDONE : out STD_LOGIC;
    USER_TXRESETDONE : out STD_LOGIC;
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    \fsm_reg[2]\ : in STD_LOGIC;
    \fsm_reg[0]\ : in STD_LOGIC;
    USER_EYESCANRESET : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    rst_gtreset : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpllpd_reg : in STD_LOGIC;
    qpllpd_reg_0 : in STD_LOGIC;
    \resetovrd_disble.fsm_reg[1]\ : in STD_LOGIC;
    gen3_reg : in STD_LOGIC;
    USER_RXBUFRESET : in STD_LOGIC;
    USER_RXCDRFREQRESET : in STD_LOGIC;
    USER_RXCDRRESET : in STD_LOGIC;
    gen3_reg_0 : in STD_LOGIC;
    converge_gen3_reg : in STD_LOGIC;
    USER_RXDFELPMRESET : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]\ : in STD_LOGIC;
    USER_RXPCSRESET : in STD_LOGIC;
    rxsync_donem_reg2_reg : in STD_LOGIC;
    GT_RXPMARESET089_out : in STD_LOGIC;
    PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 );
    \userrdy_reg_rep__4\ : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    PIPE_TXDEEMPH : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\ : in STD_LOGIC;
    \txsync_fsm.txdlyen_reg\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[2]\ : in STD_LOGIC;
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    GT_TXPMARESET092_out : in STD_LOGIC;
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_OOBCLK : in STD_LOGIC;
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 8 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    gt_rxvalid_q_reg : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in95_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in93_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_29 : entity is "PCIeGen1x8If64_gt_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_29;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_29 is
  signal CPLLPD0 : STD_LOGIC;
  signal CPLLRESET0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC;
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE";
begin
  pipe_rxstatus(2 downto 0) <= \^pipe_rxstatus\(2 downto 0);
cpllPDInst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_83
     port map (
      CPLLPD0 => CPLLPD0,
      CPLLRESET0 => CPLLRESET0,
      RST_CPLLRESET => RST_CPLLRESET,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      p_0_in93_in => p_0_in93_in,
      p_0_in95_in => p_0_in95_in,
      rst_cpllpd => rst_cpllpd
    );
\gt_rx_status_q[0]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(0),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(0)
    );
\gt_rx_status_q[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(1),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(1)
    );
\gt_rx_status_q[2]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(2),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(2)
    );
\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL
    generic map(
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"A407CC",
      CPLL_FBDIV => 5,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"0000000001CF",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => X"00018480",
      PMA_RSV2 => X"2050",
      PMA_RSV3 => B"00",
      PMA_RSV4 => X"00000000",
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"03000023FF10200020",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00000011110000",
      RXLPM_LF_CFG => B"00000011110000",
      RXOOB_CFG => B"0000110",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RX_BIAS_CFG => B"000000000100",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFE_GAIN_CFG => X"020FEA",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011110000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_KL_CFG => B"0000011111110",
      RX_DFE_KL_CFG2 => X"3290D86C",
      RX_DFE_LPM_CFG => X"0954",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '1',
      RX_DFE_UT_CFG => B"10001111000000000",
      RX_DFE_VP_CFG => B"00011111100000011",
      RX_DFE_XYD_CFG => B"0000000000000",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 4,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "3.0",
      TERM_RCAL_CFG => B"10000",
      TERM_RCAL_OVRD => '0',
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPMARESET_TIME => B"00011",
      TX_CLK25_DIV => 4,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"10100",
      TX_DEEMPH1 => B"01011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD(3) => '0',
      CLKRSVD(2) => '0',
      CLKRSVD(1) => '0',
      CLKRSVD(0) => USER_OOBCLK,
      CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\,
      CPLLLOCK => RATE_CPLLLOCK,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD0,
      CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\,
      CPLLREFCLKSEL(2) => '0',
      CPLLREFCLKSEL(1) => '0',
      CPLLREFCLKSEL(0) => '1',
      CPLLRESET => CPLLRESET0,
      DMONITOROUT(7 downto 0) => pipe_dmonitorout(7 downto 0),
      DRPADDR(8 downto 0) => DRPADDR(8 downto 0),
      DRPCLK => \resetovrd_disble.reset_reg[4]\,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => ext_ch_gt_drpdo(15 downto 0),
      DRPEN => \fsm_reg[2]\,
      DRPRDY => ext_ch_gt_drprdy(0),
      DRPWE => \fsm_reg[0]\,
      EYESCANDATAERROR => pipe_eyescandataerror(0),
      EYESCANMODE => '0',
      EYESCANRESET => USER_EYESCANRESET,
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\,
      GTRESETSEL => '0',
      GTRSVD(15) => '0',
      GTRSVD(14) => '0',
      GTRSVD(13) => '0',
      GTRSVD(12) => '0',
      GTRSVD(11) => '0',
      GTRSVD(10) => '0',
      GTRSVD(9) => '0',
      GTRSVD(8) => '0',
      GTRSVD(7) => '0',
      GTRSVD(6) => '0',
      GTRSVD(5) => '0',
      GTRSVD(4) => '0',
      GTRSVD(3) => '0',
      GTRSVD(2) => '0',
      GTRSVD(1) => '0',
      GTRSVD(0) => '0',
      GTRXRESET => rst_gtreset,
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => rst_gtreset,
      GTXRXN => pci_exp_rxn(0),
      GTXRXP => pci_exp_rxp(0),
      GTXTXN => pci_exp_txn(0),
      GTXTXP => pci_exp_txp(0),
      LOOPBACK(2) => '0',
      LOOPBACK(1) => '0',
      LOOPBACK(0) => '0',
      PCSRSVDIN(15) => '0',
      PCSRSVDIN(14) => '0',
      PCSRSVDIN(13) => '0',
      PCSRSVDIN(12) => '0',
      PCSRSVDIN(11) => '0',
      PCSRSVDIN(10) => '0',
      PCSRSVDIN(9) => '0',
      PCSRSVDIN(8) => '0',
      PCSRSVDIN(7) => '0',
      PCSRSVDIN(6) => '0',
      PCSRSVDIN(5) => '0',
      PCSRSVDIN(4) => '0',
      PCSRSVDIN(3) => '0',
      PCSRSVDIN(2) => '0',
      PCSRSVDIN(1) => '0',
      PCSRSVDIN(0) => '0',
      PCSRSVDIN2(4) => '0',
      PCSRSVDIN2(3) => '0',
      PCSRSVDIN2(2) => '0',
      PCSRSVDIN2(1) => '0',
      PCSRSVDIN2(0) => '0',
      PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => RATE_PHYSTATUS,
      PMARSVDIN(4) => '0',
      PMARSVDIN(3) => '0',
      PMARSVDIN(2) => '0',
      PMARSVDIN(1) => '0',
      PMARSVDIN(0) => '0',
      PMARSVDIN2(4) => '0',
      PMARSVDIN2(3) => '0',
      PMARSVDIN2(2) => '0',
      PMARSVDIN2(1) => '0',
      PMARSVDIN2(0) => '0',
      QPLLCLK => qpllpd_reg,
      QPLLREFCLK => qpllpd_reg_0,
      RESETOVRD => \resetovrd_disble.fsm_reg[1]\,
      RX8B10BEN => gen3_reg,
      RXBUFRESET => USER_RXBUFRESET,
      RXBUFSTATUS(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\,
      RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\,
      RXCDRFREQRESET => USER_RXCDRFREQRESET,
      RXCDRHOLD => '0',
      RXCDRLOCK => rxcdrlock_reg1_reg,
      RXCDROVRDEN => '0',
      RXCDRRESET => USER_RXCDRRESET,
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0),
      RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4),
      RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\,
      RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\,
      RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\,
      RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\,
      RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4),
      RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\,
      RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\,
      RXCHARISK(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      RXCHBONDEN => gen3_reg,
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2) => '0',
      RXCHBONDLEVEL(1) => '0',
      RXCHBONDLEVEL(0) => '0',
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\,
      RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\,
      RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\,
      RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\,
      RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\,
      RXCHBONDSLAVE => gen3_reg_0,
      RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => pipe_rxcommadet(0),
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32),
      RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\,
      RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\,
      RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\,
      RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\,
      RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\,
      RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\,
      RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\,
      RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\,
      RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\,
      RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\,
      RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\,
      RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\,
      RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\,
      RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\,
      RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\,
      RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\,
      RXDATA(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\,
      RXDDIEN => '0',
      RXDFEAGCHOLD => converge_gen3_reg,
      RXDFEAGCOVRDEN => '0',
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '1',
      RXDFELPMRESET => USER_RXDFELPMRESET,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '0',
      RXDFEXYDHOLD => '0',
      RXDFEXYDOVRDEN => '0',
      RXDISPERR(7 downto 0) => pipe_rxdisperr(7 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => SYNC_RXSYNC_DONE,
      RXDLYOVRDEN => '0',
      RXDLYSRESET => \rxsync_fsm_disable.fsm_rx_reg[2]\,
      RXDLYSRESETDONE => pipe_rxdlysresetdone(0),
      RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      RXELECIDLEMODE(1) => '0',
      RXELECIDLEMODE(0) => '0',
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMEN => gen3_reg_0,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => gen3_reg,
      RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0),
      RXMONITORSEL(1) => '0',
      RXMONITORSEL(0) => '0',
      RXNOTINTABLE(7 downto 0) => pipe_rxnotintable(7 downto 0),
      RXOOBRESET => '0',
      RXOSHOLD => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => pipe_rxoutclk_out(0),
      RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2) => '0',
      RXOUTCLKSEL(1) => '0',
      RXOUTCLKSEL(0) => '0',
      RXPCOMMAALIGNEN => gen3_reg_0,
      RXPCSRESET => USER_RXPCSRESET,
      RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      RXPHALIGN => rxsync_donem_reg2_reg,
      RXPHALIGNDONE => pipe_rxphaligndone(0),
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => GT_RXPMARESET089_out,
      RXPOLARITY => PIPE_RXPOLARITY(0),
      RXPRBSCNTRESET => '0',
      RXPRBSERR => pipe_rxprbserr(0),
      RXPRBSSEL(2) => '0',
      RXPRBSSEL(1) => '0',
      RXPRBSSEL(0) => '0',
      RXQPIEN => '0',
      RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\,
      RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\,
      RXRATE(2 downto 0) => RXRATE(2 downto 0),
      RXRATEDONE => RATE_RXRATEDONE,
      RXRESETDONE => USER_RXRESETDONE,
      RXSLIDE => '0',
      RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\,
      RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      RXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      RXUSERRDY => \userrdy_reg_rep__4\,
      RXUSRCLK => pclk_sel_reg,
      RXUSRCLK2 => pclk_sel_reg,
      RXVALID => rxvalid_reg1_reg,
      SETERRSTATUS => '0',
      TSTIN(19) => '1',
      TSTIN(18) => '1',
      TSTIN(17) => '1',
      TSTIN(16) => '1',
      TSTIN(15) => '1',
      TSTIN(14) => '1',
      TSTIN(13) => '1',
      TSTIN(12) => '1',
      TSTIN(11) => '1',
      TSTIN(10) => '1',
      TSTIN(9) => '1',
      TSTIN(8) => '1',
      TSTIN(7) => '1',
      TSTIN(6) => '1',
      TSTIN(5) => '1',
      TSTIN(4) => '1',
      TSTIN(3) => '1',
      TSTIN(2) => '1',
      TSTIN(1) => '1',
      TSTIN(0) => '1',
      TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0),
      TX8B10BBYPASS(7) => '0',
      TX8B10BBYPASS(6) => '0',
      TX8B10BBYPASS(5) => '0',
      TX8B10BBYPASS(4) => '0',
      TX8B10BBYPASS(3) => '0',
      TX8B10BBYPASS(2) => '0',
      TX8B10BBYPASS(1) => '0',
      TX8B10BBYPASS(0) => '0',
      TX8B10BEN => gen3_reg_0,
      TXBUFDIFFCTRL(2) => '1',
      TXBUFDIFFCTRL(1) => '0',
      TXBUFDIFFCTRL(0) => '0',
      TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(7) => '0',
      TXCHARDISPMODE(6) => '0',
      TXCHARDISPMODE(5) => '0',
      TXCHARDISPMODE(4) => '0',
      TXCHARDISPMODE(3) => '0',
      TXCHARDISPMODE(2) => '0',
      TXCHARDISPMODE(1) => '0',
      TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0),
      TXCHARDISPVAL(7) => '0',
      TXCHARDISPVAL(6) => '0',
      TXCHARDISPVAL(5) => '0',
      TXCHARDISPVAL(4) => '0',
      TXCHARDISPVAL(3) => '0',
      TXCHARDISPVAL(2) => '0',
      TXCHARDISPVAL(1) => '0',
      TXCHARDISPVAL(0) => '0',
      TXCHARISK(7) => '0',
      TXCHARISK(6) => '0',
      TXCHARISK(5) => '0',
      TXCHARISK(4) => '0',
      TXCHARISK(3) => '0',
      TXCHARISK(2) => '0',
      TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0),
      TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63) => '0',
      TXDATA(62) => '0',
      TXDATA(61) => '0',
      TXDATA(60) => '0',
      TXDATA(59) => '0',
      TXDATA(58) => '0',
      TXDATA(57) => '0',
      TXDATA(56) => '0',
      TXDATA(55) => '0',
      TXDATA(54) => '0',
      TXDATA(53) => '0',
      TXDATA(52) => '0',
      TXDATA(51) => '0',
      TXDATA(50) => '0',
      TXDATA(49) => '0',
      TXDATA(48) => '0',
      TXDATA(47) => '0',
      TXDATA(46) => '0',
      TXDATA(45) => '0',
      TXDATA(44) => '0',
      TXDATA(43) => '0',
      TXDATA(42) => '0',
      TXDATA(41) => '0',
      TXDATA(40) => '0',
      TXDATA(39) => '0',
      TXDATA(38) => '0',
      TXDATA(37) => '0',
      TXDATA(36) => '0',
      TXDATA(35) => '0',
      TXDATA(34) => '0',
      TXDATA(33) => '0',
      TXDATA(32) => '0',
      TXDATA(31) => '0',
      TXDATA(30) => '0',
      TXDATA(29) => '0',
      TXDATA(28) => '0',
      TXDATA(27) => '0',
      TXDATA(26) => '0',
      TXDATA(25) => '0',
      TXDATA(24) => '0',
      TXDATA(23) => '0',
      TXDATA(22) => '0',
      TXDATA(21) => '0',
      TXDATA(20) => '0',
      TXDATA(19) => '0',
      TXDATA(18) => '0',
      TXDATA(17) => '0',
      TXDATA(16) => '0',
      TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0),
      TXDEEMPH => PIPE_TXDEEMPH(0),
      TXDETECTRX => \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\,
      TXDIFFCTRL(3) => '1',
      TXDIFFCTRL(2) => '1',
      TXDIFFCTRL(1) => '0',
      TXDIFFCTRL(0) => '0',
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => \txsync_fsm.txdlyen_reg\,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => \txsync_fsm.fsm_tx_reg[2]\,
      TXDLYSRESETDONE => pipe_txdlysresetdone(0),
      TXDLYUPDOWN => '0',
      TXELECIDLE => PIPE_TXELECIDLE(0),
      TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2) => '0',
      TXHEADER(1) => '0',
      TXHEADER(0) => '0',
      TXINHIBIT => pipe_txinhibit(0),
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(2 downto 0),
      TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\,
      TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2) => '0',
      TXOUTCLKSEL(1) => '0',
      TXOUTCLKSEL(0) => '0',
      TXPCSRESET => '0',
      TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => \txsync_fsm.fsm_tx_reg[4]\,
      TXPHALIGNDONE => pipe_txphaligndone(0),
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => \txsync_fsm.fsm_tx_reg[4]_0\,
      TXPHINITDONE => pipe_txphinitdone(0),
      TXPHOVRDEN => '0',
      TXPISOPD => '0',
      TXPMARESET => GT_TXPMARESET092_out,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2) => '0',
      TXPRBSSEL(1) => '0',
      TXPRBSSEL(0) => '0',
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\,
      TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => RXRATE(2 downto 0),
      TXRATEDONE => RATE_TXRATEDONE,
      TXRESETDONE => USER_TXRESETDONE,
      TXSEQUENCE(6) => '0',
      TXSEQUENCE(5) => '0',
      TXSEQUENCE(4) => '0',
      TXSEQUENCE(3) => '0',
      TXSEQUENCE(2) => '0',
      TXSEQUENCE(1) => '0',
      TXSEQUENCE(0) => '0',
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      TXUSERRDY => \userrdy_reg_rep__4\,
      TXUSRCLK => pclk_sel_reg,
      TXUSRCLK2 => pclk_sel_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_35 is
  port (
    RATE_CPLLLOCK : out STD_LOGIC;
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_PHYSTATUS : out STD_LOGIC;
    rxcdrlock_reg1_reg : out STD_LOGIC;
    PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_RXRATEDONE : out STD_LOGIC;
    USER_RXRESETDONE : out STD_LOGIC;
    rxvalid_reg1_reg : out STD_LOGIC;
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_TXRATEDONE : out STD_LOGIC;
    USER_TXRESETDONE : out STD_LOGIC;
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    \fsm_reg[2]\ : in STD_LOGIC;
    \fsm_reg[0]\ : in STD_LOGIC;
    USER_EYESCANRESET : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    rst_gtreset : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpllpd_reg : in STD_LOGIC;
    qpllpd_reg_0 : in STD_LOGIC;
    \resetovrd_disble.fsm_reg[1]\ : in STD_LOGIC;
    gen3_reg : in STD_LOGIC;
    USER_RXBUFRESET : in STD_LOGIC;
    USER_RXCDRFREQRESET : in STD_LOGIC;
    USER_RXCDRRESET : in STD_LOGIC;
    gen3_reg_0 : in STD_LOGIC;
    converge_gen3_reg : in STD_LOGIC;
    USER_RXDFELPMRESET : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]\ : in STD_LOGIC;
    USER_RXPCSRESET : in STD_LOGIC;
    rxsync_donem_reg2_reg : in STD_LOGIC;
    GT_RXPMARESET0117_out : in STD_LOGIC;
    PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 );
    \userrdy_reg_rep__3\ : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    PIPE_TXDEEMPH : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\ : in STD_LOGIC;
    \txsync_fsm.txdlyen_reg\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[2]\ : in STD_LOGIC;
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    GT_TXPMARESET0120_out : in STD_LOGIC;
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 2 downto 0 );
    TXMARGIN : in STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_OOBCLK : in STD_LOGIC;
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 8 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    gt_rxvalid_q_reg : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in123_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in121_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_35 : entity is "PCIeGen1x8If64_gt_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_35;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_35 is
  signal CPLLPD0 : STD_LOGIC;
  signal CPLLRESET0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC;
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE";
begin
  pipe_rxstatus(2 downto 0) <= \^pipe_rxstatus\(2 downto 0);
cpllPDInst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_81
     port map (
      CPLLPD0 => CPLLPD0,
      CPLLRESET0 => CPLLRESET0,
      RST_CPLLRESET => RST_CPLLRESET,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      p_0_in121_in => p_0_in121_in,
      p_0_in123_in => p_0_in123_in,
      rst_cpllpd => rst_cpllpd
    );
\gt_rx_status_q[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(0),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(0)
    );
\gt_rx_status_q[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(1),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(1)
    );
\gt_rx_status_q[2]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(2),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(2)
    );
\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL
    generic map(
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"A407CC",
      CPLL_FBDIV => 5,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"0000000001CF",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => X"00018480",
      PMA_RSV2 => X"2050",
      PMA_RSV3 => B"00",
      PMA_RSV4 => X"00000000",
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"03000023FF10200020",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00000011110000",
      RXLPM_LF_CFG => B"00000011110000",
      RXOOB_CFG => B"0000110",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RX_BIAS_CFG => B"000000000100",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFE_GAIN_CFG => X"020FEA",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011110000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_KL_CFG => B"0000011111110",
      RX_DFE_KL_CFG2 => X"3290D86C",
      RX_DFE_LPM_CFG => X"0954",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '1',
      RX_DFE_UT_CFG => B"10001111000000000",
      RX_DFE_VP_CFG => B"00011111100000011",
      RX_DFE_XYD_CFG => B"0000000000000",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 4,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "3.0",
      TERM_RCAL_CFG => B"10000",
      TERM_RCAL_OVRD => '0',
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPMARESET_TIME => B"00011",
      TX_CLK25_DIV => 4,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"10100",
      TX_DEEMPH1 => B"01011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD(3) => '0',
      CLKRSVD(2) => '0',
      CLKRSVD(1) => '0',
      CLKRSVD(0) => USER_OOBCLK,
      CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\,
      CPLLLOCK => RATE_CPLLLOCK,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD0,
      CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\,
      CPLLREFCLKSEL(2) => '0',
      CPLLREFCLKSEL(1) => '0',
      CPLLREFCLKSEL(0) => '1',
      CPLLRESET => CPLLRESET0,
      DMONITOROUT(7 downto 0) => pipe_dmonitorout(7 downto 0),
      DRPADDR(8 downto 0) => DRPADDR(8 downto 0),
      DRPCLK => \resetovrd_disble.reset_reg[4]\,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => ext_ch_gt_drpdo(15 downto 0),
      DRPEN => \fsm_reg[2]\,
      DRPRDY => ext_ch_gt_drprdy(0),
      DRPWE => \fsm_reg[0]\,
      EYESCANDATAERROR => pipe_eyescandataerror(0),
      EYESCANMODE => '0',
      EYESCANRESET => USER_EYESCANRESET,
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\,
      GTRESETSEL => '0',
      GTRSVD(15) => '0',
      GTRSVD(14) => '0',
      GTRSVD(13) => '0',
      GTRSVD(12) => '0',
      GTRSVD(11) => '0',
      GTRSVD(10) => '0',
      GTRSVD(9) => '0',
      GTRSVD(8) => '0',
      GTRSVD(7) => '0',
      GTRSVD(6) => '0',
      GTRSVD(5) => '0',
      GTRSVD(4) => '0',
      GTRSVD(3) => '0',
      GTRSVD(2) => '0',
      GTRSVD(1) => '0',
      GTRSVD(0) => '0',
      GTRXRESET => rst_gtreset,
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => rst_gtreset,
      GTXRXN => pci_exp_rxn(0),
      GTXRXP => pci_exp_rxp(0),
      GTXTXN => pci_exp_txn(0),
      GTXTXP => pci_exp_txp(0),
      LOOPBACK(2) => '0',
      LOOPBACK(1) => '0',
      LOOPBACK(0) => '0',
      PCSRSVDIN(15) => '0',
      PCSRSVDIN(14) => '0',
      PCSRSVDIN(13) => '0',
      PCSRSVDIN(12) => '0',
      PCSRSVDIN(11) => '0',
      PCSRSVDIN(10) => '0',
      PCSRSVDIN(9) => '0',
      PCSRSVDIN(8) => '0',
      PCSRSVDIN(7) => '0',
      PCSRSVDIN(6) => '0',
      PCSRSVDIN(5) => '0',
      PCSRSVDIN(4) => '0',
      PCSRSVDIN(3) => '0',
      PCSRSVDIN(2) => '0',
      PCSRSVDIN(1) => '0',
      PCSRSVDIN(0) => '0',
      PCSRSVDIN2(4) => '0',
      PCSRSVDIN2(3) => '0',
      PCSRSVDIN2(2) => '0',
      PCSRSVDIN2(1) => '0',
      PCSRSVDIN2(0) => '0',
      PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => RATE_PHYSTATUS,
      PMARSVDIN(4) => '0',
      PMARSVDIN(3) => '0',
      PMARSVDIN(2) => '0',
      PMARSVDIN(1) => '0',
      PMARSVDIN(0) => '0',
      PMARSVDIN2(4) => '0',
      PMARSVDIN2(3) => '0',
      PMARSVDIN2(2) => '0',
      PMARSVDIN2(1) => '0',
      PMARSVDIN2(0) => '0',
      QPLLCLK => qpllpd_reg,
      QPLLREFCLK => qpllpd_reg_0,
      RESETOVRD => \resetovrd_disble.fsm_reg[1]\,
      RX8B10BEN => gen3_reg,
      RXBUFRESET => USER_RXBUFRESET,
      RXBUFSTATUS(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\,
      RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\,
      RXCDRFREQRESET => USER_RXCDRFREQRESET,
      RXCDRHOLD => '0',
      RXCDRLOCK => rxcdrlock_reg1_reg,
      RXCDROVRDEN => '0',
      RXCDRRESET => USER_RXCDRRESET,
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0),
      RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4),
      RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\,
      RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\,
      RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\,
      RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\,
      RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4),
      RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\,
      RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\,
      RXCHARISK(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      RXCHBONDEN => gen3_reg,
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2) => '0',
      RXCHBONDLEVEL(1) => '0',
      RXCHBONDLEVEL(0) => '0',
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\,
      RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\,
      RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\,
      RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\,
      RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\,
      RXCHBONDSLAVE => gen3_reg_0,
      RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => pipe_rxcommadet(0),
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32),
      RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\,
      RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\,
      RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\,
      RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\,
      RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\,
      RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\,
      RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\,
      RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\,
      RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\,
      RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\,
      RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\,
      RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\,
      RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\,
      RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\,
      RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\,
      RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\,
      RXDATA(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\,
      RXDDIEN => '0',
      RXDFEAGCHOLD => converge_gen3_reg,
      RXDFEAGCOVRDEN => '0',
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '1',
      RXDFELPMRESET => USER_RXDFELPMRESET,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '0',
      RXDFEXYDHOLD => '0',
      RXDFEXYDOVRDEN => '0',
      RXDISPERR(7 downto 0) => pipe_rxdisperr(7 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => SYNC_RXSYNC_DONE,
      RXDLYOVRDEN => '0',
      RXDLYSRESET => \rxsync_fsm_disable.fsm_rx_reg[2]\,
      RXDLYSRESETDONE => pipe_rxdlysresetdone(0),
      RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      RXELECIDLEMODE(1) => '0',
      RXELECIDLEMODE(0) => '0',
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMEN => gen3_reg_0,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => gen3_reg,
      RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0),
      RXMONITORSEL(1) => '0',
      RXMONITORSEL(0) => '0',
      RXNOTINTABLE(7 downto 0) => pipe_rxnotintable(7 downto 0),
      RXOOBRESET => '0',
      RXOSHOLD => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => pipe_rxoutclk_out(0),
      RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2) => '0',
      RXOUTCLKSEL(1) => '0',
      RXOUTCLKSEL(0) => '0',
      RXPCOMMAALIGNEN => gen3_reg_0,
      RXPCSRESET => USER_RXPCSRESET,
      RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      RXPHALIGN => rxsync_donem_reg2_reg,
      RXPHALIGNDONE => pipe_rxphaligndone(0),
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => GT_RXPMARESET0117_out,
      RXPOLARITY => PIPE_RXPOLARITY(0),
      RXPRBSCNTRESET => '0',
      RXPRBSERR => pipe_rxprbserr(0),
      RXPRBSSEL(2) => '0',
      RXPRBSSEL(1) => '0',
      RXPRBSSEL(0) => '0',
      RXQPIEN => '0',
      RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\,
      RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\,
      RXRATE(2 downto 0) => RXRATE(2 downto 0),
      RXRATEDONE => RATE_RXRATEDONE,
      RXRESETDONE => USER_RXRESETDONE,
      RXSLIDE => '0',
      RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\,
      RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      RXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      RXUSERRDY => \userrdy_reg_rep__3\,
      RXUSRCLK => pclk_sel_reg,
      RXUSRCLK2 => pclk_sel_reg,
      RXVALID => rxvalid_reg1_reg,
      SETERRSTATUS => '0',
      TSTIN(19) => '1',
      TSTIN(18) => '1',
      TSTIN(17) => '1',
      TSTIN(16) => '1',
      TSTIN(15) => '1',
      TSTIN(14) => '1',
      TSTIN(13) => '1',
      TSTIN(12) => '1',
      TSTIN(11) => '1',
      TSTIN(10) => '1',
      TSTIN(9) => '1',
      TSTIN(8) => '1',
      TSTIN(7) => '1',
      TSTIN(6) => '1',
      TSTIN(5) => '1',
      TSTIN(4) => '1',
      TSTIN(3) => '1',
      TSTIN(2) => '1',
      TSTIN(1) => '1',
      TSTIN(0) => '1',
      TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0),
      TX8B10BBYPASS(7) => '0',
      TX8B10BBYPASS(6) => '0',
      TX8B10BBYPASS(5) => '0',
      TX8B10BBYPASS(4) => '0',
      TX8B10BBYPASS(3) => '0',
      TX8B10BBYPASS(2) => '0',
      TX8B10BBYPASS(1) => '0',
      TX8B10BBYPASS(0) => '0',
      TX8B10BEN => gen3_reg_0,
      TXBUFDIFFCTRL(2) => '1',
      TXBUFDIFFCTRL(1) => '0',
      TXBUFDIFFCTRL(0) => '0',
      TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(7) => '0',
      TXCHARDISPMODE(6) => '0',
      TXCHARDISPMODE(5) => '0',
      TXCHARDISPMODE(4) => '0',
      TXCHARDISPMODE(3) => '0',
      TXCHARDISPMODE(2) => '0',
      TXCHARDISPMODE(1) => '0',
      TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0),
      TXCHARDISPVAL(7) => '0',
      TXCHARDISPVAL(6) => '0',
      TXCHARDISPVAL(5) => '0',
      TXCHARDISPVAL(4) => '0',
      TXCHARDISPVAL(3) => '0',
      TXCHARDISPVAL(2) => '0',
      TXCHARDISPVAL(1) => '0',
      TXCHARDISPVAL(0) => '0',
      TXCHARISK(7) => '0',
      TXCHARISK(6) => '0',
      TXCHARISK(5) => '0',
      TXCHARISK(4) => '0',
      TXCHARISK(3) => '0',
      TXCHARISK(2) => '0',
      TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0),
      TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63) => '0',
      TXDATA(62) => '0',
      TXDATA(61) => '0',
      TXDATA(60) => '0',
      TXDATA(59) => '0',
      TXDATA(58) => '0',
      TXDATA(57) => '0',
      TXDATA(56) => '0',
      TXDATA(55) => '0',
      TXDATA(54) => '0',
      TXDATA(53) => '0',
      TXDATA(52) => '0',
      TXDATA(51) => '0',
      TXDATA(50) => '0',
      TXDATA(49) => '0',
      TXDATA(48) => '0',
      TXDATA(47) => '0',
      TXDATA(46) => '0',
      TXDATA(45) => '0',
      TXDATA(44) => '0',
      TXDATA(43) => '0',
      TXDATA(42) => '0',
      TXDATA(41) => '0',
      TXDATA(40) => '0',
      TXDATA(39) => '0',
      TXDATA(38) => '0',
      TXDATA(37) => '0',
      TXDATA(36) => '0',
      TXDATA(35) => '0',
      TXDATA(34) => '0',
      TXDATA(33) => '0',
      TXDATA(32) => '0',
      TXDATA(31) => '0',
      TXDATA(30) => '0',
      TXDATA(29) => '0',
      TXDATA(28) => '0',
      TXDATA(27) => '0',
      TXDATA(26) => '0',
      TXDATA(25) => '0',
      TXDATA(24) => '0',
      TXDATA(23) => '0',
      TXDATA(22) => '0',
      TXDATA(21) => '0',
      TXDATA(20) => '0',
      TXDATA(19) => '0',
      TXDATA(18) => '0',
      TXDATA(17) => '0',
      TXDATA(16) => '0',
      TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0),
      TXDEEMPH => PIPE_TXDEEMPH(0),
      TXDETECTRX => \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\,
      TXDIFFCTRL(3) => '1',
      TXDIFFCTRL(2) => '1',
      TXDIFFCTRL(1) => '0',
      TXDIFFCTRL(0) => '0',
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => \txsync_fsm.txdlyen_reg\,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => \txsync_fsm.fsm_tx_reg[2]\,
      TXDLYSRESETDONE => pipe_txdlysresetdone(0),
      TXDLYUPDOWN => '0',
      TXELECIDLE => PIPE_TXELECIDLE(0),
      TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2) => '0',
      TXHEADER(1) => '0',
      TXHEADER(0) => '0',
      TXINHIBIT => pipe_txinhibit(0),
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => TXMARGIN(2 downto 0),
      TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\,
      TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2) => '0',
      TXOUTCLKSEL(1) => '0',
      TXOUTCLKSEL(0) => '0',
      TXPCSRESET => '0',
      TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => \txsync_fsm.fsm_tx_reg[4]\,
      TXPHALIGNDONE => pipe_txphaligndone(0),
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => \txsync_fsm.fsm_tx_reg[4]_0\,
      TXPHINITDONE => pipe_txphinitdone(0),
      TXPHOVRDEN => '0',
      TXPISOPD => '0',
      TXPMARESET => GT_TXPMARESET0120_out,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2) => '0',
      TXPRBSSEL(1) => '0',
      TXPRBSSEL(0) => '0',
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\,
      TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => RXRATE(2 downto 0),
      TXRATEDONE => RATE_TXRATEDONE,
      TXRESETDONE => USER_TXRESETDONE,
      TXSEQUENCE(6) => '0',
      TXSEQUENCE(5) => '0',
      TXSEQUENCE(4) => '0',
      TXSEQUENCE(3) => '0',
      TXSEQUENCE(2) => '0',
      TXSEQUENCE(1) => '0',
      TXSEQUENCE(0) => '0',
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      TXUSERRDY => \userrdy_reg_rep__3\,
      TXUSRCLK => pclk_sel_reg,
      TXUSRCLK2 => pclk_sel_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_41 is
  port (
    RATE_CPLLLOCK : out STD_LOGIC;
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_PHYSTATUS : out STD_LOGIC;
    rxcdrlock_reg1_reg : out STD_LOGIC;
    PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_RXRATEDONE : out STD_LOGIC;
    USER_RXRESETDONE : out STD_LOGIC;
    rxvalid_reg1_reg : out STD_LOGIC;
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_TXRATEDONE : out STD_LOGIC;
    USER_TXRESETDONE : out STD_LOGIC;
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 7 downto 0 );
    rxphaligndone_s_reg1_reg : out STD_LOGIC;
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    \fsm_reg[2]\ : in STD_LOGIC;
    \fsm_reg[0]\ : in STD_LOGIC;
    USER_EYESCANRESET : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    rst_gtreset : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpllpd_reg : in STD_LOGIC;
    qpllpd_reg_0 : in STD_LOGIC;
    \resetovrd_disble.fsm_reg[1]\ : in STD_LOGIC;
    gen3_reg : in STD_LOGIC;
    USER_RXBUFRESET : in STD_LOGIC;
    USER_RXCDRFREQRESET : in STD_LOGIC;
    USER_RXCDRRESET : in STD_LOGIC;
    gen3_reg_0 : in STD_LOGIC;
    converge_gen3_reg : in STD_LOGIC;
    USER_RXDFELPMRESET : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]\ : in STD_LOGIC;
    USER_RXPCSRESET : in STD_LOGIC;
    rxsync_donem_reg2_reg : in STD_LOGIC;
    GT_RXPMARESET071_out : in STD_LOGIC;
    PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 );
    \userrdy_reg_rep__2\ : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    PIPE_TXDEEMPH : in STD_LOGIC_VECTOR ( 0 to 0 );
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\ : in STD_LOGIC;
    \txsync_fsm.txdlyen_reg\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[2]\ : in STD_LOGIC;
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    GT_TXPMARESET074_out : in STD_LOGIC;
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_OOBCLK : in STD_LOGIC;
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    gt_rxvalid_q_reg : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in77_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in75_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_41 : entity is "PCIeGen1x8If64_gt_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_41;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_41 is
  signal CPLLPD0 : STD_LOGIC;
  signal CPLLRESET0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC;
  signal \^pipe_rxphaligndone\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxphaligndone_s_reg1_i_2_n_0 : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE";
begin
  pipe_rxphaligndone(0) <= \^pipe_rxphaligndone\(0);
  pipe_rxstatus(2 downto 0) <= \^pipe_rxstatus\(2 downto 0);
cpllPDInst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_79
     port map (
      CPLLPD0 => CPLLPD0,
      CPLLRESET0 => CPLLRESET0,
      RST_CPLLRESET => RST_CPLLRESET,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      p_0_in75_in => p_0_in75_in,
      p_0_in77_in => p_0_in77_in,
      rst_cpllpd => rst_cpllpd
    );
\gt_rx_status_q[0]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(0),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(0)
    );
\gt_rx_status_q[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(1),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(1)
    );
\gt_rx_status_q[2]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(2),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(2)
    );
\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL
    generic map(
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"A407CC",
      CPLL_FBDIV => 5,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"0000000001CF",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => X"00018480",
      PMA_RSV2 => X"2050",
      PMA_RSV3 => B"00",
      PMA_RSV4 => X"00000000",
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"03000023FF10200020",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00000011110000",
      RXLPM_LF_CFG => B"00000011110000",
      RXOOB_CFG => B"0000110",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RX_BIAS_CFG => B"000000000100",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFE_GAIN_CFG => X"020FEA",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011110000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_KL_CFG => B"0000011111110",
      RX_DFE_KL_CFG2 => X"3290D86C",
      RX_DFE_LPM_CFG => X"0954",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '1',
      RX_DFE_UT_CFG => B"10001111000000000",
      RX_DFE_VP_CFG => B"00011111100000011",
      RX_DFE_XYD_CFG => B"0000000000000",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 4,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "3.0",
      TERM_RCAL_CFG => B"10000",
      TERM_RCAL_OVRD => '0',
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPMARESET_TIME => B"00011",
      TX_CLK25_DIV => 4,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"10100",
      TX_DEEMPH1 => B"01011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD(3) => '0',
      CLKRSVD(2) => '0',
      CLKRSVD(1) => '0',
      CLKRSVD(0) => USER_OOBCLK,
      CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\,
      CPLLLOCK => RATE_CPLLLOCK,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD0,
      CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\,
      CPLLREFCLKSEL(2) => '0',
      CPLLREFCLKSEL(1) => '0',
      CPLLREFCLKSEL(0) => '1',
      CPLLRESET => CPLLRESET0,
      DMONITOROUT(7 downto 0) => pipe_dmonitorout(7 downto 0),
      DRPADDR(8 downto 0) => DRPADDR(8 downto 0),
      DRPCLK => \resetovrd_disble.reset_reg[4]\,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => ext_ch_gt_drpdo(15 downto 0),
      DRPEN => \fsm_reg[2]\,
      DRPRDY => ext_ch_gt_drprdy(0),
      DRPWE => \fsm_reg[0]\,
      EYESCANDATAERROR => pipe_eyescandataerror(0),
      EYESCANMODE => '0',
      EYESCANRESET => USER_EYESCANRESET,
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\,
      GTRESETSEL => '0',
      GTRSVD(15) => '0',
      GTRSVD(14) => '0',
      GTRSVD(13) => '0',
      GTRSVD(12) => '0',
      GTRSVD(11) => '0',
      GTRSVD(10) => '0',
      GTRSVD(9) => '0',
      GTRSVD(8) => '0',
      GTRSVD(7) => '0',
      GTRSVD(6) => '0',
      GTRSVD(5) => '0',
      GTRSVD(4) => '0',
      GTRSVD(3) => '0',
      GTRSVD(2) => '0',
      GTRSVD(1) => '0',
      GTRSVD(0) => '0',
      GTRXRESET => rst_gtreset,
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => rst_gtreset,
      GTXRXN => pci_exp_rxn(0),
      GTXRXP => pci_exp_rxp(0),
      GTXTXN => pci_exp_txn(0),
      GTXTXP => pci_exp_txp(0),
      LOOPBACK(2) => '0',
      LOOPBACK(1) => '0',
      LOOPBACK(0) => '0',
      PCSRSVDIN(15) => '0',
      PCSRSVDIN(14) => '0',
      PCSRSVDIN(13) => '0',
      PCSRSVDIN(12) => '0',
      PCSRSVDIN(11) => '0',
      PCSRSVDIN(10) => '0',
      PCSRSVDIN(9) => '0',
      PCSRSVDIN(8) => '0',
      PCSRSVDIN(7) => '0',
      PCSRSVDIN(6) => '0',
      PCSRSVDIN(5) => '0',
      PCSRSVDIN(4) => '0',
      PCSRSVDIN(3) => '0',
      PCSRSVDIN(2) => '0',
      PCSRSVDIN(1) => '0',
      PCSRSVDIN(0) => '0',
      PCSRSVDIN2(4) => '0',
      PCSRSVDIN2(3) => '0',
      PCSRSVDIN2(2) => '0',
      PCSRSVDIN2(1) => '0',
      PCSRSVDIN2(0) => '0',
      PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => RATE_PHYSTATUS,
      PMARSVDIN(4) => '0',
      PMARSVDIN(3) => '0',
      PMARSVDIN(2) => '0',
      PMARSVDIN(1) => '0',
      PMARSVDIN(0) => '0',
      PMARSVDIN2(4) => '0',
      PMARSVDIN2(3) => '0',
      PMARSVDIN2(2) => '0',
      PMARSVDIN2(1) => '0',
      PMARSVDIN2(0) => '0',
      QPLLCLK => qpllpd_reg,
      QPLLREFCLK => qpllpd_reg_0,
      RESETOVRD => \resetovrd_disble.fsm_reg[1]\,
      RX8B10BEN => gen3_reg,
      RXBUFRESET => USER_RXBUFRESET,
      RXBUFSTATUS(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\,
      RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\,
      RXCDRFREQRESET => USER_RXCDRFREQRESET,
      RXCDRHOLD => '0',
      RXCDRLOCK => rxcdrlock_reg1_reg,
      RXCDROVRDEN => '0',
      RXCDRRESET => USER_RXCDRRESET,
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0),
      RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4),
      RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\,
      RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\,
      RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\,
      RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\,
      RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4),
      RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\,
      RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\,
      RXCHARISK(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      RXCHBONDEN => gen3_reg,
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2) => '0',
      RXCHBONDLEVEL(1) => '0',
      RXCHBONDLEVEL(0) => '0',
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\,
      RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\,
      RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\,
      RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\,
      RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\,
      RXCHBONDSLAVE => gen3_reg_0,
      RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => pipe_rxcommadet(0),
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32),
      RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\,
      RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\,
      RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\,
      RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\,
      RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\,
      RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\,
      RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\,
      RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\,
      RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\,
      RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\,
      RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\,
      RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\,
      RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\,
      RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\,
      RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\,
      RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\,
      RXDATA(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\,
      RXDDIEN => '0',
      RXDFEAGCHOLD => converge_gen3_reg,
      RXDFEAGCOVRDEN => '0',
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '1',
      RXDFELPMRESET => USER_RXDFELPMRESET,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '0',
      RXDFEXYDHOLD => '0',
      RXDFEXYDOVRDEN => '0',
      RXDISPERR(7 downto 0) => pipe_rxdisperr(7 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => SYNC_RXSYNC_DONE,
      RXDLYOVRDEN => '0',
      RXDLYSRESET => \rxsync_fsm_disable.fsm_rx_reg[2]\,
      RXDLYSRESETDONE => pipe_rxdlysresetdone(0),
      RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      RXELECIDLEMODE(1) => '0',
      RXELECIDLEMODE(0) => '0',
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMEN => gen3_reg_0,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => gen3_reg,
      RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0),
      RXMONITORSEL(1) => '0',
      RXMONITORSEL(0) => '0',
      RXNOTINTABLE(7 downto 0) => pipe_rxnotintable(7 downto 0),
      RXOOBRESET => '0',
      RXOSHOLD => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => pipe_rxoutclk_out(0),
      RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2) => '0',
      RXOUTCLKSEL(1) => '0',
      RXOUTCLKSEL(0) => '0',
      RXPCOMMAALIGNEN => gen3_reg_0,
      RXPCSRESET => USER_RXPCSRESET,
      RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      RXPHALIGN => rxsync_donem_reg2_reg,
      RXPHALIGNDONE => \^pipe_rxphaligndone\(0),
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => GT_RXPMARESET071_out,
      RXPOLARITY => PIPE_RXPOLARITY(0),
      RXPRBSCNTRESET => '0',
      RXPRBSERR => pipe_rxprbserr(0),
      RXPRBSSEL(2) => '0',
      RXPRBSSEL(1) => '0',
      RXPRBSSEL(0) => '0',
      RXQPIEN => '0',
      RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\,
      RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\,
      RXRATE(2 downto 0) => RXRATE(2 downto 0),
      RXRATEDONE => RATE_RXRATEDONE,
      RXRESETDONE => USER_RXRESETDONE,
      RXSLIDE => '0',
      RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\,
      RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      RXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      RXUSERRDY => \userrdy_reg_rep__2\,
      RXUSRCLK => pclk_sel_reg,
      RXUSRCLK2 => pclk_sel_reg,
      RXVALID => rxvalid_reg1_reg,
      SETERRSTATUS => '0',
      TSTIN(19) => '1',
      TSTIN(18) => '1',
      TSTIN(17) => '1',
      TSTIN(16) => '1',
      TSTIN(15) => '1',
      TSTIN(14) => '1',
      TSTIN(13) => '1',
      TSTIN(12) => '1',
      TSTIN(11) => '1',
      TSTIN(10) => '1',
      TSTIN(9) => '1',
      TSTIN(8) => '1',
      TSTIN(7) => '1',
      TSTIN(6) => '1',
      TSTIN(5) => '1',
      TSTIN(4) => '1',
      TSTIN(3) => '1',
      TSTIN(2) => '1',
      TSTIN(1) => '1',
      TSTIN(0) => '1',
      TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0),
      TX8B10BBYPASS(7) => '0',
      TX8B10BBYPASS(6) => '0',
      TX8B10BBYPASS(5) => '0',
      TX8B10BBYPASS(4) => '0',
      TX8B10BBYPASS(3) => '0',
      TX8B10BBYPASS(2) => '0',
      TX8B10BBYPASS(1) => '0',
      TX8B10BBYPASS(0) => '0',
      TX8B10BEN => gen3_reg_0,
      TXBUFDIFFCTRL(2) => '1',
      TXBUFDIFFCTRL(1) => '0',
      TXBUFDIFFCTRL(0) => '0',
      TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(7) => '0',
      TXCHARDISPMODE(6) => '0',
      TXCHARDISPMODE(5) => '0',
      TXCHARDISPMODE(4) => '0',
      TXCHARDISPMODE(3) => '0',
      TXCHARDISPMODE(2) => '0',
      TXCHARDISPMODE(1) => '0',
      TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0),
      TXCHARDISPVAL(7) => '0',
      TXCHARDISPVAL(6) => '0',
      TXCHARDISPVAL(5) => '0',
      TXCHARDISPVAL(4) => '0',
      TXCHARDISPVAL(3) => '0',
      TXCHARDISPVAL(2) => '0',
      TXCHARDISPVAL(1) => '0',
      TXCHARDISPVAL(0) => '0',
      TXCHARISK(7) => '0',
      TXCHARISK(6) => '0',
      TXCHARISK(5) => '0',
      TXCHARISK(4) => '0',
      TXCHARISK(3) => '0',
      TXCHARISK(2) => '0',
      TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0),
      TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63) => '0',
      TXDATA(62) => '0',
      TXDATA(61) => '0',
      TXDATA(60) => '0',
      TXDATA(59) => '0',
      TXDATA(58) => '0',
      TXDATA(57) => '0',
      TXDATA(56) => '0',
      TXDATA(55) => '0',
      TXDATA(54) => '0',
      TXDATA(53) => '0',
      TXDATA(52) => '0',
      TXDATA(51) => '0',
      TXDATA(50) => '0',
      TXDATA(49) => '0',
      TXDATA(48) => '0',
      TXDATA(47) => '0',
      TXDATA(46) => '0',
      TXDATA(45) => '0',
      TXDATA(44) => '0',
      TXDATA(43) => '0',
      TXDATA(42) => '0',
      TXDATA(41) => '0',
      TXDATA(40) => '0',
      TXDATA(39) => '0',
      TXDATA(38) => '0',
      TXDATA(37) => '0',
      TXDATA(36) => '0',
      TXDATA(35) => '0',
      TXDATA(34) => '0',
      TXDATA(33) => '0',
      TXDATA(32) => '0',
      TXDATA(31) => '0',
      TXDATA(30) => '0',
      TXDATA(29) => '0',
      TXDATA(28) => '0',
      TXDATA(27) => '0',
      TXDATA(26) => '0',
      TXDATA(25) => '0',
      TXDATA(24) => '0',
      TXDATA(23) => '0',
      TXDATA(22) => '0',
      TXDATA(21) => '0',
      TXDATA(20) => '0',
      TXDATA(19) => '0',
      TXDATA(18) => '0',
      TXDATA(17) => '0',
      TXDATA(16) => '0',
      TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0),
      TXDEEMPH => PIPE_TXDEEMPH(0),
      TXDETECTRX => \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\,
      TXDIFFCTRL(3) => '1',
      TXDIFFCTRL(2) => '1',
      TXDIFFCTRL(1) => '0',
      TXDIFFCTRL(0) => '0',
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => \txsync_fsm.txdlyen_reg\,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => \txsync_fsm.fsm_tx_reg[2]\,
      TXDLYSRESETDONE => pipe_txdlysresetdone(0),
      TXDLYUPDOWN => '0',
      TXELECIDLE => PIPE_TXELECIDLE(0),
      TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2) => '0',
      TXHEADER(1) => '0',
      TXHEADER(0) => '0',
      TXINHIBIT => pipe_txinhibit(0),
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(2 downto 0),
      TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\,
      TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2) => '0',
      TXOUTCLKSEL(1) => '0',
      TXOUTCLKSEL(0) => '0',
      TXPCSRESET => '0',
      TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => \txsync_fsm.fsm_tx_reg[4]\,
      TXPHALIGNDONE => pipe_txphaligndone(0),
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => \txsync_fsm.fsm_tx_reg[4]_0\,
      TXPHINITDONE => pipe_txphinitdone(0),
      TXPHOVRDEN => '0',
      TXPISOPD => '0',
      TXPMARESET => GT_TXPMARESET074_out,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2) => '0',
      TXPRBSSEL(1) => '0',
      TXPRBSSEL(0) => '0',
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\,
      TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => RXRATE(2 downto 0),
      TXRATEDONE => RATE_TXRATEDONE,
      TXRESETDONE => USER_TXRESETDONE,
      TXSEQUENCE(6) => '0',
      TXSEQUENCE(5) => '0',
      TXSEQUENCE(4) => '0',
      TXSEQUENCE(3) => '0',
      TXSEQUENCE(2) => '0',
      TXSEQUENCE(1) => '0',
      TXSEQUENCE(0) => '0',
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      TXUSERRDY => \userrdy_reg_rep__2\,
      TXUSRCLK => pclk_sel_reg,
      TXUSRCLK2 => pclk_sel_reg
    );
rxphaligndone_s_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rxphaligndone_s_reg1_i_2_n_0,
      I1 => \resetovrd_disble.reset_reg[4]_0\(0),
      O => rxphaligndone_s_reg1_reg
    );
rxphaligndone_s_reg1_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^pipe_rxphaligndone\(0),
      I1 => \resetovrd_disble.reset_reg[4]_0\(1),
      I2 => \resetovrd_disble.reset_reg[4]_0\(4),
      I3 => \resetovrd_disble.reset_reg[4]_0\(5),
      I4 => \resetovrd_disble.reset_reg[4]_0\(2),
      I5 => \resetovrd_disble.reset_reg[4]_0\(3),
      O => rxphaligndone_s_reg1_i_2_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_47 is
  port (
    RATE_CPLLLOCK : out STD_LOGIC;
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_PHYSTATUS : out STD_LOGIC;
    rxcdrlock_reg1_reg : out STD_LOGIC;
    PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_RXRATEDONE : out STD_LOGIC;
    USER_RXRESETDONE : out STD_LOGIC;
    rxvalid_reg1_reg : out STD_LOGIC;
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_TXRATEDONE : out STD_LOGIC;
    USER_TXRESETDONE : out STD_LOGIC;
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    \fsm_reg[2]\ : in STD_LOGIC;
    \fsm_reg[0]\ : in STD_LOGIC;
    USER_EYESCANRESET : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    rst_gtreset : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpllpd_reg : in STD_LOGIC;
    qpllpd_reg_0 : in STD_LOGIC;
    \resetovrd_disble.fsm_reg[1]\ : in STD_LOGIC;
    gen3_reg : in STD_LOGIC;
    USER_RXBUFRESET : in STD_LOGIC;
    USER_RXCDRFREQRESET : in STD_LOGIC;
    USER_RXCDRRESET : in STD_LOGIC;
    gen3_reg_0 : in STD_LOGIC;
    GT_RX_CONVERGE0 : in STD_LOGIC;
    USER_RXDFELPMRESET : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]\ : in STD_LOGIC;
    USER_RXPCSRESET : in STD_LOGIC;
    rxsync_donem_reg2_reg : in STD_LOGIC;
    GT_RXPMARESET061_out : in STD_LOGIC;
    PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 );
    \userrdy_reg_rep__1\ : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    PIPE_TXDEEMPH : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDETECTRX : in STD_LOGIC;
    \txsync_fsm.txdlyen_reg\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[2]\ : in STD_LOGIC;
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    GT_TXPMARESET064_out : in STD_LOGIC;
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXMARGIN : in STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_OOBCLK : in STD_LOGIC;
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 8 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    gt_rxvalid_q_reg : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in67_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in65_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_47 : entity is "PCIeGen1x8If64_gt_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_47;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_47 is
  signal CPLLPD0 : STD_LOGIC;
  signal CPLLRESET0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC;
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE";
begin
  pipe_rxstatus(2 downto 0) <= \^pipe_rxstatus\(2 downto 0);
cpllPDInst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_77
     port map (
      CPLLPD0 => CPLLPD0,
      CPLLRESET0 => CPLLRESET0,
      RST_CPLLRESET => RST_CPLLRESET,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      p_0_in65_in => p_0_in65_in,
      p_0_in67_in => p_0_in67_in,
      rst_cpllpd => rst_cpllpd
    );
\gt_rx_status_q[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(0),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(0)
    );
\gt_rx_status_q[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(1),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(1)
    );
\gt_rx_status_q[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(2),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(2)
    );
\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL
    generic map(
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"A407CC",
      CPLL_FBDIV => 5,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"0000000001CF",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => X"00018480",
      PMA_RSV2 => X"2050",
      PMA_RSV3 => B"00",
      PMA_RSV4 => X"00000000",
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"03000023FF10200020",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00000011110000",
      RXLPM_LF_CFG => B"00000011110000",
      RXOOB_CFG => B"0000110",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RX_BIAS_CFG => B"000000000100",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFE_GAIN_CFG => X"020FEA",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011110000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_KL_CFG => B"0000011111110",
      RX_DFE_KL_CFG2 => X"3290D86C",
      RX_DFE_LPM_CFG => X"0954",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '1',
      RX_DFE_UT_CFG => B"10001111000000000",
      RX_DFE_VP_CFG => B"00011111100000011",
      RX_DFE_XYD_CFG => B"0000000000000",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 4,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "3.0",
      TERM_RCAL_CFG => B"10000",
      TERM_RCAL_OVRD => '0',
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPMARESET_TIME => B"00011",
      TX_CLK25_DIV => 4,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"10100",
      TX_DEEMPH1 => B"01011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD(3) => '0',
      CLKRSVD(2) => '0',
      CLKRSVD(1) => '0',
      CLKRSVD(0) => USER_OOBCLK,
      CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\,
      CPLLLOCK => RATE_CPLLLOCK,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD0,
      CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\,
      CPLLREFCLKSEL(2) => '0',
      CPLLREFCLKSEL(1) => '0',
      CPLLREFCLKSEL(0) => '1',
      CPLLRESET => CPLLRESET0,
      DMONITOROUT(7 downto 0) => pipe_dmonitorout(7 downto 0),
      DRPADDR(8 downto 0) => DRPADDR(8 downto 0),
      DRPCLK => \resetovrd_disble.reset_reg[4]\,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => ext_ch_gt_drpdo(15 downto 0),
      DRPEN => \fsm_reg[2]\,
      DRPRDY => ext_ch_gt_drprdy(0),
      DRPWE => \fsm_reg[0]\,
      EYESCANDATAERROR => pipe_eyescandataerror(0),
      EYESCANMODE => '0',
      EYESCANRESET => USER_EYESCANRESET,
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\,
      GTRESETSEL => '0',
      GTRSVD(15) => '0',
      GTRSVD(14) => '0',
      GTRSVD(13) => '0',
      GTRSVD(12) => '0',
      GTRSVD(11) => '0',
      GTRSVD(10) => '0',
      GTRSVD(9) => '0',
      GTRSVD(8) => '0',
      GTRSVD(7) => '0',
      GTRSVD(6) => '0',
      GTRSVD(5) => '0',
      GTRSVD(4) => '0',
      GTRSVD(3) => '0',
      GTRSVD(2) => '0',
      GTRSVD(1) => '0',
      GTRSVD(0) => '0',
      GTRXRESET => rst_gtreset,
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => rst_gtreset,
      GTXRXN => pci_exp_rxn(0),
      GTXRXP => pci_exp_rxp(0),
      GTXTXN => pci_exp_txn(0),
      GTXTXP => pci_exp_txp(0),
      LOOPBACK(2) => '0',
      LOOPBACK(1) => '0',
      LOOPBACK(0) => '0',
      PCSRSVDIN(15) => '0',
      PCSRSVDIN(14) => '0',
      PCSRSVDIN(13) => '0',
      PCSRSVDIN(12) => '0',
      PCSRSVDIN(11) => '0',
      PCSRSVDIN(10) => '0',
      PCSRSVDIN(9) => '0',
      PCSRSVDIN(8) => '0',
      PCSRSVDIN(7) => '0',
      PCSRSVDIN(6) => '0',
      PCSRSVDIN(5) => '0',
      PCSRSVDIN(4) => '0',
      PCSRSVDIN(3) => '0',
      PCSRSVDIN(2) => '0',
      PCSRSVDIN(1) => '0',
      PCSRSVDIN(0) => '0',
      PCSRSVDIN2(4) => '0',
      PCSRSVDIN2(3) => '0',
      PCSRSVDIN2(2) => '0',
      PCSRSVDIN2(1) => '0',
      PCSRSVDIN2(0) => '0',
      PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => RATE_PHYSTATUS,
      PMARSVDIN(4) => '0',
      PMARSVDIN(3) => '0',
      PMARSVDIN(2) => '0',
      PMARSVDIN(1) => '0',
      PMARSVDIN(0) => '0',
      PMARSVDIN2(4) => '0',
      PMARSVDIN2(3) => '0',
      PMARSVDIN2(2) => '0',
      PMARSVDIN2(1) => '0',
      PMARSVDIN2(0) => '0',
      QPLLCLK => qpllpd_reg,
      QPLLREFCLK => qpllpd_reg_0,
      RESETOVRD => \resetovrd_disble.fsm_reg[1]\,
      RX8B10BEN => gen3_reg,
      RXBUFRESET => USER_RXBUFRESET,
      RXBUFSTATUS(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\,
      RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\,
      RXCDRFREQRESET => USER_RXCDRFREQRESET,
      RXCDRHOLD => '0',
      RXCDRLOCK => rxcdrlock_reg1_reg,
      RXCDROVRDEN => '0',
      RXCDRRESET => USER_RXCDRRESET,
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0),
      RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4),
      RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\,
      RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\,
      RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\,
      RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\,
      RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4),
      RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\,
      RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\,
      RXCHARISK(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      RXCHBONDEN => gen3_reg,
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2) => '0',
      RXCHBONDLEVEL(1) => '0',
      RXCHBONDLEVEL(0) => '0',
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\,
      RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\,
      RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\,
      RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\,
      RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\,
      RXCHBONDSLAVE => gen3_reg_0,
      RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => pipe_rxcommadet(0),
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32),
      RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\,
      RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\,
      RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\,
      RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\,
      RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\,
      RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\,
      RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\,
      RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\,
      RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\,
      RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\,
      RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\,
      RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\,
      RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\,
      RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\,
      RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\,
      RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\,
      RXDATA(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\,
      RXDDIEN => '0',
      RXDFEAGCHOLD => GT_RX_CONVERGE0,
      RXDFEAGCOVRDEN => '0',
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '1',
      RXDFELPMRESET => USER_RXDFELPMRESET,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '0',
      RXDFEXYDHOLD => '0',
      RXDFEXYDOVRDEN => '0',
      RXDISPERR(7 downto 0) => pipe_rxdisperr(7 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => SYNC_RXSYNC_DONE,
      RXDLYOVRDEN => '0',
      RXDLYSRESET => \rxsync_fsm_disable.fsm_rx_reg[2]\,
      RXDLYSRESETDONE => pipe_rxdlysresetdone(0),
      RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      RXELECIDLEMODE(1) => '0',
      RXELECIDLEMODE(0) => '0',
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMEN => gen3_reg_0,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => gen3_reg,
      RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0),
      RXMONITORSEL(1) => '0',
      RXMONITORSEL(0) => '0',
      RXNOTINTABLE(7 downto 0) => pipe_rxnotintable(7 downto 0),
      RXOOBRESET => '0',
      RXOSHOLD => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => pipe_rxoutclk_out(0),
      RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2) => '0',
      RXOUTCLKSEL(1) => '0',
      RXOUTCLKSEL(0) => '0',
      RXPCOMMAALIGNEN => gen3_reg_0,
      RXPCSRESET => USER_RXPCSRESET,
      RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      RXPHALIGN => rxsync_donem_reg2_reg,
      RXPHALIGNDONE => pipe_rxphaligndone(0),
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => GT_RXPMARESET061_out,
      RXPOLARITY => PIPE_RXPOLARITY(0),
      RXPRBSCNTRESET => '0',
      RXPRBSERR => pipe_rxprbserr(0),
      RXPRBSSEL(2) => '0',
      RXPRBSSEL(1) => '0',
      RXPRBSSEL(0) => '0',
      RXQPIEN => '0',
      RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\,
      RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\,
      RXRATE(2 downto 0) => RXRATE(2 downto 0),
      RXRATEDONE => RATE_RXRATEDONE,
      RXRESETDONE => USER_RXRESETDONE,
      RXSLIDE => '0',
      RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\,
      RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      RXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      RXUSERRDY => \userrdy_reg_rep__1\,
      RXUSRCLK => pclk_sel_reg,
      RXUSRCLK2 => pclk_sel_reg,
      RXVALID => rxvalid_reg1_reg,
      SETERRSTATUS => '0',
      TSTIN(19) => '1',
      TSTIN(18) => '1',
      TSTIN(17) => '1',
      TSTIN(16) => '1',
      TSTIN(15) => '1',
      TSTIN(14) => '1',
      TSTIN(13) => '1',
      TSTIN(12) => '1',
      TSTIN(11) => '1',
      TSTIN(10) => '1',
      TSTIN(9) => '1',
      TSTIN(8) => '1',
      TSTIN(7) => '1',
      TSTIN(6) => '1',
      TSTIN(5) => '1',
      TSTIN(4) => '1',
      TSTIN(3) => '1',
      TSTIN(2) => '1',
      TSTIN(1) => '1',
      TSTIN(0) => '1',
      TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0),
      TX8B10BBYPASS(7) => '0',
      TX8B10BBYPASS(6) => '0',
      TX8B10BBYPASS(5) => '0',
      TX8B10BBYPASS(4) => '0',
      TX8B10BBYPASS(3) => '0',
      TX8B10BBYPASS(2) => '0',
      TX8B10BBYPASS(1) => '0',
      TX8B10BBYPASS(0) => '0',
      TX8B10BEN => gen3_reg_0,
      TXBUFDIFFCTRL(2) => '1',
      TXBUFDIFFCTRL(1) => '0',
      TXBUFDIFFCTRL(0) => '0',
      TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(7) => '0',
      TXCHARDISPMODE(6) => '0',
      TXCHARDISPMODE(5) => '0',
      TXCHARDISPMODE(4) => '0',
      TXCHARDISPMODE(3) => '0',
      TXCHARDISPMODE(2) => '0',
      TXCHARDISPMODE(1) => '0',
      TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0),
      TXCHARDISPVAL(7) => '0',
      TXCHARDISPVAL(6) => '0',
      TXCHARDISPVAL(5) => '0',
      TXCHARDISPVAL(4) => '0',
      TXCHARDISPVAL(3) => '0',
      TXCHARDISPVAL(2) => '0',
      TXCHARDISPVAL(1) => '0',
      TXCHARDISPVAL(0) => '0',
      TXCHARISK(7) => '0',
      TXCHARISK(6) => '0',
      TXCHARISK(5) => '0',
      TXCHARISK(4) => '0',
      TXCHARISK(3) => '0',
      TXCHARISK(2) => '0',
      TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0),
      TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63) => '0',
      TXDATA(62) => '0',
      TXDATA(61) => '0',
      TXDATA(60) => '0',
      TXDATA(59) => '0',
      TXDATA(58) => '0',
      TXDATA(57) => '0',
      TXDATA(56) => '0',
      TXDATA(55) => '0',
      TXDATA(54) => '0',
      TXDATA(53) => '0',
      TXDATA(52) => '0',
      TXDATA(51) => '0',
      TXDATA(50) => '0',
      TXDATA(49) => '0',
      TXDATA(48) => '0',
      TXDATA(47) => '0',
      TXDATA(46) => '0',
      TXDATA(45) => '0',
      TXDATA(44) => '0',
      TXDATA(43) => '0',
      TXDATA(42) => '0',
      TXDATA(41) => '0',
      TXDATA(40) => '0',
      TXDATA(39) => '0',
      TXDATA(38) => '0',
      TXDATA(37) => '0',
      TXDATA(36) => '0',
      TXDATA(35) => '0',
      TXDATA(34) => '0',
      TXDATA(33) => '0',
      TXDATA(32) => '0',
      TXDATA(31) => '0',
      TXDATA(30) => '0',
      TXDATA(29) => '0',
      TXDATA(28) => '0',
      TXDATA(27) => '0',
      TXDATA(26) => '0',
      TXDATA(25) => '0',
      TXDATA(24) => '0',
      TXDATA(23) => '0',
      TXDATA(22) => '0',
      TXDATA(21) => '0',
      TXDATA(20) => '0',
      TXDATA(19) => '0',
      TXDATA(18) => '0',
      TXDATA(17) => '0',
      TXDATA(16) => '0',
      TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0),
      TXDEEMPH => PIPE_TXDEEMPH(0),
      TXDETECTRX => PIPE_TXDETECTRX,
      TXDIFFCTRL(3) => '1',
      TXDIFFCTRL(2) => '1',
      TXDIFFCTRL(1) => '0',
      TXDIFFCTRL(0) => '0',
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => \txsync_fsm.txdlyen_reg\,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => \txsync_fsm.fsm_tx_reg[2]\,
      TXDLYSRESETDONE => pipe_txdlysresetdone(0),
      TXDLYUPDOWN => '0',
      TXELECIDLE => PIPE_TXELECIDLE(0),
      TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2) => '0',
      TXHEADER(1) => '0',
      TXHEADER(0) => '0',
      TXINHIBIT => pipe_txinhibit(0),
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => PIPE_TXMARGIN(2 downto 0),
      TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\,
      TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2) => '0',
      TXOUTCLKSEL(1) => '0',
      TXOUTCLKSEL(0) => '0',
      TXPCSRESET => '0',
      TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => \txsync_fsm.fsm_tx_reg[4]\,
      TXPHALIGNDONE => pipe_txphaligndone(0),
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => \txsync_fsm.fsm_tx_reg[4]_0\,
      TXPHINITDONE => pipe_txphinitdone(0),
      TXPHOVRDEN => '0',
      TXPISOPD => '0',
      TXPMARESET => GT_TXPMARESET064_out,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2) => '0',
      TXPRBSSEL(1) => '0',
      TXPRBSSEL(0) => '0',
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\,
      TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => RXRATE(2 downto 0),
      TXRATEDONE => RATE_TXRATEDONE,
      TXRESETDONE => USER_TXRESETDONE,
      TXSEQUENCE(6) => '0',
      TXSEQUENCE(5) => '0',
      TXSEQUENCE(4) => '0',
      TXSEQUENCE(3) => '0',
      TXSEQUENCE(2) => '0',
      TXSEQUENCE(1) => '0',
      TXSEQUENCE(0) => '0',
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      TXUSERRDY => \userrdy_reg_rep__1\,
      TXUSRCLK => pclk_sel_reg,
      TXUSRCLK2 => pclk_sel_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_54 is
  port (
    RATE_CPLLLOCK : out STD_LOGIC;
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_PHYSTATUS : out STD_LOGIC;
    rxcdrlock_reg1_reg : out STD_LOGIC;
    PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_RXRATEDONE : out STD_LOGIC;
    USER_RXRESETDONE : out STD_LOGIC;
    rxvalid_reg1_reg : out STD_LOGIC;
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_TXRATEDONE : out STD_LOGIC;
    USER_TXRESETDONE : out STD_LOGIC;
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    \fsm_reg[2]\ : in STD_LOGIC;
    \fsm_reg[0]\ : in STD_LOGIC;
    USER_EYESCANRESET : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    rst_gtreset : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpllpd_reg : in STD_LOGIC;
    qpllpd_reg_0 : in STD_LOGIC;
    \resetovrd_disble.fsm_reg[1]\ : in STD_LOGIC;
    gen3_reg : in STD_LOGIC;
    USER_RXBUFRESET : in STD_LOGIC;
    USER_RXCDRFREQRESET : in STD_LOGIC;
    USER_RXCDRRESET : in STD_LOGIC;
    gen3_reg_0 : in STD_LOGIC;
    converge_gen3_reg : in STD_LOGIC;
    USER_RXDFELPMRESET : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]\ : in STD_LOGIC;
    USER_RXPCSRESET : in STD_LOGIC;
    rxsync_donem_reg2_reg : in STD_LOGIC;
    GT_RXPMARESET043_out : in STD_LOGIC;
    PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 );
    \userrdy_reg_rep__0\ : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    PIPE_TXDEEMPH : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx_rcvr_det : in STD_LOGIC;
    \txsync_fsm.txdlyen_reg\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[2]\ : in STD_LOGIC;
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    GT_TXPMARESET046_out : in STD_LOGIC;
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_tx_margin_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_OOBCLK : in STD_LOGIC;
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 8 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    gt_rxvalid_q_reg : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in49_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in47_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_54 : entity is "PCIeGen1x8If64_gt_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_54;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_54 is
  signal CPLLPD0 : STD_LOGIC;
  signal CPLLRESET0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC;
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE";
begin
  pipe_rxstatus(2 downto 0) <= \^pipe_rxstatus\(2 downto 0);
cpllPDInst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_75
     port map (
      CPLLPD0 => CPLLPD0,
      CPLLRESET0 => CPLLRESET0,
      RST_CPLLRESET => RST_CPLLRESET,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      p_0_in47_in => p_0_in47_in,
      p_0_in49_in => p_0_in49_in,
      rst_cpllpd => rst_cpllpd
    );
\gt_rx_status_q[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(0),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(0)
    );
\gt_rx_status_q[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(1),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(1)
    );
\gt_rx_status_q[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(2),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(2)
    );
\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL
    generic map(
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"A407CC",
      CPLL_FBDIV => 5,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"0000000001CF",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => X"00018480",
      PMA_RSV2 => X"2050",
      PMA_RSV3 => B"00",
      PMA_RSV4 => X"00000000",
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"03000023FF10200020",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00000011110000",
      RXLPM_LF_CFG => B"00000011110000",
      RXOOB_CFG => B"0000110",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RX_BIAS_CFG => B"000000000100",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFE_GAIN_CFG => X"020FEA",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011110000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_KL_CFG => B"0000011111110",
      RX_DFE_KL_CFG2 => X"3290D86C",
      RX_DFE_LPM_CFG => X"0954",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '1',
      RX_DFE_UT_CFG => B"10001111000000000",
      RX_DFE_VP_CFG => B"00011111100000011",
      RX_DFE_XYD_CFG => B"0000000000000",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 4,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "3.0",
      TERM_RCAL_CFG => B"10000",
      TERM_RCAL_OVRD => '0',
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPMARESET_TIME => B"00011",
      TX_CLK25_DIV => 4,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"10100",
      TX_DEEMPH1 => B"01011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD(3) => '0',
      CLKRSVD(2) => '0',
      CLKRSVD(1) => '0',
      CLKRSVD(0) => USER_OOBCLK,
      CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\,
      CPLLLOCK => RATE_CPLLLOCK,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD0,
      CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\,
      CPLLREFCLKSEL(2) => '0',
      CPLLREFCLKSEL(1) => '0',
      CPLLREFCLKSEL(0) => '1',
      CPLLRESET => CPLLRESET0,
      DMONITOROUT(7 downto 0) => pipe_dmonitorout(7 downto 0),
      DRPADDR(8 downto 0) => DRPADDR(8 downto 0),
      DRPCLK => \resetovrd_disble.reset_reg[4]\,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => ext_ch_gt_drpdo(15 downto 0),
      DRPEN => \fsm_reg[2]\,
      DRPRDY => ext_ch_gt_drprdy(0),
      DRPWE => \fsm_reg[0]\,
      EYESCANDATAERROR => pipe_eyescandataerror(0),
      EYESCANMODE => '0',
      EYESCANRESET => USER_EYESCANRESET,
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\,
      GTRESETSEL => '0',
      GTRSVD(15) => '0',
      GTRSVD(14) => '0',
      GTRSVD(13) => '0',
      GTRSVD(12) => '0',
      GTRSVD(11) => '0',
      GTRSVD(10) => '0',
      GTRSVD(9) => '0',
      GTRSVD(8) => '0',
      GTRSVD(7) => '0',
      GTRSVD(6) => '0',
      GTRSVD(5) => '0',
      GTRSVD(4) => '0',
      GTRSVD(3) => '0',
      GTRSVD(2) => '0',
      GTRSVD(1) => '0',
      GTRSVD(0) => '0',
      GTRXRESET => rst_gtreset,
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => rst_gtreset,
      GTXRXN => pci_exp_rxn(0),
      GTXRXP => pci_exp_rxp(0),
      GTXTXN => pci_exp_txn(0),
      GTXTXP => pci_exp_txp(0),
      LOOPBACK(2) => '0',
      LOOPBACK(1) => '0',
      LOOPBACK(0) => '0',
      PCSRSVDIN(15) => '0',
      PCSRSVDIN(14) => '0',
      PCSRSVDIN(13) => '0',
      PCSRSVDIN(12) => '0',
      PCSRSVDIN(11) => '0',
      PCSRSVDIN(10) => '0',
      PCSRSVDIN(9) => '0',
      PCSRSVDIN(8) => '0',
      PCSRSVDIN(7) => '0',
      PCSRSVDIN(6) => '0',
      PCSRSVDIN(5) => '0',
      PCSRSVDIN(4) => '0',
      PCSRSVDIN(3) => '0',
      PCSRSVDIN(2) => '0',
      PCSRSVDIN(1) => '0',
      PCSRSVDIN(0) => '0',
      PCSRSVDIN2(4) => '0',
      PCSRSVDIN2(3) => '0',
      PCSRSVDIN2(2) => '0',
      PCSRSVDIN2(1) => '0',
      PCSRSVDIN2(0) => '0',
      PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => RATE_PHYSTATUS,
      PMARSVDIN(4) => '0',
      PMARSVDIN(3) => '0',
      PMARSVDIN(2) => '0',
      PMARSVDIN(1) => '0',
      PMARSVDIN(0) => '0',
      PMARSVDIN2(4) => '0',
      PMARSVDIN2(3) => '0',
      PMARSVDIN2(2) => '0',
      PMARSVDIN2(1) => '0',
      PMARSVDIN2(0) => '0',
      QPLLCLK => qpllpd_reg,
      QPLLREFCLK => qpllpd_reg_0,
      RESETOVRD => \resetovrd_disble.fsm_reg[1]\,
      RX8B10BEN => gen3_reg,
      RXBUFRESET => USER_RXBUFRESET,
      RXBUFSTATUS(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\,
      RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\,
      RXCDRFREQRESET => USER_RXCDRFREQRESET,
      RXCDRHOLD => '0',
      RXCDRLOCK => rxcdrlock_reg1_reg,
      RXCDROVRDEN => '0',
      RXCDRRESET => USER_RXCDRRESET,
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0),
      RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4),
      RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\,
      RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\,
      RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\,
      RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\,
      RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4),
      RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\,
      RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\,
      RXCHARISK(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      RXCHBONDEN => gen3_reg,
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2) => '0',
      RXCHBONDLEVEL(1) => '0',
      RXCHBONDLEVEL(0) => '0',
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\,
      RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\,
      RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\,
      RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\,
      RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\,
      RXCHBONDSLAVE => gen3_reg_0,
      RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => pipe_rxcommadet(0),
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32),
      RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\,
      RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\,
      RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\,
      RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\,
      RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\,
      RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\,
      RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\,
      RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\,
      RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\,
      RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\,
      RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\,
      RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\,
      RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\,
      RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\,
      RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\,
      RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\,
      RXDATA(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\,
      RXDDIEN => '0',
      RXDFEAGCHOLD => converge_gen3_reg,
      RXDFEAGCOVRDEN => '0',
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '1',
      RXDFELPMRESET => USER_RXDFELPMRESET,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '0',
      RXDFEXYDHOLD => '0',
      RXDFEXYDOVRDEN => '0',
      RXDISPERR(7 downto 0) => pipe_rxdisperr(7 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => SYNC_RXSYNC_DONE,
      RXDLYOVRDEN => '0',
      RXDLYSRESET => \rxsync_fsm_disable.fsm_rx_reg[2]\,
      RXDLYSRESETDONE => pipe_rxdlysresetdone(0),
      RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      RXELECIDLEMODE(1) => '0',
      RXELECIDLEMODE(0) => '0',
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMEN => gen3_reg_0,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => gen3_reg,
      RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0),
      RXMONITORSEL(1) => '0',
      RXMONITORSEL(0) => '0',
      RXNOTINTABLE(7 downto 0) => pipe_rxnotintable(7 downto 0),
      RXOOBRESET => '0',
      RXOSHOLD => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => pipe_rxoutclk_out(0),
      RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2) => '0',
      RXOUTCLKSEL(1) => '0',
      RXOUTCLKSEL(0) => '0',
      RXPCOMMAALIGNEN => gen3_reg_0,
      RXPCSRESET => USER_RXPCSRESET,
      RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      RXPHALIGN => rxsync_donem_reg2_reg,
      RXPHALIGNDONE => pipe_rxphaligndone(0),
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => GT_RXPMARESET043_out,
      RXPOLARITY => PIPE_RXPOLARITY(0),
      RXPRBSCNTRESET => '0',
      RXPRBSERR => pipe_rxprbserr(0),
      RXPRBSSEL(2) => '0',
      RXPRBSSEL(1) => '0',
      RXPRBSSEL(0) => '0',
      RXQPIEN => '0',
      RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\,
      RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\,
      RXRATE(2 downto 0) => RXRATE(2 downto 0),
      RXRATEDONE => RATE_RXRATEDONE,
      RXRESETDONE => USER_RXRESETDONE,
      RXSLIDE => '0',
      RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\,
      RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      RXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      RXUSERRDY => \userrdy_reg_rep__0\,
      RXUSRCLK => pclk_sel_reg,
      RXUSRCLK2 => pclk_sel_reg,
      RXVALID => rxvalid_reg1_reg,
      SETERRSTATUS => '0',
      TSTIN(19) => '1',
      TSTIN(18) => '1',
      TSTIN(17) => '1',
      TSTIN(16) => '1',
      TSTIN(15) => '1',
      TSTIN(14) => '1',
      TSTIN(13) => '1',
      TSTIN(12) => '1',
      TSTIN(11) => '1',
      TSTIN(10) => '1',
      TSTIN(9) => '1',
      TSTIN(8) => '1',
      TSTIN(7) => '1',
      TSTIN(6) => '1',
      TSTIN(5) => '1',
      TSTIN(4) => '1',
      TSTIN(3) => '1',
      TSTIN(2) => '1',
      TSTIN(1) => '1',
      TSTIN(0) => '1',
      TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0),
      TX8B10BBYPASS(7) => '0',
      TX8B10BBYPASS(6) => '0',
      TX8B10BBYPASS(5) => '0',
      TX8B10BBYPASS(4) => '0',
      TX8B10BBYPASS(3) => '0',
      TX8B10BBYPASS(2) => '0',
      TX8B10BBYPASS(1) => '0',
      TX8B10BBYPASS(0) => '0',
      TX8B10BEN => gen3_reg_0,
      TXBUFDIFFCTRL(2) => '1',
      TXBUFDIFFCTRL(1) => '0',
      TXBUFDIFFCTRL(0) => '0',
      TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(7) => '0',
      TXCHARDISPMODE(6) => '0',
      TXCHARDISPMODE(5) => '0',
      TXCHARDISPMODE(4) => '0',
      TXCHARDISPMODE(3) => '0',
      TXCHARDISPMODE(2) => '0',
      TXCHARDISPMODE(1) => '0',
      TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0),
      TXCHARDISPVAL(7) => '0',
      TXCHARDISPVAL(6) => '0',
      TXCHARDISPVAL(5) => '0',
      TXCHARDISPVAL(4) => '0',
      TXCHARDISPVAL(3) => '0',
      TXCHARDISPVAL(2) => '0',
      TXCHARDISPVAL(1) => '0',
      TXCHARDISPVAL(0) => '0',
      TXCHARISK(7) => '0',
      TXCHARISK(6) => '0',
      TXCHARISK(5) => '0',
      TXCHARISK(4) => '0',
      TXCHARISK(3) => '0',
      TXCHARISK(2) => '0',
      TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0),
      TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63) => '0',
      TXDATA(62) => '0',
      TXDATA(61) => '0',
      TXDATA(60) => '0',
      TXDATA(59) => '0',
      TXDATA(58) => '0',
      TXDATA(57) => '0',
      TXDATA(56) => '0',
      TXDATA(55) => '0',
      TXDATA(54) => '0',
      TXDATA(53) => '0',
      TXDATA(52) => '0',
      TXDATA(51) => '0',
      TXDATA(50) => '0',
      TXDATA(49) => '0',
      TXDATA(48) => '0',
      TXDATA(47) => '0',
      TXDATA(46) => '0',
      TXDATA(45) => '0',
      TXDATA(44) => '0',
      TXDATA(43) => '0',
      TXDATA(42) => '0',
      TXDATA(41) => '0',
      TXDATA(40) => '0',
      TXDATA(39) => '0',
      TXDATA(38) => '0',
      TXDATA(37) => '0',
      TXDATA(36) => '0',
      TXDATA(35) => '0',
      TXDATA(34) => '0',
      TXDATA(33) => '0',
      TXDATA(32) => '0',
      TXDATA(31) => '0',
      TXDATA(30) => '0',
      TXDATA(29) => '0',
      TXDATA(28) => '0',
      TXDATA(27) => '0',
      TXDATA(26) => '0',
      TXDATA(25) => '0',
      TXDATA(24) => '0',
      TXDATA(23) => '0',
      TXDATA(22) => '0',
      TXDATA(21) => '0',
      TXDATA(20) => '0',
      TXDATA(19) => '0',
      TXDATA(18) => '0',
      TXDATA(17) => '0',
      TXDATA(16) => '0',
      TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0),
      TXDEEMPH => PIPE_TXDEEMPH(0),
      TXDETECTRX => pipe_tx_rcvr_det,
      TXDIFFCTRL(3) => '1',
      TXDIFFCTRL(2) => '1',
      TXDIFFCTRL(1) => '0',
      TXDIFFCTRL(0) => '0',
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => \txsync_fsm.txdlyen_reg\,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => \txsync_fsm.fsm_tx_reg[2]\,
      TXDLYSRESETDONE => pipe_txdlysresetdone(0),
      TXDLYUPDOWN => '0',
      TXELECIDLE => PIPE_TXELECIDLE(0),
      TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2) => '0',
      TXHEADER(1) => '0',
      TXHEADER(0) => '0',
      TXINHIBIT => pipe_txinhibit(0),
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0),
      TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\,
      TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2) => '0',
      TXOUTCLKSEL(1) => '0',
      TXOUTCLKSEL(0) => '0',
      TXPCSRESET => '0',
      TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => \txsync_fsm.fsm_tx_reg[4]\,
      TXPHALIGNDONE => pipe_txphaligndone(0),
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => \txsync_fsm.fsm_tx_reg[4]_0\,
      TXPHINITDONE => pipe_txphinitdone(0),
      TXPHOVRDEN => '0',
      TXPISOPD => '0',
      TXPMARESET => GT_TXPMARESET046_out,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2) => '0',
      TXPRBSSEL(1) => '0',
      TXPRBSSEL(0) => '0',
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\,
      TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => RXRATE(2 downto 0),
      TXRATEDONE => RATE_TXRATEDONE,
      TXRESETDONE => USER_TXRESETDONE,
      TXSEQUENCE(6) => '0',
      TXSEQUENCE(5) => '0',
      TXSEQUENCE(4) => '0',
      TXSEQUENCE(3) => '0',
      TXSEQUENCE(2) => '0',
      TXSEQUENCE(1) => '0',
      TXSEQUENCE(0) => '0',
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      TXUSERRDY => \userrdy_reg_rep__0\,
      TXUSRCLK => pclk_sel_reg,
      TXUSRCLK2 => pclk_sel_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_60 is
  port (
    RATE_CPLLLOCK : out STD_LOGIC;
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_PHYSTATUS : out STD_LOGIC;
    rxcdrlock_reg1_reg : out STD_LOGIC;
    PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_RXRATEDONE : out STD_LOGIC;
    USER_RXRESETDONE : out STD_LOGIC;
    rxvalid_reg1_reg : out STD_LOGIC;
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_TXRATEDONE : out STD_LOGIC;
    USER_TXRESETDONE : out STD_LOGIC;
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    SYNC_TXDLYSRESETDONE0 : out STD_LOGIC;
    SYNC_RXDLYSRESETDONE0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    \fsm_reg[2]\ : in STD_LOGIC;
    \fsm_reg[0]\ : in STD_LOGIC;
    USER_EYESCANRESET : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    rst_gtreset : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpllpd_reg : in STD_LOGIC;
    qpllpd_reg_0 : in STD_LOGIC;
    \resetovrd_disble.fsm_reg[1]\ : in STD_LOGIC;
    gen3_reg : in STD_LOGIC;
    USER_RXBUFRESET : in STD_LOGIC;
    USER_RXCDRFREQRESET : in STD_LOGIC;
    USER_RXCDRRESET : in STD_LOGIC;
    gen3_reg_0 : in STD_LOGIC;
    GT_RX_CONVERGE0 : in STD_LOGIC;
    USER_RXDFELPMRESET : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]\ : in STD_LOGIC;
    USER_RXPCSRESET : in STD_LOGIC;
    rxsync_donem_reg2_reg : in STD_LOGIC;
    GT_RXPMARESET032_out : in STD_LOGIC;
    PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 );
    userrdy_reg_rep : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    PIPE_TXDEEMPH : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDETECTRX : in STD_LOGIC;
    \txsync_fsm.txdlyen_reg\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[2]\ : in STD_LOGIC;
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    GT_TXPMARESET035_out : in STD_LOGIC;
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXMARGIN : in STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_OOBCLK : in STD_LOGIC;
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 8 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    gt_rxvalid_q_reg : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in38_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in36_in : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
    \resetovrd_disble.reset_reg[4]_1\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_60 : entity is "PCIeGen1x8If64_gt_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_60;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_60 is
  signal CPLLPD0 : STD_LOGIC;
  signal CPLLRESET0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC;
  signal \^pipe_rxdlysresetdone\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^pipe_txdlysresetdone\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rxdlysresetdone_reg1_i_2_n_0 : STD_LOGIC;
  signal txdlysresetdone_reg1_i_2_n_0 : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE";
begin
  pipe_rxdlysresetdone(0) <= \^pipe_rxdlysresetdone\(0);
  pipe_rxstatus(2 downto 0) <= \^pipe_rxstatus\(2 downto 0);
  pipe_txdlysresetdone(0) <= \^pipe_txdlysresetdone\(0);
cpllPDInst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_73
     port map (
      CPLLPD0 => CPLLPD0,
      CPLLRESET0 => CPLLRESET0,
      RST_CPLLRESET => RST_CPLLRESET,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      p_0_in36_in => p_0_in36_in,
      p_0_in38_in => p_0_in38_in,
      rst_cpllpd => rst_cpllpd
    );
\gt_rx_status_q[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(0),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(0)
    );
\gt_rx_status_q[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(1),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(1)
    );
\gt_rx_status_q[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(2),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(2)
    );
\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL
    generic map(
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"A407CC",
      CPLL_FBDIV => 5,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"0000000001CF",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => X"00018480",
      PMA_RSV2 => X"2050",
      PMA_RSV3 => B"00",
      PMA_RSV4 => X"00000000",
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"03000023FF10200020",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00000011110000",
      RXLPM_LF_CFG => B"00000011110000",
      RXOOB_CFG => B"0000110",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RX_BIAS_CFG => B"000000000100",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFE_GAIN_CFG => X"020FEA",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011110000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_KL_CFG => B"0000011111110",
      RX_DFE_KL_CFG2 => X"3290D86C",
      RX_DFE_LPM_CFG => X"0954",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '1',
      RX_DFE_UT_CFG => B"10001111000000000",
      RX_DFE_VP_CFG => B"00011111100000011",
      RX_DFE_XYD_CFG => B"0000000000000",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 4,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "3.0",
      TERM_RCAL_CFG => B"10000",
      TERM_RCAL_OVRD => '0',
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPMARESET_TIME => B"00011",
      TX_CLK25_DIV => 4,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"10100",
      TX_DEEMPH1 => B"01011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD(3) => '0',
      CLKRSVD(2) => '0',
      CLKRSVD(1) => '0',
      CLKRSVD(0) => USER_OOBCLK,
      CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\,
      CPLLLOCK => RATE_CPLLLOCK,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD0,
      CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\,
      CPLLREFCLKSEL(2) => '0',
      CPLLREFCLKSEL(1) => '0',
      CPLLREFCLKSEL(0) => '1',
      CPLLRESET => CPLLRESET0,
      DMONITOROUT(7 downto 0) => pipe_dmonitorout(7 downto 0),
      DRPADDR(8 downto 0) => DRPADDR(8 downto 0),
      DRPCLK => \resetovrd_disble.reset_reg[4]\,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => ext_ch_gt_drpdo(15 downto 0),
      DRPEN => \fsm_reg[2]\,
      DRPRDY => ext_ch_gt_drprdy(0),
      DRPWE => \fsm_reg[0]\,
      EYESCANDATAERROR => pipe_eyescandataerror(0),
      EYESCANMODE => '0',
      EYESCANRESET => USER_EYESCANRESET,
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\,
      GTRESETSEL => '0',
      GTRSVD(15) => '0',
      GTRSVD(14) => '0',
      GTRSVD(13) => '0',
      GTRSVD(12) => '0',
      GTRSVD(11) => '0',
      GTRSVD(10) => '0',
      GTRSVD(9) => '0',
      GTRSVD(8) => '0',
      GTRSVD(7) => '0',
      GTRSVD(6) => '0',
      GTRSVD(5) => '0',
      GTRSVD(4) => '0',
      GTRSVD(3) => '0',
      GTRSVD(2) => '0',
      GTRSVD(1) => '0',
      GTRSVD(0) => '0',
      GTRXRESET => rst_gtreset,
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => rst_gtreset,
      GTXRXN => pci_exp_rxn(0),
      GTXRXP => pci_exp_rxp(0),
      GTXTXN => pci_exp_txn(0),
      GTXTXP => pci_exp_txp(0),
      LOOPBACK(2) => '0',
      LOOPBACK(1) => '0',
      LOOPBACK(0) => '0',
      PCSRSVDIN(15) => '0',
      PCSRSVDIN(14) => '0',
      PCSRSVDIN(13) => '0',
      PCSRSVDIN(12) => '0',
      PCSRSVDIN(11) => '0',
      PCSRSVDIN(10) => '0',
      PCSRSVDIN(9) => '0',
      PCSRSVDIN(8) => '0',
      PCSRSVDIN(7) => '0',
      PCSRSVDIN(6) => '0',
      PCSRSVDIN(5) => '0',
      PCSRSVDIN(4) => '0',
      PCSRSVDIN(3) => '0',
      PCSRSVDIN(2) => '0',
      PCSRSVDIN(1) => '0',
      PCSRSVDIN(0) => '0',
      PCSRSVDIN2(4) => '0',
      PCSRSVDIN2(3) => '0',
      PCSRSVDIN2(2) => '0',
      PCSRSVDIN2(1) => '0',
      PCSRSVDIN2(0) => '0',
      PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => RATE_PHYSTATUS,
      PMARSVDIN(4) => '0',
      PMARSVDIN(3) => '0',
      PMARSVDIN(2) => '0',
      PMARSVDIN(1) => '0',
      PMARSVDIN(0) => '0',
      PMARSVDIN2(4) => '0',
      PMARSVDIN2(3) => '0',
      PMARSVDIN2(2) => '0',
      PMARSVDIN2(1) => '0',
      PMARSVDIN2(0) => '0',
      QPLLCLK => qpllpd_reg,
      QPLLREFCLK => qpllpd_reg_0,
      RESETOVRD => \resetovrd_disble.fsm_reg[1]\,
      RX8B10BEN => gen3_reg,
      RXBUFRESET => USER_RXBUFRESET,
      RXBUFSTATUS(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\,
      RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\,
      RXCDRFREQRESET => USER_RXCDRFREQRESET,
      RXCDRHOLD => '0',
      RXCDRLOCK => rxcdrlock_reg1_reg,
      RXCDROVRDEN => '0',
      RXCDRRESET => USER_RXCDRRESET,
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0),
      RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4),
      RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\,
      RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\,
      RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\,
      RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\,
      RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4),
      RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\,
      RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\,
      RXCHARISK(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      RXCHBONDEN => gen3_reg,
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2) => '0',
      RXCHBONDLEVEL(1) => '0',
      RXCHBONDLEVEL(0) => '0',
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\,
      RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\,
      RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\,
      RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\,
      RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\,
      RXCHBONDSLAVE => gen3_reg_0,
      RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => pipe_rxcommadet(0),
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32),
      RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\,
      RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\,
      RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\,
      RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\,
      RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\,
      RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\,
      RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\,
      RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\,
      RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\,
      RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\,
      RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\,
      RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\,
      RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\,
      RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\,
      RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\,
      RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\,
      RXDATA(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\,
      RXDDIEN => '0',
      RXDFEAGCHOLD => GT_RX_CONVERGE0,
      RXDFEAGCOVRDEN => '0',
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '1',
      RXDFELPMRESET => USER_RXDFELPMRESET,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '0',
      RXDFEXYDHOLD => '0',
      RXDFEXYDOVRDEN => '0',
      RXDISPERR(7 downto 0) => pipe_rxdisperr(7 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => SYNC_RXSYNC_DONE,
      RXDLYOVRDEN => '0',
      RXDLYSRESET => \rxsync_fsm_disable.fsm_rx_reg[2]\,
      RXDLYSRESETDONE => \^pipe_rxdlysresetdone\(0),
      RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      RXELECIDLEMODE(1) => '0',
      RXELECIDLEMODE(0) => '0',
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMEN => gen3_reg_0,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => gen3_reg,
      RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0),
      RXMONITORSEL(1) => '0',
      RXMONITORSEL(0) => '0',
      RXNOTINTABLE(7 downto 0) => pipe_rxnotintable(7 downto 0),
      RXOOBRESET => '0',
      RXOSHOLD => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => pipe_rxoutclk_out(0),
      RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2) => '0',
      RXOUTCLKSEL(1) => '0',
      RXOUTCLKSEL(0) => '0',
      RXPCOMMAALIGNEN => gen3_reg_0,
      RXPCSRESET => USER_RXPCSRESET,
      RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      RXPHALIGN => rxsync_donem_reg2_reg,
      RXPHALIGNDONE => pipe_rxphaligndone(0),
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => GT_RXPMARESET032_out,
      RXPOLARITY => PIPE_RXPOLARITY(0),
      RXPRBSCNTRESET => '0',
      RXPRBSERR => pipe_rxprbserr(0),
      RXPRBSSEL(2) => '0',
      RXPRBSSEL(1) => '0',
      RXPRBSSEL(0) => '0',
      RXQPIEN => '0',
      RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\,
      RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\,
      RXRATE(2 downto 0) => RXRATE(2 downto 0),
      RXRATEDONE => RATE_RXRATEDONE,
      RXRESETDONE => USER_RXRESETDONE,
      RXSLIDE => '0',
      RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\,
      RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      RXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      RXUSERRDY => userrdy_reg_rep,
      RXUSRCLK => pclk_sel_reg,
      RXUSRCLK2 => pclk_sel_reg,
      RXVALID => rxvalid_reg1_reg,
      SETERRSTATUS => '0',
      TSTIN(19) => '1',
      TSTIN(18) => '1',
      TSTIN(17) => '1',
      TSTIN(16) => '1',
      TSTIN(15) => '1',
      TSTIN(14) => '1',
      TSTIN(13) => '1',
      TSTIN(12) => '1',
      TSTIN(11) => '1',
      TSTIN(10) => '1',
      TSTIN(9) => '1',
      TSTIN(8) => '1',
      TSTIN(7) => '1',
      TSTIN(6) => '1',
      TSTIN(5) => '1',
      TSTIN(4) => '1',
      TSTIN(3) => '1',
      TSTIN(2) => '1',
      TSTIN(1) => '1',
      TSTIN(0) => '1',
      TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0),
      TX8B10BBYPASS(7) => '0',
      TX8B10BBYPASS(6) => '0',
      TX8B10BBYPASS(5) => '0',
      TX8B10BBYPASS(4) => '0',
      TX8B10BBYPASS(3) => '0',
      TX8B10BBYPASS(2) => '0',
      TX8B10BBYPASS(1) => '0',
      TX8B10BBYPASS(0) => '0',
      TX8B10BEN => gen3_reg_0,
      TXBUFDIFFCTRL(2) => '1',
      TXBUFDIFFCTRL(1) => '0',
      TXBUFDIFFCTRL(0) => '0',
      TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(7) => '0',
      TXCHARDISPMODE(6) => '0',
      TXCHARDISPMODE(5) => '0',
      TXCHARDISPMODE(4) => '0',
      TXCHARDISPMODE(3) => '0',
      TXCHARDISPMODE(2) => '0',
      TXCHARDISPMODE(1) => '0',
      TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0),
      TXCHARDISPVAL(7) => '0',
      TXCHARDISPVAL(6) => '0',
      TXCHARDISPVAL(5) => '0',
      TXCHARDISPVAL(4) => '0',
      TXCHARDISPVAL(3) => '0',
      TXCHARDISPVAL(2) => '0',
      TXCHARDISPVAL(1) => '0',
      TXCHARDISPVAL(0) => '0',
      TXCHARISK(7) => '0',
      TXCHARISK(6) => '0',
      TXCHARISK(5) => '0',
      TXCHARISK(4) => '0',
      TXCHARISK(3) => '0',
      TXCHARISK(2) => '0',
      TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0),
      TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63) => '0',
      TXDATA(62) => '0',
      TXDATA(61) => '0',
      TXDATA(60) => '0',
      TXDATA(59) => '0',
      TXDATA(58) => '0',
      TXDATA(57) => '0',
      TXDATA(56) => '0',
      TXDATA(55) => '0',
      TXDATA(54) => '0',
      TXDATA(53) => '0',
      TXDATA(52) => '0',
      TXDATA(51) => '0',
      TXDATA(50) => '0',
      TXDATA(49) => '0',
      TXDATA(48) => '0',
      TXDATA(47) => '0',
      TXDATA(46) => '0',
      TXDATA(45) => '0',
      TXDATA(44) => '0',
      TXDATA(43) => '0',
      TXDATA(42) => '0',
      TXDATA(41) => '0',
      TXDATA(40) => '0',
      TXDATA(39) => '0',
      TXDATA(38) => '0',
      TXDATA(37) => '0',
      TXDATA(36) => '0',
      TXDATA(35) => '0',
      TXDATA(34) => '0',
      TXDATA(33) => '0',
      TXDATA(32) => '0',
      TXDATA(31) => '0',
      TXDATA(30) => '0',
      TXDATA(29) => '0',
      TXDATA(28) => '0',
      TXDATA(27) => '0',
      TXDATA(26) => '0',
      TXDATA(25) => '0',
      TXDATA(24) => '0',
      TXDATA(23) => '0',
      TXDATA(22) => '0',
      TXDATA(21) => '0',
      TXDATA(20) => '0',
      TXDATA(19) => '0',
      TXDATA(18) => '0',
      TXDATA(17) => '0',
      TXDATA(16) => '0',
      TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0),
      TXDEEMPH => PIPE_TXDEEMPH(0),
      TXDETECTRX => PIPE_TXDETECTRX,
      TXDIFFCTRL(3) => '1',
      TXDIFFCTRL(2) => '1',
      TXDIFFCTRL(1) => '0',
      TXDIFFCTRL(0) => '0',
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => \txsync_fsm.txdlyen_reg\,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => \txsync_fsm.fsm_tx_reg[2]\,
      TXDLYSRESETDONE => \^pipe_txdlysresetdone\(0),
      TXDLYUPDOWN => '0',
      TXELECIDLE => PIPE_TXELECIDLE(0),
      TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2) => '0',
      TXHEADER(1) => '0',
      TXHEADER(0) => '0',
      TXINHIBIT => pipe_txinhibit(0),
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => PIPE_TXMARGIN(2 downto 0),
      TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\,
      TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2) => '0',
      TXOUTCLKSEL(1) => '0',
      TXOUTCLKSEL(0) => '0',
      TXPCSRESET => '0',
      TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => \txsync_fsm.fsm_tx_reg[4]\,
      TXPHALIGNDONE => pipe_txphaligndone(0),
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => \txsync_fsm.fsm_tx_reg[4]_0\,
      TXPHINITDONE => pipe_txphinitdone(0),
      TXPHOVRDEN => '0',
      TXPISOPD => '0',
      TXPMARESET => GT_TXPMARESET035_out,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2) => '0',
      TXPRBSSEL(1) => '0',
      TXPRBSSEL(0) => '0',
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\,
      TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => RXRATE(2 downto 0),
      TXRATEDONE => RATE_TXRATEDONE,
      TXRESETDONE => USER_TXRESETDONE,
      TXSEQUENCE(6) => '0',
      TXSEQUENCE(5) => '0',
      TXSEQUENCE(4) => '0',
      TXSEQUENCE(3) => '0',
      TXSEQUENCE(2) => '0',
      TXSEQUENCE(1) => '0',
      TXSEQUENCE(0) => '0',
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      TXUSERRDY => userrdy_reg_rep,
      TXUSRCLK => pclk_sel_reg,
      TXUSRCLK2 => pclk_sel_reg
    );
rxdlysresetdone_reg1_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => rxdlysresetdone_reg1_i_2_n_0,
      I1 => \resetovrd_disble.reset_reg[4]_1\(4),
      I2 => \resetovrd_disble.reset_reg[4]_1\(5),
      O => SYNC_RXDLYSRESETDONE0
    );
rxdlysresetdone_reg1_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^pipe_rxdlysresetdone\(0),
      I1 => \resetovrd_disble.reset_reg[4]_1\(6),
      I2 => \resetovrd_disble.reset_reg[4]_1\(1),
      I3 => \resetovrd_disble.reset_reg[4]_1\(0),
      I4 => \resetovrd_disble.reset_reg[4]_1\(3),
      I5 => \resetovrd_disble.reset_reg[4]_1\(2),
      O => rxdlysresetdone_reg1_i_2_n_0
    );
txdlysresetdone_reg1_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => txdlysresetdone_reg1_i_2_n_0,
      I1 => \resetovrd_disble.reset_reg[4]_0\(4),
      I2 => \resetovrd_disble.reset_reg[4]_0\(5),
      O => SYNC_TXDLYSRESETDONE0
    );
txdlysresetdone_reg1_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \^pipe_txdlysresetdone\(0),
      I1 => \resetovrd_disble.reset_reg[4]_0\(6),
      I2 => \resetovrd_disble.reset_reg[4]_0\(1),
      I3 => \resetovrd_disble.reset_reg[4]_0\(0),
      I4 => \resetovrd_disble.reset_reg[4]_0\(3),
      I5 => \resetovrd_disble.reset_reg[4]_0\(2),
      O => txdlysresetdone_reg1_i_2_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_66 is
  port (
    RATE_CPLLLOCK : out STD_LOGIC;
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_PHYSTATUS : out STD_LOGIC;
    rxcdrlock_reg1_reg : out STD_LOGIC;
    PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_RXRATEDONE : out STD_LOGIC;
    USER_RXRESETDONE : out STD_LOGIC;
    rxvalid_reg1_reg : out STD_LOGIC;
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    RATE_TXRATEDONE : out STD_LOGIC;
    USER_TXRESETDONE : out STD_LOGIC;
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    \resetovrd_disble.reset_reg[4]\ : in STD_LOGIC;
    \fsm_reg[2]\ : in STD_LOGIC;
    \fsm_reg[0]\ : in STD_LOGIC;
    USER_EYESCANRESET : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    rst_gtreset : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpllpd_reg : in STD_LOGIC;
    qpllpd_reg_0 : in STD_LOGIC;
    \resetovrd_disble.fsm_reg[1]\ : in STD_LOGIC;
    gen3_reg : in STD_LOGIC;
    USER_RXBUFRESET : in STD_LOGIC;
    USER_RXCDRFREQRESET : in STD_LOGIC;
    USER_RXCDRRESET : in STD_LOGIC;
    gen3_reg_0 : in STD_LOGIC;
    converge_gen3_reg : in STD_LOGIC;
    USER_RXDFELPMRESET : in STD_LOGIC;
    SYNC_RXSYNC_DONE : in STD_LOGIC;
    \rxsync_fsm_disable.fsm_rx_reg[2]\ : in STD_LOGIC;
    USER_RXPCSRESET : in STD_LOGIC;
    rxsync_donem_reg2_reg : in STD_LOGIC;
    GT_RXPMARESET014_out : in STD_LOGIC;
    PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_userrdy : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    PIPE_TXDEEMPH : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx_rcvr_det : in STD_LOGIC;
    \txsync_fsm.txdlyen_reg\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[2]\ : in STD_LOGIC;
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 0 to 0 );
    \txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    \txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    GT_TXPMARESET017_out : in STD_LOGIC;
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_tx_margin_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    USER_OOBCLK : in STD_LOGIC;
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    PIPE_TXDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 8 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    gt_rxvalid_q_reg : in STD_LOGIC;
    rst_cpllpd : in STD_LOGIC;
    p_0_in20_in : in STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    p_0_in18_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_66 : entity is "PCIeGen1x8If64_gt_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_66;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_66 is
  signal CPLLPD0 : STD_LOGIC;
  signal CPLLRESET0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC;
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE";
begin
  pipe_rxstatus(2 downto 0) <= \^pipe_rxstatus\(2 downto 0);
cpllPDInst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd
     port map (
      CPLLPD0 => CPLLPD0,
      CPLLRESET0 => CPLLRESET0,
      RST_CPLLRESET => RST_CPLLRESET,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      p_0_in18_in => p_0_in18_in,
      p_0_in20_in => p_0_in20_in,
      rst_cpllpd => rst_cpllpd
    );
\gt_rx_status_q[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(0),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(0)
    );
\gt_rx_status_q[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(1),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(1)
    );
\gt_rx_status_q[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA8"
    )
        port map (
      I0 => \^pipe_rxstatus\(2),
      I1 => Q(1),
      I2 => Q(0),
      I3 => \pl_ltssm_state_q_reg[4]\,
      I4 => gt_rxvalid_q_reg,
      O => \gt_rx_status_q_reg[2]\(2)
    );
\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL
    generic map(
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"A407CC",
      CPLL_FBDIV => 5,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"0000000001CF",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => X"00018480",
      PMA_RSV2 => X"2050",
      PMA_RSV3 => B"00",
      PMA_RSV4 => X"00000000",
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"03000023FF10200020",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00000011110000",
      RXLPM_LF_CFG => B"00000011110000",
      RXOOB_CFG => B"0000110",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RX_BIAS_CFG => B"000000000100",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFE_GAIN_CFG => X"020FEA",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011110000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_KL_CFG => B"0000011111110",
      RX_DFE_KL_CFG2 => X"3290D86C",
      RX_DFE_LPM_CFG => X"0954",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '1',
      RX_DFE_UT_CFG => B"10001111000000000",
      RX_DFE_VP_CFG => B"00011111100000011",
      RX_DFE_XYD_CFG => B"0000000000000",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 4,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "3.0",
      TERM_RCAL_CFG => B"10000",
      TERM_RCAL_OVRD => '0',
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPMARESET_TIME => B"00011",
      TX_CLK25_DIV => 4,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"10100",
      TX_DEEMPH1 => B"01011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD(3) => '0',
      CLKRSVD(2) => '0',
      CLKRSVD(1) => '0',
      CLKRSVD(0) => USER_OOBCLK,
      CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\,
      CPLLLOCK => RATE_CPLLLOCK,
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD0,
      CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\,
      CPLLREFCLKSEL(2) => '0',
      CPLLREFCLKSEL(1) => '0',
      CPLLREFCLKSEL(0) => '1',
      CPLLRESET => CPLLRESET0,
      DMONITOROUT(7 downto 0) => pipe_dmonitorout(7 downto 0),
      DRPADDR(8 downto 0) => DRPADDR(8 downto 0),
      DRPCLK => \resetovrd_disble.reset_reg[4]\,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => ext_ch_gt_drpdo(15 downto 0),
      DRPEN => \fsm_reg[2]\,
      DRPRDY => ext_ch_gt_drprdy(0),
      DRPWE => \fsm_reg[0]\,
      EYESCANDATAERROR => pipe_eyescandataerror(0),
      EYESCANMODE => '0',
      EYESCANRESET => USER_EYESCANRESET,
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\,
      GTRESETSEL => '0',
      GTRSVD(15) => '0',
      GTRSVD(14) => '0',
      GTRSVD(13) => '0',
      GTRSVD(12) => '0',
      GTRSVD(11) => '0',
      GTRSVD(10) => '0',
      GTRSVD(9) => '0',
      GTRSVD(8) => '0',
      GTRSVD(7) => '0',
      GTRSVD(6) => '0',
      GTRSVD(5) => '0',
      GTRSVD(4) => '0',
      GTRSVD(3) => '0',
      GTRSVD(2) => '0',
      GTRSVD(1) => '0',
      GTRSVD(0) => '0',
      GTRXRESET => rst_gtreset,
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => rst_gtreset,
      GTXRXN => pci_exp_rxn(0),
      GTXRXP => pci_exp_rxp(0),
      GTXTXN => pci_exp_txn(0),
      GTXTXP => pci_exp_txp(0),
      LOOPBACK(2) => '0',
      LOOPBACK(1) => '0',
      LOOPBACK(0) => '0',
      PCSRSVDIN(15) => '0',
      PCSRSVDIN(14) => '0',
      PCSRSVDIN(13) => '0',
      PCSRSVDIN(12) => '0',
      PCSRSVDIN(11) => '0',
      PCSRSVDIN(10) => '0',
      PCSRSVDIN(9) => '0',
      PCSRSVDIN(8) => '0',
      PCSRSVDIN(7) => '0',
      PCSRSVDIN(6) => '0',
      PCSRSVDIN(5) => '0',
      PCSRSVDIN(4) => '0',
      PCSRSVDIN(3) => '0',
      PCSRSVDIN(2) => '0',
      PCSRSVDIN(1) => '0',
      PCSRSVDIN(0) => '0',
      PCSRSVDIN2(4) => '0',
      PCSRSVDIN2(3) => '0',
      PCSRSVDIN2(2) => '0',
      PCSRSVDIN2(1) => '0',
      PCSRSVDIN2(0) => '0',
      PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => RATE_PHYSTATUS,
      PMARSVDIN(4) => '0',
      PMARSVDIN(3) => '0',
      PMARSVDIN(2) => '0',
      PMARSVDIN(1) => '0',
      PMARSVDIN(0) => '0',
      PMARSVDIN2(4) => '0',
      PMARSVDIN2(3) => '0',
      PMARSVDIN2(2) => '0',
      PMARSVDIN2(1) => '0',
      PMARSVDIN2(0) => '0',
      QPLLCLK => qpllpd_reg,
      QPLLREFCLK => qpllpd_reg_0,
      RESETOVRD => \resetovrd_disble.fsm_reg[1]\,
      RX8B10BEN => gen3_reg,
      RXBUFRESET => USER_RXBUFRESET,
      RXBUFSTATUS(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\,
      RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\,
      RXCDRFREQRESET => USER_RXCDRFREQRESET,
      RXCDRHOLD => '0',
      RXCDRLOCK => rxcdrlock_reg1_reg,
      RXCDROVRDEN => '0',
      RXCDRRESET => USER_RXCDRRESET,
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => PIPE_RXCHANISALIGNED(0),
      RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4),
      RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\,
      RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\,
      RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\,
      RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\,
      RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4),
      RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\,
      RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\,
      RXCHARISK(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      RXCHBONDEN => gen3_reg,
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2) => '0',
      RXCHBONDLEVEL(1) => '0',
      RXCHBONDLEVEL(0) => '0',
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\,
      RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\,
      RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\,
      RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\,
      RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\,
      RXCHBONDSLAVE => gen3_reg_0,
      RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => pipe_rxcommadet(0),
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32),
      RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\,
      RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\,
      RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\,
      RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\,
      RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\,
      RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\,
      RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\,
      RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\,
      RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\,
      RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\,
      RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\,
      RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\,
      RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\,
      RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\,
      RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\,
      RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\,
      RXDATA(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\,
      RXDDIEN => '0',
      RXDFEAGCHOLD => converge_gen3_reg,
      RXDFEAGCOVRDEN => '0',
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '1',
      RXDFELPMRESET => USER_RXDFELPMRESET,
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '0',
      RXDFEXYDHOLD => '0',
      RXDFEXYDOVRDEN => '0',
      RXDISPERR(7 downto 0) => pipe_rxdisperr(7 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => SYNC_RXSYNC_DONE,
      RXDLYOVRDEN => '0',
      RXDLYSRESET => \rxsync_fsm_disable.fsm_rx_reg[2]\,
      RXDLYSRESETDONE => pipe_rxdlysresetdone(0),
      RXELECIDLE => gt_rx_elec_idle_wire_filter(0),
      RXELECIDLEMODE(1) => '0',
      RXELECIDLEMODE(0) => '0',
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMEN => gen3_reg_0,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => gen3_reg,
      RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0),
      RXMONITORSEL(1) => '0',
      RXMONITORSEL(0) => '0',
      RXNOTINTABLE(7 downto 0) => pipe_rxnotintable(7 downto 0),
      RXOOBRESET => '0',
      RXOSHOLD => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => pipe_rxoutclk_out(0),
      RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2) => '0',
      RXOUTCLKSEL(1) => '0',
      RXOUTCLKSEL(0) => '0',
      RXPCOMMAALIGNEN => gen3_reg_0,
      RXPCSRESET => USER_RXPCSRESET,
      RXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      RXPHALIGN => rxsync_donem_reg2_reg,
      RXPHALIGNDONE => pipe_rxphaligndone(0),
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => GT_RXPMARESET014_out,
      RXPOLARITY => PIPE_RXPOLARITY(0),
      RXPRBSCNTRESET => '0',
      RXPRBSERR => pipe_rxprbserr(0),
      RXPRBSSEL(2) => '0',
      RXPRBSSEL(1) => '0',
      RXPRBSSEL(0) => '0',
      RXQPIEN => '0',
      RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\,
      RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\,
      RXRATE(2 downto 0) => RXRATE(2 downto 0),
      RXRATEDONE => RATE_RXRATEDONE,
      RXRESETDONE => USER_RXRESETDONE,
      RXSLIDE => '0',
      RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\,
      RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      RXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      RXUSERRDY => rst_userrdy,
      RXUSRCLK => pclk_sel_reg,
      RXUSRCLK2 => pclk_sel_reg,
      RXVALID => rxvalid_reg1_reg,
      SETERRSTATUS => '0',
      TSTIN(19) => '1',
      TSTIN(18) => '1',
      TSTIN(17) => '1',
      TSTIN(16) => '1',
      TSTIN(15) => '1',
      TSTIN(14) => '1',
      TSTIN(13) => '1',
      TSTIN(12) => '1',
      TSTIN(11) => '1',
      TSTIN(10) => '1',
      TSTIN(9) => '1',
      TSTIN(8) => '1',
      TSTIN(7) => '1',
      TSTIN(6) => '1',
      TSTIN(5) => '1',
      TSTIN(4) => '1',
      TSTIN(3) => '1',
      TSTIN(2) => '1',
      TSTIN(1) => '1',
      TSTIN(0) => '1',
      TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0),
      TX8B10BBYPASS(7) => '0',
      TX8B10BBYPASS(6) => '0',
      TX8B10BBYPASS(5) => '0',
      TX8B10BBYPASS(4) => '0',
      TX8B10BBYPASS(3) => '0',
      TX8B10BBYPASS(2) => '0',
      TX8B10BBYPASS(1) => '0',
      TX8B10BBYPASS(0) => '0',
      TX8B10BEN => gen3_reg_0,
      TXBUFDIFFCTRL(2) => '1',
      TXBUFDIFFCTRL(1) => '0',
      TXBUFDIFFCTRL(0) => '0',
      TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(7) => '0',
      TXCHARDISPMODE(6) => '0',
      TXCHARDISPMODE(5) => '0',
      TXCHARDISPMODE(4) => '0',
      TXCHARDISPMODE(3) => '0',
      TXCHARDISPMODE(2) => '0',
      TXCHARDISPMODE(1) => '0',
      TXCHARDISPMODE(0) => PIPE_TXCOMPLIANCE(0),
      TXCHARDISPVAL(7) => '0',
      TXCHARDISPVAL(6) => '0',
      TXCHARDISPVAL(5) => '0',
      TXCHARDISPVAL(4) => '0',
      TXCHARDISPVAL(3) => '0',
      TXCHARDISPVAL(2) => '0',
      TXCHARDISPVAL(1) => '0',
      TXCHARDISPVAL(0) => '0',
      TXCHARISK(7) => '0',
      TXCHARISK(6) => '0',
      TXCHARISK(5) => '0',
      TXCHARISK(4) => '0',
      TXCHARISK(3) => '0',
      TXCHARISK(2) => '0',
      TXCHARISK(1 downto 0) => PIPE_TXDATAK(1 downto 0),
      TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63) => '0',
      TXDATA(62) => '0',
      TXDATA(61) => '0',
      TXDATA(60) => '0',
      TXDATA(59) => '0',
      TXDATA(58) => '0',
      TXDATA(57) => '0',
      TXDATA(56) => '0',
      TXDATA(55) => '0',
      TXDATA(54) => '0',
      TXDATA(53) => '0',
      TXDATA(52) => '0',
      TXDATA(51) => '0',
      TXDATA(50) => '0',
      TXDATA(49) => '0',
      TXDATA(48) => '0',
      TXDATA(47) => '0',
      TXDATA(46) => '0',
      TXDATA(45) => '0',
      TXDATA(44) => '0',
      TXDATA(43) => '0',
      TXDATA(42) => '0',
      TXDATA(41) => '0',
      TXDATA(40) => '0',
      TXDATA(39) => '0',
      TXDATA(38) => '0',
      TXDATA(37) => '0',
      TXDATA(36) => '0',
      TXDATA(35) => '0',
      TXDATA(34) => '0',
      TXDATA(33) => '0',
      TXDATA(32) => '0',
      TXDATA(31) => '0',
      TXDATA(30) => '0',
      TXDATA(29) => '0',
      TXDATA(28) => '0',
      TXDATA(27) => '0',
      TXDATA(26) => '0',
      TXDATA(25) => '0',
      TXDATA(24) => '0',
      TXDATA(23) => '0',
      TXDATA(22) => '0',
      TXDATA(21) => '0',
      TXDATA(20) => '0',
      TXDATA(19) => '0',
      TXDATA(18) => '0',
      TXDATA(17) => '0',
      TXDATA(16) => '0',
      TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0),
      TXDEEMPH => PIPE_TXDEEMPH(0),
      TXDETECTRX => pipe_tx_rcvr_det,
      TXDIFFCTRL(3) => '1',
      TXDIFFCTRL(2) => '1',
      TXDIFFCTRL(1) => '0',
      TXDIFFCTRL(0) => '0',
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => \txsync_fsm.txdlyen_reg\,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => \txsync_fsm.fsm_tx_reg[2]\,
      TXDLYSRESETDONE => pipe_txdlysresetdone(0),
      TXDLYUPDOWN => '0',
      TXELECIDLE => PIPE_TXELECIDLE(0),
      TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2) => '0',
      TXHEADER(1) => '0',
      TXHEADER(0) => '0',
      TXINHIBIT => pipe_txinhibit(0),
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0),
      TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\,
      TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2) => '0',
      TXOUTCLKSEL(1) => '0',
      TXOUTCLKSEL(0) => '0',
      TXPCSRESET => '0',
      TXPD(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => \txsync_fsm.fsm_tx_reg[4]\,
      TXPHALIGNDONE => pipe_txphaligndone(0),
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => \txsync_fsm.fsm_tx_reg[4]_0\,
      TXPHINITDONE => pipe_txphinitdone(0),
      TXPHOVRDEN => '0',
      TXPISOPD => '0',
      TXPMARESET => GT_TXPMARESET017_out,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2) => '0',
      TXPRBSSEL(1) => '0',
      TXPRBSSEL(0) => '0',
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\,
      TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 0) => RXRATE(2 downto 0),
      TXRATEDONE => RATE_TXRATEDONE,
      TXRESETDONE => USER_TXRESETDONE,
      TXSEQUENCE(6) => '0',
      TXSEQUENCE(5) => '0',
      TXSEQUENCE(4) => '0',
      TXSEQUENCE(3) => '0',
      TXSEQUENCE(2) => '0',
      TXSEQUENCE(1) => '0',
      TXSEQUENCE(0) => '0',
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYSCLKSEL(1 downto 0) => RXSYSCLKSEL(1 downto 0),
      TXUSERRDY => rst_userrdy,
      TXUSRCLK => pclk_sel_reg,
      TXUSRCLK2 => pclk_sel_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_tx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x : entity is "PCIeGen1x8If64_pcie_bram_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x is
begin
\use_tdp.ramb36\: entity work.PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_13
     port map (
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      user_clk => user_clk,
      wdata(17 downto 0) => wdata(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_10 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 14 downto 0 );
    mim_tx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 14 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_10 : entity is "PCIeGen1x8If64_pcie_bram_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_10;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_10 is
begin
\use_tdp.ramb36\: entity work.PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO
     port map (
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(14 downto 0) => rdata(14 downto 0),
      user_clk => user_clk,
      wdata(14 downto 0) => wdata(14 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_14 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_14 : entity is "PCIeGen1x8If64_pcie_bram_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_14;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_14 is
begin
\use_tdp.ramb36\: entity work.PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_21
     port map (
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0),
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_15 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_15 : entity is "PCIeGen1x8If64_pcie_bram_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_15;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_15 is
begin
\use_tdp.ramb36\: entity work.PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_20
     port map (
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0),
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_16 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_16 : entity is "PCIeGen1x8If64_pcie_bram_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_16;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_16 is
begin
\use_tdp.ramb36\: entity work.PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_19
     port map (
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0),
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_17 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_17 : entity is "PCIeGen1x8If64_pcie_bram_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_17;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_17 is
begin
\use_tdp.ramb36\: entity work.PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_18
     port map (
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(13 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(13 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(13 downto 0),
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_8 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_tx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_8 : entity is "PCIeGen1x8If64_pcie_bram_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_8;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_8 is
begin
\use_tdp.ramb36\: entity work.PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_12
     port map (
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      user_clk => user_clk,
      wdata(17 downto 0) => wdata(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_9 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    mim_tx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_9 : entity is "PCIeGen1x8If64_pcie_bram_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_9;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_9 is
begin
\use_tdp.ramb36\: entity work.PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_11
     port map (
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      user_clk => user_clk,
      wdata(17 downto 0) => wdata(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_pipeline is
  port (
    pipe_tx_rcvr_det : out STD_LOGIC;
    \rate_reg1_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDEEMPH : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_rx0_valid_o : out STD_LOGIC;
    pipe_rx0_chanisaligned_o : out STD_LOGIC;
    pipe_rx0_phy_status_o : out STD_LOGIC;
    pipe_rx0_elec_idle_o : out STD_LOGIC;
    PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rx1_valid_o : out STD_LOGIC;
    pipe_rx1_chanisaligned_o : out STD_LOGIC;
    pipe_rx1_phy_status_o : out STD_LOGIC;
    pipe_rx1_elec_idle_o : out STD_LOGIC;
    pipe_rx2_valid_o : out STD_LOGIC;
    pipe_rx2_chanisaligned_o : out STD_LOGIC;
    pipe_rx2_phy_status_o : out STD_LOGIC;
    pipe_rx2_elec_idle_o : out STD_LOGIC;
    pipe_rx3_valid_o : out STD_LOGIC;
    pipe_rx3_chanisaligned_o : out STD_LOGIC;
    pipe_rx3_phy_status_o : out STD_LOGIC;
    pipe_rx3_elec_idle_o : out STD_LOGIC;
    pipe_rx4_valid_o : out STD_LOGIC;
    pipe_rx4_chanisaligned_o : out STD_LOGIC;
    pipe_rx4_phy_status_o : out STD_LOGIC;
    pipe_rx4_elec_idle_o : out STD_LOGIC;
    pipe_rx5_valid_o : out STD_LOGIC;
    pipe_rx5_chanisaligned_o : out STD_LOGIC;
    pipe_rx5_phy_status_o : out STD_LOGIC;
    pipe_rx5_elec_idle_o : out STD_LOGIC;
    pipe_rx6_valid_o : out STD_LOGIC;
    pipe_rx6_chanisaligned_o : out STD_LOGIC;
    pipe_rx6_phy_status_o : out STD_LOGIC;
    pipe_rx6_elec_idle_o : out STD_LOGIC;
    pipe_rx7_valid_o : out STD_LOGIC;
    pipe_rx7_chanisaligned_o : out STD_LOGIC;
    pipe_rx7_phy_status_o : out STD_LOGIC;
    pipe_rx7_elec_idle_o : out STD_LOGIC;
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    \cplllock_reg1_reg[2]\ : out STD_LOGIC;
    \cplllock_reg1_reg[6]\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cplllock_reg1_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TXMARGIN : out STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXMARGIN : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_TXDATA : out STD_LOGIC_VECTOR ( 127 downto 0 );
    PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_3\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_4\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_5\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_6\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_7\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_8\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_9\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_10\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_11\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_12\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_13\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_14\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_15\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_16\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_17\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_18\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_19\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_20\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_21\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_22\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    phy_rdy_n : in STD_LOGIC;
    pipe_tx_rcvr_det_i : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_tx_rate_i : in STD_LOGIC;
    pipe_tx_deemph_i : in STD_LOGIC;
    pipe_rx0_valid : in STD_LOGIC;
    PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 7 downto 0 );
    gt_rx_phy_status_q : in STD_LOGIC;
    gt_rxelecidle_q : in STD_LOGIC;
    pipe_rx0_polarity_i : in STD_LOGIC;
    pipe_rx1_polarity_i : in STD_LOGIC;
    pipe_rx2_polarity_i : in STD_LOGIC;
    pipe_rx3_polarity_i : in STD_LOGIC;
    pipe_rx4_polarity_i : in STD_LOGIC;
    pipe_rx5_polarity_i : in STD_LOGIC;
    pipe_rx6_polarity_i : in STD_LOGIC;
    pipe_rx7_polarity_i : in STD_LOGIC;
    pipe_tx0_compliance_i : in STD_LOGIC;
    pipe_tx1_compliance_i : in STD_LOGIC;
    pipe_tx2_compliance_i : in STD_LOGIC;
    pipe_tx3_compliance_i : in STD_LOGIC;
    pipe_tx4_compliance_i : in STD_LOGIC;
    pipe_tx5_compliance_i : in STD_LOGIC;
    pipe_tx6_compliance_i : in STD_LOGIC;
    pipe_tx7_compliance_i : in STD_LOGIC;
    pipe_tx0_elec_idle_i : in STD_LOGIC;
    pipe_tx1_elec_idle_i : in STD_LOGIC;
    pipe_tx2_elec_idle_i : in STD_LOGIC;
    pipe_tx3_elec_idle_i : in STD_LOGIC;
    pipe_tx4_elec_idle_i : in STD_LOGIC;
    pipe_tx5_elec_idle_i : in STD_LOGIC;
    pipe_tx6_elec_idle_i : in STD_LOGIC;
    pipe_tx7_elec_idle_i : in STD_LOGIC;
    pipe_rx1_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg : in STD_LOGIC;
    gt_rxelecidle_q_reg : in STD_LOGIC;
    pipe_rx2_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_0 : in STD_LOGIC;
    gt_rxelecidle_q_reg_0 : in STD_LOGIC;
    pipe_rx3_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_1 : in STD_LOGIC;
    gt_rxelecidle_q_reg_1 : in STD_LOGIC;
    pipe_rx4_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_2 : in STD_LOGIC;
    gt_rxelecidle_q_reg_2 : in STD_LOGIC;
    pipe_rx5_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_3 : in STD_LOGIC;
    gt_rxelecidle_q_reg_3 : in STD_LOGIC;
    pipe_rx6_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_4 : in STD_LOGIC;
    gt_rxelecidle_q_reg_4 : in STD_LOGIC;
    pipe_rx7_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_5 : in STD_LOGIC;
    gt_rxelecidle_q_reg_5 : in STD_LOGIC;
    pipe_tx_margin : in STD_LOGIC_VECTOR ( 2 downto 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_7\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_8\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_9\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_10\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_11\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_12\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_13\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_14\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_15\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_16\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_18\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_19\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_20\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_21\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_22\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_2\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_3\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_4\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_4\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_5\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_5\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_6\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_6\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_pipeline : entity is "PCIeGen1x8If64_pcie_pipe_pipeline";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_pipeline;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_pipeline is
begin
pipe_lane_0_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane
     port map (
      CLK => CLK,
      D(1 downto 0) => D(1 downto 0),
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(0),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(0),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(0),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(1 downto 0),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(0),
      gt_rx_phy_status_q => gt_rx_phy_status_q,
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]\(2 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      gt_rxelecidle_q => gt_rxelecidle_q,
      phy_rdy_n => phy_rdy_n,
      pipe_rx0_chanisaligned_o => pipe_rx0_chanisaligned_o,
      pipe_rx0_elec_idle_o => pipe_rx0_elec_idle_o,
      pipe_rx0_phy_status_o => pipe_rx0_phy_status_o,
      pipe_rx0_polarity_i => pipe_rx0_polarity_i,
      pipe_rx0_valid => pipe_rx0_valid,
      pipe_rx0_valid_o => pipe_rx0_valid_o,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_7\(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_15\(1 downto 0),
      pipe_tx0_compliance_i => pipe_tx0_compliance_i,
      pipe_tx0_elec_idle_i => pipe_tx0_elec_idle_i,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2 downto 0)
    );
\pipe_lane_2.pipe_lane_1_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_0
     port map (
      CLK => CLK,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(3 downto 2),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(1),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(1),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(1),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(31 downto 16),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(3 downto 2),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(1),
      gt_rx_phy_status_q_reg => gt_rx_phy_status_q_reg,
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_0\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_0\(15 downto 0),
      gt_rxelecidle_q_reg => gt_rxelecidle_q_reg,
      phy_rdy_n => phy_rdy_n,
      pipe_rx1_chanisaligned_o => pipe_rx1_chanisaligned_o,
      pipe_rx1_elec_idle_o => pipe_rx1_elec_idle_o,
      pipe_rx1_phy_status_o => pipe_rx1_phy_status_o,
      pipe_rx1_polarity_i => pipe_rx1_polarity_i,
      pipe_rx1_valid => pipe_rx1_valid,
      pipe_rx1_valid_o => pipe_rx1_valid_o,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_8\(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_16\(1 downto 0),
      pipe_tx1_compliance_i => pipe_tx1_compliance_i,
      pipe_tx1_elec_idle_i => pipe_tx1_elec_idle_i,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_2\(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_3\(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_4\(2 downto 0)
    );
\pipe_lane_4.pipe_lane_2_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_1
     port map (
      CLK => CLK,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(5 downto 4),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(2),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(2),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(2),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(47 downto 32),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(5 downto 4),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(2),
      gt_rx_phy_status_q_reg => gt_rx_phy_status_q_reg_0,
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_1\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_0\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_1\(15 downto 0),
      gt_rxelecidle_q_reg => gt_rxelecidle_q_reg_0,
      phy_rdy_n => phy_rdy_n,
      pipe_rx2_chanisaligned_o => pipe_rx2_chanisaligned_o,
      pipe_rx2_elec_idle_o => pipe_rx2_elec_idle_o,
      pipe_rx2_phy_status_o => pipe_rx2_phy_status_o,
      pipe_rx2_polarity_i => pipe_rx2_polarity_i,
      pipe_rx2_valid => pipe_rx2_valid,
      pipe_rx2_valid_o => pipe_rx2_valid_o,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_9\(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_17\(1 downto 0),
      pipe_tx2_compliance_i => pipe_tx2_compliance_i,
      pipe_tx2_elec_idle_i => pipe_tx2_elec_idle_i,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_5\(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_6\(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_7\(2 downto 0)
    );
\pipe_lane_4.pipe_lane_3_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_2
     port map (
      CLK => CLK,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(7 downto 6),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(3),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(3),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(3),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(63 downto 48),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(7 downto 6),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(3),
      gt_rx_phy_status_q_reg => gt_rx_phy_status_q_reg_1,
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_2\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_1\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_2\(15 downto 0),
      gt_rxelecidle_q_reg => gt_rxelecidle_q_reg_1,
      phy_rdy_n => phy_rdy_n,
      pipe_rx3_chanisaligned_o => pipe_rx3_chanisaligned_o,
      pipe_rx3_elec_idle_o => pipe_rx3_elec_idle_o,
      pipe_rx3_phy_status_o => pipe_rx3_phy_status_o,
      pipe_rx3_polarity_i => pipe_rx3_polarity_i,
      pipe_rx3_valid => pipe_rx3_valid,
      pipe_rx3_valid_o => pipe_rx3_valid_o,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_10\(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_18\(1 downto 0),
      pipe_tx3_compliance_i => pipe_tx3_compliance_i,
      pipe_tx3_elec_idle_i => pipe_tx3_elec_idle_i,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_8\(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_9\(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_10\(2 downto 0)
    );
\pipe_lane_8.pipe_lane_4_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_3
     port map (
      CLK => CLK,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(9 downto 8),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(4),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(4),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(4),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(79 downto 64),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(9 downto 8),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(4),
      gt_rx_phy_status_q_reg => gt_rx_phy_status_q_reg_2,
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_3\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_2\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_3\(15 downto 0),
      gt_rxelecidle_q_reg => gt_rxelecidle_q_reg_2,
      phy_rdy_n => phy_rdy_n,
      pipe_rx4_chanisaligned_o => pipe_rx4_chanisaligned_o,
      pipe_rx4_elec_idle_o => pipe_rx4_elec_idle_o,
      pipe_rx4_phy_status_o => pipe_rx4_phy_status_o,
      pipe_rx4_polarity_i => pipe_rx4_polarity_i,
      pipe_rx4_valid => pipe_rx4_valid,
      pipe_rx4_valid_o => pipe_rx4_valid_o,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_3\(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_11\(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_19\(1 downto 0),
      pipe_tx4_compliance_i => pipe_tx4_compliance_i,
      pipe_tx4_elec_idle_i => pipe_tx4_elec_idle_i,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_11\(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_12\(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_13\(2 downto 0)
    );
\pipe_lane_8.pipe_lane_5_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_4
     port map (
      CLK => CLK,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(11 downto 10),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(5),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(5),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(5),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(95 downto 80),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(11 downto 10),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(5),
      gt_rx_phy_status_q_reg => gt_rx_phy_status_q_reg_3,
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_4\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_3\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_4\(15 downto 0),
      gt_rxelecidle_q_reg => gt_rxelecidle_q_reg_3,
      phy_rdy_n => phy_rdy_n,
      pipe_rx5_chanisaligned_o => pipe_rx5_chanisaligned_o,
      pipe_rx5_elec_idle_o => pipe_rx5_elec_idle_o,
      pipe_rx5_phy_status_o => pipe_rx5_phy_status_o,
      pipe_rx5_polarity_i => pipe_rx5_polarity_i,
      pipe_rx5_valid => pipe_rx5_valid,
      pipe_rx5_valid_o => pipe_rx5_valid_o,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_4\(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_12\(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_20\(1 downto 0),
      pipe_tx5_compliance_i => pipe_tx5_compliance_i,
      pipe_tx5_elec_idle_i => pipe_tx5_elec_idle_i,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_14\(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_15\(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_16\(2 downto 0)
    );
\pipe_lane_8.pipe_lane_6_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_5
     port map (
      CLK => CLK,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(13 downto 12),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(6),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(6),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(6),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(111 downto 96),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(13 downto 12),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(6),
      gt_rx_phy_status_q_reg => gt_rx_phy_status_q_reg_4,
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_5\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_4\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_5\(15 downto 0),
      gt_rxelecidle_q_reg => gt_rxelecidle_q_reg_4,
      phy_rdy_n => phy_rdy_n,
      pipe_rx6_chanisaligned_o => pipe_rx6_chanisaligned_o,
      pipe_rx6_elec_idle_o => pipe_rx6_elec_idle_o,
      pipe_rx6_phy_status_o => pipe_rx6_phy_status_o,
      pipe_rx6_polarity_i => pipe_rx6_polarity_i,
      pipe_rx6_valid => pipe_rx6_valid,
      pipe_rx6_valid_o => pipe_rx6_valid_o,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_5\(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_13\(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_21\(1 downto 0),
      pipe_tx6_compliance_i => pipe_tx6_compliance_i,
      pipe_tx6_elec_idle_i => pipe_tx6_elec_idle_i,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_17\(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_18\(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_19\(2 downto 0)
    );
\pipe_lane_8.pipe_lane_7_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_6
     port map (
      CLK => CLK,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(15 downto 14),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(7),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(7),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(7),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(127 downto 112),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(15 downto 14),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(7),
      gt_rx_phy_status_q_reg => gt_rx_phy_status_q_reg_5,
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_6\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_5\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_6\(15 downto 0),
      gt_rxelecidle_q_reg => gt_rxelecidle_q_reg_5,
      phy_rdy_n => phy_rdy_n,
      pipe_rx7_chanisaligned_o => pipe_rx7_chanisaligned_o,
      pipe_rx7_elec_idle_o => pipe_rx7_elec_idle_o,
      pipe_rx7_phy_status_o => pipe_rx7_phy_status_o,
      pipe_rx7_polarity_i => pipe_rx7_polarity_i,
      pipe_rx7_valid => pipe_rx7_valid,
      pipe_rx7_valid_o => pipe_rx7_valid_o,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_6\(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(15 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_14\(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_22\(1 downto 0),
      pipe_tx7_compliance_i => pipe_tx7_compliance_i,
      pipe_tx7_elec_idle_i => pipe_tx7_elec_idle_i,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_20\(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_21\(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_22\(2 downto 0)
    );
pipe_misc_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_misc
     port map (
      CLK => CLK,
      PIPE_TXDEEMPH(3 downto 0) => PIPE_TXDEEMPH(3 downto 0),
      PIPE_TXMARGIN(2 downto 0) => PIPE_TXMARGIN(2 downto 0),
      Q(2 downto 0) => Q(2 downto 0),
      TXMARGIN(2 downto 0) => TXMARGIN(2 downto 0),
      \cplllock_reg1_reg[2]\ => \cplllock_reg1_reg[2]\,
      \cplllock_reg1_reg[3]\ => \cplllock_reg1_reg[3]\,
      \cplllock_reg1_reg[3]_0\(2 downto 0) => \cplllock_reg1_reg[3]_0\(2 downto 0),
      \cplllock_reg1_reg[6]\ => \cplllock_reg1_reg[6]\,
      phy_rdy_n => phy_rdy_n,
      pipe_tx_deemph_i => pipe_tx_deemph_i,
      pipe_tx_margin(2 downto 0) => pipe_tx_margin(2 downto 0),
      pipe_tx_rate_i => pipe_tx_rate_i,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_tx_rcvr_det_i => pipe_tx_rcvr_det_i,
      \rate_reg1_reg[0]\(0) => \rate_reg1_reg[0]\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq is
  port (
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RXEQ_ADAPT_DONE : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    CLK : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq : entity is "PCIeGen1x8If64_pipe_eq";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq is
  signal \FSM_onehot_fsm_tx[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[4]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[5]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[5]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[6]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[6]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[2]\ : signal is "yes";
  signal \^user_rxeq_adapt_done\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_fs__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_lf__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2_n_0\ : STD_LOGIC;
  signal \rxeq_preset__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_preset_valid_reg_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_scan_i_n_5 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_user_en_reg1 : STD_LOGIC;
  signal rxeq_user_en_reg2 : STD_LOGIC;
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \txeq_preset[0]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[10]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[11]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[12]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[13]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[14]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[15]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[16]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_preset[1]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[2]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[8]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[9]_i_1_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_tx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[4]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[5]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[6]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[2]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
begin
  USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\;
\FSM_onehot_fsm_tx[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF10101050"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx[1]_i_2_n_0\,
      I3 => txeq_control_reg2(0),
      I4 => txeq_control_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[1]_i_1_n_0\
    );
\FSM_onehot_fsm_tx[1]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[1]_i_2_n_0\
    );
\FSM_onehot_fsm_tx[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20202F20"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I4 => txeq_preset_done,
      O => \FSM_onehot_fsm_tx[2]_i_1_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45454545FF454545"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[3]_i_2_n_0\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \FSM_onehot_fsm_tx[3]_i_1_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_fsm_tx[3]_i_2_n_0\
    );
\FSM_onehot_fsm_tx[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[4]_i_1_n_0\
    );
\FSM_onehot_fsm_tx[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[5]_i_1_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAA8"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[6]_i_2_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_tx[6]_i_3_n_0\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[6]_i_1_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBBBBBB8"
    )
        port map (
      I0 => txeq_preset_done,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[6]_i_2_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      O => \FSM_onehot_fsm_tx[6]_i_3_n_0\
    );
\FSM_onehot_fsm_tx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_tx_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm_tx[1]_i_1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm_tx[2]_i_1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm_tx[3]_i_1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm_tx[4]_i_1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm_tx[5]_i_1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm_tx[6]_i_1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"838183C3"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => rxeq_control_reg2(0),
      O => \FSM_sequential_fsm_rx[0]_i_2_n_0\
    );
\FSM_sequential_fsm_rx[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD000080"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => \FSM_sequential_fsm_rx[0]_i_3_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_rx[2]_i_2_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeq_control_reg2(0),
      I1 => rxeq_control_reg2(1),
      O => \FSM_sequential_fsm_rx[2]_i_3_n_0\
    );
\FSM_sequential_fsm_rx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      S => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_gen3(0),
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_31\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_34\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_39\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[0]\,
      O => TXPRECURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_40\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtx_channel.gtxe2_channel_i_i_41\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtx_channel.gtxe2_channel_i_i_42\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_43\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_44\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_45\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_46\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \^user_rxeq_adapt_done\,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxeq_scan_i_n_5,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04041C10"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00424200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0042420042004200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \rxeq_cnt_reg_n_0_[1]\,
      I5 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_fs[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C203"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_fs[5]_i_1_n_0\
    );
\rxeq_fs[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lf[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF000000000080FF"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I5 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_lf[5]_i_1_n_0\
    );
\rxeq_lf[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => RST_CPLLRESET
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_preset[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(0),
      I4 => \rxeq_preset[2]_i_2_n_0\,
      I5 => \rxeq_preset__0\(0),
      O => \rxeq_preset[0]_i_1_n_0\
    );
\rxeq_preset[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(1),
      I4 => \rxeq_preset[2]_i_2_n_0\,
      I5 => \rxeq_preset__0\(1),
      O => \rxeq_preset[1]_i_1_n_0\
    );
\rxeq_preset[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(2),
      I4 => \rxeq_preset[2]_i_2_n_0\,
      I5 => \rxeq_preset__0\(2),
      O => \rxeq_preset[2]_i_1_n_0\
    );
\rxeq_preset[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F00400FF"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => rxeq_control_reg2(0),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_preset[2]_i_2_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rxeq_preset[0]_i_1_n_0\,
      Q => \rxeq_preset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rxeq_preset[1]_i_1_n_0\,
      Q => \rxeq_preset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \rxeq_preset[2]_i_1_n_0\,
      Q => \rxeq_preset__0\(2),
      R => RST_CPLLRESET
    );
rxeq_preset_valid_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => rxeq_preset_valid
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => rxeq_preset_valid,
      Q => rxeq_preset_valid_reg_n_0,
      R => RST_CPLLRESET
    );
rxeq_scan_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_86
     port map (
      CLK => CLK,
      D(2) => rxeq_scan_i_n_0,
      D(1) => rxeq_scan_i_n_1,
      D(0) => rxeq_scan_i_n_2,
      \FSM_sequential_fsm_rx_reg[0]\ => \FSM_sequential_fsm_rx[0]_i_2_n_0\,
      \FSM_sequential_fsm_rx_reg[2]\(2) => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      \FSM_sequential_fsm_rx_reg[2]\(1) => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      \FSM_sequential_fsm_rx_reg[2]\(0) => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      Q(3 downto 0) => \rxeq_txpreset__0\(3 downto 0),
      RST_CPLLRESET => RST_CPLLRESET,
      USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\,
      \out\(1 downto 0) => rxeq_control_reg2(1 downto 0),
      rxeq_adapt_done_reg => rxeq_scan_i_n_4,
      rxeq_adapt_done_reg_reg => rxeq_scan_i_n_5,
      rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_reg_n_0,
      \rxeq_cnt_reg[1]\ => \FSM_sequential_fsm_rx[0]_i_3_n_0\,
      \rxeq_cnt_reg[1]_0\ => \FSM_sequential_fsm_rx[2]_i_2_n_0\,
      \rxeq_control_reg2_reg[0]\ => \FSM_sequential_fsm_rx[2]_i_3_n_0\,
      \rxeq_fs_reg[5]\(5 downto 0) => \rxeq_fs__0\(5 downto 0),
      \rxeq_lf_reg[5]\(5 downto 0) => \rxeq_lf__0\(5 downto 0),
      rxeq_new_txcoeff_req_reg => rxeq_scan_i_n_3,
      rxeq_new_txcoeff_req_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \rxeq_preset_reg[2]\(2 downto 0) => \rxeq_preset__0\(2 downto 0),
      rxeq_preset_valid_reg => rxeq_preset_valid_reg_n_0,
      \rxeq_txcoeff_reg[17]\(17) => \rxeq_txcoeff_reg_n_0_[17]\,
      \rxeq_txcoeff_reg[17]\(16) => \rxeq_txcoeff_reg_n_0_[16]\,
      \rxeq_txcoeff_reg[17]\(15) => \rxeq_txcoeff_reg_n_0_[15]\,
      \rxeq_txcoeff_reg[17]\(14) => \rxeq_txcoeff_reg_n_0_[14]\,
      \rxeq_txcoeff_reg[17]\(13) => \rxeq_txcoeff_reg_n_0_[13]\,
      \rxeq_txcoeff_reg[17]\(12) => \rxeq_txcoeff_reg_n_0_[12]\,
      \rxeq_txcoeff_reg[17]\(11) => \rxeq_txcoeff_reg_n_0_[11]\,
      \rxeq_txcoeff_reg[17]\(10) => \rxeq_txcoeff_reg_n_0_[10]\,
      \rxeq_txcoeff_reg[17]\(9) => \rxeq_txcoeff_reg_n_0_[9]\,
      \rxeq_txcoeff_reg[17]\(8) => \rxeq_txcoeff_reg_n_0_[8]\,
      \rxeq_txcoeff_reg[17]\(7) => \rxeq_txcoeff_reg_n_0_[7]\,
      \rxeq_txcoeff_reg[17]\(6) => \rxeq_txcoeff_reg_n_0_[6]\,
      \rxeq_txcoeff_reg[17]\(5 downto 0) => \rxeq_txcoeff__0\(5 downto 0)
    );
\rxeq_txcoeff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[6]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[16]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[17]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(0),
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(1),
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(2),
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(3),
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(4),
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(5),
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[7]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[8]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[9]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[10]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[11]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[12]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[13]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[14]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[15]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(10),
      Q => \rxeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(11),
      Q => \rxeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(12),
      Q => \rxeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(13),
      Q => \rxeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(14),
      Q => \rxeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(15),
      Q => \rxeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(16),
      Q => \rxeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(17),
      Q => \rxeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(6),
      Q => \rxeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(7),
      Q => \rxeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(8),
      Q => \rxeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(9),
      Q => \rxeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\rxeq_txpreset[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(0),
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(1),
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(2),
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F405"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_txpreset[3]_i_1_n_0\
    );
\rxeq_txpreset[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(3),
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset__0\(3),
      R => RST_CPLLRESET
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => RST_CPLLRESET
    );
\txeq_preset[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[0]_i_1_n_0\
    );
\txeq_preset[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEABBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[10]_i_1_n_0\
    );
\txeq_preset[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[11]_i_1_n_0\
    );
\txeq_preset[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001574"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[12]_i_1_n_0\
    );
\txeq_preset[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[13]_i_1_n_0\
    );
\txeq_preset[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000410"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[14]_i_1_n_0\
    );
\txeq_preset[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      O => \txeq_preset[15]_i_1_n_0\
    );
\txeq_preset[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0014"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[16]_i_1_n_0\
    );
\txeq_preset[17]_i_1__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => RST_CPLLRESET,
      O => \txeq_preset[17]_i_1__6_n_0\
    );
\txeq_preset[17]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[17]_i_2_n_0\
    );
\txeq_preset[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[1]_i_1_n_0\
    );
\txeq_preset[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[2]_i_1_n_0\
    );
\txeq_preset[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003424"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[3]_i_1_n_0\
    );
\txeq_preset[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000408"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[7]_i_1_n_0\
    );
\txeq_preset[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAEBBFB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[8]_i_1_n_0\
    );
\txeq_preset[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAEBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[9]_i_1_n_0\
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      Q => txeq_preset_done,
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[0]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[10]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[11]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[12]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[13]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[14]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[15]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[16]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[17]_i_2_n_0\,
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[1]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[2]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[3]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[4]\,
      R => '0'
    );
\txeq_preset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[5]\,
      R => '0'
    );
\txeq_preset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[6]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[7]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[8]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_preset[17]_i_1__6_n_0\,
      D => \txeq_preset[9]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \txeq_preset_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[0]_i_2_n_0\,
      O => \txeq_txcoeff[0]_i_1_n_0\
    );
\txeq_txcoeff[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA208A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[0]_i_2_n_0\
    );
\txeq_txcoeff[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[10]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => \txeq_txcoeff[10]_i_2_n_0\,
      O => \txeq_txcoeff[10]_i_1_n_0\
    );
\txeq_txcoeff[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[16]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[10]_i_2_n_0\
    );
\txeq_txcoeff[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[11]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[10]\,
      I4 => \txeq_txcoeff[11]_i_2_n_0\,
      O => \txeq_txcoeff[11]_i_1_n_0\
    );
\txeq_txcoeff[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[18]\,
      I2 => \txeq_txcoeff_reg_n_0_[17]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[11]_i_2_n_0\
    );
\txeq_txcoeff[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[11]\,
      I4 => \txeq_txcoeff[12]_i_2_n_0\,
      O => \txeq_txcoeff[12]_i_1_n_0\
    );
\txeq_txcoeff[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(0),
      I2 => \txeq_txcoeff_reg_n_0_[18]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[12]_i_2_n_0\
    );
\txeq_txcoeff[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[12]\,
      I4 => \txeq_txcoeff[13]_i_2_n_0\,
      O => \txeq_txcoeff[13]_i_1_n_0\
    );
\txeq_txcoeff[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(1),
      I2 => txeq_deemph_reg2(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[13]_i_2_n_0\
    );
\txeq_txcoeff[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => \txeq_txcoeff[14]_i_2_n_0\,
      O => \txeq_txcoeff[14]_i_1_n_0\
    );
\txeq_txcoeff[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[14]_i_2_n_0\
    );
\txeq_txcoeff[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[15]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => \txeq_txcoeff[15]_i_2_n_0\,
      O => \txeq_txcoeff[15]_i_1_n_0\
    );
\txeq_txcoeff[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(3),
      I2 => txeq_deemph_reg2(2),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[15]_i_2_n_0\
    );
\txeq_txcoeff[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[16]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => \txeq_txcoeff[16]_i_2_n_0\,
      O => \txeq_txcoeff[16]_i_1_n_0\
    );
\txeq_txcoeff[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(4),
      I2 => txeq_deemph_reg2(3),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[16]_i_2_n_0\
    );
\txeq_txcoeff[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[17]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => \txeq_txcoeff[17]_i_2_n_0\,
      O => \txeq_txcoeff[17]_i_1_n_0\
    );
\txeq_txcoeff[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(4),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[17]_i_2_n_0\
    );
\txeq_txcoeff[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557FF5755575557"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[1]_i_2_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(0),
      I5 => txeq_control_reg2(1),
      O => \txeq_txcoeff[18]_i_1_n_0\
    );
\txeq_txcoeff[18]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \txeq_txcoeff[18]_i_3_n_0\,
      O => \txeq_txcoeff[18]_i_2_n_0\
    );
\txeq_txcoeff[18]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888F8F888888888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => txeq_deemph_reg2(5),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[18]_i_3_n_0\
    );
\txeq_txcoeff[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[1]_i_2_n_0\,
      O => \txeq_txcoeff[1]_i_1_n_0\
    );
\txeq_txcoeff[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2_n_0\
    );
\txeq_txcoeff[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[1]\,
      I4 => \txeq_txcoeff[2]_i_2_n_0\,
      O => \txeq_txcoeff[2]_i_1_n_0\
    );
\txeq_txcoeff[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[8]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[2]_i_2_n_0\
    );
\txeq_txcoeff[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[2]\,
      I4 => \txeq_txcoeff[3]_i_2_n_0\,
      O => \txeq_txcoeff[3]_i_1_n_0\
    );
\txeq_txcoeff[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff_reg_n_0_[9]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2_n_0\
    );
\txeq_txcoeff[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[3]\,
      I4 => \txeq_txcoeff[4]_i_2_n_0\,
      O => \txeq_txcoeff[4]_i_1_n_0\
    );
\txeq_txcoeff[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff_reg_n_0_[10]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[4]_i_2_n_0\
    );
\txeq_txcoeff[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[4]\,
      I4 => \txeq_txcoeff[5]_i_2_n_0\,
      O => \txeq_txcoeff[5]_i_1_n_0\
    );
\txeq_txcoeff[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      I2 => \txeq_txcoeff_reg_n_0_[11]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[5]_i_2_n_0\
    );
\txeq_txcoeff[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[5]\,
      I4 => \txeq_txcoeff[6]_i_2_n_0\,
      O => \txeq_txcoeff[6]_i_1_n_0\
    );
\txeq_txcoeff[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[12]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[6]_i_2_n_0\
    );
\txeq_txcoeff[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[7]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff[7]_i_2_n_0\,
      O => \txeq_txcoeff[7]_i_1_n_0\
    );
\txeq_txcoeff[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      I2 => \txeq_txcoeff_reg_n_0_[13]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[7]_i_2_n_0\
    );
\txeq_txcoeff[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[8]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => \txeq_txcoeff[8]_i_2_n_0\,
      O => \txeq_txcoeff[8]_i_1_n_0\
    );
\txeq_txcoeff[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      I2 => \txeq_txcoeff_reg_n_0_[14]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[8]_i_2_n_0\
    );
\txeq_txcoeff[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[9]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => \txeq_txcoeff[9]_i_2_n_0\,
      O => \txeq_txcoeff[9]_i_1_n_0\
    );
\txeq_txcoeff[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[15]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[9]_i_2_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4444F444"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => txeq_control_reg2(1),
      I4 => txeq_control_reg2(0),
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[0]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[10]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[11]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[12]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[13]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[14]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[15]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[16]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[17]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[18]_i_2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[1]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[2]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[3]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[4]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[5]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[6]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[7]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[8]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \txeq_txcoeff[18]_i_1_n_0\,
      D => \txeq_txcoeff[9]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_31 is
  port (
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RXEQ_ADAPT_DONE : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_31 : entity is "PCIeGen1x8If64_pipe_eq";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_31;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_31 is
  signal \FSM_onehot_fsm_tx[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[4]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[5]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[5]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[6]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[6]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[2]\ : signal is "yes";
  signal \^user_rxeq_adapt_done\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_fs__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_lf__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_preset_valid_reg_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_scan_i_n_5 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_user_en_reg1 : STD_LOGIC;
  signal rxeq_user_en_reg2 : STD_LOGIC;
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \txeq_preset[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[9]_i_1__0_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2__0_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_tx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[4]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[5]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[6]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[2]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
begin
  USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\;
\FSM_onehot_fsm_tx[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF10101050"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx[1]_i_2__0_n_0\,
      I3 => txeq_control_reg2(0),
      I4 => txeq_control_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[1]_i_1__0_n_0\
    );
\FSM_onehot_fsm_tx[1]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[1]_i_2__0_n_0\
    );
\FSM_onehot_fsm_tx[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20202F20"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I4 => txeq_preset_done,
      O => \FSM_onehot_fsm_tx[2]_i_1__0_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45454545FF454545"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[3]_i_2__0_n_0\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \FSM_onehot_fsm_tx[3]_i_1__0_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_fsm_tx[3]_i_2__0_n_0\
    );
\FSM_onehot_fsm_tx[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[4]_i_1__0_n_0\
    );
\FSM_onehot_fsm_tx[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[5]_i_1__0_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAA8"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[6]_i_2__0_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_tx[6]_i_3__0_n_0\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[6]_i_1__0_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBBBBBB8"
    )
        port map (
      I0 => txeq_preset_done,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[6]_i_2__0_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      O => \FSM_onehot_fsm_tx[6]_i_3__0_n_0\
    );
\FSM_onehot_fsm_tx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_tx_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[1]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[2]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[3]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[4]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[5]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[6]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"838183C3"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => rxeq_control_reg2(0),
      O => \FSM_sequential_fsm_rx[0]_i_2__0_n_0\
    );
\FSM_sequential_fsm_rx[0]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD000080"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => \FSM_sequential_fsm_rx[0]_i_3__0_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_rx[2]_i_2__0_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeq_control_reg2(0),
      I1 => rxeq_control_reg2(1),
      O => \FSM_sequential_fsm_rx[2]_i_3__0_n_0\
    );
\FSM_sequential_fsm_rx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      S => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_30__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_31__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_32__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_33__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_34__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_35__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_36__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_37__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_38__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_39__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[0]\,
      O => TXPRECURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_40__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtx_channel.gtxe2_channel_i_i_41__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtx_channel.gtxe2_channel_i_i_42__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_43__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_44__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_45__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_46__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \^user_rxeq_adapt_done\,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_5,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04041C10"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00424200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0042420042004200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \rxeq_cnt_reg_n_0_[1]\,
      I5 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_fs[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C203"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_fs[5]_i_1__0_n_0\
    );
\rxeq_fs[5]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lf[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF000000000080FF"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I5 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_lf[5]_i_1__0_n_0\
    );
\rxeq_lf[5]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => RST_CPLLRESET
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_preset[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(0),
      I4 => \rxeq_preset[2]_i_2__0_n_0\,
      I5 => \rxeq_preset__0\(0),
      O => \rxeq_preset[0]_i_1__0_n_0\
    );
\rxeq_preset[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(1),
      I4 => \rxeq_preset[2]_i_2__0_n_0\,
      I5 => \rxeq_preset__0\(1),
      O => \rxeq_preset[1]_i_1__0_n_0\
    );
\rxeq_preset[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(2),
      I4 => \rxeq_preset[2]_i_2__0_n_0\,
      I5 => \rxeq_preset__0\(2),
      O => \rxeq_preset[2]_i_1__0_n_0\
    );
\rxeq_preset[2]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F00400FF"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => rxeq_control_reg2(0),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_preset[2]_i_2__0_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[0]_i_1__0_n_0\,
      Q => \rxeq_preset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[1]_i_1__0_n_0\,
      Q => \rxeq_preset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[2]_i_1__0_n_0\,
      Q => \rxeq_preset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_valid_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => rxeq_preset_valid
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid,
      Q => rxeq_preset_valid_reg_n_0,
      R => RST_CPLLRESET
    );
rxeq_scan_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_82
     port map (
      D(2) => rxeq_scan_i_n_0,
      D(1) => rxeq_scan_i_n_1,
      D(0) => rxeq_scan_i_n_2,
      \FSM_sequential_fsm_rx_reg[0]\ => \FSM_sequential_fsm_rx[0]_i_2__0_n_0\,
      \FSM_sequential_fsm_rx_reg[2]\(2) => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      \FSM_sequential_fsm_rx_reg[2]\(1) => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      \FSM_sequential_fsm_rx_reg[2]\(0) => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      Q(3 downto 0) => \rxeq_txpreset__0\(3 downto 0),
      RST_CPLLRESET => RST_CPLLRESET,
      USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\,
      \out\(1 downto 0) => rxeq_control_reg2(1 downto 0),
      pclk_sel_reg => pclk_sel_reg,
      rxeq_adapt_done_reg => rxeq_scan_i_n_4,
      rxeq_adapt_done_reg_reg => rxeq_scan_i_n_5,
      rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_reg_n_0,
      \rxeq_cnt_reg[1]\ => \FSM_sequential_fsm_rx[0]_i_3__0_n_0\,
      \rxeq_cnt_reg[1]_0\ => \FSM_sequential_fsm_rx[2]_i_2__0_n_0\,
      \rxeq_control_reg2_reg[0]\ => \FSM_sequential_fsm_rx[2]_i_3__0_n_0\,
      \rxeq_fs_reg[5]\(5 downto 0) => \rxeq_fs__0\(5 downto 0),
      \rxeq_lf_reg[5]\(5 downto 0) => \rxeq_lf__0\(5 downto 0),
      rxeq_new_txcoeff_req_reg => rxeq_scan_i_n_3,
      rxeq_new_txcoeff_req_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \rxeq_preset_reg[2]\(2 downto 0) => \rxeq_preset__0\(2 downto 0),
      rxeq_preset_valid_reg => rxeq_preset_valid_reg_n_0,
      \rxeq_txcoeff_reg[17]\(17) => \rxeq_txcoeff_reg_n_0_[17]\,
      \rxeq_txcoeff_reg[17]\(16) => \rxeq_txcoeff_reg_n_0_[16]\,
      \rxeq_txcoeff_reg[17]\(15) => \rxeq_txcoeff_reg_n_0_[15]\,
      \rxeq_txcoeff_reg[17]\(14) => \rxeq_txcoeff_reg_n_0_[14]\,
      \rxeq_txcoeff_reg[17]\(13) => \rxeq_txcoeff_reg_n_0_[13]\,
      \rxeq_txcoeff_reg[17]\(12) => \rxeq_txcoeff_reg_n_0_[12]\,
      \rxeq_txcoeff_reg[17]\(11) => \rxeq_txcoeff_reg_n_0_[11]\,
      \rxeq_txcoeff_reg[17]\(10) => \rxeq_txcoeff_reg_n_0_[10]\,
      \rxeq_txcoeff_reg[17]\(9) => \rxeq_txcoeff_reg_n_0_[9]\,
      \rxeq_txcoeff_reg[17]\(8) => \rxeq_txcoeff_reg_n_0_[8]\,
      \rxeq_txcoeff_reg[17]\(7) => \rxeq_txcoeff_reg_n_0_[7]\,
      \rxeq_txcoeff_reg[17]\(6) => \rxeq_txcoeff_reg_n_0_[6]\,
      \rxeq_txcoeff_reg[17]\(5 downto 0) => \rxeq_txcoeff__0\(5 downto 0)
    );
\rxeq_txcoeff[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[6]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[16]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[17]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(0),
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(1),
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(2),
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(3),
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(4),
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(5),
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[7]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[8]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[9]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[10]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[11]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[12]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[13]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[14]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[15]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(10),
      Q => \rxeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(11),
      Q => \rxeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(12),
      Q => \rxeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(13),
      Q => \rxeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(14),
      Q => \rxeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(15),
      Q => \rxeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(16),
      Q => \rxeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(17),
      Q => \rxeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(6),
      Q => \rxeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(7),
      Q => \rxeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(8),
      Q => \rxeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(9),
      Q => \rxeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\rxeq_txpreset[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(0),
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(1),
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(2),
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F405"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_txpreset[3]_i_1__0_n_0\
    );
\rxeq_txpreset[3]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(3),
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset__0\(3),
      R => RST_CPLLRESET
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => RST_CPLLRESET
    );
\txeq_preset[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[0]_i_1__0_n_0\
    );
\txeq_preset[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEABBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[10]_i_1__0_n_0\
    );
\txeq_preset[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[11]_i_1__0_n_0\
    );
\txeq_preset[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001574"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[12]_i_1__0_n_0\
    );
\txeq_preset[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[13]_i_1__0_n_0\
    );
\txeq_preset[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000410"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[14]_i_1__0_n_0\
    );
\txeq_preset[15]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      O => \txeq_preset[15]_i_1__0_n_0\
    );
\txeq_preset[16]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0014"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[16]_i_1__0_n_0\
    );
\txeq_preset[17]_i_1__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => RST_CPLLRESET,
      O => \txeq_preset[17]_i_1__5_n_0\
    );
\txeq_preset[17]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[17]_i_2__0_n_0\
    );
\txeq_preset[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[1]_i_1__0_n_0\
    );
\txeq_preset[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[2]_i_1__0_n_0\
    );
\txeq_preset[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003424"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[3]_i_1__0_n_0\
    );
\txeq_preset[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000408"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[7]_i_1__0_n_0\
    );
\txeq_preset[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAEBBFB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[8]_i_1__0_n_0\
    );
\txeq_preset[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAEBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[9]_i_1__0_n_0\
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      Q => txeq_preset_done,
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[0]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[10]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[11]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[12]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[13]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[14]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[15]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[16]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[17]_i_2__0_n_0\,
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[1]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[2]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[3]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[4]\,
      R => '0'
    );
\txeq_preset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[5]\,
      R => '0'
    );
\txeq_preset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[6]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[7]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[8]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__5_n_0\,
      D => \txeq_preset[9]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \txeq_preset_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[0]_i_2__0_n_0\,
      O => \txeq_txcoeff[0]_i_1__0_n_0\
    );
\txeq_txcoeff[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA208A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[0]_i_2__0_n_0\
    );
\txeq_txcoeff[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[10]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => \txeq_txcoeff[10]_i_2__0_n_0\,
      O => \txeq_txcoeff[10]_i_1__0_n_0\
    );
\txeq_txcoeff[10]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[16]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[10]_i_2__0_n_0\
    );
\txeq_txcoeff[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[11]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[10]\,
      I4 => \txeq_txcoeff[11]_i_2__0_n_0\,
      O => \txeq_txcoeff[11]_i_1__0_n_0\
    );
\txeq_txcoeff[11]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[18]\,
      I2 => \txeq_txcoeff_reg_n_0_[17]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[11]_i_2__0_n_0\
    );
\txeq_txcoeff[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[11]\,
      I4 => \txeq_txcoeff[12]_i_2__0_n_0\,
      O => \txeq_txcoeff[12]_i_1__0_n_0\
    );
\txeq_txcoeff[12]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(0),
      I2 => \txeq_txcoeff_reg_n_0_[18]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[12]_i_2__0_n_0\
    );
\txeq_txcoeff[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[12]\,
      I4 => \txeq_txcoeff[13]_i_2__0_n_0\,
      O => \txeq_txcoeff[13]_i_1__0_n_0\
    );
\txeq_txcoeff[13]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(1),
      I2 => txeq_deemph_reg2(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[13]_i_2__0_n_0\
    );
\txeq_txcoeff[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => \txeq_txcoeff[14]_i_2__0_n_0\,
      O => \txeq_txcoeff[14]_i_1__0_n_0\
    );
\txeq_txcoeff[14]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[14]_i_2__0_n_0\
    );
\txeq_txcoeff[15]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[15]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => \txeq_txcoeff[15]_i_2__0_n_0\,
      O => \txeq_txcoeff[15]_i_1__0_n_0\
    );
\txeq_txcoeff[15]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(3),
      I2 => txeq_deemph_reg2(2),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[15]_i_2__0_n_0\
    );
\txeq_txcoeff[16]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[16]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => \txeq_txcoeff[16]_i_2__0_n_0\,
      O => \txeq_txcoeff[16]_i_1__0_n_0\
    );
\txeq_txcoeff[16]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(4),
      I2 => txeq_deemph_reg2(3),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[16]_i_2__0_n_0\
    );
\txeq_txcoeff[17]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[17]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => \txeq_txcoeff[17]_i_2__0_n_0\,
      O => \txeq_txcoeff[17]_i_1__0_n_0\
    );
\txeq_txcoeff[17]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(4),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[17]_i_2__0_n_0\
    );
\txeq_txcoeff[18]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557FF5755575557"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[1]_i_2__0_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(0),
      I5 => txeq_control_reg2(1),
      O => \txeq_txcoeff[18]_i_1__0_n_0\
    );
\txeq_txcoeff[18]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \txeq_txcoeff[18]_i_3__0_n_0\,
      O => \txeq_txcoeff[18]_i_2__0_n_0\
    );
\txeq_txcoeff[18]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888F8F888888888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => txeq_deemph_reg2(5),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[18]_i_3__0_n_0\
    );
\txeq_txcoeff[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[1]_i_2__0_n_0\,
      O => \txeq_txcoeff[1]_i_1__0_n_0\
    );
\txeq_txcoeff[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2__0_n_0\
    );
\txeq_txcoeff[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[1]\,
      I4 => \txeq_txcoeff[2]_i_2__0_n_0\,
      O => \txeq_txcoeff[2]_i_1__0_n_0\
    );
\txeq_txcoeff[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[8]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[2]_i_2__0_n_0\
    );
\txeq_txcoeff[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[2]\,
      I4 => \txeq_txcoeff[3]_i_2__0_n_0\,
      O => \txeq_txcoeff[3]_i_1__0_n_0\
    );
\txeq_txcoeff[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff_reg_n_0_[9]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2__0_n_0\
    );
\txeq_txcoeff[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[3]\,
      I4 => \txeq_txcoeff[4]_i_2__0_n_0\,
      O => \txeq_txcoeff[4]_i_1__0_n_0\
    );
\txeq_txcoeff[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff_reg_n_0_[10]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[4]_i_2__0_n_0\
    );
\txeq_txcoeff[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[4]\,
      I4 => \txeq_txcoeff[5]_i_2__0_n_0\,
      O => \txeq_txcoeff[5]_i_1__0_n_0\
    );
\txeq_txcoeff[5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      I2 => \txeq_txcoeff_reg_n_0_[11]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[5]_i_2__0_n_0\
    );
\txeq_txcoeff[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[5]\,
      I4 => \txeq_txcoeff[6]_i_2__0_n_0\,
      O => \txeq_txcoeff[6]_i_1__0_n_0\
    );
\txeq_txcoeff[6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[12]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[6]_i_2__0_n_0\
    );
\txeq_txcoeff[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[7]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff[7]_i_2__0_n_0\,
      O => \txeq_txcoeff[7]_i_1__0_n_0\
    );
\txeq_txcoeff[7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      I2 => \txeq_txcoeff_reg_n_0_[13]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[7]_i_2__0_n_0\
    );
\txeq_txcoeff[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[8]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => \txeq_txcoeff[8]_i_2__0_n_0\,
      O => \txeq_txcoeff[8]_i_1__0_n_0\
    );
\txeq_txcoeff[8]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      I2 => \txeq_txcoeff_reg_n_0_[14]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[8]_i_2__0_n_0\
    );
\txeq_txcoeff[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[9]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => \txeq_txcoeff[9]_i_2__0_n_0\,
      O => \txeq_txcoeff[9]_i_1__0_n_0\
    );
\txeq_txcoeff[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[15]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[9]_i_2__0_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4444F444"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => txeq_control_reg2(1),
      I4 => txeq_control_reg2(0),
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[0]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[10]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[11]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[12]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[13]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[14]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[15]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[16]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[17]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[18]_i_2__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[1]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[2]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[3]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[4]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[5]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[6]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[7]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[8]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__0_n_0\,
      D => \txeq_txcoeff[9]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_37 is
  port (
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RXEQ_ADAPT_DONE : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_37 : entity is "PCIeGen1x8If64_pipe_eq";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_37;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_37 is
  signal \FSM_onehot_fsm_tx[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_3__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[4]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[5]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[5]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[6]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[6]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[0]_i_3__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_3__1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[2]\ : signal is "yes";
  signal \^user_rxeq_adapt_done\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \rxeq_fs__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \rxeq_lf__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \rxeq_preset__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_preset_valid_reg_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_scan_i_n_5 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_user_en_reg1 : STD_LOGIC;
  signal rxeq_user_en_reg2 : STD_LOGIC;
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \txeq_preset[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[11]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[13]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[14]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[15]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[16]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[9]_i_1__1_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2__1_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_tx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[4]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[5]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[6]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[2]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
begin
  USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\;
\FSM_onehot_fsm_tx[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF10101050"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx[1]_i_2__1_n_0\,
      I3 => txeq_control_reg2(0),
      I4 => txeq_control_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[1]_i_1__1_n_0\
    );
\FSM_onehot_fsm_tx[1]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[1]_i_2__1_n_0\
    );
\FSM_onehot_fsm_tx[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20202F20"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I4 => txeq_preset_done,
      O => \FSM_onehot_fsm_tx[2]_i_1__1_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45454545FF454545"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[3]_i_2__1_n_0\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \FSM_onehot_fsm_tx[3]_i_1__1_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_fsm_tx[3]_i_2__1_n_0\
    );
\FSM_onehot_fsm_tx[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[4]_i_1__1_n_0\
    );
\FSM_onehot_fsm_tx[5]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[5]_i_1__1_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAA8"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[6]_i_2__1_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_tx[6]_i_3__1_n_0\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[6]_i_1__1_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBBBBBB8"
    )
        port map (
      I0 => txeq_preset_done,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[6]_i_2__1_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      O => \FSM_onehot_fsm_tx[6]_i_3__1_n_0\
    );
\FSM_onehot_fsm_tx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_tx_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[1]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[2]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[3]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[4]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[5]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[6]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"838183C3"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => rxeq_control_reg2(0),
      O => \FSM_sequential_fsm_rx[0]_i_2__1_n_0\
    );
\FSM_sequential_fsm_rx[0]_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD000080"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => \FSM_sequential_fsm_rx[0]_i_3__1_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_rx[2]_i_2__1_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_3__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeq_control_reg2(0),
      I1 => rxeq_control_reg2(1),
      O => \FSM_sequential_fsm_rx[2]_i_3__1_n_0\
    );
\FSM_sequential_fsm_rx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      S => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_31__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_32__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_33__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_34__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_35__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_36__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_37__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_38__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_39__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_40__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[0]\,
      O => TXPRECURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_41__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtx_channel.gtxe2_channel_i_i_42__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtx_channel.gtxe2_channel_i_i_43__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_44__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_45__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_46__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_47\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \^user_rxeq_adapt_done\,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_5,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_cnt[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04041C10"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00424200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0042420042004200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \rxeq_cnt_reg_n_0_[1]\,
      I5 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_fs[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C203"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_fs[5]_i_1__1_n_0\
    );
\rxeq_fs[5]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__1_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__1_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__1_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__1_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__1_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__1_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lf[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF000000000080FF"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I5 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_lf[5]_i_1__1_n_0\
    );
\rxeq_lf[5]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__1_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__1_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__1_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__1_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__1_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__1_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => RST_CPLLRESET
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_preset[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(0),
      I4 => \rxeq_preset[2]_i_2__1_n_0\,
      I5 => \rxeq_preset__0\(0),
      O => \rxeq_preset[0]_i_1__1_n_0\
    );
\rxeq_preset[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(1),
      I4 => \rxeq_preset[2]_i_2__1_n_0\,
      I5 => \rxeq_preset__0\(1),
      O => \rxeq_preset[1]_i_1__1_n_0\
    );
\rxeq_preset[2]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(2),
      I4 => \rxeq_preset[2]_i_2__1_n_0\,
      I5 => \rxeq_preset__0\(2),
      O => \rxeq_preset[2]_i_1__1_n_0\
    );
\rxeq_preset[2]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F00400FF"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => rxeq_control_reg2(0),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_preset[2]_i_2__1_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[0]_i_1__1_n_0\,
      Q => \rxeq_preset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[1]_i_1__1_n_0\,
      Q => \rxeq_preset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[2]_i_1__1_n_0\,
      Q => \rxeq_preset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_valid_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => rxeq_preset_valid
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid,
      Q => rxeq_preset_valid_reg_n_0,
      R => RST_CPLLRESET
    );
rxeq_scan_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_80
     port map (
      D(2) => rxeq_scan_i_n_0,
      D(1) => rxeq_scan_i_n_1,
      D(0) => rxeq_scan_i_n_2,
      \FSM_sequential_fsm_rx_reg[0]\ => \FSM_sequential_fsm_rx[0]_i_2__1_n_0\,
      \FSM_sequential_fsm_rx_reg[2]\(2) => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      \FSM_sequential_fsm_rx_reg[2]\(1) => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      \FSM_sequential_fsm_rx_reg[2]\(0) => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      Q(3 downto 0) => \rxeq_txpreset__0\(3 downto 0),
      RST_CPLLRESET => RST_CPLLRESET,
      USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\,
      \out\(1 downto 0) => rxeq_control_reg2(1 downto 0),
      pclk_sel_reg => pclk_sel_reg,
      rxeq_adapt_done_reg => rxeq_scan_i_n_4,
      rxeq_adapt_done_reg_reg => rxeq_scan_i_n_5,
      rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_reg_n_0,
      \rxeq_cnt_reg[1]\ => \FSM_sequential_fsm_rx[0]_i_3__1_n_0\,
      \rxeq_cnt_reg[1]_0\ => \FSM_sequential_fsm_rx[2]_i_2__1_n_0\,
      \rxeq_control_reg2_reg[0]\ => \FSM_sequential_fsm_rx[2]_i_3__1_n_0\,
      \rxeq_fs_reg[5]\(5 downto 0) => \rxeq_fs__0\(5 downto 0),
      \rxeq_lf_reg[5]\(5 downto 0) => \rxeq_lf__0\(5 downto 0),
      rxeq_new_txcoeff_req_reg => rxeq_scan_i_n_3,
      rxeq_new_txcoeff_req_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \rxeq_preset_reg[2]\(2 downto 0) => \rxeq_preset__0\(2 downto 0),
      rxeq_preset_valid_reg => rxeq_preset_valid_reg_n_0,
      \rxeq_txcoeff_reg[17]\(17) => \rxeq_txcoeff_reg_n_0_[17]\,
      \rxeq_txcoeff_reg[17]\(16) => \rxeq_txcoeff_reg_n_0_[16]\,
      \rxeq_txcoeff_reg[17]\(15) => \rxeq_txcoeff_reg_n_0_[15]\,
      \rxeq_txcoeff_reg[17]\(14) => \rxeq_txcoeff_reg_n_0_[14]\,
      \rxeq_txcoeff_reg[17]\(13) => \rxeq_txcoeff_reg_n_0_[13]\,
      \rxeq_txcoeff_reg[17]\(12) => \rxeq_txcoeff_reg_n_0_[12]\,
      \rxeq_txcoeff_reg[17]\(11) => \rxeq_txcoeff_reg_n_0_[11]\,
      \rxeq_txcoeff_reg[17]\(10) => \rxeq_txcoeff_reg_n_0_[10]\,
      \rxeq_txcoeff_reg[17]\(9) => \rxeq_txcoeff_reg_n_0_[9]\,
      \rxeq_txcoeff_reg[17]\(8) => \rxeq_txcoeff_reg_n_0_[8]\,
      \rxeq_txcoeff_reg[17]\(7) => \rxeq_txcoeff_reg_n_0_[7]\,
      \rxeq_txcoeff_reg[17]\(6) => \rxeq_txcoeff_reg_n_0_[6]\,
      \rxeq_txcoeff_reg[17]\(5 downto 0) => \rxeq_txcoeff__0\(5 downto 0)
    );
\rxeq_txcoeff[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[6]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[16]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[17]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(0),
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(1),
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(2),
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(3),
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(4),
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(5),
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[7]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[8]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[9]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[10]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[11]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[12]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[13]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[14]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[15]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(10),
      Q => \rxeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(11),
      Q => \rxeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(12),
      Q => \rxeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(13),
      Q => \rxeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(14),
      Q => \rxeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(15),
      Q => \rxeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(16),
      Q => \rxeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(17),
      Q => \rxeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(6),
      Q => \rxeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(7),
      Q => \rxeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(8),
      Q => \rxeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txcoeff(9),
      Q => \rxeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\rxeq_txpreset[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(0),
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(1),
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(2),
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F405"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_txpreset[3]_i_1__1_n_0\
    );
\rxeq_txpreset[3]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(3),
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__1_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset__0\(3),
      R => RST_CPLLRESET
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => RST_CPLLRESET
    );
\txeq_preset[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[0]_i_1__1_n_0\
    );
\txeq_preset[10]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEABBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[10]_i_1__1_n_0\
    );
\txeq_preset[11]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[11]_i_1__1_n_0\
    );
\txeq_preset[12]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001574"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[12]_i_1__1_n_0\
    );
\txeq_preset[13]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[13]_i_1__1_n_0\
    );
\txeq_preset[14]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000410"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[14]_i_1__1_n_0\
    );
\txeq_preset[15]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      O => \txeq_preset[15]_i_1__1_n_0\
    );
\txeq_preset[16]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0014"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[16]_i_1__1_n_0\
    );
\txeq_preset[17]_i_1__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => RST_CPLLRESET,
      O => \txeq_preset[17]_i_1__4_n_0\
    );
\txeq_preset[17]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[17]_i_2__1_n_0\
    );
\txeq_preset[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[1]_i_1__1_n_0\
    );
\txeq_preset[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[2]_i_1__1_n_0\
    );
\txeq_preset[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003424"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[3]_i_1__1_n_0\
    );
\txeq_preset[7]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000408"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[7]_i_1__1_n_0\
    );
\txeq_preset[8]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAEBBFB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[8]_i_1__1_n_0\
    );
\txeq_preset[9]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAEBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[9]_i_1__1_n_0\
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      Q => txeq_preset_done,
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[0]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[10]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[11]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[12]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[13]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[14]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[15]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[16]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[17]_i_2__1_n_0\,
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[1]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[2]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[3]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[4]\,
      R => '0'
    );
\txeq_preset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[5]\,
      R => '0'
    );
\txeq_preset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[6]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[7]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[8]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__4_n_0\,
      D => \txeq_preset[9]_i_1__1_n_0\,
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \txeq_preset_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[0]_i_2__1_n_0\,
      O => \txeq_txcoeff[0]_i_1__1_n_0\
    );
\txeq_txcoeff[0]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA208A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[0]_i_2__1_n_0\
    );
\txeq_txcoeff[10]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[10]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => \txeq_txcoeff[10]_i_2__1_n_0\,
      O => \txeq_txcoeff[10]_i_1__1_n_0\
    );
\txeq_txcoeff[10]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[16]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[10]_i_2__1_n_0\
    );
\txeq_txcoeff[11]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[11]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[10]\,
      I4 => \txeq_txcoeff[11]_i_2__1_n_0\,
      O => \txeq_txcoeff[11]_i_1__1_n_0\
    );
\txeq_txcoeff[11]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[18]\,
      I2 => \txeq_txcoeff_reg_n_0_[17]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[11]_i_2__1_n_0\
    );
\txeq_txcoeff[12]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[11]\,
      I4 => \txeq_txcoeff[12]_i_2__1_n_0\,
      O => \txeq_txcoeff[12]_i_1__1_n_0\
    );
\txeq_txcoeff[12]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(0),
      I2 => \txeq_txcoeff_reg_n_0_[18]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[12]_i_2__1_n_0\
    );
\txeq_txcoeff[13]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[12]\,
      I4 => \txeq_txcoeff[13]_i_2__1_n_0\,
      O => \txeq_txcoeff[13]_i_1__1_n_0\
    );
\txeq_txcoeff[13]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(1),
      I2 => txeq_deemph_reg2(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[13]_i_2__1_n_0\
    );
\txeq_txcoeff[14]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => \txeq_txcoeff[14]_i_2__1_n_0\,
      O => \txeq_txcoeff[14]_i_1__1_n_0\
    );
\txeq_txcoeff[14]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[14]_i_2__1_n_0\
    );
\txeq_txcoeff[15]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[15]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => \txeq_txcoeff[15]_i_2__1_n_0\,
      O => \txeq_txcoeff[15]_i_1__1_n_0\
    );
\txeq_txcoeff[15]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(3),
      I2 => txeq_deemph_reg2(2),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[15]_i_2__1_n_0\
    );
\txeq_txcoeff[16]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[16]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => \txeq_txcoeff[16]_i_2__1_n_0\,
      O => \txeq_txcoeff[16]_i_1__1_n_0\
    );
\txeq_txcoeff[16]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(4),
      I2 => txeq_deemph_reg2(3),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[16]_i_2__1_n_0\
    );
\txeq_txcoeff[17]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[17]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => \txeq_txcoeff[17]_i_2__1_n_0\,
      O => \txeq_txcoeff[17]_i_1__1_n_0\
    );
\txeq_txcoeff[17]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(4),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[17]_i_2__1_n_0\
    );
\txeq_txcoeff[18]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557FF5755575557"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[1]_i_2__1_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(0),
      I5 => txeq_control_reg2(1),
      O => \txeq_txcoeff[18]_i_1__1_n_0\
    );
\txeq_txcoeff[18]_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \txeq_txcoeff[18]_i_3__1_n_0\,
      O => \txeq_txcoeff[18]_i_2__1_n_0\
    );
\txeq_txcoeff[18]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888F8F888888888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => txeq_deemph_reg2(5),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[18]_i_3__1_n_0\
    );
\txeq_txcoeff[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[1]_i_2__1_n_0\,
      O => \txeq_txcoeff[1]_i_1__1_n_0\
    );
\txeq_txcoeff[1]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2__1_n_0\
    );
\txeq_txcoeff[2]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[1]\,
      I4 => \txeq_txcoeff[2]_i_2__1_n_0\,
      O => \txeq_txcoeff[2]_i_1__1_n_0\
    );
\txeq_txcoeff[2]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[8]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[2]_i_2__1_n_0\
    );
\txeq_txcoeff[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[2]\,
      I4 => \txeq_txcoeff[3]_i_2__1_n_0\,
      O => \txeq_txcoeff[3]_i_1__1_n_0\
    );
\txeq_txcoeff[3]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff_reg_n_0_[9]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2__1_n_0\
    );
\txeq_txcoeff[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[3]\,
      I4 => \txeq_txcoeff[4]_i_2__1_n_0\,
      O => \txeq_txcoeff[4]_i_1__1_n_0\
    );
\txeq_txcoeff[4]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff_reg_n_0_[10]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[4]_i_2__1_n_0\
    );
\txeq_txcoeff[5]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[4]\,
      I4 => \txeq_txcoeff[5]_i_2__1_n_0\,
      O => \txeq_txcoeff[5]_i_1__1_n_0\
    );
\txeq_txcoeff[5]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      I2 => \txeq_txcoeff_reg_n_0_[11]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[5]_i_2__1_n_0\
    );
\txeq_txcoeff[6]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[5]\,
      I4 => \txeq_txcoeff[6]_i_2__1_n_0\,
      O => \txeq_txcoeff[6]_i_1__1_n_0\
    );
\txeq_txcoeff[6]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[12]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[6]_i_2__1_n_0\
    );
\txeq_txcoeff[7]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[7]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff[7]_i_2__1_n_0\,
      O => \txeq_txcoeff[7]_i_1__1_n_0\
    );
\txeq_txcoeff[7]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      I2 => \txeq_txcoeff_reg_n_0_[13]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[7]_i_2__1_n_0\
    );
\txeq_txcoeff[8]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[8]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => \txeq_txcoeff[8]_i_2__1_n_0\,
      O => \txeq_txcoeff[8]_i_1__1_n_0\
    );
\txeq_txcoeff[8]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      I2 => \txeq_txcoeff_reg_n_0_[14]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[8]_i_2__1_n_0\
    );
\txeq_txcoeff[9]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[9]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => \txeq_txcoeff[9]_i_2__1_n_0\,
      O => \txeq_txcoeff[9]_i_1__1_n_0\
    );
\txeq_txcoeff[9]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[15]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[9]_i_2__1_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4444F444"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => txeq_control_reg2(1),
      I4 => txeq_control_reg2(0),
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[0]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[10]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[11]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[12]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[13]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[14]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[15]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[16]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[17]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[18]_i_2__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[1]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[2]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[3]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[4]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[5]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[6]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[7]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[8]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__1_n_0\,
      D => \txeq_txcoeff[9]_i_1__1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_43 is
  port (
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RXEQ_ADAPT_DONE : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_43 : entity is "PCIeGen1x8If64_pipe_eq";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_43;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_43 is
  signal \FSM_onehot_fsm_tx[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_3__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[4]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[5]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[5]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[6]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[6]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[0]_i_3__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_3__2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[2]\ : signal is "yes";
  signal \^user_rxeq_adapt_done\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \rxeq_fs__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \rxeq_lf__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \rxeq_preset__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_preset_valid_reg_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_scan_i_n_5 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_user_en_reg1 : STD_LOGIC;
  signal rxeq_user_en_reg2 : STD_LOGIC;
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \txeq_preset[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[10]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[11]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[13]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[14]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[15]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[16]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[9]_i_1__2_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2__2_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_tx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[4]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[5]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[6]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[2]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
begin
  USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\;
\FSM_onehot_fsm_tx[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF10101050"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx[1]_i_2__2_n_0\,
      I3 => txeq_control_reg2(0),
      I4 => txeq_control_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[1]_i_1__2_n_0\
    );
\FSM_onehot_fsm_tx[1]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[1]_i_2__2_n_0\
    );
\FSM_onehot_fsm_tx[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20202F20"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I4 => txeq_preset_done,
      O => \FSM_onehot_fsm_tx[2]_i_1__2_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45454545FF454545"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[3]_i_2__2_n_0\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \FSM_onehot_fsm_tx[3]_i_1__2_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_fsm_tx[3]_i_2__2_n_0\
    );
\FSM_onehot_fsm_tx[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[4]_i_1__2_n_0\
    );
\FSM_onehot_fsm_tx[5]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[5]_i_1__2_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAA8"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[6]_i_2__2_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_tx[6]_i_3__2_n_0\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[6]_i_1__2_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBBBBBB8"
    )
        port map (
      I0 => txeq_preset_done,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[6]_i_2__2_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      O => \FSM_onehot_fsm_tx[6]_i_3__2_n_0\
    );
\FSM_onehot_fsm_tx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_tx_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[1]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[2]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[3]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[4]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[5]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[6]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"838183C3"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => rxeq_control_reg2(0),
      O => \FSM_sequential_fsm_rx[0]_i_2__2_n_0\
    );
\FSM_sequential_fsm_rx[0]_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD000080"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => \FSM_sequential_fsm_rx[0]_i_3__2_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_rx[2]_i_2__2_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_3__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeq_control_reg2(0),
      I1 => rxeq_control_reg2(1),
      O => \FSM_sequential_fsm_rx[2]_i_3__2_n_0\
    );
\FSM_sequential_fsm_rx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      S => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_31__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_32__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_33__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_34__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_35__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_36__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_37__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_38__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_39__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_40__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[0]\,
      O => TXPRECURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_41__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtx_channel.gtxe2_channel_i_i_42__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtx_channel.gtxe2_channel_i_i_43__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_44__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_45__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_46__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_47__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \^user_rxeq_adapt_done\,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_5,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_cnt[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04041C10"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00424200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0042420042004200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \rxeq_cnt_reg_n_0_[1]\,
      I5 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_fs[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C203"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_fs[5]_i_1__2_n_0\
    );
\rxeq_fs[5]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__2_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__2_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__2_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__2_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__2_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__2_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lf[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF000000000080FF"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I5 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_lf[5]_i_1__2_n_0\
    );
\rxeq_lf[5]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__2_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__2_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__2_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__2_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__2_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__2_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => RST_CPLLRESET
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_preset[0]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(0),
      I4 => \rxeq_preset[2]_i_2__2_n_0\,
      I5 => \rxeq_preset__0\(0),
      O => \rxeq_preset[0]_i_1__2_n_0\
    );
\rxeq_preset[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(1),
      I4 => \rxeq_preset[2]_i_2__2_n_0\,
      I5 => \rxeq_preset__0\(1),
      O => \rxeq_preset[1]_i_1__2_n_0\
    );
\rxeq_preset[2]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(2),
      I4 => \rxeq_preset[2]_i_2__2_n_0\,
      I5 => \rxeq_preset__0\(2),
      O => \rxeq_preset[2]_i_1__2_n_0\
    );
\rxeq_preset[2]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F00400FF"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => rxeq_control_reg2(0),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_preset[2]_i_2__2_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[0]_i_1__2_n_0\,
      Q => \rxeq_preset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[1]_i_1__2_n_0\,
      Q => \rxeq_preset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[2]_i_1__2_n_0\,
      Q => \rxeq_preset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_valid_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => rxeq_preset_valid
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid,
      Q => rxeq_preset_valid_reg_n_0,
      R => RST_CPLLRESET
    );
rxeq_scan_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_78
     port map (
      D(2) => rxeq_scan_i_n_0,
      D(1) => rxeq_scan_i_n_1,
      D(0) => rxeq_scan_i_n_2,
      \FSM_sequential_fsm_rx_reg[0]\ => \FSM_sequential_fsm_rx[0]_i_2__2_n_0\,
      \FSM_sequential_fsm_rx_reg[2]\(2) => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      \FSM_sequential_fsm_rx_reg[2]\(1) => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      \FSM_sequential_fsm_rx_reg[2]\(0) => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      Q(3 downto 0) => \rxeq_txpreset__0\(3 downto 0),
      RST_CPLLRESET => RST_CPLLRESET,
      USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\,
      \out\(1 downto 0) => rxeq_control_reg2(1 downto 0),
      pclk_sel_reg => pclk_sel_reg,
      rxeq_adapt_done_reg => rxeq_scan_i_n_4,
      rxeq_adapt_done_reg_reg => rxeq_scan_i_n_5,
      rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_reg_n_0,
      \rxeq_cnt_reg[1]\ => \FSM_sequential_fsm_rx[0]_i_3__2_n_0\,
      \rxeq_cnt_reg[1]_0\ => \FSM_sequential_fsm_rx[2]_i_2__2_n_0\,
      \rxeq_control_reg2_reg[0]\ => \FSM_sequential_fsm_rx[2]_i_3__2_n_0\,
      \rxeq_fs_reg[5]\(5 downto 0) => \rxeq_fs__0\(5 downto 0),
      \rxeq_lf_reg[5]\(5 downto 0) => \rxeq_lf__0\(5 downto 0),
      rxeq_new_txcoeff_req_reg => rxeq_scan_i_n_3,
      rxeq_new_txcoeff_req_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \rxeq_preset_reg[2]\(2 downto 0) => \rxeq_preset__0\(2 downto 0),
      rxeq_preset_valid_reg => rxeq_preset_valid_reg_n_0,
      \rxeq_txcoeff_reg[17]\(17) => \rxeq_txcoeff_reg_n_0_[17]\,
      \rxeq_txcoeff_reg[17]\(16) => \rxeq_txcoeff_reg_n_0_[16]\,
      \rxeq_txcoeff_reg[17]\(15) => \rxeq_txcoeff_reg_n_0_[15]\,
      \rxeq_txcoeff_reg[17]\(14) => \rxeq_txcoeff_reg_n_0_[14]\,
      \rxeq_txcoeff_reg[17]\(13) => \rxeq_txcoeff_reg_n_0_[13]\,
      \rxeq_txcoeff_reg[17]\(12) => \rxeq_txcoeff_reg_n_0_[12]\,
      \rxeq_txcoeff_reg[17]\(11) => \rxeq_txcoeff_reg_n_0_[11]\,
      \rxeq_txcoeff_reg[17]\(10) => \rxeq_txcoeff_reg_n_0_[10]\,
      \rxeq_txcoeff_reg[17]\(9) => \rxeq_txcoeff_reg_n_0_[9]\,
      \rxeq_txcoeff_reg[17]\(8) => \rxeq_txcoeff_reg_n_0_[8]\,
      \rxeq_txcoeff_reg[17]\(7) => \rxeq_txcoeff_reg_n_0_[7]\,
      \rxeq_txcoeff_reg[17]\(6) => \rxeq_txcoeff_reg_n_0_[6]\,
      \rxeq_txcoeff_reg[17]\(5 downto 0) => \rxeq_txcoeff__0\(5 downto 0)
    );
\rxeq_txcoeff[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[6]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[16]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[17]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(0),
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(1),
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(2),
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(3),
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(4),
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(5),
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[7]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[8]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[9]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[10]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[11]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[12]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[13]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[14]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[15]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(10),
      Q => \rxeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(11),
      Q => \rxeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(12),
      Q => \rxeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(13),
      Q => \rxeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(14),
      Q => \rxeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(15),
      Q => \rxeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(16),
      Q => \rxeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(17),
      Q => \rxeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(6),
      Q => \rxeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(7),
      Q => \rxeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(8),
      Q => \rxeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txcoeff(9),
      Q => \rxeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\rxeq_txpreset[0]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(0),
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(1),
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(2),
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F405"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_txpreset[3]_i_1__2_n_0\
    );
\rxeq_txpreset[3]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(3),
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__2_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset__0\(3),
      R => RST_CPLLRESET
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => RST_CPLLRESET
    );
\txeq_preset[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[0]_i_1__2_n_0\
    );
\txeq_preset[10]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEABBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[10]_i_1__2_n_0\
    );
\txeq_preset[11]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[11]_i_1__2_n_0\
    );
\txeq_preset[12]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001574"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[12]_i_1__2_n_0\
    );
\txeq_preset[13]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[13]_i_1__2_n_0\
    );
\txeq_preset[14]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000410"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[14]_i_1__2_n_0\
    );
\txeq_preset[15]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      O => \txeq_preset[15]_i_1__2_n_0\
    );
\txeq_preset[16]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0014"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[16]_i_1__2_n_0\
    );
\txeq_preset[17]_i_1__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => RST_CPLLRESET,
      O => \txeq_preset[17]_i_1__3_n_0\
    );
\txeq_preset[17]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[17]_i_2__2_n_0\
    );
\txeq_preset[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[1]_i_1__2_n_0\
    );
\txeq_preset[2]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[2]_i_1__2_n_0\
    );
\txeq_preset[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003424"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[3]_i_1__2_n_0\
    );
\txeq_preset[7]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000408"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[7]_i_1__2_n_0\
    );
\txeq_preset[8]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAEBBFB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[8]_i_1__2_n_0\
    );
\txeq_preset[9]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAEBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[9]_i_1__2_n_0\
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      Q => txeq_preset_done,
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[0]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[10]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[11]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[12]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[13]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[14]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[15]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[16]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[17]_i_2__2_n_0\,
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[1]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[2]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[3]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[4]\,
      R => '0'
    );
\txeq_preset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[5]\,
      R => '0'
    );
\txeq_preset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[6]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[7]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[8]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__3_n_0\,
      D => \txeq_preset[9]_i_1__2_n_0\,
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \txeq_preset_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[0]_i_2__2_n_0\,
      O => \txeq_txcoeff[0]_i_1__2_n_0\
    );
\txeq_txcoeff[0]_i_2__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA208A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[0]_i_2__2_n_0\
    );
\txeq_txcoeff[10]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[10]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => \txeq_txcoeff[10]_i_2__2_n_0\,
      O => \txeq_txcoeff[10]_i_1__2_n_0\
    );
\txeq_txcoeff[10]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[16]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[10]_i_2__2_n_0\
    );
\txeq_txcoeff[11]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[11]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[10]\,
      I4 => \txeq_txcoeff[11]_i_2__2_n_0\,
      O => \txeq_txcoeff[11]_i_1__2_n_0\
    );
\txeq_txcoeff[11]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[18]\,
      I2 => \txeq_txcoeff_reg_n_0_[17]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[11]_i_2__2_n_0\
    );
\txeq_txcoeff[12]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[11]\,
      I4 => \txeq_txcoeff[12]_i_2__2_n_0\,
      O => \txeq_txcoeff[12]_i_1__2_n_0\
    );
\txeq_txcoeff[12]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(0),
      I2 => \txeq_txcoeff_reg_n_0_[18]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[12]_i_2__2_n_0\
    );
\txeq_txcoeff[13]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[12]\,
      I4 => \txeq_txcoeff[13]_i_2__2_n_0\,
      O => \txeq_txcoeff[13]_i_1__2_n_0\
    );
\txeq_txcoeff[13]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(1),
      I2 => txeq_deemph_reg2(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[13]_i_2__2_n_0\
    );
\txeq_txcoeff[14]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => \txeq_txcoeff[14]_i_2__2_n_0\,
      O => \txeq_txcoeff[14]_i_1__2_n_0\
    );
\txeq_txcoeff[14]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[14]_i_2__2_n_0\
    );
\txeq_txcoeff[15]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[15]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => \txeq_txcoeff[15]_i_2__2_n_0\,
      O => \txeq_txcoeff[15]_i_1__2_n_0\
    );
\txeq_txcoeff[15]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(3),
      I2 => txeq_deemph_reg2(2),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[15]_i_2__2_n_0\
    );
\txeq_txcoeff[16]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[16]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => \txeq_txcoeff[16]_i_2__2_n_0\,
      O => \txeq_txcoeff[16]_i_1__2_n_0\
    );
\txeq_txcoeff[16]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(4),
      I2 => txeq_deemph_reg2(3),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[16]_i_2__2_n_0\
    );
\txeq_txcoeff[17]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[17]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => \txeq_txcoeff[17]_i_2__2_n_0\,
      O => \txeq_txcoeff[17]_i_1__2_n_0\
    );
\txeq_txcoeff[17]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(4),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[17]_i_2__2_n_0\
    );
\txeq_txcoeff[18]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557FF5755575557"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[1]_i_2__2_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(0),
      I5 => txeq_control_reg2(1),
      O => \txeq_txcoeff[18]_i_1__2_n_0\
    );
\txeq_txcoeff[18]_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \txeq_txcoeff[18]_i_3__2_n_0\,
      O => \txeq_txcoeff[18]_i_2__2_n_0\
    );
\txeq_txcoeff[18]_i_3__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888F8F888888888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => txeq_deemph_reg2(5),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[18]_i_3__2_n_0\
    );
\txeq_txcoeff[1]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[1]_i_2__2_n_0\,
      O => \txeq_txcoeff[1]_i_1__2_n_0\
    );
\txeq_txcoeff[1]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2__2_n_0\
    );
\txeq_txcoeff[2]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[1]\,
      I4 => \txeq_txcoeff[2]_i_2__2_n_0\,
      O => \txeq_txcoeff[2]_i_1__2_n_0\
    );
\txeq_txcoeff[2]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[8]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[2]_i_2__2_n_0\
    );
\txeq_txcoeff[3]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[2]\,
      I4 => \txeq_txcoeff[3]_i_2__2_n_0\,
      O => \txeq_txcoeff[3]_i_1__2_n_0\
    );
\txeq_txcoeff[3]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff_reg_n_0_[9]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2__2_n_0\
    );
\txeq_txcoeff[4]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[3]\,
      I4 => \txeq_txcoeff[4]_i_2__2_n_0\,
      O => \txeq_txcoeff[4]_i_1__2_n_0\
    );
\txeq_txcoeff[4]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff_reg_n_0_[10]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[4]_i_2__2_n_0\
    );
\txeq_txcoeff[5]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[4]\,
      I4 => \txeq_txcoeff[5]_i_2__2_n_0\,
      O => \txeq_txcoeff[5]_i_1__2_n_0\
    );
\txeq_txcoeff[5]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      I2 => \txeq_txcoeff_reg_n_0_[11]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[5]_i_2__2_n_0\
    );
\txeq_txcoeff[6]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[5]\,
      I4 => \txeq_txcoeff[6]_i_2__2_n_0\,
      O => \txeq_txcoeff[6]_i_1__2_n_0\
    );
\txeq_txcoeff[6]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[12]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[6]_i_2__2_n_0\
    );
\txeq_txcoeff[7]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[7]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff[7]_i_2__2_n_0\,
      O => \txeq_txcoeff[7]_i_1__2_n_0\
    );
\txeq_txcoeff[7]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      I2 => \txeq_txcoeff_reg_n_0_[13]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[7]_i_2__2_n_0\
    );
\txeq_txcoeff[8]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[8]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => \txeq_txcoeff[8]_i_2__2_n_0\,
      O => \txeq_txcoeff[8]_i_1__2_n_0\
    );
\txeq_txcoeff[8]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      I2 => \txeq_txcoeff_reg_n_0_[14]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[8]_i_2__2_n_0\
    );
\txeq_txcoeff[9]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[9]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => \txeq_txcoeff[9]_i_2__2_n_0\,
      O => \txeq_txcoeff[9]_i_1__2_n_0\
    );
\txeq_txcoeff[9]_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[15]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[9]_i_2__2_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4444F444"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => txeq_control_reg2(1),
      I4 => txeq_control_reg2(0),
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[0]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[10]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[11]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[12]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[13]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[14]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[15]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[16]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[17]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[18]_i_2__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[1]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[2]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[3]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[4]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[5]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[6]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[7]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[8]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__2_n_0\,
      D => \txeq_txcoeff[9]_i_1__2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_49 is
  port (
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RXEQ_ADAPT_DONE : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_49 : entity is "PCIeGen1x8If64_pipe_eq";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_49;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_49 is
  signal \FSM_onehot_fsm_tx[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[1]_i_2__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_2__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[5]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_2__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_3__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[4]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[5]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[5]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[6]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[6]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx[0]_i_2__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[0]_i_3__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_2__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_3__3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[2]\ : signal is "yes";
  signal \^user_rxeq_adapt_done\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1__3_n_0\ : STD_LOGIC;
  signal \rxeq_fs__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1__3_n_0\ : STD_LOGIC;
  signal \rxeq_lf__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2__3_n_0\ : STD_LOGIC;
  signal \rxeq_preset__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_preset_valid_reg_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_scan_i_n_5 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_user_en_reg1 : STD_LOGIC;
  signal rxeq_user_en_reg2 : STD_LOGIC;
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \txeq_preset[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[10]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[11]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[12]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[13]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[14]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[15]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[16]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_1__2_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[8]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_preset[9]_i_1__3_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1__3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2__3_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_tx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[4]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[5]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[6]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[2]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
begin
  USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\;
\FSM_onehot_fsm_tx[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF10101050"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx[1]_i_2__3_n_0\,
      I3 => txeq_control_reg2(0),
      I4 => txeq_control_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[1]_i_1__3_n_0\
    );
\FSM_onehot_fsm_tx[1]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[1]_i_2__3_n_0\
    );
\FSM_onehot_fsm_tx[2]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20202F20"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I4 => txeq_preset_done,
      O => \FSM_onehot_fsm_tx[2]_i_1__3_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45454545FF454545"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[3]_i_2__3_n_0\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \FSM_onehot_fsm_tx[3]_i_1__3_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_fsm_tx[3]_i_2__3_n_0\
    );
\FSM_onehot_fsm_tx[4]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[4]_i_1__3_n_0\
    );
\FSM_onehot_fsm_tx[5]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[5]_i_1__3_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAA8"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[6]_i_2__3_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_tx[6]_i_3__3_n_0\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[6]_i_1__3_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBBBBBB8"
    )
        port map (
      I0 => txeq_preset_done,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[6]_i_2__3_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      O => \FSM_onehot_fsm_tx[6]_i_3__3_n_0\
    );
\FSM_onehot_fsm_tx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_tx_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[1]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[2]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[3]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[4]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[5]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[6]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"838183C3"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => rxeq_control_reg2(0),
      O => \FSM_sequential_fsm_rx[0]_i_2__3_n_0\
    );
\FSM_sequential_fsm_rx[0]_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD000080"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => \FSM_sequential_fsm_rx[0]_i_3__3_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_rx[2]_i_2__3_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_3__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeq_control_reg2(0),
      I1 => rxeq_control_reg2(1),
      O => \FSM_sequential_fsm_rx[2]_i_3__3_n_0\
    );
\FSM_sequential_fsm_rx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      S => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_30__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_31__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_32__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_33__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_34__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_35__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_36__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_37__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_38__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_39__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[0]\,
      O => TXPRECURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_40__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtx_channel.gtxe2_channel_i_i_41__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtx_channel.gtxe2_channel_i_i_42__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_43__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_44__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_45__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_46__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \^user_rxeq_adapt_done\,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_5,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_cnt[0]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04041C10"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00424200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0042420042004200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \rxeq_cnt_reg_n_0_[1]\,
      I5 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_fs[0]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C203"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_fs[5]_i_1__3_n_0\
    );
\rxeq_fs[5]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__3_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__3_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__3_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__3_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__3_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__3_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lf[0]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF000000000080FF"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I5 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_lf[5]_i_1__3_n_0\
    );
\rxeq_lf[5]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__3_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__3_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__3_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__3_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__3_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__3_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => RST_CPLLRESET
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_preset[0]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(0),
      I4 => \rxeq_preset[2]_i_2__3_n_0\,
      I5 => \rxeq_preset__0\(0),
      O => \rxeq_preset[0]_i_1__3_n_0\
    );
\rxeq_preset[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(1),
      I4 => \rxeq_preset[2]_i_2__3_n_0\,
      I5 => \rxeq_preset__0\(1),
      O => \rxeq_preset[1]_i_1__3_n_0\
    );
\rxeq_preset[2]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(2),
      I4 => \rxeq_preset[2]_i_2__3_n_0\,
      I5 => \rxeq_preset__0\(2),
      O => \rxeq_preset[2]_i_1__3_n_0\
    );
\rxeq_preset[2]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F00400FF"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => rxeq_control_reg2(0),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_preset[2]_i_2__3_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[0]_i_1__3_n_0\,
      Q => \rxeq_preset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[1]_i_1__3_n_0\,
      Q => \rxeq_preset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[2]_i_1__3_n_0\,
      Q => \rxeq_preset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_valid_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => rxeq_preset_valid
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid,
      Q => rxeq_preset_valid_reg_n_0,
      R => RST_CPLLRESET
    );
rxeq_scan_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_76
     port map (
      D(2) => rxeq_scan_i_n_0,
      D(1) => rxeq_scan_i_n_1,
      D(0) => rxeq_scan_i_n_2,
      \FSM_sequential_fsm_rx_reg[0]\ => \FSM_sequential_fsm_rx[0]_i_2__3_n_0\,
      \FSM_sequential_fsm_rx_reg[2]\(2) => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      \FSM_sequential_fsm_rx_reg[2]\(1) => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      \FSM_sequential_fsm_rx_reg[2]\(0) => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      Q(3 downto 0) => \rxeq_txpreset__0\(3 downto 0),
      RST_CPLLRESET => RST_CPLLRESET,
      USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\,
      \out\(1 downto 0) => rxeq_control_reg2(1 downto 0),
      pclk_sel_reg => pclk_sel_reg,
      rxeq_adapt_done_reg => rxeq_scan_i_n_4,
      rxeq_adapt_done_reg_reg => rxeq_scan_i_n_5,
      rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_reg_n_0,
      \rxeq_cnt_reg[1]\ => \FSM_sequential_fsm_rx[0]_i_3__3_n_0\,
      \rxeq_cnt_reg[1]_0\ => \FSM_sequential_fsm_rx[2]_i_2__3_n_0\,
      \rxeq_control_reg2_reg[0]\ => \FSM_sequential_fsm_rx[2]_i_3__3_n_0\,
      \rxeq_fs_reg[5]\(5 downto 0) => \rxeq_fs__0\(5 downto 0),
      \rxeq_lf_reg[5]\(5 downto 0) => \rxeq_lf__0\(5 downto 0),
      rxeq_new_txcoeff_req_reg => rxeq_scan_i_n_3,
      rxeq_new_txcoeff_req_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \rxeq_preset_reg[2]\(2 downto 0) => \rxeq_preset__0\(2 downto 0),
      rxeq_preset_valid_reg => rxeq_preset_valid_reg_n_0,
      \rxeq_txcoeff_reg[17]\(17) => \rxeq_txcoeff_reg_n_0_[17]\,
      \rxeq_txcoeff_reg[17]\(16) => \rxeq_txcoeff_reg_n_0_[16]\,
      \rxeq_txcoeff_reg[17]\(15) => \rxeq_txcoeff_reg_n_0_[15]\,
      \rxeq_txcoeff_reg[17]\(14) => \rxeq_txcoeff_reg_n_0_[14]\,
      \rxeq_txcoeff_reg[17]\(13) => \rxeq_txcoeff_reg_n_0_[13]\,
      \rxeq_txcoeff_reg[17]\(12) => \rxeq_txcoeff_reg_n_0_[12]\,
      \rxeq_txcoeff_reg[17]\(11) => \rxeq_txcoeff_reg_n_0_[11]\,
      \rxeq_txcoeff_reg[17]\(10) => \rxeq_txcoeff_reg_n_0_[10]\,
      \rxeq_txcoeff_reg[17]\(9) => \rxeq_txcoeff_reg_n_0_[9]\,
      \rxeq_txcoeff_reg[17]\(8) => \rxeq_txcoeff_reg_n_0_[8]\,
      \rxeq_txcoeff_reg[17]\(7) => \rxeq_txcoeff_reg_n_0_[7]\,
      \rxeq_txcoeff_reg[17]\(6) => \rxeq_txcoeff_reg_n_0_[6]\,
      \rxeq_txcoeff_reg[17]\(5 downto 0) => \rxeq_txcoeff__0\(5 downto 0)
    );
\rxeq_txcoeff[0]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[6]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[16]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[17]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(0),
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(1),
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(2),
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(3),
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(4),
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(5),
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[7]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[8]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[9]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[10]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[11]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[12]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[13]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[14]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[15]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(10),
      Q => \rxeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(11),
      Q => \rxeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(12),
      Q => \rxeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(13),
      Q => \rxeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(14),
      Q => \rxeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(15),
      Q => \rxeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(16),
      Q => \rxeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(17),
      Q => \rxeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(6),
      Q => \rxeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(7),
      Q => \rxeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(8),
      Q => \rxeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txcoeff(9),
      Q => \rxeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\rxeq_txpreset[0]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(0),
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(1),
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(2),
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F405"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_txpreset[3]_i_1__3_n_0\
    );
\rxeq_txpreset[3]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(3),
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__3_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset__0\(3),
      R => RST_CPLLRESET
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => RST_CPLLRESET
    );
\txeq_preset[0]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[0]_i_1__3_n_0\
    );
\txeq_preset[10]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEABBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[10]_i_1__3_n_0\
    );
\txeq_preset[11]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[11]_i_1__3_n_0\
    );
\txeq_preset[12]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001574"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[12]_i_1__3_n_0\
    );
\txeq_preset[13]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[13]_i_1__3_n_0\
    );
\txeq_preset[14]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000410"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[14]_i_1__3_n_0\
    );
\txeq_preset[15]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      O => \txeq_preset[15]_i_1__3_n_0\
    );
\txeq_preset[16]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0014"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[16]_i_1__3_n_0\
    );
\txeq_preset[17]_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => RST_CPLLRESET,
      O => \txeq_preset[17]_i_1__2_n_0\
    );
\txeq_preset[17]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[17]_i_2__3_n_0\
    );
\txeq_preset[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[1]_i_1__3_n_0\
    );
\txeq_preset[2]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[2]_i_1__3_n_0\
    );
\txeq_preset[3]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003424"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[3]_i_1__3_n_0\
    );
\txeq_preset[7]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000408"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[7]_i_1__3_n_0\
    );
\txeq_preset[8]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAEBBFB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[8]_i_1__3_n_0\
    );
\txeq_preset[9]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAEBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[9]_i_1__3_n_0\
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      Q => txeq_preset_done,
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[0]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[10]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[11]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[12]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[13]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[14]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[15]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[16]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[17]_i_2__3_n_0\,
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[1]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[2]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[3]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[4]\,
      R => '0'
    );
\txeq_preset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[5]\,
      R => '0'
    );
\txeq_preset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[6]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[7]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[8]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__2_n_0\,
      D => \txeq_preset[9]_i_1__3_n_0\,
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \txeq_preset_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[0]_i_2__3_n_0\,
      O => \txeq_txcoeff[0]_i_1__3_n_0\
    );
\txeq_txcoeff[0]_i_2__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA208A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[0]_i_2__3_n_0\
    );
\txeq_txcoeff[10]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[10]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => \txeq_txcoeff[10]_i_2__3_n_0\,
      O => \txeq_txcoeff[10]_i_1__3_n_0\
    );
\txeq_txcoeff[10]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[16]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[10]_i_2__3_n_0\
    );
\txeq_txcoeff[11]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[11]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[10]\,
      I4 => \txeq_txcoeff[11]_i_2__3_n_0\,
      O => \txeq_txcoeff[11]_i_1__3_n_0\
    );
\txeq_txcoeff[11]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[18]\,
      I2 => \txeq_txcoeff_reg_n_0_[17]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[11]_i_2__3_n_0\
    );
\txeq_txcoeff[12]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[11]\,
      I4 => \txeq_txcoeff[12]_i_2__3_n_0\,
      O => \txeq_txcoeff[12]_i_1__3_n_0\
    );
\txeq_txcoeff[12]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(0),
      I2 => \txeq_txcoeff_reg_n_0_[18]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[12]_i_2__3_n_0\
    );
\txeq_txcoeff[13]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[12]\,
      I4 => \txeq_txcoeff[13]_i_2__3_n_0\,
      O => \txeq_txcoeff[13]_i_1__3_n_0\
    );
\txeq_txcoeff[13]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(1),
      I2 => txeq_deemph_reg2(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[13]_i_2__3_n_0\
    );
\txeq_txcoeff[14]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => \txeq_txcoeff[14]_i_2__3_n_0\,
      O => \txeq_txcoeff[14]_i_1__3_n_0\
    );
\txeq_txcoeff[14]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[14]_i_2__3_n_0\
    );
\txeq_txcoeff[15]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[15]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => \txeq_txcoeff[15]_i_2__3_n_0\,
      O => \txeq_txcoeff[15]_i_1__3_n_0\
    );
\txeq_txcoeff[15]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(3),
      I2 => txeq_deemph_reg2(2),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[15]_i_2__3_n_0\
    );
\txeq_txcoeff[16]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[16]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => \txeq_txcoeff[16]_i_2__3_n_0\,
      O => \txeq_txcoeff[16]_i_1__3_n_0\
    );
\txeq_txcoeff[16]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(4),
      I2 => txeq_deemph_reg2(3),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[16]_i_2__3_n_0\
    );
\txeq_txcoeff[17]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[17]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => \txeq_txcoeff[17]_i_2__3_n_0\,
      O => \txeq_txcoeff[17]_i_1__3_n_0\
    );
\txeq_txcoeff[17]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(4),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[17]_i_2__3_n_0\
    );
\txeq_txcoeff[18]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557FF5755575557"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[1]_i_2__3_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(0),
      I5 => txeq_control_reg2(1),
      O => \txeq_txcoeff[18]_i_1__3_n_0\
    );
\txeq_txcoeff[18]_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \txeq_txcoeff[18]_i_3__3_n_0\,
      O => \txeq_txcoeff[18]_i_2__3_n_0\
    );
\txeq_txcoeff[18]_i_3__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888F8F888888888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => txeq_deemph_reg2(5),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[18]_i_3__3_n_0\
    );
\txeq_txcoeff[1]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[1]_i_2__3_n_0\,
      O => \txeq_txcoeff[1]_i_1__3_n_0\
    );
\txeq_txcoeff[1]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2__3_n_0\
    );
\txeq_txcoeff[2]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[1]\,
      I4 => \txeq_txcoeff[2]_i_2__3_n_0\,
      O => \txeq_txcoeff[2]_i_1__3_n_0\
    );
\txeq_txcoeff[2]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[8]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[2]_i_2__3_n_0\
    );
\txeq_txcoeff[3]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[2]\,
      I4 => \txeq_txcoeff[3]_i_2__3_n_0\,
      O => \txeq_txcoeff[3]_i_1__3_n_0\
    );
\txeq_txcoeff[3]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff_reg_n_0_[9]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2__3_n_0\
    );
\txeq_txcoeff[4]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[3]\,
      I4 => \txeq_txcoeff[4]_i_2__3_n_0\,
      O => \txeq_txcoeff[4]_i_1__3_n_0\
    );
\txeq_txcoeff[4]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff_reg_n_0_[10]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[4]_i_2__3_n_0\
    );
\txeq_txcoeff[5]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[4]\,
      I4 => \txeq_txcoeff[5]_i_2__3_n_0\,
      O => \txeq_txcoeff[5]_i_1__3_n_0\
    );
\txeq_txcoeff[5]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      I2 => \txeq_txcoeff_reg_n_0_[11]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[5]_i_2__3_n_0\
    );
\txeq_txcoeff[6]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[5]\,
      I4 => \txeq_txcoeff[6]_i_2__3_n_0\,
      O => \txeq_txcoeff[6]_i_1__3_n_0\
    );
\txeq_txcoeff[6]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[12]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[6]_i_2__3_n_0\
    );
\txeq_txcoeff[7]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[7]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff[7]_i_2__3_n_0\,
      O => \txeq_txcoeff[7]_i_1__3_n_0\
    );
\txeq_txcoeff[7]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      I2 => \txeq_txcoeff_reg_n_0_[13]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[7]_i_2__3_n_0\
    );
\txeq_txcoeff[8]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[8]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => \txeq_txcoeff[8]_i_2__3_n_0\,
      O => \txeq_txcoeff[8]_i_1__3_n_0\
    );
\txeq_txcoeff[8]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      I2 => \txeq_txcoeff_reg_n_0_[14]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[8]_i_2__3_n_0\
    );
\txeq_txcoeff[9]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[9]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => \txeq_txcoeff[9]_i_2__3_n_0\,
      O => \txeq_txcoeff[9]_i_1__3_n_0\
    );
\txeq_txcoeff[9]_i_2__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[15]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[9]_i_2__3_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4444F444"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => txeq_control_reg2(1),
      I4 => txeq_control_reg2(0),
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[0]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[10]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[11]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[12]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[13]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[14]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[15]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[16]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[17]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[18]_i_2__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[1]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[2]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[3]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[4]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[5]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[6]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[7]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[8]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__3_n_0\,
      D => \txeq_txcoeff[9]_i_1__3_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_56 is
  port (
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RXEQ_ADAPT_DONE : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_56 : entity is "PCIeGen1x8If64_pipe_eq";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_56;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_56 is
  signal \FSM_onehot_fsm_tx[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[1]_i_2__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_2__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[5]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_1__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_2__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_3__4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[4]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[5]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[5]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[6]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[6]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx[0]_i_2__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[0]_i_3__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_2__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_3__4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[2]\ : signal is "yes";
  signal \^user_rxeq_adapt_done\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1__4_n_0\ : STD_LOGIC;
  signal \rxeq_fs__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1__4_n_0\ : STD_LOGIC;
  signal \rxeq_lf__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2__4_n_0\ : STD_LOGIC;
  signal \rxeq_preset__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_preset_valid_reg_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_scan_i_n_5 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_user_en_reg1 : STD_LOGIC;
  signal rxeq_user_en_reg2 : STD_LOGIC;
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \txeq_preset[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[10]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[11]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[12]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[13]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[14]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[15]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[16]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_1__1_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[8]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_preset[9]_i_1__4_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1__4_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2__4_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_tx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[4]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[5]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[6]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[2]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
begin
  USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\;
\FSM_onehot_fsm_tx[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF10101050"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx[1]_i_2__4_n_0\,
      I3 => txeq_control_reg2(0),
      I4 => txeq_control_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[1]_i_1__4_n_0\
    );
\FSM_onehot_fsm_tx[1]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[1]_i_2__4_n_0\
    );
\FSM_onehot_fsm_tx[2]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20202F20"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I4 => txeq_preset_done,
      O => \FSM_onehot_fsm_tx[2]_i_1__4_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45454545FF454545"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[3]_i_2__4_n_0\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \FSM_onehot_fsm_tx[3]_i_1__4_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_fsm_tx[3]_i_2__4_n_0\
    );
\FSM_onehot_fsm_tx[4]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[4]_i_1__4_n_0\
    );
\FSM_onehot_fsm_tx[5]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[5]_i_1__4_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAA8"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[6]_i_2__4_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_tx[6]_i_3__4_n_0\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[6]_i_1__4_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBBBBBB8"
    )
        port map (
      I0 => txeq_preset_done,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[6]_i_2__4_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      O => \FSM_onehot_fsm_tx[6]_i_3__4_n_0\
    );
\FSM_onehot_fsm_tx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_tx_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[1]_i_1__4_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[2]_i_1__4_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[3]_i_1__4_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[4]_i_1__4_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[5]_i_1__4_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[6]_i_1__4_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"838183C3"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => rxeq_control_reg2(0),
      O => \FSM_sequential_fsm_rx[0]_i_2__4_n_0\
    );
\FSM_sequential_fsm_rx[0]_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD000080"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => \FSM_sequential_fsm_rx[0]_i_3__4_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_rx[2]_i_2__4_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_3__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeq_control_reg2(0),
      I1 => rxeq_control_reg2(1),
      O => \FSM_sequential_fsm_rx[2]_i_3__4_n_0\
    );
\FSM_sequential_fsm_rx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      S => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_30__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_31__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_32__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_33__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_34__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_35__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_36__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_37__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_38__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_39__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[0]\,
      O => TXPRECURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_40__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtx_channel.gtxe2_channel_i_i_41__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtx_channel.gtxe2_channel_i_i_42__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_43__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_44__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_45__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_46__4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \^user_rxeq_adapt_done\,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_5,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_cnt[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04041C10"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00424200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0042420042004200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \rxeq_cnt_reg_n_0_[1]\,
      I5 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_fs[0]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C203"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_fs[5]_i_1__4_n_0\
    );
\rxeq_fs[5]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__4_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__4_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__4_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__4_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__4_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__4_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lf[0]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF000000000080FF"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I5 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_lf[5]_i_1__4_n_0\
    );
\rxeq_lf[5]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__4_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__4_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__4_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__4_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__4_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__4_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => RST_CPLLRESET
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_preset[0]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(0),
      I4 => \rxeq_preset[2]_i_2__4_n_0\,
      I5 => \rxeq_preset__0\(0),
      O => \rxeq_preset[0]_i_1__4_n_0\
    );
\rxeq_preset[1]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(1),
      I4 => \rxeq_preset[2]_i_2__4_n_0\,
      I5 => \rxeq_preset__0\(1),
      O => \rxeq_preset[1]_i_1__4_n_0\
    );
\rxeq_preset[2]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(2),
      I4 => \rxeq_preset[2]_i_2__4_n_0\,
      I5 => \rxeq_preset__0\(2),
      O => \rxeq_preset[2]_i_1__4_n_0\
    );
\rxeq_preset[2]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F00400FF"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => rxeq_control_reg2(0),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_preset[2]_i_2__4_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[0]_i_1__4_n_0\,
      Q => \rxeq_preset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[1]_i_1__4_n_0\,
      Q => \rxeq_preset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[2]_i_1__4_n_0\,
      Q => \rxeq_preset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_valid_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => rxeq_preset_valid
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid,
      Q => rxeq_preset_valid_reg_n_0,
      R => RST_CPLLRESET
    );
rxeq_scan_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_74
     port map (
      D(2) => rxeq_scan_i_n_0,
      D(1) => rxeq_scan_i_n_1,
      D(0) => rxeq_scan_i_n_2,
      \FSM_sequential_fsm_rx_reg[0]\ => \FSM_sequential_fsm_rx[0]_i_2__4_n_0\,
      \FSM_sequential_fsm_rx_reg[2]\(2) => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      \FSM_sequential_fsm_rx_reg[2]\(1) => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      \FSM_sequential_fsm_rx_reg[2]\(0) => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      Q(3 downto 0) => \rxeq_txpreset__0\(3 downto 0),
      RST_CPLLRESET => RST_CPLLRESET,
      USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\,
      \out\(1 downto 0) => rxeq_control_reg2(1 downto 0),
      pclk_sel_reg => pclk_sel_reg,
      rxeq_adapt_done_reg => rxeq_scan_i_n_4,
      rxeq_adapt_done_reg_reg => rxeq_scan_i_n_5,
      rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_reg_n_0,
      \rxeq_cnt_reg[1]\ => \FSM_sequential_fsm_rx[0]_i_3__4_n_0\,
      \rxeq_cnt_reg[1]_0\ => \FSM_sequential_fsm_rx[2]_i_2__4_n_0\,
      \rxeq_control_reg2_reg[0]\ => \FSM_sequential_fsm_rx[2]_i_3__4_n_0\,
      \rxeq_fs_reg[5]\(5 downto 0) => \rxeq_fs__0\(5 downto 0),
      \rxeq_lf_reg[5]\(5 downto 0) => \rxeq_lf__0\(5 downto 0),
      rxeq_new_txcoeff_req_reg => rxeq_scan_i_n_3,
      rxeq_new_txcoeff_req_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \rxeq_preset_reg[2]\(2 downto 0) => \rxeq_preset__0\(2 downto 0),
      rxeq_preset_valid_reg => rxeq_preset_valid_reg_n_0,
      \rxeq_txcoeff_reg[17]\(17) => \rxeq_txcoeff_reg_n_0_[17]\,
      \rxeq_txcoeff_reg[17]\(16) => \rxeq_txcoeff_reg_n_0_[16]\,
      \rxeq_txcoeff_reg[17]\(15) => \rxeq_txcoeff_reg_n_0_[15]\,
      \rxeq_txcoeff_reg[17]\(14) => \rxeq_txcoeff_reg_n_0_[14]\,
      \rxeq_txcoeff_reg[17]\(13) => \rxeq_txcoeff_reg_n_0_[13]\,
      \rxeq_txcoeff_reg[17]\(12) => \rxeq_txcoeff_reg_n_0_[12]\,
      \rxeq_txcoeff_reg[17]\(11) => \rxeq_txcoeff_reg_n_0_[11]\,
      \rxeq_txcoeff_reg[17]\(10) => \rxeq_txcoeff_reg_n_0_[10]\,
      \rxeq_txcoeff_reg[17]\(9) => \rxeq_txcoeff_reg_n_0_[9]\,
      \rxeq_txcoeff_reg[17]\(8) => \rxeq_txcoeff_reg_n_0_[8]\,
      \rxeq_txcoeff_reg[17]\(7) => \rxeq_txcoeff_reg_n_0_[7]\,
      \rxeq_txcoeff_reg[17]\(6) => \rxeq_txcoeff_reg_n_0_[6]\,
      \rxeq_txcoeff_reg[17]\(5 downto 0) => \rxeq_txcoeff__0\(5 downto 0)
    );
\rxeq_txcoeff[0]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[6]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[16]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[17]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(0),
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(1),
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(2),
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(3),
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(4),
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(5),
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[7]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[8]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[9]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[10]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[11]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[12]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[13]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[14]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[15]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(10),
      Q => \rxeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(11),
      Q => \rxeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(12),
      Q => \rxeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(13),
      Q => \rxeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(14),
      Q => \rxeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(15),
      Q => \rxeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(16),
      Q => \rxeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(17),
      Q => \rxeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(6),
      Q => \rxeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(7),
      Q => \rxeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(8),
      Q => \rxeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txcoeff(9),
      Q => \rxeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\rxeq_txpreset[0]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(0),
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(1),
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(2),
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F405"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_txpreset[3]_i_1__4_n_0\
    );
\rxeq_txpreset[3]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(3),
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__4_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset__0\(3),
      R => RST_CPLLRESET
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => RST_CPLLRESET
    );
\txeq_preset[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[0]_i_1__4_n_0\
    );
\txeq_preset[10]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEABBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[10]_i_1__4_n_0\
    );
\txeq_preset[11]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[11]_i_1__4_n_0\
    );
\txeq_preset[12]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001574"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[12]_i_1__4_n_0\
    );
\txeq_preset[13]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[13]_i_1__4_n_0\
    );
\txeq_preset[14]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000410"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[14]_i_1__4_n_0\
    );
\txeq_preset[15]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      O => \txeq_preset[15]_i_1__4_n_0\
    );
\txeq_preset[16]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0014"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[16]_i_1__4_n_0\
    );
\txeq_preset[17]_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => RST_CPLLRESET,
      O => \txeq_preset[17]_i_1__1_n_0\
    );
\txeq_preset[17]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[17]_i_2__4_n_0\
    );
\txeq_preset[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[1]_i_1__4_n_0\
    );
\txeq_preset[2]_i_1__4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[2]_i_1__4_n_0\
    );
\txeq_preset[3]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003424"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[3]_i_1__4_n_0\
    );
\txeq_preset[7]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000408"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[7]_i_1__4_n_0\
    );
\txeq_preset[8]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAEBBFB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[8]_i_1__4_n_0\
    );
\txeq_preset[9]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAEBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[9]_i_1__4_n_0\
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      Q => txeq_preset_done,
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[0]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[10]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[11]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[12]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[13]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[14]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[15]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[16]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[17]_i_2__4_n_0\,
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[1]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[2]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[3]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[4]\,
      R => '0'
    );
\txeq_preset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[5]\,
      R => '0'
    );
\txeq_preset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[6]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[7]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[8]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__1_n_0\,
      D => \txeq_preset[9]_i_1__4_n_0\,
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \txeq_preset_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[0]_i_2__4_n_0\,
      O => \txeq_txcoeff[0]_i_1__4_n_0\
    );
\txeq_txcoeff[0]_i_2__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA208A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[0]_i_2__4_n_0\
    );
\txeq_txcoeff[10]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[10]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => \txeq_txcoeff[10]_i_2__4_n_0\,
      O => \txeq_txcoeff[10]_i_1__4_n_0\
    );
\txeq_txcoeff[10]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[16]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[10]_i_2__4_n_0\
    );
\txeq_txcoeff[11]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[11]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[10]\,
      I4 => \txeq_txcoeff[11]_i_2__4_n_0\,
      O => \txeq_txcoeff[11]_i_1__4_n_0\
    );
\txeq_txcoeff[11]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[18]\,
      I2 => \txeq_txcoeff_reg_n_0_[17]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[11]_i_2__4_n_0\
    );
\txeq_txcoeff[12]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[11]\,
      I4 => \txeq_txcoeff[12]_i_2__4_n_0\,
      O => \txeq_txcoeff[12]_i_1__4_n_0\
    );
\txeq_txcoeff[12]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(0),
      I2 => \txeq_txcoeff_reg_n_0_[18]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[12]_i_2__4_n_0\
    );
\txeq_txcoeff[13]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[12]\,
      I4 => \txeq_txcoeff[13]_i_2__4_n_0\,
      O => \txeq_txcoeff[13]_i_1__4_n_0\
    );
\txeq_txcoeff[13]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(1),
      I2 => txeq_deemph_reg2(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[13]_i_2__4_n_0\
    );
\txeq_txcoeff[14]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => \txeq_txcoeff[14]_i_2__4_n_0\,
      O => \txeq_txcoeff[14]_i_1__4_n_0\
    );
\txeq_txcoeff[14]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[14]_i_2__4_n_0\
    );
\txeq_txcoeff[15]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[15]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => \txeq_txcoeff[15]_i_2__4_n_0\,
      O => \txeq_txcoeff[15]_i_1__4_n_0\
    );
\txeq_txcoeff[15]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(3),
      I2 => txeq_deemph_reg2(2),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[15]_i_2__4_n_0\
    );
\txeq_txcoeff[16]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[16]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => \txeq_txcoeff[16]_i_2__4_n_0\,
      O => \txeq_txcoeff[16]_i_1__4_n_0\
    );
\txeq_txcoeff[16]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(4),
      I2 => txeq_deemph_reg2(3),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[16]_i_2__4_n_0\
    );
\txeq_txcoeff[17]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[17]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => \txeq_txcoeff[17]_i_2__4_n_0\,
      O => \txeq_txcoeff[17]_i_1__4_n_0\
    );
\txeq_txcoeff[17]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(4),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[17]_i_2__4_n_0\
    );
\txeq_txcoeff[18]_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557FF5755575557"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[1]_i_2__4_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(0),
      I5 => txeq_control_reg2(1),
      O => \txeq_txcoeff[18]_i_1__4_n_0\
    );
\txeq_txcoeff[18]_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \txeq_txcoeff[18]_i_3__4_n_0\,
      O => \txeq_txcoeff[18]_i_2__4_n_0\
    );
\txeq_txcoeff[18]_i_3__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888F8F888888888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => txeq_deemph_reg2(5),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[18]_i_3__4_n_0\
    );
\txeq_txcoeff[1]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[1]_i_2__4_n_0\,
      O => \txeq_txcoeff[1]_i_1__4_n_0\
    );
\txeq_txcoeff[1]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2__4_n_0\
    );
\txeq_txcoeff[2]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[1]\,
      I4 => \txeq_txcoeff[2]_i_2__4_n_0\,
      O => \txeq_txcoeff[2]_i_1__4_n_0\
    );
\txeq_txcoeff[2]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[8]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[2]_i_2__4_n_0\
    );
\txeq_txcoeff[3]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[2]\,
      I4 => \txeq_txcoeff[3]_i_2__4_n_0\,
      O => \txeq_txcoeff[3]_i_1__4_n_0\
    );
\txeq_txcoeff[3]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff_reg_n_0_[9]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2__4_n_0\
    );
\txeq_txcoeff[4]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[3]\,
      I4 => \txeq_txcoeff[4]_i_2__4_n_0\,
      O => \txeq_txcoeff[4]_i_1__4_n_0\
    );
\txeq_txcoeff[4]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff_reg_n_0_[10]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[4]_i_2__4_n_0\
    );
\txeq_txcoeff[5]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[4]\,
      I4 => \txeq_txcoeff[5]_i_2__4_n_0\,
      O => \txeq_txcoeff[5]_i_1__4_n_0\
    );
\txeq_txcoeff[5]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      I2 => \txeq_txcoeff_reg_n_0_[11]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[5]_i_2__4_n_0\
    );
\txeq_txcoeff[6]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[5]\,
      I4 => \txeq_txcoeff[6]_i_2__4_n_0\,
      O => \txeq_txcoeff[6]_i_1__4_n_0\
    );
\txeq_txcoeff[6]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[12]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[6]_i_2__4_n_0\
    );
\txeq_txcoeff[7]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[7]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff[7]_i_2__4_n_0\,
      O => \txeq_txcoeff[7]_i_1__4_n_0\
    );
\txeq_txcoeff[7]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      I2 => \txeq_txcoeff_reg_n_0_[13]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[7]_i_2__4_n_0\
    );
\txeq_txcoeff[8]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[8]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => \txeq_txcoeff[8]_i_2__4_n_0\,
      O => \txeq_txcoeff[8]_i_1__4_n_0\
    );
\txeq_txcoeff[8]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      I2 => \txeq_txcoeff_reg_n_0_[14]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[8]_i_2__4_n_0\
    );
\txeq_txcoeff[9]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[9]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => \txeq_txcoeff[9]_i_2__4_n_0\,
      O => \txeq_txcoeff[9]_i_1__4_n_0\
    );
\txeq_txcoeff[9]_i_2__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[15]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[9]_i_2__4_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4444F444"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => txeq_control_reg2(1),
      I4 => txeq_control_reg2(0),
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[0]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[10]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[11]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[12]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[13]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[14]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[15]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[16]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[17]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[18]_i_2__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[1]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[2]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[3]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[4]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[5]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[6]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[7]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[8]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__4_n_0\,
      D => \txeq_txcoeff[9]_i_1__4_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_62 is
  port (
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RXEQ_ADAPT_DONE : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    rate_gen3 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_62 : entity is "PCIeGen1x8If64_pipe_eq";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_62;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_62 is
  signal \FSM_onehot_fsm_tx[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[1]_i_2__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_2__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[5]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_1__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_2__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_3__5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[4]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[5]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[5]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[6]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[6]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx[0]_i_2__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[0]_i_3__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_2__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_3__5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[2]\ : signal is "yes";
  signal \^user_rxeq_adapt_done\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1__5_n_0\ : STD_LOGIC;
  signal \rxeq_fs__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1__5_n_0\ : STD_LOGIC;
  signal \rxeq_lf__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2__5_n_0\ : STD_LOGIC;
  signal \rxeq_preset__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_preset_valid_reg_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_scan_i_n_5 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_user_en_reg1 : STD_LOGIC;
  signal rxeq_user_en_reg2 : STD_LOGIC;
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \txeq_preset[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[10]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[11]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[12]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[13]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[14]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[15]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[16]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[8]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_preset[9]_i_1__5_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1__5_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2__5_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_tx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[4]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[5]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[6]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[2]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
begin
  USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\;
\FSM_onehot_fsm_tx[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF10101050"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx[1]_i_2__5_n_0\,
      I3 => txeq_control_reg2(0),
      I4 => txeq_control_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[1]_i_1__5_n_0\
    );
\FSM_onehot_fsm_tx[1]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[1]_i_2__5_n_0\
    );
\FSM_onehot_fsm_tx[2]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20202F20"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I4 => txeq_preset_done,
      O => \FSM_onehot_fsm_tx[2]_i_1__5_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45454545FF454545"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[3]_i_2__5_n_0\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \FSM_onehot_fsm_tx[3]_i_1__5_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_fsm_tx[3]_i_2__5_n_0\
    );
\FSM_onehot_fsm_tx[4]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[4]_i_1__5_n_0\
    );
\FSM_onehot_fsm_tx[5]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[5]_i_1__5_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAA8"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[6]_i_2__5_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_tx[6]_i_3__5_n_0\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[6]_i_1__5_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBBBBBB8"
    )
        port map (
      I0 => txeq_preset_done,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[6]_i_2__5_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      O => \FSM_onehot_fsm_tx[6]_i_3__5_n_0\
    );
\FSM_onehot_fsm_tx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_tx_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[1]_i_1__5_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[2]_i_1__5_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[3]_i_1__5_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[4]_i_1__5_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[5]_i_1__5_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[6]_i_1__5_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"838183C3"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => rxeq_control_reg2(0),
      O => \FSM_sequential_fsm_rx[0]_i_2__5_n_0\
    );
\FSM_sequential_fsm_rx[0]_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD000080"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => \FSM_sequential_fsm_rx[0]_i_3__5_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_rx[2]_i_2__5_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_3__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeq_control_reg2(0),
      I1 => rxeq_control_reg2(1),
      O => \FSM_sequential_fsm_rx[2]_i_3__5_n_0\
    );
\FSM_sequential_fsm_rx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      S => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rate_gen3(0),
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_31__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_32__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_33__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_34__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_35__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_36__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_37__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_38__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_39__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_40__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[0]\,
      O => TXPRECURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_41__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtx_channel.gtxe2_channel_i_i_42__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtx_channel.gtxe2_channel_i_i_43__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_44__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_45__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_46__5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_47__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \^user_rxeq_adapt_done\,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_5,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_cnt[0]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04041C10"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00424200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0042420042004200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \rxeq_cnt_reg_n_0_[1]\,
      I5 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_fs[0]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C203"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_fs[5]_i_1__5_n_0\
    );
\rxeq_fs[5]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__5_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__5_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__5_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__5_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__5_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__5_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lf[0]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF000000000080FF"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I5 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_lf[5]_i_1__5_n_0\
    );
\rxeq_lf[5]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__5_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__5_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__5_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__5_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__5_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__5_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => RST_CPLLRESET
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_preset[0]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(0),
      I4 => \rxeq_preset[2]_i_2__5_n_0\,
      I5 => \rxeq_preset__0\(0),
      O => \rxeq_preset[0]_i_1__5_n_0\
    );
\rxeq_preset[1]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(1),
      I4 => \rxeq_preset[2]_i_2__5_n_0\,
      I5 => \rxeq_preset__0\(1),
      O => \rxeq_preset[1]_i_1__5_n_0\
    );
\rxeq_preset[2]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(2),
      I4 => \rxeq_preset[2]_i_2__5_n_0\,
      I5 => \rxeq_preset__0\(2),
      O => \rxeq_preset[2]_i_1__5_n_0\
    );
\rxeq_preset[2]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F00400FF"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => rxeq_control_reg2(0),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_preset[2]_i_2__5_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[0]_i_1__5_n_0\,
      Q => \rxeq_preset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[1]_i_1__5_n_0\,
      Q => \rxeq_preset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[2]_i_1__5_n_0\,
      Q => \rxeq_preset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_valid_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => rxeq_preset_valid
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid,
      Q => rxeq_preset_valid_reg_n_0,
      R => RST_CPLLRESET
    );
rxeq_scan_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_72
     port map (
      D(2) => rxeq_scan_i_n_0,
      D(1) => rxeq_scan_i_n_1,
      D(0) => rxeq_scan_i_n_2,
      \FSM_sequential_fsm_rx_reg[0]\ => \FSM_sequential_fsm_rx[0]_i_2__5_n_0\,
      \FSM_sequential_fsm_rx_reg[2]\(2) => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      \FSM_sequential_fsm_rx_reg[2]\(1) => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      \FSM_sequential_fsm_rx_reg[2]\(0) => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      Q(3 downto 0) => \rxeq_txpreset__0\(3 downto 0),
      RST_CPLLRESET => RST_CPLLRESET,
      USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\,
      \out\(1 downto 0) => rxeq_control_reg2(1 downto 0),
      pclk_sel_reg => pclk_sel_reg,
      rxeq_adapt_done_reg => rxeq_scan_i_n_4,
      rxeq_adapt_done_reg_reg => rxeq_scan_i_n_5,
      rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_reg_n_0,
      \rxeq_cnt_reg[1]\ => \FSM_sequential_fsm_rx[0]_i_3__5_n_0\,
      \rxeq_cnt_reg[1]_0\ => \FSM_sequential_fsm_rx[2]_i_2__5_n_0\,
      \rxeq_control_reg2_reg[0]\ => \FSM_sequential_fsm_rx[2]_i_3__5_n_0\,
      \rxeq_fs_reg[5]\(5 downto 0) => \rxeq_fs__0\(5 downto 0),
      \rxeq_lf_reg[5]\(5 downto 0) => \rxeq_lf__0\(5 downto 0),
      rxeq_new_txcoeff_req_reg => rxeq_scan_i_n_3,
      rxeq_new_txcoeff_req_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \rxeq_preset_reg[2]\(2 downto 0) => \rxeq_preset__0\(2 downto 0),
      rxeq_preset_valid_reg => rxeq_preset_valid_reg_n_0,
      \rxeq_txcoeff_reg[17]\(17) => \rxeq_txcoeff_reg_n_0_[17]\,
      \rxeq_txcoeff_reg[17]\(16) => \rxeq_txcoeff_reg_n_0_[16]\,
      \rxeq_txcoeff_reg[17]\(15) => \rxeq_txcoeff_reg_n_0_[15]\,
      \rxeq_txcoeff_reg[17]\(14) => \rxeq_txcoeff_reg_n_0_[14]\,
      \rxeq_txcoeff_reg[17]\(13) => \rxeq_txcoeff_reg_n_0_[13]\,
      \rxeq_txcoeff_reg[17]\(12) => \rxeq_txcoeff_reg_n_0_[12]\,
      \rxeq_txcoeff_reg[17]\(11) => \rxeq_txcoeff_reg_n_0_[11]\,
      \rxeq_txcoeff_reg[17]\(10) => \rxeq_txcoeff_reg_n_0_[10]\,
      \rxeq_txcoeff_reg[17]\(9) => \rxeq_txcoeff_reg_n_0_[9]\,
      \rxeq_txcoeff_reg[17]\(8) => \rxeq_txcoeff_reg_n_0_[8]\,
      \rxeq_txcoeff_reg[17]\(7) => \rxeq_txcoeff_reg_n_0_[7]\,
      \rxeq_txcoeff_reg[17]\(6) => \rxeq_txcoeff_reg_n_0_[6]\,
      \rxeq_txcoeff_reg[17]\(5 downto 0) => \rxeq_txcoeff__0\(5 downto 0)
    );
\rxeq_txcoeff[0]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[6]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[16]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[17]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(0),
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(1),
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(2),
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(3),
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(4),
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(5),
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[7]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[8]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[9]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[10]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[11]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[12]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[13]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[14]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[15]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(10),
      Q => \rxeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(11),
      Q => \rxeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(12),
      Q => \rxeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(13),
      Q => \rxeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(14),
      Q => \rxeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(15),
      Q => \rxeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(16),
      Q => \rxeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(17),
      Q => \rxeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(6),
      Q => \rxeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(7),
      Q => \rxeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(8),
      Q => \rxeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txcoeff(9),
      Q => \rxeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\rxeq_txpreset[0]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(0),
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(1),
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(2),
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F405"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_txpreset[3]_i_1__5_n_0\
    );
\rxeq_txpreset[3]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(3),
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__5_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset__0\(3),
      R => RST_CPLLRESET
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => RST_CPLLRESET
    );
\txeq_preset[0]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[0]_i_1__5_n_0\
    );
\txeq_preset[10]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEABBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[10]_i_1__5_n_0\
    );
\txeq_preset[11]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[11]_i_1__5_n_0\
    );
\txeq_preset[12]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001574"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[12]_i_1__5_n_0\
    );
\txeq_preset[13]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[13]_i_1__5_n_0\
    );
\txeq_preset[14]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000410"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[14]_i_1__5_n_0\
    );
\txeq_preset[15]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      O => \txeq_preset[15]_i_1__5_n_0\
    );
\txeq_preset[16]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0014"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[16]_i_1__5_n_0\
    );
\txeq_preset[17]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => RST_CPLLRESET,
      O => \txeq_preset[17]_i_1__0_n_0\
    );
\txeq_preset[17]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[17]_i_2__5_n_0\
    );
\txeq_preset[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[1]_i_1__5_n_0\
    );
\txeq_preset[2]_i_1__5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[2]_i_1__5_n_0\
    );
\txeq_preset[3]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003424"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[3]_i_1__5_n_0\
    );
\txeq_preset[7]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000408"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[7]_i_1__5_n_0\
    );
\txeq_preset[8]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAEBBFB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[8]_i_1__5_n_0\
    );
\txeq_preset[9]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAEBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[9]_i_1__5_n_0\
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      Q => txeq_preset_done,
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[0]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[10]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[11]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[12]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[13]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[14]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[15]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[16]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[17]_i_2__5_n_0\,
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[1]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[2]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[3]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[4]\,
      R => '0'
    );
\txeq_preset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[5]\,
      R => '0'
    );
\txeq_preset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[6]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[7]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[8]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[9]_i_1__5_n_0\,
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \txeq_preset_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[0]_i_2__5_n_0\,
      O => \txeq_txcoeff[0]_i_1__5_n_0\
    );
\txeq_txcoeff[0]_i_2__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA208A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[0]_i_2__5_n_0\
    );
\txeq_txcoeff[10]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[10]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => \txeq_txcoeff[10]_i_2__5_n_0\,
      O => \txeq_txcoeff[10]_i_1__5_n_0\
    );
\txeq_txcoeff[10]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[16]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[10]_i_2__5_n_0\
    );
\txeq_txcoeff[11]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[11]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[10]\,
      I4 => \txeq_txcoeff[11]_i_2__5_n_0\,
      O => \txeq_txcoeff[11]_i_1__5_n_0\
    );
\txeq_txcoeff[11]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[18]\,
      I2 => \txeq_txcoeff_reg_n_0_[17]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[11]_i_2__5_n_0\
    );
\txeq_txcoeff[12]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[11]\,
      I4 => \txeq_txcoeff[12]_i_2__5_n_0\,
      O => \txeq_txcoeff[12]_i_1__5_n_0\
    );
\txeq_txcoeff[12]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(0),
      I2 => \txeq_txcoeff_reg_n_0_[18]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[12]_i_2__5_n_0\
    );
\txeq_txcoeff[13]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[12]\,
      I4 => \txeq_txcoeff[13]_i_2__5_n_0\,
      O => \txeq_txcoeff[13]_i_1__5_n_0\
    );
\txeq_txcoeff[13]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(1),
      I2 => txeq_deemph_reg2(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[13]_i_2__5_n_0\
    );
\txeq_txcoeff[14]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => \txeq_txcoeff[14]_i_2__5_n_0\,
      O => \txeq_txcoeff[14]_i_1__5_n_0\
    );
\txeq_txcoeff[14]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[14]_i_2__5_n_0\
    );
\txeq_txcoeff[15]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[15]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => \txeq_txcoeff[15]_i_2__5_n_0\,
      O => \txeq_txcoeff[15]_i_1__5_n_0\
    );
\txeq_txcoeff[15]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(3),
      I2 => txeq_deemph_reg2(2),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[15]_i_2__5_n_0\
    );
\txeq_txcoeff[16]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[16]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => \txeq_txcoeff[16]_i_2__5_n_0\,
      O => \txeq_txcoeff[16]_i_1__5_n_0\
    );
\txeq_txcoeff[16]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(4),
      I2 => txeq_deemph_reg2(3),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[16]_i_2__5_n_0\
    );
\txeq_txcoeff[17]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[17]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => \txeq_txcoeff[17]_i_2__5_n_0\,
      O => \txeq_txcoeff[17]_i_1__5_n_0\
    );
\txeq_txcoeff[17]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(4),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[17]_i_2__5_n_0\
    );
\txeq_txcoeff[18]_i_1__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557FF5755575557"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[1]_i_2__5_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(0),
      I5 => txeq_control_reg2(1),
      O => \txeq_txcoeff[18]_i_1__5_n_0\
    );
\txeq_txcoeff[18]_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \txeq_txcoeff[18]_i_3__5_n_0\,
      O => \txeq_txcoeff[18]_i_2__5_n_0\
    );
\txeq_txcoeff[18]_i_3__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888F8F888888888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => txeq_deemph_reg2(5),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[18]_i_3__5_n_0\
    );
\txeq_txcoeff[1]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[1]_i_2__5_n_0\,
      O => \txeq_txcoeff[1]_i_1__5_n_0\
    );
\txeq_txcoeff[1]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2__5_n_0\
    );
\txeq_txcoeff[2]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[1]\,
      I4 => \txeq_txcoeff[2]_i_2__5_n_0\,
      O => \txeq_txcoeff[2]_i_1__5_n_0\
    );
\txeq_txcoeff[2]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[8]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[2]_i_2__5_n_0\
    );
\txeq_txcoeff[3]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[2]\,
      I4 => \txeq_txcoeff[3]_i_2__5_n_0\,
      O => \txeq_txcoeff[3]_i_1__5_n_0\
    );
\txeq_txcoeff[3]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff_reg_n_0_[9]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2__5_n_0\
    );
\txeq_txcoeff[4]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[3]\,
      I4 => \txeq_txcoeff[4]_i_2__5_n_0\,
      O => \txeq_txcoeff[4]_i_1__5_n_0\
    );
\txeq_txcoeff[4]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff_reg_n_0_[10]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[4]_i_2__5_n_0\
    );
\txeq_txcoeff[5]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[4]\,
      I4 => \txeq_txcoeff[5]_i_2__5_n_0\,
      O => \txeq_txcoeff[5]_i_1__5_n_0\
    );
\txeq_txcoeff[5]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      I2 => \txeq_txcoeff_reg_n_0_[11]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[5]_i_2__5_n_0\
    );
\txeq_txcoeff[6]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[5]\,
      I4 => \txeq_txcoeff[6]_i_2__5_n_0\,
      O => \txeq_txcoeff[6]_i_1__5_n_0\
    );
\txeq_txcoeff[6]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[12]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[6]_i_2__5_n_0\
    );
\txeq_txcoeff[7]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[7]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff[7]_i_2__5_n_0\,
      O => \txeq_txcoeff[7]_i_1__5_n_0\
    );
\txeq_txcoeff[7]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      I2 => \txeq_txcoeff_reg_n_0_[13]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[7]_i_2__5_n_0\
    );
\txeq_txcoeff[8]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[8]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => \txeq_txcoeff[8]_i_2__5_n_0\,
      O => \txeq_txcoeff[8]_i_1__5_n_0\
    );
\txeq_txcoeff[8]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      I2 => \txeq_txcoeff_reg_n_0_[14]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[8]_i_2__5_n_0\
    );
\txeq_txcoeff[9]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[9]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => \txeq_txcoeff[9]_i_2__5_n_0\,
      O => \txeq_txcoeff[9]_i_1__5_n_0\
    );
\txeq_txcoeff[9]_i_2__5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[15]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[9]_i_2__5_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4444F444"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => txeq_control_reg2(1),
      I4 => txeq_control_reg2(0),
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[0]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[10]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[11]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[12]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[13]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[14]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[15]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[16]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[17]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[18]_i_2__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[1]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[2]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[3]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[4]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[5]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[6]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[7]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[8]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__5_n_0\,
      D => \txeq_txcoeff[9]_i_1__5_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_68 is
  port (
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    USER_RXEQ_ADAPT_DONE : out STD_LOGIC;
    RST_CPLLRESET : in STD_LOGIC;
    pclk_sel_reg : in STD_LOGIC;
    gen3_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_68 : entity is "PCIeGen1x8If64_pipe_eq";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_68;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_68 is
  signal \FSM_onehot_fsm_tx[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[1]_i_2__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[3]_i_2__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[5]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_1__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_2__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx[6]_i_3__6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_tx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[2]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[3]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[3]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[4]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[4]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[5]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[5]\ : signal is "yes";
  signal \FSM_onehot_fsm_tx_reg_n_0_[6]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_onehot_fsm_tx_reg_n_0_[6]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx[0]_i_2__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[0]_i_3__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_2__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx[2]_i_3__6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_rx_reg_n_0_[0]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[0]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[1]\ : signal is "yes";
  signal \FSM_sequential_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  attribute RTL_KEEP of \FSM_sequential_fsm_rx_reg_n_0_[2]\ : signal is "yes";
  signal \^user_rxeq_adapt_done\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  signal gen3_reg2 : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1__6_n_0\ : STD_LOGIC;
  signal \rxeq_fs__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1__6_n_0\ : STD_LOGIC;
  signal \rxeq_lf__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2__6_n_0\ : STD_LOGIC;
  signal \rxeq_preset__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_preset_valid_reg_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_scan_i_n_5 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxeq_user_en_reg1 : STD_LOGIC;
  signal rxeq_user_en_reg2 : STD_LOGIC;
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \txeq_preset[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[10]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[11]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[12]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[13]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[14]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[15]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[16]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[17]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[8]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_preset[9]_i_1__6_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1__6_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2__6_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute KEEP : string;
  attribute KEEP of \FSM_onehot_fsm_tx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[2]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[3]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[4]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[5]\ : label is "yes";
  attribute KEEP of \FSM_onehot_fsm_tx_reg[6]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[0]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[1]\ : label is "yes";
  attribute KEEP of \FSM_sequential_fsm_rx_reg[2]\ : label is "yes";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute ASYNC_REG of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute ASYNC_REG of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute ASYNC_REG of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute ASYNC_REG of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute ASYNC_REG of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
begin
  USER_RXEQ_ADAPT_DONE <= \^user_rxeq_adapt_done\;
\FSM_onehot_fsm_tx[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FF10101050"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx[1]_i_2__6_n_0\,
      I3 => txeq_control_reg2(0),
      I4 => txeq_control_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[1]_i_1__6_n_0\
    );
\FSM_onehot_fsm_tx[1]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[1]_i_2__6_n_0\
    );
\FSM_onehot_fsm_tx[2]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20202F20"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I4 => txeq_preset_done,
      O => \FSM_onehot_fsm_tx[2]_i_1__6_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45454545FF454545"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[3]_i_2__6_n_0\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \FSM_onehot_fsm_tx[3]_i_1__6_n_0\
    );
\FSM_onehot_fsm_tx[3]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      O => \FSM_onehot_fsm_tx[3]_i_2__6_n_0\
    );
\FSM_onehot_fsm_tx[4]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000200"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[4]_i_1__6_n_0\
    );
\FSM_onehot_fsm_tx[5]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[5]_i_1__6_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAA8"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[6]_i_2__6_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I4 => \FSM_onehot_fsm_tx[6]_i_3__6_n_0\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \FSM_onehot_fsm_tx[6]_i_1__6_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88888888BBBBBBB8"
    )
        port map (
      I0 => txeq_preset_done,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I4 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_tx[6]_i_2__6_n_0\
    );
\FSM_onehot_fsm_tx[6]_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      O => \FSM_onehot_fsm_tx[6]_i_3__6_n_0\
    );
\FSM_onehot_fsm_tx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => \FSM_onehot_fsm_tx_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[1]_i_1__6_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      S => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[2]_i_1__6_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[3]_i_1__6_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[4]_i_1__6_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[5]_i_1__6_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\FSM_onehot_fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx[6]_i_1__6_n_0\,
      Q => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx[0]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"838183C3"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => rxeq_control_reg2(0),
      O => \FSM_sequential_fsm_rx[0]_i_2__6_n_0\
    );
\FSM_sequential_fsm_rx[0]_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD000080"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => \FSM_sequential_fsm_rx[0]_i_3__6_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_rx[2]_i_2__6_n_0\
    );
\FSM_sequential_fsm_rx[2]_i_3__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rxeq_control_reg2(0),
      I1 => rxeq_control_reg2(1),
      O => \FSM_sequential_fsm_rx[2]_i_3__6_n_0\
    );
\FSM_sequential_fsm_rx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      S => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\FSM_sequential_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg(0),
      Q => gen3_reg1,
      R => RST_CPLLRESET
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST_CPLLRESET
    );
\gtx_channel.gtxe2_channel_i_i_31__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_32__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_33__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_34__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_35__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_36__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_37__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_38__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_39__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_40__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[0]\,
      O => TXPRECURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_41__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtx_channel.gtxe2_channel_i_i_42__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtx_channel.gtxe2_channel_i_i_43__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_44__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_45__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_46__6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_47__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \^user_rxeq_adapt_done\,
      R => RST_CPLLRESET
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_5,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_cnt[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04041C10"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I3 => rxeq_control_reg2(1),
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00424200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0042420042004200"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \rxeq_cnt_reg_n_0_[1]\,
      I5 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_fs[0]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C203"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_fs[5]_i_1__6_n_0\
    );
\rxeq_fs[5]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__6_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__6_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__6_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__6_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__6_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_fs[5]_i_1__6_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lf[0]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF000000000080FF"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I5 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_lf[5]_i_1__6_n_0\
    );
\rxeq_lf[5]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__6_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__6_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__6_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__6_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__6_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_lf[5]_i_1__6_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => RST_CPLLRESET
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => RST_CPLLRESET
    );
\rxeq_preset[0]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(0),
      I4 => \rxeq_preset[2]_i_2__6_n_0\,
      I5 => \rxeq_preset__0\(0),
      O => \rxeq_preset[0]_i_1__6_n_0\
    );
\rxeq_preset[1]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(1),
      I4 => \rxeq_preset[2]_i_2__6_n_0\,
      I5 => \rxeq_preset__0\(1),
      O => \rxeq_preset[1]_i_1__6_n_0\
    );
\rxeq_preset[2]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3200FFFF32000000"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_preset_reg2(2),
      I4 => \rxeq_preset[2]_i_2__6_n_0\,
      I5 => \rxeq_preset__0\(2),
      O => \rxeq_preset[2]_i_1__6_n_0\
    );
\rxeq_preset[2]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F00400FF"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => rxeq_control_reg2(0),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I4 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_preset[2]_i_2__6_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[0]_i_1__6_n_0\,
      Q => \rxeq_preset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[1]_i_1__6_n_0\,
      Q => \rxeq_preset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \rxeq_preset[2]_i_1__6_n_0\,
      Q => \rxeq_preset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_preset_valid_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => rxeq_preset_valid
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_preset_valid,
      Q => rxeq_preset_valid_reg_n_0,
      R => RST_CPLLRESET
    );
rxeq_scan_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan
     port map (
      D(2) => rxeq_scan_i_n_0,
      D(1) => rxeq_scan_i_n_1,
      D(0) => rxeq_scan_i_n_2,
      \FSM_sequential_fsm_rx_reg[0]\ => \FSM_sequential_fsm_rx[0]_i_2__6_n_0\,
      \FSM_sequential_fsm_rx_reg[2]\(2) => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      \FSM_sequential_fsm_rx_reg[2]\(1) => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      \FSM_sequential_fsm_rx_reg[2]\(0) => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      Q(3 downto 0) => \rxeq_txpreset__0\(3 downto 0),
      RST_CPLLRESET => RST_CPLLRESET,
      USER_RXEQ_ADAPT_DONE => \^user_rxeq_adapt_done\,
      \out\(1 downto 0) => rxeq_control_reg2(1 downto 0),
      pclk_sel_reg => pclk_sel_reg,
      rxeq_adapt_done_reg => rxeq_scan_i_n_4,
      rxeq_adapt_done_reg_reg => rxeq_scan_i_n_5,
      rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_reg_n_0,
      \rxeq_cnt_reg[1]\ => \FSM_sequential_fsm_rx[0]_i_3__6_n_0\,
      \rxeq_cnt_reg[1]_0\ => \FSM_sequential_fsm_rx[2]_i_2__6_n_0\,
      \rxeq_control_reg2_reg[0]\ => \FSM_sequential_fsm_rx[2]_i_3__6_n_0\,
      \rxeq_fs_reg[5]\(5 downto 0) => \rxeq_fs__0\(5 downto 0),
      \rxeq_lf_reg[5]\(5 downto 0) => \rxeq_lf__0\(5 downto 0),
      rxeq_new_txcoeff_req_reg => rxeq_scan_i_n_3,
      rxeq_new_txcoeff_req_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \rxeq_preset_reg[2]\(2 downto 0) => \rxeq_preset__0\(2 downto 0),
      rxeq_preset_valid_reg => rxeq_preset_valid_reg_n_0,
      \rxeq_txcoeff_reg[17]\(17) => \rxeq_txcoeff_reg_n_0_[17]\,
      \rxeq_txcoeff_reg[17]\(16) => \rxeq_txcoeff_reg_n_0_[16]\,
      \rxeq_txcoeff_reg[17]\(15) => \rxeq_txcoeff_reg_n_0_[15]\,
      \rxeq_txcoeff_reg[17]\(14) => \rxeq_txcoeff_reg_n_0_[14]\,
      \rxeq_txcoeff_reg[17]\(13) => \rxeq_txcoeff_reg_n_0_[13]\,
      \rxeq_txcoeff_reg[17]\(12) => \rxeq_txcoeff_reg_n_0_[12]\,
      \rxeq_txcoeff_reg[17]\(11) => \rxeq_txcoeff_reg_n_0_[11]\,
      \rxeq_txcoeff_reg[17]\(10) => \rxeq_txcoeff_reg_n_0_[10]\,
      \rxeq_txcoeff_reg[17]\(9) => \rxeq_txcoeff_reg_n_0_[9]\,
      \rxeq_txcoeff_reg[17]\(8) => \rxeq_txcoeff_reg_n_0_[8]\,
      \rxeq_txcoeff_reg[17]\(7) => \rxeq_txcoeff_reg_n_0_[7]\,
      \rxeq_txcoeff_reg[17]\(6) => \rxeq_txcoeff_reg_n_0_[6]\,
      \rxeq_txcoeff_reg[17]\(5 downto 0) => \rxeq_txcoeff__0\(5 downto 0)
    );
\rxeq_txcoeff[0]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[6]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[16]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[17]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(0),
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(1),
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(2),
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(3),
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(4),
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => txeq_deemph_reg2(5),
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[7]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[8]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[9]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[10]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[11]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[12]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[13]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[14]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => \rxeq_txcoeff_reg_n_0_[15]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(10),
      Q => \rxeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(11),
      Q => \rxeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(12),
      Q => \rxeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(13),
      Q => \rxeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(14),
      Q => \rxeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(15),
      Q => \rxeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(16),
      Q => \rxeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(17),
      Q => \rxeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff__0\(3),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff__0\(4),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff__0\(5),
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(6),
      Q => \rxeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(7),
      Q => \rxeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(8),
      Q => \rxeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txcoeff(9),
      Q => \rxeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
\rxeq_txpreset[0]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(0),
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(1),
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(2),
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F405"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => rxeq_control_reg2(1),
      I2 => \FSM_sequential_fsm_rx_reg_n_0_[1]\,
      I3 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      O => \rxeq_txpreset[3]_i_1__6_n_0\
    );
\rxeq_txpreset[3]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \FSM_sequential_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_sequential_fsm_rx_reg_n_0_[0]\,
      I2 => rxeq_txpreset_reg2(3),
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset__0\(0),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset__0\(1),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset__0\(2),
      R => RST_CPLLRESET
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \rxeq_txpreset[3]_i_1__6_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset__0\(3),
      R => RST_CPLLRESET
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => RST_CPLLRESET
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => RST_CPLLRESET
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => RST_CPLLRESET
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => RST_CPLLRESET
    );
\txeq_preset[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[0]_i_1__6_n_0\
    );
\txeq_preset[10]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEABBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[10]_i_1__6_n_0\
    );
\txeq_preset[11]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[11]_i_1__6_n_0\
    );
\txeq_preset[12]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001574"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[12]_i_1__6_n_0\
    );
\txeq_preset[13]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[13]_i_1__6_n_0\
    );
\txeq_preset[14]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000410"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[14]_i_1__6_n_0\
    );
\txeq_preset[15]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      O => \txeq_preset[15]_i_1__6_n_0\
    );
\txeq_preset[16]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0014"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[16]_i_1__6_n_0\
    );
\txeq_preset[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => RST_CPLLRESET,
      O => \txeq_preset[17]_i_1_n_0\
    );
\txeq_preset[17]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[17]_i_2__6_n_0\
    );
\txeq_preset[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[1]_i_1__6_n_0\
    );
\txeq_preset[2]_i_1__6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00C8"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => RST_CPLLRESET,
      O => \txeq_preset[2]_i_1__6_n_0\
    );
\txeq_preset[3]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003424"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[3]_i_1__6_n_0\
    );
\txeq_preset[7]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000408"
    )
        port map (
      I0 => txeq_preset_reg2(0),
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(2),
      I4 => RST_CPLLRESET,
      O => \txeq_preset[7]_i_1__6_n_0\
    );
\txeq_preset[8]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAEBBFB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(1),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[8]_i_1__6_n_0\
    );
\txeq_preset[9]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AEAEBABB"
    )
        port map (
      I0 => RST_CPLLRESET,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => txeq_preset_reg2(2),
      O => \txeq_preset[9]_i_1__6_n_0\
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      Q => txeq_preset_done,
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => RST_CPLLRESET
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => RST_CPLLRESET
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[0]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[10]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[11]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[12]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[13]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[14]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[15]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[16]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[17]_i_2__6_n_0\,
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[1]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[2]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[3]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[4]\,
      R => '0'
    );
\txeq_preset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[5]\,
      R => '0'
    );
\txeq_preset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => '0',
      Q => \txeq_preset_reg_n_0_[6]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[7]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[8]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[9]_i_1__6_n_0\,
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I3 => \txeq_preset_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[0]_i_2__6_n_0\,
      O => \txeq_txcoeff[0]_i_1__6_n_0\
    );
\txeq_txcoeff[0]_i_2__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA208A00"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[0]_i_2__6_n_0\
    );
\txeq_txcoeff[10]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[10]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => \txeq_txcoeff[10]_i_2__6_n_0\,
      O => \txeq_txcoeff[10]_i_1__6_n_0\
    );
\txeq_txcoeff[10]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[16]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[10]_i_2__6_n_0\
    );
\txeq_txcoeff[11]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[11]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[10]\,
      I4 => \txeq_txcoeff[11]_i_2__6_n_0\,
      O => \txeq_txcoeff[11]_i_1__6_n_0\
    );
\txeq_txcoeff[11]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[18]\,
      I2 => \txeq_txcoeff_reg_n_0_[17]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[11]_i_2__6_n_0\
    );
\txeq_txcoeff[12]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[11]\,
      I4 => \txeq_txcoeff[12]_i_2__6_n_0\,
      O => \txeq_txcoeff[12]_i_1__6_n_0\
    );
\txeq_txcoeff[12]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(0),
      I2 => \txeq_txcoeff_reg_n_0_[18]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[12]_i_2__6_n_0\
    );
\txeq_txcoeff[13]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[12]\,
      I4 => \txeq_txcoeff[13]_i_2__6_n_0\,
      O => \txeq_txcoeff[13]_i_1__6_n_0\
    );
\txeq_txcoeff[13]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(1),
      I2 => txeq_deemph_reg2(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[13]_i_2__6_n_0\
    );
\txeq_txcoeff[14]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => \txeq_txcoeff[14]_i_2__6_n_0\,
      O => \txeq_txcoeff[14]_i_1__6_n_0\
    );
\txeq_txcoeff[14]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(1),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[14]_i_2__6_n_0\
    );
\txeq_txcoeff[15]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[15]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => \txeq_txcoeff[15]_i_2__6_n_0\,
      O => \txeq_txcoeff[15]_i_1__6_n_0\
    );
\txeq_txcoeff[15]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(3),
      I2 => txeq_deemph_reg2(2),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[15]_i_2__6_n_0\
    );
\txeq_txcoeff[16]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[16]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => \txeq_txcoeff[16]_i_2__6_n_0\,
      O => \txeq_txcoeff[16]_i_1__6_n_0\
    );
\txeq_txcoeff[16]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => txeq_deemph_reg2(4),
      I2 => txeq_deemph_reg2(3),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[16]_i_2__6_n_0\
    );
\txeq_txcoeff[17]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[17]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => \txeq_txcoeff[17]_i_2__6_n_0\,
      O => \txeq_txcoeff[17]_i_1__6_n_0\
    );
\txeq_txcoeff[17]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => txeq_deemph_reg2(4),
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[17]_i_2__6_n_0\
    );
\txeq_txcoeff[18]_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557FF5755575557"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx[1]_i_2__6_n_0\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I4 => txeq_control_reg2(0),
      I5 => txeq_control_reg2(1),
      O => \txeq_txcoeff[18]_i_1__6_n_0\
    );
\txeq_txcoeff[18]_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I2 => \txeq_txcoeff[18]_i_3__6_n_0\,
      O => \txeq_txcoeff[18]_i_2__6_n_0\
    );
\txeq_txcoeff[18]_i_3__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F888F8F888888888"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I2 => txeq_deemph_reg2(5),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[18]_i_3__6_n_0\
    );
\txeq_txcoeff[1]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[0]\,
      I4 => \txeq_txcoeff[1]_i_2__6_n_0\,
      O => \txeq_txcoeff[1]_i_1__6_n_0\
    );
\txeq_txcoeff[1]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[7]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2__6_n_0\
    );
\txeq_txcoeff[2]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[1]\,
      I4 => \txeq_txcoeff[2]_i_2__6_n_0\,
      O => \txeq_txcoeff[2]_i_1__6_n_0\
    );
\txeq_txcoeff[2]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[8]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[2]_i_2__6_n_0\
    );
\txeq_txcoeff[3]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[2]\,
      I4 => \txeq_txcoeff[3]_i_2__6_n_0\,
      O => \txeq_txcoeff[3]_i_1__6_n_0\
    );
\txeq_txcoeff[3]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff_reg_n_0_[9]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2__6_n_0\
    );
\txeq_txcoeff[4]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[3]\,
      I4 => \txeq_txcoeff[4]_i_2__6_n_0\,
      O => \txeq_txcoeff[4]_i_1__6_n_0\
    );
\txeq_txcoeff[4]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff_reg_n_0_[10]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[4]_i_2__6_n_0\
    );
\txeq_txcoeff[5]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[4]\,
      I4 => \txeq_txcoeff[5]_i_2__6_n_0\,
      O => \txeq_txcoeff[5]_i_1__6_n_0\
    );
\txeq_txcoeff[5]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      I2 => \txeq_txcoeff_reg_n_0_[11]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[5]_i_2__6_n_0\
    );
\txeq_txcoeff[6]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[6]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[5]\,
      I4 => \txeq_txcoeff[6]_i_2__6_n_0\,
      O => \txeq_txcoeff[6]_i_1__6_n_0\
    );
\txeq_txcoeff[6]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[12]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[6]_i_2__6_n_0\
    );
\txeq_txcoeff[7]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[7]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => \txeq_txcoeff[7]_i_2__6_n_0\,
      O => \txeq_txcoeff[7]_i_1__6_n_0\
    );
\txeq_txcoeff[7]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      I2 => \txeq_txcoeff_reg_n_0_[13]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[7]_i_2__6_n_0\
    );
\txeq_txcoeff[8]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[8]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => \txeq_txcoeff[8]_i_2__6_n_0\,
      O => \txeq_txcoeff[8]_i_1__6_n_0\
    );
\txeq_txcoeff[8]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0ECF0A0A0A0A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      I2 => \txeq_txcoeff_reg_n_0_[14]\,
      I3 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      O => \txeq_txcoeff[8]_i_2__6_n_0\
    );
\txeq_txcoeff[9]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF888"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[2]\,
      I1 => \txeq_preset_reg_n_0_[9]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[4]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => \txeq_txcoeff[9]_i_2__6_n_0\,
      O => \txeq_txcoeff[9]_i_1__6_n_0\
    );
\txeq_txcoeff[9]_i_2__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0800FB000800"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I4 => \txeq_txcoeff_reg_n_0_[15]\,
      I5 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      O => \txeq_txcoeff[9]_i_2__6_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4444F444"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_tx_reg_n_0_[1]\,
      I3 => txeq_control_reg2(1),
      I4 => txeq_control_reg2(0),
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \FSM_onehot_fsm_tx_reg_n_0_[3]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[0]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[10]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[11]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[12]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[13]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[14]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[15]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[16]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[17]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[18]_i_2__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[1]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[2]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[3]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[4]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[5]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[6]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[7]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[8]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => RST_CPLLRESET
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => pclk_sel_reg,
      CE => \txeq_txcoeff[18]_i_1__6_n_0\,
      D => \txeq_txcoeff[9]_i_1__6_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => RST_CPLLRESET
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_top is
  port (
    trn_rdst_rdy : out STD_LOGIC;
    m_axis_rx_tvalid : out STD_LOGIC;
    m_axis_rx_tlast : out STD_LOGIC;
    trn_teof : out STD_LOGIC;
    trn_tsrc_rdy : out STD_LOGIC;
    trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_tx_tready : out STD_LOGIC;
    trn_in_packet_reg : out STD_LOGIC;
    tbuf_av_gap_thrtl_reg : out STD_LOGIC;
    tbuf_av_gap_thrtl_reg_0 : out STD_LOGIC;
    trn_tcfg_gnt : out STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    cfg_pm_turnoff_ok_n : out STD_LOGIC;
    trn_tsof : out STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    user_reset_out_reg : in STD_LOGIC;
    trn_rsrc_dsc : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    rsrc_rdy_filtered10_out : in STD_LOGIC;
    trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 );
    trn_reof : in STD_LOGIC;
    trn_rsof : in STD_LOGIC;
    trn_recrc_err : in STD_LOGIC;
    trn_rerrfwd : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_cfg_gnt : in STD_LOGIC;
    trn_tcfg_req : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    tbuf_av_min_trig : in STD_LOGIC;
    user_reset_out_reg_0 : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    trn_rdst_rdy_xhdl4_reg : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC;
    user_lnk_up_int_reg : in STD_LOGIC;
    cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 );
    user_reset_out_reg_1 : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ : in STD_LOGIC;
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ : in STD_LOGIC;
    \tcfg_req_cnt_reg[1]\ : in STD_LOGIC;
    trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 );
    trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 );
    trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_to_turnoff : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_top : entity is "PCIeGen1x8If64_axi_basic_top";
end PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_top;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_top is
begin
rx_inst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx
     port map (
      E(0) => trn_rdst_rdy,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(7 downto 0) => m_axis_rx_tkeep(7 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(21 downto 0) => m_axis_rx_tuser(21 downto 0),
      m_axis_rx_tvalid => m_axis_rx_tvalid,
      rsrc_rdy_filtered10_out => rsrc_rdy_filtered10_out,
      trn_in_packet_reg => trn_in_packet_reg,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_rdst_rdy_xhdl4_reg => trn_rdst_rdy_xhdl4_reg,
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem(0),
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      user_clk => user_clk,
      user_reset_out_reg => user_reset_out_reg,
      user_reset_out_reg_0 => user_reset_out_reg_0
    );
tx_inst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx
     port map (
      Q(63 downto 0) => Q(63 downto 0),
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      cfg_pm_turnoff_ok_n => cfg_pm_turnoff_ok_n,
      cfg_to_turnoff => cfg_to_turnoff,
      cfg_turnoff_ok => cfg_turnoff_ok,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ => \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(3 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(3 downto 0),
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => s_axis_tx_tready,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      tbuf_av_gap_thrtl_reg => tbuf_av_gap_thrtl_reg,
      tbuf_av_gap_thrtl_reg_0 => tbuf_av_gap_thrtl_reg_0,
      tbuf_av_min_trig => tbuf_av_min_trig,
      \tcfg_req_cnt_reg[1]\ => \tcfg_req_cnt_reg[1]\,
      trn_tbuf_av(5 downto 0) => trn_tbuf_av(5 downto 0),
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => trn_tcfg_req,
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem(0),
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy,
      tx_cfg_gnt => tx_cfg_gnt,
      user_clk => user_clk,
      user_lnk_up_int_reg => user_lnk_up_int_reg,
      user_reset_out_reg => user_reset_out_reg,
      user_reset_out_reg_0 => user_reset_out_reg_1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x : entity is "PCIeGen1x8If64_pcie_brams_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x is
begin
\brams[0].ram\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_14
     port map (
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0),
      user_clk => user_clk
    );
\brams[1].ram\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_15
     port map (
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(35 downto 18),
      \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(35 downto 18),
      user_clk => user_clk
    );
\brams[2].ram\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_16
     port map (
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(17 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(53 downto 36),
      \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(53 downto 36),
      user_clk => user_clk
    );
\brams[3].ram\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_17
     port map (
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(13 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(67 downto 54),
      \ramb_bl.ramb36_dp_bl.ram36_bl\(13 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(67 downto 54),
      user_clk => user_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x_7 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 68 downto 0 );
    mim_tx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 68 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x_7 : entity is "PCIeGen1x8If64_pcie_brams_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x_7;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x_7 is
begin
\brams[0].ram\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x
     port map (
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      user_clk => user_clk,
      wdata(17 downto 0) => wdata(17 downto 0)
    );
\brams[1].ram\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_8
     port map (
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(35 downto 18),
      user_clk => user_clk,
      wdata(17 downto 0) => wdata(35 downto 18)
    );
\brams[2].ram\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_9
     port map (
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(53 downto 36),
      user_clk => user_clk,
      wdata(17 downto 0) => wdata(53 downto 36)
    );
\brams[3].ram\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_10
     port map (
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(14 downto 0) => rdata(68 downto 54),
      user_clk => user_clk,
      wdata(14 downto 0) => wdata(68 downto 54)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pipe_wrapper is
  port (
    QRST_QPLLLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    \cplllock_reg1_reg[3]_0\ : out STD_LOGIC;
    CLK_DCLK : out STD_LOGIC;
    QRST_CPLLLOCK : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gt_rx_elec_idle_wire_filter : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
    SYNC_RXPHALIGNDONE_M : out STD_LOGIC;
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txoutclk_out : out STD_LOGIC;
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 127 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 23 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 23 downto 0 );
    PIPE_RXDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 63 downto 0 );
    PIPE_RXDATAK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 63 downto 0 );
    CLK_OOBCLK : out STD_LOGIC;
    GT_TXPMARESET0 : out STD_LOGIC;
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 6 downto 0 );
    \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GT_TXPMARESET092_out : out STD_LOGIC;
    \gt_rxdata_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GT_TXPMARESET0120_out : out STD_LOGIC;
    \gt_rxdata_q_reg[15]_1\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GT_TXPMARESET074_out : out STD_LOGIC;
    \cplllock_reg1_reg[7]\ : out STD_LOGIC;
    \cplllock_reg1_reg[7]_0\ : out STD_LOGIC;
    \gt_rxdata_q_reg[15]_2\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GT_TXPMARESET064_out : out STD_LOGIC;
    \gt_rxdata_q_reg[15]_3\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]_3\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GT_TXPMARESET046_out : out STD_LOGIC;
    \gt_rxdata_q_reg[15]_4\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]_4\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GT_TXPMARESET035_out : out STD_LOGIC;
    \gt_rxdata_q_reg[15]_5\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]_5\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GT_TXPMARESET017_out : out STD_LOGIC;
    reset_n_reg2_reg_0 : out STD_LOGIC;
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    SYNC_FSM_TX : out STD_LOGIC_VECTOR ( 5 downto 0 );
    RATE_FSM : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt_rxvalid_q_reg : out STD_LOGIC;
    DRP_FSM : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt_rxvalid_q_reg_0 : out STD_LOGIC;
    \index_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt_rxvalid_q_reg_1 : out STD_LOGIC;
    \index_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_1\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_1\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt_rxvalid_q_reg_2 : out STD_LOGIC;
    \index_reg[1]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_2\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_2\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt_rxvalid_q_reg_3 : out STD_LOGIC;
    \index_reg[1]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_3\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_3\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt_rxvalid_q_reg_4 : out STD_LOGIC;
    \index_reg[1]_3\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_4\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_4\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt_rxvalid_q_reg_5 : out STD_LOGIC;
    \index_reg[1]_4\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_5\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_5\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    gt_rxvalid_q_reg_6 : out STD_LOGIC;
    \index_reg[1]_5\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    D : out STD_LOGIC;
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rx_status_q_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rx_status_q_reg[2]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rx_status_q_reg[2]_3\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rx_status_q_reg[2]_4\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rx_status_q_reg[2]_5\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rx_status_q_reg[2]_6\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rate_idle : out STD_LOGIC;
    EQ_GEN3 : out STD_LOGIC;
    CLK_MMCM_LOCK : out STD_LOGIC;
    CLK_USERCLK1 : out STD_LOGIC;
    CLK_PCLK_SEL : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_qrst_idle : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    USER_RXPMARESET : out STD_LOGIC;
    gt_rx_phy_status_wire_filter : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \cplllock_reg1_reg[1]\ : out STD_LOGIC;
    \cplllock_reg1_reg[2]\ : out STD_LOGIC;
    \cplllock_reg1_reg[3]_1\ : out STD_LOGIC;
    \cplllock_reg1_reg[4]\ : out STD_LOGIC;
    \cplllock_reg1_reg[5]\ : out STD_LOGIC;
    \cplllock_reg1_reg[6]\ : out STD_LOGIC;
    \cplllock_reg1_reg[7]_1\ : out STD_LOGIC;
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 55 downto 0 );
    sys_clk : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 );
    GT_RXPMARESET0 : in STD_LOGIC;
    PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_TXDEEMPH : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\ : in STD_LOGIC;
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMARGIN : in STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXDATA : in STD_LOGIC_VECTOR ( 127 downto 0 );
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 15 downto 0 );
    GT_RXPMARESET089_out : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\ : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    GT_RXPMARESET0117_out : in STD_LOGIC;
    GT_RXPMARESET071_out : in STD_LOGIC;
    GT_RXPMARESET061_out : in STD_LOGIC;
    PIPE_TXDETECTRX : in STD_LOGIC;
    PIPE_TXMARGIN : in STD_LOGIC_VECTOR ( 2 downto 0 );
    GT_RXPMARESET043_out : in STD_LOGIC;
    pipe_tx_rcvr_det : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_margin_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    GT_RXPMARESET032_out : in STD_LOGIC;
    GT_RXPMARESET014_out : in STD_LOGIC;
    gt_rxvalid_q_reg_7 : in STD_LOGIC;
    gt_rxvalid_q_reg_8 : in STD_LOGIC;
    gt_rxvalid_q_reg_9 : in STD_LOGIC;
    gt_rxvalid_q_reg_10 : in STD_LOGIC;
    gt_rxvalid_q_reg_11 : in STD_LOGIC;
    gt_rxvalid_q_reg_12 : in STD_LOGIC;
    gt_rxvalid_q_reg_13 : in STD_LOGIC;
    gt_rxvalid_q_reg_14 : in STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 71 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pl_ltssm_state_q_reg[4]\ : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_mmcm_rst_n : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 127 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pipe_wrapper : entity is "PCIeGen1x8If64_pipe_wrapper";
end PCIeGen1x8If64_PCIeGen1x8If64_pipe_wrapper;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pipe_wrapper is
  signal \^clk_dclk\ : STD_LOGIC;
  signal \^clk_mmcm_lock\ : STD_LOGIC;
  signal \^clk_oobclk\ : STD_LOGIC;
  signal \^clk_pclk_sel\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal DRP_START0 : STD_LOGIC;
  signal DRP_START0102_out : STD_LOGIC;
  signal DRP_START0110_out : STD_LOGIC;
  signal DRP_START0130_out : STD_LOGIC;
  signal DRP_START025_out : STD_LOGIC;
  signal DRP_START054_out : STD_LOGIC;
  signal DRP_START082_out : STD_LOGIC;
  signal DRP_START08_out : STD_LOGIC;
  signal DRP_X160 : STD_LOGIC;
  signal DRP_X160104_out : STD_LOGIC;
  signal DRP_X16010_out : STD_LOGIC;
  signal DRP_X160112_out : STD_LOGIC;
  signal DRP_X160132_out : STD_LOGIC;
  signal DRP_X16027_out : STD_LOGIC;
  signal DRP_X16056_out : STD_LOGIC;
  signal DRP_X16084_out : STD_LOGIC;
  signal DRP_X16X20_MODE0 : STD_LOGIC;
  signal DRP_X16X20_MODE0106_out : STD_LOGIC;
  signal DRP_X16X20_MODE0114_out : STD_LOGIC;
  signal DRP_X16X20_MODE0134_out : STD_LOGIC;
  signal DRP_X16X20_MODE0136_out : STD_LOGIC;
  signal DRP_X16X20_MODE029_out : STD_LOGIC;
  signal DRP_X16X20_MODE058_out : STD_LOGIC;
  signal DRP_X16X20_MODE086_out : STD_LOGIC;
  signal \^eq_gen3\ : STD_LOGIC;
  signal \^gt_txpmareset0\ : STD_LOGIC;
  signal \^gt_txpmareset0120_out\ : STD_LOGIC;
  signal \^gt_txpmareset017_out\ : STD_LOGIC;
  signal \^gt_txpmareset035_out\ : STD_LOGIC;
  signal \^gt_txpmareset046_out\ : STD_LOGIC;
  signal \^gt_txpmareset064_out\ : STD_LOGIC;
  signal \^gt_txpmareset074_out\ : STD_LOGIC;
  signal \^gt_txpmareset092_out\ : STD_LOGIC;
  signal \^qrst_cplllock\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^qrst_qplllock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^sync_rxphaligndone_m\ : STD_LOGIC;
  signal SYNC_TXSYNC_START0 : STD_LOGIC;
  signal SYNC_TXSYNC_START0100_out : STD_LOGIC;
  signal SYNC_TXSYNC_START0108_out : STD_LOGIC;
  signal SYNC_TXSYNC_START0128_out : STD_LOGIC;
  signal SYNC_TXSYNC_START023_out : STD_LOGIC;
  signal SYNC_TXSYNC_START052_out : STD_LOGIC;
  signal SYNC_TXSYNC_START080_out : STD_LOGIC;
  signal SYNC_TXSYNC_START098_out : STD_LOGIC;
  signal \^cplllock_reg1_reg[3]\ : STD_LOGIC;
  signal \^cplllock_reg1_reg[3]_0\ : STD_LOGIC;
  signal \^cplllock_reg1_reg[7]\ : STD_LOGIC;
  signal \^cplllock_reg1_reg[7]_0\ : STD_LOGIC;
  signal \^ext_ch_gt_drpdo\ : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal \^ext_ch_gt_drprdy\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal gt_cpllpdrefclk : STD_LOGIC;
  signal \^gt_rx_elec_idle_wire_filter\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \gt_rxchbondo[1]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal p_0_in121_in : STD_LOGIC;
  signal p_0_in123_in : STD_LOGIC;
  signal p_0_in18_in : STD_LOGIC;
  signal p_0_in20_in : STD_LOGIC;
  signal p_0_in2_in : STD_LOGIC;
  signal p_0_in36_in : STD_LOGIC;
  signal p_0_in38_in : STD_LOGIC;
  signal p_0_in3_in : STD_LOGIC;
  signal p_0_in47_in : STD_LOGIC;
  signal p_0_in49_in : STD_LOGIC;
  signal p_0_in65_in : STD_LOGIC;
  signal p_0_in67_in : STD_LOGIC;
  signal p_0_in75_in : STD_LOGIC;
  signal p_0_in77_in : STD_LOGIC;
  signal p_0_in7_in : STD_LOGIC;
  signal p_0_in7_in_1 : STD_LOGIC;
  signal p_0_in7_in_11 : STD_LOGIC;
  signal p_0_in7_in_13 : STD_LOGIC;
  signal p_0_in7_in_15 : STD_LOGIC;
  signal p_0_in7_in_17 : STD_LOGIC;
  signal p_0_in7_in_4 : STD_LOGIC;
  signal p_0_in7_in_7 : STD_LOGIC;
  signal p_0_in93_in : STD_LOGIC;
  signal p_0_in95_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC;
  signal p_104_out : STD_LOGIC;
  signal p_105_out : STD_LOGIC;
  signal p_111_out : STD_LOGIC;
  signal p_113_out : STD_LOGIC;
  signal p_131_out : STD_LOGIC;
  signal p_149_out : STD_LOGIC;
  signal p_152_out : STD_LOGIC;
  signal p_157_out : STD_LOGIC;
  signal p_158_out : STD_LOGIC;
  signal p_159_out : STD_LOGIC;
  signal p_164_out : STD_LOGIC;
  signal p_166_out : STD_LOGIC;
  signal p_184_out : STD_LOGIC;
  signal p_196_out : STD_LOGIC;
  signal p_1_in8_in : STD_LOGIC;
  signal p_1_in8_in_10 : STD_LOGIC;
  signal p_1_in8_in_12 : STD_LOGIC;
  signal p_1_in8_in_14 : STD_LOGIC;
  signal p_1_in8_in_18 : STD_LOGIC;
  signal p_1_in8_in_2 : STD_LOGIC;
  signal p_1_in8_in_5 : STD_LOGIC;
  signal p_1_in8_in_6 : STD_LOGIC;
  signal p_206_out : STD_LOGIC;
  signal p_209_out : STD_LOGIC;
  signal p_214_out : STD_LOGIC;
  signal p_215_out : STD_LOGIC;
  signal p_216_out : STD_LOGIC;
  signal p_221_out : STD_LOGIC;
  signal p_223_out : STD_LOGIC;
  signal p_241_out : STD_LOGIC;
  signal p_259_out : STD_LOGIC;
  signal p_25_out : STD_LOGIC;
  signal p_262_out : STD_LOGIC;
  signal p_267_out : STD_LOGIC;
  signal p_268_out : STD_LOGIC;
  signal p_269_out : STD_LOGIC;
  signal p_274_out : STD_LOGIC;
  signal p_276_out : STD_LOGIC;
  signal p_294_out : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_2_in_0 : STD_LOGIC;
  signal p_2_in_16 : STD_LOGIC;
  signal p_2_in_3 : STD_LOGIC;
  signal p_2_in_8 : STD_LOGIC;
  signal p_2_in_9 : STD_LOGIC;
  signal p_312_out : STD_LOGIC;
  signal p_315_out : STD_LOGIC;
  signal p_320_out : STD_LOGIC;
  signal p_321_out : STD_LOGIC;
  signal p_322_out : STD_LOGIC;
  signal p_327_out : STD_LOGIC;
  signal p_329_out : STD_LOGIC;
  signal p_347_out : STD_LOGIC;
  signal p_365_out : STD_LOGIC;
  signal p_368_out : STD_LOGIC;
  signal p_373_out : STD_LOGIC;
  signal p_374_out : STD_LOGIC;
  signal p_375_out : STD_LOGIC;
  signal p_380_out : STD_LOGIC;
  signal p_382_out : STD_LOGIC;
  signal p_400_out : STD_LOGIC;
  signal p_412_out : STD_LOGIC;
  signal p_422_out : STD_LOGIC;
  signal p_425_out : STD_LOGIC;
  signal p_429_out : STD_LOGIC;
  signal p_430_out : STD_LOGIC;
  signal p_431_out : STD_LOGIC;
  signal p_436_out : STD_LOGIC;
  signal p_438_out : STD_LOGIC;
  signal p_43_out : STD_LOGIC;
  signal p_46_out : STD_LOGIC;
  signal p_51_out : STD_LOGIC;
  signal p_52_out : STD_LOGIC;
  signal p_53_out : STD_LOGIC;
  signal p_58_out : STD_LOGIC;
  signal p_60_out : STD_LOGIC;
  signal p_78_out : STD_LOGIC;
  signal p_96_out : STD_LOGIC;
  signal p_99_out : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[0].gt_wrapper_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_26\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_27\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_28\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_29\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_30\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[1].gt_wrapper_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_26\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_27\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_28\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_29\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_30\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_rate.pipe_rate_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[2].gt_wrapper_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[2].gt_wrapper_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[2].gt_wrapper_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[2].gt_wrapper_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[2].gt_wrapper_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[2].gt_wrapper_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_26\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_27\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_28\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_29\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_30\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_eq.pipe_eq_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_rate.pipe_rate_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_sync_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_sync_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_sync_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_sync_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_sync_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_sync_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_sync_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[2].pipe_user_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[3].gt_wrapper_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[3].gt_wrapper_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[3].gt_wrapper_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[3].gt_wrapper_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[3].gt_wrapper_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[3].gt_wrapper_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[3].gt_wrapper_i_n_86\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_26\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_27\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_28\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_29\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_30\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_eq.pipe_eq_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_rate.pipe_rate_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_sync_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_sync_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_sync_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_sync_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_sync_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_sync_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_sync_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_user_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_user_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_user_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_user_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_user_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_user_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_user_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_user_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_user_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[3].pipe_user_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[4].gt_wrapper_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[4].gt_wrapper_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[4].gt_wrapper_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[4].gt_wrapper_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[4].gt_wrapper_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[4].gt_wrapper_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_26\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_27\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_28\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_29\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_30\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_eq.pipe_eq_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_rate.pipe_rate_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_sync_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_sync_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_sync_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_sync_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_sync_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_sync_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_sync_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[4].pipe_user_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[5].gt_wrapper_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[5].gt_wrapper_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[5].gt_wrapper_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[5].gt_wrapper_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[5].gt_wrapper_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[5].gt_wrapper_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_26\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_27\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_28\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_29\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_30\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_eq.pipe_eq_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_rate.pipe_rate_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_sync_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_sync_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_sync_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_sync_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_sync_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_sync_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_sync_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_user_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_user_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_user_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_user_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_user_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_user_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_user_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_user_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[5].pipe_user_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[6].gt_wrapper_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[6].gt_wrapper_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[6].gt_wrapper_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[6].gt_wrapper_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[6].gt_wrapper_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[6].gt_wrapper_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[6].gt_wrapper_i_n_89\ : STD_LOGIC;
  signal \pipe_lane[6].gt_wrapper_i_n_90\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_26\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_27\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_28\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_29\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_30\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_eq.pipe_eq_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_rate.pipe_rate_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_sync_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_sync_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_sync_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_sync_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_sync_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_sync_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_sync_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[6].pipe_user_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[7].gt_wrapper_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[7].gt_wrapper_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[7].gt_wrapper_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[7].gt_wrapper_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[7].gt_wrapper_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[7].gt_wrapper_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_22\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_23\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_24\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_25\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_26\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_27\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_28\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_29\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_30\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_drp.pipe_drp_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_13\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_eq.pipe_eq_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_20\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_rate.pipe_rate_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_sync_i_n_14\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_sync_i_n_15\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_sync_i_n_16\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_sync_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_sync_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_sync_i_n_19\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_sync_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_17\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_18\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_5\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_6\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[7].pipe_user_i_n_9\ : STD_LOGIC;
  signal \^pipe_qrst_idle\ : STD_LOGIC;
  signal \pipe_reset.pipe_reset_i_n_17\ : STD_LOGIC;
  signal \pipe_reset.pipe_reset_i_n_18\ : STD_LOGIC;
  signal \pipe_reset.pipe_reset_i_n_19\ : STD_LOGIC;
  signal \pipe_reset.pipe_reset_i_n_20\ : STD_LOGIC;
  signal \pipe_reset.pipe_reset_i_n_21\ : STD_LOGIC;
  signal \pipe_reset.pipe_reset_i_n_22\ : STD_LOGIC;
  signal \pipe_reset.pipe_reset_i_n_23\ : STD_LOGIC;
  signal \pipe_reset.pipe_reset_i_n_4\ : STD_LOGIC;
  signal \^pipe_rxdlysresetdone\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^pipe_rxphaligndone\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal \^pipe_txdlysresetdone\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^pipe_txoutclk_out\ : STD_LOGIC;
  signal \^pipe_txphaligndone\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^pipe_txphinitdone\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \qpll_reset.qpll_reset_i_n_4\ : STD_LOGIC;
  signal qpllpd : STD_LOGIC;
  signal qrst_ovrd : STD_LOGIC;
  signal qrst_qpllreset : STD_LOGIC;
  signal rate_gen3 : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal rate_idle : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal reset_n_reg1 : STD_LOGIC;
  signal reset_n_reg2 : STD_LOGIC;
  signal \^reset_n_reg2_reg_0\ : STD_LOGIC;
  signal rst_cpllpd : STD_LOGIC;
  signal rst_dclk_reset : STD_LOGIC;
  signal rst_drp_start : STD_LOGIC;
  signal rst_drp_x16 : STD_LOGIC;
  signal rst_drp_x16x20_mode : STD_LOGIC;
  signal rst_gtreset : STD_LOGIC;
  signal rst_rxusrclk_reset : STD_LOGIC;
  signal rst_txsync_start : STD_LOGIC;
  signal rst_userrdy : STD_LOGIC;
  signal txsyncallin : STD_LOGIC;
  signal user_active_lane : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute box_type : string;
  attribute box_type of cpllpd_refclk_inst : label is "PRIMITIVE";
  attribute ASYNC_REG : boolean;
  attribute ASYNC_REG of reset_n_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of reset_n_reg1_reg : label is "yes";
  attribute ASYNC_REG of reset_n_reg2_reg : label is std.standard.true;
  attribute KEEP of reset_n_reg2_reg : label is "yes";
begin
  CLK_DCLK <= \^clk_dclk\;
  CLK_MMCM_LOCK <= \^clk_mmcm_lock\;
  CLK_OOBCLK <= \^clk_oobclk\;
  CLK_PCLK_SEL(7 downto 0) <= \^clk_pclk_sel\(7 downto 0);
  EQ_GEN3 <= \^eq_gen3\;
  GT_TXPMARESET0 <= \^gt_txpmareset0\;
  GT_TXPMARESET0120_out <= \^gt_txpmareset0120_out\;
  GT_TXPMARESET017_out <= \^gt_txpmareset017_out\;
  GT_TXPMARESET035_out <= \^gt_txpmareset035_out\;
  GT_TXPMARESET046_out <= \^gt_txpmareset046_out\;
  GT_TXPMARESET064_out <= \^gt_txpmareset064_out\;
  GT_TXPMARESET074_out <= \^gt_txpmareset074_out\;
  GT_TXPMARESET092_out <= \^gt_txpmareset092_out\;
  QRST_CPLLLOCK(7 downto 0) <= \^qrst_cplllock\(7 downto 0);
  QRST_QPLLLOCK(1 downto 0) <= \^qrst_qplllock\(1 downto 0);
  SYNC_RXPHALIGNDONE_M <= \^sync_rxphaligndone_m\;
  \cplllock_reg1_reg[3]\ <= \^cplllock_reg1_reg[3]\;
  \cplllock_reg1_reg[3]_0\ <= \^cplllock_reg1_reg[3]_0\;
  \cplllock_reg1_reg[7]\ <= \^cplllock_reg1_reg[7]\;
  \cplllock_reg1_reg[7]_0\ <= \^cplllock_reg1_reg[7]_0\;
  ext_ch_gt_drpdo(127 downto 0) <= \^ext_ch_gt_drpdo\(127 downto 0);
  ext_ch_gt_drprdy(7 downto 0) <= \^ext_ch_gt_drprdy\(7 downto 0);
  gt_rx_elec_idle_wire_filter(7 downto 0) <= \^gt_rx_elec_idle_wire_filter\(7 downto 0);
  \out\(1 downto 0) <= \^out\(1 downto 0);
  pipe_qrst_idle <= \^pipe_qrst_idle\;
  pipe_rxdlysresetdone(7 downto 0) <= \^pipe_rxdlysresetdone\(7 downto 0);
  pipe_rxphaligndone(6 downto 0) <= \^pipe_rxphaligndone\(6 downto 0);
  pipe_rxstatus(23 downto 0) <= \^pipe_rxstatus\(23 downto 0);
  pipe_txdlysresetdone(7 downto 0) <= \^pipe_txdlysresetdone\(7 downto 0);
  pipe_txoutclk_out <= \^pipe_txoutclk_out\;
  pipe_txphaligndone(7 downto 0) <= \^pipe_txphaligndone\(7 downto 0);
  pipe_txphinitdone(7 downto 0) <= \^pipe_txphinitdone\(7 downto 0);
  reset_n_reg2_reg_0 <= \^reset_n_reg2_reg_0\;
cpllpd_refclk_inst: unisim.vcomponents.BUFG
     port map (
      I => sys_clk,
      O => gt_cpllpdrefclk
    );
\pipe_clock_int.pipe_clock_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_clock
     port map (
      CLK_DCLK => \^clk_dclk\,
      CLK_MMCM_LOCK => \^clk_mmcm_lock\,
      CLK_PCLK => \^clk_oobclk\,
      CLK_USERCLK1 => CLK_USERCLK1,
      D(7 downto 0) => \^clk_pclk_sel\(7 downto 0),
      int_pclk_sel_slave(7 downto 0) => int_pclk_sel_slave(7 downto 0),
      pipe_mmcm_rst_n => pipe_mmcm_rst_n,
      pipe_txoutclk_out => \^pipe_txoutclk_out\,
      rate_gen3(0) => \^eq_gen3\
    );
\pipe_lane[0].gt_wrapper_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper
     port map (
      CLK => \^clk_dclk\,
      DRPADDR(8) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_30\,
      DRP_GTXRESET => rst_gtreset,
      GT_RXPMARESET0 => GT_RXPMARESET0,
      GT_TXPMARESET0 => \^gt_txpmareset0\,
      O1671 => \pipe_lane[0].pipe_rate.pipe_rate_i_n_12\,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(1 downto 0),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(0),
      PIPE_RXDATA(15 downto 0) => PIPE_RXDATA(15 downto 0),
      PIPE_RXDATAK(1 downto 0) => PIPE_RXDATAK(1 downto 0),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(0),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(0),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(15 downto 0),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(1 downto 0),
      PIPE_TXDEEMPH(0) => PIPE_TXDEEMPH(0),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(0),
      Q(1 downto 0) => Q(1 downto 0),
      RATE_CPLLLOCK => \^qrst_cplllock\(0),
      RATE_PHYSTATUS => p_400_out,
      RATE_RXRATEDONE => \pipe_lane[0].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[0].gt_wrapper_i_n_21\,
      RST_CPLLRESET => \p_0_in__0\,
      RXCHBONDO(4 downto 0) => \gt_rxchbondo[1]_0\(4 downto 0),
      RXRATE(2) => \pipe_lane[0].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[0].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[0].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[0].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[0].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXPHALIGNDONE_M => \^sync_rxphaligndone_m\,
      SYNC_RXSYNC_DONE => \pipe_lane[0].pipe_sync_i_n_15\,
      TXMAINCURSOR(6) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_11\,
      TXMARGIN(2 downto 0) => TXMARGIN(2 downto 0),
      TXPOSTCURSOR(4) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_4\,
      USER_EYESCANRESET => \pipe_lane[0].pipe_user_i_n_8\,
      USER_OOBCLK => \pipe_lane[0].pipe_user_i_n_5\,
      USER_RXBUFRESET => \pipe_lane[0].pipe_user_i_n_6\,
      USER_RXCDRFREQRESET => \pipe_lane[0].pipe_user_i_n_10\,
      USER_RXCDRRESET => \pipe_lane[0].pipe_user_i_n_11\,
      USER_RXDFELPMRESET => \pipe_lane[0].pipe_user_i_n_9\,
      USER_RXPCSRESET => \pipe_lane[0].pipe_user_i_n_7\,
      USER_RXRESETDONE => \pipe_lane[0].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[0].gt_wrapper_i_n_22\,
      converge_gen3_reg => \pipe_lane[6].pipe_user_i_n_4\,
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(15 downto 0),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(0),
      \fsm_reg[0]\ => \pipe_lane[0].pipe_drp.pipe_drp_i_n_13\,
      \fsm_reg[2]\ => \pipe_lane[0].pipe_drp.pipe_drp_i_n_12\,
      gen3_reg => \pipe_lane[0].pipe_rate.pipe_rate_i_n_14\,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(0),
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_6\(2 downto 0),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_7,
      p_0_in2_in => p_0_in2_in,
      p_0_in3_in => p_0_in3_in,
      pci_exp_rxn(0) => pci_exp_rxn(0),
      pci_exp_rxp(0) => pci_exp_rxp(0),
      pci_exp_txn(0) => pci_exp_txn(0),
      pci_exp_txp(0) => pci_exp_txp(0),
      pclk_sel_reg => \^clk_oobclk\,
      pipe_dmonitorout(7 downto 0) => pipe_dmonitorout(7 downto 0),
      pipe_eyescandataerror(0) => pipe_eyescandataerror(0),
      pipe_rxbufstatus(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      pipe_rxcommadet(0) => pipe_rxcommadet(0),
      pipe_rxdisperr(7 downto 0) => pipe_rxdisperr(7 downto 0),
      pipe_rxdlysresetdone(0) => \^pipe_rxdlysresetdone\(0),
      pipe_rxnotintable(7 downto 0) => pipe_rxnotintable(7 downto 0),
      pipe_rxoutclk_out(0) => pipe_rxoutclk_out(0),
      pipe_rxprbserr(0) => pipe_rxprbserr(0),
      pipe_rxstatus(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\ => \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\,
      pipe_txdlysresetdone(0) => \^pipe_txdlysresetdone\(0),
      pipe_txinhibit(0) => pipe_txinhibit(0),
      pipe_txoutclk_out => \^pipe_txoutclk_out\,
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(0),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(0),
      \pl_ltssm_state_q_reg[4]\ => \pl_ltssm_state_q_reg[4]\,
      qpllpd_reg => \^cplllock_reg1_reg[3]\,
      qpllpd_reg_0 => \^cplllock_reg1_reg[3]_0\,
      \resetovrd_disble.fsm_reg[1]\ => \pipe_lane[0].pipe_user_i_n_16\,
      rst_cpllpd => rst_cpllpd,
      rxcdrlock_reg1_reg => \pipe_lane[0].gt_wrapper_i_n_6\,
      \rxsync_fsm_disable.fsm_rx_reg[2]\ => \pipe_lane[0].pipe_sync_i_n_20\,
      \rxsync_fsm_disable.fsm_rx_reg[2]_0\ => \pipe_lane[0].pipe_sync_i_n_19\,
      rxvalid_reg1_reg => \pipe_lane[0].gt_wrapper_i_n_16\,
      sys_clk => sys_clk,
      \txsync_fsm.fsm_tx_reg[2]\ => \pipe_lane[0].pipe_sync_i_n_16\,
      \txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[0].pipe_sync_i_n_18\,
      \txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[0].pipe_sync_i_n_17\,
      \txsync_fsm.txdlyen_reg\ => \pipe_lane[0].pipe_sync_i_n_21\,
      \userrdy_reg_rep__5\ => \pipe_reset.pipe_reset_i_n_23\
    );
\pipe_lane[0].pipe_drp.pipe_drp_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp
     port map (
      DRPADDR(8) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_30\,
      DRP_DONE => p_422_out,
      DRP_GTXRESET => rst_gtreset,
      DRP_START => DRP_START0,
      DRP_X16 => DRP_X160,
      DRP_X16X20_MODE => DRP_X16X20_MODE0,
      Q(2 downto 0) => DRP_FSM(2 downto 0),
      RST_DCLK_RESET => rst_dclk_reset,
      \cplllock_reg1_reg[0]\ => \pipe_lane[0].pipe_drp.pipe_drp_i_n_12\,
      \cplllock_reg1_reg[0]_0\ => \pipe_lane[0].pipe_drp.pipe_drp_i_n_13\,
      ext_ch_gt_drpaddr(8 downto 0) => ext_ch_gt_drpaddr(8 downto 0),
      ext_ch_gt_drpdi(15 downto 0) => ext_ch_gt_drpdi(15 downto 0),
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(15 downto 0),
      ext_ch_gt_drpen(0) => ext_ch_gt_drpen(0),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(0),
      ext_ch_gt_drpwe(0) => ext_ch_gt_drpwe(0),
      gt_ch_drp_rdy(0) => gt_ch_drp_rdy(0),
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\
    );
\pipe_lane[0].pipe_eq.pipe_eq_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq
     port map (
      CLK => \^clk_oobclk\,
      RST_CPLLRESET => \p_0_in__0\,
      TXMAINCURSOR(6) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[0].pipe_eq.pipe_eq_i_n_4\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[0].pipe_eq.pipe_eq_i_n_17\,
      rate_gen3(0) => \^eq_gen3\
    );
\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_common
     port map (
      DRP_DONE => p_412_out,
      DRP_OVRD => qrst_ovrd,
      DRP_START => \qpll_reset.qpll_reset_i_n_4\,
      O1687 => \pipe_lane[6].pipe_rate.pipe_rate_i_n_14\,
      RATE_QPLLLOCK => \^qrst_qplllock\(0),
      RST_DCLK_RESET => rst_dclk_reset,
      \cplllock_reg1_reg[3]\ => \^cplllock_reg1_reg[3]\,
      \cplllock_reg1_reg[3]_0\ => \^cplllock_reg1_reg[3]_0\,
      qpllpd => qpllpd,
      qrst_qpllreset => qrst_qpllreset,
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      sys_clk => sys_clk
    );
\pipe_lane[0].pipe_rate.pipe_rate_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate
     port map (
      CLK => \^clk_oobclk\,
      DRP_START0 => DRP_START0,
      DRP_X160 => DRP_X160,
      DRP_X16X20_MODE0 => DRP_X16X20_MODE0,
      GT_TXPMARESET0 => \^gt_txpmareset0\,
      Q(4 downto 0) => RATE_FSM(4 downto 0),
      QRST_QPLLPD_IN(0) => p_430_out,
      QRST_QPLLRESET_IN(0) => p_429_out,
      RATE_CPLLLOCK => \^qrst_cplllock\(0),
      RATE_DRP_DONE => p_422_out,
      RATE_MMCM_LOCK => \^clk_mmcm_lock\,
      RATE_PHYSTATUS => p_400_out,
      RATE_QPLLLOCK => \^qrst_qplllock\(0),
      RATE_RESETOVRD_DONE => \pipe_lane[0].pipe_user_i_n_17\,
      RATE_RXRATEDONE => \pipe_lane[0].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[0].gt_wrapper_i_n_21\,
      RATE_TXSYNC_DONE => p_425_out,
      RST_CPLLRESET => \p_0_in__0\,
      RST_DRP_START => rst_drp_start,
      RST_DRP_X16 => rst_drp_x16,
      RST_DRP_X16X20_MODE => rst_drp_x16x20_mode,
      RST_RATE_IDLE(0) => rate_idle(0),
      RXRATE(2) => \pipe_lane[0].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[0].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[0].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[0].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[0].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[0].pipe_sync_i_n_15\,
      SYNC_RXSYNC_START => \pipe_lane[0].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START098_out,
      USER_PCLK_SEL => \^clk_pclk_sel\(0),
      USER_RATE_DONE => \pipe_lane[0].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[0].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[0].pipe_rate.pipe_rate_i_n_5\,
      USER_RXRESETDONE => \pipe_lane[0].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[0].gt_wrapper_i_n_22\,
      \cplllock_reg1_reg[0]\ => \pipe_lane[0].pipe_rate.pipe_rate_i_n_12\,
      \cplllock_reg1_reg[0]_0\ => \pipe_lane[0].pipe_rate.pipe_rate_i_n_14\,
      out1(1) => \^out\(0),
      out1(0) => rst_txsync_start,
      p_0_in2_in => p_0_in2_in,
      p_0_in3_in => p_0_in3_in,
      p_0_in7_in => p_0_in7_in,
      p_1_in8_in => p_1_in8_in,
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      rate_gen3(0) => \^eq_gen3\
    );
\pipe_lane[0].pipe_sync_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync
     port map (
      Q(5 downto 0) => SYNC_FSM_TX(5 downto 0),
      RATE_MMCM_LOCK => \^clk_mmcm_lock\,
      RST_CPLLRESET => \p_0_in__0\,
      RST_RATE_IDLE(0) => rate_idle(0),
      RST_TXSYNC_DONE(0) => p_425_out,
      SYNC_RXCDRLOCK => p_436_out,
      SYNC_RXDLYEN => \pipe_lane[0].pipe_sync_i_n_15\,
      SYNC_RXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_90\,
      SYNC_RXPHALIGNDONE_M => \^sync_rxphaligndone_m\,
      SYNC_RXPHALIGNDONE_S => \pipe_lane[3].gt_wrapper_i_n_86\,
      SYNC_RXSYNC_DONEM_IN => \pipe_lane[0].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[0].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_89\,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXPHINITDONE => \pipe_lane[4].pipe_user_i_n_0\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START098_out,
      \cplllock_reg1_reg[0]\ => \pipe_lane[0].pipe_sync_i_n_16\,
      \cplllock_reg1_reg[0]_0\ => \pipe_lane[0].pipe_sync_i_n_17\,
      \cplllock_reg1_reg[0]_1\ => \pipe_lane[0].pipe_sync_i_n_18\,
      \cplllock_reg1_reg[0]_2\ => \pipe_lane[0].pipe_sync_i_n_19\,
      \cplllock_reg1_reg[0]_3\ => \pipe_lane[0].pipe_sync_i_n_20\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(0),
      p_0_in7_in => p_0_in7_in,
      p_1_in8_in => p_1_in8_in,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_sync_fsm_rx(6 downto 0) => pipe_sync_fsm_rx(6 downto 0),
      rate_gen3(0) => \^eq_gen3\,
      \txsync_fsm.txdlyen_reg_0\ => \pipe_lane[0].pipe_sync_i_n_21\,
      user_active_lane(0) => user_active_lane(0)
    );
\pipe_lane[0].pipe_user_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_user
     port map (
      CLK_PCLK_SEL(0) => \^clk_pclk_sel\(0),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(0),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(0),
      Q(6) => \pipe_lane[0].pipe_user_i_n_6\,
      Q(5) => \pipe_lane[0].pipe_user_i_n_7\,
      Q(4) => \pipe_lane[0].pipe_user_i_n_8\,
      Q(3) => \pipe_lane[0].pipe_user_i_n_9\,
      Q(2) => \pipe_lane[0].pipe_user_i_n_10\,
      Q(1) => \pipe_lane[0].pipe_user_i_n_11\,
      Q(0) => USER_RXPMARESET,
      RST_CPLLRESET => \p_0_in__0\,
      RST_PHYSTATUS(0) => p_400_out,
      RST_RATE_IDLE(0) => rate_idle(0),
      RST_RESETDONE(0) => p_438_out,
      RST_RXCDRLOCK(0) => p_436_out,
      RST_RXUSRCLK_RESET => rst_rxusrclk_reset,
      USER_OOBCLK => \pipe_lane[0].pipe_user_i_n_5\,
      USER_RATE_DONE => \pipe_lane[0].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[0].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[0].pipe_rate.pipe_rate_i_n_5\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[0].pipe_eq.pipe_eq_i_n_17\,
      USER_RXRESETDONE => \pipe_lane[0].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[0].gt_wrapper_i_n_22\,
      \cplllock_reg1_reg[0]\ => \pipe_lane[0].pipe_user_i_n_16\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(0),
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(0),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg,
      gt_rxvalid_q_reg_0 => gt_rxvalid_q_reg_7,
      out1(0) => \^out\(0),
      p_0_in7_in => p_0_in7_in,
      p_0_in7_in_1 => p_0_in7_in_1,
      p_1_in8_in => p_1_in8_in,
      p_1_in8_in_0 => p_1_in8_in_2,
      p_2_in => p_2_in,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_rxstatus(0) => \^pipe_rxstatus\(2),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(1),
      rate_gen3(0) => \^eq_gen3\,
      \resetovrd_disble.reset_reg[4]_0\ => \pipe_lane[0].gt_wrapper_i_n_16\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[0].gt_wrapper_i_n_6\,
      resetovrd_done_reg1_reg => \pipe_lane[0].pipe_user_i_n_17\,
      txelecidle_reg2_reg_0 => \pipe_lane[2].pipe_user_i_n_4\,
      txphinitdone_reg1_reg => \pipe_lane[0].pipe_user_i_n_0\,
      user_active_lane(0) => user_active_lane(0),
      user_rx_converge(0) => p_431_out
    );
\pipe_lane[1].gt_wrapper_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_29
     port map (
      DRPADDR(8) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_30\,
      GT_RXPMARESET089_out => GT_RXPMARESET089_out,
      GT_TXPMARESET092_out => \^gt_txpmareset092_out\,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(3 downto 2),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(1),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(1),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(1),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(31 downto 16),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(3 downto 2),
      PIPE_TXDEEMPH(0) => PIPE_TXDEEMPH(0),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(1),
      Q(1 downto 0) => Q(1 downto 0),
      RATE_CPLLLOCK => \^qrst_cplllock\(1),
      RATE_PHYSTATUS => p_347_out,
      RATE_RXRATEDONE => \pipe_lane[1].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[1].gt_wrapper_i_n_20\,
      RST_CPLLRESET => \p_0_in__0\,
      RXCHBONDO(4 downto 0) => \gt_rxchbondo[1]_0\(4 downto 0),
      RXRATE(2) => \pipe_lane[1].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[1].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[1].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[1].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[1].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[1].pipe_sync_i_n_14\,
      TXMAINCURSOR(6) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_4\,
      USER_EYESCANRESET => \pipe_lane[1].pipe_user_i_n_10\,
      USER_OOBCLK => \pipe_lane[1].pipe_user_i_n_7\,
      USER_RXBUFRESET => \pipe_lane[1].pipe_user_i_n_8\,
      USER_RXCDRFREQRESET => \pipe_lane[1].pipe_user_i_n_12\,
      USER_RXCDRRESET => \pipe_lane[1].pipe_user_i_n_13\,
      USER_RXDFELPMRESET => \pipe_lane[1].pipe_user_i_n_11\,
      USER_RXPCSRESET => \pipe_lane[1].pipe_user_i_n_9\,
      USER_RXRESETDONE => \pipe_lane[1].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[1].gt_wrapper_i_n_21\,
      converge_gen3_reg => \pipe_lane[6].pipe_user_i_n_5\,
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(31 downto 16),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(1),
      \fsm_reg[0]\ => \pipe_lane[1].pipe_drp.pipe_drp_i_n_13\,
      \fsm_reg[2]\ => \pipe_lane[1].pipe_drp.pipe_drp_i_n_12\,
      gen3_reg => \pipe_lane[1].pipe_rate.pipe_rate_i_n_14\,
      gen3_reg_0 => \pipe_lane[1].pipe_rate.pipe_rate_i_n_12\,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(1),
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_5\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_8,
      p_0_in93_in => p_0_in93_in,
      p_0_in95_in => p_0_in95_in,
      pci_exp_rxn(0) => pci_exp_rxn(1),
      pci_exp_rxp(0) => pci_exp_rxp(1),
      pci_exp_txn(0) => pci_exp_txn(1),
      pci_exp_txp(0) => pci_exp_txp(1),
      pclk_sel_reg => \^clk_oobclk\,
      pipe_dmonitorout(7 downto 0) => pipe_dmonitorout(15 downto 8),
      pipe_eyescandataerror(0) => pipe_eyescandataerror(1),
      pipe_rxbufstatus(2 downto 0) => pipe_rxbufstatus(5 downto 3),
      pipe_rxcommadet(0) => pipe_rxcommadet(1),
      pipe_rxdisperr(7 downto 0) => pipe_rxdisperr(15 downto 8),
      pipe_rxdlysresetdone(0) => \^pipe_rxdlysresetdone\(1),
      pipe_rxnotintable(7 downto 0) => pipe_rxnotintable(15 downto 8),
      pipe_rxoutclk_out(0) => pipe_rxoutclk_out(1),
      pipe_rxphaligndone(0) => \^pipe_rxphaligndone\(0),
      pipe_rxprbserr(0) => pipe_rxprbserr(1),
      pipe_rxstatus(2 downto 0) => \^pipe_rxstatus\(5 downto 3),
      \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(2 downto 0),
      \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\ => \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\,
      pipe_txdlysresetdone(0) => \^pipe_txdlysresetdone\(1),
      pipe_txinhibit(0) => pipe_txinhibit(1),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(1),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(1),
      \pl_ltssm_state_q_reg[4]\ => \pl_ltssm_state_q_reg[4]\,
      qpllpd_reg => \^cplllock_reg1_reg[3]\,
      qpllpd_reg_0 => \^cplllock_reg1_reg[3]_0\,
      \resetovrd_disble.fsm_reg[1]\ => \pipe_lane[1].pipe_user_i_n_18\,
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_cpllpd => rst_cpllpd,
      rst_gtreset => rst_gtreset,
      rxcdrlock_reg1_reg => \pipe_lane[1].gt_wrapper_i_n_6\,
      rxsync_donem_reg2_reg => \pipe_lane[1].pipe_sync_i_n_18\,
      \rxsync_fsm_disable.fsm_rx_reg[2]\ => \pipe_lane[1].pipe_sync_i_n_19\,
      rxvalid_reg1_reg => \pipe_lane[1].gt_wrapper_i_n_16\,
      sys_clk => sys_clk,
      \txsync_fsm.fsm_tx_reg[2]\ => \pipe_lane[1].pipe_sync_i_n_15\,
      \txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[1].pipe_sync_i_n_17\,
      \txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[1].pipe_sync_i_n_16\,
      \txsync_fsm.txdlyen_reg\ => \pipe_lane[1].pipe_sync_i_n_6\,
      \userrdy_reg_rep__4\ => \pipe_reset.pipe_reset_i_n_22\
    );
\pipe_lane[1].pipe_drp.pipe_drp_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_30
     port map (
      DRPADDR(8) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[1].pipe_drp.pipe_drp_i_n_30\,
      DRP_DONE => p_365_out,
      DRP_START => DRP_START0102_out,
      DRP_X16 => DRP_X160104_out,
      DRP_X16X20_MODE => DRP_X16X20_MODE0106_out,
      Q(2 downto 0) => \index_reg[1]\(2 downto 0),
      RST_DCLK_RESET => rst_dclk_reset,
      \cplllock_reg1_reg[1]\ => \pipe_lane[1].pipe_drp.pipe_drp_i_n_12\,
      \cplllock_reg1_reg[1]_0\ => \pipe_lane[1].pipe_drp.pipe_drp_i_n_13\,
      ext_ch_gt_drpaddr(8 downto 0) => ext_ch_gt_drpaddr(17 downto 9),
      ext_ch_gt_drpdi(15 downto 0) => ext_ch_gt_drpdi(31 downto 16),
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(31 downto 16),
      ext_ch_gt_drpen(0) => ext_ch_gt_drpen(1),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(1),
      ext_ch_gt_drpwe(0) => ext_ch_gt_drpwe(1),
      gt_ch_drp_rdy(0) => gt_ch_drp_rdy(1),
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_gtreset => rst_gtreset
    );
\pipe_lane[1].pipe_eq.pipe_eq_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_31
     port map (
      RST_CPLLRESET => \p_0_in__0\,
      TXMAINCURSOR(6) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[1].pipe_eq.pipe_eq_i_n_4\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[1].pipe_eq.pipe_eq_i_n_17\,
      pclk_sel_reg => \^clk_oobclk\,
      rate_gen3(0) => rate_gen3(1)
    );
\pipe_lane[1].pipe_rate.pipe_rate_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_32
     port map (
      DRP_START0102_out => DRP_START0102_out,
      DRP_X160104_out => DRP_X160104_out,
      DRP_X16X20_MODE0106_out => DRP_X16X20_MODE0106_out,
      GT_TXPMARESET092_out => \^gt_txpmareset092_out\,
      Q(4 downto 0) => \sysclksel_reg[1]\(4 downto 0),
      QRST_QPLLPD_IN(0) => p_374_out,
      QRST_QPLLRESET_IN(0) => p_373_out,
      RATE_CPLLLOCK => \^qrst_cplllock\(1),
      RATE_DRP_DONE => p_365_out,
      RATE_MMCM_LOCK => \^clk_mmcm_lock\,
      RATE_PHYSTATUS => p_347_out,
      RATE_QPLLLOCK => \^qrst_qplllock\(0),
      RATE_RESETOVRD_DONE => \pipe_lane[1].pipe_user_i_n_19\,
      RATE_RXRATEDONE => \pipe_lane[1].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[1].gt_wrapper_i_n_20\,
      RATE_TXSYNC_DONE => p_368_out,
      RST_CPLLRESET => \p_0_in__0\,
      RST_DRP_START => rst_drp_start,
      RST_DRP_X16 => rst_drp_x16,
      RST_DRP_X16X20_MODE => rst_drp_x16x20_mode,
      RST_RATE_IDLE(0) => rate_idle(1),
      RXRATE(2) => \pipe_lane[1].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[1].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[1].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[1].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[1].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[1].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[1].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0100_out,
      USER_PCLK_SEL => \^clk_pclk_sel\(1),
      USER_RATE_DONE => \pipe_lane[1].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[1].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[1].pipe_rate.pipe_rate_i_n_5\,
      USER_RXRESETDONE => \pipe_lane[1].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[1].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[1]\ => \pipe_lane[1].pipe_rate.pipe_rate_i_n_12\,
      \cplllock_reg1_reg[1]_0\ => \pipe_lane[1].pipe_rate.pipe_rate_i_n_14\,
      out1(1) => \^out\(0),
      out1(0) => rst_txsync_start,
      p_0_in7_in => p_0_in7_in_1,
      p_0_in93_in => p_0_in93_in,
      p_0_in95_in => p_0_in95_in,
      p_1_in8_in => p_1_in8_in_2,
      pclk_sel_reg_0 => \^clk_oobclk\,
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      rate_gen3(0) => rate_gen3(1)
    );
\pipe_lane[1].pipe_sync_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_33
     port map (
      Q(5 downto 0) => \txsync_fsm.txdlyen_reg\(5 downto 0),
      RST_CPLLRESET => \p_0_in__0\,
      RST_RATE_IDLE(0) => rate_idle(1),
      RST_TXSYNC_DONE(0) => p_368_out,
      SYNC_GEN3 => rate_gen3(1),
      SYNC_RXCDRLOCK => p_380_out,
      SYNC_RXDLYEN => \pipe_lane[1].pipe_sync_i_n_14\,
      SYNC_RXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_90\,
      SYNC_RXPHALIGNDONE_M => \^sync_rxphaligndone_m\,
      SYNC_RXPHALIGNDONE_S => \pipe_lane[3].gt_wrapper_i_n_86\,
      SYNC_RXSYNC_DONEM_IN => \pipe_lane[0].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[1].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_89\,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXPHINITDONE => \pipe_lane[4].pipe_user_i_n_0\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0100_out,
      \cplllock_reg1_reg[1]\ => \pipe_lane[1].pipe_sync_i_n_15\,
      \cplllock_reg1_reg[1]_0\ => \pipe_lane[1].pipe_sync_i_n_16\,
      \cplllock_reg1_reg[1]_1\ => \pipe_lane[1].pipe_sync_i_n_17\,
      \cplllock_reg1_reg[1]_2\ => \pipe_lane[1].pipe_sync_i_n_18\,
      \cplllock_reg1_reg[1]_3\ => \pipe_lane[1].pipe_sync_i_n_19\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(1),
      p_0_in7_in => p_0_in7_in_1,
      p_1_in8_in => p_1_in8_in_2,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_sync_fsm_rx(6 downto 0) => pipe_sync_fsm_rx(13 downto 7),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\,
      \txsync_fsm.txdlyen_reg_0\ => \pipe_lane[1].pipe_sync_i_n_6\
    );
\pipe_lane[1].pipe_user_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_34
     port map (
      CLK_PCLK_SEL(0) => \^clk_pclk_sel\(1),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(1),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(1),
      Q(6) => \pipe_lane[1].pipe_user_i_n_8\,
      Q(5) => \pipe_lane[1].pipe_user_i_n_9\,
      Q(4) => \pipe_lane[1].pipe_user_i_n_10\,
      Q(3) => \pipe_lane[1].pipe_user_i_n_11\,
      Q(2) => \pipe_lane[1].pipe_user_i_n_12\,
      Q(1) => \pipe_lane[1].pipe_user_i_n_13\,
      Q(0) => \cplllock_reg1_reg[1]\,
      RST_CPLLRESET => \p_0_in__0\,
      RST_PHYSTATUS(0) => p_347_out,
      RST_RATE_IDLE(0) => rate_idle(1),
      RST_RESETDONE(0) => p_382_out,
      RST_RXCDRLOCK(0) => p_380_out,
      RST_RXUSRCLK_RESET => rst_rxusrclk_reset,
      USER_OOBCLK => \pipe_lane[1].pipe_user_i_n_7\,
      USER_RATE_DONE => \pipe_lane[1].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[1].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[1].pipe_rate.pipe_rate_i_n_5\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[1].pipe_eq.pipe_eq_i_n_17\,
      USER_RXRESETDONE => \pipe_lane[1].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[1].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[1]\ => \pipe_lane[1].pipe_user_i_n_18\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(1),
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(1),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_0,
      gt_rxvalid_q_reg_0 => gt_rxvalid_q_reg_8,
      out1(0) => \^out\(0),
      p_0_in7_in => p_0_in7_in_1,
      p_0_in7_in_1 => p_0_in7_in_7,
      p_1_in8_in => p_1_in8_in_2,
      p_1_in8_in_0 => p_1_in8_in_6,
      p_2_in => p_2_in_0,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_rxstatus(0) => \^pipe_rxstatus\(5),
      pipe_txphaligndone(1) => \^pipe_txphaligndone\(3),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(1),
      pipe_txphinitdone(1) => \^pipe_txphinitdone\(3),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(1),
      rate_gen3(0) => rate_gen3(1),
      \resetovrd_disble.reset_reg[4]_0\ => \pipe_lane[1].gt_wrapper_i_n_16\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[1].gt_wrapper_i_n_6\,
      resetovrd_done_reg1_reg => \pipe_lane[1].pipe_user_i_n_19\,
      txelecidle_reg2_reg_0 => \pipe_lane[2].pipe_user_i_n_0\,
      txphaligndone_reg1_reg => \pipe_lane[1].pipe_user_i_n_0\,
      txphaligndone_reg1_reg_0 => \pipe_lane[1].pipe_user_i_n_3\,
      txphinitdone_reg1_reg => \pipe_lane[1].pipe_user_i_n_4\,
      user_active_lane(0) => user_active_lane(3),
      user_rx_converge(0) => p_375_out
    );
\pipe_lane[2].gt_wrapper_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_35
     port map (
      DRPADDR(8) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_30\,
      GT_RXPMARESET0117_out => GT_RXPMARESET0117_out,
      GT_TXPMARESET0120_out => \^gt_txpmareset0120_out\,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(5 downto 4),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(2),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(2),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(2),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(47 downto 32),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(5 downto 4),
      PIPE_TXDEEMPH(0) => PIPE_TXDEEMPH(1),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(2),
      Q(1 downto 0) => Q(1 downto 0),
      RATE_CPLLLOCK => \^qrst_cplllock\(2),
      RATE_PHYSTATUS => p_294_out,
      RATE_RXRATEDONE => \pipe_lane[2].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[2].gt_wrapper_i_n_20\,
      RST_CPLLRESET => \p_0_in__0\,
      RXCHBONDO(4 downto 0) => \gt_rxchbondo[1]_0\(4 downto 0),
      RXRATE(2) => \pipe_lane[2].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[2].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[2].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[2].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[2].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[2].pipe_sync_i_n_14\,
      TXMAINCURSOR(6) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_11\,
      TXMARGIN(2 downto 0) => TXMARGIN(2 downto 0),
      TXPOSTCURSOR(4) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_4\,
      USER_EYESCANRESET => \pipe_lane[2].pipe_user_i_n_10\,
      USER_OOBCLK => \pipe_lane[2].pipe_user_i_n_7\,
      USER_RXBUFRESET => \pipe_lane[2].pipe_user_i_n_8\,
      USER_RXCDRFREQRESET => \pipe_lane[2].pipe_user_i_n_12\,
      USER_RXCDRRESET => \pipe_lane[2].pipe_user_i_n_13\,
      USER_RXDFELPMRESET => \pipe_lane[2].pipe_user_i_n_11\,
      USER_RXPCSRESET => \pipe_lane[2].pipe_user_i_n_9\,
      USER_RXRESETDONE => \pipe_lane[2].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[2].gt_wrapper_i_n_21\,
      converge_gen3_reg => \pipe_lane[6].pipe_user_i_n_4\,
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(47 downto 32),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(2),
      \fsm_reg[0]\ => \pipe_lane[2].pipe_drp.pipe_drp_i_n_13\,
      \fsm_reg[2]\ => \pipe_lane[2].pipe_drp.pipe_drp_i_n_12\,
      gen3_reg => \pipe_lane[2].pipe_rate.pipe_rate_i_n_14\,
      gen3_reg_0 => \pipe_lane[2].pipe_rate.pipe_rate_i_n_12\,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(2),
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_4\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_0\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_0\(15 downto 0),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_9,
      p_0_in121_in => p_0_in121_in,
      p_0_in123_in => p_0_in123_in,
      pci_exp_rxn(0) => pci_exp_rxn(2),
      pci_exp_rxp(0) => pci_exp_rxp(2),
      pci_exp_txn(0) => pci_exp_txn(2),
      pci_exp_txp(0) => pci_exp_txp(2),
      pclk_sel_reg => \^clk_oobclk\,
      pipe_dmonitorout(7 downto 0) => pipe_dmonitorout(23 downto 16),
      pipe_eyescandataerror(0) => pipe_eyescandataerror(2),
      pipe_rxbufstatus(2 downto 0) => pipe_rxbufstatus(8 downto 6),
      pipe_rxcommadet(0) => pipe_rxcommadet(2),
      pipe_rxdisperr(7 downto 0) => pipe_rxdisperr(23 downto 16),
      pipe_rxdlysresetdone(0) => \^pipe_rxdlysresetdone\(2),
      pipe_rxnotintable(7 downto 0) => pipe_rxnotintable(23 downto 16),
      pipe_rxoutclk_out(0) => pipe_rxoutclk_out(2),
      pipe_rxphaligndone(0) => \^pipe_rxphaligndone\(1),
      pipe_rxprbserr(0) => pipe_rxprbserr(2),
      pipe_rxstatus(2 downto 0) => \^pipe_rxstatus\(8 downto 6),
      \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\ => \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\,
      pipe_txdlysresetdone(0) => \^pipe_txdlysresetdone\(2),
      pipe_txinhibit(0) => pipe_txinhibit(2),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(2),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(2),
      \pl_ltssm_state_q_reg[4]\ => \pl_ltssm_state_q_reg[4]\,
      qpllpd_reg => \^cplllock_reg1_reg[3]\,
      qpllpd_reg_0 => \^cplllock_reg1_reg[3]_0\,
      \resetovrd_disble.fsm_reg[1]\ => \pipe_lane[2].pipe_user_i_n_18\,
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_cpllpd => rst_cpllpd,
      rst_gtreset => rst_gtreset,
      rxcdrlock_reg1_reg => \pipe_lane[2].gt_wrapper_i_n_6\,
      rxsync_donem_reg2_reg => \pipe_lane[2].pipe_sync_i_n_18\,
      \rxsync_fsm_disable.fsm_rx_reg[2]\ => \pipe_lane[2].pipe_sync_i_n_19\,
      rxvalid_reg1_reg => \pipe_lane[2].gt_wrapper_i_n_16\,
      sys_clk => sys_clk,
      \txsync_fsm.fsm_tx_reg[2]\ => \pipe_lane[2].pipe_sync_i_n_15\,
      \txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[2].pipe_sync_i_n_17\,
      \txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[2].pipe_sync_i_n_16\,
      \txsync_fsm.txdlyen_reg\ => \pipe_lane[2].pipe_sync_i_n_6\,
      \userrdy_reg_rep__3\ => \pipe_reset.pipe_reset_i_n_21\
    );
\pipe_lane[2].pipe_drp.pipe_drp_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_36
     port map (
      DRPADDR(8) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[2].pipe_drp.pipe_drp_i_n_30\,
      DRP_DONE => p_312_out,
      DRP_START => DRP_START0110_out,
      DRP_X16 => DRP_X160112_out,
      DRP_X16X20_MODE => DRP_X16X20_MODE0114_out,
      Q(2 downto 0) => \index_reg[1]_0\(2 downto 0),
      RST_DCLK_RESET => rst_dclk_reset,
      \cplllock_reg1_reg[2]\ => \pipe_lane[2].pipe_drp.pipe_drp_i_n_12\,
      \cplllock_reg1_reg[2]_0\ => \pipe_lane[2].pipe_drp.pipe_drp_i_n_13\,
      ext_ch_gt_drpaddr(8 downto 0) => ext_ch_gt_drpaddr(26 downto 18),
      ext_ch_gt_drpdi(15 downto 0) => ext_ch_gt_drpdi(47 downto 32),
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(47 downto 32),
      ext_ch_gt_drpen(0) => ext_ch_gt_drpen(2),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(2),
      ext_ch_gt_drpwe(0) => ext_ch_gt_drpwe(2),
      gt_ch_drp_rdy(0) => gt_ch_drp_rdy(2),
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_gtreset => rst_gtreset
    );
\pipe_lane[2].pipe_eq.pipe_eq_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_37
     port map (
      RST_CPLLRESET => \p_0_in__0\,
      TXMAINCURSOR(6) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[2].pipe_eq.pipe_eq_i_n_4\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[2].pipe_eq.pipe_eq_i_n_17\,
      pclk_sel_reg => \^clk_oobclk\,
      rate_gen3(0) => rate_gen3(2)
    );
\pipe_lane[2].pipe_rate.pipe_rate_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_38
     port map (
      DRP_START0110_out => DRP_START0110_out,
      DRP_X160112_out => DRP_X160112_out,
      DRP_X16X20_MODE0114_out => DRP_X16X20_MODE0114_out,
      GT_TXPMARESET0120_out => \^gt_txpmareset0120_out\,
      Q(4 downto 0) => \sysclksel_reg[1]_0\(4 downto 0),
      QRST_QPLLPD_IN(0) => p_321_out,
      QRST_QPLLRESET_IN(0) => p_320_out,
      RATE_CPLLLOCK => \^qrst_cplllock\(2),
      RATE_DRP_DONE => p_312_out,
      RATE_PHYSTATUS => p_294_out,
      RATE_QPLLLOCK => \^qrst_qplllock\(0),
      RATE_RESETOVRD_DONE => \pipe_lane[2].pipe_user_i_n_19\,
      RATE_RXRATEDONE => \pipe_lane[2].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[2].gt_wrapper_i_n_20\,
      RATE_TXSYNC_DONE => p_315_out,
      RST_CPLLRESET => \p_0_in__0\,
      RST_DRP_START => rst_drp_start,
      RST_DRP_X16 => rst_drp_x16,
      RST_DRP_X16X20_MODE => rst_drp_x16x20_mode,
      RST_RATE_IDLE(0) => rate_idle(2),
      RXRATE(2) => \pipe_lane[2].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[2].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[2].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[2].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[2].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[2].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[2].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0108_out,
      USER_PCLK_SEL => \^clk_pclk_sel\(2),
      USER_RATE_DONE => \pipe_lane[2].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[2].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[2].pipe_rate.pipe_rate_i_n_5\,
      USER_RXRESETDONE => \pipe_lane[2].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[2].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[2]\ => \pipe_lane[2].pipe_rate.pipe_rate_i_n_12\,
      \cplllock_reg1_reg[2]_0\ => \pipe_lane[2].pipe_rate.pipe_rate_i_n_14\,
      out1(1) => \^out\(0),
      out1(0) => rst_txsync_start,
      p_0_in121_in => p_0_in121_in,
      p_0_in123_in => p_0_in123_in,
      p_0_in7_in => p_0_in7_in_4,
      p_1_in8_in => p_1_in8_in_5,
      pclk_sel_reg_0 => \^clk_oobclk\,
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      rate_gen3(0) => rate_gen3(2),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\
    );
\pipe_lane[2].pipe_sync_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_39
     port map (
      Q(5 downto 0) => \txsync_fsm.txdlyen_reg_0\(5 downto 0),
      RST_CPLLRESET => \p_0_in__0\,
      RST_RATE_IDLE(0) => rate_idle(2),
      RST_TXSYNC_DONE(0) => p_315_out,
      SYNC_GEN3 => rate_gen3(2),
      SYNC_RXCDRLOCK => p_327_out,
      SYNC_RXDLYEN => \pipe_lane[2].pipe_sync_i_n_14\,
      SYNC_RXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_90\,
      SYNC_RXPHALIGNDONE_M => \^sync_rxphaligndone_m\,
      SYNC_RXPHALIGNDONE_S => \pipe_lane[3].gt_wrapper_i_n_86\,
      SYNC_RXSYNC_DONEM_IN => \pipe_lane[0].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[2].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_89\,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXPHINITDONE => \pipe_lane[4].pipe_user_i_n_0\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0108_out,
      \cplllock_reg1_reg[2]\ => \pipe_lane[2].pipe_sync_i_n_15\,
      \cplllock_reg1_reg[2]_0\ => \pipe_lane[2].pipe_sync_i_n_16\,
      \cplllock_reg1_reg[2]_1\ => \pipe_lane[2].pipe_sync_i_n_17\,
      \cplllock_reg1_reg[2]_2\ => \pipe_lane[2].pipe_sync_i_n_18\,
      \cplllock_reg1_reg[2]_3\ => \pipe_lane[2].pipe_sync_i_n_19\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(2),
      p_0_in7_in => p_0_in7_in_4,
      p_1_in8_in => p_1_in8_in_5,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_sync_fsm_rx(6 downto 0) => pipe_sync_fsm_rx(20 downto 14),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\,
      \txsync_fsm.txdlyen_reg_0\ => \pipe_lane[2].pipe_sync_i_n_6\
    );
\pipe_lane[2].pipe_user_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_40
     port map (
      CLK_PCLK_SEL(0) => \^clk_pclk_sel\(2),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(2),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(2),
      Q(6) => \pipe_lane[2].pipe_user_i_n_8\,
      Q(5) => \pipe_lane[2].pipe_user_i_n_9\,
      Q(4) => \pipe_lane[2].pipe_user_i_n_10\,
      Q(3) => \pipe_lane[2].pipe_user_i_n_11\,
      Q(2) => \pipe_lane[2].pipe_user_i_n_12\,
      Q(1) => \pipe_lane[2].pipe_user_i_n_13\,
      Q(0) => \cplllock_reg1_reg[2]\,
      RST_CPLLRESET => \p_0_in__0\,
      RST_PHYSTATUS(0) => p_294_out,
      RST_RATE_IDLE(0) => rate_idle(2),
      RST_RESETDONE(0) => p_329_out,
      RST_RXCDRLOCK(0) => p_327_out,
      RST_RXUSRCLK_RESET => rst_rxusrclk_reset,
      USER_OOBCLK => \pipe_lane[2].pipe_user_i_n_7\,
      USER_RATE_DONE => \pipe_lane[2].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[2].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[2].pipe_rate.pipe_rate_i_n_5\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[2].pipe_eq.pipe_eq_i_n_17\,
      USER_RXRESETDONE => \pipe_lane[2].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[2].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[2]\ => \pipe_lane[2].pipe_user_i_n_18\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(2),
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(2),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_1,
      gt_rxvalid_q_reg_0 => gt_rxvalid_q_reg_9,
      out1(0) => \^out\(0),
      p_0_in7_in => p_0_in7_in_4,
      p_0_in7_in_1 => p_0_in7_in,
      p_0_in7_in_3 => p_0_in7_in_7,
      p_1_in8_in => p_1_in8_in_5,
      p_1_in8_in_0 => p_1_in8_in,
      p_1_in8_in_2 => p_1_in8_in_6,
      p_2_in => p_2_in_3,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_rxstatus(0) => \^pipe_rxstatus\(8),
      pipe_txphaligndone(1) => \^pipe_txphaligndone\(2),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(0),
      pipe_txphinitdone(2 downto 1) => \^pipe_txphinitdone\(3 downto 2),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(0),
      rate_gen3(0) => rate_gen3(2),
      \resetovrd_disble.reset_reg[4]_0\ => \pipe_lane[2].gt_wrapper_i_n_16\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[2].gt_wrapper_i_n_6\,
      resetovrd_done_reg1_reg => \pipe_lane[2].pipe_user_i_n_19\,
      txelecidle_reg2_reg_0 => \pipe_lane[1].pipe_user_i_n_4\,
      txphaligndone_reg1_reg => \pipe_lane[2].pipe_user_i_n_0\,
      txphinitdone_reg1_reg => \pipe_lane[2].pipe_user_i_n_3\,
      txphinitdone_reg1_reg_0 => \pipe_lane[2].pipe_user_i_n_4\,
      user_active_lane(0) => user_active_lane(2),
      user_rx_converge(0) => p_322_out
    );
\pipe_lane[3].gt_wrapper_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_41
     port map (
      DRPADDR(8) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_30\,
      GT_RXPMARESET071_out => GT_RXPMARESET071_out,
      GT_TXPMARESET074_out => \^gt_txpmareset074_out\,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(7 downto 6),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(3),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(3),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(3),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(63 downto 48),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(7 downto 6),
      PIPE_TXDEEMPH(0) => PIPE_TXDEEMPH(1),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(3),
      Q(1 downto 0) => Q(1 downto 0),
      RATE_CPLLLOCK => \^qrst_cplllock\(3),
      RATE_PHYSTATUS => p_241_out,
      RATE_RXRATEDONE => \pipe_lane[3].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[3].gt_wrapper_i_n_20\,
      RST_CPLLRESET => \p_0_in__0\,
      RXCHBONDO(4 downto 0) => \gt_rxchbondo[1]_0\(4 downto 0),
      RXRATE(2) => \pipe_lane[3].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[3].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[3].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[3].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[3].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[3].pipe_sync_i_n_14\,
      TXMAINCURSOR(6) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_4\,
      USER_EYESCANRESET => \pipe_lane[3].pipe_user_i_n_9\,
      USER_OOBCLK => \pipe_lane[3].pipe_user_i_n_6\,
      USER_RXBUFRESET => \pipe_lane[3].pipe_user_i_n_7\,
      USER_RXCDRFREQRESET => \pipe_lane[3].pipe_user_i_n_11\,
      USER_RXCDRRESET => \pipe_lane[3].pipe_user_i_n_12\,
      USER_RXDFELPMRESET => \pipe_lane[3].pipe_user_i_n_10\,
      USER_RXPCSRESET => \pipe_lane[3].pipe_user_i_n_8\,
      USER_RXRESETDONE => \pipe_lane[3].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[3].gt_wrapper_i_n_21\,
      converge_gen3_reg => \pipe_lane[6].pipe_user_i_n_5\,
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(63 downto 48),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(3),
      \fsm_reg[0]\ => \pipe_lane[3].pipe_drp.pipe_drp_i_n_13\,
      \fsm_reg[2]\ => \pipe_lane[3].pipe_drp.pipe_drp_i_n_12\,
      gen3_reg => \pipe_lane[3].pipe_rate.pipe_rate_i_n_14\,
      gen3_reg_0 => \pipe_lane[3].pipe_rate.pipe_rate_i_n_12\,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(3),
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_3\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_1\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_1\(15 downto 0),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_10,
      p_0_in75_in => p_0_in75_in,
      p_0_in77_in => p_0_in77_in,
      pci_exp_rxn(0) => pci_exp_rxn(3),
      pci_exp_rxp(0) => pci_exp_rxp(3),
      pci_exp_txn(0) => pci_exp_txn(3),
      pci_exp_txp(0) => pci_exp_txp(3),
      pclk_sel_reg => \^clk_oobclk\,
      pipe_dmonitorout(7 downto 0) => pipe_dmonitorout(31 downto 24),
      pipe_eyescandataerror(0) => pipe_eyescandataerror(3),
      pipe_rxbufstatus(2 downto 0) => pipe_rxbufstatus(11 downto 9),
      pipe_rxcommadet(0) => pipe_rxcommadet(3),
      pipe_rxdisperr(7 downto 0) => pipe_rxdisperr(31 downto 24),
      pipe_rxdlysresetdone(0) => \^pipe_rxdlysresetdone\(3),
      pipe_rxnotintable(7 downto 0) => pipe_rxnotintable(31 downto 24),
      pipe_rxoutclk_out(0) => pipe_rxoutclk_out(3),
      pipe_rxphaligndone(0) => \^pipe_rxphaligndone\(2),
      pipe_rxprbserr(0) => pipe_rxprbserr(3),
      pipe_rxstatus(2 downto 0) => \^pipe_rxstatus\(11 downto 9),
      \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(2 downto 0),
      \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\ => \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\,
      pipe_txdlysresetdone(0) => \^pipe_txdlysresetdone\(3),
      pipe_txinhibit(0) => pipe_txinhibit(3),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(3),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(3),
      \pl_ltssm_state_q_reg[4]\ => \pl_ltssm_state_q_reg[4]\,
      qpllpd_reg => \^cplllock_reg1_reg[3]\,
      qpllpd_reg_0 => \^cplllock_reg1_reg[3]_0\,
      \resetovrd_disble.fsm_reg[1]\ => \pipe_lane[3].pipe_user_i_n_17\,
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      \resetovrd_disble.reset_reg[4]_0\(5 downto 2) => \^pipe_rxphaligndone\(6 downto 3),
      \resetovrd_disble.reset_reg[4]_0\(1 downto 0) => \^pipe_rxphaligndone\(1 downto 0),
      rst_cpllpd => rst_cpllpd,
      rst_gtreset => rst_gtreset,
      rxcdrlock_reg1_reg => \pipe_lane[3].gt_wrapper_i_n_6\,
      rxphaligndone_s_reg1_reg => \pipe_lane[3].gt_wrapper_i_n_86\,
      rxsync_donem_reg2_reg => \pipe_lane[3].pipe_sync_i_n_18\,
      \rxsync_fsm_disable.fsm_rx_reg[2]\ => \pipe_lane[3].pipe_sync_i_n_19\,
      rxvalid_reg1_reg => \pipe_lane[3].gt_wrapper_i_n_16\,
      sys_clk => sys_clk,
      \txsync_fsm.fsm_tx_reg[2]\ => \pipe_lane[3].pipe_sync_i_n_15\,
      \txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[3].pipe_sync_i_n_17\,
      \txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[3].pipe_sync_i_n_16\,
      \txsync_fsm.txdlyen_reg\ => \pipe_lane[3].pipe_sync_i_n_6\,
      \userrdy_reg_rep__2\ => \pipe_reset.pipe_reset_i_n_20\
    );
\pipe_lane[3].pipe_drp.pipe_drp_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_42
     port map (
      DRPADDR(8) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[3].pipe_drp.pipe_drp_i_n_30\,
      DRP_DONE => p_259_out,
      DRP_START => DRP_START082_out,
      DRP_X16 => DRP_X16084_out,
      DRP_X16X20_MODE => DRP_X16X20_MODE086_out,
      Q(2 downto 0) => \index_reg[1]_1\(2 downto 0),
      RST_DCLK_RESET => rst_dclk_reset,
      \cplllock_reg1_reg[3]\ => \pipe_lane[3].pipe_drp.pipe_drp_i_n_12\,
      \cplllock_reg1_reg[3]_0\ => \pipe_lane[3].pipe_drp.pipe_drp_i_n_13\,
      ext_ch_gt_drpaddr(8 downto 0) => ext_ch_gt_drpaddr(35 downto 27),
      ext_ch_gt_drpdi(15 downto 0) => ext_ch_gt_drpdi(63 downto 48),
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(63 downto 48),
      ext_ch_gt_drpen(0) => ext_ch_gt_drpen(3),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(3),
      ext_ch_gt_drpwe(0) => ext_ch_gt_drpwe(3),
      gt_ch_drp_rdy(0) => gt_ch_drp_rdy(3),
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_gtreset => rst_gtreset
    );
\pipe_lane[3].pipe_eq.pipe_eq_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_43
     port map (
      RST_CPLLRESET => \p_0_in__0\,
      TXMAINCURSOR(6) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[3].pipe_eq.pipe_eq_i_n_4\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[3].pipe_eq.pipe_eq_i_n_17\,
      pclk_sel_reg => \^clk_oobclk\,
      rate_gen3(0) => rate_gen3(3)
    );
\pipe_lane[3].pipe_rate.pipe_rate_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_44
     port map (
      DRP_START082_out => DRP_START082_out,
      DRP_X16084_out => DRP_X16084_out,
      DRP_X16X20_MODE086_out => DRP_X16X20_MODE086_out,
      GT_TXPMARESET074_out => \^gt_txpmareset074_out\,
      Q(4 downto 0) => \sysclksel_reg[1]_1\(4 downto 0),
      QRST_QPLLPD_IN(0) => p_268_out,
      QRST_QPLLRESET_IN(0) => p_267_out,
      RATE_CPLLLOCK => \^qrst_cplllock\(3),
      RATE_DRP_DONE => p_259_out,
      RATE_PHYSTATUS => p_241_out,
      RATE_RESETOVRD_DONE => \pipe_lane[3].pipe_user_i_n_18\,
      RATE_RXRATEDONE => \pipe_lane[3].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[3].gt_wrapper_i_n_20\,
      RATE_TXSYNC_DONE => p_262_out,
      RST_CPLLRESET => \p_0_in__0\,
      RST_DRP_START => rst_drp_start,
      RST_DRP_X16 => rst_drp_x16,
      RST_DRP_X16X20_MODE => rst_drp_x16x20_mode,
      RST_RATE_IDLE(0) => rate_idle(3),
      RXRATE(2) => \pipe_lane[3].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[3].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[3].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[3].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[3].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[3].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[3].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START080_out,
      USER_PCLK_SEL => \^clk_pclk_sel\(3),
      USER_RATE_DONE => \pipe_lane[3].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[3].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[3].pipe_rate.pipe_rate_i_n_5\,
      USER_RXRESETDONE => \pipe_lane[3].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[3].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[3]\ => \pipe_lane[3].pipe_rate.pipe_rate_i_n_12\,
      \cplllock_reg1_reg[3]_0\ => \pipe_lane[3].pipe_rate.pipe_rate_i_n_14\,
      out1(1) => \^out\(0),
      out1(0) => rst_txsync_start,
      p_0_in75_in => p_0_in75_in,
      p_0_in77_in => p_0_in77_in,
      p_0_in7_in => p_0_in7_in_7,
      p_1_in8_in => p_1_in8_in_6,
      pclk_sel_reg_0 => \^clk_oobclk\,
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      qpllpd_reg_0 => \^qrst_qplllock\(0),
      rate_gen3(0) => rate_gen3(3),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\
    );
\pipe_lane[3].pipe_sync_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_45
     port map (
      Q(5 downto 0) => \txsync_fsm.txdlyen_reg_1\(5 downto 0),
      RST_CPLLRESET => \p_0_in__0\,
      RST_RATE_IDLE(0) => rate_idle(3),
      RST_TXSYNC_DONE(0) => p_262_out,
      SYNC_GEN3 => rate_gen3(3),
      SYNC_RXCDRLOCK => p_274_out,
      SYNC_RXDLYEN => \pipe_lane[3].pipe_sync_i_n_14\,
      SYNC_RXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_90\,
      SYNC_RXSYNC_DONEM_IN => \pipe_lane[0].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[3].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_89\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START080_out,
      \cplllock_reg1_reg[3]\ => \pipe_lane[3].pipe_sync_i_n_15\,
      \cplllock_reg1_reg[3]_0\ => \pipe_lane[3].pipe_sync_i_n_16\,
      \cplllock_reg1_reg[3]_1\ => \pipe_lane[3].pipe_sync_i_n_17\,
      \cplllock_reg1_reg[3]_2\ => \pipe_lane[3].pipe_sync_i_n_18\,
      \cplllock_reg1_reg[3]_3\ => \pipe_lane[3].pipe_sync_i_n_19\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(3),
      p_0_in7_in => p_0_in7_in_7,
      p_1_in8_in => p_1_in8_in_6,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_sync_fsm_rx(6 downto 0) => pipe_sync_fsm_rx(27 downto 21),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\,
      \resetovrd_disble.reset_reg[4]_0\ => \^sync_rxphaligndone_m\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[3].gt_wrapper_i_n_86\,
      txelecidle_reg2_reg => \pipe_lane[4].pipe_user_i_n_0\,
      \txsync_fsm.txdlyen_reg_0\ => \pipe_lane[3].pipe_sync_i_n_6\,
      txsyncallin => txsyncallin
    );
\pipe_lane[3].pipe_user_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_46
     port map (
      CLK_PCLK_SEL(0) => \^clk_pclk_sel\(3),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(3),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(3),
      Q(6) => \pipe_lane[3].pipe_user_i_n_7\,
      Q(5) => \pipe_lane[3].pipe_user_i_n_8\,
      Q(4) => \pipe_lane[3].pipe_user_i_n_9\,
      Q(3) => \pipe_lane[3].pipe_user_i_n_10\,
      Q(2) => \pipe_lane[3].pipe_user_i_n_11\,
      Q(1) => \pipe_lane[3].pipe_user_i_n_12\,
      Q(0) => \cplllock_reg1_reg[3]_1\,
      RST_CPLLRESET => \p_0_in__0\,
      RST_PHYSTATUS(0) => p_241_out,
      RST_RATE_IDLE(0) => rate_idle(3),
      RST_RESETDONE(0) => p_276_out,
      RST_RXCDRLOCK(0) => p_274_out,
      RST_RXUSRCLK_RESET => rst_rxusrclk_reset,
      USER_OOBCLK => \pipe_lane[3].pipe_user_i_n_6\,
      USER_RATE_DONE => \pipe_lane[3].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[3].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[3].pipe_rate.pipe_rate_i_n_5\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[3].pipe_eq.pipe_eq_i_n_17\,
      USER_RXRESETDONE => \pipe_lane[3].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[3].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[3]\ => \pipe_lane[3].pipe_user_i_n_17\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(3),
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(3),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_2,
      gt_rxvalid_q_reg_0 => gt_rxvalid_q_reg_10,
      out1(0) => \^out\(0),
      p_0_in7_in => p_0_in7_in_7,
      p_1_in8_in => p_1_in8_in_6,
      p_2_in => p_2_in_8,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_rxstatus(0) => \^pipe_rxstatus\(11),
      pipe_txphaligndone(1) => \^pipe_txphaligndone\(2),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(0),
      rate_gen3(0) => rate_gen3(3),
      \resetovrd_disble.reset_reg[4]_0\ => \pipe_lane[3].gt_wrapper_i_n_16\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[3].gt_wrapper_i_n_6\,
      resetovrd_done_reg1_reg => \pipe_lane[3].pipe_user_i_n_18\,
      txcompliance_reg2_reg_0 => \pipe_lane[1].pipe_user_i_n_3\,
      txelecidle_reg2_reg_0(1) => user_active_lane(2),
      txelecidle_reg2_reg_0(0) => user_active_lane(0),
      txphaligndone_reg1_reg => \pipe_lane[3].pipe_user_i_n_0\,
      user_active_lane(0) => user_active_lane(3),
      user_rx_converge(0) => p_269_out
    );
\pipe_lane[4].gt_wrapper_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_47
     port map (
      DRPADDR(8) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_30\,
      GT_RXPMARESET061_out => GT_RXPMARESET061_out,
      GT_RX_CONVERGE0 => \pipe_lane[6].pipe_user_i_n_3\,
      GT_TXPMARESET064_out => \^gt_txpmareset064_out\,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(9 downto 8),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(4),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(4),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(4),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(79 downto 64),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(9 downto 8),
      PIPE_TXDEEMPH(0) => PIPE_TXDEEMPH(2),
      PIPE_TXDETECTRX => PIPE_TXDETECTRX,
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(4),
      PIPE_TXMARGIN(2 downto 0) => PIPE_TXMARGIN(2 downto 0),
      Q(1 downto 0) => Q(1 downto 0),
      RATE_CPLLLOCK => \^qrst_cplllock\(4),
      RATE_PHYSTATUS => p_184_out,
      RATE_RXRATEDONE => \pipe_lane[4].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[4].gt_wrapper_i_n_20\,
      RST_CPLLRESET => \p_0_in__0\,
      RXCHBONDO(4 downto 0) => \gt_rxchbondo[1]_0\(4 downto 0),
      RXRATE(2) => \pipe_lane[4].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[4].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[4].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[4].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[4].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[4].pipe_sync_i_n_14\,
      TXMAINCURSOR(6) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_4\,
      USER_EYESCANRESET => \pipe_lane[4].pipe_user_i_n_9\,
      USER_OOBCLK => \pipe_lane[4].pipe_user_i_n_6\,
      USER_RXBUFRESET => \pipe_lane[4].pipe_user_i_n_7\,
      USER_RXCDRFREQRESET => \pipe_lane[4].pipe_user_i_n_11\,
      USER_RXCDRRESET => \pipe_lane[4].pipe_user_i_n_12\,
      USER_RXDFELPMRESET => \pipe_lane[4].pipe_user_i_n_10\,
      USER_RXPCSRESET => \pipe_lane[4].pipe_user_i_n_8\,
      USER_RXRESETDONE => \pipe_lane[4].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[4].gt_wrapper_i_n_21\,
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(79 downto 64),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(4),
      \fsm_reg[0]\ => \pipe_lane[4].pipe_drp.pipe_drp_i_n_13\,
      \fsm_reg[2]\ => \pipe_lane[4].pipe_drp.pipe_drp_i_n_12\,
      gen3_reg => \pipe_lane[4].pipe_rate.pipe_rate_i_n_14\,
      gen3_reg_0 => \pipe_lane[4].pipe_rate.pipe_rate_i_n_12\,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(4),
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_2\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_2\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_2\(15 downto 0),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_11,
      p_0_in65_in => p_0_in65_in,
      p_0_in67_in => p_0_in67_in,
      pci_exp_rxn(0) => pci_exp_rxn(4),
      pci_exp_rxp(0) => pci_exp_rxp(4),
      pci_exp_txn(0) => pci_exp_txn(4),
      pci_exp_txp(0) => pci_exp_txp(4),
      pclk_sel_reg => \^clk_oobclk\,
      pipe_dmonitorout(7 downto 0) => pipe_dmonitorout(39 downto 32),
      pipe_eyescandataerror(0) => pipe_eyescandataerror(4),
      pipe_rxbufstatus(2 downto 0) => pipe_rxbufstatus(14 downto 12),
      pipe_rxcommadet(0) => pipe_rxcommadet(4),
      pipe_rxdisperr(7 downto 0) => pipe_rxdisperr(39 downto 32),
      pipe_rxdlysresetdone(0) => \^pipe_rxdlysresetdone\(4),
      pipe_rxnotintable(7 downto 0) => pipe_rxnotintable(39 downto 32),
      pipe_rxoutclk_out(0) => pipe_rxoutclk_out(4),
      pipe_rxphaligndone(0) => \^pipe_rxphaligndone\(3),
      pipe_rxprbserr(0) => pipe_rxprbserr(4),
      pipe_rxstatus(2 downto 0) => \^pipe_rxstatus\(14 downto 12),
      pipe_txdlysresetdone(0) => \^pipe_txdlysresetdone\(4),
      pipe_txinhibit(0) => pipe_txinhibit(4),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(4),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(4),
      \pl_ltssm_state_q_reg[4]\ => \pl_ltssm_state_q_reg[4]\,
      qpllpd_reg => \^cplllock_reg1_reg[7]\,
      qpllpd_reg_0 => \^cplllock_reg1_reg[7]_0\,
      \resetovrd_disble.fsm_reg[1]\ => \pipe_lane[4].pipe_user_i_n_17\,
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_cpllpd => rst_cpllpd,
      rst_gtreset => rst_gtreset,
      rxcdrlock_reg1_reg => \pipe_lane[4].gt_wrapper_i_n_6\,
      rxsync_donem_reg2_reg => \pipe_lane[4].pipe_sync_i_n_18\,
      \rxsync_fsm_disable.fsm_rx_reg[2]\ => \pipe_lane[4].pipe_sync_i_n_19\,
      rxvalid_reg1_reg => \pipe_lane[4].gt_wrapper_i_n_16\,
      sys_clk => sys_clk,
      \txsync_fsm.fsm_tx_reg[2]\ => \pipe_lane[4].pipe_sync_i_n_15\,
      \txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[4].pipe_sync_i_n_17\,
      \txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[4].pipe_sync_i_n_16\,
      \txsync_fsm.txdlyen_reg\ => \pipe_lane[4].pipe_sync_i_n_6\,
      \userrdy_reg_rep__1\ => \pipe_reset.pipe_reset_i_n_19\
    );
\pipe_lane[4].pipe_drp.pipe_drp_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_48
     port map (
      DRPADDR(8) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[4].pipe_drp.pipe_drp_i_n_30\,
      DRP_DONE => p_206_out,
      DRP_START => DRP_START0130_out,
      DRP_X16 => DRP_X160132_out,
      DRP_X16X20_MODE => DRP_X16X20_MODE0134_out,
      Q(2 downto 0) => \index_reg[1]_2\(2 downto 0),
      RST_DCLK_RESET => rst_dclk_reset,
      \cplllock_reg1_reg[4]\ => \pipe_lane[4].pipe_drp.pipe_drp_i_n_12\,
      \cplllock_reg1_reg[4]_0\ => \pipe_lane[4].pipe_drp.pipe_drp_i_n_13\,
      ext_ch_gt_drpaddr(8 downto 0) => ext_ch_gt_drpaddr(44 downto 36),
      ext_ch_gt_drpdi(15 downto 0) => ext_ch_gt_drpdi(79 downto 64),
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(79 downto 64),
      ext_ch_gt_drpen(0) => ext_ch_gt_drpen(4),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(4),
      ext_ch_gt_drpwe(0) => ext_ch_gt_drpwe(4),
      gt_ch_drp_rdy(0) => gt_ch_drp_rdy(4),
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_gtreset => rst_gtreset
    );
\pipe_lane[4].pipe_eq.pipe_eq_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_49
     port map (
      RST_CPLLRESET => \p_0_in__0\,
      TXMAINCURSOR(6) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[4].pipe_eq.pipe_eq_i_n_4\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[4].pipe_eq.pipe_eq_i_n_17\,
      pclk_sel_reg => \^clk_oobclk\,
      rate_gen3(0) => rate_gen3(4)
    );
\pipe_lane[4].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_common_50
     port map (
      DRP_DONE => p_196_out,
      DRP_GEN3 => \pipe_lane[6].pipe_rate.pipe_rate_i_n_14\,
      DRP_OVRD => qrst_ovrd,
      DRP_START => \qpll_reset.qpll_reset_i_n_4\,
      RATE_QPLLLOCK => \^qrst_qplllock\(1),
      RST_DCLK_RESET => rst_dclk_reset,
      \cplllock_reg1_reg[7]\ => \^cplllock_reg1_reg[7]\,
      \cplllock_reg1_reg[7]_0\ => \^cplllock_reg1_reg[7]_0\,
      qpllpd => qpllpd,
      qrst_qpllreset => qrst_qpllreset,
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      sys_clk => sys_clk
    );
\pipe_lane[4].pipe_rate.pipe_rate_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_51
     port map (
      DRP_START0130_out => DRP_START0130_out,
      DRP_X160132_out => DRP_X160132_out,
      DRP_X16X20_MODE0134_out => DRP_X16X20_MODE0134_out,
      GT_TXPMARESET064_out => \^gt_txpmareset064_out\,
      Q(4 downto 0) => \sysclksel_reg[1]_2\(4 downto 0),
      QRST_QPLLPD_IN(0) => p_215_out,
      QRST_QPLLRESET_IN(0) => p_214_out,
      RATE_CPLLLOCK => \^qrst_cplllock\(4),
      RATE_DRP_DONE => p_206_out,
      RATE_PHYSTATUS => p_184_out,
      RATE_QPLLLOCK => \^qrst_qplllock\(1),
      RATE_RESETOVRD_DONE => \pipe_lane[4].pipe_user_i_n_18\,
      RATE_RXRATEDONE => \pipe_lane[4].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[4].gt_wrapper_i_n_20\,
      RATE_TXSYNC_DONE => p_209_out,
      RST_CPLLRESET => \p_0_in__0\,
      RST_DRP_START => rst_drp_start,
      RST_DRP_X16 => rst_drp_x16,
      RST_DRP_X16X20_MODE => rst_drp_x16x20_mode,
      RST_RATE_IDLE(0) => rate_idle(4),
      RXRATE(2) => \pipe_lane[4].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[4].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[4].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[4].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[4].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[4].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[4].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0128_out,
      USER_PCLK_SEL => \^clk_pclk_sel\(4),
      USER_RATE_DONE => \pipe_lane[4].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[4].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[4].pipe_rate.pipe_rate_i_n_5\,
      USER_RXRESETDONE => \pipe_lane[4].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[4].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[4]\ => \pipe_lane[4].pipe_rate.pipe_rate_i_n_12\,
      \cplllock_reg1_reg[4]_0\ => \pipe_lane[4].pipe_rate.pipe_rate_i_n_14\,
      out1(1) => \^out\(0),
      out1(0) => rst_txsync_start,
      p_0_in65_in => p_0_in65_in,
      p_0_in67_in => p_0_in67_in,
      p_0_in7_in => p_0_in7_in_11,
      p_1_in8_in => p_1_in8_in_10,
      pclk_sel_reg_0 => \^clk_oobclk\,
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      rate_gen3(0) => rate_gen3(4),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\
    );
\pipe_lane[4].pipe_sync_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_52
     port map (
      Q(5 downto 0) => \txsync_fsm.txdlyen_reg_2\(5 downto 0),
      RST_CPLLRESET => \p_0_in__0\,
      RST_RATE_IDLE(0) => rate_idle(4),
      RST_TXSYNC_DONE(0) => p_209_out,
      SYNC_GEN3 => rate_gen3(4),
      SYNC_RXCDRLOCK => p_221_out,
      SYNC_RXDLYEN => \pipe_lane[4].pipe_sync_i_n_14\,
      SYNC_RXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_90\,
      SYNC_RXSYNC_START => \pipe_lane[4].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_89\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0128_out,
      \cplllock_reg1_reg[4]\ => \pipe_lane[4].pipe_sync_i_n_15\,
      \cplllock_reg1_reg[4]_0\ => \pipe_lane[4].pipe_sync_i_n_16\,
      \cplllock_reg1_reg[4]_1\ => \pipe_lane[4].pipe_sync_i_n_17\,
      \cplllock_reg1_reg[4]_2\ => \pipe_lane[4].pipe_sync_i_n_18\,
      \cplllock_reg1_reg[4]_3\ => \pipe_lane[4].pipe_sync_i_n_19\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(4),
      p_0_in7_in => p_0_in7_in_11,
      p_1_in8_in => p_1_in8_in_10,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_sync_fsm_rx(6 downto 0) => pipe_sync_fsm_rx(34 downto 28),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\,
      \resetovrd_disble.reset_reg[4]_0\ => \^sync_rxphaligndone_m\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[3].gt_wrapper_i_n_86\,
      \rxsync_fsm_disable.fsm_rx_reg[2]_0\ => \pipe_lane[0].pipe_sync_i_n_14\,
      txelecidle_reg2_reg => \pipe_lane[4].pipe_user_i_n_0\,
      \txsync_fsm.txdlyen_reg_0\ => \pipe_lane[4].pipe_sync_i_n_6\,
      txsyncallin => txsyncallin
    );
\pipe_lane[4].pipe_user_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_53
     port map (
      CLK_PCLK_SEL(0) => \^clk_pclk_sel\(4),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(4),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(4),
      Q(6) => \pipe_lane[4].pipe_user_i_n_7\,
      Q(5) => \pipe_lane[4].pipe_user_i_n_8\,
      Q(4) => \pipe_lane[4].pipe_user_i_n_9\,
      Q(3) => \pipe_lane[4].pipe_user_i_n_10\,
      Q(2) => \pipe_lane[4].pipe_user_i_n_11\,
      Q(1) => \pipe_lane[4].pipe_user_i_n_12\,
      Q(0) => \cplllock_reg1_reg[4]\,
      RST_CPLLRESET => \p_0_in__0\,
      RST_PHYSTATUS(0) => p_184_out,
      RST_RATE_IDLE(0) => rate_idle(4),
      RST_RESETDONE(0) => p_223_out,
      RST_RXCDRLOCK(0) => p_221_out,
      RST_RXUSRCLK_RESET => rst_rxusrclk_reset,
      USER_OOBCLK => \pipe_lane[4].pipe_user_i_n_6\,
      USER_RATE_DONE => \pipe_lane[4].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[4].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[4].pipe_rate.pipe_rate_i_n_5\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[4].pipe_eq.pipe_eq_i_n_17\,
      USER_RXRESETDONE => \pipe_lane[4].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[4].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[4]\ => \pipe_lane[4].pipe_user_i_n_17\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(4),
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(4),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_3,
      gt_rxvalid_q_reg_0 => gt_rxvalid_q_reg_11,
      out1(0) => \^out\(0),
      p_0_in7_in => p_0_in7_in_11,
      p_0_in7_in_1 => p_0_in7_in_13,
      p_1_in8_in => p_1_in8_in_10,
      p_1_in8_in_0 => p_1_in8_in_12,
      p_216_out => p_216_out,
      p_2_in => p_2_in_9,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_rxstatus(0) => \^pipe_rxstatus\(14),
      pipe_txphaligndone(1 downto 0) => \^pipe_txphaligndone\(5 downto 4),
      pipe_txphinitdone(2 downto 1) => \^pipe_txphinitdone\(5 downto 4),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(0),
      rate_gen3(0) => rate_gen3(4),
      \resetovrd_disble.reset_reg[4]_0\ => \pipe_lane[4].gt_wrapper_i_n_16\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[4].gt_wrapper_i_n_6\,
      resetovrd_done_reg1_reg => \pipe_lane[4].pipe_user_i_n_18\,
      txcompliance_reg2_reg_0 => \pipe_lane[2].pipe_user_i_n_3\,
      txelecidle_reg2_reg_0 => \pipe_lane[7].pipe_user_i_n_0\,
      txelecidle_reg2_reg_1 => \pipe_lane[0].pipe_user_i_n_0\,
      txphaligndone_reg1_reg => \pipe_lane[4].pipe_user_i_n_3\,
      txphinitdone_reg1_reg => \pipe_lane[4].pipe_user_i_n_0\,
      user_active_lane(0) => user_active_lane(5)
    );
\pipe_lane[5].gt_wrapper_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_54
     port map (
      DRPADDR(8) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_30\,
      GT_RXPMARESET043_out => GT_RXPMARESET043_out,
      GT_TXPMARESET046_out => \^gt_txpmareset046_out\,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(11 downto 10),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(5),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(5),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(5),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(95 downto 80),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(11 downto 10),
      PIPE_TXDEEMPH(0) => PIPE_TXDEEMPH(2),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(5),
      Q(1 downto 0) => Q(1 downto 0),
      RATE_CPLLLOCK => \^qrst_cplllock\(5),
      RATE_PHYSTATUS => p_131_out,
      RATE_RXRATEDONE => \pipe_lane[5].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[5].gt_wrapper_i_n_20\,
      RST_CPLLRESET => \p_0_in__0\,
      RXCHBONDO(4 downto 0) => \gt_rxchbondo[1]_0\(4 downto 0),
      RXRATE(2) => \pipe_lane[5].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[5].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[5].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[5].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[5].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[5].pipe_sync_i_n_14\,
      TXMAINCURSOR(6) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_4\,
      USER_EYESCANRESET => \pipe_lane[5].pipe_user_i_n_7\,
      USER_OOBCLK => \pipe_lane[5].pipe_user_i_n_4\,
      USER_RXBUFRESET => \pipe_lane[5].pipe_user_i_n_5\,
      USER_RXCDRFREQRESET => \pipe_lane[5].pipe_user_i_n_9\,
      USER_RXCDRRESET => \pipe_lane[5].pipe_user_i_n_10\,
      USER_RXDFELPMRESET => \pipe_lane[5].pipe_user_i_n_8\,
      USER_RXPCSRESET => \pipe_lane[5].pipe_user_i_n_6\,
      USER_RXRESETDONE => \pipe_lane[5].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[5].gt_wrapper_i_n_21\,
      converge_gen3_reg => \pipe_lane[6].pipe_user_i_n_6\,
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(95 downto 80),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(5),
      \fsm_reg[0]\ => \pipe_lane[5].pipe_drp.pipe_drp_i_n_13\,
      \fsm_reg[2]\ => \pipe_lane[5].pipe_drp.pipe_drp_i_n_12\,
      gen3_reg => \pipe_lane[5].pipe_rate.pipe_rate_i_n_14\,
      gen3_reg_0 => \pipe_lane[5].pipe_rate.pipe_rate_i_n_12\,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(5),
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_1\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_3\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_3\(15 downto 0),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_12,
      p_0_in47_in => p_0_in47_in,
      p_0_in49_in => p_0_in49_in,
      pci_exp_rxn(0) => pci_exp_rxn(5),
      pci_exp_rxp(0) => pci_exp_rxp(5),
      pci_exp_txn(0) => pci_exp_txn(5),
      pci_exp_txp(0) => pci_exp_txp(5),
      pclk_sel_reg => \^clk_oobclk\,
      pipe_dmonitorout(7 downto 0) => pipe_dmonitorout(47 downto 40),
      pipe_eyescandataerror(0) => pipe_eyescandataerror(5),
      pipe_rxbufstatus(2 downto 0) => pipe_rxbufstatus(17 downto 15),
      pipe_rxcommadet(0) => pipe_rxcommadet(5),
      pipe_rxdisperr(7 downto 0) => pipe_rxdisperr(47 downto 40),
      pipe_rxdlysresetdone(0) => \^pipe_rxdlysresetdone\(5),
      pipe_rxnotintable(7 downto 0) => pipe_rxnotintable(47 downto 40),
      pipe_rxoutclk_out(0) => pipe_rxoutclk_out(5),
      pipe_rxphaligndone(0) => \^pipe_rxphaligndone\(4),
      pipe_rxprbserr(0) => pipe_rxprbserr(5),
      pipe_rxstatus(2 downto 0) => \^pipe_rxstatus\(17 downto 15),
      \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0),
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_txdlysresetdone(0) => \^pipe_txdlysresetdone\(5),
      pipe_txinhibit(0) => pipe_txinhibit(5),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(5),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(5),
      \pl_ltssm_state_q_reg[4]\ => \pl_ltssm_state_q_reg[4]\,
      qpllpd_reg => \^cplllock_reg1_reg[7]\,
      qpllpd_reg_0 => \^cplllock_reg1_reg[7]_0\,
      \resetovrd_disble.fsm_reg[1]\ => \pipe_lane[5].pipe_user_i_n_15\,
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_cpllpd => rst_cpllpd,
      rst_gtreset => rst_gtreset,
      rxcdrlock_reg1_reg => \pipe_lane[5].gt_wrapper_i_n_6\,
      rxsync_donem_reg2_reg => \pipe_lane[5].pipe_sync_i_n_18\,
      \rxsync_fsm_disable.fsm_rx_reg[2]\ => \pipe_lane[5].pipe_sync_i_n_19\,
      rxvalid_reg1_reg => \pipe_lane[5].gt_wrapper_i_n_16\,
      sys_clk => sys_clk,
      \txsync_fsm.fsm_tx_reg[2]\ => \pipe_lane[5].pipe_sync_i_n_15\,
      \txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[5].pipe_sync_i_n_17\,
      \txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[5].pipe_sync_i_n_16\,
      \txsync_fsm.txdlyen_reg\ => \pipe_lane[5].pipe_sync_i_n_6\,
      \userrdy_reg_rep__0\ => \pipe_reset.pipe_reset_i_n_18\
    );
\pipe_lane[5].pipe_drp.pipe_drp_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_55
     port map (
      DRPADDR(8) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[5].pipe_drp.pipe_drp_i_n_30\,
      DRP_DONE => p_149_out,
      DRP_START => DRP_START054_out,
      DRP_X16 => DRP_X16056_out,
      DRP_X16X20_MODE => DRP_X16X20_MODE058_out,
      Q(2 downto 0) => \index_reg[1]_3\(2 downto 0),
      RST_DCLK_RESET => rst_dclk_reset,
      \cplllock_reg1_reg[5]\ => \pipe_lane[5].pipe_drp.pipe_drp_i_n_12\,
      \cplllock_reg1_reg[5]_0\ => \pipe_lane[5].pipe_drp.pipe_drp_i_n_13\,
      ext_ch_gt_drpaddr(8 downto 0) => ext_ch_gt_drpaddr(53 downto 45),
      ext_ch_gt_drpdi(15 downto 0) => ext_ch_gt_drpdi(95 downto 80),
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(95 downto 80),
      ext_ch_gt_drpen(0) => ext_ch_gt_drpen(5),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(5),
      ext_ch_gt_drpwe(0) => ext_ch_gt_drpwe(5),
      gt_ch_drp_rdy(0) => gt_ch_drp_rdy(5),
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_gtreset => rst_gtreset
    );
\pipe_lane[5].pipe_eq.pipe_eq_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_56
     port map (
      RST_CPLLRESET => \p_0_in__0\,
      TXMAINCURSOR(6) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[5].pipe_eq.pipe_eq_i_n_4\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[5].pipe_eq.pipe_eq_i_n_17\,
      pclk_sel_reg => \^clk_oobclk\,
      rate_gen3(0) => rate_gen3(5)
    );
\pipe_lane[5].pipe_rate.pipe_rate_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_57
     port map (
      DRP_START054_out => DRP_START054_out,
      DRP_X16056_out => DRP_X16056_out,
      DRP_X16X20_MODE058_out => DRP_X16X20_MODE058_out,
      GT_TXPMARESET046_out => \^gt_txpmareset046_out\,
      Q(4 downto 0) => \sysclksel_reg[1]_3\(4 downto 0),
      QRST_QPLLPD_IN(0) => p_158_out,
      QRST_QPLLRESET_IN(0) => p_157_out,
      RATE_CPLLLOCK => \^qrst_cplllock\(5),
      RATE_DRP_DONE => p_149_out,
      RATE_PHYSTATUS => p_131_out,
      RATE_QPLLLOCK => \^qrst_qplllock\(1),
      RATE_RESETOVRD_DONE => \pipe_lane[5].pipe_user_i_n_16\,
      RATE_RXRATEDONE => \pipe_lane[5].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[5].gt_wrapper_i_n_20\,
      RATE_TXSYNC_DONE => p_152_out,
      RST_CPLLRESET => \p_0_in__0\,
      RST_DRP_START => rst_drp_start,
      RST_DRP_X16 => rst_drp_x16,
      RST_DRP_X16X20_MODE => rst_drp_x16x20_mode,
      RST_RATE_IDLE(0) => rate_idle(5),
      RXRATE(2) => \pipe_lane[5].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[5].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[5].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[5].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[5].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[5].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[5].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START052_out,
      USER_PCLK_SEL => \^clk_pclk_sel\(5),
      USER_RATE_DONE => \pipe_lane[5].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[5].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[5].pipe_rate.pipe_rate_i_n_5\,
      USER_RXRESETDONE => \pipe_lane[5].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[5].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[5]\ => \pipe_lane[5].pipe_rate.pipe_rate_i_n_12\,
      \cplllock_reg1_reg[5]_0\ => \pipe_lane[5].pipe_rate.pipe_rate_i_n_14\,
      out1(1) => \^out\(0),
      out1(0) => rst_txsync_start,
      p_0_in47_in => p_0_in47_in,
      p_0_in49_in => p_0_in49_in,
      p_0_in7_in => p_0_in7_in_13,
      p_1_in8_in => p_1_in8_in_12,
      pclk_sel_reg_0 => \^clk_oobclk\,
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      rate_gen3(0) => rate_gen3(5),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\
    );
\pipe_lane[5].pipe_sync_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_58
     port map (
      Q(5 downto 0) => \txsync_fsm.txdlyen_reg_3\(5 downto 0),
      RST_CPLLRESET => \p_0_in__0\,
      RST_RATE_IDLE(0) => rate_idle(5),
      RST_TXSYNC_DONE(0) => p_152_out,
      SYNC_GEN3 => rate_gen3(5),
      SYNC_RXCDRLOCK => p_164_out,
      SYNC_RXDLYEN => \pipe_lane[5].pipe_sync_i_n_14\,
      SYNC_RXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_90\,
      SYNC_RXSYNC_START => \pipe_lane[5].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_89\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START052_out,
      \cplllock_reg1_reg[5]\ => \pipe_lane[5].pipe_sync_i_n_15\,
      \cplllock_reg1_reg[5]_0\ => \pipe_lane[5].pipe_sync_i_n_16\,
      \cplllock_reg1_reg[5]_1\ => \pipe_lane[5].pipe_sync_i_n_17\,
      \cplllock_reg1_reg[5]_2\ => \pipe_lane[5].pipe_sync_i_n_18\,
      \cplllock_reg1_reg[5]_3\ => \pipe_lane[5].pipe_sync_i_n_19\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(5),
      p_0_in7_in => p_0_in7_in_13,
      p_1_in8_in => p_1_in8_in_12,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_sync_fsm_rx(6 downto 0) => pipe_sync_fsm_rx(41 downto 35),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\,
      \resetovrd_disble.reset_reg[4]_0\ => \^sync_rxphaligndone_m\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[3].gt_wrapper_i_n_86\,
      \rxsync_fsm_disable.fsm_rx_reg[2]_0\ => \pipe_lane[0].pipe_sync_i_n_14\,
      txelecidle_reg2_reg => \pipe_lane[4].pipe_user_i_n_0\,
      \txsync_fsm.txdlyen_reg_0\ => \pipe_lane[5].pipe_sync_i_n_6\,
      txsyncallin => txsyncallin
    );
\pipe_lane[5].pipe_user_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_59
     port map (
      CLK_PCLK_SEL(0) => \^clk_pclk_sel\(5),
      D => D,
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(5),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(5),
      Q(6) => \pipe_lane[5].pipe_user_i_n_5\,
      Q(5) => \pipe_lane[5].pipe_user_i_n_6\,
      Q(4) => \pipe_lane[5].pipe_user_i_n_7\,
      Q(3) => \pipe_lane[5].pipe_user_i_n_8\,
      Q(2) => \pipe_lane[5].pipe_user_i_n_9\,
      Q(1) => \pipe_lane[5].pipe_user_i_n_10\,
      Q(0) => \cplllock_reg1_reg[5]\,
      RST_CPLLRESET => \p_0_in__0\,
      RST_PHYSTATUS(0) => p_131_out,
      RST_RATE_IDLE(0) => rate_idle(5),
      RST_RESETDONE(0) => p_166_out,
      RST_RXCDRLOCK(0) => p_164_out,
      RST_RXUSRCLK_RESET => rst_rxusrclk_reset,
      USER_OOBCLK => \pipe_lane[5].pipe_user_i_n_4\,
      USER_RATE_DONE => \pipe_lane[5].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[5].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[5].pipe_rate.pipe_rate_i_n_5\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[5].pipe_eq.pipe_eq_i_n_17\,
      USER_RXRESETDONE => \pipe_lane[5].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[5].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[5]\ => \pipe_lane[5].pipe_user_i_n_15\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(5),
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(5),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_4,
      gt_rxvalid_q_reg_0 => gt_rxvalid_q_reg_12,
      out1(0) => \^out\(0),
      p_0_in7_in => p_0_in7_in_13,
      p_159_out => p_159_out,
      p_1_in8_in => p_1_in8_in_12,
      p_2_in => p_2_in_9,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_rxstatus(0) => \^pipe_rxstatus\(17),
      rate_gen3(0) => rate_gen3(5),
      \resetovrd_disble.reset_reg[4]_0\ => \pipe_lane[5].gt_wrapper_i_n_16\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[5].gt_wrapper_i_n_6\,
      resetovrd_done_reg1_reg => \pipe_lane[5].pipe_user_i_n_16\,
      rst_idle_reg2_reg_0 => \pipe_lane[7].pipe_user_i_n_5\,
      user_active_lane(0) => user_active_lane(5)
    );
\pipe_lane[6].gt_wrapper_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_60
     port map (
      DRPADDR(8) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_30\,
      GT_RXPMARESET032_out => GT_RXPMARESET032_out,
      GT_RX_CONVERGE0 => \pipe_lane[6].pipe_user_i_n_3\,
      GT_TXPMARESET035_out => \^gt_txpmareset035_out\,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(13 downto 12),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(6),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(6),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(6),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(111 downto 96),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(13 downto 12),
      PIPE_TXDEEMPH(0) => PIPE_TXDEEMPH(3),
      PIPE_TXDETECTRX => PIPE_TXDETECTRX,
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(6),
      PIPE_TXMARGIN(2 downto 0) => PIPE_TXMARGIN(2 downto 0),
      Q(1 downto 0) => Q(1 downto 0),
      RATE_CPLLLOCK => \^qrst_cplllock\(6),
      RATE_PHYSTATUS => p_78_out,
      RATE_RXRATEDONE => \pipe_lane[6].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[6].gt_wrapper_i_n_20\,
      RST_CPLLRESET => \p_0_in__0\,
      RXCHBONDO(4 downto 0) => \gt_rxchbondo[1]_0\(4 downto 0),
      RXRATE(2) => \pipe_lane[6].pipe_rate.pipe_rate_i_n_18\,
      RXRATE(1) => \pipe_lane[6].pipe_rate.pipe_rate_i_n_19\,
      RXRATE(0) => \pipe_lane[6].pipe_rate.pipe_rate_i_n_20\,
      RXSYSCLKSEL(1) => \pipe_lane[6].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[6].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_90\,
      SYNC_RXSYNC_DONE => \pipe_lane[6].pipe_sync_i_n_14\,
      SYNC_TXDLYSRESETDONE0 => \pipe_lane[6].gt_wrapper_i_n_89\,
      TXMAINCURSOR(6) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_4\,
      USER_EYESCANRESET => \pipe_lane[6].pipe_user_i_n_12\,
      USER_OOBCLK => \pipe_lane[6].pipe_user_i_n_9\,
      USER_RXBUFRESET => \pipe_lane[6].pipe_user_i_n_10\,
      USER_RXCDRFREQRESET => \pipe_lane[6].pipe_user_i_n_14\,
      USER_RXCDRRESET => \pipe_lane[6].pipe_user_i_n_15\,
      USER_RXDFELPMRESET => \pipe_lane[6].pipe_user_i_n_13\,
      USER_RXPCSRESET => \pipe_lane[6].pipe_user_i_n_11\,
      USER_RXRESETDONE => \pipe_lane[6].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[6].gt_wrapper_i_n_21\,
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(111 downto 96),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(6),
      \fsm_reg[0]\ => \pipe_lane[6].pipe_drp.pipe_drp_i_n_13\,
      \fsm_reg[2]\ => \pipe_lane[6].pipe_drp.pipe_drp_i_n_12\,
      gen3_reg => \pipe_lane[6].pipe_rate.pipe_rate_i_n_15\,
      gen3_reg_0 => \pipe_lane[6].pipe_rate.pipe_rate_i_n_12\,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(6),
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]_0\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_4\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_4\(15 downto 0),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_13,
      p_0_in36_in => p_0_in36_in,
      p_0_in38_in => p_0_in38_in,
      pci_exp_rxn(0) => pci_exp_rxn(6),
      pci_exp_rxp(0) => pci_exp_rxp(6),
      pci_exp_txn(0) => pci_exp_txn(6),
      pci_exp_txp(0) => pci_exp_txp(6),
      pclk_sel_reg => \^clk_oobclk\,
      pipe_dmonitorout(7 downto 0) => pipe_dmonitorout(55 downto 48),
      pipe_eyescandataerror(0) => pipe_eyescandataerror(6),
      pipe_rxbufstatus(2 downto 0) => pipe_rxbufstatus(20 downto 18),
      pipe_rxcommadet(0) => pipe_rxcommadet(6),
      pipe_rxdisperr(7 downto 0) => pipe_rxdisperr(55 downto 48),
      pipe_rxdlysresetdone(0) => \^pipe_rxdlysresetdone\(6),
      pipe_rxnotintable(7 downto 0) => pipe_rxnotintable(55 downto 48),
      pipe_rxoutclk_out(0) => pipe_rxoutclk_out(6),
      pipe_rxphaligndone(0) => \^pipe_rxphaligndone\(5),
      pipe_rxprbserr(0) => pipe_rxprbserr(6),
      pipe_rxstatus(2 downto 0) => \^pipe_rxstatus\(20 downto 18),
      pipe_txdlysresetdone(0) => \^pipe_txdlysresetdone\(6),
      pipe_txinhibit(0) => pipe_txinhibit(6),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(6),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(6),
      \pl_ltssm_state_q_reg[4]\ => \pl_ltssm_state_q_reg[4]\,
      qpllpd_reg => \^cplllock_reg1_reg[7]\,
      qpllpd_reg_0 => \^cplllock_reg1_reg[7]_0\,
      \resetovrd_disble.fsm_reg[1]\ => \pipe_lane[6].pipe_user_i_n_19\,
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      \resetovrd_disble.reset_reg[4]_0\(6) => \^pipe_txdlysresetdone\(7),
      \resetovrd_disble.reset_reg[4]_0\(5 downto 0) => \^pipe_txdlysresetdone\(5 downto 0),
      \resetovrd_disble.reset_reg[4]_1\(6) => \^pipe_rxdlysresetdone\(7),
      \resetovrd_disble.reset_reg[4]_1\(5 downto 0) => \^pipe_rxdlysresetdone\(5 downto 0),
      rst_cpllpd => rst_cpllpd,
      rst_gtreset => rst_gtreset,
      rxcdrlock_reg1_reg => \pipe_lane[6].gt_wrapper_i_n_6\,
      rxsync_donem_reg2_reg => \pipe_lane[6].pipe_sync_i_n_18\,
      \rxsync_fsm_disable.fsm_rx_reg[2]\ => \pipe_lane[6].pipe_sync_i_n_19\,
      rxvalid_reg1_reg => \pipe_lane[6].gt_wrapper_i_n_16\,
      sys_clk => sys_clk,
      \txsync_fsm.fsm_tx_reg[2]\ => \pipe_lane[6].pipe_sync_i_n_15\,
      \txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[6].pipe_sync_i_n_17\,
      \txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[6].pipe_sync_i_n_16\,
      \txsync_fsm.txdlyen_reg\ => \pipe_lane[6].pipe_sync_i_n_6\,
      userrdy_reg_rep => \pipe_reset.pipe_reset_i_n_17\
    );
\pipe_lane[6].pipe_drp.pipe_drp_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_61
     port map (
      DRPADDR(8) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[6].pipe_drp.pipe_drp_i_n_30\,
      DRP_DONE => p_96_out,
      DRP_START => DRP_START025_out,
      DRP_X16 => DRP_X16027_out,
      DRP_X16X20_MODE => DRP_X16X20_MODE029_out,
      Q(2 downto 0) => \index_reg[1]_4\(2 downto 0),
      RST_DCLK_RESET => rst_dclk_reset,
      \cplllock_reg1_reg[6]\ => \pipe_lane[6].pipe_drp.pipe_drp_i_n_12\,
      \cplllock_reg1_reg[6]_0\ => \pipe_lane[6].pipe_drp.pipe_drp_i_n_13\,
      ext_ch_gt_drpaddr(8 downto 0) => ext_ch_gt_drpaddr(62 downto 54),
      ext_ch_gt_drpdi(15 downto 0) => ext_ch_gt_drpdi(111 downto 96),
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(111 downto 96),
      ext_ch_gt_drpen(0) => ext_ch_gt_drpen(6),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(6),
      ext_ch_gt_drpwe(0) => ext_ch_gt_drpwe(6),
      gt_ch_drp_rdy(0) => gt_ch_drp_rdy(6),
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_gtreset => rst_gtreset
    );
\pipe_lane[6].pipe_eq.pipe_eq_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_62
     port map (
      RST_CPLLRESET => \p_0_in__0\,
      TXMAINCURSOR(6) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[6].pipe_eq.pipe_eq_i_n_4\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[6].pipe_eq.pipe_eq_i_n_17\,
      pclk_sel_reg => \^clk_oobclk\,
      rate_gen3(0) => rate_gen3(6)
    );
\pipe_lane[6].pipe_rate.pipe_rate_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_63
     port map (
      DRP_START025_out => DRP_START025_out,
      DRP_X16027_out => DRP_X16027_out,
      DRP_X16X20_MODE029_out => DRP_X16X20_MODE029_out,
      GT_TXPMARESET035_out => \^gt_txpmareset035_out\,
      Q(4 downto 0) => \sysclksel_reg[1]_4\(4 downto 0),
      QRST_QPLLPD_IN(0) => p_105_out,
      QRST_QPLLRESET_IN(0) => p_104_out,
      RATE_CPLLLOCK => \^qrst_cplllock\(6),
      RATE_DRP_DONE => p_96_out,
      RATE_PHYSTATUS => p_78_out,
      RATE_QPLLLOCK => \^qrst_qplllock\(1),
      RATE_RESETOVRD_DONE => \pipe_lane[6].pipe_user_i_n_20\,
      RATE_RXRATEDONE => \pipe_lane[6].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[6].gt_wrapper_i_n_20\,
      RATE_TXSYNC_DONE => p_99_out,
      RST_CPLLRESET => \p_0_in__0\,
      RST_DRP_START => rst_drp_start,
      RST_DRP_X16 => rst_drp_x16,
      RST_DRP_X16X20_MODE => rst_drp_x16x20_mode,
      RST_RATE_IDLE(6) => rate_idle(7),
      RST_RATE_IDLE(5 downto 0) => rate_idle(5 downto 0),
      RXRATE(2) => \pipe_lane[6].pipe_rate.pipe_rate_i_n_18\,
      RXRATE(1) => \pipe_lane[6].pipe_rate.pipe_rate_i_n_19\,
      RXRATE(0) => \pipe_lane[6].pipe_rate.pipe_rate_i_n_20\,
      RXSYSCLKSEL(1) => \pipe_lane[6].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[6].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[6].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[6].pipe_rate.pipe_rate_i_n_23\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START023_out,
      USER_PCLK_SEL => \^clk_pclk_sel\(6),
      USER_RATE_DONE => \pipe_lane[6].pipe_rate.pipe_rate_i_n_21\,
      USER_RATE_RXSYNC => \pipe_lane[6].pipe_rate.pipe_rate_i_n_22\,
      USER_RESETOVRD_START => \pipe_lane[6].pipe_rate.pipe_rate_i_n_5\,
      USER_RXRESETDONE => \pipe_lane[6].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[6].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[6]\ => \pipe_lane[6].pipe_rate.pipe_rate_i_n_12\,
      \cplllock_reg1_reg[6]_0\ => \pipe_lane[6].pipe_rate.pipe_rate_i_n_15\,
      gen3_reg1_reg => \pipe_lane[6].pipe_rate.pipe_rate_i_n_14\,
      gen3_reg_0(5) => rate_gen3(7),
      gen3_reg_0(4 downto 0) => rate_gen3(5 downto 1),
      gen3_reg_1(0) => \^eq_gen3\,
      out1(1) => \^out\(0),
      out1(0) => rst_txsync_start,
      p_0_in36_in => p_0_in36_in,
      p_0_in38_in => p_0_in38_in,
      p_0_in7_in => p_0_in7_in_15,
      p_1_in8_in => p_1_in8_in_14,
      pclk_sel_reg_0 => \^clk_oobclk\,
      pipe_rate_idle => pipe_rate_idle,
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      rate_gen3(0) => rate_gen3(6),
      \rate_idle_reg1_reg[6]\(0) => rate_idle(6),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\
    );
\pipe_lane[6].pipe_sync_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_64
     port map (
      Q(5 downto 0) => \txsync_fsm.txdlyen_reg_4\(5 downto 0),
      RST_CPLLRESET => \p_0_in__0\,
      RST_TXSYNC_DONE(0) => p_99_out,
      SYNC_GEN3 => rate_gen3(6),
      SYNC_RATE_IDLE => rate_idle(6),
      SYNC_RXCDRLOCK => p_111_out,
      SYNC_RXDLYEN => \pipe_lane[6].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[6].pipe_rate.pipe_rate_i_n_23\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START023_out,
      \cplllock_reg1_reg[6]\ => \pipe_lane[6].pipe_sync_i_n_15\,
      \cplllock_reg1_reg[6]_0\ => \pipe_lane[6].pipe_sync_i_n_16\,
      \cplllock_reg1_reg[6]_1\ => \pipe_lane[6].pipe_sync_i_n_17\,
      \cplllock_reg1_reg[6]_2\ => \pipe_lane[6].pipe_sync_i_n_18\,
      \cplllock_reg1_reg[6]_3\ => \pipe_lane[6].pipe_sync_i_n_19\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(6),
      p_0_in7_in => p_0_in7_in_15,
      p_1_in8_in => p_1_in8_in_14,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_sync_fsm_rx(6 downto 0) => pipe_sync_fsm_rx(48 downto 42),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\,
      \resetovrd_disble.reset_reg[4]_0\ => \pipe_lane[6].gt_wrapper_i_n_89\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[6].gt_wrapper_i_n_90\,
      \resetovrd_disble.reset_reg[4]_2\ => \^sync_rxphaligndone_m\,
      \resetovrd_disble.reset_reg[4]_3\ => \pipe_lane[3].gt_wrapper_i_n_86\,
      \rxsync_fsm_disable.fsm_rx_reg[2]_0\ => \pipe_lane[0].pipe_sync_i_n_14\,
      txelecidle_reg2_reg => \pipe_lane[4].pipe_user_i_n_0\,
      \txsync_fsm.txdlyen_reg_0\ => \pipe_lane[6].pipe_sync_i_n_6\,
      txsyncallin => txsyncallin
    );
\pipe_lane[6].pipe_user_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_65
     port map (
      CLK_PCLK_SEL(0) => \^clk_pclk_sel\(6),
      GT_RX_CONVERGE0 => \pipe_lane[6].pipe_user_i_n_3\,
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(6),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(6),
      Q(6) => \pipe_lane[6].pipe_user_i_n_10\,
      Q(5) => \pipe_lane[6].pipe_user_i_n_11\,
      Q(4) => \pipe_lane[6].pipe_user_i_n_12\,
      Q(3) => \pipe_lane[6].pipe_user_i_n_13\,
      Q(2) => \pipe_lane[6].pipe_user_i_n_14\,
      Q(1) => \pipe_lane[6].pipe_user_i_n_15\,
      Q(0) => \cplllock_reg1_reg[6]\,
      RST_CPLLRESET => \p_0_in__0\,
      RST_PHYSTATUS(0) => p_78_out,
      RST_RESETDONE(0) => p_113_out,
      RST_RXCDRLOCK(0) => p_111_out,
      RST_RXUSRCLK_RESET => rst_rxusrclk_reset,
      USER_OOBCLK => \pipe_lane[6].pipe_user_i_n_9\,
      USER_RATE_DONE => \pipe_lane[6].pipe_rate.pipe_rate_i_n_21\,
      USER_RATE_GEN3 => rate_gen3(6),
      USER_RATE_IDLE => rate_idle(6),
      USER_RATE_RXSYNC => \pipe_lane[6].pipe_rate.pipe_rate_i_n_22\,
      USER_RESETOVRD_START => \pipe_lane[6].pipe_rate.pipe_rate_i_n_5\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[6].pipe_eq.pipe_eq_i_n_17\,
      USER_RXRESETDONE => \pipe_lane[6].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[6].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[2]\ => \pipe_lane[6].pipe_user_i_n_4\,
      \cplllock_reg1_reg[3]\ => \pipe_lane[6].pipe_user_i_n_5\,
      \cplllock_reg1_reg[6]\ => \pipe_lane[6].pipe_user_i_n_19\,
      \cplllock_reg1_reg[7]\ => \pipe_lane[6].pipe_user_i_n_6\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(6),
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(6),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_5,
      gt_rxvalid_q_reg_0 => gt_rxvalid_q_reg_13,
      out1(0) => \^out\(0),
      p_0_in7_in => p_0_in7_in_15,
      p_159_out => p_159_out,
      p_1_in8_in => p_1_in8_in_14,
      p_216_out => p_216_out,
      p_2_in => p_2_in_16,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_rxstatus(0) => \^pipe_rxstatus\(20),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(6),
      \resetovrd_disble.reset_reg[4]_0\ => \pipe_lane[6].gt_wrapper_i_n_16\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[6].gt_wrapper_i_n_6\,
      resetovrd_done_reg1_reg => \pipe_lane[6].pipe_user_i_n_20\,
      txcompliance_reg2_reg_0 => \pipe_lane[7].pipe_user_i_n_3\,
      txelecidle_reg2_reg_0 => \pipe_lane[1].pipe_user_i_n_0\,
      txelecidle_reg2_reg_1 => \pipe_lane[4].pipe_user_i_n_3\,
      txelecidle_reg2_reg_2 => \pipe_lane[3].pipe_user_i_n_0\,
      txsyncallin => txsyncallin,
      user_rx_converge(4) => p_53_out,
      user_rx_converge(3) => p_269_out,
      user_rx_converge(2) => p_322_out,
      user_rx_converge(1) => p_375_out,
      user_rx_converge(0) => p_431_out
    );
\pipe_lane[7].gt_wrapper_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_66
     port map (
      DRPADDR(8) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_30\,
      GT_RXPMARESET014_out => GT_RXPMARESET014_out,
      GT_TXPMARESET017_out => \^gt_txpmareset017_out\,
      PIPE_POWERDOWN(1 downto 0) => PIPE_POWERDOWN(15 downto 14),
      PIPE_RXCHANISALIGNED(0) => PIPE_RXCHANISALIGNED(7),
      PIPE_RXPOLARITY(0) => PIPE_RXPOLARITY(7),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(7),
      PIPE_TXDATA(15 downto 0) => PIPE_TXDATA(127 downto 112),
      PIPE_TXDATAK(1 downto 0) => PIPE_TXDATAK(15 downto 14),
      PIPE_TXDEEMPH(0) => PIPE_TXDEEMPH(3),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(7),
      Q(1 downto 0) => Q(1 downto 0),
      RATE_CPLLLOCK => \^qrst_cplllock\(7),
      RATE_PHYSTATUS => p_25_out,
      RATE_RXRATEDONE => \pipe_lane[7].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[7].gt_wrapper_i_n_20\,
      RST_CPLLRESET => \p_0_in__0\,
      RXCHBONDO(4 downto 0) => \gt_rxchbondo[1]_0\(4 downto 0),
      RXRATE(2) => \pipe_lane[7].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[7].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[7].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[7].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[7].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RXSYNC_DONE => \pipe_lane[7].pipe_sync_i_n_14\,
      TXMAINCURSOR(6) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_4\,
      USER_EYESCANRESET => \pipe_lane[7].pipe_user_i_n_9\,
      USER_OOBCLK => \pipe_lane[7].pipe_user_i_n_6\,
      USER_RXBUFRESET => \pipe_lane[7].pipe_user_i_n_7\,
      USER_RXCDRFREQRESET => \pipe_lane[7].pipe_user_i_n_11\,
      USER_RXCDRRESET => \pipe_lane[7].pipe_user_i_n_12\,
      USER_RXDFELPMRESET => \pipe_lane[7].pipe_user_i_n_10\,
      USER_RXPCSRESET => \pipe_lane[7].pipe_user_i_n_8\,
      USER_RXRESETDONE => \pipe_lane[7].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[7].gt_wrapper_i_n_21\,
      converge_gen3_reg => \pipe_lane[6].pipe_user_i_n_6\,
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(127 downto 112),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(7),
      \fsm_reg[0]\ => \pipe_lane[7].pipe_drp.pipe_drp_i_n_13\,
      \fsm_reg[2]\ => \pipe_lane[7].pipe_drp.pipe_drp_i_n_12\,
      gen3_reg => \pipe_lane[7].pipe_rate.pipe_rate_i_n_14\,
      gen3_reg_0 => \pipe_lane[7].pipe_rate.pipe_rate_i_n_12\,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(7),
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]_5\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]_5\(15 downto 0),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_14,
      p_0_in18_in => p_0_in18_in,
      p_0_in20_in => p_0_in20_in,
      pci_exp_rxn(0) => pci_exp_rxn(7),
      pci_exp_rxp(0) => pci_exp_rxp(7),
      pci_exp_txn(0) => pci_exp_txn(7),
      pci_exp_txp(0) => pci_exp_txp(7),
      pclk_sel_reg => \^clk_oobclk\,
      pipe_dmonitorout(7 downto 0) => pipe_dmonitorout(63 downto 56),
      pipe_eyescandataerror(0) => pipe_eyescandataerror(7),
      pipe_rxbufstatus(2 downto 0) => pipe_rxbufstatus(23 downto 21),
      pipe_rxcommadet(0) => pipe_rxcommadet(7),
      pipe_rxdisperr(7 downto 0) => pipe_rxdisperr(63 downto 56),
      pipe_rxdlysresetdone(0) => \^pipe_rxdlysresetdone\(7),
      pipe_rxnotintable(7 downto 0) => pipe_rxnotintable(63 downto 56),
      pipe_rxoutclk_out(0) => pipe_rxoutclk_out(7),
      pipe_rxphaligndone(0) => \^pipe_rxphaligndone\(6),
      pipe_rxprbserr(0) => pipe_rxprbserr(7),
      pipe_rxstatus(2 downto 0) => \^pipe_rxstatus\(23 downto 21),
      \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0),
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_txdlysresetdone(0) => \^pipe_txdlysresetdone\(7),
      pipe_txinhibit(0) => pipe_txinhibit(7),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(7),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(7),
      \pl_ltssm_state_q_reg[4]\ => \pl_ltssm_state_q_reg[4]\,
      qpllpd_reg => \^cplllock_reg1_reg[7]\,
      qpllpd_reg_0 => \^cplllock_reg1_reg[7]_0\,
      \resetovrd_disble.fsm_reg[1]\ => \pipe_lane[7].pipe_user_i_n_17\,
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_cpllpd => rst_cpllpd,
      rst_gtreset => rst_gtreset,
      rst_userrdy => rst_userrdy,
      rxcdrlock_reg1_reg => \pipe_lane[7].gt_wrapper_i_n_6\,
      rxsync_donem_reg2_reg => \pipe_lane[7].pipe_sync_i_n_18\,
      \rxsync_fsm_disable.fsm_rx_reg[2]\ => \pipe_lane[7].pipe_sync_i_n_19\,
      rxvalid_reg1_reg => \pipe_lane[7].gt_wrapper_i_n_16\,
      sys_clk => sys_clk,
      \txsync_fsm.fsm_tx_reg[2]\ => \pipe_lane[7].pipe_sync_i_n_15\,
      \txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[7].pipe_sync_i_n_17\,
      \txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[7].pipe_sync_i_n_16\,
      \txsync_fsm.txdlyen_reg\ => \pipe_lane[7].pipe_sync_i_n_6\
    );
\pipe_lane[7].pipe_drp.pipe_drp_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_67
     port map (
      DRPADDR(8) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_3\,
      DRPADDR(7) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(6) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_5\,
      DRPADDR(5) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_6\,
      DRPADDR(4) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_7\,
      DRPADDR(3) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_8\,
      DRPADDR(2) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_9\,
      DRPADDR(1) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_10\,
      DRPADDR(0) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_11\,
      DRPDI(15) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_15\,
      DRPDI(14) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_16\,
      DRPDI(13) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_17\,
      DRPDI(12) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_18\,
      DRPDI(11) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_19\,
      DRPDI(10) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_20\,
      DRPDI(9) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_21\,
      DRPDI(8) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_22\,
      DRPDI(7) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_23\,
      DRPDI(6) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_24\,
      DRPDI(5) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_25\,
      DRPDI(4) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_26\,
      DRPDI(3) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_27\,
      DRPDI(2) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_28\,
      DRPDI(1) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_29\,
      DRPDI(0) => \pipe_lane[7].pipe_drp.pipe_drp_i_n_30\,
      DRP_DONE => p_43_out,
      DRP_START => DRP_START08_out,
      DRP_X16 => DRP_X16010_out,
      DRP_X16X20_MODE => DRP_X16X20_MODE0136_out,
      Q(2 downto 0) => \index_reg[1]_5\(2 downto 0),
      RST_DCLK_RESET => rst_dclk_reset,
      \cplllock_reg1_reg[7]\ => \pipe_lane[7].pipe_drp.pipe_drp_i_n_12\,
      \cplllock_reg1_reg[7]_0\ => \pipe_lane[7].pipe_drp.pipe_drp_i_n_13\,
      ext_ch_gt_drpaddr(8 downto 0) => ext_ch_gt_drpaddr(71 downto 63),
      ext_ch_gt_drpdi(15 downto 0) => ext_ch_gt_drpdi(127 downto 112),
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(127 downto 112),
      ext_ch_gt_drpen(0) => ext_ch_gt_drpen(7),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(7),
      ext_ch_gt_drpwe(0) => ext_ch_gt_drpwe(7),
      gt_ch_drp_rdy(0) => gt_ch_drp_rdy(7),
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      \resetovrd_disble.reset_reg[4]\ => \^clk_dclk\,
      rst_gtreset => rst_gtreset
    );
\pipe_lane[7].pipe_eq.pipe_eq_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_68
     port map (
      RST_CPLLRESET => \p_0_in__0\,
      TXMAINCURSOR(6) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_5\,
      TXMAINCURSOR(5) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_6\,
      TXMAINCURSOR(4) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_7\,
      TXMAINCURSOR(3) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_8\,
      TXMAINCURSOR(2) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_9\,
      TXMAINCURSOR(1) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_10\,
      TXMAINCURSOR(0) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_11\,
      TXPOSTCURSOR(4) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_12\,
      TXPOSTCURSOR(3) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_13\,
      TXPOSTCURSOR(2) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_14\,
      TXPOSTCURSOR(1) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_15\,
      TXPOSTCURSOR(0) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_16\,
      TXPRECURSOR(4) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_0\,
      TXPRECURSOR(3) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_1\,
      TXPRECURSOR(2) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_2\,
      TXPRECURSOR(1) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_3\,
      TXPRECURSOR(0) => \pipe_lane[7].pipe_eq.pipe_eq_i_n_4\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[7].pipe_eq.pipe_eq_i_n_17\,
      gen3_reg(0) => rate_gen3(7),
      pclk_sel_reg => \^clk_oobclk\
    );
\pipe_lane[7].pipe_rate.pipe_rate_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_69
     port map (
      DRP_START08_out => DRP_START08_out,
      DRP_X16010_out => DRP_X16010_out,
      DRP_X16X20_MODE0136_out => DRP_X16X20_MODE0136_out,
      GT_TXPMARESET017_out => \^gt_txpmareset017_out\,
      Q(4 downto 0) => \sysclksel_reg[1]_5\(4 downto 0),
      QRST_QPLLPD_IN(0) => p_52_out,
      QRST_QPLLRESET_IN(0) => p_51_out,
      RATE_CPLLLOCK => \^qrst_cplllock\(7),
      RATE_DRP_DONE => p_43_out,
      RATE_PHYSTATUS => p_25_out,
      RATE_RESETOVRD_DONE => \pipe_lane[7].pipe_user_i_n_18\,
      RATE_RXRATEDONE => \pipe_lane[7].gt_wrapper_i_n_14\,
      RATE_TXRATEDONE => \pipe_lane[7].gt_wrapper_i_n_20\,
      RATE_TXSYNC_DONE => p_46_out,
      RST_CPLLRESET => \p_0_in__0\,
      RST_DRP_START => rst_drp_start,
      RST_DRP_X16 => rst_drp_x16,
      RST_DRP_X16X20_MODE => rst_drp_x16x20_mode,
      RXRATE(2) => \pipe_lane[7].pipe_rate.pipe_rate_i_n_15\,
      RXRATE(1) => \pipe_lane[7].pipe_rate.pipe_rate_i_n_16\,
      RXRATE(0) => \pipe_lane[7].pipe_rate.pipe_rate_i_n_17\,
      RXSYSCLKSEL(1) => \pipe_lane[7].pipe_rate.pipe_rate_i_n_6\,
      RXSYSCLKSEL(0) => \pipe_lane[7].pipe_rate.pipe_rate_i_n_7\,
      SYNC_RATE_IDLE => rate_idle(7),
      SYNC_RXSYNC_DONE => \pipe_lane[7].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[7].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0,
      USER_PCLK_SEL => \^clk_pclk_sel\(7),
      USER_RATE_DONE => \pipe_lane[7].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_RXSYNC => \pipe_lane[7].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[7].pipe_rate.pipe_rate_i_n_5\,
      USER_RXRESETDONE => \pipe_lane[7].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[7].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[7]\ => \pipe_lane[7].pipe_rate.pipe_rate_i_n_12\,
      \cplllock_reg1_reg[7]_0\ => \pipe_lane[7].pipe_rate.pipe_rate_i_n_14\,
      out1(1) => \^out\(0),
      out1(0) => rst_txsync_start,
      p_0_in18_in => p_0_in18_in,
      p_0_in20_in => p_0_in20_in,
      p_0_in7_in => p_0_in7_in_17,
      p_1_in8_in => p_1_in8_in_18,
      pclk_sel_reg_0 => \^clk_oobclk\,
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      qpllpd_reg_0 => \^qrst_qplllock\(1),
      rate_gen3_reg1_reg(0) => rate_gen3(7),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\
    );
\pipe_lane[7].pipe_sync_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_70
     port map (
      Q(5 downto 0) => \txsync_fsm.txdlyen_reg_5\(5 downto 0),
      RST_CPLLRESET => \p_0_in__0\,
      RST_TXSYNC_DONE(0) => p_46_out,
      SYNC_GEN3 => rate_gen3(7),
      SYNC_RATE_IDLE => rate_idle(7),
      SYNC_RXCDRLOCK => p_58_out,
      SYNC_RXDLYEN => \pipe_lane[7].pipe_sync_i_n_14\,
      SYNC_RXSYNC_START => \pipe_lane[7].pipe_rate.pipe_rate_i_n_20\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0,
      \cplllock_reg1_reg[7]\ => \pipe_lane[7].pipe_sync_i_n_15\,
      \cplllock_reg1_reg[7]_0\ => \pipe_lane[7].pipe_sync_i_n_16\,
      \cplllock_reg1_reg[7]_1\ => \pipe_lane[7].pipe_sync_i_n_17\,
      \cplllock_reg1_reg[7]_2\ => \pipe_lane[7].pipe_sync_i_n_18\,
      \cplllock_reg1_reg[7]_3\ => \pipe_lane[7].pipe_sync_i_n_19\,
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(7),
      p_0_in7_in => p_0_in7_in_17,
      p_1_in8_in => p_1_in8_in_18,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_sync_fsm_rx(6 downto 0) => pipe_sync_fsm_rx(55 downto 49),
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\,
      \resetovrd_disble.reset_reg[4]_0\ => \pipe_lane[6].gt_wrapper_i_n_89\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[6].gt_wrapper_i_n_90\,
      \resetovrd_disble.reset_reg[4]_2\ => \^sync_rxphaligndone_m\,
      \resetovrd_disble.reset_reg[4]_3\ => \pipe_lane[3].gt_wrapper_i_n_86\,
      \rxsync_fsm_disable.fsm_rx_reg[2]_0\ => \pipe_lane[0].pipe_sync_i_n_14\,
      txelecidle_reg2_reg => \pipe_lane[4].pipe_user_i_n_0\,
      \txsync_fsm.txdlyen_reg_0\ => \pipe_lane[7].pipe_sync_i_n_6\,
      txsyncallin => txsyncallin
    );
\pipe_lane[7].pipe_user_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_71
     port map (
      CLK_PCLK_SEL(0) => \^clk_pclk_sel\(7),
      PIPE_TXCOMPLIANCE(0) => PIPE_TXCOMPLIANCE(7),
      PIPE_TXELECIDLE(0) => PIPE_TXELECIDLE(7),
      Q(6) => \pipe_lane[7].pipe_user_i_n_7\,
      Q(5) => \pipe_lane[7].pipe_user_i_n_8\,
      Q(4) => \pipe_lane[7].pipe_user_i_n_9\,
      Q(3) => \pipe_lane[7].pipe_user_i_n_10\,
      Q(2) => \pipe_lane[7].pipe_user_i_n_11\,
      Q(1) => \pipe_lane[7].pipe_user_i_n_12\,
      Q(0) => \cplllock_reg1_reg[7]_1\,
      RST_CPLLRESET => \p_0_in__0\,
      RST_PHYSTATUS(0) => p_25_out,
      RST_RESETDONE(0) => p_60_out,
      RST_RXCDRLOCK(0) => p_58_out,
      RST_RXUSRCLK_RESET => rst_rxusrclk_reset,
      USER_OOBCLK => \pipe_lane[7].pipe_user_i_n_6\,
      USER_RATE_DONE => \pipe_lane[7].pipe_rate.pipe_rate_i_n_18\,
      USER_RATE_IDLE => rate_idle(7),
      USER_RATE_RXSYNC => \pipe_lane[7].pipe_rate.pipe_rate_i_n_19\,
      USER_RESETOVRD_START => \pipe_lane[7].pipe_rate.pipe_rate_i_n_5\,
      USER_RXEQ_ADAPT_DONE => \pipe_lane[7].pipe_eq.pipe_eq_i_n_17\,
      USER_RXRESETDONE => \pipe_lane[7].gt_wrapper_i_n_15\,
      USER_TXRESETDONE => \pipe_lane[7].gt_wrapper_i_n_21\,
      \cplllock_reg1_reg[7]\ => \pipe_lane[7].pipe_user_i_n_17\,
      gen3_reg(0) => rate_gen3(7),
      gt_rx_elec_idle_wire_filter(0) => \^gt_rx_elec_idle_wire_filter\(7),
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(7),
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_6,
      gt_rxvalid_q_reg_0 => gt_rxvalid_q_reg_14,
      out1(0) => \^out\(0),
      p_0_in7_in => p_0_in7_in_17,
      p_0_in7_in_0 => p_0_in7_in_15,
      p_1_in8_in => p_1_in8_in_18,
      p_1_in8_in_1 => p_1_in8_in_14,
      p_2_in => p_2_in_16,
      p_2_in_2 => p_2_in_8,
      p_2_in_3 => p_2_in_3,
      p_2_in_4 => p_2_in_0,
      p_2_in_5 => p_2_in,
      pclk_sel_reg => \^clk_oobclk\,
      phy_rdy_n_int_reg => \pipe_lane[7].pipe_user_i_n_5\,
      pipe_rxstatus(0) => \^pipe_rxstatus\(23),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(7),
      pipe_txphinitdone(1 downto 0) => \^pipe_txphinitdone\(7 downto 6),
      \resetovrd_disble.reset_reg[4]_0\ => \pipe_lane[7].gt_wrapper_i_n_16\,
      \resetovrd_disble.reset_reg[4]_1\ => \pipe_lane[7].gt_wrapper_i_n_6\,
      resetovrd_done_reg1_reg => \pipe_lane[7].pipe_user_i_n_18\,
      txphaligndone_reg1_reg => \pipe_lane[7].pipe_user_i_n_3\,
      txphinitdone_reg1_reg => \pipe_lane[7].pipe_user_i_n_0\,
      user_rx_converge(0) => p_53_out
    );
\pipe_reset.pipe_reset_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_reset
     port map (
      D(7) => p_60_out,
      D(6) => p_113_out,
      D(5) => p_166_out,
      D(4) => p_223_out,
      D(3) => p_276_out,
      D(2) => p_329_out,
      D(1) => p_382_out,
      D(0) => p_438_out,
      RST_CPLLRESET => \p_0_in__0\,
      RST_DCLK_RESET => rst_dclk_reset,
      RST_DRP_START => rst_drp_start,
      RST_DRP_X16 => rst_drp_x16,
      RST_DRP_X16X20_MODE => rst_drp_x16x20_mode,
      RST_RXUSRCLK_RESET => rst_rxusrclk_reset,
      \cfg_wait_cnt_reg[5]_0\ => \pipe_reset.pipe_reset_i_n_4\,
      done_reg(7) => p_43_out,
      done_reg(6) => p_96_out,
      done_reg(5) => p_149_out,
      done_reg(4) => p_206_out,
      done_reg(3) => p_259_out,
      done_reg(2) => p_312_out,
      done_reg(1) => p_365_out,
      done_reg(0) => p_422_out,
      \out\(2) => \^out\(1),
      \out\(1) => rst_txsync_start,
      \out\(0) => \^out\(0),
      pclk_sel_reg => \^clk_oobclk\,
      pipe_qrst_idle => \^pipe_qrst_idle\,
      pipe_rst_fsm(3 downto 0) => pipe_rst_fsm(3 downto 0),
      rate_idle(7 downto 0) => rate_idle(7 downto 0),
      reset_n_reg2_reg => reset_n_reg2,
      \resetovrd_disble.reset_reg[4]\ => \^clk_mmcm_lock\,
      \resetovrd_disble.reset_reg[4]_0\(7 downto 0) => \^qrst_cplllock\(7 downto 0),
      \resetovrd_disble.reset_reg[4]_1\(7) => p_25_out,
      \resetovrd_disble.reset_reg[4]_1\(6) => p_78_out,
      \resetovrd_disble.reset_reg[4]_1\(5) => p_131_out,
      \resetovrd_disble.reset_reg[4]_1\(4) => p_184_out,
      \resetovrd_disble.reset_reg[4]_1\(3) => p_241_out,
      \resetovrd_disble.reset_reg[4]_1\(2) => p_294_out,
      \resetovrd_disble.reset_reg[4]_1\(1) => p_347_out,
      \resetovrd_disble.reset_reg[4]_1\(0) => p_400_out,
      \resetovrd_disble.reset_reg[4]_2\ => \^clk_dclk\,
      rst_cpllpd => rst_cpllpd,
      rst_gtreset => rst_gtreset,
      rst_userrdy => rst_userrdy,
      \rxcdrlock_cnt_reg[3]\(7) => p_58_out,
      \rxcdrlock_cnt_reg[3]\(6) => p_111_out,
      \rxcdrlock_cnt_reg[3]\(5) => p_164_out,
      \rxcdrlock_cnt_reg[3]\(4) => p_221_out,
      \rxcdrlock_cnt_reg[3]\(3) => p_274_out,
      \rxcdrlock_cnt_reg[3]\(2) => p_327_out,
      \rxcdrlock_cnt_reg[3]\(1) => p_380_out,
      \rxcdrlock_cnt_reg[3]\(0) => p_436_out,
      \txsync_fsm.txsync_done_reg\(7) => p_46_out,
      \txsync_fsm.txsync_done_reg\(6) => p_99_out,
      \txsync_fsm.txsync_done_reg\(5) => p_152_out,
      \txsync_fsm.txsync_done_reg\(4) => p_209_out,
      \txsync_fsm.txsync_done_reg\(3) => p_262_out,
      \txsync_fsm.txsync_done_reg\(2) => p_315_out,
      \txsync_fsm.txsync_done_reg\(1) => p_368_out,
      \txsync_fsm.txsync_done_reg\(0) => p_425_out,
      userrdy_reg_rep_0 => \pipe_reset.pipe_reset_i_n_17\,
      \userrdy_reg_rep__0_0\ => \pipe_reset.pipe_reset_i_n_18\,
      \userrdy_reg_rep__1_0\ => \pipe_reset.pipe_reset_i_n_19\,
      \userrdy_reg_rep__2_0\ => \pipe_reset.pipe_reset_i_n_20\,
      \userrdy_reg_rep__3_0\ => \pipe_reset.pipe_reset_i_n_21\,
      \userrdy_reg_rep__4_0\ => \pipe_reset.pipe_reset_i_n_22\,
      \userrdy_reg_rep__5_0\ => \pipe_reset.pipe_reset_i_n_23\
    );
\qpll_reset.qpll_reset_i\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_qpll_reset
     port map (
      D(7) => p_52_out,
      D(6) => p_105_out,
      D(5) => p_158_out,
      D(4) => p_215_out,
      D(3) => p_268_out,
      D(2) => p_321_out,
      D(1) => p_374_out,
      D(0) => p_430_out,
      done_reg(1) => p_196_out,
      done_reg(0) => p_412_out,
      pclk_sel_reg => \^clk_oobclk\,
      pipe_qrst_fsm(3 downto 0) => pipe_qrst_fsm(3 downto 0),
      pipe_qrst_idle => \^pipe_qrst_idle\,
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      qpllpd => qpllpd,
      qpllpd_reg_0 => \^qrst_qplllock\(1),
      qpllpd_reg_1 => \^qrst_qplllock\(0),
      qpllreset_reg_0(7) => p_51_out,
      qpllreset_reg_0(6) => p_104_out,
      qpllreset_reg_0(5) => p_157_out,
      qpllreset_reg_0(4) => p_214_out,
      qpllreset_reg_0(3) => p_267_out,
      qpllreset_reg_0(2) => p_320_out,
      qpllreset_reg_0(1) => p_373_out,
      qpllreset_reg_0(0) => p_429_out,
      qrst_ovrd => qrst_ovrd,
      qrst_qpllreset => qrst_qpllreset,
      reset_n_reg2_reg => \pipe_reset.pipe_reset_i_n_4\,
      \resetovrd_disble.reset_reg[4]\(7 downto 0) => \^qrst_cplllock\(7 downto 0),
      \resetovrd_disble.reset_reg[4]_0\ => \^clk_mmcm_lock\,
      start_reg1_reg => \qpll_reset.qpll_reset_i_n_4\
    );
reset_n_reg1_reg: unisim.vcomponents.FDCE
     port map (
      C => \^clk_oobclk\,
      CE => '1',
      CLR => \^reset_n_reg2_reg_0\,
      D => '1',
      Q => reset_n_reg1
    );
reset_n_reg2_reg: unisim.vcomponents.FDCE
     port map (
      C => \^clk_oobclk\,
      CE => '1',
      CLR => \^reset_n_reg2_reg_0\,
      D => reset_n_reg1,
      Q => reset_n_reg2
    );
user_lnk_up_int_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sys_rst_n,
      O => \^reset_n_reg2_reg_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_gt_top is
  port (
    pipe_rx0_valid : out STD_LOGIC;
    Q : out STD_LOGIC;
    CLK_PCLK : out STD_LOGIC;
    pipe_rx1_valid : out STD_LOGIC;
    pipe_rx2_valid : out STD_LOGIC;
    pipe_rx3_valid : out STD_LOGIC;
    pipe_rx4_valid : out STD_LOGIC;
    pipe_rx5_valid : out STD_LOGIC;
    pipe_rx6_valid : out STD_LOGIC;
    pipe_rx7_valid : out STD_LOGIC;
    gt_rx_phy_status_q : out STD_LOGIC;
    gt_rxelecidle_q : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg_1\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_1\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg_2\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_2\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg_3\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_3\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg_4\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_4\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_phy_status_q_reg_5\ : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_5\ : out STD_LOGIC;
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \txsync_fsm.txsync_done_reg\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \index_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \index_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_1\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \index_reg[1]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_1\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_2\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \index_reg[1]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_2\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_3\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \index_reg[1]_3\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_3\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_4\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \index_reg[1]_4\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_4\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_5\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \index_reg[1]_5\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \txsync_fsm.txdlyen_reg_5\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \sysclksel_reg[1]_6\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \index_reg[1]_6\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    sys_rst_n : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_2\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_3\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_4\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_5\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_6\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK_MMCM_LOCK : out STD_LOGIC;
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_3\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_4\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_5\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_6\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 23 downto 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txoutclk_out : out STD_LOGIC;
    CLK_DCLK : out STD_LOGIC;
    CLK_USERCLK1 : out STD_LOGIC;
    pclk_sel_reg1_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
    rate_gen3 : out STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    PIPE_CPLL_LOCK : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_qrst_idle : out STD_LOGIC;
    PIPE_QPLL_LOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 55 downto 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 127 downto 0 );
    INT_QPLLOUTCLK_OUT : out STD_LOGIC_VECTOR ( 1 downto 0 );
    INT_QPLLOUTREFCLK_OUT : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_RXCHANISALIGNED : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 23 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 63 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 63 downto 0 );
    pipe_rate_idle : out STD_LOGIC;
    reset_n_reg2_reg : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 71 downto 0 );
    pl_ltssm_state : in STD_LOGIC_VECTOR ( 5 downto 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_mmcm_rst_n : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_rate_q_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    sys_clk : in STD_LOGIC;
    PIPE_TXCOMPLIANCE : in STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_TXELECIDLE : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_RXPOLARITY : in STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_TXDEEMPH : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\ : in STD_LOGIC;
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_POWERDOWN : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMARGIN : in STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXDATA : in STD_LOGIC_VECTOR ( 127 downto 0 );
    PIPE_TXDATAK : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\ : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXDETECTRX : in STD_LOGIC;
    PIPE_TXMARGIN : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx_rcvr_det : in STD_LOGIC;
    \pipe_stages_1.pipe_tx_margin_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    sys_rst_n_0 : in STD_LOGIC;
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 127 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_gt_top : entity is "PCIeGen1x8If64_gt_top";
end PCIeGen1x8If64_PCIeGen1x8If64_gt_top;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_gt_top is
  signal \^clk_mmcm_lock\ : STD_LOGIC;
  signal \^clk_pclk\ : STD_LOGIC;
  signal GT_RXCHARISK : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal GT_RXDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal GT_RXPMARESET0 : STD_LOGIC;
  signal GT_RXPMARESET0117_out : STD_LOGIC;
  signal GT_RXPMARESET014_out : STD_LOGIC;
  signal GT_RXPMARESET032_out : STD_LOGIC;
  signal GT_RXPMARESET043_out : STD_LOGIC;
  signal GT_RXPMARESET061_out : STD_LOGIC;
  signal GT_RXPMARESET071_out : STD_LOGIC;
  signal GT_RXPMARESET089_out : STD_LOGIC;
  signal GT_TXPMARESET0 : STD_LOGIC;
  signal GT_TXPMARESET0120_out : STD_LOGIC;
  signal GT_TXPMARESET017_out : STD_LOGIC;
  signal GT_TXPMARESET035_out : STD_LOGIC;
  signal GT_TXPMARESET046_out : STD_LOGIC;
  signal GT_TXPMARESET064_out : STD_LOGIC;
  signal GT_TXPMARESET074_out : STD_LOGIC;
  signal GT_TXPMARESET092_out : STD_LOGIC;
  signal \^q\ : STD_LOGIC;
  signal all_phystatus_rst : STD_LOGIC;
  signal gt_rx_elec_idle_wire_filter : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal gt_rx_phy_status_wire_filter : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_1_in116_in : STD_LOGIC;
  signal p_1_in13_in : STD_LOGIC;
  signal p_1_in31_in : STD_LOGIC;
  signal p_1_in42_in : STD_LOGIC;
  signal p_1_in60_in : STD_LOGIC;
  signal p_1_in70_in : STD_LOGIC;
  signal p_1_in88_in : STD_LOGIC;
  signal phy_rdy_n_int_i_2_n_0 : STD_LOGIC;
  signal \^pipe_rx0_valid\ : STD_LOGIC;
  signal \^pipe_rx1_valid\ : STD_LOGIC;
  signal \^pipe_rx2_valid\ : STD_LOGIC;
  signal \^pipe_rx3_valid\ : STD_LOGIC;
  signal \^pipe_rx4_valid\ : STD_LOGIC;
  signal \^pipe_rx5_valid\ : STD_LOGIC;
  signal \^pipe_rx6_valid\ : STD_LOGIC;
  signal \^pipe_rx7_valid\ : STD_LOGIC;
  signal pipe_wrapper_i_n_295 : STD_LOGIC;
  signal pipe_wrapper_i_n_296 : STD_LOGIC;
  signal pipe_wrapper_i_n_297 : STD_LOGIC;
  signal pipe_wrapper_i_n_298 : STD_LOGIC;
  signal pipe_wrapper_i_n_299 : STD_LOGIC;
  signal pipe_wrapper_i_n_300 : STD_LOGIC;
  signal pipe_wrapper_i_n_301 : STD_LOGIC;
  signal pipe_wrapper_i_n_302 : STD_LOGIC;
  signal pipe_wrapper_i_n_303 : STD_LOGIC;
  signal pipe_wrapper_i_n_304 : STD_LOGIC;
  signal pipe_wrapper_i_n_305 : STD_LOGIC;
  signal pipe_wrapper_i_n_306 : STD_LOGIC;
  signal pipe_wrapper_i_n_307 : STD_LOGIC;
  signal pipe_wrapper_i_n_308 : STD_LOGIC;
  signal pipe_wrapper_i_n_309 : STD_LOGIC;
  signal pipe_wrapper_i_n_310 : STD_LOGIC;
  signal pipe_wrapper_i_n_375 : STD_LOGIC;
  signal pipe_wrapper_i_n_376 : STD_LOGIC;
  signal pipe_wrapper_i_n_533 : STD_LOGIC;
  signal pipe_wrapper_i_n_534 : STD_LOGIC;
  signal pipe_wrapper_i_n_535 : STD_LOGIC;
  signal pipe_wrapper_i_n_536 : STD_LOGIC;
  signal pipe_wrapper_i_n_537 : STD_LOGIC;
  signal pipe_wrapper_i_n_538 : STD_LOGIC;
  signal pipe_wrapper_i_n_539 : STD_LOGIC;
  signal pipe_wrapper_i_n_540 : STD_LOGIC;
  signal pipe_wrapper_i_n_541 : STD_LOGIC;
  signal pipe_wrapper_i_n_542 : STD_LOGIC;
  signal pipe_wrapper_i_n_543 : STD_LOGIC;
  signal pipe_wrapper_i_n_544 : STD_LOGIC;
  signal pipe_wrapper_i_n_545 : STD_LOGIC;
  signal pipe_wrapper_i_n_546 : STD_LOGIC;
  signal pipe_wrapper_i_n_547 : STD_LOGIC;
  signal pipe_wrapper_i_n_548 : STD_LOGIC;
  signal pipe_wrapper_i_n_549 : STD_LOGIC;
  signal pipe_wrapper_i_n_550 : STD_LOGIC;
  signal pipe_wrapper_i_n_552 : STD_LOGIC;
  signal pipe_wrapper_i_n_553 : STD_LOGIC;
  signal pipe_wrapper_i_n_554 : STD_LOGIC;
  signal pipe_wrapper_i_n_555 : STD_LOGIC;
  signal pipe_wrapper_i_n_556 : STD_LOGIC;
  signal pipe_wrapper_i_n_557 : STD_LOGIC;
  signal pipe_wrapper_i_n_558 : STD_LOGIC;
  signal pipe_wrapper_i_n_559 : STD_LOGIC;
  signal pipe_wrapper_i_n_560 : STD_LOGIC;
  signal pipe_wrapper_i_n_561 : STD_LOGIC;
  signal pipe_wrapper_i_n_562 : STD_LOGIC;
  signal pipe_wrapper_i_n_563 : STD_LOGIC;
  signal pipe_wrapper_i_n_564 : STD_LOGIC;
  signal pipe_wrapper_i_n_565 : STD_LOGIC;
  signal pipe_wrapper_i_n_566 : STD_LOGIC;
  signal pipe_wrapper_i_n_567 : STD_LOGIC;
  signal pipe_wrapper_i_n_568 : STD_LOGIC;
  signal pipe_wrapper_i_n_569 : STD_LOGIC;
  signal pipe_wrapper_i_n_573 : STD_LOGIC;
  signal pipe_wrapper_i_n_574 : STD_LOGIC;
  signal pipe_wrapper_i_n_575 : STD_LOGIC;
  signal pipe_wrapper_i_n_576 : STD_LOGIC;
  signal pipe_wrapper_i_n_577 : STD_LOGIC;
  signal pipe_wrapper_i_n_578 : STD_LOGIC;
  signal pipe_wrapper_i_n_579 : STD_LOGIC;
  signal pipe_wrapper_i_n_580 : STD_LOGIC;
  signal pipe_wrapper_i_n_581 : STD_LOGIC;
  signal pipe_wrapper_i_n_582 : STD_LOGIC;
  signal pipe_wrapper_i_n_583 : STD_LOGIC;
  signal pipe_wrapper_i_n_584 : STD_LOGIC;
  signal pipe_wrapper_i_n_585 : STD_LOGIC;
  signal pipe_wrapper_i_n_586 : STD_LOGIC;
  signal pipe_wrapper_i_n_587 : STD_LOGIC;
  signal pipe_wrapper_i_n_588 : STD_LOGIC;
  signal pipe_wrapper_i_n_589 : STD_LOGIC;
  signal pipe_wrapper_i_n_590 : STD_LOGIC;
  signal pipe_wrapper_i_n_592 : STD_LOGIC;
  signal pipe_wrapper_i_n_593 : STD_LOGIC;
  signal pipe_wrapper_i_n_594 : STD_LOGIC;
  signal pipe_wrapper_i_n_595 : STD_LOGIC;
  signal pipe_wrapper_i_n_596 : STD_LOGIC;
  signal pipe_wrapper_i_n_597 : STD_LOGIC;
  signal pipe_wrapper_i_n_598 : STD_LOGIC;
  signal pipe_wrapper_i_n_599 : STD_LOGIC;
  signal pipe_wrapper_i_n_600 : STD_LOGIC;
  signal pipe_wrapper_i_n_601 : STD_LOGIC;
  signal pipe_wrapper_i_n_602 : STD_LOGIC;
  signal pipe_wrapper_i_n_603 : STD_LOGIC;
  signal pipe_wrapper_i_n_604 : STD_LOGIC;
  signal pipe_wrapper_i_n_605 : STD_LOGIC;
  signal pipe_wrapper_i_n_606 : STD_LOGIC;
  signal pipe_wrapper_i_n_607 : STD_LOGIC;
  signal pipe_wrapper_i_n_608 : STD_LOGIC;
  signal pipe_wrapper_i_n_609 : STD_LOGIC;
  signal pipe_wrapper_i_n_611 : STD_LOGIC;
  signal pipe_wrapper_i_n_612 : STD_LOGIC;
  signal pipe_wrapper_i_n_613 : STD_LOGIC;
  signal pipe_wrapper_i_n_614 : STD_LOGIC;
  signal pipe_wrapper_i_n_615 : STD_LOGIC;
  signal pipe_wrapper_i_n_616 : STD_LOGIC;
  signal pipe_wrapper_i_n_617 : STD_LOGIC;
  signal pipe_wrapper_i_n_618 : STD_LOGIC;
  signal pipe_wrapper_i_n_619 : STD_LOGIC;
  signal pipe_wrapper_i_n_620 : STD_LOGIC;
  signal pipe_wrapper_i_n_621 : STD_LOGIC;
  signal pipe_wrapper_i_n_622 : STD_LOGIC;
  signal pipe_wrapper_i_n_623 : STD_LOGIC;
  signal pipe_wrapper_i_n_624 : STD_LOGIC;
  signal pipe_wrapper_i_n_625 : STD_LOGIC;
  signal pipe_wrapper_i_n_626 : STD_LOGIC;
  signal pipe_wrapper_i_n_627 : STD_LOGIC;
  signal pipe_wrapper_i_n_628 : STD_LOGIC;
  signal pipe_wrapper_i_n_630 : STD_LOGIC;
  signal pipe_wrapper_i_n_631 : STD_LOGIC;
  signal pipe_wrapper_i_n_632 : STD_LOGIC;
  signal pipe_wrapper_i_n_633 : STD_LOGIC;
  signal pipe_wrapper_i_n_634 : STD_LOGIC;
  signal pipe_wrapper_i_n_635 : STD_LOGIC;
  signal pipe_wrapper_i_n_636 : STD_LOGIC;
  signal pipe_wrapper_i_n_637 : STD_LOGIC;
  signal pipe_wrapper_i_n_638 : STD_LOGIC;
  signal pipe_wrapper_i_n_639 : STD_LOGIC;
  signal pipe_wrapper_i_n_640 : STD_LOGIC;
  signal pipe_wrapper_i_n_641 : STD_LOGIC;
  signal pipe_wrapper_i_n_642 : STD_LOGIC;
  signal pipe_wrapper_i_n_643 : STD_LOGIC;
  signal pipe_wrapper_i_n_644 : STD_LOGIC;
  signal pipe_wrapper_i_n_645 : STD_LOGIC;
  signal pipe_wrapper_i_n_646 : STD_LOGIC;
  signal pipe_wrapper_i_n_647 : STD_LOGIC;
  signal pipe_wrapper_i_n_665 : STD_LOGIC;
  signal pipe_wrapper_i_n_680 : STD_LOGIC;
  signal pipe_wrapper_i_n_695 : STD_LOGIC;
  signal pipe_wrapper_i_n_710 : STD_LOGIC;
  signal pipe_wrapper_i_n_725 : STD_LOGIC;
  signal pipe_wrapper_i_n_740 : STD_LOGIC;
  signal pipe_wrapper_i_n_755 : STD_LOGIC;
  signal pipe_wrapper_i_n_770 : STD_LOGIC;
  signal pipe_wrapper_i_n_775 : STD_LOGIC;
  signal pipe_wrapper_i_n_776 : STD_LOGIC;
  signal pipe_wrapper_i_n_777 : STD_LOGIC;
  signal pipe_wrapper_i_n_778 : STD_LOGIC;
  signal pipe_wrapper_i_n_779 : STD_LOGIC;
  signal pipe_wrapper_i_n_780 : STD_LOGIC;
  signal pipe_wrapper_i_n_781 : STD_LOGIC;
  signal pipe_wrapper_i_n_782 : STD_LOGIC;
  signal pipe_wrapper_i_n_783 : STD_LOGIC;
  signal pipe_wrapper_i_n_784 : STD_LOGIC;
  signal pipe_wrapper_i_n_785 : STD_LOGIC;
  signal pipe_wrapper_i_n_786 : STD_LOGIC;
  signal pipe_wrapper_i_n_787 : STD_LOGIC;
  signal pipe_wrapper_i_n_788 : STD_LOGIC;
  signal pipe_wrapper_i_n_789 : STD_LOGIC;
  signal pipe_wrapper_i_n_790 : STD_LOGIC;
  signal pipe_wrapper_i_n_791 : STD_LOGIC;
  signal pipe_wrapper_i_n_792 : STD_LOGIC;
  signal pipe_wrapper_i_n_793 : STD_LOGIC;
  signal pipe_wrapper_i_n_794 : STD_LOGIC;
  signal pipe_wrapper_i_n_795 : STD_LOGIC;
  signal pipe_wrapper_i_n_796 : STD_LOGIC;
  signal pipe_wrapper_i_n_797 : STD_LOGIC;
  signal pipe_wrapper_i_n_798 : STD_LOGIC;
  signal pl_ltssm_state_q : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \pl_ltssm_state_q[5]_i_1_n_0\ : STD_LOGIC;
  signal reg_clock_locked : STD_LOGIC;
begin
  CLK_MMCM_LOCK <= \^clk_mmcm_lock\;
  CLK_PCLK <= \^clk_pclk\;
  Q <= \^q\;
  pipe_rx0_valid <= \^pipe_rx0_valid\;
  pipe_rx1_valid <= \^pipe_rx1_valid\;
  pipe_rx2_valid <= \^pipe_rx2_valid\;
  pipe_rx3_valid <= \^pipe_rx3_valid\;
  pipe_rx4_valid <= \^pipe_rx4_valid\;
  pipe_rx5_valid <= \^pipe_rx5_valid\;
  pipe_rx6_valid <= \^pipe_rx6_valid\;
  pipe_rx7_valid <= \^pipe_rx7_valid\;
\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x
     port map (
      CLK_PCLK => \^clk_pclk\,
      D(1 downto 0) => D(1 downto 0),
      PIPE_RXDATA(15) => pipe_wrapper_i_n_295,
      PIPE_RXDATA(14) => pipe_wrapper_i_n_296,
      PIPE_RXDATA(13) => pipe_wrapper_i_n_297,
      PIPE_RXDATA(12) => pipe_wrapper_i_n_298,
      PIPE_RXDATA(11) => pipe_wrapper_i_n_299,
      PIPE_RXDATA(10) => pipe_wrapper_i_n_300,
      PIPE_RXDATA(9) => pipe_wrapper_i_n_301,
      PIPE_RXDATA(8) => pipe_wrapper_i_n_302,
      PIPE_RXDATA(7) => pipe_wrapper_i_n_303,
      PIPE_RXDATA(6) => pipe_wrapper_i_n_304,
      PIPE_RXDATA(5) => pipe_wrapper_i_n_305,
      PIPE_RXDATA(4) => pipe_wrapper_i_n_306,
      PIPE_RXDATA(3) => pipe_wrapper_i_n_307,
      PIPE_RXDATA(2) => pipe_wrapper_i_n_308,
      PIPE_RXDATA(1) => pipe_wrapper_i_n_309,
      PIPE_RXDATA(0) => pipe_wrapper_i_n_310,
      PIPE_RXDATAK(1) => pipe_wrapper_i_n_375,
      PIPE_RXDATAK(0) => pipe_wrapper_i_n_376,
      PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(0),
      Q => \^q\,
      gt_rx_phy_status_q => gt_rx_phy_status_q,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(0),
      \gt_rx_status_q_reg[2]_0\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\,
      gt_rxelecidle_q => gt_rxelecidle_q,
      gt_rxvalid_q_reg_0 => pipe_wrapper_i_n_665,
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0),
      \pipe_stages_1.pipe_rx_valid_q_reg\ => \^pipe_rx0_valid\,
      \pl_ltssm_state_q_reg[5]\(5 downto 0) => pl_ltssm_state_q(5 downto 0),
      \pl_ltssm_state_q_reg[5]_0\(2) => pipe_wrapper_i_n_796,
      \pl_ltssm_state_q_reg[5]_0\(1) => pipe_wrapper_i_n_797,
      \pl_ltssm_state_q_reg[5]_0\(0) => pipe_wrapper_i_n_798
    );
\gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_22
     port map (
      CLK_PCLK => \^clk_pclk\,
      D(2) => pipe_wrapper_i_n_793,
      D(1) => pipe_wrapper_i_n_794,
      D(0) => pipe_wrapper_i_n_795,
      PIPE_RXDATA(15 downto 0) => GT_RXDATA(15 downto 0),
      PIPE_RXDATAK(1 downto 0) => GT_RXCHARISK(1 downto 0),
      PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(1),
      Q => \^q\,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(1),
      gt_rxvalid_q_reg_0 => pipe_wrapper_i_n_680,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg\,
      \pipe_stages_1.pipe_rx_phy_status_q_reg\ => \pipe_stages_1.pipe_rx_phy_status_q_reg\,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0),
      \pipe_stages_1.pipe_rx_valid_q_reg\ => \^pipe_rx1_valid\,
      \pl_ltssm_state_q_reg[4]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\,
      \pl_ltssm_state_q_reg[5]\(1) => pl_ltssm_state_q(5),
      \pl_ltssm_state_q_reg[5]\(0) => pl_ltssm_state_q(0)
    );
\gt_rx_valid_filter[2].GT_RX_VALID_FILTER_7x_inst\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_23
     port map (
      CLK_PCLK => \^clk_pclk\,
      D(2) => pipe_wrapper_i_n_790,
      D(1) => pipe_wrapper_i_n_791,
      D(0) => pipe_wrapper_i_n_792,
      PIPE_RXDATA(15) => pipe_wrapper_i_n_533,
      PIPE_RXDATA(14) => pipe_wrapper_i_n_534,
      PIPE_RXDATA(13) => pipe_wrapper_i_n_535,
      PIPE_RXDATA(12) => pipe_wrapper_i_n_536,
      PIPE_RXDATA(11) => pipe_wrapper_i_n_537,
      PIPE_RXDATA(10) => pipe_wrapper_i_n_538,
      PIPE_RXDATA(9) => pipe_wrapper_i_n_539,
      PIPE_RXDATA(8) => pipe_wrapper_i_n_540,
      PIPE_RXDATA(7) => pipe_wrapper_i_n_541,
      PIPE_RXDATA(6) => pipe_wrapper_i_n_542,
      PIPE_RXDATA(5) => pipe_wrapper_i_n_543,
      PIPE_RXDATA(4) => pipe_wrapper_i_n_544,
      PIPE_RXDATA(3) => pipe_wrapper_i_n_545,
      PIPE_RXDATA(2) => pipe_wrapper_i_n_546,
      PIPE_RXDATA(1) => pipe_wrapper_i_n_547,
      PIPE_RXDATA(0) => pipe_wrapper_i_n_548,
      PIPE_RXDATAK(1) => pipe_wrapper_i_n_549,
      PIPE_RXDATAK(0) => pipe_wrapper_i_n_550,
      PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(2),
      Q => \^q\,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(2),
      gt_rxvalid_q_reg_0 => pipe_wrapper_i_n_695,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\,
      \pipe_stages_1.pipe_rx_phy_status_q_reg\ => \pipe_stages_1.pipe_rx_phy_status_q_reg_0\,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0),
      \pipe_stages_1.pipe_rx_valid_q_reg\ => \^pipe_rx2_valid\,
      \pl_ltssm_state_q_reg[4]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\,
      \pl_ltssm_state_q_reg[5]\(1) => pl_ltssm_state_q(5),
      \pl_ltssm_state_q_reg[5]\(0) => pl_ltssm_state_q(0)
    );
\gt_rx_valid_filter[3].GT_RX_VALID_FILTER_7x_inst\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_24
     port map (
      CLK_PCLK => \^clk_pclk\,
      D(2) => pipe_wrapper_i_n_787,
      D(1) => pipe_wrapper_i_n_788,
      D(0) => pipe_wrapper_i_n_789,
      PIPE_RXDATA(15) => pipe_wrapper_i_n_552,
      PIPE_RXDATA(14) => pipe_wrapper_i_n_553,
      PIPE_RXDATA(13) => pipe_wrapper_i_n_554,
      PIPE_RXDATA(12) => pipe_wrapper_i_n_555,
      PIPE_RXDATA(11) => pipe_wrapper_i_n_556,
      PIPE_RXDATA(10) => pipe_wrapper_i_n_557,
      PIPE_RXDATA(9) => pipe_wrapper_i_n_558,
      PIPE_RXDATA(8) => pipe_wrapper_i_n_559,
      PIPE_RXDATA(7) => pipe_wrapper_i_n_560,
      PIPE_RXDATA(6) => pipe_wrapper_i_n_561,
      PIPE_RXDATA(5) => pipe_wrapper_i_n_562,
      PIPE_RXDATA(4) => pipe_wrapper_i_n_563,
      PIPE_RXDATA(3) => pipe_wrapper_i_n_564,
      PIPE_RXDATA(2) => pipe_wrapper_i_n_565,
      PIPE_RXDATA(1) => pipe_wrapper_i_n_566,
      PIPE_RXDATA(0) => pipe_wrapper_i_n_567,
      PIPE_RXDATAK(1) => pipe_wrapper_i_n_568,
      PIPE_RXDATAK(0) => pipe_wrapper_i_n_569,
      PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(3),
      Q => \^q\,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(3),
      gt_rxvalid_q_reg_0 => pipe_wrapper_i_n_710,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_2\(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg_1\,
      \pipe_stages_1.pipe_rx_phy_status_q_reg\ => \pipe_stages_1.pipe_rx_phy_status_q_reg_1\,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(2 downto 0),
      \pipe_stages_1.pipe_rx_valid_q_reg\ => \^pipe_rx3_valid\,
      \pl_ltssm_state_q_reg[4]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\,
      \pl_ltssm_state_q_reg[5]\(1) => pl_ltssm_state_q(5),
      \pl_ltssm_state_q_reg[5]\(0) => pl_ltssm_state_q(0)
    );
\gt_rx_valid_filter[4].GT_RX_VALID_FILTER_7x_inst\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_25
     port map (
      CLK_PCLK => \^clk_pclk\,
      D(2) => pipe_wrapper_i_n_784,
      D(1) => pipe_wrapper_i_n_785,
      D(0) => pipe_wrapper_i_n_786,
      PIPE_RXDATA(15) => pipe_wrapper_i_n_573,
      PIPE_RXDATA(14) => pipe_wrapper_i_n_574,
      PIPE_RXDATA(13) => pipe_wrapper_i_n_575,
      PIPE_RXDATA(12) => pipe_wrapper_i_n_576,
      PIPE_RXDATA(11) => pipe_wrapper_i_n_577,
      PIPE_RXDATA(10) => pipe_wrapper_i_n_578,
      PIPE_RXDATA(9) => pipe_wrapper_i_n_579,
      PIPE_RXDATA(8) => pipe_wrapper_i_n_580,
      PIPE_RXDATA(7) => pipe_wrapper_i_n_581,
      PIPE_RXDATA(6) => pipe_wrapper_i_n_582,
      PIPE_RXDATA(5) => pipe_wrapper_i_n_583,
      PIPE_RXDATA(4) => pipe_wrapper_i_n_584,
      PIPE_RXDATA(3) => pipe_wrapper_i_n_585,
      PIPE_RXDATA(2) => pipe_wrapper_i_n_586,
      PIPE_RXDATA(1) => pipe_wrapper_i_n_587,
      PIPE_RXDATA(0) => pipe_wrapper_i_n_588,
      PIPE_RXDATAK(1) => pipe_wrapper_i_n_589,
      PIPE_RXDATAK(0) => pipe_wrapper_i_n_590,
      PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(4),
      Q => \^q\,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(4),
      gt_rxvalid_q_reg_0 => pipe_wrapper_i_n_725,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2\(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_3\(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg_2\,
      \pipe_stages_1.pipe_rx_phy_status_q_reg\ => \pipe_stages_1.pipe_rx_phy_status_q_reg_2\,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_3\(2 downto 0),
      \pipe_stages_1.pipe_rx_valid_q_reg\ => \^pipe_rx4_valid\,
      \pl_ltssm_state_q_reg[4]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\,
      \pl_ltssm_state_q_reg[5]\(1) => pl_ltssm_state_q(5),
      \pl_ltssm_state_q_reg[5]\(0) => pl_ltssm_state_q(0)
    );
\gt_rx_valid_filter[5].GT_RX_VALID_FILTER_7x_inst\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_26
     port map (
      CLK_PCLK => \^clk_pclk\,
      D(2) => pipe_wrapper_i_n_781,
      D(1) => pipe_wrapper_i_n_782,
      D(0) => pipe_wrapper_i_n_783,
      PIPE_RXDATA(15) => pipe_wrapper_i_n_592,
      PIPE_RXDATA(14) => pipe_wrapper_i_n_593,
      PIPE_RXDATA(13) => pipe_wrapper_i_n_594,
      PIPE_RXDATA(12) => pipe_wrapper_i_n_595,
      PIPE_RXDATA(11) => pipe_wrapper_i_n_596,
      PIPE_RXDATA(10) => pipe_wrapper_i_n_597,
      PIPE_RXDATA(9) => pipe_wrapper_i_n_598,
      PIPE_RXDATA(8) => pipe_wrapper_i_n_599,
      PIPE_RXDATA(7) => pipe_wrapper_i_n_600,
      PIPE_RXDATA(6) => pipe_wrapper_i_n_601,
      PIPE_RXDATA(5) => pipe_wrapper_i_n_602,
      PIPE_RXDATA(4) => pipe_wrapper_i_n_603,
      PIPE_RXDATA(3) => pipe_wrapper_i_n_604,
      PIPE_RXDATA(2) => pipe_wrapper_i_n_605,
      PIPE_RXDATA(1) => pipe_wrapper_i_n_606,
      PIPE_RXDATA(0) => pipe_wrapper_i_n_607,
      PIPE_RXDATAK(1) => pipe_wrapper_i_n_608,
      PIPE_RXDATAK(0) => pipe_wrapper_i_n_609,
      PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(5),
      Q => \^q\,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(5),
      gt_rxvalid_q_reg_0 => pipe_wrapper_i_n_740,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3\(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_4\(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg_3\,
      \pipe_stages_1.pipe_rx_phy_status_q_reg\ => \pipe_stages_1.pipe_rx_phy_status_q_reg_3\,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_4\(2 downto 0),
      \pipe_stages_1.pipe_rx_valid_q_reg\ => \^pipe_rx5_valid\,
      \pl_ltssm_state_q_reg[4]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\,
      \pl_ltssm_state_q_reg[5]\(1) => pl_ltssm_state_q(5),
      \pl_ltssm_state_q_reg[5]\(0) => pl_ltssm_state_q(0)
    );
\gt_rx_valid_filter[6].GT_RX_VALID_FILTER_7x_inst\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_27
     port map (
      CLK_PCLK => \^clk_pclk\,
      D(2) => pipe_wrapper_i_n_778,
      D(1) => pipe_wrapper_i_n_779,
      D(0) => pipe_wrapper_i_n_780,
      PIPE_RXDATA(15) => pipe_wrapper_i_n_611,
      PIPE_RXDATA(14) => pipe_wrapper_i_n_612,
      PIPE_RXDATA(13) => pipe_wrapper_i_n_613,
      PIPE_RXDATA(12) => pipe_wrapper_i_n_614,
      PIPE_RXDATA(11) => pipe_wrapper_i_n_615,
      PIPE_RXDATA(10) => pipe_wrapper_i_n_616,
      PIPE_RXDATA(9) => pipe_wrapper_i_n_617,
      PIPE_RXDATA(8) => pipe_wrapper_i_n_618,
      PIPE_RXDATA(7) => pipe_wrapper_i_n_619,
      PIPE_RXDATA(6) => pipe_wrapper_i_n_620,
      PIPE_RXDATA(5) => pipe_wrapper_i_n_621,
      PIPE_RXDATA(4) => pipe_wrapper_i_n_622,
      PIPE_RXDATA(3) => pipe_wrapper_i_n_623,
      PIPE_RXDATA(2) => pipe_wrapper_i_n_624,
      PIPE_RXDATA(1) => pipe_wrapper_i_n_625,
      PIPE_RXDATA(0) => pipe_wrapper_i_n_626,
      PIPE_RXDATAK(1) => pipe_wrapper_i_n_627,
      PIPE_RXDATAK(0) => pipe_wrapper_i_n_628,
      PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(6),
      Q => \^q\,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(6),
      gt_rxvalid_q_reg_0 => pipe_wrapper_i_n_755,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4\(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_5\(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg_4\,
      \pipe_stages_1.pipe_rx_phy_status_q_reg\ => \pipe_stages_1.pipe_rx_phy_status_q_reg_4\,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_5\(2 downto 0),
      \pipe_stages_1.pipe_rx_valid_q_reg\ => \^pipe_rx6_valid\,
      \pl_ltssm_state_q_reg[4]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\,
      \pl_ltssm_state_q_reg[5]\(1) => pl_ltssm_state_q(5),
      \pl_ltssm_state_q_reg[5]\(0) => pl_ltssm_state_q(0)
    );
\gt_rx_valid_filter[7].GT_RX_VALID_FILTER_7x_inst\: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_28
     port map (
      CLK_PCLK => \^clk_pclk\,
      D(2) => pipe_wrapper_i_n_775,
      D(1) => pipe_wrapper_i_n_776,
      D(0) => pipe_wrapper_i_n_777,
      PIPE_RXDATA(15) => pipe_wrapper_i_n_630,
      PIPE_RXDATA(14) => pipe_wrapper_i_n_631,
      PIPE_RXDATA(13) => pipe_wrapper_i_n_632,
      PIPE_RXDATA(12) => pipe_wrapper_i_n_633,
      PIPE_RXDATA(11) => pipe_wrapper_i_n_634,
      PIPE_RXDATA(10) => pipe_wrapper_i_n_635,
      PIPE_RXDATA(9) => pipe_wrapper_i_n_636,
      PIPE_RXDATA(8) => pipe_wrapper_i_n_637,
      PIPE_RXDATA(7) => pipe_wrapper_i_n_638,
      PIPE_RXDATA(6) => pipe_wrapper_i_n_639,
      PIPE_RXDATA(5) => pipe_wrapper_i_n_640,
      PIPE_RXDATA(4) => pipe_wrapper_i_n_641,
      PIPE_RXDATA(3) => pipe_wrapper_i_n_642,
      PIPE_RXDATA(2) => pipe_wrapper_i_n_643,
      PIPE_RXDATA(1) => pipe_wrapper_i_n_644,
      PIPE_RXDATA(0) => pipe_wrapper_i_n_645,
      PIPE_RXDATAK(1) => pipe_wrapper_i_n_646,
      PIPE_RXDATAK(0) => pipe_wrapper_i_n_647,
      PIPE_RXELECIDLE(0) => gt_rx_elec_idle_wire_filter(7),
      Q => \^q\,
      gt_rx_phy_status_wire_filter(0) => gt_rx_phy_status_wire_filter(7),
      gt_rxvalid_q_reg_0 => pipe_wrapper_i_n_770,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5\(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_6\(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => \pipe_stages_1.pipe_rx_elec_idle_q_reg_5\,
      \pipe_stages_1.pipe_rx_phy_status_q_reg\ => \pipe_stages_1.pipe_rx_phy_status_q_reg_5\,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_6\(2 downto 0),
      \pipe_stages_1.pipe_rx_valid_q_reg\ => \^pipe_rx7_valid\,
      \pl_ltssm_state_q_reg[4]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\,
      \pl_ltssm_state_q_reg[5]\(1) => pl_ltssm_state_q(5),
      \pl_ltssm_state_q_reg[5]\(0) => pl_ltssm_state_q(0)
    );
\gtx_channel.gtxe2_channel_i_i_10__0__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => GT_TXPMARESET092_out,
      I1 => p_1_in88_in,
      O => GT_RXPMARESET089_out
    );
\gtx_channel.gtxe2_channel_i_i_10__1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => GT_TXPMARESET064_out,
      I1 => p_1_in60_in,
      O => GT_RXPMARESET061_out
    );
\gtx_channel.gtxe2_channel_i_i_10__2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => GT_TXPMARESET046_out,
      I1 => p_1_in42_in,
      O => GT_RXPMARESET043_out
    );
\gtx_channel.gtxe2_channel_i_i_10__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => GT_TXPMARESET0,
      I1 => p_1_in,
      O => GT_RXPMARESET0
    );
\gtx_channel.gtxe2_channel_i_i_11__0__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => GT_TXPMARESET074_out,
      I1 => p_1_in70_in,
      O => GT_RXPMARESET071_out
    );
\gtx_channel.gtxe2_channel_i_i_11__1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => GT_TXPMARESET035_out,
      I1 => p_1_in31_in,
      O => GT_RXPMARESET032_out
    );
\gtx_channel.gtxe2_channel_i_i_11__2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => GT_TXPMARESET017_out,
      I1 => p_1_in13_in,
      O => GT_RXPMARESET014_out
    );
\gtx_channel.gtxe2_channel_i_i_11__3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => GT_TXPMARESET0120_out,
      I1 => p_1_in116_in,
      O => GT_RXPMARESET0117_out
    );
pcie_block_i_i_29: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^q\,
      O => sys_rst_n
    );
phy_rdy_n_int_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => reg_clock_locked,
      O => phy_rdy_n_int_i_2_n_0
    );
phy_rdy_n_int_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      CLR => phy_rdy_n_int_i_2_n_0,
      D => all_phystatus_rst,
      Q => \^q\
    );
pipe_wrapper_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pipe_wrapper
     port map (
      CLK_DCLK => CLK_DCLK,
      CLK_MMCM_LOCK => \^clk_mmcm_lock\,
      CLK_OOBCLK => \^clk_pclk\,
      CLK_PCLK_SEL(7 downto 0) => pclk_sel_reg1_reg(7 downto 0),
      CLK_USERCLK1 => CLK_USERCLK1,
      D => all_phystatus_rst,
      DRP_FSM(2 downto 0) => \index_reg[1]\(2 downto 0),
      EQ_GEN3 => rate_gen3(0),
      GT_RXPMARESET0 => GT_RXPMARESET0,
      GT_RXPMARESET0117_out => GT_RXPMARESET0117_out,
      GT_RXPMARESET014_out => GT_RXPMARESET014_out,
      GT_RXPMARESET032_out => GT_RXPMARESET032_out,
      GT_RXPMARESET043_out => GT_RXPMARESET043_out,
      GT_RXPMARESET061_out => GT_RXPMARESET061_out,
      GT_RXPMARESET071_out => GT_RXPMARESET071_out,
      GT_RXPMARESET089_out => GT_RXPMARESET089_out,
      GT_TXPMARESET0 => GT_TXPMARESET0,
      GT_TXPMARESET0120_out => GT_TXPMARESET0120_out,
      GT_TXPMARESET017_out => GT_TXPMARESET017_out,
      GT_TXPMARESET035_out => GT_TXPMARESET035_out,
      GT_TXPMARESET046_out => GT_TXPMARESET046_out,
      GT_TXPMARESET064_out => GT_TXPMARESET064_out,
      GT_TXPMARESET074_out => GT_TXPMARESET074_out,
      GT_TXPMARESET092_out => GT_TXPMARESET092_out,
      PIPE_POWERDOWN(15 downto 0) => PIPE_POWERDOWN(15 downto 0),
      PIPE_RXCHANISALIGNED(7 downto 0) => PIPE_RXCHANISALIGNED(7 downto 0),
      PIPE_RXDATA(15) => pipe_wrapper_i_n_295,
      PIPE_RXDATA(14) => pipe_wrapper_i_n_296,
      PIPE_RXDATA(13) => pipe_wrapper_i_n_297,
      PIPE_RXDATA(12) => pipe_wrapper_i_n_298,
      PIPE_RXDATA(11) => pipe_wrapper_i_n_299,
      PIPE_RXDATA(10) => pipe_wrapper_i_n_300,
      PIPE_RXDATA(9) => pipe_wrapper_i_n_301,
      PIPE_RXDATA(8) => pipe_wrapper_i_n_302,
      PIPE_RXDATA(7) => pipe_wrapper_i_n_303,
      PIPE_RXDATA(6) => pipe_wrapper_i_n_304,
      PIPE_RXDATA(5) => pipe_wrapper_i_n_305,
      PIPE_RXDATA(4) => pipe_wrapper_i_n_306,
      PIPE_RXDATA(3) => pipe_wrapper_i_n_307,
      PIPE_RXDATA(2) => pipe_wrapper_i_n_308,
      PIPE_RXDATA(1) => pipe_wrapper_i_n_309,
      PIPE_RXDATA(0) => pipe_wrapper_i_n_310,
      PIPE_RXDATAK(1) => pipe_wrapper_i_n_375,
      PIPE_RXDATAK(0) => pipe_wrapper_i_n_376,
      PIPE_RXPOLARITY(7 downto 0) => PIPE_RXPOLARITY(7 downto 0),
      PIPE_TXCOMPLIANCE(7 downto 0) => PIPE_TXCOMPLIANCE(7 downto 0),
      PIPE_TXDATA(127 downto 0) => PIPE_TXDATA(127 downto 0),
      PIPE_TXDATAK(15 downto 0) => PIPE_TXDATAK(15 downto 0),
      PIPE_TXDEEMPH(3 downto 0) => PIPE_TXDEEMPH(3 downto 0),
      PIPE_TXDETECTRX => PIPE_TXDETECTRX,
      PIPE_TXELECIDLE(7 downto 0) => PIPE_TXELECIDLE(7 downto 0),
      PIPE_TXMARGIN(2 downto 0) => PIPE_TXMARGIN(2 downto 0),
      Q(1) => pl_ltssm_state_q(5),
      Q(0) => pl_ltssm_state_q(0),
      QRST_CPLLLOCK(7 downto 0) => PIPE_CPLL_LOCK(7 downto 0),
      QRST_QPLLLOCK(1 downto 0) => PIPE_QPLL_LOCK(1 downto 0),
      RATE_FSM(4 downto 0) => \sysclksel_reg[1]\(4 downto 0),
      SYNC_FSM_TX(5 downto 0) => \txsync_fsm.txsync_done_reg\(5 downto 0),
      SYNC_RXPHALIGNDONE_M => pipe_rxphaligndone(0),
      TXMARGIN(2 downto 0) => TXMARGIN(2 downto 0),
      USER_RXPMARESET => p_1_in,
      \cplllock_reg1_reg[1]\ => p_1_in88_in,
      \cplllock_reg1_reg[2]\ => p_1_in116_in,
      \cplllock_reg1_reg[3]\ => INT_QPLLOUTCLK_OUT(0),
      \cplllock_reg1_reg[3]_0\ => INT_QPLLOUTREFCLK_OUT(0),
      \cplllock_reg1_reg[3]_1\ => p_1_in70_in,
      \cplllock_reg1_reg[4]\ => p_1_in60_in,
      \cplllock_reg1_reg[5]\ => p_1_in42_in,
      \cplllock_reg1_reg[6]\ => p_1_in31_in,
      \cplllock_reg1_reg[7]\ => INT_QPLLOUTCLK_OUT(1),
      \cplllock_reg1_reg[7]_0\ => INT_QPLLOUTREFCLK_OUT(1),
      \cplllock_reg1_reg[7]_1\ => p_1_in13_in,
      ext_ch_gt_drpaddr(71 downto 0) => ext_ch_gt_drpaddr(71 downto 0),
      ext_ch_gt_drpdi(127 downto 0) => ext_ch_gt_drpdi(127 downto 0),
      ext_ch_gt_drpdo(127 downto 0) => ext_ch_gt_drpdo(127 downto 0),
      ext_ch_gt_drpen(7 downto 0) => ext_ch_gt_drpen(7 downto 0),
      ext_ch_gt_drprdy(7 downto 0) => ext_ch_gt_drprdy(7 downto 0),
      ext_ch_gt_drpwe(7 downto 0) => ext_ch_gt_drpwe(7 downto 0),
      gt_ch_drp_rdy(7 downto 0) => gt_ch_drp_rdy(7 downto 0),
      gt_rx_elec_idle_wire_filter(7 downto 0) => gt_rx_elec_idle_wire_filter(7 downto 0),
      gt_rx_phy_status_wire_filter(7 downto 0) => gt_rx_phy_status_wire_filter(7 downto 0),
      \gt_rx_status_q_reg[2]\(2) => pipe_wrapper_i_n_775,
      \gt_rx_status_q_reg[2]\(1) => pipe_wrapper_i_n_776,
      \gt_rx_status_q_reg[2]\(0) => pipe_wrapper_i_n_777,
      \gt_rx_status_q_reg[2]_0\(2) => pipe_wrapper_i_n_778,
      \gt_rx_status_q_reg[2]_0\(1) => pipe_wrapper_i_n_779,
      \gt_rx_status_q_reg[2]_0\(0) => pipe_wrapper_i_n_780,
      \gt_rx_status_q_reg[2]_1\(2) => pipe_wrapper_i_n_781,
      \gt_rx_status_q_reg[2]_1\(1) => pipe_wrapper_i_n_782,
      \gt_rx_status_q_reg[2]_1\(0) => pipe_wrapper_i_n_783,
      \gt_rx_status_q_reg[2]_2\(2) => pipe_wrapper_i_n_784,
      \gt_rx_status_q_reg[2]_2\(1) => pipe_wrapper_i_n_785,
      \gt_rx_status_q_reg[2]_2\(0) => pipe_wrapper_i_n_786,
      \gt_rx_status_q_reg[2]_3\(2) => pipe_wrapper_i_n_787,
      \gt_rx_status_q_reg[2]_3\(1) => pipe_wrapper_i_n_788,
      \gt_rx_status_q_reg[2]_3\(0) => pipe_wrapper_i_n_789,
      \gt_rx_status_q_reg[2]_4\(2) => pipe_wrapper_i_n_790,
      \gt_rx_status_q_reg[2]_4\(1) => pipe_wrapper_i_n_791,
      \gt_rx_status_q_reg[2]_4\(0) => pipe_wrapper_i_n_792,
      \gt_rx_status_q_reg[2]_5\(2) => pipe_wrapper_i_n_793,
      \gt_rx_status_q_reg[2]_5\(1) => pipe_wrapper_i_n_794,
      \gt_rx_status_q_reg[2]_5\(0) => pipe_wrapper_i_n_795,
      \gt_rx_status_q_reg[2]_6\(2) => pipe_wrapper_i_n_796,
      \gt_rx_status_q_reg[2]_6\(1) => pipe_wrapper_i_n_797,
      \gt_rx_status_q_reg[2]_6\(0) => pipe_wrapper_i_n_798,
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => GT_RXCHARISK(1 downto 0),
      \gt_rxcharisk_q_reg[1]_0\(1) => pipe_wrapper_i_n_549,
      \gt_rxcharisk_q_reg[1]_0\(0) => pipe_wrapper_i_n_550,
      \gt_rxcharisk_q_reg[1]_1\(1) => pipe_wrapper_i_n_568,
      \gt_rxcharisk_q_reg[1]_1\(0) => pipe_wrapper_i_n_569,
      \gt_rxcharisk_q_reg[1]_2\(1) => pipe_wrapper_i_n_589,
      \gt_rxcharisk_q_reg[1]_2\(0) => pipe_wrapper_i_n_590,
      \gt_rxcharisk_q_reg[1]_3\(1) => pipe_wrapper_i_n_608,
      \gt_rxcharisk_q_reg[1]_3\(0) => pipe_wrapper_i_n_609,
      \gt_rxcharisk_q_reg[1]_4\(1) => pipe_wrapper_i_n_627,
      \gt_rxcharisk_q_reg[1]_4\(0) => pipe_wrapper_i_n_628,
      \gt_rxcharisk_q_reg[1]_5\(1) => pipe_wrapper_i_n_646,
      \gt_rxcharisk_q_reg[1]_5\(0) => pipe_wrapper_i_n_647,
      \gt_rxdata_q_reg[15]\(15 downto 0) => GT_RXDATA(15 downto 0),
      \gt_rxdata_q_reg[15]_0\(15) => pipe_wrapper_i_n_533,
      \gt_rxdata_q_reg[15]_0\(14) => pipe_wrapper_i_n_534,
      \gt_rxdata_q_reg[15]_0\(13) => pipe_wrapper_i_n_535,
      \gt_rxdata_q_reg[15]_0\(12) => pipe_wrapper_i_n_536,
      \gt_rxdata_q_reg[15]_0\(11) => pipe_wrapper_i_n_537,
      \gt_rxdata_q_reg[15]_0\(10) => pipe_wrapper_i_n_538,
      \gt_rxdata_q_reg[15]_0\(9) => pipe_wrapper_i_n_539,
      \gt_rxdata_q_reg[15]_0\(8) => pipe_wrapper_i_n_540,
      \gt_rxdata_q_reg[15]_0\(7) => pipe_wrapper_i_n_541,
      \gt_rxdata_q_reg[15]_0\(6) => pipe_wrapper_i_n_542,
      \gt_rxdata_q_reg[15]_0\(5) => pipe_wrapper_i_n_543,
      \gt_rxdata_q_reg[15]_0\(4) => pipe_wrapper_i_n_544,
      \gt_rxdata_q_reg[15]_0\(3) => pipe_wrapper_i_n_545,
      \gt_rxdata_q_reg[15]_0\(2) => pipe_wrapper_i_n_546,
      \gt_rxdata_q_reg[15]_0\(1) => pipe_wrapper_i_n_547,
      \gt_rxdata_q_reg[15]_0\(0) => pipe_wrapper_i_n_548,
      \gt_rxdata_q_reg[15]_1\(15) => pipe_wrapper_i_n_552,
      \gt_rxdata_q_reg[15]_1\(14) => pipe_wrapper_i_n_553,
      \gt_rxdata_q_reg[15]_1\(13) => pipe_wrapper_i_n_554,
      \gt_rxdata_q_reg[15]_1\(12) => pipe_wrapper_i_n_555,
      \gt_rxdata_q_reg[15]_1\(11) => pipe_wrapper_i_n_556,
      \gt_rxdata_q_reg[15]_1\(10) => pipe_wrapper_i_n_557,
      \gt_rxdata_q_reg[15]_1\(9) => pipe_wrapper_i_n_558,
      \gt_rxdata_q_reg[15]_1\(8) => pipe_wrapper_i_n_559,
      \gt_rxdata_q_reg[15]_1\(7) => pipe_wrapper_i_n_560,
      \gt_rxdata_q_reg[15]_1\(6) => pipe_wrapper_i_n_561,
      \gt_rxdata_q_reg[15]_1\(5) => pipe_wrapper_i_n_562,
      \gt_rxdata_q_reg[15]_1\(4) => pipe_wrapper_i_n_563,
      \gt_rxdata_q_reg[15]_1\(3) => pipe_wrapper_i_n_564,
      \gt_rxdata_q_reg[15]_1\(2) => pipe_wrapper_i_n_565,
      \gt_rxdata_q_reg[15]_1\(1) => pipe_wrapper_i_n_566,
      \gt_rxdata_q_reg[15]_1\(0) => pipe_wrapper_i_n_567,
      \gt_rxdata_q_reg[15]_2\(15) => pipe_wrapper_i_n_573,
      \gt_rxdata_q_reg[15]_2\(14) => pipe_wrapper_i_n_574,
      \gt_rxdata_q_reg[15]_2\(13) => pipe_wrapper_i_n_575,
      \gt_rxdata_q_reg[15]_2\(12) => pipe_wrapper_i_n_576,
      \gt_rxdata_q_reg[15]_2\(11) => pipe_wrapper_i_n_577,
      \gt_rxdata_q_reg[15]_2\(10) => pipe_wrapper_i_n_578,
      \gt_rxdata_q_reg[15]_2\(9) => pipe_wrapper_i_n_579,
      \gt_rxdata_q_reg[15]_2\(8) => pipe_wrapper_i_n_580,
      \gt_rxdata_q_reg[15]_2\(7) => pipe_wrapper_i_n_581,
      \gt_rxdata_q_reg[15]_2\(6) => pipe_wrapper_i_n_582,
      \gt_rxdata_q_reg[15]_2\(5) => pipe_wrapper_i_n_583,
      \gt_rxdata_q_reg[15]_2\(4) => pipe_wrapper_i_n_584,
      \gt_rxdata_q_reg[15]_2\(3) => pipe_wrapper_i_n_585,
      \gt_rxdata_q_reg[15]_2\(2) => pipe_wrapper_i_n_586,
      \gt_rxdata_q_reg[15]_2\(1) => pipe_wrapper_i_n_587,
      \gt_rxdata_q_reg[15]_2\(0) => pipe_wrapper_i_n_588,
      \gt_rxdata_q_reg[15]_3\(15) => pipe_wrapper_i_n_592,
      \gt_rxdata_q_reg[15]_3\(14) => pipe_wrapper_i_n_593,
      \gt_rxdata_q_reg[15]_3\(13) => pipe_wrapper_i_n_594,
      \gt_rxdata_q_reg[15]_3\(12) => pipe_wrapper_i_n_595,
      \gt_rxdata_q_reg[15]_3\(11) => pipe_wrapper_i_n_596,
      \gt_rxdata_q_reg[15]_3\(10) => pipe_wrapper_i_n_597,
      \gt_rxdata_q_reg[15]_3\(9) => pipe_wrapper_i_n_598,
      \gt_rxdata_q_reg[15]_3\(8) => pipe_wrapper_i_n_599,
      \gt_rxdata_q_reg[15]_3\(7) => pipe_wrapper_i_n_600,
      \gt_rxdata_q_reg[15]_3\(6) => pipe_wrapper_i_n_601,
      \gt_rxdata_q_reg[15]_3\(5) => pipe_wrapper_i_n_602,
      \gt_rxdata_q_reg[15]_3\(4) => pipe_wrapper_i_n_603,
      \gt_rxdata_q_reg[15]_3\(3) => pipe_wrapper_i_n_604,
      \gt_rxdata_q_reg[15]_3\(2) => pipe_wrapper_i_n_605,
      \gt_rxdata_q_reg[15]_3\(1) => pipe_wrapper_i_n_606,
      \gt_rxdata_q_reg[15]_3\(0) => pipe_wrapper_i_n_607,
      \gt_rxdata_q_reg[15]_4\(15) => pipe_wrapper_i_n_611,
      \gt_rxdata_q_reg[15]_4\(14) => pipe_wrapper_i_n_612,
      \gt_rxdata_q_reg[15]_4\(13) => pipe_wrapper_i_n_613,
      \gt_rxdata_q_reg[15]_4\(12) => pipe_wrapper_i_n_614,
      \gt_rxdata_q_reg[15]_4\(11) => pipe_wrapper_i_n_615,
      \gt_rxdata_q_reg[15]_4\(10) => pipe_wrapper_i_n_616,
      \gt_rxdata_q_reg[15]_4\(9) => pipe_wrapper_i_n_617,
      \gt_rxdata_q_reg[15]_4\(8) => pipe_wrapper_i_n_618,
      \gt_rxdata_q_reg[15]_4\(7) => pipe_wrapper_i_n_619,
      \gt_rxdata_q_reg[15]_4\(6) => pipe_wrapper_i_n_620,
      \gt_rxdata_q_reg[15]_4\(5) => pipe_wrapper_i_n_621,
      \gt_rxdata_q_reg[15]_4\(4) => pipe_wrapper_i_n_622,
      \gt_rxdata_q_reg[15]_4\(3) => pipe_wrapper_i_n_623,
      \gt_rxdata_q_reg[15]_4\(2) => pipe_wrapper_i_n_624,
      \gt_rxdata_q_reg[15]_4\(1) => pipe_wrapper_i_n_625,
      \gt_rxdata_q_reg[15]_4\(0) => pipe_wrapper_i_n_626,
      \gt_rxdata_q_reg[15]_5\(15) => pipe_wrapper_i_n_630,
      \gt_rxdata_q_reg[15]_5\(14) => pipe_wrapper_i_n_631,
      \gt_rxdata_q_reg[15]_5\(13) => pipe_wrapper_i_n_632,
      \gt_rxdata_q_reg[15]_5\(12) => pipe_wrapper_i_n_633,
      \gt_rxdata_q_reg[15]_5\(11) => pipe_wrapper_i_n_634,
      \gt_rxdata_q_reg[15]_5\(10) => pipe_wrapper_i_n_635,
      \gt_rxdata_q_reg[15]_5\(9) => pipe_wrapper_i_n_636,
      \gt_rxdata_q_reg[15]_5\(8) => pipe_wrapper_i_n_637,
      \gt_rxdata_q_reg[15]_5\(7) => pipe_wrapper_i_n_638,
      \gt_rxdata_q_reg[15]_5\(6) => pipe_wrapper_i_n_639,
      \gt_rxdata_q_reg[15]_5\(5) => pipe_wrapper_i_n_640,
      \gt_rxdata_q_reg[15]_5\(4) => pipe_wrapper_i_n_641,
      \gt_rxdata_q_reg[15]_5\(3) => pipe_wrapper_i_n_642,
      \gt_rxdata_q_reg[15]_5\(2) => pipe_wrapper_i_n_643,
      \gt_rxdata_q_reg[15]_5\(1) => pipe_wrapper_i_n_644,
      \gt_rxdata_q_reg[15]_5\(0) => pipe_wrapper_i_n_645,
      gt_rxvalid_q_reg => pipe_wrapper_i_n_665,
      gt_rxvalid_q_reg_0 => pipe_wrapper_i_n_680,
      gt_rxvalid_q_reg_1 => pipe_wrapper_i_n_695,
      gt_rxvalid_q_reg_10 => \^pipe_rx3_valid\,
      gt_rxvalid_q_reg_11 => \^pipe_rx4_valid\,
      gt_rxvalid_q_reg_12 => \^pipe_rx5_valid\,
      gt_rxvalid_q_reg_13 => \^pipe_rx6_valid\,
      gt_rxvalid_q_reg_14 => \^pipe_rx7_valid\,
      gt_rxvalid_q_reg_2 => pipe_wrapper_i_n_710,
      gt_rxvalid_q_reg_3 => pipe_wrapper_i_n_725,
      gt_rxvalid_q_reg_4 => pipe_wrapper_i_n_740,
      gt_rxvalid_q_reg_5 => pipe_wrapper_i_n_755,
      gt_rxvalid_q_reg_6 => pipe_wrapper_i_n_770,
      gt_rxvalid_q_reg_7 => \^pipe_rx0_valid\,
      gt_rxvalid_q_reg_8 => \^pipe_rx1_valid\,
      gt_rxvalid_q_reg_9 => \^pipe_rx2_valid\,
      \index_reg[1]\(2 downto 0) => \index_reg[1]_0\(2 downto 0),
      \index_reg[1]_0\(2 downto 0) => \index_reg[1]_1\(2 downto 0),
      \index_reg[1]_1\(2 downto 0) => \index_reg[1]_2\(2 downto 0),
      \index_reg[1]_2\(2 downto 0) => \index_reg[1]_3\(2 downto 0),
      \index_reg[1]_3\(2 downto 0) => \index_reg[1]_4\(2 downto 0),
      \index_reg[1]_4\(2 downto 0) => \index_reg[1]_5\(2 downto 0),
      \index_reg[1]_5\(2 downto 0) => \index_reg[1]_6\(2 downto 0),
      int_pclk_sel_slave(7 downto 0) => int_pclk_sel_slave(7 downto 0),
      \out\(1 downto 0) => \out\(1 downto 0),
      pci_exp_rxn(7 downto 0) => pci_exp_rxn(7 downto 0),
      pci_exp_rxp(7 downto 0) => pci_exp_rxp(7 downto 0),
      pci_exp_txn(7 downto 0) => pci_exp_txn(7 downto 0),
      pci_exp_txp(7 downto 0) => pci_exp_txp(7 downto 0),
      pipe_dmonitorout(63 downto 0) => pipe_dmonitorout(63 downto 0),
      pipe_eyescandataerror(7 downto 0) => pipe_eyescandataerror(7 downto 0),
      pipe_mmcm_rst_n => pipe_mmcm_rst_n,
      pipe_qrst_fsm(3 downto 0) => pipe_qrst_fsm(3 downto 0),
      pipe_qrst_idle => pipe_qrst_idle,
      pipe_rate_idle => pipe_rate_idle,
      pipe_rst_fsm(3 downto 0) => pipe_rst_fsm(3 downto 0),
      pipe_rxbufstatus(23 downto 0) => pipe_rxbufstatus(23 downto 0),
      pipe_rxcommadet(7 downto 0) => pipe_rxcommadet(7 downto 0),
      pipe_rxdisperr(63 downto 0) => pipe_rxdisperr(63 downto 0),
      pipe_rxdlysresetdone(7 downto 0) => pipe_rxdlysresetdone(7 downto 0),
      pipe_rxnotintable(63 downto 0) => pipe_rxnotintable(63 downto 0),
      pipe_rxoutclk_out(7 downto 0) => pipe_rxoutclk_out(7 downto 0),
      pipe_rxphaligndone(6 downto 0) => pipe_rxphaligndone(7 downto 1),
      pipe_rxprbserr(7 downto 0) => pipe_rxprbserr(7 downto 0),
      pipe_rxstatus(23 downto 0) => pipe_rxstatus(23 downto 0),
      \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0),
      \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(2 downto 0) => \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(2 downto 0),
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => \pipe_stages_1.pipe_tx_rate_q_reg\(0),
      \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\ => \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\,
      \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\ => \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\,
      pipe_sync_fsm_rx(55 downto 0) => pipe_sync_fsm_rx(55 downto 0),
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_txdlysresetdone(7 downto 0) => pipe_txdlysresetdone(7 downto 0),
      pipe_txinhibit(7 downto 0) => pipe_txinhibit(7 downto 0),
      pipe_txoutclk_out => pipe_txoutclk_out,
      pipe_txphaligndone(7 downto 0) => pipe_txphaligndone(7 downto 0),
      pipe_txphinitdone(7 downto 0) => pipe_txphinitdone(7 downto 0),
      \pl_ltssm_state_q_reg[4]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3\,
      reset_n_reg2_reg_0 => reset_n_reg2_reg,
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n_0,
      \sysclksel_reg[1]\(4 downto 0) => \sysclksel_reg[1]_0\(4 downto 0),
      \sysclksel_reg[1]_0\(4 downto 0) => \sysclksel_reg[1]_1\(4 downto 0),
      \sysclksel_reg[1]_1\(4 downto 0) => \sysclksel_reg[1]_2\(4 downto 0),
      \sysclksel_reg[1]_2\(4 downto 0) => \sysclksel_reg[1]_3\(4 downto 0),
      \sysclksel_reg[1]_3\(4 downto 0) => \sysclksel_reg[1]_4\(4 downto 0),
      \sysclksel_reg[1]_4\(4 downto 0) => \sysclksel_reg[1]_5\(4 downto 0),
      \sysclksel_reg[1]_5\(4 downto 0) => \sysclksel_reg[1]_6\(4 downto 0),
      \txsync_fsm.txdlyen_reg\(5 downto 0) => \txsync_fsm.txdlyen_reg\(5 downto 0),
      \txsync_fsm.txdlyen_reg_0\(5 downto 0) => \txsync_fsm.txdlyen_reg_0\(5 downto 0),
      \txsync_fsm.txdlyen_reg_1\(5 downto 0) => \txsync_fsm.txdlyen_reg_1\(5 downto 0),
      \txsync_fsm.txdlyen_reg_2\(5 downto 0) => \txsync_fsm.txdlyen_reg_2\(5 downto 0),
      \txsync_fsm.txdlyen_reg_3\(5 downto 0) => \txsync_fsm.txdlyen_reg_3\(5 downto 0),
      \txsync_fsm.txdlyen_reg_4\(5 downto 0) => \txsync_fsm.txdlyen_reg_4\(5 downto 0),
      \txsync_fsm.txdlyen_reg_5\(5 downto 0) => \txsync_fsm.txdlyen_reg_5\(5 downto 0)
    );
\pl_ltssm_state_q[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^clk_mmcm_lock\,
      O => \pl_ltssm_state_q[5]_i_1_n_0\
    );
\pl_ltssm_state_q_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      CLR => \pl_ltssm_state_q[5]_i_1_n_0\,
      D => pl_ltssm_state(0),
      Q => pl_ltssm_state_q(0)
    );
\pl_ltssm_state_q_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      CLR => \pl_ltssm_state_q[5]_i_1_n_0\,
      D => pl_ltssm_state(1),
      Q => pl_ltssm_state_q(1)
    );
\pl_ltssm_state_q_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      CLR => \pl_ltssm_state_q[5]_i_1_n_0\,
      D => pl_ltssm_state(2),
      Q => pl_ltssm_state_q(2)
    );
\pl_ltssm_state_q_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      CLR => \pl_ltssm_state_q[5]_i_1_n_0\,
      D => pl_ltssm_state(3),
      Q => pl_ltssm_state_q(3)
    );
\pl_ltssm_state_q_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      CLR => \pl_ltssm_state_q[5]_i_1_n_0\,
      D => pl_ltssm_state(4),
      Q => pl_ltssm_state_q(4)
    );
\pl_ltssm_state_q_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      CLR => \pl_ltssm_state_q[5]_i_1_n_0\,
      D => pl_ltssm_state(5),
      Q => pl_ltssm_state_q(5)
    );
reg_clock_locked_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^clk_pclk\,
      CE => '1',
      CLR => \pl_ltssm_state_q[5]_i_1_n_0\,
      D => '1',
      Q => reg_clock_locked
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_top_7x is
  port (
    rdata : out STD_LOGIC_VECTOR ( 68 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    mim_tx_wen : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 68 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_top_7x : entity is "PCIeGen1x8If64_pcie_bram_top_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_top_7x;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_top_7x is
begin
pcie_brams_rx: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x
     port map (
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(67 downto 0) => \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(67 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl\(67 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(67 downto 0),
      user_clk => user_clk
    );
pcie_brams_tx: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x_7
     port map (
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(68 downto 0) => rdata(68 downto 0),
      user_clk => user_clk,
      wdata(68 downto 0) => wdata(68 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_7x is
  port (
    user_reset_int_reg : out STD_LOGIC;
    trn_rsrc_dsc : out STD_LOGIC;
    trn_rsof : out STD_LOGIC;
    tbuf_av_gap_thrtl_reg : out STD_LOGIC;
    trn_tbuf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    tbuf_av_min_trig : out STD_LOGIC;
    tready_thrtl_xhdl1_reg : out STD_LOGIC;
    reg_dsc_detect_reg : out STD_LOGIC;
    trn_reof : out STD_LOGIC;
    tbuf_av_gap_thrtl_reg_0 : out STD_LOGIC;
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_msg_received : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    pl_phy_lnk_up_q_reg : out STD_LOGIC;
    trn_in_packet_reg : out STD_LOGIC;
    rsrc_rdy_filtered10_out : out STD_LOGIC;
    tready_thrtl_xhdl1_reg_0 : out STD_LOGIC;
    ppm_L1_thrtl_reg : out STD_LOGIC;
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_command : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 14 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_lcommand : out STD_LOGIC_VECTOR ( 10 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_msg_received_assert_int_a : out STD_LOGIC;
    cfg_msg_received_assert_int_b : out STD_LOGIC;
    cfg_msg_received_assert_int_c : out STD_LOGIC;
    cfg_msg_received_assert_int_d : out STD_LOGIC;
    cfg_msg_received_deassert_int_a : out STD_LOGIC;
    cfg_msg_received_deassert_int_b : out STD_LOGIC;
    cfg_msg_received_deassert_int_c : out STD_LOGIC;
    cfg_msg_received_deassert_int_d : out STD_LOGIC;
    cfg_msg_received_err_cor : out STD_LOGIC;
    cfg_msg_received_err_fatal : out STD_LOGIC;
    cfg_msg_received_err_non_fatal : out STD_LOGIC;
    cfg_msg_received_pm_as_nak : out STD_LOGIC;
    cfg_to_turnoff : out STD_LOGIC;
    cfg_msg_received_pme_to_ack : out STD_LOGIC;
    cfg_msg_received_pm_pme : out STD_LOGIC;
    cfg_msg_received_setslotpowerlimit : out STD_LOGIC;
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    pcie_drp_rdy : out STD_LOGIC;
    pipe_rx0_polarity : out STD_LOGIC;
    pipe_rx1_polarity : out STD_LOGIC;
    pipe_rx2_polarity : out STD_LOGIC;
    pipe_rx3_polarity : out STD_LOGIC;
    pipe_rx4_polarity : out STD_LOGIC;
    pipe_rx5_polarity : out STD_LOGIC;
    pipe_rx6_polarity : out STD_LOGIC;
    pipe_rx7_polarity : out STD_LOGIC;
    pipe_tx0_compliance : out STD_LOGIC;
    pipe_tx0_elec_idle : out STD_LOGIC;
    pipe_tx1_compliance : out STD_LOGIC;
    pipe_tx1_elec_idle : out STD_LOGIC;
    pipe_tx2_compliance : out STD_LOGIC;
    pipe_tx2_elec_idle : out STD_LOGIC;
    pipe_tx3_compliance : out STD_LOGIC;
    pipe_tx3_elec_idle : out STD_LOGIC;
    pipe_tx4_compliance : out STD_LOGIC;
    pipe_tx4_elec_idle : out STD_LOGIC;
    pipe_tx5_compliance : out STD_LOGIC;
    pipe_tx5_elec_idle : out STD_LOGIC;
    pipe_tx6_compliance : out STD_LOGIC;
    pipe_tx6_elec_idle : out STD_LOGIC;
    pipe_tx7_compliance : out STD_LOGIC;
    pipe_tx7_elec_idle : out STD_LOGIC;
    pipe_tx_deemph : out STD_LOGIC;
    pipe_tx_rate : out STD_LOGIC;
    pipe_tx_rcvr_det : out STD_LOGIC;
    pl_directed_change_done : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    trn_lnk_up : out STD_LOGIC;
    trn_recrc_err : out STD_LOGIC;
    trn_rerrfwd : out STD_LOGIC;
    trn_tcfg_req : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx0_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx1_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx2_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx3_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx4_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx5_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx6_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx7_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx0_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx0_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx2_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx2_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx3_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx3_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx4_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx4_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx5_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx5_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx6_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx6_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx7_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx7_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    trn_rrem : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx_margin : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    trn_tdst_rdy : out STD_LOGIC;
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    trn_rbar_hit : out STD_LOGIC_VECTOR ( 6 downto 0 );
    bridge_reset_int : in STD_LOGIC;
    pl_phy_lnk_up : in STD_LOGIC;
    trn_in_packet_reg_0 : in STD_LOGIC;
    tready_thrtl_xhdl1_reg_1 : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    trn_rdst_rdy : in STD_LOGIC;
    \tbuf_av_d_reg[4]\ : in STD_LOGIC;
    cfg_trn_pending : in STD_LOGIC;
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_wake : in STD_LOGIC;
    user_reset_out_reg : in STD_LOGIC;
    \tcfg_req_cnt_reg[1]\ : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    cfg_pm_turnoff_ok_n : in STD_LOGIC;
    pcie_drp_clk : in STD_LOGIC;
    pcie_drp_en : in STD_LOGIC;
    pcie_drp_we : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_rx0_chanisaligned : in STD_LOGIC;
    pipe_rx0_elec_idle : in STD_LOGIC;
    pipe_rx0_phy_status : in STD_LOGIC;
    pipe_rx0_valid : in STD_LOGIC;
    pipe_rx1_chanisaligned : in STD_LOGIC;
    pipe_rx1_elec_idle : in STD_LOGIC;
    pipe_rx1_phy_status : in STD_LOGIC;
    pipe_rx1_valid : in STD_LOGIC;
    pipe_rx2_chanisaligned : in STD_LOGIC;
    pipe_rx2_elec_idle : in STD_LOGIC;
    pipe_rx2_phy_status : in STD_LOGIC;
    pipe_rx2_valid : in STD_LOGIC;
    pipe_rx3_chanisaligned : in STD_LOGIC;
    pipe_rx3_elec_idle : in STD_LOGIC;
    pipe_rx3_phy_status : in STD_LOGIC;
    pipe_rx3_valid : in STD_LOGIC;
    pipe_rx4_chanisaligned : in STD_LOGIC;
    pipe_rx4_elec_idle : in STD_LOGIC;
    pipe_rx4_phy_status : in STD_LOGIC;
    pipe_rx4_valid : in STD_LOGIC;
    pipe_rx5_chanisaligned : in STD_LOGIC;
    pipe_rx5_elec_idle : in STD_LOGIC;
    pipe_rx5_phy_status : in STD_LOGIC;
    pipe_rx5_valid : in STD_LOGIC;
    pipe_rx6_chanisaligned : in STD_LOGIC;
    pipe_rx6_elec_idle : in STD_LOGIC;
    pipe_rx6_phy_status : in STD_LOGIC;
    pipe_rx6_valid : in STD_LOGIC;
    pipe_rx7_chanisaligned : in STD_LOGIC;
    pipe_rx7_elec_idle : in STD_LOGIC;
    pipe_rx7_phy_status : in STD_LOGIC;
    pipe_rx7_valid : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_directed_link_speed : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    trn_tcfg_gnt : in STD_LOGIC;
    \xhdl12.reg_tuser_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    trn_teof : in STD_LOGIC;
    trn_tsof : in STD_LOGIC;
    trn_tsrc_rdy : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 );
    pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_2\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_3\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_4\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \pipe_stages_1.pipe_rx_data_q_reg[15]_5\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    trn_trem : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_4\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_5\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \pipe_stages_1.pipe_rx_status_q_reg[2]_6\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_7x : entity is "PCIeGen1x8If64_pcie_7x";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_7x;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_7x is
  signal cfg_err_aer_headerlog_set_n : STD_LOGIC;
  signal cfg_err_atomic_egress_blocked_n : STD_LOGIC;
  signal cfg_err_cor_n : STD_LOGIC;
  signal cfg_err_cpl_abort_n : STD_LOGIC;
  signal cfg_err_cpl_rdy_n : STD_LOGIC;
  signal cfg_err_cpl_timeout_n : STD_LOGIC;
  signal cfg_err_cpl_unexpect_n : STD_LOGIC;
  signal cfg_err_ecrc_n : STD_LOGIC;
  signal cfg_err_internal_cor_n : STD_LOGIC;
  signal cfg_err_internal_uncor_n : STD_LOGIC;
  signal cfg_err_locked_n : STD_LOGIC;
  signal cfg_err_malformed_n : STD_LOGIC;
  signal cfg_err_mc_blocked_n : STD_LOGIC;
  signal cfg_err_norecovery_n : STD_LOGIC;
  signal cfg_err_poisoned_n : STD_LOGIC;
  signal cfg_err_posted_n : STD_LOGIC;
  signal cfg_err_ur_n : STD_LOGIC;
  signal cfg_interrupt_assert_n : STD_LOGIC;
  signal cfg_interrupt_n : STD_LOGIC;
  signal cfg_interrupt_rdy_n : STD_LOGIC;
  signal cfg_interrupt_stat_n : STD_LOGIC;
  signal cfg_mgmt_rd_en_n : STD_LOGIC;
  signal cfg_mgmt_rd_wr_done_n : STD_LOGIC;
  signal cfg_mgmt_wr_en_n : STD_LOGIC;
  signal cfg_mgmt_wr_readonly_n : STD_LOGIC;
  signal cfg_mgmt_wr_rw1c_as_rw_n : STD_LOGIC;
  signal \^cfg_msg_received\ : STD_LOGIC;
  signal \^cfg_pcie_link_state\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal cfg_pm_force_state_en_n : STD_LOGIC;
  signal cfg_pm_halt_aspm_l0s_n : STD_LOGIC;
  signal cfg_pm_halt_aspm_l1_n : STD_LOGIC;
  signal cfg_pm_wake_n : STD_LOGIC;
  signal cfg_trn_pending_n : STD_LOGIC;
  signal mim_rx_raddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_rx_ren : STD_LOGIC;
  signal mim_rx_waddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_rx_wdata : STD_LOGIC_VECTOR ( 67 downto 0 );
  signal mim_rx_wen : STD_LOGIC;
  signal mim_tx_raddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_tx_ren : STD_LOGIC;
  signal mim_tx_waddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_tx_wdata : STD_LOGIC_VECTOR ( 68 downto 0 );
  signal mim_tx_wen : STD_LOGIC;
  signal pcie_block_i_n_100 : STD_LOGIC;
  signal pcie_block_i_n_101 : STD_LOGIC;
  signal pcie_block_i_n_102 : STD_LOGIC;
  signal pcie_block_i_n_103 : STD_LOGIC;
  signal pcie_block_i_n_104 : STD_LOGIC;
  signal pcie_block_i_n_105 : STD_LOGIC;
  signal pcie_block_i_n_106 : STD_LOGIC;
  signal pcie_block_i_n_107 : STD_LOGIC;
  signal pcie_block_i_n_108 : STD_LOGIC;
  signal pcie_block_i_n_1097 : STD_LOGIC;
  signal pcie_block_i_n_1098 : STD_LOGIC;
  signal pcie_block_i_n_1099 : STD_LOGIC;
  signal pcie_block_i_n_1100 : STD_LOGIC;
  signal pcie_block_i_n_1101 : STD_LOGIC;
  signal pcie_block_i_n_1102 : STD_LOGIC;
  signal pcie_block_i_n_1103 : STD_LOGIC;
  signal pcie_block_i_n_1143 : STD_LOGIC;
  signal pcie_block_i_n_140 : STD_LOGIC;
  signal pcie_block_i_n_141 : STD_LOGIC;
  signal pcie_block_i_n_142 : STD_LOGIC;
  signal pcie_block_i_n_143 : STD_LOGIC;
  signal pcie_block_i_n_144 : STD_LOGIC;
  signal pcie_block_i_n_145 : STD_LOGIC;
  signal pcie_block_i_n_146 : STD_LOGIC;
  signal pcie_block_i_n_155 : STD_LOGIC;
  signal pcie_block_i_n_156 : STD_LOGIC;
  signal pcie_block_i_n_157 : STD_LOGIC;
  signal pcie_block_i_n_158 : STD_LOGIC;
  signal pcie_block_i_n_159 : STD_LOGIC;
  signal pcie_block_i_n_160 : STD_LOGIC;
  signal pcie_block_i_n_169 : STD_LOGIC;
  signal pcie_block_i_n_172 : STD_LOGIC;
  signal pcie_block_i_n_173 : STD_LOGIC;
  signal pcie_block_i_n_174 : STD_LOGIC;
  signal pcie_block_i_n_175 : STD_LOGIC;
  signal pcie_block_i_n_176 : STD_LOGIC;
  signal pcie_block_i_n_177 : STD_LOGIC;
  signal pcie_block_i_n_178 : STD_LOGIC;
  signal pcie_block_i_n_179 : STD_LOGIC;
  signal pcie_block_i_n_180 : STD_LOGIC;
  signal pcie_block_i_n_181 : STD_LOGIC;
  signal pcie_block_i_n_182 : STD_LOGIC;
  signal pcie_block_i_n_183 : STD_LOGIC;
  signal pcie_block_i_n_184 : STD_LOGIC;
  signal pcie_block_i_n_185 : STD_LOGIC;
  signal pcie_block_i_n_186 : STD_LOGIC;
  signal pcie_block_i_n_187 : STD_LOGIC;
  signal pcie_block_i_n_188 : STD_LOGIC;
  signal pcie_block_i_n_189 : STD_LOGIC;
  signal pcie_block_i_n_190 : STD_LOGIC;
  signal pcie_block_i_n_191 : STD_LOGIC;
  signal pcie_block_i_n_192 : STD_LOGIC;
  signal pcie_block_i_n_193 : STD_LOGIC;
  signal pcie_block_i_n_194 : STD_LOGIC;
  signal pcie_block_i_n_195 : STD_LOGIC;
  signal pcie_block_i_n_610 : STD_LOGIC;
  signal pcie_block_i_n_611 : STD_LOGIC;
  signal pcie_block_i_n_618 : STD_LOGIC;
  signal pcie_block_i_n_619 : STD_LOGIC;
  signal pcie_block_i_n_687 : STD_LOGIC;
  signal pcie_block_i_n_688 : STD_LOGIC;
  signal pcie_block_i_n_689 : STD_LOGIC;
  signal pcie_block_i_n_690 : STD_LOGIC;
  signal pcie_block_i_n_691 : STD_LOGIC;
  signal pcie_block_i_n_704 : STD_LOGIC;
  signal pcie_block_i_n_705 : STD_LOGIC;
  signal pcie_block_i_n_706 : STD_LOGIC;
  signal pcie_block_i_n_707 : STD_LOGIC;
  signal pcie_block_i_n_708 : STD_LOGIC;
  signal pcie_block_i_n_709 : STD_LOGIC;
  signal pcie_block_i_n_710 : STD_LOGIC;
  signal pcie_block_i_n_711 : STD_LOGIC;
  signal pcie_block_i_n_712 : STD_LOGIC;
  signal pcie_block_i_n_713 : STD_LOGIC;
  signal pcie_block_i_n_714 : STD_LOGIC;
  signal pcie_block_i_n_715 : STD_LOGIC;
  signal pcie_block_i_n_716 : STD_LOGIC;
  signal pcie_block_i_n_717 : STD_LOGIC;
  signal pcie_block_i_n_718 : STD_LOGIC;
  signal pcie_block_i_n_719 : STD_LOGIC;
  signal pcie_block_i_n_72 : STD_LOGIC;
  signal pcie_block_i_n_720 : STD_LOGIC;
  signal pcie_block_i_n_721 : STD_LOGIC;
  signal pcie_block_i_n_722 : STD_LOGIC;
  signal pcie_block_i_n_723 : STD_LOGIC;
  signal pcie_block_i_n_724 : STD_LOGIC;
  signal pcie_block_i_n_725 : STD_LOGIC;
  signal pcie_block_i_n_726 : STD_LOGIC;
  signal pcie_block_i_n_727 : STD_LOGIC;
  signal pcie_block_i_n_728 : STD_LOGIC;
  signal pcie_block_i_n_729 : STD_LOGIC;
  signal pcie_block_i_n_730 : STD_LOGIC;
  signal pcie_block_i_n_731 : STD_LOGIC;
  signal pcie_block_i_n_732 : STD_LOGIC;
  signal pcie_block_i_n_733 : STD_LOGIC;
  signal pcie_block_i_n_734 : STD_LOGIC;
  signal pcie_block_i_n_735 : STD_LOGIC;
  signal pcie_block_i_n_736 : STD_LOGIC;
  signal pcie_block_i_n_737 : STD_LOGIC;
  signal pcie_block_i_n_738 : STD_LOGIC;
  signal pcie_block_i_n_739 : STD_LOGIC;
  signal pcie_block_i_n_740 : STD_LOGIC;
  signal pcie_block_i_n_741 : STD_LOGIC;
  signal pcie_block_i_n_742 : STD_LOGIC;
  signal pcie_block_i_n_743 : STD_LOGIC;
  signal pcie_block_i_n_744 : STD_LOGIC;
  signal pcie_block_i_n_745 : STD_LOGIC;
  signal pcie_block_i_n_746 : STD_LOGIC;
  signal pcie_block_i_n_747 : STD_LOGIC;
  signal pcie_block_i_n_748 : STD_LOGIC;
  signal pcie_block_i_n_749 : STD_LOGIC;
  signal pcie_block_i_n_75 : STD_LOGIC;
  signal pcie_block_i_n_750 : STD_LOGIC;
  signal pcie_block_i_n_751 : STD_LOGIC;
  signal pcie_block_i_n_752 : STD_LOGIC;
  signal pcie_block_i_n_753 : STD_LOGIC;
  signal pcie_block_i_n_754 : STD_LOGIC;
  signal pcie_block_i_n_755 : STD_LOGIC;
  signal pcie_block_i_n_756 : STD_LOGIC;
  signal pcie_block_i_n_757 : STD_LOGIC;
  signal pcie_block_i_n_758 : STD_LOGIC;
  signal pcie_block_i_n_759 : STD_LOGIC;
  signal pcie_block_i_n_76 : STD_LOGIC;
  signal pcie_block_i_n_760 : STD_LOGIC;
  signal pcie_block_i_n_761 : STD_LOGIC;
  signal pcie_block_i_n_762 : STD_LOGIC;
  signal pcie_block_i_n_763 : STD_LOGIC;
  signal pcie_block_i_n_764 : STD_LOGIC;
  signal pcie_block_i_n_765 : STD_LOGIC;
  signal pcie_block_i_n_766 : STD_LOGIC;
  signal pcie_block_i_n_767 : STD_LOGIC;
  signal pcie_block_i_n_768 : STD_LOGIC;
  signal pcie_block_i_n_769 : STD_LOGIC;
  signal pcie_block_i_n_77 : STD_LOGIC;
  signal pcie_block_i_n_770 : STD_LOGIC;
  signal pcie_block_i_n_771 : STD_LOGIC;
  signal pcie_block_i_n_772 : STD_LOGIC;
  signal pcie_block_i_n_773 : STD_LOGIC;
  signal pcie_block_i_n_774 : STD_LOGIC;
  signal pcie_block_i_n_775 : STD_LOGIC;
  signal pcie_block_i_n_776 : STD_LOGIC;
  signal pcie_block_i_n_777 : STD_LOGIC;
  signal pcie_block_i_n_778 : STD_LOGIC;
  signal pcie_block_i_n_779 : STD_LOGIC;
  signal pcie_block_i_n_78 : STD_LOGIC;
  signal pcie_block_i_n_780 : STD_LOGIC;
  signal pcie_block_i_n_781 : STD_LOGIC;
  signal pcie_block_i_n_782 : STD_LOGIC;
  signal pcie_block_i_n_783 : STD_LOGIC;
  signal pcie_block_i_n_784 : STD_LOGIC;
  signal pcie_block_i_n_785 : STD_LOGIC;
  signal pcie_block_i_n_786 : STD_LOGIC;
  signal pcie_block_i_n_787 : STD_LOGIC;
  signal pcie_block_i_n_788 : STD_LOGIC;
  signal pcie_block_i_n_789 : STD_LOGIC;
  signal pcie_block_i_n_790 : STD_LOGIC;
  signal pcie_block_i_n_791 : STD_LOGIC;
  signal pcie_block_i_n_792 : STD_LOGIC;
  signal pcie_block_i_n_793 : STD_LOGIC;
  signal pcie_block_i_n_794 : STD_LOGIC;
  signal pcie_block_i_n_795 : STD_LOGIC;
  signal pcie_block_i_n_796 : STD_LOGIC;
  signal pcie_block_i_n_797 : STD_LOGIC;
  signal pcie_block_i_n_798 : STD_LOGIC;
  signal pcie_block_i_n_799 : STD_LOGIC;
  signal pcie_block_i_n_800 : STD_LOGIC;
  signal pcie_block_i_n_801 : STD_LOGIC;
  signal pcie_block_i_n_802 : STD_LOGIC;
  signal pcie_block_i_n_803 : STD_LOGIC;
  signal pcie_block_i_n_804 : STD_LOGIC;
  signal pcie_block_i_n_805 : STD_LOGIC;
  signal pcie_block_i_n_806 : STD_LOGIC;
  signal pcie_block_i_n_807 : STD_LOGIC;
  signal pcie_block_i_n_808 : STD_LOGIC;
  signal pcie_block_i_n_809 : STD_LOGIC;
  signal pcie_block_i_n_810 : STD_LOGIC;
  signal pcie_block_i_n_811 : STD_LOGIC;
  signal pcie_block_i_n_812 : STD_LOGIC;
  signal pcie_block_i_n_813 : STD_LOGIC;
  signal pcie_block_i_n_814 : STD_LOGIC;
  signal pcie_block_i_n_815 : STD_LOGIC;
  signal pcie_block_i_n_816 : STD_LOGIC;
  signal pcie_block_i_n_817 : STD_LOGIC;
  signal pcie_block_i_n_818 : STD_LOGIC;
  signal pcie_block_i_n_819 : STD_LOGIC;
  signal pcie_block_i_n_820 : STD_LOGIC;
  signal pcie_block_i_n_821 : STD_LOGIC;
  signal pcie_block_i_n_822 : STD_LOGIC;
  signal pcie_block_i_n_823 : STD_LOGIC;
  signal pcie_block_i_n_824 : STD_LOGIC;
  signal pcie_block_i_n_825 : STD_LOGIC;
  signal pcie_block_i_n_826 : STD_LOGIC;
  signal pcie_block_i_n_827 : STD_LOGIC;
  signal pcie_block_i_n_828 : STD_LOGIC;
  signal pcie_block_i_n_829 : STD_LOGIC;
  signal pcie_block_i_n_830 : STD_LOGIC;
  signal pcie_block_i_n_831 : STD_LOGIC;
  signal pcie_block_i_n_832 : STD_LOGIC;
  signal pcie_block_i_n_833 : STD_LOGIC;
  signal pcie_block_i_n_834 : STD_LOGIC;
  signal pcie_block_i_n_835 : STD_LOGIC;
  signal pcie_block_i_n_836 : STD_LOGIC;
  signal pcie_block_i_n_837 : STD_LOGIC;
  signal pcie_block_i_n_838 : STD_LOGIC;
  signal pcie_block_i_n_839 : STD_LOGIC;
  signal pcie_block_i_n_84 : STD_LOGIC;
  signal pcie_block_i_n_840 : STD_LOGIC;
  signal pcie_block_i_n_841 : STD_LOGIC;
  signal pcie_block_i_n_842 : STD_LOGIC;
  signal pcie_block_i_n_843 : STD_LOGIC;
  signal pcie_block_i_n_844 : STD_LOGIC;
  signal pcie_block_i_n_845 : STD_LOGIC;
  signal pcie_block_i_n_846 : STD_LOGIC;
  signal pcie_block_i_n_847 : STD_LOGIC;
  signal pcie_block_i_n_848 : STD_LOGIC;
  signal pcie_block_i_n_849 : STD_LOGIC;
  signal pcie_block_i_n_85 : STD_LOGIC;
  signal pcie_block_i_n_850 : STD_LOGIC;
  signal pcie_block_i_n_851 : STD_LOGIC;
  signal pcie_block_i_n_852 : STD_LOGIC;
  signal pcie_block_i_n_853 : STD_LOGIC;
  signal pcie_block_i_n_854 : STD_LOGIC;
  signal pcie_block_i_n_855 : STD_LOGIC;
  signal pcie_block_i_n_856 : STD_LOGIC;
  signal pcie_block_i_n_857 : STD_LOGIC;
  signal pcie_block_i_n_858 : STD_LOGIC;
  signal pcie_block_i_n_859 : STD_LOGIC;
  signal pcie_block_i_n_86 : STD_LOGIC;
  signal pcie_block_i_n_860 : STD_LOGIC;
  signal pcie_block_i_n_861 : STD_LOGIC;
  signal pcie_block_i_n_862 : STD_LOGIC;
  signal pcie_block_i_n_863 : STD_LOGIC;
  signal pcie_block_i_n_864 : STD_LOGIC;
  signal pcie_block_i_n_865 : STD_LOGIC;
  signal pcie_block_i_n_866 : STD_LOGIC;
  signal pcie_block_i_n_867 : STD_LOGIC;
  signal pcie_block_i_n_868 : STD_LOGIC;
  signal pcie_block_i_n_869 : STD_LOGIC;
  signal pcie_block_i_n_87 : STD_LOGIC;
  signal pcie_block_i_n_870 : STD_LOGIC;
  signal pcie_block_i_n_871 : STD_LOGIC;
  signal pcie_block_i_n_872 : STD_LOGIC;
  signal pcie_block_i_n_873 : STD_LOGIC;
  signal pcie_block_i_n_874 : STD_LOGIC;
  signal pcie_block_i_n_875 : STD_LOGIC;
  signal pcie_block_i_n_876 : STD_LOGIC;
  signal pcie_block_i_n_877 : STD_LOGIC;
  signal pcie_block_i_n_878 : STD_LOGIC;
  signal pcie_block_i_n_879 : STD_LOGIC;
  signal pcie_block_i_n_88 : STD_LOGIC;
  signal pcie_block_i_n_880 : STD_LOGIC;
  signal pcie_block_i_n_881 : STD_LOGIC;
  signal pcie_block_i_n_882 : STD_LOGIC;
  signal pcie_block_i_n_883 : STD_LOGIC;
  signal pcie_block_i_n_884 : STD_LOGIC;
  signal pcie_block_i_n_885 : STD_LOGIC;
  signal pcie_block_i_n_886 : STD_LOGIC;
  signal pcie_block_i_n_887 : STD_LOGIC;
  signal pcie_block_i_n_888 : STD_LOGIC;
  signal pcie_block_i_n_889 : STD_LOGIC;
  signal pcie_block_i_n_89 : STD_LOGIC;
  signal pcie_block_i_n_890 : STD_LOGIC;
  signal pcie_block_i_n_891 : STD_LOGIC;
  signal pcie_block_i_n_892 : STD_LOGIC;
  signal pcie_block_i_n_893 : STD_LOGIC;
  signal pcie_block_i_n_894 : STD_LOGIC;
  signal pcie_block_i_n_895 : STD_LOGIC;
  signal pcie_block_i_n_896 : STD_LOGIC;
  signal pcie_block_i_n_897 : STD_LOGIC;
  signal pcie_block_i_n_898 : STD_LOGIC;
  signal pcie_block_i_n_899 : STD_LOGIC;
  signal pcie_block_i_n_90 : STD_LOGIC;
  signal pcie_block_i_n_900 : STD_LOGIC;
  signal pcie_block_i_n_901 : STD_LOGIC;
  signal pcie_block_i_n_902 : STD_LOGIC;
  signal pcie_block_i_n_903 : STD_LOGIC;
  signal pcie_block_i_n_904 : STD_LOGIC;
  signal pcie_block_i_n_905 : STD_LOGIC;
  signal pcie_block_i_n_906 : STD_LOGIC;
  signal pcie_block_i_n_907 : STD_LOGIC;
  signal pcie_block_i_n_908 : STD_LOGIC;
  signal pcie_block_i_n_909 : STD_LOGIC;
  signal pcie_block_i_n_91 : STD_LOGIC;
  signal pcie_block_i_n_910 : STD_LOGIC;
  signal pcie_block_i_n_911 : STD_LOGIC;
  signal pcie_block_i_n_912 : STD_LOGIC;
  signal pcie_block_i_n_913 : STD_LOGIC;
  signal pcie_block_i_n_914 : STD_LOGIC;
  signal pcie_block_i_n_915 : STD_LOGIC;
  signal pcie_block_i_n_916 : STD_LOGIC;
  signal pcie_block_i_n_917 : STD_LOGIC;
  signal pcie_block_i_n_918 : STD_LOGIC;
  signal pcie_block_i_n_919 : STD_LOGIC;
  signal pcie_block_i_n_92 : STD_LOGIC;
  signal pcie_block_i_n_920 : STD_LOGIC;
  signal pcie_block_i_n_921 : STD_LOGIC;
  signal pcie_block_i_n_922 : STD_LOGIC;
  signal pcie_block_i_n_923 : STD_LOGIC;
  signal pcie_block_i_n_924 : STD_LOGIC;
  signal pcie_block_i_n_925 : STD_LOGIC;
  signal pcie_block_i_n_926 : STD_LOGIC;
  signal pcie_block_i_n_927 : STD_LOGIC;
  signal pcie_block_i_n_928 : STD_LOGIC;
  signal pcie_block_i_n_929 : STD_LOGIC;
  signal pcie_block_i_n_93 : STD_LOGIC;
  signal pcie_block_i_n_930 : STD_LOGIC;
  signal pcie_block_i_n_931 : STD_LOGIC;
  signal pcie_block_i_n_932 : STD_LOGIC;
  signal pcie_block_i_n_933 : STD_LOGIC;
  signal pcie_block_i_n_934 : STD_LOGIC;
  signal pcie_block_i_n_935 : STD_LOGIC;
  signal pcie_block_i_n_936 : STD_LOGIC;
  signal pcie_block_i_n_937 : STD_LOGIC;
  signal pcie_block_i_n_938 : STD_LOGIC;
  signal pcie_block_i_n_939 : STD_LOGIC;
  signal pcie_block_i_n_94 : STD_LOGIC;
  signal pcie_block_i_n_940 : STD_LOGIC;
  signal pcie_block_i_n_941 : STD_LOGIC;
  signal pcie_block_i_n_942 : STD_LOGIC;
  signal pcie_block_i_n_943 : STD_LOGIC;
  signal pcie_block_i_n_944 : STD_LOGIC;
  signal pcie_block_i_n_945 : STD_LOGIC;
  signal pcie_block_i_n_946 : STD_LOGIC;
  signal pcie_block_i_n_947 : STD_LOGIC;
  signal pcie_block_i_n_948 : STD_LOGIC;
  signal pcie_block_i_n_949 : STD_LOGIC;
  signal pcie_block_i_n_95 : STD_LOGIC;
  signal pcie_block_i_n_950 : STD_LOGIC;
  signal pcie_block_i_n_951 : STD_LOGIC;
  signal pcie_block_i_n_952 : STD_LOGIC;
  signal pcie_block_i_n_953 : STD_LOGIC;
  signal pcie_block_i_n_954 : STD_LOGIC;
  signal pcie_block_i_n_955 : STD_LOGIC;
  signal pcie_block_i_n_956 : STD_LOGIC;
  signal pcie_block_i_n_957 : STD_LOGIC;
  signal pcie_block_i_n_958 : STD_LOGIC;
  signal pcie_block_i_n_959 : STD_LOGIC;
  signal pcie_block_i_n_96 : STD_LOGIC;
  signal pcie_block_i_n_98 : STD_LOGIC;
  signal pcie_block_i_n_99 : STD_LOGIC;
  signal pcie_bram_top_n_0 : STD_LOGIC;
  signal pcie_bram_top_n_1 : STD_LOGIC;
  signal pcie_bram_top_n_10 : STD_LOGIC;
  signal pcie_bram_top_n_100 : STD_LOGIC;
  signal pcie_bram_top_n_101 : STD_LOGIC;
  signal pcie_bram_top_n_102 : STD_LOGIC;
  signal pcie_bram_top_n_103 : STD_LOGIC;
  signal pcie_bram_top_n_104 : STD_LOGIC;
  signal pcie_bram_top_n_105 : STD_LOGIC;
  signal pcie_bram_top_n_106 : STD_LOGIC;
  signal pcie_bram_top_n_107 : STD_LOGIC;
  signal pcie_bram_top_n_108 : STD_LOGIC;
  signal pcie_bram_top_n_109 : STD_LOGIC;
  signal pcie_bram_top_n_11 : STD_LOGIC;
  signal pcie_bram_top_n_110 : STD_LOGIC;
  signal pcie_bram_top_n_111 : STD_LOGIC;
  signal pcie_bram_top_n_112 : STD_LOGIC;
  signal pcie_bram_top_n_113 : STD_LOGIC;
  signal pcie_bram_top_n_114 : STD_LOGIC;
  signal pcie_bram_top_n_115 : STD_LOGIC;
  signal pcie_bram_top_n_116 : STD_LOGIC;
  signal pcie_bram_top_n_117 : STD_LOGIC;
  signal pcie_bram_top_n_118 : STD_LOGIC;
  signal pcie_bram_top_n_119 : STD_LOGIC;
  signal pcie_bram_top_n_12 : STD_LOGIC;
  signal pcie_bram_top_n_120 : STD_LOGIC;
  signal pcie_bram_top_n_121 : STD_LOGIC;
  signal pcie_bram_top_n_122 : STD_LOGIC;
  signal pcie_bram_top_n_123 : STD_LOGIC;
  signal pcie_bram_top_n_124 : STD_LOGIC;
  signal pcie_bram_top_n_125 : STD_LOGIC;
  signal pcie_bram_top_n_126 : STD_LOGIC;
  signal pcie_bram_top_n_127 : STD_LOGIC;
  signal pcie_bram_top_n_128 : STD_LOGIC;
  signal pcie_bram_top_n_129 : STD_LOGIC;
  signal pcie_bram_top_n_13 : STD_LOGIC;
  signal pcie_bram_top_n_130 : STD_LOGIC;
  signal pcie_bram_top_n_131 : STD_LOGIC;
  signal pcie_bram_top_n_132 : STD_LOGIC;
  signal pcie_bram_top_n_133 : STD_LOGIC;
  signal pcie_bram_top_n_134 : STD_LOGIC;
  signal pcie_bram_top_n_135 : STD_LOGIC;
  signal pcie_bram_top_n_136 : STD_LOGIC;
  signal pcie_bram_top_n_14 : STD_LOGIC;
  signal pcie_bram_top_n_15 : STD_LOGIC;
  signal pcie_bram_top_n_16 : STD_LOGIC;
  signal pcie_bram_top_n_17 : STD_LOGIC;
  signal pcie_bram_top_n_18 : STD_LOGIC;
  signal pcie_bram_top_n_19 : STD_LOGIC;
  signal pcie_bram_top_n_2 : STD_LOGIC;
  signal pcie_bram_top_n_20 : STD_LOGIC;
  signal pcie_bram_top_n_21 : STD_LOGIC;
  signal pcie_bram_top_n_22 : STD_LOGIC;
  signal pcie_bram_top_n_23 : STD_LOGIC;
  signal pcie_bram_top_n_24 : STD_LOGIC;
  signal pcie_bram_top_n_25 : STD_LOGIC;
  signal pcie_bram_top_n_26 : STD_LOGIC;
  signal pcie_bram_top_n_27 : STD_LOGIC;
  signal pcie_bram_top_n_28 : STD_LOGIC;
  signal pcie_bram_top_n_29 : STD_LOGIC;
  signal pcie_bram_top_n_3 : STD_LOGIC;
  signal pcie_bram_top_n_30 : STD_LOGIC;
  signal pcie_bram_top_n_31 : STD_LOGIC;
  signal pcie_bram_top_n_32 : STD_LOGIC;
  signal pcie_bram_top_n_33 : STD_LOGIC;
  signal pcie_bram_top_n_34 : STD_LOGIC;
  signal pcie_bram_top_n_35 : STD_LOGIC;
  signal pcie_bram_top_n_36 : STD_LOGIC;
  signal pcie_bram_top_n_37 : STD_LOGIC;
  signal pcie_bram_top_n_38 : STD_LOGIC;
  signal pcie_bram_top_n_39 : STD_LOGIC;
  signal pcie_bram_top_n_4 : STD_LOGIC;
  signal pcie_bram_top_n_40 : STD_LOGIC;
  signal pcie_bram_top_n_41 : STD_LOGIC;
  signal pcie_bram_top_n_42 : STD_LOGIC;
  signal pcie_bram_top_n_43 : STD_LOGIC;
  signal pcie_bram_top_n_44 : STD_LOGIC;
  signal pcie_bram_top_n_45 : STD_LOGIC;
  signal pcie_bram_top_n_46 : STD_LOGIC;
  signal pcie_bram_top_n_47 : STD_LOGIC;
  signal pcie_bram_top_n_48 : STD_LOGIC;
  signal pcie_bram_top_n_49 : STD_LOGIC;
  signal pcie_bram_top_n_5 : STD_LOGIC;
  signal pcie_bram_top_n_50 : STD_LOGIC;
  signal pcie_bram_top_n_51 : STD_LOGIC;
  signal pcie_bram_top_n_52 : STD_LOGIC;
  signal pcie_bram_top_n_53 : STD_LOGIC;
  signal pcie_bram_top_n_54 : STD_LOGIC;
  signal pcie_bram_top_n_55 : STD_LOGIC;
  signal pcie_bram_top_n_56 : STD_LOGIC;
  signal pcie_bram_top_n_57 : STD_LOGIC;
  signal pcie_bram_top_n_58 : STD_LOGIC;
  signal pcie_bram_top_n_59 : STD_LOGIC;
  signal pcie_bram_top_n_6 : STD_LOGIC;
  signal pcie_bram_top_n_60 : STD_LOGIC;
  signal pcie_bram_top_n_61 : STD_LOGIC;
  signal pcie_bram_top_n_62 : STD_LOGIC;
  signal pcie_bram_top_n_63 : STD_LOGIC;
  signal pcie_bram_top_n_64 : STD_LOGIC;
  signal pcie_bram_top_n_65 : STD_LOGIC;
  signal pcie_bram_top_n_66 : STD_LOGIC;
  signal pcie_bram_top_n_67 : STD_LOGIC;
  signal pcie_bram_top_n_68 : STD_LOGIC;
  signal pcie_bram_top_n_69 : STD_LOGIC;
  signal pcie_bram_top_n_7 : STD_LOGIC;
  signal pcie_bram_top_n_70 : STD_LOGIC;
  signal pcie_bram_top_n_71 : STD_LOGIC;
  signal pcie_bram_top_n_72 : STD_LOGIC;
  signal pcie_bram_top_n_73 : STD_LOGIC;
  signal pcie_bram_top_n_74 : STD_LOGIC;
  signal pcie_bram_top_n_75 : STD_LOGIC;
  signal pcie_bram_top_n_76 : STD_LOGIC;
  signal pcie_bram_top_n_77 : STD_LOGIC;
  signal pcie_bram_top_n_78 : STD_LOGIC;
  signal pcie_bram_top_n_79 : STD_LOGIC;
  signal pcie_bram_top_n_8 : STD_LOGIC;
  signal pcie_bram_top_n_80 : STD_LOGIC;
  signal pcie_bram_top_n_81 : STD_LOGIC;
  signal pcie_bram_top_n_82 : STD_LOGIC;
  signal pcie_bram_top_n_83 : STD_LOGIC;
  signal pcie_bram_top_n_84 : STD_LOGIC;
  signal pcie_bram_top_n_85 : STD_LOGIC;
  signal pcie_bram_top_n_86 : STD_LOGIC;
  signal pcie_bram_top_n_87 : STD_LOGIC;
  signal pcie_bram_top_n_88 : STD_LOGIC;
  signal pcie_bram_top_n_89 : STD_LOGIC;
  signal pcie_bram_top_n_9 : STD_LOGIC;
  signal pcie_bram_top_n_90 : STD_LOGIC;
  signal pcie_bram_top_n_91 : STD_LOGIC;
  signal pcie_bram_top_n_92 : STD_LOGIC;
  signal pcie_bram_top_n_93 : STD_LOGIC;
  signal pcie_bram_top_n_94 : STD_LOGIC;
  signal pcie_bram_top_n_95 : STD_LOGIC;
  signal pcie_bram_top_n_96 : STD_LOGIC;
  signal pcie_bram_top_n_97 : STD_LOGIC;
  signal pcie_bram_top_n_98 : STD_LOGIC;
  signal pcie_bram_top_n_99 : STD_LOGIC;
  signal pl_phy_lnk_up_n : STD_LOGIC;
  signal received_func_lvl_rst_n : STD_LOGIC;
  signal tbuf_av_gap_thrtl_i_6_n_0 : STD_LOGIC;
  signal tbuf_av_gap_thrtl_i_8_n_0 : STD_LOGIC;
  signal \^tbuf_av_gap_thrtl_reg\ : STD_LOGIC;
  signal \^tbuf_av_gap_thrtl_reg_0\ : STD_LOGIC;
  signal trn_in_packet_i_2_n_0 : STD_LOGIC;
  signal \trn_in_packet_i_3__0_n_0\ : STD_LOGIC;
  signal trn_in_packet_i_4_n_0 : STD_LOGIC;
  signal \^trn_reof\ : STD_LOGIC;
  signal \^trn_rsof\ : STD_LOGIC;
  signal \^trn_rsrc_dsc\ : STD_LOGIC;
  signal trn_rsrc_rdy : STD_LOGIC;
  signal \^trn_tbuf_av\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal user_rst_n : STD_LOGIC;
  signal NLW_pcie_block_i_TRNRD_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 64 );
  signal NLW_pcie_block_i_TRNRREM_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute box_type : string;
  attribute box_type of pcie_block_i : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of reg_dsc_detect_i_2 : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of tbuf_av_min_thrtl_i_1 : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of tready_thrtl_xhdl1_i_8 : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of trn_in_packet_i_2 : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of \trn_in_packet_i_3__0\ : label is "soft_lutpair230";
  attribute SOFT_HLUTNM of trn_rsrc_rdy_prev_i_1 : label is "soft_lutpair230";
begin
  cfg_msg_received <= \^cfg_msg_received\;
  cfg_pcie_link_state(2 downto 0) <= \^cfg_pcie_link_state\(2 downto 0);
  tbuf_av_gap_thrtl_reg <= \^tbuf_av_gap_thrtl_reg\;
  tbuf_av_gap_thrtl_reg_0 <= \^tbuf_av_gap_thrtl_reg_0\;
  trn_reof <= \^trn_reof\;
  trn_rsof <= \^trn_rsof\;
  trn_rsrc_dsc <= \^trn_rsrc_dsc\;
  trn_tbuf_av(5 downto 0) <= \^trn_tbuf_av\(5 downto 0);
\cfg_bus_number_d[7]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cfg_msg_received\,
      O => E(0)
    );
cfg_err_aer_headerlog_set_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_aer_headerlog_set_n,
      O => cfg_err_aer_headerlog_set
    );
cfg_err_cpl_rdy_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_cpl_rdy_n,
      O => cfg_err_cpl_rdy
    );
cfg_interrupt_rdy_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt_rdy_n,
      O => cfg_interrupt_rdy
    );
cfg_mgmt_rd_wr_done_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_rd_wr_done_n,
      O => cfg_mgmt_rd_wr_done
    );
cfg_received_func_lvl_rst_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => received_func_lvl_rst_n,
      O => cfg_received_func_lvl_rst
    );
pcie_block_i: unisim.vcomponents.PCIE_2_1
    generic map(
      AER_BASE_PTR => X"000",
      AER_CAP_ECRC_CHECK_CAPABLE => "FALSE",
      AER_CAP_ECRC_GEN_CAPABLE => "FALSE",
      AER_CAP_ID => X"0001",
      AER_CAP_MULTIHEADER => "FALSE",
      AER_CAP_NEXTPTR => X"000",
      AER_CAP_ON => "FALSE",
      AER_CAP_OPTIONAL_ERR_SUPPORT => X"000000",
      AER_CAP_PERMIT_ROOTERR_UPDATE => "FALSE",
      AER_CAP_VERSION => X"1",
      ALLOW_X8_GEN2 => "FALSE",
      BAR0 => X"FFFFFC00",
      BAR1 => X"00000000",
      BAR2 => X"00000000",
      BAR3 => X"00000000",
      BAR4 => X"00000000",
      BAR5 => X"00000000",
      CAPABILITIES_PTR => X"40",
      CARDBUS_CIS_POINTER => X"00000000",
      CFG_ECRC_ERR_CPLSTAT => 0,
      CLASS_CODE => X"058000",
      CMD_INTX_IMPLEMENTED => "FALSE",
      CPL_TIMEOUT_DISABLE_SUPPORTED => "FALSE",
      CPL_TIMEOUT_RANGES_SUPPORTED => X"2",
      CRM_MODULE_RSTS => X"00",
      DEV_CAP2_ARI_FORWARDING_SUPPORTED => "FALSE",
      DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED => "FALSE",
      DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED => "FALSE",
      DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED => "FALSE",
      DEV_CAP2_CAS128_COMPLETER_SUPPORTED => "FALSE",
      DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED => "FALSE",
      DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED => "FALSE",
      DEV_CAP2_LTR_MECHANISM_SUPPORTED => "FALSE",
      DEV_CAP2_MAX_ENDEND_TLP_PREFIXES => X"0",
      DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING => "FALSE",
      DEV_CAP2_TPH_COMPLETER_SUPPORTED => X"0",
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => "TRUE",
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => "TRUE",
      DEV_CAP_ENDPOINT_L0S_LATENCY => 0,
      DEV_CAP_ENDPOINT_L1_LATENCY => 7,
      DEV_CAP_EXT_TAG_SUPPORTED => "TRUE",
      DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => "FALSE",
      DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
      DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => 0,
      DEV_CAP_ROLE_BASED_ERROR => "TRUE",
      DEV_CAP_RSVD_14_12 => 0,
      DEV_CAP_RSVD_17_16 => 0,
      DEV_CAP_RSVD_31_29 => 0,
      DEV_CONTROL_AUX_POWER_SUPPORTED => "FALSE",
      DEV_CONTROL_EXT_TAG_DEFAULT => "FALSE",
      DISABLE_ASPM_L1_TIMER => "FALSE",
      DISABLE_BAR_FILTERING => "FALSE",
      DISABLE_ERR_MSG => "FALSE",
      DISABLE_ID_CHECK => "FALSE",
      DISABLE_LANE_REVERSAL => "TRUE",
      DISABLE_LOCKED_FILTER => "FALSE",
      DISABLE_PPM_FILTER => "FALSE",
      DISABLE_RX_POISONED_RESP => "FALSE",
      DISABLE_RX_TC_FILTER => "FALSE",
      DISABLE_SCRAMBLING => "FALSE",
      DNSTREAM_LINK_NUM => X"00",
      DSN_BASE_PTR => X"100",
      DSN_CAP_ID => X"0003",
      DSN_CAP_NEXTPTR => X"000",
      DSN_CAP_ON => "TRUE",
      DSN_CAP_VERSION => X"1",
      ENABLE_MSG_ROUTE => X"000",
      ENABLE_RX_TD_ECRC_TRIM => "FALSE",
      ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED => "FALSE",
      ENTER_RVRY_EI_L0 => "TRUE",
      EXIT_LOOPBACK_ON_EI => "TRUE",
      EXPANSION_ROM => X"00000000",
      EXT_CFG_CAP_PTR => X"3F",
      EXT_CFG_XP_CAP_PTR => X"3FF",
      HEADER_TYPE => X"00",
      INFER_EI => X"00",
      INTERRUPT_PIN => X"00",
      INTERRUPT_STAT_AUTO => "TRUE",
      IS_SWITCH => "FALSE",
      LAST_CONFIG_DWORD => X"3FF",
      LINK_CAP_ASPM_OPTIONALITY => "FALSE",
      LINK_CAP_ASPM_SUPPORT => 1,
      LINK_CAP_CLOCK_POWER_MANAGEMENT => "FALSE",
      LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => "FALSE",
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => 7,
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => 7,
      LINK_CAP_L0S_EXIT_LATENCY_GEN1 => 7,
      LINK_CAP_L0S_EXIT_LATENCY_GEN2 => 7,
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => 7,
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => 7,
      LINK_CAP_L1_EXIT_LATENCY_GEN1 => 7,
      LINK_CAP_L1_EXIT_LATENCY_GEN2 => 7,
      LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => "FALSE",
      LINK_CAP_MAX_LINK_SPEED => X"1",
      LINK_CAP_MAX_LINK_WIDTH => X"08",
      LINK_CAP_RSVD_23 => 0,
      LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => "FALSE",
      LINK_CONTROL_RCB => 0,
      LINK_CTRL2_DEEMPHASIS => "FALSE",
      LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => "FALSE",
      LINK_CTRL2_TARGET_LINK_SPEED => X"0",
      LINK_STATUS_SLOT_CLOCK_CONFIG => "TRUE",
      LL_ACK_TIMEOUT => X"0000",
      LL_ACK_TIMEOUT_EN => "FALSE",
      LL_ACK_TIMEOUT_FUNC => 0,
      LL_REPLAY_TIMEOUT => X"0000",
      LL_REPLAY_TIMEOUT_EN => "FALSE",
      LL_REPLAY_TIMEOUT_FUNC => 1,
      LTSSM_MAX_LINK_WIDTH => X"08",
      MPS_FORCE => "FALSE",
      MSIX_BASE_PTR => X"9C",
      MSIX_CAP_ID => X"11",
      MSIX_CAP_NEXTPTR => X"00",
      MSIX_CAP_ON => "FALSE",
      MSIX_CAP_PBA_BIR => 0,
      MSIX_CAP_PBA_OFFSET => X"00000000",
      MSIX_CAP_TABLE_BIR => 0,
      MSIX_CAP_TABLE_OFFSET => X"00000000",
      MSIX_CAP_TABLE_SIZE => X"000",
      MSI_BASE_PTR => X"48",
      MSI_CAP_64_BIT_ADDR_CAPABLE => "TRUE",
      MSI_CAP_ID => X"05",
      MSI_CAP_MULTIMSGCAP => 0,
      MSI_CAP_MULTIMSG_EXTENSION => 0,
      MSI_CAP_NEXTPTR => X"60",
      MSI_CAP_ON => "TRUE",
      MSI_CAP_PER_VECTOR_MASKING_CAPABLE => "FALSE",
      N_FTS_COMCLK_GEN1 => 255,
      N_FTS_COMCLK_GEN2 => 255,
      N_FTS_GEN1 => 255,
      N_FTS_GEN2 => 255,
      PCIE_BASE_PTR => X"60",
      PCIE_CAP_CAPABILITY_ID => X"10",
      PCIE_CAP_CAPABILITY_VERSION => X"2",
      PCIE_CAP_DEVICE_PORT_TYPE => X"0",
      PCIE_CAP_NEXTPTR => X"00",
      PCIE_CAP_ON => "TRUE",
      PCIE_CAP_RSVD_15_14 => 0,
      PCIE_CAP_SLOT_IMPLEMENTED => "FALSE",
      PCIE_REVISION => 2,
      PL_AUTO_CONFIG => 0,
      PL_FAST_TRAIN => "TRUE",
      PM_ASPML0S_TIMEOUT => X"0000",
      PM_ASPML0S_TIMEOUT_EN => "FALSE",
      PM_ASPML0S_TIMEOUT_FUNC => 0,
      PM_ASPM_FASTEXIT => "FALSE",
      PM_BASE_PTR => X"40",
      PM_CAP_AUXCURRENT => 0,
      PM_CAP_D1SUPPORT => "FALSE",
      PM_CAP_D2SUPPORT => "FALSE",
      PM_CAP_DSI => "FALSE",
      PM_CAP_ID => X"01",
      PM_CAP_NEXTPTR => X"48",
      PM_CAP_ON => "TRUE",
      PM_CAP_PMESUPPORT => X"0F",
      PM_CAP_PME_CLOCK => "FALSE",
      PM_CAP_RSVD_04 => 0,
      PM_CAP_VERSION => 3,
      PM_CSR_B2B3 => "FALSE",
      PM_CSR_BPCCEN => "FALSE",
      PM_CSR_NOSOFTRST => "TRUE",
      PM_DATA0 => X"00",
      PM_DATA1 => X"00",
      PM_DATA2 => X"00",
      PM_DATA3 => X"00",
      PM_DATA4 => X"00",
      PM_DATA5 => X"00",
      PM_DATA6 => X"00",
      PM_DATA7 => X"00",
      PM_DATA_SCALE0 => X"0",
      PM_DATA_SCALE1 => X"0",
      PM_DATA_SCALE2 => X"0",
      PM_DATA_SCALE3 => X"0",
      PM_DATA_SCALE4 => X"0",
      PM_DATA_SCALE5 => X"0",
      PM_DATA_SCALE6 => X"0",
      PM_DATA_SCALE7 => X"0",
      PM_MF => "FALSE",
      RBAR_BASE_PTR => X"000",
      RBAR_CAP_CONTROL_ENCODEDBAR0 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR1 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR2 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR3 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR4 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR5 => X"00",
      RBAR_CAP_ID => X"0015",
      RBAR_CAP_INDEX0 => X"0",
      RBAR_CAP_INDEX1 => X"0",
      RBAR_CAP_INDEX2 => X"0",
      RBAR_CAP_INDEX3 => X"0",
      RBAR_CAP_INDEX4 => X"0",
      RBAR_CAP_INDEX5 => X"0",
      RBAR_CAP_NEXTPTR => X"000",
      RBAR_CAP_ON => "FALSE",
      RBAR_CAP_SUP0 => X"00000001",
      RBAR_CAP_SUP1 => X"00000001",
      RBAR_CAP_SUP2 => X"00000001",
      RBAR_CAP_SUP3 => X"00000001",
      RBAR_CAP_SUP4 => X"00000001",
      RBAR_CAP_SUP5 => X"00000001",
      RBAR_CAP_VERSION => X"1",
      RBAR_NUM => X"0",
      RECRC_CHK => 0,
      RECRC_CHK_TRIM => "FALSE",
      ROOT_CAP_CRS_SW_VISIBILITY => "FALSE",
      RP_AUTO_SPD => X"1",
      RP_AUTO_SPD_LOOPCNT => X"1F",
      SELECT_DLL_IF => "FALSE",
      SIM_VERSION => "1.0",
      SLOT_CAP_ATT_BUTTON_PRESENT => "FALSE",
      SLOT_CAP_ATT_INDICATOR_PRESENT => "FALSE",
      SLOT_CAP_ELEC_INTERLOCK_PRESENT => "FALSE",
      SLOT_CAP_HOTPLUG_CAPABLE => "FALSE",
      SLOT_CAP_HOTPLUG_SURPRISE => "FALSE",
      SLOT_CAP_MRL_SENSOR_PRESENT => "FALSE",
      SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => "FALSE",
      SLOT_CAP_PHYSICAL_SLOT_NUM => X"0000",
      SLOT_CAP_POWER_CONTROLLER_PRESENT => "FALSE",
      SLOT_CAP_POWER_INDICATOR_PRESENT => "FALSE",
      SLOT_CAP_SLOT_POWER_LIMIT_SCALE => 0,
      SLOT_CAP_SLOT_POWER_LIMIT_VALUE => X"00",
      SPARE_BIT0 => 0,
      SPARE_BIT1 => 0,
      SPARE_BIT2 => 0,
      SPARE_BIT3 => 0,
      SPARE_BIT4 => 0,
      SPARE_BIT5 => 0,
      SPARE_BIT6 => 0,
      SPARE_BIT7 => 0,
      SPARE_BIT8 => 0,
      SPARE_BYTE0 => X"00",
      SPARE_BYTE1 => X"00",
      SPARE_BYTE2 => X"00",
      SPARE_BYTE3 => X"00",
      SPARE_WORD0 => X"00000000",
      SPARE_WORD1 => X"00000000",
      SPARE_WORD2 => X"00000000",
      SPARE_WORD3 => X"00000000",
      SSL_MESSAGE_AUTO => "FALSE",
      TECRC_EP_INV => "FALSE",
      TL_RBYPASS => "FALSE",
      TL_RX_RAM_RADDR_LATENCY => 0,
      TL_RX_RAM_RDATA_LATENCY => 2,
      TL_RX_RAM_WRITE_LATENCY => 0,
      TL_TFC_DISABLE => "FALSE",
      TL_TX_CHECKS_DISABLE => "FALSE",
      TL_TX_RAM_RADDR_LATENCY => 0,
      TL_TX_RAM_RDATA_LATENCY => 2,
      TL_TX_RAM_WRITE_LATENCY => 0,
      TRN_DW => "FALSE",
      TRN_NP_FC => "TRUE",
      UPCONFIG_CAPABLE => "TRUE",
      UPSTREAM_FACING => "TRUE",
      UR_ATOMIC => "FALSE",
      UR_CFG1 => "TRUE",
      UR_INV_REQ => "TRUE",
      UR_PRS_RESPONSE => "TRUE",
      USER_CLK2_DIV2 => "FALSE",
      USER_CLK_FREQ => 3,
      USE_RID_PINS => "FALSE",
      VC0_CPL_INFINITE => "TRUE",
      VC0_RX_RAM_LIMIT => X"07FF",
      VC0_TOTAL_CREDITS_CD => 850,
      VC0_TOTAL_CREDITS_CH => 72,
      VC0_TOTAL_CREDITS_NPD => 8,
      VC0_TOTAL_CREDITS_NPH => 4,
      VC0_TOTAL_CREDITS_PD => 64,
      VC0_TOTAL_CREDITS_PH => 4,
      VC0_TX_LASTPACKET => 29,
      VC_BASE_PTR => X"000",
      VC_CAP_ID => X"0002",
      VC_CAP_NEXTPTR => X"000",
      VC_CAP_ON => "FALSE",
      VC_CAP_REJECT_SNOOP_TRANSACTIONS => "FALSE",
      VC_CAP_VERSION => X"1",
      VSEC_BASE_PTR => X"000",
      VSEC_CAP_HDR_ID => X"1234",
      VSEC_CAP_HDR_LENGTH => X"018",
      VSEC_CAP_HDR_REVISION => X"1",
      VSEC_CAP_ID => X"000B",
      VSEC_CAP_IS_LINK_VISIBLE => "TRUE",
      VSEC_CAP_NEXTPTR => X"000",
      VSEC_CAP_ON => "FALSE",
      VSEC_CAP_VERSION => X"1"
    )
        port map (
      CFGAERECRCCHECKEN => cfg_aer_ecrc_check_en,
      CFGAERECRCGENEN => cfg_aer_ecrc_gen_en,
      CFGAERINTERRUPTMSGNUM(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0),
      CFGAERROOTERRCORRERRRECEIVED => cfg_aer_rooterr_corr_err_received,
      CFGAERROOTERRCORRERRREPORTINGEN => cfg_aer_rooterr_corr_err_reporting_en,
      CFGAERROOTERRFATALERRRECEIVED => cfg_aer_rooterr_fatal_err_received,
      CFGAERROOTERRFATALERRREPORTINGEN => cfg_aer_rooterr_fatal_err_reporting_en,
      CFGAERROOTERRNONFATALERRRECEIVED => cfg_aer_rooterr_non_fatal_err_received,
      CFGAERROOTERRNONFATALERRREPORTINGEN => cfg_aer_rooterr_non_fatal_err_reporting_en,
      CFGBRIDGESERREN => cfg_bridge_serr_en,
      CFGCOMMANDBUSMASTERENABLE => cfg_command(2),
      CFGCOMMANDINTERRUPTDISABLE => cfg_command(4),
      CFGCOMMANDIOENABLE => cfg_command(0),
      CFGCOMMANDMEMENABLE => cfg_command(1),
      CFGCOMMANDSERREN => cfg_command(3),
      CFGDEVCONTROL2ARIFORWARDEN => cfg_dcommand2(5),
      CFGDEVCONTROL2ATOMICEGRESSBLOCK => cfg_dcommand2(7),
      CFGDEVCONTROL2ATOMICREQUESTEREN => cfg_dcommand2(6),
      CFGDEVCONTROL2CPLTIMEOUTDIS => cfg_dcommand2(4),
      CFGDEVCONTROL2CPLTIMEOUTVAL(3 downto 0) => cfg_dcommand2(3 downto 0),
      CFGDEVCONTROL2IDOCPLEN => cfg_dcommand2(9),
      CFGDEVCONTROL2IDOREQEN => cfg_dcommand2(8),
      CFGDEVCONTROL2LTREN => cfg_dcommand2(10),
      CFGDEVCONTROL2TLPPREFIXBLOCK => cfg_dcommand2(11),
      CFGDEVCONTROLAUXPOWEREN => cfg_dcommand(10),
      CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dcommand(0),
      CFGDEVCONTROLENABLERO => cfg_dcommand(4),
      CFGDEVCONTROLEXTTAGEN => cfg_dcommand(8),
      CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dcommand(2),
      CFGDEVCONTROLMAXPAYLOAD(2 downto 0) => cfg_dcommand(7 downto 5),
      CFGDEVCONTROLMAXREADREQ(2 downto 0) => cfg_dcommand(14 downto 12),
      CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dcommand(1),
      CFGDEVCONTROLNOSNOOPEN => cfg_dcommand(11),
      CFGDEVCONTROLPHANTOMEN => cfg_dcommand(9),
      CFGDEVCONTROLURERRREPORTINGEN => cfg_dcommand(3),
      CFGDEVID(15) => '0',
      CFGDEVID(14) => '1',
      CFGDEVID(13) => '1',
      CFGDEVID(12) => '1',
      CFGDEVID(11) => '0',
      CFGDEVID(10) => '0',
      CFGDEVID(9) => '0',
      CFGDEVID(8) => '0',
      CFGDEVID(7) => '0',
      CFGDEVID(6) => '0',
      CFGDEVID(5) => '0',
      CFGDEVID(4) => '1',
      CFGDEVID(3) => '1',
      CFGDEVID(2) => '0',
      CFGDEVID(1) => '0',
      CFGDEVID(0) => '0',
      CFGDEVSTATUSCORRERRDETECTED => cfg_dstatus(0),
      CFGDEVSTATUSFATALERRDETECTED => cfg_dstatus(2),
      CFGDEVSTATUSNONFATALERRDETECTED => cfg_dstatus(1),
      CFGDEVSTATUSURDETECTED => cfg_dstatus(3),
      CFGDSBUSNUMBER(7 downto 0) => cfg_ds_bus_number(7 downto 0),
      CFGDSDEVICENUMBER(4 downto 0) => cfg_ds_device_number(4 downto 0),
      CFGDSFUNCTIONNUMBER(2 downto 0) => cfg_ds_function_number(2 downto 0),
      CFGDSN(63 downto 0) => cfg_dsn(63 downto 0),
      CFGERRACSN => '1',
      CFGERRAERHEADERLOG(127 downto 0) => cfg_err_aer_headerlog(127 downto 0),
      CFGERRAERHEADERLOGSETN => cfg_err_aer_headerlog_set_n,
      CFGERRATOMICEGRESSBLOCKEDN => cfg_err_atomic_egress_blocked_n,
      CFGERRCORN => cfg_err_cor_n,
      CFGERRCPLABORTN => cfg_err_cpl_abort_n,
      CFGERRCPLRDYN => cfg_err_cpl_rdy_n,
      CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n,
      CFGERRCPLUNEXPECTN => cfg_err_cpl_unexpect_n,
      CFGERRECRCN => cfg_err_ecrc_n,
      CFGERRINTERNALCORN => cfg_err_internal_cor_n,
      CFGERRINTERNALUNCORN => cfg_err_internal_uncor_n,
      CFGERRLOCKEDN => cfg_err_locked_n,
      CFGERRMALFORMEDN => cfg_err_malformed_n,
      CFGERRMCBLOCKEDN => cfg_err_mc_blocked_n,
      CFGERRNORECOVERYN => cfg_err_norecovery_n,
      CFGERRPOISONEDN => cfg_err_poisoned_n,
      CFGERRPOSTEDN => cfg_err_posted_n,
      CFGERRTLPCPLHEADER(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0),
      CFGERRURN => cfg_err_ur_n,
      CFGFORCECOMMONCLOCKOFF => '0',
      CFGFORCEEXTENDEDSYNCON => '0',
      CFGFORCEMPS(2) => '0',
      CFGFORCEMPS(1) => '0',
      CFGFORCEMPS(0) => '0',
      CFGINTERRUPTASSERTN => cfg_interrupt_assert_n,
      CFGINTERRUPTDI(7 downto 0) => cfg_interrupt_di(7 downto 0),
      CFGINTERRUPTDO(7 downto 0) => cfg_interrupt_do(7 downto 0),
      CFGINTERRUPTMMENABLE(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable,
      CFGINTERRUPTMSIXENABLE => cfg_interrupt_msixenable,
      CFGINTERRUPTMSIXFM => cfg_interrupt_msixfm,
      CFGINTERRUPTN => cfg_interrupt_n,
      CFGINTERRUPTRDYN => cfg_interrupt_rdy_n,
      CFGINTERRUPTSTATN => cfg_interrupt_stat_n,
      CFGLINKCONTROLASPMCONTROL(1 downto 0) => cfg_lcommand(1 downto 0),
      CFGLINKCONTROLAUTOBANDWIDTHINTEN => cfg_lcommand(10),
      CFGLINKCONTROLBANDWIDTHINTEN => cfg_lcommand(9),
      CFGLINKCONTROLCLOCKPMEN => cfg_lcommand(7),
      CFGLINKCONTROLCOMMONCLOCK => cfg_lcommand(5),
      CFGLINKCONTROLEXTENDEDSYNC => cfg_lcommand(6),
      CFGLINKCONTROLHWAUTOWIDTHDIS => cfg_lcommand(8),
      CFGLINKCONTROLLINKDISABLE => cfg_lcommand(3),
      CFGLINKCONTROLRCB => cfg_lcommand(2),
      CFGLINKCONTROLRETRAINLINK => cfg_lcommand(4),
      CFGLINKSTATUSAUTOBANDWIDTHSTATUS => cfg_lstatus(9),
      CFGLINKSTATUSBANDWIDTHSTATUS => cfg_lstatus(8),
      CFGLINKSTATUSCURRENTSPEED(1 downto 0) => cfg_lstatus(1 downto 0),
      CFGLINKSTATUSDLLACTIVE => cfg_lstatus(7),
      CFGLINKSTATUSLINKTRAINING => cfg_lstatus(6),
      CFGLINKSTATUSNEGOTIATEDWIDTH(3 downto 0) => cfg_lstatus(5 downto 2),
      CFGMGMTBYTEENN(3 downto 0) => cfg_mgmt_byte_en_n(3 downto 0),
      CFGMGMTDI(31 downto 0) => cfg_mgmt_di(31 downto 0),
      CFGMGMTDO(31 downto 0) => cfg_mgmt_do(31 downto 0),
      CFGMGMTDWADDR(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      CFGMGMTRDENN => cfg_mgmt_rd_en_n,
      CFGMGMTRDWRDONEN => cfg_mgmt_rd_wr_done_n,
      CFGMGMTWRENN => cfg_mgmt_wr_en_n,
      CFGMGMTWRREADONLYN => cfg_mgmt_wr_readonly_n,
      CFGMGMTWRRW1CASRWN => cfg_mgmt_wr_rw1c_as_rw_n,
      CFGMSGDATA(15 downto 0) => cfg_msg_data(15 downto 0),
      CFGMSGRECEIVED => \^cfg_msg_received\,
      CFGMSGRECEIVEDASSERTINTA => cfg_msg_received_assert_int_a,
      CFGMSGRECEIVEDASSERTINTB => cfg_msg_received_assert_int_b,
      CFGMSGRECEIVEDASSERTINTC => cfg_msg_received_assert_int_c,
      CFGMSGRECEIVEDASSERTINTD => cfg_msg_received_assert_int_d,
      CFGMSGRECEIVEDDEASSERTINTA => cfg_msg_received_deassert_int_a,
      CFGMSGRECEIVEDDEASSERTINTB => cfg_msg_received_deassert_int_b,
      CFGMSGRECEIVEDDEASSERTINTC => cfg_msg_received_deassert_int_c,
      CFGMSGRECEIVEDDEASSERTINTD => cfg_msg_received_deassert_int_d,
      CFGMSGRECEIVEDERRCOR => cfg_msg_received_err_cor,
      CFGMSGRECEIVEDERRFATAL => cfg_msg_received_err_fatal,
      CFGMSGRECEIVEDERRNONFATAL => cfg_msg_received_err_non_fatal,
      CFGMSGRECEIVEDPMASNAK => cfg_msg_received_pm_as_nak,
      CFGMSGRECEIVEDPMETO => cfg_to_turnoff,
      CFGMSGRECEIVEDPMETOACK => cfg_msg_received_pme_to_ack,
      CFGMSGRECEIVEDPMPME => cfg_msg_received_pm_pme,
      CFGMSGRECEIVEDSETSLOTPOWERLIMIT => cfg_msg_received_setslotpowerlimit,
      CFGMSGRECEIVEDUNLOCK => pcie_block_i_n_72,
      CFGPCIECAPINTERRUPTMSGNUM(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0),
      CFGPCIELINKSTATE(2 downto 0) => \^cfg_pcie_link_state\(2 downto 0),
      CFGPMCSRPMEEN => cfg_pmcsr_pme_en,
      CFGPMCSRPMESTATUS => cfg_pmcsr_pme_status,
      CFGPMCSRPOWERSTATE(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0),
      CFGPMFORCESTATE(1 downto 0) => cfg_pm_force_state(1 downto 0),
      CFGPMFORCESTATEENN => cfg_pm_force_state_en_n,
      CFGPMHALTASPML0SN => cfg_pm_halt_aspm_l0s_n,
      CFGPMHALTASPML1N => cfg_pm_halt_aspm_l1_n,
      CFGPMRCVASREQL1N => pcie_block_i_n_75,
      CFGPMRCVENTERL1N => pcie_block_i_n_76,
      CFGPMRCVENTERL23N => pcie_block_i_n_77,
      CFGPMRCVREQACKN => pcie_block_i_n_78,
      CFGPMSENDPMETON => '1',
      CFGPMTURNOFFOKN => cfg_pm_turnoff_ok_n,
      CFGPMWAKEN => cfg_pm_wake_n,
      CFGPORTNUMBER(7) => '0',
      CFGPORTNUMBER(6) => '0',
      CFGPORTNUMBER(5) => '0',
      CFGPORTNUMBER(4) => '0',
      CFGPORTNUMBER(3) => '0',
      CFGPORTNUMBER(2) => '0',
      CFGPORTNUMBER(1) => '0',
      CFGPORTNUMBER(0) => '0',
      CFGREVID(7) => '0',
      CFGREVID(6) => '0',
      CFGREVID(5) => '0',
      CFGREVID(4) => '0',
      CFGREVID(3) => '0',
      CFGREVID(2) => '0',
      CFGREVID(1) => '0',
      CFGREVID(0) => '0',
      CFGROOTCONTROLPMEINTEN => cfg_root_control_pme_int_en,
      CFGROOTCONTROLSYSERRCORRERREN => cfg_root_control_syserr_corr_err_en,
      CFGROOTCONTROLSYSERRFATALERREN => cfg_root_control_syserr_fatal_err_en,
      CFGROOTCONTROLSYSERRNONFATALERREN => cfg_root_control_syserr_non_fatal_err_en,
      CFGSLOTCONTROLELECTROMECHILCTLPULSE => cfg_slot_control_electromech_il_ctl_pulse,
      CFGSUBSYSID(15) => '0',
      CFGSUBSYSID(14) => '0',
      CFGSUBSYSID(13) => '0',
      CFGSUBSYSID(12) => '0',
      CFGSUBSYSID(11) => '0',
      CFGSUBSYSID(10) => '0',
      CFGSUBSYSID(9) => '0',
      CFGSUBSYSID(8) => '0',
      CFGSUBSYSID(7) => '0',
      CFGSUBSYSID(6) => '0',
      CFGSUBSYSID(5) => '0',
      CFGSUBSYSID(4) => '0',
      CFGSUBSYSID(3) => '0',
      CFGSUBSYSID(2) => '1',
      CFGSUBSYSID(1) => '1',
      CFGSUBSYSID(0) => '1',
      CFGSUBSYSVENDID(15) => '0',
      CFGSUBSYSVENDID(14) => '0',
      CFGSUBSYSVENDID(13) => '0',
      CFGSUBSYSVENDID(12) => '1',
      CFGSUBSYSVENDID(11) => '0',
      CFGSUBSYSVENDID(10) => '0',
      CFGSUBSYSVENDID(9) => '0',
      CFGSUBSYSVENDID(8) => '0',
      CFGSUBSYSVENDID(7) => '1',
      CFGSUBSYSVENDID(6) => '1',
      CFGSUBSYSVENDID(5) => '1',
      CFGSUBSYSVENDID(4) => '0',
      CFGSUBSYSVENDID(3) => '1',
      CFGSUBSYSVENDID(2) => '1',
      CFGSUBSYSVENDID(1) => '1',
      CFGSUBSYSVENDID(0) => '0',
      CFGTRANSACTION => pcie_block_i_n_84,
      CFGTRANSACTIONADDR(6) => pcie_block_i_n_1097,
      CFGTRANSACTIONADDR(5) => pcie_block_i_n_1098,
      CFGTRANSACTIONADDR(4) => pcie_block_i_n_1099,
      CFGTRANSACTIONADDR(3) => pcie_block_i_n_1100,
      CFGTRANSACTIONADDR(2) => pcie_block_i_n_1101,
      CFGTRANSACTIONADDR(1) => pcie_block_i_n_1102,
      CFGTRANSACTIONADDR(0) => pcie_block_i_n_1103,
      CFGTRANSACTIONTYPE => pcie_block_i_n_85,
      CFGTRNPENDINGN => cfg_trn_pending_n,
      CFGVCTCVCMAP(6 downto 0) => cfg_vc_tcvc_map(6 downto 0),
      CFGVENDID(15) => '0',
      CFGVENDID(14) => '0',
      CFGVENDID(13) => '0',
      CFGVENDID(12) => '1',
      CFGVENDID(11) => '0',
      CFGVENDID(10) => '0',
      CFGVENDID(9) => '0',
      CFGVENDID(8) => '0',
      CFGVENDID(7) => '1',
      CFGVENDID(6) => '1',
      CFGVENDID(5) => '1',
      CFGVENDID(4) => '0',
      CFGVENDID(3) => '1',
      CFGVENDID(2) => '1',
      CFGVENDID(1) => '1',
      CFGVENDID(0) => '0',
      CMRSTN => '1',
      CMSTICKYRSTN => '1',
      DBGMODE(1) => '0',
      DBGMODE(0) => '0',
      DBGSCLRA => pcie_block_i_n_86,
      DBGSCLRB => pcie_block_i_n_87,
      DBGSCLRC => pcie_block_i_n_88,
      DBGSCLRD => pcie_block_i_n_89,
      DBGSCLRE => pcie_block_i_n_90,
      DBGSCLRF => pcie_block_i_n_91,
      DBGSCLRG => pcie_block_i_n_92,
      DBGSCLRH => pcie_block_i_n_93,
      DBGSCLRI => pcie_block_i_n_94,
      DBGSCLRJ => pcie_block_i_n_95,
      DBGSCLRK => pcie_block_i_n_96,
      DBGSUBMODE => '0',
      DBGVECA(63) => pcie_block_i_n_704,
      DBGVECA(62) => pcie_block_i_n_705,
      DBGVECA(61) => pcie_block_i_n_706,
      DBGVECA(60) => pcie_block_i_n_707,
      DBGVECA(59) => pcie_block_i_n_708,
      DBGVECA(58) => pcie_block_i_n_709,
      DBGVECA(57) => pcie_block_i_n_710,
      DBGVECA(56) => pcie_block_i_n_711,
      DBGVECA(55) => pcie_block_i_n_712,
      DBGVECA(54) => pcie_block_i_n_713,
      DBGVECA(53) => pcie_block_i_n_714,
      DBGVECA(52) => pcie_block_i_n_715,
      DBGVECA(51) => pcie_block_i_n_716,
      DBGVECA(50) => pcie_block_i_n_717,
      DBGVECA(49) => pcie_block_i_n_718,
      DBGVECA(48) => pcie_block_i_n_719,
      DBGVECA(47) => pcie_block_i_n_720,
      DBGVECA(46) => pcie_block_i_n_721,
      DBGVECA(45) => pcie_block_i_n_722,
      DBGVECA(44) => pcie_block_i_n_723,
      DBGVECA(43) => pcie_block_i_n_724,
      DBGVECA(42) => pcie_block_i_n_725,
      DBGVECA(41) => pcie_block_i_n_726,
      DBGVECA(40) => pcie_block_i_n_727,
      DBGVECA(39) => pcie_block_i_n_728,
      DBGVECA(38) => pcie_block_i_n_729,
      DBGVECA(37) => pcie_block_i_n_730,
      DBGVECA(36) => pcie_block_i_n_731,
      DBGVECA(35) => pcie_block_i_n_732,
      DBGVECA(34) => pcie_block_i_n_733,
      DBGVECA(33) => pcie_block_i_n_734,
      DBGVECA(32) => pcie_block_i_n_735,
      DBGVECA(31) => pcie_block_i_n_736,
      DBGVECA(30) => pcie_block_i_n_737,
      DBGVECA(29) => pcie_block_i_n_738,
      DBGVECA(28) => pcie_block_i_n_739,
      DBGVECA(27) => pcie_block_i_n_740,
      DBGVECA(26) => pcie_block_i_n_741,
      DBGVECA(25) => pcie_block_i_n_742,
      DBGVECA(24) => pcie_block_i_n_743,
      DBGVECA(23) => pcie_block_i_n_744,
      DBGVECA(22) => pcie_block_i_n_745,
      DBGVECA(21) => pcie_block_i_n_746,
      DBGVECA(20) => pcie_block_i_n_747,
      DBGVECA(19) => pcie_block_i_n_748,
      DBGVECA(18) => pcie_block_i_n_749,
      DBGVECA(17) => pcie_block_i_n_750,
      DBGVECA(16) => pcie_block_i_n_751,
      DBGVECA(15) => pcie_block_i_n_752,
      DBGVECA(14) => pcie_block_i_n_753,
      DBGVECA(13) => pcie_block_i_n_754,
      DBGVECA(12) => pcie_block_i_n_755,
      DBGVECA(11) => pcie_block_i_n_756,
      DBGVECA(10) => pcie_block_i_n_757,
      DBGVECA(9) => pcie_block_i_n_758,
      DBGVECA(8) => pcie_block_i_n_759,
      DBGVECA(7) => pcie_block_i_n_760,
      DBGVECA(6) => pcie_block_i_n_761,
      DBGVECA(5) => pcie_block_i_n_762,
      DBGVECA(4) => pcie_block_i_n_763,
      DBGVECA(3) => pcie_block_i_n_764,
      DBGVECA(2) => pcie_block_i_n_765,
      DBGVECA(1) => pcie_block_i_n_766,
      DBGVECA(0) => pcie_block_i_n_767,
      DBGVECB(63) => pcie_block_i_n_768,
      DBGVECB(62) => pcie_block_i_n_769,
      DBGVECB(61) => pcie_block_i_n_770,
      DBGVECB(60) => pcie_block_i_n_771,
      DBGVECB(59) => pcie_block_i_n_772,
      DBGVECB(58) => pcie_block_i_n_773,
      DBGVECB(57) => pcie_block_i_n_774,
      DBGVECB(56) => pcie_block_i_n_775,
      DBGVECB(55) => pcie_block_i_n_776,
      DBGVECB(54) => pcie_block_i_n_777,
      DBGVECB(53) => pcie_block_i_n_778,
      DBGVECB(52) => pcie_block_i_n_779,
      DBGVECB(51) => pcie_block_i_n_780,
      DBGVECB(50) => pcie_block_i_n_781,
      DBGVECB(49) => pcie_block_i_n_782,
      DBGVECB(48) => pcie_block_i_n_783,
      DBGVECB(47) => pcie_block_i_n_784,
      DBGVECB(46) => pcie_block_i_n_785,
      DBGVECB(45) => pcie_block_i_n_786,
      DBGVECB(44) => pcie_block_i_n_787,
      DBGVECB(43) => pcie_block_i_n_788,
      DBGVECB(42) => pcie_block_i_n_789,
      DBGVECB(41) => pcie_block_i_n_790,
      DBGVECB(40) => pcie_block_i_n_791,
      DBGVECB(39) => pcie_block_i_n_792,
      DBGVECB(38) => pcie_block_i_n_793,
      DBGVECB(37) => pcie_block_i_n_794,
      DBGVECB(36) => pcie_block_i_n_795,
      DBGVECB(35) => pcie_block_i_n_796,
      DBGVECB(34) => pcie_block_i_n_797,
      DBGVECB(33) => pcie_block_i_n_798,
      DBGVECB(32) => pcie_block_i_n_799,
      DBGVECB(31) => pcie_block_i_n_800,
      DBGVECB(30) => pcie_block_i_n_801,
      DBGVECB(29) => pcie_block_i_n_802,
      DBGVECB(28) => pcie_block_i_n_803,
      DBGVECB(27) => pcie_block_i_n_804,
      DBGVECB(26) => pcie_block_i_n_805,
      DBGVECB(25) => pcie_block_i_n_806,
      DBGVECB(24) => pcie_block_i_n_807,
      DBGVECB(23) => pcie_block_i_n_808,
      DBGVECB(22) => pcie_block_i_n_809,
      DBGVECB(21) => pcie_block_i_n_810,
      DBGVECB(20) => pcie_block_i_n_811,
      DBGVECB(19) => pcie_block_i_n_812,
      DBGVECB(18) => pcie_block_i_n_813,
      DBGVECB(17) => pcie_block_i_n_814,
      DBGVECB(16) => pcie_block_i_n_815,
      DBGVECB(15) => pcie_block_i_n_816,
      DBGVECB(14) => pcie_block_i_n_817,
      DBGVECB(13) => pcie_block_i_n_818,
      DBGVECB(12) => pcie_block_i_n_819,
      DBGVECB(11) => pcie_block_i_n_820,
      DBGVECB(10) => pcie_block_i_n_821,
      DBGVECB(9) => pcie_block_i_n_822,
      DBGVECB(8) => pcie_block_i_n_823,
      DBGVECB(7) => pcie_block_i_n_824,
      DBGVECB(6) => pcie_block_i_n_825,
      DBGVECB(5) => pcie_block_i_n_826,
      DBGVECB(4) => pcie_block_i_n_827,
      DBGVECB(3) => pcie_block_i_n_828,
      DBGVECB(2) => pcie_block_i_n_829,
      DBGVECB(1) => pcie_block_i_n_830,
      DBGVECB(0) => pcie_block_i_n_831,
      DBGVECC(11) => pcie_block_i_n_172,
      DBGVECC(10) => pcie_block_i_n_173,
      DBGVECC(9) => pcie_block_i_n_174,
      DBGVECC(8) => pcie_block_i_n_175,
      DBGVECC(7) => pcie_block_i_n_176,
      DBGVECC(6) => pcie_block_i_n_177,
      DBGVECC(5) => pcie_block_i_n_178,
      DBGVECC(4) => pcie_block_i_n_179,
      DBGVECC(3) => pcie_block_i_n_180,
      DBGVECC(2) => pcie_block_i_n_181,
      DBGVECC(1) => pcie_block_i_n_182,
      DBGVECC(0) => pcie_block_i_n_183,
      DLRSTN => '1',
      DRPADDR(8 downto 0) => pcie_drp_addr(8 downto 0),
      DRPCLK => pcie_drp_clk,
      DRPDI(15 downto 0) => pcie_drp_di(15 downto 0),
      DRPDO(15 downto 0) => pcie_drp_do(15 downto 0),
      DRPEN => pcie_drp_en,
      DRPRDY => pcie_drp_rdy,
      DRPWE => pcie_drp_we,
      FUNCLVLRSTN => '1',
      LL2BADDLLPERR => pcie_block_i_n_98,
      LL2BADTLPERR => pcie_block_i_n_99,
      LL2LINKSTATUS(4) => pcie_block_i_n_687,
      LL2LINKSTATUS(3) => pcie_block_i_n_688,
      LL2LINKSTATUS(2) => pcie_block_i_n_689,
      LL2LINKSTATUS(1) => pcie_block_i_n_690,
      LL2LINKSTATUS(0) => pcie_block_i_n_691,
      LL2PROTOCOLERR => pcie_block_i_n_100,
      LL2RECEIVERERR => pcie_block_i_n_101,
      LL2REPLAYROERR => pcie_block_i_n_102,
      LL2REPLAYTOERR => pcie_block_i_n_103,
      LL2SENDASREQL1 => '0',
      LL2SENDENTERL1 => '0',
      LL2SENDENTERL23 => '0',
      LL2SENDPMACK => '0',
      LL2SUSPENDNOW => '0',
      LL2SUSPENDOK => pcie_block_i_n_104,
      LL2TFCINIT1SEQ => pcie_block_i_n_105,
      LL2TFCINIT2SEQ => pcie_block_i_n_106,
      LL2TLPRCV => '0',
      LL2TXIDLE => pcie_block_i_n_107,
      LNKCLKEN => pcie_block_i_n_108,
      MIMRXRADDR(12 downto 0) => mim_rx_raddr(12 downto 0),
      MIMRXRDATA(67) => pcie_bram_top_n_69,
      MIMRXRDATA(66) => pcie_bram_top_n_70,
      MIMRXRDATA(65) => pcie_bram_top_n_71,
      MIMRXRDATA(64) => pcie_bram_top_n_72,
      MIMRXRDATA(63) => pcie_bram_top_n_73,
      MIMRXRDATA(62) => pcie_bram_top_n_74,
      MIMRXRDATA(61) => pcie_bram_top_n_75,
      MIMRXRDATA(60) => pcie_bram_top_n_76,
      MIMRXRDATA(59) => pcie_bram_top_n_77,
      MIMRXRDATA(58) => pcie_bram_top_n_78,
      MIMRXRDATA(57) => pcie_bram_top_n_79,
      MIMRXRDATA(56) => pcie_bram_top_n_80,
      MIMRXRDATA(55) => pcie_bram_top_n_81,
      MIMRXRDATA(54) => pcie_bram_top_n_82,
      MIMRXRDATA(53) => pcie_bram_top_n_83,
      MIMRXRDATA(52) => pcie_bram_top_n_84,
      MIMRXRDATA(51) => pcie_bram_top_n_85,
      MIMRXRDATA(50) => pcie_bram_top_n_86,
      MIMRXRDATA(49) => pcie_bram_top_n_87,
      MIMRXRDATA(48) => pcie_bram_top_n_88,
      MIMRXRDATA(47) => pcie_bram_top_n_89,
      MIMRXRDATA(46) => pcie_bram_top_n_90,
      MIMRXRDATA(45) => pcie_bram_top_n_91,
      MIMRXRDATA(44) => pcie_bram_top_n_92,
      MIMRXRDATA(43) => pcie_bram_top_n_93,
      MIMRXRDATA(42) => pcie_bram_top_n_94,
      MIMRXRDATA(41) => pcie_bram_top_n_95,
      MIMRXRDATA(40) => pcie_bram_top_n_96,
      MIMRXRDATA(39) => pcie_bram_top_n_97,
      MIMRXRDATA(38) => pcie_bram_top_n_98,
      MIMRXRDATA(37) => pcie_bram_top_n_99,
      MIMRXRDATA(36) => pcie_bram_top_n_100,
      MIMRXRDATA(35) => pcie_bram_top_n_101,
      MIMRXRDATA(34) => pcie_bram_top_n_102,
      MIMRXRDATA(33) => pcie_bram_top_n_103,
      MIMRXRDATA(32) => pcie_bram_top_n_104,
      MIMRXRDATA(31) => pcie_bram_top_n_105,
      MIMRXRDATA(30) => pcie_bram_top_n_106,
      MIMRXRDATA(29) => pcie_bram_top_n_107,
      MIMRXRDATA(28) => pcie_bram_top_n_108,
      MIMRXRDATA(27) => pcie_bram_top_n_109,
      MIMRXRDATA(26) => pcie_bram_top_n_110,
      MIMRXRDATA(25) => pcie_bram_top_n_111,
      MIMRXRDATA(24) => pcie_bram_top_n_112,
      MIMRXRDATA(23) => pcie_bram_top_n_113,
      MIMRXRDATA(22) => pcie_bram_top_n_114,
      MIMRXRDATA(21) => pcie_bram_top_n_115,
      MIMRXRDATA(20) => pcie_bram_top_n_116,
      MIMRXRDATA(19) => pcie_bram_top_n_117,
      MIMRXRDATA(18) => pcie_bram_top_n_118,
      MIMRXRDATA(17) => pcie_bram_top_n_119,
      MIMRXRDATA(16) => pcie_bram_top_n_120,
      MIMRXRDATA(15) => pcie_bram_top_n_121,
      MIMRXRDATA(14) => pcie_bram_top_n_122,
      MIMRXRDATA(13) => pcie_bram_top_n_123,
      MIMRXRDATA(12) => pcie_bram_top_n_124,
      MIMRXRDATA(11) => pcie_bram_top_n_125,
      MIMRXRDATA(10) => pcie_bram_top_n_126,
      MIMRXRDATA(9) => pcie_bram_top_n_127,
      MIMRXRDATA(8) => pcie_bram_top_n_128,
      MIMRXRDATA(7) => pcie_bram_top_n_129,
      MIMRXRDATA(6) => pcie_bram_top_n_130,
      MIMRXRDATA(5) => pcie_bram_top_n_131,
      MIMRXRDATA(4) => pcie_bram_top_n_132,
      MIMRXRDATA(3) => pcie_bram_top_n_133,
      MIMRXRDATA(2) => pcie_bram_top_n_134,
      MIMRXRDATA(1) => pcie_bram_top_n_135,
      MIMRXRDATA(0) => pcie_bram_top_n_136,
      MIMRXREN => mim_rx_ren,
      MIMRXWADDR(12 downto 0) => mim_rx_waddr(12 downto 0),
      MIMRXWDATA(67 downto 0) => mim_rx_wdata(67 downto 0),
      MIMRXWEN => mim_rx_wen,
      MIMTXRADDR(12 downto 0) => mim_tx_raddr(12 downto 0),
      MIMTXRDATA(68) => pcie_bram_top_n_0,
      MIMTXRDATA(67) => pcie_bram_top_n_1,
      MIMTXRDATA(66) => pcie_bram_top_n_2,
      MIMTXRDATA(65) => pcie_bram_top_n_3,
      MIMTXRDATA(64) => pcie_bram_top_n_4,
      MIMTXRDATA(63) => pcie_bram_top_n_5,
      MIMTXRDATA(62) => pcie_bram_top_n_6,
      MIMTXRDATA(61) => pcie_bram_top_n_7,
      MIMTXRDATA(60) => pcie_bram_top_n_8,
      MIMTXRDATA(59) => pcie_bram_top_n_9,
      MIMTXRDATA(58) => pcie_bram_top_n_10,
      MIMTXRDATA(57) => pcie_bram_top_n_11,
      MIMTXRDATA(56) => pcie_bram_top_n_12,
      MIMTXRDATA(55) => pcie_bram_top_n_13,
      MIMTXRDATA(54) => pcie_bram_top_n_14,
      MIMTXRDATA(53) => pcie_bram_top_n_15,
      MIMTXRDATA(52) => pcie_bram_top_n_16,
      MIMTXRDATA(51) => pcie_bram_top_n_17,
      MIMTXRDATA(50) => pcie_bram_top_n_18,
      MIMTXRDATA(49) => pcie_bram_top_n_19,
      MIMTXRDATA(48) => pcie_bram_top_n_20,
      MIMTXRDATA(47) => pcie_bram_top_n_21,
      MIMTXRDATA(46) => pcie_bram_top_n_22,
      MIMTXRDATA(45) => pcie_bram_top_n_23,
      MIMTXRDATA(44) => pcie_bram_top_n_24,
      MIMTXRDATA(43) => pcie_bram_top_n_25,
      MIMTXRDATA(42) => pcie_bram_top_n_26,
      MIMTXRDATA(41) => pcie_bram_top_n_27,
      MIMTXRDATA(40) => pcie_bram_top_n_28,
      MIMTXRDATA(39) => pcie_bram_top_n_29,
      MIMTXRDATA(38) => pcie_bram_top_n_30,
      MIMTXRDATA(37) => pcie_bram_top_n_31,
      MIMTXRDATA(36) => pcie_bram_top_n_32,
      MIMTXRDATA(35) => pcie_bram_top_n_33,
      MIMTXRDATA(34) => pcie_bram_top_n_34,
      MIMTXRDATA(33) => pcie_bram_top_n_35,
      MIMTXRDATA(32) => pcie_bram_top_n_36,
      MIMTXRDATA(31) => pcie_bram_top_n_37,
      MIMTXRDATA(30) => pcie_bram_top_n_38,
      MIMTXRDATA(29) => pcie_bram_top_n_39,
      MIMTXRDATA(28) => pcie_bram_top_n_40,
      MIMTXRDATA(27) => pcie_bram_top_n_41,
      MIMTXRDATA(26) => pcie_bram_top_n_42,
      MIMTXRDATA(25) => pcie_bram_top_n_43,
      MIMTXRDATA(24) => pcie_bram_top_n_44,
      MIMTXRDATA(23) => pcie_bram_top_n_45,
      MIMTXRDATA(22) => pcie_bram_top_n_46,
      MIMTXRDATA(21) => pcie_bram_top_n_47,
      MIMTXRDATA(20) => pcie_bram_top_n_48,
      MIMTXRDATA(19) => pcie_bram_top_n_49,
      MIMTXRDATA(18) => pcie_bram_top_n_50,
      MIMTXRDATA(17) => pcie_bram_top_n_51,
      MIMTXRDATA(16) => pcie_bram_top_n_52,
      MIMTXRDATA(15) => pcie_bram_top_n_53,
      MIMTXRDATA(14) => pcie_bram_top_n_54,
      MIMTXRDATA(13) => pcie_bram_top_n_55,
      MIMTXRDATA(12) => pcie_bram_top_n_56,
      MIMTXRDATA(11) => pcie_bram_top_n_57,
      MIMTXRDATA(10) => pcie_bram_top_n_58,
      MIMTXRDATA(9) => pcie_bram_top_n_59,
      MIMTXRDATA(8) => pcie_bram_top_n_60,
      MIMTXRDATA(7) => pcie_bram_top_n_61,
      MIMTXRDATA(6) => pcie_bram_top_n_62,
      MIMTXRDATA(5) => pcie_bram_top_n_63,
      MIMTXRDATA(4) => pcie_bram_top_n_64,
      MIMTXRDATA(3) => pcie_bram_top_n_65,
      MIMTXRDATA(2) => pcie_bram_top_n_66,
      MIMTXRDATA(1) => pcie_bram_top_n_67,
      MIMTXRDATA(0) => pcie_bram_top_n_68,
      MIMTXREN => mim_tx_ren,
      MIMTXWADDR(12 downto 0) => mim_tx_waddr(12 downto 0),
      MIMTXWDATA(68 downto 0) => mim_tx_wdata(68 downto 0),
      MIMTXWEN => mim_tx_wen,
      PIPECLK => CLK,
      PIPERX0CHANISALIGNED => pipe_rx0_chanisaligned,
      PIPERX0CHARISK(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0),
      PIPERX0DATA(15 downto 0) => Q(15 downto 0),
      PIPERX0ELECIDLE => pipe_rx0_elec_idle,
      PIPERX0PHYSTATUS => pipe_rx0_phy_status,
      PIPERX0POLARITY => pipe_rx0_polarity,
      PIPERX0STATUS(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0),
      PIPERX0VALID => pipe_rx0_valid,
      PIPERX1CHANISALIGNED => pipe_rx1_chanisaligned,
      PIPERX1CHARISK(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0),
      PIPERX1DATA(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0),
      PIPERX1ELECIDLE => pipe_rx1_elec_idle,
      PIPERX1PHYSTATUS => pipe_rx1_phy_status,
      PIPERX1POLARITY => pipe_rx1_polarity,
      PIPERX1STATUS(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0),
      PIPERX1VALID => pipe_rx1_valid,
      PIPERX2CHANISALIGNED => pipe_rx2_chanisaligned,
      PIPERX2CHARISK(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0),
      PIPERX2DATA(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0),
      PIPERX2ELECIDLE => pipe_rx2_elec_idle,
      PIPERX2PHYSTATUS => pipe_rx2_phy_status,
      PIPERX2POLARITY => pipe_rx2_polarity,
      PIPERX2STATUS(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0),
      PIPERX2VALID => pipe_rx2_valid,
      PIPERX3CHANISALIGNED => pipe_rx3_chanisaligned,
      PIPERX3CHARISK(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2\(1 downto 0),
      PIPERX3DATA(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0),
      PIPERX3ELECIDLE => pipe_rx3_elec_idle,
      PIPERX3PHYSTATUS => pipe_rx3_phy_status,
      PIPERX3POLARITY => pipe_rx3_polarity,
      PIPERX3STATUS(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(2 downto 0),
      PIPERX3VALID => pipe_rx3_valid,
      PIPERX4CHANISALIGNED => pipe_rx4_chanisaligned,
      PIPERX4CHARISK(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3\(1 downto 0),
      PIPERX4DATA(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_2\(15 downto 0),
      PIPERX4ELECIDLE => pipe_rx4_elec_idle,
      PIPERX4PHYSTATUS => pipe_rx4_phy_status,
      PIPERX4POLARITY => pipe_rx4_polarity,
      PIPERX4STATUS(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_3\(2 downto 0),
      PIPERX4VALID => pipe_rx4_valid,
      PIPERX5CHANISALIGNED => pipe_rx5_chanisaligned,
      PIPERX5CHARISK(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4\(1 downto 0),
      PIPERX5DATA(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_3\(15 downto 0),
      PIPERX5ELECIDLE => pipe_rx5_elec_idle,
      PIPERX5PHYSTATUS => pipe_rx5_phy_status,
      PIPERX5POLARITY => pipe_rx5_polarity,
      PIPERX5STATUS(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_4\(2 downto 0),
      PIPERX5VALID => pipe_rx5_valid,
      PIPERX6CHANISALIGNED => pipe_rx6_chanisaligned,
      PIPERX6CHARISK(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5\(1 downto 0),
      PIPERX6DATA(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_4\(15 downto 0),
      PIPERX6ELECIDLE => pipe_rx6_elec_idle,
      PIPERX6PHYSTATUS => pipe_rx6_phy_status,
      PIPERX6POLARITY => pipe_rx6_polarity,
      PIPERX6STATUS(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_5\(2 downto 0),
      PIPERX6VALID => pipe_rx6_valid,
      PIPERX7CHANISALIGNED => pipe_rx7_chanisaligned,
      PIPERX7CHARISK(1 downto 0) => \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_6\(1 downto 0),
      PIPERX7DATA(15 downto 0) => \pipe_stages_1.pipe_rx_data_q_reg[15]_5\(15 downto 0),
      PIPERX7ELECIDLE => pipe_rx7_elec_idle,
      PIPERX7PHYSTATUS => pipe_rx7_phy_status,
      PIPERX7POLARITY => pipe_rx7_polarity,
      PIPERX7STATUS(2 downto 0) => \pipe_stages_1.pipe_rx_status_q_reg[2]_6\(2 downto 0),
      PIPERX7VALID => pipe_rx7_valid,
      PIPETX0CHARISK(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      PIPETX0COMPLIANCE => pipe_tx0_compliance,
      PIPETX0DATA(15 downto 0) => pipe_tx0_data(15 downto 0),
      PIPETX0ELECIDLE => pipe_tx0_elec_idle,
      PIPETX0POWERDOWN(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      PIPETX1CHARISK(1 downto 0) => pipe_tx1_char_is_k(1 downto 0),
      PIPETX1COMPLIANCE => pipe_tx1_compliance,
      PIPETX1DATA(15 downto 0) => pipe_tx1_data(15 downto 0),
      PIPETX1ELECIDLE => pipe_tx1_elec_idle,
      PIPETX1POWERDOWN(1 downto 0) => pipe_tx1_powerdown(1 downto 0),
      PIPETX2CHARISK(1 downto 0) => pipe_tx2_char_is_k(1 downto 0),
      PIPETX2COMPLIANCE => pipe_tx2_compliance,
      PIPETX2DATA(15 downto 0) => pipe_tx2_data(15 downto 0),
      PIPETX2ELECIDLE => pipe_tx2_elec_idle,
      PIPETX2POWERDOWN(1 downto 0) => pipe_tx2_powerdown(1 downto 0),
      PIPETX3CHARISK(1 downto 0) => pipe_tx3_char_is_k(1 downto 0),
      PIPETX3COMPLIANCE => pipe_tx3_compliance,
      PIPETX3DATA(15 downto 0) => pipe_tx3_data(15 downto 0),
      PIPETX3ELECIDLE => pipe_tx3_elec_idle,
      PIPETX3POWERDOWN(1 downto 0) => pipe_tx3_powerdown(1 downto 0),
      PIPETX4CHARISK(1 downto 0) => pipe_tx4_char_is_k(1 downto 0),
      PIPETX4COMPLIANCE => pipe_tx4_compliance,
      PIPETX4DATA(15 downto 0) => pipe_tx4_data(15 downto 0),
      PIPETX4ELECIDLE => pipe_tx4_elec_idle,
      PIPETX4POWERDOWN(1 downto 0) => pipe_tx4_powerdown(1 downto 0),
      PIPETX5CHARISK(1 downto 0) => pipe_tx5_char_is_k(1 downto 0),
      PIPETX5COMPLIANCE => pipe_tx5_compliance,
      PIPETX5DATA(15 downto 0) => pipe_tx5_data(15 downto 0),
      PIPETX5ELECIDLE => pipe_tx5_elec_idle,
      PIPETX5POWERDOWN(1 downto 0) => pipe_tx5_powerdown(1 downto 0),
      PIPETX6CHARISK(1 downto 0) => pipe_tx6_char_is_k(1 downto 0),
      PIPETX6COMPLIANCE => pipe_tx6_compliance,
      PIPETX6DATA(15 downto 0) => pipe_tx6_data(15 downto 0),
      PIPETX6ELECIDLE => pipe_tx6_elec_idle,
      PIPETX6POWERDOWN(1 downto 0) => pipe_tx6_powerdown(1 downto 0),
      PIPETX7CHARISK(1 downto 0) => pipe_tx7_char_is_k(1 downto 0),
      PIPETX7COMPLIANCE => pipe_tx7_compliance,
      PIPETX7DATA(15 downto 0) => pipe_tx7_data(15 downto 0),
      PIPETX7ELECIDLE => pipe_tx7_elec_idle,
      PIPETX7POWERDOWN(1 downto 0) => pipe_tx7_powerdown(1 downto 0),
      PIPETXDEEMPH => pipe_tx_deemph,
      PIPETXMARGIN(2 downto 0) => pipe_tx_margin(2 downto 0),
      PIPETXRATE => pipe_tx_rate,
      PIPETXRCVRDET => pipe_tx_rcvr_det,
      PIPETXRESET => pcie_block_i_n_140,
      PL2DIRECTEDLSTATE(4) => '0',
      PL2DIRECTEDLSTATE(3) => '0',
      PL2DIRECTEDLSTATE(2) => '0',
      PL2DIRECTEDLSTATE(1) => '0',
      PL2DIRECTEDLSTATE(0) => '0',
      PL2L0REQ => pcie_block_i_n_141,
      PL2LINKUP => pcie_block_i_n_142,
      PL2RECEIVERERR => pcie_block_i_n_143,
      PL2RECOVERY => pcie_block_i_n_144,
      PL2RXELECIDLE => pcie_block_i_n_145,
      PL2RXPMSTATE(1) => pcie_block_i_n_610,
      PL2RXPMSTATE(0) => pcie_block_i_n_611,
      PL2SUSPENDOK => pcie_block_i_n_146,
      PLDBGMODE(2) => '0',
      PLDBGMODE(1) => '0',
      PLDBGMODE(0) => '0',
      PLDBGVEC(11) => pcie_block_i_n_184,
      PLDBGVEC(10) => pcie_block_i_n_185,
      PLDBGVEC(9) => pcie_block_i_n_186,
      PLDBGVEC(8) => pcie_block_i_n_187,
      PLDBGVEC(7) => pcie_block_i_n_188,
      PLDBGVEC(6) => pcie_block_i_n_189,
      PLDBGVEC(5) => pcie_block_i_n_190,
      PLDBGVEC(4) => pcie_block_i_n_191,
      PLDBGVEC(3) => pcie_block_i_n_192,
      PLDBGVEC(2) => pcie_block_i_n_193,
      PLDBGVEC(1) => pcie_block_i_n_194,
      PLDBGVEC(0) => pcie_block_i_n_195,
      PLDIRECTEDCHANGEDONE => pl_directed_change_done,
      PLDIRECTEDLINKAUTON => pl_directed_link_auton,
      PLDIRECTEDLINKCHANGE(1 downto 0) => pl_directed_link_change(1 downto 0),
      PLDIRECTEDLINKSPEED => pl_directed_link_speed,
      PLDIRECTEDLINKWIDTH(1 downto 0) => pl_directed_link_width(1 downto 0),
      PLDIRECTEDLTSSMNEW(5) => '0',
      PLDIRECTEDLTSSMNEW(4) => '0',
      PLDIRECTEDLTSSMNEW(3) => '0',
      PLDIRECTEDLTSSMNEW(2) => '0',
      PLDIRECTEDLTSSMNEW(1) => '0',
      PLDIRECTEDLTSSMNEW(0) => '0',
      PLDIRECTEDLTSSMNEWVLD => '0',
      PLDIRECTEDLTSSMSTALL => '0',
      PLDOWNSTREAMDEEMPHSOURCE => pl_downstream_deemph_source,
      PLINITIALLINKWIDTH(2 downto 0) => pl_initial_link_width(2 downto 0),
      PLLANEREVERSALMODE(1 downto 0) => pl_lane_reversal_mode(1 downto 0),
      PLLINKGEN2CAP => pl_link_gen2_cap,
      PLLINKPARTNERGEN2SUPPORTED => pl_link_partner_gen2_supported,
      PLLINKUPCFGCAP => pl_link_upcfg_cap,
      PLLTSSMSTATE(5 downto 0) => pl_ltssm_state(5 downto 0),
      PLPHYLNKUPN => pl_phy_lnk_up_n,
      PLRECEIVEDHOTRST => pl_received_hot_rst,
      PLRSTN => '1',
      PLRXPMSTATE(1 downto 0) => pl_rx_pm_state(1 downto 0),
      PLSELLNKRATE => pl_sel_lnk_rate,
      PLSELLNKWIDTH(1 downto 0) => pl_sel_lnk_width(1 downto 0),
      PLTRANSMITHOTRST => pl_transmit_hot_rst,
      PLTXPMSTATE(2 downto 0) => pl_tx_pm_state(2 downto 0),
      PLUPSTREAMPREFERDEEMPH => pl_upstream_prefer_deemph,
      RECEIVEDFUNCLVLRSTN => received_func_lvl_rst_n,
      SYSRSTN => sys_rst_n,
      TL2ASPMSUSPENDCREDITCHECK => '0',
      TL2ASPMSUSPENDCREDITCHECKOK => pcie_block_i_n_155,
      TL2ASPMSUSPENDREQ => pcie_block_i_n_156,
      TL2ERRFCPE => pcie_block_i_n_157,
      TL2ERRHDR(63) => pcie_block_i_n_832,
      TL2ERRHDR(62) => pcie_block_i_n_833,
      TL2ERRHDR(61) => pcie_block_i_n_834,
      TL2ERRHDR(60) => pcie_block_i_n_835,
      TL2ERRHDR(59) => pcie_block_i_n_836,
      TL2ERRHDR(58) => pcie_block_i_n_837,
      TL2ERRHDR(57) => pcie_block_i_n_838,
      TL2ERRHDR(56) => pcie_block_i_n_839,
      TL2ERRHDR(55) => pcie_block_i_n_840,
      TL2ERRHDR(54) => pcie_block_i_n_841,
      TL2ERRHDR(53) => pcie_block_i_n_842,
      TL2ERRHDR(52) => pcie_block_i_n_843,
      TL2ERRHDR(51) => pcie_block_i_n_844,
      TL2ERRHDR(50) => pcie_block_i_n_845,
      TL2ERRHDR(49) => pcie_block_i_n_846,
      TL2ERRHDR(48) => pcie_block_i_n_847,
      TL2ERRHDR(47) => pcie_block_i_n_848,
      TL2ERRHDR(46) => pcie_block_i_n_849,
      TL2ERRHDR(45) => pcie_block_i_n_850,
      TL2ERRHDR(44) => pcie_block_i_n_851,
      TL2ERRHDR(43) => pcie_block_i_n_852,
      TL2ERRHDR(42) => pcie_block_i_n_853,
      TL2ERRHDR(41) => pcie_block_i_n_854,
      TL2ERRHDR(40) => pcie_block_i_n_855,
      TL2ERRHDR(39) => pcie_block_i_n_856,
      TL2ERRHDR(38) => pcie_block_i_n_857,
      TL2ERRHDR(37) => pcie_block_i_n_858,
      TL2ERRHDR(36) => pcie_block_i_n_859,
      TL2ERRHDR(35) => pcie_block_i_n_860,
      TL2ERRHDR(34) => pcie_block_i_n_861,
      TL2ERRHDR(33) => pcie_block_i_n_862,
      TL2ERRHDR(32) => pcie_block_i_n_863,
      TL2ERRHDR(31) => pcie_block_i_n_864,
      TL2ERRHDR(30) => pcie_block_i_n_865,
      TL2ERRHDR(29) => pcie_block_i_n_866,
      TL2ERRHDR(28) => pcie_block_i_n_867,
      TL2ERRHDR(27) => pcie_block_i_n_868,
      TL2ERRHDR(26) => pcie_block_i_n_869,
      TL2ERRHDR(25) => pcie_block_i_n_870,
      TL2ERRHDR(24) => pcie_block_i_n_871,
      TL2ERRHDR(23) => pcie_block_i_n_872,
      TL2ERRHDR(22) => pcie_block_i_n_873,
      TL2ERRHDR(21) => pcie_block_i_n_874,
      TL2ERRHDR(20) => pcie_block_i_n_875,
      TL2ERRHDR(19) => pcie_block_i_n_876,
      TL2ERRHDR(18) => pcie_block_i_n_877,
      TL2ERRHDR(17) => pcie_block_i_n_878,
      TL2ERRHDR(16) => pcie_block_i_n_879,
      TL2ERRHDR(15) => pcie_block_i_n_880,
      TL2ERRHDR(14) => pcie_block_i_n_881,
      TL2ERRHDR(13) => pcie_block_i_n_882,
      TL2ERRHDR(12) => pcie_block_i_n_883,
      TL2ERRHDR(11) => pcie_block_i_n_884,
      TL2ERRHDR(10) => pcie_block_i_n_885,
      TL2ERRHDR(9) => pcie_block_i_n_886,
      TL2ERRHDR(8) => pcie_block_i_n_887,
      TL2ERRHDR(7) => pcie_block_i_n_888,
      TL2ERRHDR(6) => pcie_block_i_n_889,
      TL2ERRHDR(5) => pcie_block_i_n_890,
      TL2ERRHDR(4) => pcie_block_i_n_891,
      TL2ERRHDR(3) => pcie_block_i_n_892,
      TL2ERRHDR(2) => pcie_block_i_n_893,
      TL2ERRHDR(1) => pcie_block_i_n_894,
      TL2ERRHDR(0) => pcie_block_i_n_895,
      TL2ERRMALFORMED => pcie_block_i_n_158,
      TL2ERRRXOVERFLOW => pcie_block_i_n_159,
      TL2PPMSUSPENDOK => pcie_block_i_n_160,
      TL2PPMSUSPENDREQ => '0',
      TLRSTN => '1',
      TRNFCCPLD(11 downto 0) => fc_cpld(11 downto 0),
      TRNFCCPLH(7 downto 0) => fc_cplh(7 downto 0),
      TRNFCNPD(11 downto 0) => fc_npd(11 downto 0),
      TRNFCNPH(7 downto 0) => fc_nph(7 downto 0),
      TRNFCPD(11 downto 0) => fc_pd(11 downto 0),
      TRNFCPH(7 downto 0) => fc_ph(7 downto 0),
      TRNFCSEL(2 downto 0) => fc_sel(2 downto 0),
      TRNLNKUP => trn_lnk_up,
      TRNRBARHIT(7) => pcie_block_i_n_1143,
      TRNRBARHIT(6 downto 0) => trn_rbar_hit(6 downto 0),
      TRNRD(127 downto 64) => NLW_pcie_block_i_TRNRD_UNCONNECTED(127 downto 64),
      TRNRD(63 downto 0) => trn_rd(63 downto 0),
      TRNRDLLPDATA(63) => pcie_block_i_n_896,
      TRNRDLLPDATA(62) => pcie_block_i_n_897,
      TRNRDLLPDATA(61) => pcie_block_i_n_898,
      TRNRDLLPDATA(60) => pcie_block_i_n_899,
      TRNRDLLPDATA(59) => pcie_block_i_n_900,
      TRNRDLLPDATA(58) => pcie_block_i_n_901,
      TRNRDLLPDATA(57) => pcie_block_i_n_902,
      TRNRDLLPDATA(56) => pcie_block_i_n_903,
      TRNRDLLPDATA(55) => pcie_block_i_n_904,
      TRNRDLLPDATA(54) => pcie_block_i_n_905,
      TRNRDLLPDATA(53) => pcie_block_i_n_906,
      TRNRDLLPDATA(52) => pcie_block_i_n_907,
      TRNRDLLPDATA(51) => pcie_block_i_n_908,
      TRNRDLLPDATA(50) => pcie_block_i_n_909,
      TRNRDLLPDATA(49) => pcie_block_i_n_910,
      TRNRDLLPDATA(48) => pcie_block_i_n_911,
      TRNRDLLPDATA(47) => pcie_block_i_n_912,
      TRNRDLLPDATA(46) => pcie_block_i_n_913,
      TRNRDLLPDATA(45) => pcie_block_i_n_914,
      TRNRDLLPDATA(44) => pcie_block_i_n_915,
      TRNRDLLPDATA(43) => pcie_block_i_n_916,
      TRNRDLLPDATA(42) => pcie_block_i_n_917,
      TRNRDLLPDATA(41) => pcie_block_i_n_918,
      TRNRDLLPDATA(40) => pcie_block_i_n_919,
      TRNRDLLPDATA(39) => pcie_block_i_n_920,
      TRNRDLLPDATA(38) => pcie_block_i_n_921,
      TRNRDLLPDATA(37) => pcie_block_i_n_922,
      TRNRDLLPDATA(36) => pcie_block_i_n_923,
      TRNRDLLPDATA(35) => pcie_block_i_n_924,
      TRNRDLLPDATA(34) => pcie_block_i_n_925,
      TRNRDLLPDATA(33) => pcie_block_i_n_926,
      TRNRDLLPDATA(32) => pcie_block_i_n_927,
      TRNRDLLPDATA(31) => pcie_block_i_n_928,
      TRNRDLLPDATA(30) => pcie_block_i_n_929,
      TRNRDLLPDATA(29) => pcie_block_i_n_930,
      TRNRDLLPDATA(28) => pcie_block_i_n_931,
      TRNRDLLPDATA(27) => pcie_block_i_n_932,
      TRNRDLLPDATA(26) => pcie_block_i_n_933,
      TRNRDLLPDATA(25) => pcie_block_i_n_934,
      TRNRDLLPDATA(24) => pcie_block_i_n_935,
      TRNRDLLPDATA(23) => pcie_block_i_n_936,
      TRNRDLLPDATA(22) => pcie_block_i_n_937,
      TRNRDLLPDATA(21) => pcie_block_i_n_938,
      TRNRDLLPDATA(20) => pcie_block_i_n_939,
      TRNRDLLPDATA(19) => pcie_block_i_n_940,
      TRNRDLLPDATA(18) => pcie_block_i_n_941,
      TRNRDLLPDATA(17) => pcie_block_i_n_942,
      TRNRDLLPDATA(16) => pcie_block_i_n_943,
      TRNRDLLPDATA(15) => pcie_block_i_n_944,
      TRNRDLLPDATA(14) => pcie_block_i_n_945,
      TRNRDLLPDATA(13) => pcie_block_i_n_946,
      TRNRDLLPDATA(12) => pcie_block_i_n_947,
      TRNRDLLPDATA(11) => pcie_block_i_n_948,
      TRNRDLLPDATA(10) => pcie_block_i_n_949,
      TRNRDLLPDATA(9) => pcie_block_i_n_950,
      TRNRDLLPDATA(8) => pcie_block_i_n_951,
      TRNRDLLPDATA(7) => pcie_block_i_n_952,
      TRNRDLLPDATA(6) => pcie_block_i_n_953,
      TRNRDLLPDATA(5) => pcie_block_i_n_954,
      TRNRDLLPDATA(4) => pcie_block_i_n_955,
      TRNRDLLPDATA(3) => pcie_block_i_n_956,
      TRNRDLLPDATA(2) => pcie_block_i_n_957,
      TRNRDLLPDATA(1) => pcie_block_i_n_958,
      TRNRDLLPDATA(0) => pcie_block_i_n_959,
      TRNRDLLPSRCRDY(1) => pcie_block_i_n_618,
      TRNRDLLPSRCRDY(0) => pcie_block_i_n_619,
      TRNRDSTRDY => trn_rdst_rdy,
      TRNRECRCERR => trn_recrc_err,
      TRNREOF => \^trn_reof\,
      TRNRERRFWD => trn_rerrfwd,
      TRNRFCPRET => '1',
      TRNRNPOK => rx_np_ok,
      TRNRNPREQ => rx_np_req,
      TRNRREM(1) => NLW_pcie_block_i_TRNRREM_UNCONNECTED(1),
      TRNRREM(0) => trn_rrem(0),
      TRNRSOF => \^trn_rsof\,
      TRNRSRCDSC => \^trn_rsrc_dsc\,
      TRNRSRCRDY => trn_rsrc_rdy,
      TRNTBUFAV(5 downto 0) => \^trn_tbuf_av\(5 downto 0),
      TRNTCFGGNT => trn_tcfg_gnt,
      TRNTCFGREQ => trn_tcfg_req,
      TRNTD(127) => '0',
      TRNTD(126) => '0',
      TRNTD(125) => '0',
      TRNTD(124) => '0',
      TRNTD(123) => '0',
      TRNTD(122) => '0',
      TRNTD(121) => '0',
      TRNTD(120) => '0',
      TRNTD(119) => '0',
      TRNTD(118) => '0',
      TRNTD(117) => '0',
      TRNTD(116) => '0',
      TRNTD(115) => '0',
      TRNTD(114) => '0',
      TRNTD(113) => '0',
      TRNTD(112) => '0',
      TRNTD(111) => '0',
      TRNTD(110) => '0',
      TRNTD(109) => '0',
      TRNTD(108) => '0',
      TRNTD(107) => '0',
      TRNTD(106) => '0',
      TRNTD(105) => '0',
      TRNTD(104) => '0',
      TRNTD(103) => '0',
      TRNTD(102) => '0',
      TRNTD(101) => '0',
      TRNTD(100) => '0',
      TRNTD(99) => '0',
      TRNTD(98) => '0',
      TRNTD(97) => '0',
      TRNTD(96) => '0',
      TRNTD(95) => '0',
      TRNTD(94) => '0',
      TRNTD(93) => '0',
      TRNTD(92) => '0',
      TRNTD(91) => '0',
      TRNTD(90) => '0',
      TRNTD(89) => '0',
      TRNTD(88) => '0',
      TRNTD(87) => '0',
      TRNTD(86) => '0',
      TRNTD(85) => '0',
      TRNTD(84) => '0',
      TRNTD(83) => '0',
      TRNTD(82) => '0',
      TRNTD(81) => '0',
      TRNTD(80) => '0',
      TRNTD(79) => '0',
      TRNTD(78) => '0',
      TRNTD(77) => '0',
      TRNTD(76) => '0',
      TRNTD(75) => '0',
      TRNTD(74) => '0',
      TRNTD(73) => '0',
      TRNTD(72) => '0',
      TRNTD(71) => '0',
      TRNTD(70) => '0',
      TRNTD(69) => '0',
      TRNTD(68) => '0',
      TRNTD(67) => '0',
      TRNTD(66) => '0',
      TRNTD(65) => '0',
      TRNTD(64) => '0',
      TRNTD(63 downto 0) => trn_td(63 downto 0),
      TRNTDLLPDATA(31) => '0',
      TRNTDLLPDATA(30) => '0',
      TRNTDLLPDATA(29) => '0',
      TRNTDLLPDATA(28) => '0',
      TRNTDLLPDATA(27) => '0',
      TRNTDLLPDATA(26) => '0',
      TRNTDLLPDATA(25) => '0',
      TRNTDLLPDATA(24) => '0',
      TRNTDLLPDATA(23) => '0',
      TRNTDLLPDATA(22) => '0',
      TRNTDLLPDATA(21) => '0',
      TRNTDLLPDATA(20) => '0',
      TRNTDLLPDATA(19) => '0',
      TRNTDLLPDATA(18) => '0',
      TRNTDLLPDATA(17) => '0',
      TRNTDLLPDATA(16) => '0',
      TRNTDLLPDATA(15) => '0',
      TRNTDLLPDATA(14) => '0',
      TRNTDLLPDATA(13) => '0',
      TRNTDLLPDATA(12) => '0',
      TRNTDLLPDATA(11) => '0',
      TRNTDLLPDATA(10) => '0',
      TRNTDLLPDATA(9) => '0',
      TRNTDLLPDATA(8) => '0',
      TRNTDLLPDATA(7) => '0',
      TRNTDLLPDATA(6) => '0',
      TRNTDLLPDATA(5) => '0',
      TRNTDLLPDATA(4) => '0',
      TRNTDLLPDATA(3) => '0',
      TRNTDLLPDATA(2) => '0',
      TRNTDLLPDATA(1) => '0',
      TRNTDLLPDATA(0) => '0',
      TRNTDLLPDSTRDY => pcie_block_i_n_169,
      TRNTDLLPSRCRDY => '0',
      TRNTDSTRDY(3 downto 1) => NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED(3 downto 1),
      TRNTDSTRDY(0) => trn_tdst_rdy,
      TRNTECRCGEN => \xhdl12.reg_tuser_reg[3]\(0),
      TRNTEOF => trn_teof,
      TRNTERRDROP => tx_err_drop,
      TRNTERRFWD => \xhdl12.reg_tuser_reg[3]\(1),
      TRNTREM(1) => '0',
      TRNTREM(0) => trn_trem(0),
      TRNTSOF => trn_tsof,
      TRNTSRCDSC => \xhdl12.reg_tuser_reg[3]\(3),
      TRNTSRCRDY => trn_tsrc_rdy,
      TRNTSTR => \xhdl12.reg_tuser_reg[3]\(2),
      USERCLK => user_clk,
      USERCLK2 => user_clk,
      USERRSTN => user_rst_n
    );
pcie_block_i_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_atomic_egress_blocked,
      O => cfg_err_atomic_egress_blocked_n
    );
pcie_block_i_i_10: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_malformed,
      O => cfg_err_malformed_n
    );
pcie_block_i_i_11: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_mc_blocked,
      O => cfg_err_mc_blocked_n
    );
pcie_block_i_i_12: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_norecovery,
      O => cfg_err_norecovery_n
    );
pcie_block_i_i_13: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_poisoned,
      O => cfg_err_poisoned_n
    );
pcie_block_i_i_14: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_posted,
      O => cfg_err_posted_n
    );
pcie_block_i_i_15: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_ur,
      O => cfg_err_ur_n
    );
pcie_block_i_i_16: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt_assert,
      O => cfg_interrupt_assert_n
    );
pcie_block_i_i_17: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt,
      O => cfg_interrupt_n
    );
pcie_block_i_i_18: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt_stat,
      O => cfg_interrupt_stat_n
    );
pcie_block_i_i_19: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_rd_en,
      O => cfg_mgmt_rd_en_n
    );
pcie_block_i_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_cor,
      O => cfg_err_cor_n
    );
pcie_block_i_i_20: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_wr_en,
      O => cfg_mgmt_wr_en_n
    );
pcie_block_i_i_21: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_wr_readonly,
      O => cfg_mgmt_wr_readonly_n
    );
pcie_block_i_i_22: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_wr_rw1c_as_rw,
      O => cfg_mgmt_wr_rw1c_as_rw_n
    );
pcie_block_i_i_23: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_pm_force_state_en,
      O => cfg_pm_force_state_en_n
    );
pcie_block_i_i_24: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_pm_halt_aspm_l0s,
      O => cfg_pm_halt_aspm_l0s_n
    );
pcie_block_i_i_25: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_pm_halt_aspm_l1,
      O => cfg_pm_halt_aspm_l1_n
    );
pcie_block_i_i_27: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_pm_wake,
      O => cfg_pm_wake_n
    );
pcie_block_i_i_28: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_trn_pending,
      O => cfg_trn_pending_n
    );
pcie_block_i_i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_cpl_abort,
      O => cfg_err_cpl_abort_n
    );
pcie_block_i_i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_cpl_timeout,
      O => cfg_err_cpl_timeout_n
    );
pcie_block_i_i_5: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_cpl_unexpect,
      O => cfg_err_cpl_unexpect_n
    );
pcie_block_i_i_6: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_ecrc,
      O => cfg_err_ecrc_n
    );
pcie_block_i_i_7: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_internal_cor,
      O => cfg_err_internal_cor_n
    );
pcie_block_i_i_8: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_internal_uncor,
      O => cfg_err_internal_uncor_n
    );
pcie_block_i_i_9: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_locked,
      O => cfg_err_locked_n
    );
pcie_bram_top: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_top_7x
     port map (
      MIMRXRADDR(10 downto 0) => mim_rx_raddr(10 downto 0),
      MIMRXWADDR(10 downto 0) => mim_rx_waddr(10 downto 0),
      MIMTXRADDR(10 downto 0) => mim_tx_raddr(10 downto 0),
      MIMTXWADDR(10 downto 0) => mim_tx_waddr(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(67 downto 0) => mim_rx_wdata(67 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl\(67) => pcie_bram_top_n_69,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(66) => pcie_bram_top_n_70,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(65) => pcie_bram_top_n_71,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(64) => pcie_bram_top_n_72,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(63) => pcie_bram_top_n_73,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(62) => pcie_bram_top_n_74,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(61) => pcie_bram_top_n_75,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(60) => pcie_bram_top_n_76,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(59) => pcie_bram_top_n_77,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(58) => pcie_bram_top_n_78,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(57) => pcie_bram_top_n_79,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(56) => pcie_bram_top_n_80,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(55) => pcie_bram_top_n_81,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(54) => pcie_bram_top_n_82,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(53) => pcie_bram_top_n_83,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(52) => pcie_bram_top_n_84,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(51) => pcie_bram_top_n_85,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(50) => pcie_bram_top_n_86,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(49) => pcie_bram_top_n_87,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(48) => pcie_bram_top_n_88,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(47) => pcie_bram_top_n_89,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(46) => pcie_bram_top_n_90,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(45) => pcie_bram_top_n_91,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(44) => pcie_bram_top_n_92,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(43) => pcie_bram_top_n_93,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(42) => pcie_bram_top_n_94,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(41) => pcie_bram_top_n_95,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(40) => pcie_bram_top_n_96,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(39) => pcie_bram_top_n_97,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(38) => pcie_bram_top_n_98,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(37) => pcie_bram_top_n_99,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(36) => pcie_bram_top_n_100,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(35) => pcie_bram_top_n_101,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(34) => pcie_bram_top_n_102,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(33) => pcie_bram_top_n_103,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(32) => pcie_bram_top_n_104,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(31) => pcie_bram_top_n_105,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(30) => pcie_bram_top_n_106,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(29) => pcie_bram_top_n_107,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(28) => pcie_bram_top_n_108,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(27) => pcie_bram_top_n_109,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(26) => pcie_bram_top_n_110,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(25) => pcie_bram_top_n_111,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(24) => pcie_bram_top_n_112,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(23) => pcie_bram_top_n_113,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(22) => pcie_bram_top_n_114,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(21) => pcie_bram_top_n_115,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(20) => pcie_bram_top_n_116,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(19) => pcie_bram_top_n_117,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(18) => pcie_bram_top_n_118,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(17) => pcie_bram_top_n_119,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(16) => pcie_bram_top_n_120,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(15) => pcie_bram_top_n_121,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(14) => pcie_bram_top_n_122,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(13) => pcie_bram_top_n_123,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(12) => pcie_bram_top_n_124,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(11) => pcie_bram_top_n_125,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(10) => pcie_bram_top_n_126,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(9) => pcie_bram_top_n_127,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(8) => pcie_bram_top_n_128,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(7) => pcie_bram_top_n_129,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(6) => pcie_bram_top_n_130,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(5) => pcie_bram_top_n_131,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(4) => pcie_bram_top_n_132,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(3) => pcie_bram_top_n_133,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(2) => pcie_bram_top_n_134,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1) => pcie_bram_top_n_135,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(0) => pcie_bram_top_n_136,
      rdata(68) => pcie_bram_top_n_0,
      rdata(67) => pcie_bram_top_n_1,
      rdata(66) => pcie_bram_top_n_2,
      rdata(65) => pcie_bram_top_n_3,
      rdata(64) => pcie_bram_top_n_4,
      rdata(63) => pcie_bram_top_n_5,
      rdata(62) => pcie_bram_top_n_6,
      rdata(61) => pcie_bram_top_n_7,
      rdata(60) => pcie_bram_top_n_8,
      rdata(59) => pcie_bram_top_n_9,
      rdata(58) => pcie_bram_top_n_10,
      rdata(57) => pcie_bram_top_n_11,
      rdata(56) => pcie_bram_top_n_12,
      rdata(55) => pcie_bram_top_n_13,
      rdata(54) => pcie_bram_top_n_14,
      rdata(53) => pcie_bram_top_n_15,
      rdata(52) => pcie_bram_top_n_16,
      rdata(51) => pcie_bram_top_n_17,
      rdata(50) => pcie_bram_top_n_18,
      rdata(49) => pcie_bram_top_n_19,
      rdata(48) => pcie_bram_top_n_20,
      rdata(47) => pcie_bram_top_n_21,
      rdata(46) => pcie_bram_top_n_22,
      rdata(45) => pcie_bram_top_n_23,
      rdata(44) => pcie_bram_top_n_24,
      rdata(43) => pcie_bram_top_n_25,
      rdata(42) => pcie_bram_top_n_26,
      rdata(41) => pcie_bram_top_n_27,
      rdata(40) => pcie_bram_top_n_28,
      rdata(39) => pcie_bram_top_n_29,
      rdata(38) => pcie_bram_top_n_30,
      rdata(37) => pcie_bram_top_n_31,
      rdata(36) => pcie_bram_top_n_32,
      rdata(35) => pcie_bram_top_n_33,
      rdata(34) => pcie_bram_top_n_34,
      rdata(33) => pcie_bram_top_n_35,
      rdata(32) => pcie_bram_top_n_36,
      rdata(31) => pcie_bram_top_n_37,
      rdata(30) => pcie_bram_top_n_38,
      rdata(29) => pcie_bram_top_n_39,
      rdata(28) => pcie_bram_top_n_40,
      rdata(27) => pcie_bram_top_n_41,
      rdata(26) => pcie_bram_top_n_42,
      rdata(25) => pcie_bram_top_n_43,
      rdata(24) => pcie_bram_top_n_44,
      rdata(23) => pcie_bram_top_n_45,
      rdata(22) => pcie_bram_top_n_46,
      rdata(21) => pcie_bram_top_n_47,
      rdata(20) => pcie_bram_top_n_48,
      rdata(19) => pcie_bram_top_n_49,
      rdata(18) => pcie_bram_top_n_50,
      rdata(17) => pcie_bram_top_n_51,
      rdata(16) => pcie_bram_top_n_52,
      rdata(15) => pcie_bram_top_n_53,
      rdata(14) => pcie_bram_top_n_54,
      rdata(13) => pcie_bram_top_n_55,
      rdata(12) => pcie_bram_top_n_56,
      rdata(11) => pcie_bram_top_n_57,
      rdata(10) => pcie_bram_top_n_58,
      rdata(9) => pcie_bram_top_n_59,
      rdata(8) => pcie_bram_top_n_60,
      rdata(7) => pcie_bram_top_n_61,
      rdata(6) => pcie_bram_top_n_62,
      rdata(5) => pcie_bram_top_n_63,
      rdata(4) => pcie_bram_top_n_64,
      rdata(3) => pcie_bram_top_n_65,
      rdata(2) => pcie_bram_top_n_66,
      rdata(1) => pcie_bram_top_n_67,
      rdata(0) => pcie_bram_top_n_68,
      user_clk => user_clk,
      wdata(68 downto 0) => mim_tx_wdata(68 downto 0)
    );
pl_phy_lnk_up_q_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pl_phy_lnk_up_n,
      O => pl_phy_lnk_up_q_reg
    );
ppm_L1_thrtl_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => user_reset_out_reg,
      I1 => \^cfg_pcie_link_state\(1),
      I2 => \^cfg_pcie_link_state\(2),
      I3 => \^cfg_pcie_link_state\(0),
      O => ppm_L1_thrtl_reg
    );
reg_dsc_detect_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rdst_rdy,
      I1 => \^trn_reof\,
      I2 => \^trn_rsof\,
      O => reg_dsc_detect_reg
    );
tbuf_av_gap_thrtl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => tbuf_av_gap_thrtl_i_6_n_0,
      I1 => \^trn_tbuf_av\(0),
      I2 => \tbuf_av_d_reg[4]\,
      I3 => \^trn_tbuf_av\(3),
      I4 => \^trn_tbuf_av\(2),
      I5 => \^trn_tbuf_av\(4),
      O => \^tbuf_av_gap_thrtl_reg_0\
    );
tbuf_av_gap_thrtl_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF8"
    )
        port map (
      I0 => \^trn_tbuf_av\(0),
      I1 => \^trn_tbuf_av\(1),
      I2 => tbuf_av_gap_thrtl_i_8_n_0,
      I3 => \^trn_tbuf_av\(3),
      I4 => \^trn_tbuf_av\(2),
      I5 => \^trn_tbuf_av\(4),
      O => \^tbuf_av_gap_thrtl_reg\
    );
tbuf_av_gap_thrtl_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^trn_tbuf_av\(1),
      I1 => \^trn_tbuf_av\(5),
      O => tbuf_av_gap_thrtl_i_6_n_0
    );
tbuf_av_gap_thrtl_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BFFF"
    )
        port map (
      I0 => \^trn_tbuf_av\(5),
      I1 => tready_thrtl_xhdl1_reg_1,
      I2 => s_axis_tx_tvalid,
      I3 => s_axis_tx_tlast,
      O => tbuf_av_gap_thrtl_i_8_n_0
    );
tbuf_av_min_thrtl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^trn_tbuf_av\(5),
      I1 => \^trn_tbuf_av\(4),
      I2 => \^trn_tbuf_av\(3),
      I3 => \^trn_tbuf_av\(1),
      I4 => \^trn_tbuf_av\(2),
      O => tbuf_av_min_trig
    );
tready_thrtl_xhdl1_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \^tbuf_av_gap_thrtl_reg_0\,
      I1 => \tcfg_req_cnt_reg[1]\,
      I2 => \^tbuf_av_gap_thrtl_reg\,
      O => tready_thrtl_xhdl1_reg_0
    );
tready_thrtl_xhdl1_i_8: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^trn_tbuf_av\(2),
      I1 => \^trn_tbuf_av\(1),
      I2 => \^trn_tbuf_av\(3),
      I3 => \^trn_tbuf_av\(4),
      I4 => \^trn_tbuf_av\(5),
      O => tready_thrtl_xhdl1_reg
    );
trn_in_packet_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFDF00100010"
    )
        port map (
      I0 => user_reset_out_reg,
      I1 => trn_in_packet_i_2_n_0,
      I2 => trn_rsrc_rdy,
      I3 => \trn_in_packet_i_3__0_n_0\,
      I4 => trn_in_packet_i_4_n_0,
      I5 => trn_in_packet_reg_0,
      O => trn_in_packet_reg
    );
trn_in_packet_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \^trn_rsof\,
      I1 => \^trn_reof\,
      I2 => trn_rdst_rdy,
      O => trn_in_packet_i_2_n_0
    );
\trn_in_packet_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"45"
    )
        port map (
      I0 => trn_in_packet_reg_0,
      I1 => \^trn_rsrc_dsc\,
      I2 => \^trn_rsof\,
      O => \trn_in_packet_i_3__0_n_0\
    );
trn_in_packet_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF4000"
    )
        port map (
      I0 => \^trn_rsof\,
      I1 => trn_rsrc_rdy,
      I2 => \^trn_reof\,
      I3 => trn_rdst_rdy,
      I4 => \^trn_rsrc_dsc\,
      I5 => user_reset_out_reg,
      O => trn_in_packet_i_4_n_0
    );
trn_rsrc_rdy_prev_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => trn_rsrc_rdy,
      I1 => \^trn_rsof\,
      I2 => \^trn_rsrc_dsc\,
      I3 => trn_in_packet_reg_0,
      O => rsrc_rdy_filtered10_out
    );
user_reset_int_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => bridge_reset_int,
      I1 => pl_phy_lnk_up,
      I2 => user_rst_n,
      O => user_reset_int_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie_top is
  port (
    m_axis_rx_tvalid : out STD_LOGIC;
    m_axis_rx_tlast : out STD_LOGIC;
    trn_tcfg_req : out STD_LOGIC;
    s_axis_tx_tready : out STD_LOGIC;
    pipe_tx_rcvr_det : out STD_LOGIC;
    \rate_reg1_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_TXDEEMPH : out STD_LOGIC_VECTOR ( 3 downto 0 );
    PIPE_RXPOLARITY : out STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_TXCOMPLIANCE : out STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_TXELECIDLE : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \cplllock_reg1_reg[3]\ : out STD_LOGIC;
    \cplllock_reg1_reg[2]\ : out STD_LOGIC;
    \cplllock_reg1_reg[6]\ : out STD_LOGIC;
    user_reset_int_reg : out STD_LOGIC;
    trn_tbuf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    cfg_msg_received : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    pl_phy_lnk_up_q_reg : out STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    cfg_to_turnoff : out STD_LOGIC;
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \cplllock_reg1_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TXMARGIN : out STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXMARGIN : out STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_TXDATAK : out STD_LOGIC_VECTOR ( 15 downto 0 );
    PIPE_TXDATA : out STD_LOGIC_VECTOR ( 127 downto 0 );
    PIPE_POWERDOWN : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_command : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 14 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_lcommand : out STD_LOGIC_VECTOR ( 10 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_msg_received_assert_int_a : out STD_LOGIC;
    cfg_msg_received_assert_int_b : out STD_LOGIC;
    cfg_msg_received_assert_int_c : out STD_LOGIC;
    cfg_msg_received_assert_int_d : out STD_LOGIC;
    cfg_msg_received_deassert_int_a : out STD_LOGIC;
    cfg_msg_received_deassert_int_b : out STD_LOGIC;
    cfg_msg_received_deassert_int_c : out STD_LOGIC;
    cfg_msg_received_deassert_int_d : out STD_LOGIC;
    cfg_msg_received_err_cor : out STD_LOGIC;
    cfg_msg_received_err_fatal : out STD_LOGIC;
    cfg_msg_received_err_non_fatal : out STD_LOGIC;
    cfg_msg_received_pm_as_nak : out STD_LOGIC;
    cfg_msg_received_pme_to_ack : out STD_LOGIC;
    cfg_msg_received_pm_pme : out STD_LOGIC;
    cfg_msg_received_setslotpowerlimit : out STD_LOGIC;
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    pcie_drp_rdy : out STD_LOGIC;
    pl_directed_change_done : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    trn_lnk_up : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    user_reset_out_reg : in STD_LOGIC;
    user_clk : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_cfg_gnt : in STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    phy_rdy_n : in STD_LOGIC;
    CLK : in STD_LOGIC;
    pipe_rx0_valid : in STD_LOGIC;
    PIPE_RXCHANISALIGNED : in STD_LOGIC_VECTOR ( 7 downto 0 );
    gt_rx_phy_status_q : in STD_LOGIC;
    gt_rxelecidle_q : in STD_LOGIC;
    pipe_rx1_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg : in STD_LOGIC;
    gt_rxelecidle_q_reg : in STD_LOGIC;
    pipe_rx2_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_0 : in STD_LOGIC;
    gt_rxelecidle_q_reg_0 : in STD_LOGIC;
    pipe_rx3_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_1 : in STD_LOGIC;
    gt_rxelecidle_q_reg_1 : in STD_LOGIC;
    pipe_rx4_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_2 : in STD_LOGIC;
    gt_rxelecidle_q_reg_2 : in STD_LOGIC;
    pipe_rx5_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_3 : in STD_LOGIC;
    gt_rxelecidle_q_reg_3 : in STD_LOGIC;
    pipe_rx6_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_4 : in STD_LOGIC;
    gt_rxelecidle_q_reg_4 : in STD_LOGIC;
    pipe_rx7_valid : in STD_LOGIC;
    gt_rx_phy_status_q_reg_5 : in STD_LOGIC;
    gt_rxelecidle_q_reg_5 : in STD_LOGIC;
    bridge_reset_int : in STD_LOGIC;
    pl_phy_lnk_up : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    user_lnk_up_int_reg : in STD_LOGIC;
    cfg_trn_pending : in STD_LOGIC;
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_wake : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_1\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_2\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_3\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_4\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_4\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_5\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_5\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rxcharisk_q_reg[1]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rxdata_q_reg[15]_6\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rx_status_q_reg[2]_6\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pcie_drp_clk : in STD_LOGIC;
    pcie_drp_en : in STD_LOGIC;
    pcie_drp_we : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_directed_link_speed : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie_top : entity is "PCIeGen1x8If64_pcie_top";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie_top;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie_top is
  signal axi_basic_top_i_n_7 : STD_LOGIC;
  signal axi_basic_top_i_n_8 : STD_LOGIC;
  signal axi_basic_top_i_n_9 : STD_LOGIC;
  signal \^cfg_msg_data\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^cfg_pcie_link_state\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal cfg_pm_turnoff_ok_n : STD_LOGIC;
  signal \^cfg_to_turnoff\ : STD_LOGIC;
  signal pcie_7x_i_n_11 : STD_LOGIC;
  signal pcie_7x_i_n_12 : STD_LOGIC;
  signal pcie_7x_i_n_14 : STD_LOGIC;
  signal pcie_7x_i_n_19 : STD_LOGIC;
  signal pcie_7x_i_n_23 : STD_LOGIC;
  signal pcie_7x_i_n_25 : STD_LOGIC;
  signal pcie_7x_i_n_26 : STD_LOGIC;
  signal pcie_7x_i_n_3 : STD_LOGIC;
  signal pipe_rx0_chanisaligned_o : STD_LOGIC;
  signal pipe_rx0_char_is_k_o : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx0_data_o : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx0_elec_idle_o : STD_LOGIC;
  signal pipe_rx0_phy_status_o : STD_LOGIC;
  signal pipe_rx0_polarity_i : STD_LOGIC;
  signal pipe_rx0_status_o : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx0_valid_o : STD_LOGIC;
  signal pipe_rx1_chanisaligned_o : STD_LOGIC;
  signal pipe_rx1_char_is_k_o : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx1_data_o : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx1_elec_idle_o : STD_LOGIC;
  signal pipe_rx1_phy_status_o : STD_LOGIC;
  signal pipe_rx1_polarity_i : STD_LOGIC;
  signal pipe_rx1_status_o : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx1_valid_o : STD_LOGIC;
  signal pipe_rx2_chanisaligned_o : STD_LOGIC;
  signal pipe_rx2_char_is_k_o : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx2_data_o : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx2_elec_idle_o : STD_LOGIC;
  signal pipe_rx2_phy_status_o : STD_LOGIC;
  signal pipe_rx2_polarity_i : STD_LOGIC;
  signal pipe_rx2_status_o : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx2_valid_o : STD_LOGIC;
  signal pipe_rx3_chanisaligned_o : STD_LOGIC;
  signal pipe_rx3_char_is_k_o : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx3_data_o : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx3_elec_idle_o : STD_LOGIC;
  signal pipe_rx3_phy_status_o : STD_LOGIC;
  signal pipe_rx3_polarity_i : STD_LOGIC;
  signal pipe_rx3_status_o : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx3_valid_o : STD_LOGIC;
  signal pipe_rx4_chanisaligned_o : STD_LOGIC;
  signal pipe_rx4_char_is_k_o : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx4_data_o : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx4_elec_idle_o : STD_LOGIC;
  signal pipe_rx4_phy_status_o : STD_LOGIC;
  signal pipe_rx4_polarity_i : STD_LOGIC;
  signal pipe_rx4_status_o : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx4_valid_o : STD_LOGIC;
  signal pipe_rx5_chanisaligned_o : STD_LOGIC;
  signal pipe_rx5_char_is_k_o : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx5_data_o : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx5_elec_idle_o : STD_LOGIC;
  signal pipe_rx5_phy_status_o : STD_LOGIC;
  signal pipe_rx5_polarity_i : STD_LOGIC;
  signal pipe_rx5_status_o : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx5_valid_o : STD_LOGIC;
  signal pipe_rx6_chanisaligned_o : STD_LOGIC;
  signal pipe_rx6_char_is_k_o : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx6_data_o : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx6_elec_idle_o : STD_LOGIC;
  signal pipe_rx6_phy_status_o : STD_LOGIC;
  signal pipe_rx6_polarity_i : STD_LOGIC;
  signal pipe_rx6_status_o : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx6_valid_o : STD_LOGIC;
  signal pipe_rx7_chanisaligned_o : STD_LOGIC;
  signal pipe_rx7_char_is_k_o : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx7_data_o : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx7_elec_idle_o : STD_LOGIC;
  signal pipe_rx7_phy_status_o : STD_LOGIC;
  signal pipe_rx7_polarity_i : STD_LOGIC;
  signal pipe_rx7_status_o : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx7_valid_o : STD_LOGIC;
  signal pipe_tx0_char_is_k_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx0_compliance_i : STD_LOGIC;
  signal pipe_tx0_data_i : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx0_elec_idle_i : STD_LOGIC;
  signal pipe_tx0_powerdown_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx1_char_is_k_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx1_compliance_i : STD_LOGIC;
  signal pipe_tx1_data_i : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx1_elec_idle_i : STD_LOGIC;
  signal pipe_tx1_powerdown_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx2_char_is_k_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx2_compliance_i : STD_LOGIC;
  signal pipe_tx2_data_i : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx2_elec_idle_i : STD_LOGIC;
  signal pipe_tx2_powerdown_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx3_char_is_k_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx3_compliance_i : STD_LOGIC;
  signal pipe_tx3_data_i : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx3_elec_idle_i : STD_LOGIC;
  signal pipe_tx3_powerdown_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx4_char_is_k_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx4_compliance_i : STD_LOGIC;
  signal pipe_tx4_data_i : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx4_elec_idle_i : STD_LOGIC;
  signal pipe_tx4_powerdown_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx5_char_is_k_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx5_compliance_i : STD_LOGIC;
  signal pipe_tx5_data_i : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx5_elec_idle_i : STD_LOGIC;
  signal pipe_tx5_powerdown_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx6_char_is_k_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx6_compliance_i : STD_LOGIC;
  signal pipe_tx6_data_i : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx6_elec_idle_i : STD_LOGIC;
  signal pipe_tx6_powerdown_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx7_char_is_k_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx7_compliance_i : STD_LOGIC;
  signal pipe_tx7_data_i : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx7_elec_idle_i : STD_LOGIC;
  signal pipe_tx7_powerdown_i : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx_deemph_i : STD_LOGIC;
  signal pipe_tx_margin_i : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_tx_rate_i : STD_LOGIC;
  signal pipe_tx_rcvr_det_i : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered10_out\ : STD_LOGIC;
  signal \^s_axis_tx_tready\ : STD_LOGIC;
  signal trn_rbar_hit : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal trn_rd : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal trn_rdst_rdy : STD_LOGIC;
  signal trn_recrc_err : STD_LOGIC;
  signal trn_reof : STD_LOGIC;
  signal trn_rerrfwd : STD_LOGIC;
  signal trn_rrem : STD_LOGIC;
  signal trn_rsof : STD_LOGIC;
  signal trn_rsrc_dsc : STD_LOGIC;
  signal \^trn_tbuf_av\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal trn_tcfg_gnt : STD_LOGIC;
  signal \^trn_tcfg_req\ : STD_LOGIC;
  signal trn_td : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal trn_tdst_rdy : STD_LOGIC;
  signal trn_tecrc_gen : STD_LOGIC;
  signal trn_teof : STD_LOGIC;
  signal trn_terrfwd : STD_LOGIC;
  signal trn_trem : STD_LOGIC;
  signal trn_tsof : STD_LOGIC;
  signal trn_tsrc_dsc : STD_LOGIC;
  signal trn_tsrc_rdy : STD_LOGIC;
  signal trn_tstr : STD_LOGIC;
  signal \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\ : STD_LOGIC;
  signal \tx_inst/xhdl12.tx_thrl_ctl_inst/tbuf_av_min_trig\ : STD_LOGIC;
begin
  cfg_msg_data(15 downto 0) <= \^cfg_msg_data\(15 downto 0);
  cfg_pcie_link_state(2 downto 0) <= \^cfg_pcie_link_state\(2 downto 0);
  cfg_to_turnoff <= \^cfg_to_turnoff\;
  s_axis_tx_tready <= \^s_axis_tx_tready\;
  trn_tbuf_av(5 downto 0) <= \^trn_tbuf_av\(5 downto 0);
  trn_tcfg_req <= \^trn_tcfg_req\;
axi_basic_top_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_top
     port map (
      Q(63 downto 32) => trn_td(31 downto 0),
      Q(31 downto 0) => trn_td(63 downto 32),
      cfg_pcie_link_state(2 downto 0) => \^cfg_pcie_link_state\(2 downto 0),
      cfg_pm_turnoff_ok_n => cfg_pm_turnoff_ok_n,
      cfg_to_turnoff => \^cfg_to_turnoff\,
      cfg_turnoff_ok => cfg_turnoff_ok,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(7 downto 0) => m_axis_rx_tkeep(7 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(21 downto 0) => m_axis_rx_tuser(21 downto 0),
      m_axis_rx_tvalid => m_axis_rx_tvalid,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\ => pcie_7x_i_n_11,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\ => pcie_7x_i_n_14,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\ => pcie_7x_i_n_3,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(3) => trn_tsrc_dsc,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(2) => trn_tstr,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1) => trn_terrfwd,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(0) => trn_tecrc_gen,
      rsrc_rdy_filtered10_out => \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered10_out\,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => \^s_axis_tx_tready\,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      tbuf_av_gap_thrtl_reg => axi_basic_top_i_n_8,
      tbuf_av_gap_thrtl_reg_0 => axi_basic_top_i_n_9,
      tbuf_av_min_trig => \tx_inst/xhdl12.tx_thrl_ctl_inst/tbuf_av_min_trig\,
      \tcfg_req_cnt_reg[1]\ => pcie_7x_i_n_25,
      trn_in_packet_reg => axi_basic_top_i_n_7,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_rdst_rdy => trn_rdst_rdy,
      trn_rdst_rdy_xhdl4_reg => pcie_7x_i_n_12,
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem,
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      trn_tbuf_av(5 downto 0) => \^trn_tbuf_av\(5 downto 0),
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => \^trn_tcfg_req\,
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem,
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy,
      tx_cfg_gnt => tx_cfg_gnt,
      user_clk => user_clk,
      user_lnk_up_int_reg => user_lnk_up_int_reg,
      user_reset_out_reg => user_reset_out_reg,
      user_reset_out_reg_0 => pcie_7x_i_n_23,
      user_reset_out_reg_1 => pcie_7x_i_n_26
    );
\cfg_bus_number_d[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => user_lnk_up_int_reg,
      O => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(8),
      Q => cfg_bus_number(0),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(9),
      Q => cfg_bus_number(1),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(10),
      Q => cfg_bus_number(2),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(11),
      Q => cfg_bus_number(3),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(12),
      Q => cfg_bus_number(4),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(13),
      Q => cfg_bus_number(5),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(14),
      Q => cfg_bus_number(6),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(15),
      Q => cfg_bus_number(7),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_device_number_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(3),
      Q => cfg_device_number(0),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_device_number_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(4),
      Q => cfg_device_number(1),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_device_number_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(5),
      Q => cfg_device_number(2),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_device_number_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(6),
      Q => cfg_device_number(3),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_device_number_d_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(7),
      Q => cfg_device_number(4),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_function_number_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(0),
      Q => cfg_function_number(0),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_function_number_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(1),
      Q => cfg_function_number(1),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_function_number_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => user_clk,
      CE => pcie_7x_i_n_19,
      D => \^cfg_msg_data\(2),
      Q => cfg_function_number(2),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
pcie_7x_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_7x
     port map (
      CLK => CLK,
      E(0) => pcie_7x_i_n_19,
      Q(15 downto 0) => pipe_rx0_data_o(15 downto 0),
      bridge_reset_int => bridge_reset_int,
      cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en,
      cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en,
      cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0),
      cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received,
      cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en,
      cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received,
      cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en,
      cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received,
      cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en,
      cfg_bridge_serr_en => cfg_bridge_serr_en,
      cfg_command(4 downto 0) => cfg_command(4 downto 0),
      cfg_dcommand(14 downto 0) => cfg_dcommand(14 downto 0),
      cfg_dcommand2(11 downto 0) => cfg_dcommand2(11 downto 0),
      cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0),
      cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0),
      cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0),
      cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0),
      cfg_dstatus(3 downto 0) => cfg_dstatus(3 downto 0),
      cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0),
      cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set,
      cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked,
      cfg_err_cor => cfg_err_cor,
      cfg_err_cpl_abort => cfg_err_cpl_abort,
      cfg_err_cpl_rdy => cfg_err_cpl_rdy,
      cfg_err_cpl_timeout => cfg_err_cpl_timeout,
      cfg_err_cpl_unexpect => cfg_err_cpl_unexpect,
      cfg_err_ecrc => cfg_err_ecrc,
      cfg_err_internal_cor => cfg_err_internal_cor,
      cfg_err_internal_uncor => cfg_err_internal_uncor,
      cfg_err_locked => cfg_err_locked,
      cfg_err_malformed => cfg_err_malformed,
      cfg_err_mc_blocked => cfg_err_mc_blocked,
      cfg_err_norecovery => cfg_err_norecovery,
      cfg_err_poisoned => cfg_err_poisoned,
      cfg_err_posted => cfg_err_posted,
      cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0),
      cfg_err_ur => cfg_err_ur,
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0),
      cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_msixenable => cfg_interrupt_msixenable,
      cfg_interrupt_msixfm => cfg_interrupt_msixfm,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_interrupt_stat => cfg_interrupt_stat,
      cfg_lcommand(10 downto 0) => cfg_lcommand(10 downto 0),
      cfg_lstatus(9 downto 0) => cfg_lstatus(9 downto 0),
      cfg_mgmt_byte_en_n(3 downto 0) => cfg_mgmt_byte_en_n(3 downto 0),
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw,
      cfg_msg_data(15 downto 0) => \^cfg_msg_data\(15 downto 0),
      cfg_msg_received => cfg_msg_received,
      cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a,
      cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b,
      cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c,
      cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d,
      cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a,
      cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b,
      cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c,
      cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d,
      cfg_msg_received_err_cor => cfg_msg_received_err_cor,
      cfg_msg_received_err_fatal => cfg_msg_received_err_fatal,
      cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal,
      cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak,
      cfg_msg_received_pm_pme => cfg_msg_received_pm_pme,
      cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack,
      cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit,
      cfg_pcie_link_state(2 downto 0) => \^cfg_pcie_link_state\(2 downto 0),
      cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0),
      cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0),
      cfg_pm_force_state_en => cfg_pm_force_state_en,
      cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s,
      cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1,
      cfg_pm_turnoff_ok_n => cfg_pm_turnoff_ok_n,
      cfg_pm_wake => cfg_pm_wake,
      cfg_pmcsr_pme_en => cfg_pmcsr_pme_en,
      cfg_pmcsr_pme_status => cfg_pmcsr_pme_status,
      cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0),
      cfg_received_func_lvl_rst => cfg_received_func_lvl_rst,
      cfg_root_control_pme_int_en => cfg_root_control_pme_int_en,
      cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en,
      cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en,
      cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en,
      cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse,
      cfg_to_turnoff => \^cfg_to_turnoff\,
      cfg_trn_pending => cfg_trn_pending,
      cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0),
      fc_cpld(11 downto 0) => fc_cpld(11 downto 0),
      fc_cplh(7 downto 0) => fc_cplh(7 downto 0),
      fc_npd(11 downto 0) => fc_npd(11 downto 0),
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_pd(11 downto 0) => fc_pd(11 downto 0),
      fc_ph(7 downto 0) => fc_ph(7 downto 0),
      fc_sel(2 downto 0) => fc_sel(2 downto 0),
      pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0),
      pcie_drp_clk => pcie_drp_clk,
      pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0),
      pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0),
      pcie_drp_en => pcie_drp_en,
      pcie_drp_rdy => pcie_drp_rdy,
      pcie_drp_we => pcie_drp_we,
      pipe_rx0_chanisaligned => pipe_rx0_chanisaligned_o,
      pipe_rx0_elec_idle => pipe_rx0_elec_idle_o,
      pipe_rx0_phy_status => pipe_rx0_phy_status_o,
      pipe_rx0_polarity => pipe_rx0_polarity_i,
      pipe_rx0_valid => pipe_rx0_valid_o,
      pipe_rx1_chanisaligned => pipe_rx1_chanisaligned_o,
      pipe_rx1_elec_idle => pipe_rx1_elec_idle_o,
      pipe_rx1_phy_status => pipe_rx1_phy_status_o,
      pipe_rx1_polarity => pipe_rx1_polarity_i,
      pipe_rx1_valid => pipe_rx1_valid_o,
      pipe_rx2_chanisaligned => pipe_rx2_chanisaligned_o,
      pipe_rx2_elec_idle => pipe_rx2_elec_idle_o,
      pipe_rx2_phy_status => pipe_rx2_phy_status_o,
      pipe_rx2_polarity => pipe_rx2_polarity_i,
      pipe_rx2_valid => pipe_rx2_valid_o,
      pipe_rx3_chanisaligned => pipe_rx3_chanisaligned_o,
      pipe_rx3_elec_idle => pipe_rx3_elec_idle_o,
      pipe_rx3_phy_status => pipe_rx3_phy_status_o,
      pipe_rx3_polarity => pipe_rx3_polarity_i,
      pipe_rx3_valid => pipe_rx3_valid_o,
      pipe_rx4_chanisaligned => pipe_rx4_chanisaligned_o,
      pipe_rx4_elec_idle => pipe_rx4_elec_idle_o,
      pipe_rx4_phy_status => pipe_rx4_phy_status_o,
      pipe_rx4_polarity => pipe_rx4_polarity_i,
      pipe_rx4_valid => pipe_rx4_valid_o,
      pipe_rx5_chanisaligned => pipe_rx5_chanisaligned_o,
      pipe_rx5_elec_idle => pipe_rx5_elec_idle_o,
      pipe_rx5_phy_status => pipe_rx5_phy_status_o,
      pipe_rx5_polarity => pipe_rx5_polarity_i,
      pipe_rx5_valid => pipe_rx5_valid_o,
      pipe_rx6_chanisaligned => pipe_rx6_chanisaligned_o,
      pipe_rx6_elec_idle => pipe_rx6_elec_idle_o,
      pipe_rx6_phy_status => pipe_rx6_phy_status_o,
      pipe_rx6_polarity => pipe_rx6_polarity_i,
      pipe_rx6_valid => pipe_rx6_valid_o,
      pipe_rx7_chanisaligned => pipe_rx7_chanisaligned_o,
      pipe_rx7_elec_idle => pipe_rx7_elec_idle_o,
      pipe_rx7_phy_status => pipe_rx7_phy_status_o,
      pipe_rx7_polarity => pipe_rx7_polarity_i,
      pipe_rx7_valid => pipe_rx7_valid_o,
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => pipe_rx0_char_is_k_o(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => pipe_rx1_char_is_k_o(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0) => pipe_rx2_char_is_k_o(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2\(1 downto 0) => pipe_rx3_char_is_k_o(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3\(1 downto 0) => pipe_rx4_char_is_k_o(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4\(1 downto 0) => pipe_rx5_char_is_k_o(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5\(1 downto 0) => pipe_rx6_char_is_k_o(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_6\(1 downto 0) => pipe_rx7_char_is_k_o(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => pipe_rx1_data_o(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => pipe_rx2_data_o(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => pipe_rx3_data_o(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_2\(15 downto 0) => pipe_rx4_data_o(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_3\(15 downto 0) => pipe_rx5_data_o(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_4\(15 downto 0) => pipe_rx6_data_o(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_5\(15 downto 0) => pipe_rx7_data_o(15 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2 downto 0) => pipe_rx0_status_o(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2 downto 0) => pipe_rx1_status_o(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2 downto 0) => pipe_rx2_status_o(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(2 downto 0) => pipe_rx3_status_o(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_3\(2 downto 0) => pipe_rx4_status_o(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_4\(2 downto 0) => pipe_rx5_status_o(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_5\(2 downto 0) => pipe_rx6_status_o(2 downto 0),
      \pipe_stages_1.pipe_rx_status_q_reg[2]_6\(2 downto 0) => pipe_rx7_status_o(2 downto 0),
      pipe_tx0_char_is_k(1 downto 0) => pipe_tx0_char_is_k_i(1 downto 0),
      pipe_tx0_compliance => pipe_tx0_compliance_i,
      pipe_tx0_data(15 downto 0) => pipe_tx0_data_i(15 downto 0),
      pipe_tx0_elec_idle => pipe_tx0_elec_idle_i,
      pipe_tx0_powerdown(1 downto 0) => pipe_tx0_powerdown_i(1 downto 0),
      pipe_tx1_char_is_k(1 downto 0) => pipe_tx1_char_is_k_i(1 downto 0),
      pipe_tx1_compliance => pipe_tx1_compliance_i,
      pipe_tx1_data(15 downto 0) => pipe_tx1_data_i(15 downto 0),
      pipe_tx1_elec_idle => pipe_tx1_elec_idle_i,
      pipe_tx1_powerdown(1 downto 0) => pipe_tx1_powerdown_i(1 downto 0),
      pipe_tx2_char_is_k(1 downto 0) => pipe_tx2_char_is_k_i(1 downto 0),
      pipe_tx2_compliance => pipe_tx2_compliance_i,
      pipe_tx2_data(15 downto 0) => pipe_tx2_data_i(15 downto 0),
      pipe_tx2_elec_idle => pipe_tx2_elec_idle_i,
      pipe_tx2_powerdown(1 downto 0) => pipe_tx2_powerdown_i(1 downto 0),
      pipe_tx3_char_is_k(1 downto 0) => pipe_tx3_char_is_k_i(1 downto 0),
      pipe_tx3_compliance => pipe_tx3_compliance_i,
      pipe_tx3_data(15 downto 0) => pipe_tx3_data_i(15 downto 0),
      pipe_tx3_elec_idle => pipe_tx3_elec_idle_i,
      pipe_tx3_powerdown(1 downto 0) => pipe_tx3_powerdown_i(1 downto 0),
      pipe_tx4_char_is_k(1 downto 0) => pipe_tx4_char_is_k_i(1 downto 0),
      pipe_tx4_compliance => pipe_tx4_compliance_i,
      pipe_tx4_data(15 downto 0) => pipe_tx4_data_i(15 downto 0),
      pipe_tx4_elec_idle => pipe_tx4_elec_idle_i,
      pipe_tx4_powerdown(1 downto 0) => pipe_tx4_powerdown_i(1 downto 0),
      pipe_tx5_char_is_k(1 downto 0) => pipe_tx5_char_is_k_i(1 downto 0),
      pipe_tx5_compliance => pipe_tx5_compliance_i,
      pipe_tx5_data(15 downto 0) => pipe_tx5_data_i(15 downto 0),
      pipe_tx5_elec_idle => pipe_tx5_elec_idle_i,
      pipe_tx5_powerdown(1 downto 0) => pipe_tx5_powerdown_i(1 downto 0),
      pipe_tx6_char_is_k(1 downto 0) => pipe_tx6_char_is_k_i(1 downto 0),
      pipe_tx6_compliance => pipe_tx6_compliance_i,
      pipe_tx6_data(15 downto 0) => pipe_tx6_data_i(15 downto 0),
      pipe_tx6_elec_idle => pipe_tx6_elec_idle_i,
      pipe_tx6_powerdown(1 downto 0) => pipe_tx6_powerdown_i(1 downto 0),
      pipe_tx7_char_is_k(1 downto 0) => pipe_tx7_char_is_k_i(1 downto 0),
      pipe_tx7_compliance => pipe_tx7_compliance_i,
      pipe_tx7_data(15 downto 0) => pipe_tx7_data_i(15 downto 0),
      pipe_tx7_elec_idle => pipe_tx7_elec_idle_i,
      pipe_tx7_powerdown(1 downto 0) => pipe_tx7_powerdown_i(1 downto 0),
      pipe_tx_deemph => pipe_tx_deemph_i,
      pipe_tx_margin(2 downto 0) => pipe_tx_margin_i(2 downto 0),
      pipe_tx_rate => pipe_tx_rate_i,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det_i,
      pl_directed_change_done => pl_directed_change_done,
      pl_directed_link_auton => pl_directed_link_auton,
      pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0),
      pl_directed_link_speed => pl_directed_link_speed,
      pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0),
      pl_downstream_deemph_source => pl_downstream_deemph_source,
      pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0),
      pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0),
      pl_link_gen2_cap => pl_link_gen2_cap,
      pl_link_partner_gen2_supported => pl_link_partner_gen2_supported,
      pl_link_upcfg_cap => pl_link_upcfg_cap,
      pl_ltssm_state(5 downto 0) => pl_ltssm_state(5 downto 0),
      pl_phy_lnk_up => pl_phy_lnk_up,
      pl_phy_lnk_up_q_reg => pl_phy_lnk_up_q_reg,
      pl_received_hot_rst => pl_received_hot_rst,
      pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0),
      pl_sel_lnk_rate => pl_sel_lnk_rate,
      pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0),
      pl_transmit_hot_rst => pl_transmit_hot_rst,
      pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0),
      pl_upstream_prefer_deemph => pl_upstream_prefer_deemph,
      ppm_L1_thrtl_reg => pcie_7x_i_n_26,
      reg_dsc_detect_reg => pcie_7x_i_n_12,
      rsrc_rdy_filtered10_out => \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered10_out\,
      rx_np_ok => rx_np_ok,
      rx_np_req => rx_np_req,
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      sys_rst_n => sys_rst_n,
      \tbuf_av_d_reg[4]\ => axi_basic_top_i_n_9,
      tbuf_av_gap_thrtl_reg => pcie_7x_i_n_3,
      tbuf_av_gap_thrtl_reg_0 => pcie_7x_i_n_14,
      tbuf_av_min_trig => \tx_inst/xhdl12.tx_thrl_ctl_inst/tbuf_av_min_trig\,
      \tcfg_req_cnt_reg[1]\ => axi_basic_top_i_n_8,
      tready_thrtl_xhdl1_reg => pcie_7x_i_n_11,
      tready_thrtl_xhdl1_reg_0 => pcie_7x_i_n_25,
      tready_thrtl_xhdl1_reg_1 => \^s_axis_tx_tready\,
      trn_in_packet_reg => pcie_7x_i_n_23,
      trn_in_packet_reg_0 => axi_basic_top_i_n_7,
      trn_lnk_up => trn_lnk_up,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_rdst_rdy => trn_rdst_rdy,
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem,
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      trn_tbuf_av(5 downto 0) => \^trn_tbuf_av\(5 downto 0),
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => \^trn_tcfg_req\,
      trn_td(63 downto 0) => trn_td(63 downto 0),
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem,
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy,
      tx_err_drop => tx_err_drop,
      user_clk => user_clk,
      user_reset_int_reg => user_reset_int_reg,
      user_reset_out_reg => user_reset_out_reg,
      \xhdl12.reg_tuser_reg[3]\(3) => trn_tsrc_dsc,
      \xhdl12.reg_tuser_reg[3]\(2) => trn_tstr,
      \xhdl12.reg_tuser_reg[3]\(1) => trn_terrfwd,
      \xhdl12.reg_tuser_reg[3]\(0) => trn_tecrc_gen
    );
pcie_pipe_pipeline_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_pipeline
     port map (
      CLK => CLK,
      D(1 downto 0) => D(1 downto 0),
      PIPE_POWERDOWN(15 downto 0) => PIPE_POWERDOWN(15 downto 0),
      PIPE_RXCHANISALIGNED(7 downto 0) => PIPE_RXCHANISALIGNED(7 downto 0),
      PIPE_RXPOLARITY(7 downto 0) => PIPE_RXPOLARITY(7 downto 0),
      PIPE_TXCOMPLIANCE(7 downto 0) => PIPE_TXCOMPLIANCE(7 downto 0),
      PIPE_TXDATA(127 downto 0) => PIPE_TXDATA(127 downto 0),
      PIPE_TXDATAK(15 downto 0) => PIPE_TXDATAK(15 downto 0),
      PIPE_TXDEEMPH(3 downto 0) => PIPE_TXDEEMPH(3 downto 0),
      PIPE_TXELECIDLE(7 downto 0) => PIPE_TXELECIDLE(7 downto 0),
      PIPE_TXMARGIN(2 downto 0) => PIPE_TXMARGIN(2 downto 0),
      Q(2 downto 0) => Q(2 downto 0),
      TXMARGIN(2 downto 0) => TXMARGIN(2 downto 0),
      \cplllock_reg1_reg[2]\ => \cplllock_reg1_reg[2]\,
      \cplllock_reg1_reg[3]\ => \cplllock_reg1_reg[3]\,
      \cplllock_reg1_reg[3]_0\(2 downto 0) => \cplllock_reg1_reg[3]_0\(2 downto 0),
      \cplllock_reg1_reg[6]\ => \cplllock_reg1_reg[6]\,
      gt_rx_phy_status_q => gt_rx_phy_status_q,
      gt_rx_phy_status_q_reg => gt_rx_phy_status_q_reg,
      gt_rx_phy_status_q_reg_0 => gt_rx_phy_status_q_reg_0,
      gt_rx_phy_status_q_reg_1 => gt_rx_phy_status_q_reg_1,
      gt_rx_phy_status_q_reg_2 => gt_rx_phy_status_q_reg_2,
      gt_rx_phy_status_q_reg_3 => gt_rx_phy_status_q_reg_3,
      gt_rx_phy_status_q_reg_4 => gt_rx_phy_status_q_reg_4,
      gt_rx_phy_status_q_reg_5 => gt_rx_phy_status_q_reg_5,
      \gt_rx_status_q_reg[2]\(2 downto 0) => \gt_rx_status_q_reg[2]\(2 downto 0),
      \gt_rx_status_q_reg[2]_0\(2 downto 0) => \gt_rx_status_q_reg[2]_0\(2 downto 0),
      \gt_rx_status_q_reg[2]_1\(2 downto 0) => \gt_rx_status_q_reg[2]_1\(2 downto 0),
      \gt_rx_status_q_reg[2]_2\(2 downto 0) => \gt_rx_status_q_reg[2]_2\(2 downto 0),
      \gt_rx_status_q_reg[2]_3\(2 downto 0) => \gt_rx_status_q_reg[2]_3\(2 downto 0),
      \gt_rx_status_q_reg[2]_4\(2 downto 0) => \gt_rx_status_q_reg[2]_4\(2 downto 0),
      \gt_rx_status_q_reg[2]_5\(2 downto 0) => \gt_rx_status_q_reg[2]_5\(2 downto 0),
      \gt_rx_status_q_reg[2]_6\(2 downto 0) => \gt_rx_status_q_reg[2]_6\(2 downto 0),
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => \gt_rxcharisk_q_reg[1]\(1 downto 0),
      \gt_rxcharisk_q_reg[1]_0\(1 downto 0) => \gt_rxcharisk_q_reg[1]_0\(1 downto 0),
      \gt_rxcharisk_q_reg[1]_1\(1 downto 0) => \gt_rxcharisk_q_reg[1]_1\(1 downto 0),
      \gt_rxcharisk_q_reg[1]_2\(1 downto 0) => \gt_rxcharisk_q_reg[1]_2\(1 downto 0),
      \gt_rxcharisk_q_reg[1]_3\(1 downto 0) => \gt_rxcharisk_q_reg[1]_3\(1 downto 0),
      \gt_rxcharisk_q_reg[1]_4\(1 downto 0) => \gt_rxcharisk_q_reg[1]_4\(1 downto 0),
      \gt_rxcharisk_q_reg[1]_5\(1 downto 0) => \gt_rxcharisk_q_reg[1]_5\(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      \gt_rxdata_q_reg[15]_0\(15 downto 0) => \gt_rxdata_q_reg[15]_0\(15 downto 0),
      \gt_rxdata_q_reg[15]_1\(15 downto 0) => \gt_rxdata_q_reg[15]_1\(15 downto 0),
      \gt_rxdata_q_reg[15]_2\(15 downto 0) => \gt_rxdata_q_reg[15]_2\(15 downto 0),
      \gt_rxdata_q_reg[15]_3\(15 downto 0) => \gt_rxdata_q_reg[15]_3\(15 downto 0),
      \gt_rxdata_q_reg[15]_4\(15 downto 0) => \gt_rxdata_q_reg[15]_4\(15 downto 0),
      \gt_rxdata_q_reg[15]_5\(15 downto 0) => \gt_rxdata_q_reg[15]_5\(15 downto 0),
      \gt_rxdata_q_reg[15]_6\(15 downto 0) => \gt_rxdata_q_reg[15]_6\(15 downto 0),
      gt_rxelecidle_q => gt_rxelecidle_q,
      gt_rxelecidle_q_reg => gt_rxelecidle_q_reg,
      gt_rxelecidle_q_reg_0 => gt_rxelecidle_q_reg_0,
      gt_rxelecidle_q_reg_1 => gt_rxelecidle_q_reg_1,
      gt_rxelecidle_q_reg_2 => gt_rxelecidle_q_reg_2,
      gt_rxelecidle_q_reg_3 => gt_rxelecidle_q_reg_3,
      gt_rxelecidle_q_reg_4 => gt_rxelecidle_q_reg_4,
      gt_rxelecidle_q_reg_5 => gt_rxelecidle_q_reg_5,
      phy_rdy_n => phy_rdy_n,
      pipe_rx0_chanisaligned_o => pipe_rx0_chanisaligned_o,
      pipe_rx0_elec_idle_o => pipe_rx0_elec_idle_o,
      pipe_rx0_phy_status_o => pipe_rx0_phy_status_o,
      pipe_rx0_polarity_i => pipe_rx0_polarity_i,
      pipe_rx0_valid => pipe_rx0_valid,
      pipe_rx0_valid_o => pipe_rx0_valid_o,
      pipe_rx1_chanisaligned_o => pipe_rx1_chanisaligned_o,
      pipe_rx1_elec_idle_o => pipe_rx1_elec_idle_o,
      pipe_rx1_phy_status_o => pipe_rx1_phy_status_o,
      pipe_rx1_polarity_i => pipe_rx1_polarity_i,
      pipe_rx1_valid => pipe_rx1_valid,
      pipe_rx1_valid_o => pipe_rx1_valid_o,
      pipe_rx2_chanisaligned_o => pipe_rx2_chanisaligned_o,
      pipe_rx2_elec_idle_o => pipe_rx2_elec_idle_o,
      pipe_rx2_phy_status_o => pipe_rx2_phy_status_o,
      pipe_rx2_polarity_i => pipe_rx2_polarity_i,
      pipe_rx2_valid => pipe_rx2_valid,
      pipe_rx2_valid_o => pipe_rx2_valid_o,
      pipe_rx3_chanisaligned_o => pipe_rx3_chanisaligned_o,
      pipe_rx3_elec_idle_o => pipe_rx3_elec_idle_o,
      pipe_rx3_phy_status_o => pipe_rx3_phy_status_o,
      pipe_rx3_polarity_i => pipe_rx3_polarity_i,
      pipe_rx3_valid => pipe_rx3_valid,
      pipe_rx3_valid_o => pipe_rx3_valid_o,
      pipe_rx4_chanisaligned_o => pipe_rx4_chanisaligned_o,
      pipe_rx4_elec_idle_o => pipe_rx4_elec_idle_o,
      pipe_rx4_phy_status_o => pipe_rx4_phy_status_o,
      pipe_rx4_polarity_i => pipe_rx4_polarity_i,
      pipe_rx4_valid => pipe_rx4_valid,
      pipe_rx4_valid_o => pipe_rx4_valid_o,
      pipe_rx5_chanisaligned_o => pipe_rx5_chanisaligned_o,
      pipe_rx5_elec_idle_o => pipe_rx5_elec_idle_o,
      pipe_rx5_phy_status_o => pipe_rx5_phy_status_o,
      pipe_rx5_polarity_i => pipe_rx5_polarity_i,
      pipe_rx5_valid => pipe_rx5_valid,
      pipe_rx5_valid_o => pipe_rx5_valid_o,
      pipe_rx6_chanisaligned_o => pipe_rx6_chanisaligned_o,
      pipe_rx6_elec_idle_o => pipe_rx6_elec_idle_o,
      pipe_rx6_phy_status_o => pipe_rx6_phy_status_o,
      pipe_rx6_polarity_i => pipe_rx6_polarity_i,
      pipe_rx6_valid => pipe_rx6_valid,
      pipe_rx6_valid_o => pipe_rx6_valid_o,
      pipe_rx7_chanisaligned_o => pipe_rx7_chanisaligned_o,
      pipe_rx7_elec_idle_o => pipe_rx7_elec_idle_o,
      pipe_rx7_phy_status_o => pipe_rx7_phy_status_o,
      pipe_rx7_polarity_i => pipe_rx7_polarity_i,
      pipe_rx7_valid => pipe_rx7_valid,
      pipe_rx7_valid_o => pipe_rx7_valid_o,
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg\(1 downto 0) => pipe_tx0_char_is_k_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0\(1 downto 0) => pipe_tx1_char_is_k_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1\(1 downto 0) => pipe_tx2_char_is_k_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_10\(15 downto 0) => pipe_tx3_data_i(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_11\(15 downto 0) => pipe_tx4_data_i(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_12\(15 downto 0) => pipe_tx5_data_i(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_13\(15 downto 0) => pipe_tx6_data_i(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_14\(15 downto 0) => pipe_tx7_data_i(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_15\(1 downto 0) => pipe_tx0_powerdown_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_16\(1 downto 0) => pipe_tx1_powerdown_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_17\(1 downto 0) => pipe_tx2_powerdown_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_18\(1 downto 0) => pipe_tx3_powerdown_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_19\(1 downto 0) => pipe_tx4_powerdown_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2\(1 downto 0) => pipe_tx3_char_is_k_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_20\(1 downto 0) => pipe_tx5_powerdown_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_21\(1 downto 0) => pipe_tx6_powerdown_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_22\(1 downto 0) => pipe_tx7_powerdown_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_3\(1 downto 0) => pipe_tx4_char_is_k_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_4\(1 downto 0) => pipe_tx5_char_is_k_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_5\(1 downto 0) => pipe_tx6_char_is_k_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_6\(1 downto 0) => pipe_tx7_char_is_k_i(1 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_7\(15 downto 0) => pipe_tx0_data_i(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_8\(15 downto 0) => pipe_tx1_data_i(15 downto 0),
      \pipe_stages_1.pipe_rx_chanisaligned_q_reg_9\(15 downto 0) => pipe_tx2_data_i(15 downto 0),
      pipe_tx0_compliance_i => pipe_tx0_compliance_i,
      pipe_tx0_elec_idle_i => pipe_tx0_elec_idle_i,
      pipe_tx1_compliance_i => pipe_tx1_compliance_i,
      pipe_tx1_elec_idle_i => pipe_tx1_elec_idle_i,
      pipe_tx2_compliance_i => pipe_tx2_compliance_i,
      pipe_tx2_elec_idle_i => pipe_tx2_elec_idle_i,
      pipe_tx3_compliance_i => pipe_tx3_compliance_i,
      pipe_tx3_elec_idle_i => pipe_tx3_elec_idle_i,
      pipe_tx4_compliance_i => pipe_tx4_compliance_i,
      pipe_tx4_elec_idle_i => pipe_tx4_elec_idle_i,
      pipe_tx5_compliance_i => pipe_tx5_compliance_i,
      pipe_tx5_elec_idle_i => pipe_tx5_elec_idle_i,
      pipe_tx6_compliance_i => pipe_tx6_compliance_i,
      pipe_tx6_elec_idle_i => pipe_tx6_elec_idle_i,
      pipe_tx7_compliance_i => pipe_tx7_compliance_i,
      pipe_tx7_elec_idle_i => pipe_tx7_elec_idle_i,
      pipe_tx_deemph_i => pipe_tx_deemph_i,
      pipe_tx_margin(2 downto 0) => pipe_tx_margin_i(2 downto 0),
      pipe_tx_rate_i => pipe_tx_rate_i,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_tx_rcvr_det_i => pipe_tx_rcvr_det_i,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(1 downto 0) => pipe_rx0_char_is_k_o(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(15 downto 0) => pipe_rx0_data_o(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(2 downto 0) => pipe_rx0_status_o(2 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_10\(2 downto 0) => pipe_rx3_status_o(2 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_11\(1 downto 0) => pipe_rx4_char_is_k_o(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_12\(15 downto 0) => pipe_rx4_data_o(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_13\(2 downto 0) => pipe_rx4_status_o(2 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_14\(1 downto 0) => pipe_rx5_char_is_k_o(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_15\(15 downto 0) => pipe_rx5_data_o(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_16\(2 downto 0) => pipe_rx5_status_o(2 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_17\(1 downto 0) => pipe_rx6_char_is_k_o(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_18\(15 downto 0) => pipe_rx6_data_o(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_19\(2 downto 0) => pipe_rx6_status_o(2 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_2\(1 downto 0) => pipe_rx1_char_is_k_o(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_20\(1 downto 0) => pipe_rx7_char_is_k_o(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_21\(15 downto 0) => pipe_rx7_data_o(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_22\(2 downto 0) => pipe_rx7_status_o(2 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_3\(15 downto 0) => pipe_rx1_data_o(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_4\(2 downto 0) => pipe_rx1_status_o(2 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_5\(1 downto 0) => pipe_rx2_char_is_k_o(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_6\(15 downto 0) => pipe_rx2_data_o(15 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_7\(2 downto 0) => pipe_rx2_status_o(2 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_8\(1 downto 0) => pipe_rx3_char_is_k_o(1 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_9\(15 downto 0) => pipe_rx3_data_o(15 downto 0),
      \rate_reg1_reg[0]\(0) => \rate_reg1_reg[0]\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_core_top is
  port (
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    PIPE_SYNC_FSM_TX : out STD_LOGIC_VECTOR ( 47 downto 0 );
    PIPE_RATE_FSM : out STD_LOGIC_VECTOR ( 39 downto 0 );
    PIPE_DRP_FSM : out STD_LOGIC_VECTOR ( 23 downto 0 );
    pl_phy_lnk_up : out STD_LOGIC;
    user_reset_out : out STD_LOGIC;
    m_axis_rx_tvalid : out STD_LOGIC;
    tx_cfg_req : out STD_LOGIC;
    s_axis_tx_tready : out STD_LOGIC;
    tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    user_lnk_up : out STD_LOGIC;
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_received_hot_rst : out STD_LOGIC;
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    INT_USERCLK2_OUT : out STD_LOGIC;
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_command : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 14 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_lcommand : out STD_LOGIC_VECTOR ( 10 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_msg_received : out STD_LOGIC;
    cfg_msg_received_assert_int_a : out STD_LOGIC;
    cfg_msg_received_assert_int_b : out STD_LOGIC;
    cfg_msg_received_assert_int_c : out STD_LOGIC;
    cfg_msg_received_assert_int_d : out STD_LOGIC;
    cfg_msg_received_deassert_int_a : out STD_LOGIC;
    cfg_msg_received_deassert_int_b : out STD_LOGIC;
    cfg_msg_received_deassert_int_c : out STD_LOGIC;
    cfg_msg_received_deassert_int_d : out STD_LOGIC;
    cfg_msg_received_err_cor : out STD_LOGIC;
    cfg_msg_received_err_fatal : out STD_LOGIC;
    cfg_msg_received_err_non_fatal : out STD_LOGIC;
    cfg_msg_received_pm_as_nak : out STD_LOGIC;
    cfg_to_turnoff : out STD_LOGIC;
    cfg_msg_received_pme_to_ack : out STD_LOGIC;
    cfg_msg_received_pm_pme : out STD_LOGIC;
    cfg_msg_received_setslotpowerlimit : out STD_LOGIC;
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    pcie_drp_rdy : out STD_LOGIC;
    pl_directed_change_done : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    INT_OOBCLK_OUT : out STD_LOGIC;
    pipe_txoutclk_out : out STD_LOGIC;
    int_mmcm_lock_out : out STD_LOGIC;
    ext_ch_gt_drpclk : out STD_LOGIC;
    pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
    EQ_GEN3 : out STD_LOGIC;
    \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_cpll_lock : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_qrst_idle : out STD_LOGIC;
    int_qplllock_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 23 downto 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 55 downto 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 127 downto 0 );
    int_qplloutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 23 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 63 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 63 downto 0 );
    pipe_rate_idle : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 71 downto 0 );
    m_axis_rx_tready : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tlast : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    pcie_drp_clk : in STD_LOGIC;
    pcie_drp_en : in STD_LOGIC;
    pcie_drp_we : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_directed_link_speed : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_mmcm_rst_n : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 127 downto 0 );
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_cfg_gnt : in STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_trn_pending : in STD_LOGIC;
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_wake : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_core_top : entity is "PCIeGen1x8If64_core_top";
end PCIeGen1x8If64_PCIeGen1x8If64_core_top;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_core_top is
  signal \^int_oobclk_out\ : STD_LOGIC;
  signal \^int_userclk2_out\ : STD_LOGIC;
  signal bridge_reset_int : STD_LOGIC;
  signal cfg_mgmt_byte_en_n : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal gt_rx_phy_status_q : STD_LOGIC;
  signal gt_rxelecidle_q : STD_LOGIC;
  signal gt_top_i_n_12 : STD_LOGIC;
  signal gt_top_i_n_13 : STD_LOGIC;
  signal gt_top_i_n_14 : STD_LOGIC;
  signal gt_top_i_n_15 : STD_LOGIC;
  signal gt_top_i_n_16 : STD_LOGIC;
  signal gt_top_i_n_17 : STD_LOGIC;
  signal gt_top_i_n_18 : STD_LOGIC;
  signal gt_top_i_n_19 : STD_LOGIC;
  signal gt_top_i_n_20 : STD_LOGIC;
  signal gt_top_i_n_21 : STD_LOGIC;
  signal gt_top_i_n_22 : STD_LOGIC;
  signal gt_top_i_n_23 : STD_LOGIC;
  signal gt_top_i_n_24 : STD_LOGIC;
  signal gt_top_i_n_25 : STD_LOGIC;
  signal gt_top_i_n_296 : STD_LOGIC;
  signal gt_top_i_n_297 : STD_LOGIC;
  signal gt_top_i_n_298 : STD_LOGIC;
  signal gt_top_i_n_299 : STD_LOGIC;
  signal gt_top_i_n_300 : STD_LOGIC;
  signal gt_top_i_n_301 : STD_LOGIC;
  signal gt_top_i_n_302 : STD_LOGIC;
  signal gt_top_i_n_303 : STD_LOGIC;
  signal gt_top_i_n_304 : STD_LOGIC;
  signal gt_top_i_n_305 : STD_LOGIC;
  signal gt_top_i_n_306 : STD_LOGIC;
  signal gt_top_i_n_307 : STD_LOGIC;
  signal gt_top_i_n_308 : STD_LOGIC;
  signal gt_top_i_n_309 : STD_LOGIC;
  signal gt_top_i_n_310 : STD_LOGIC;
  signal gt_top_i_n_311 : STD_LOGIC;
  signal gt_top_i_n_312 : STD_LOGIC;
  signal gt_top_i_n_313 : STD_LOGIC;
  signal gt_top_i_n_314 : STD_LOGIC;
  signal gt_top_i_n_315 : STD_LOGIC;
  signal gt_top_i_n_316 : STD_LOGIC;
  signal gt_top_i_n_317 : STD_LOGIC;
  signal gt_top_i_n_318 : STD_LOGIC;
  signal gt_top_i_n_319 : STD_LOGIC;
  signal gt_top_i_n_874 : STD_LOGIC;
  signal pcie_top_i_n_184 : STD_LOGIC;
  signal pcie_top_i_n_185 : STD_LOGIC;
  signal pcie_top_i_n_186 : STD_LOGIC;
  signal pcie_top_i_n_187 : STD_LOGIC;
  signal pcie_top_i_n_188 : STD_LOGIC;
  signal pcie_top_i_n_189 : STD_LOGIC;
  signal pcie_top_i_n_190 : STD_LOGIC;
  signal pcie_top_i_n_191 : STD_LOGIC;
  signal pcie_top_i_n_192 : STD_LOGIC;
  signal pcie_top_i_n_34 : STD_LOGIC;
  signal pcie_top_i_n_35 : STD_LOGIC;
  signal pcie_top_i_n_36 : STD_LOGIC;
  signal pcie_top_i_n_37 : STD_LOGIC;
  signal pcie_top_i_n_449 : STD_LOGIC;
  signal pcie_top_i_n_53 : STD_LOGIC;
  signal pcie_top_i_n_6 : STD_LOGIC;
  signal pcie_top_i_n_7 : STD_LOGIC;
  signal pcie_top_i_n_8 : STD_LOGIC;
  signal phy_rdy_n : STD_LOGIC;
  signal pipe_rx0_chanisaligned : STD_LOGIC;
  signal pipe_rx0_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx0_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx0_polarity : STD_LOGIC;
  signal pipe_rx0_valid : STD_LOGIC;
  signal pipe_rx1_chanisaligned : STD_LOGIC;
  signal pipe_rx1_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx1_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx1_polarity : STD_LOGIC;
  signal pipe_rx1_valid : STD_LOGIC;
  signal pipe_rx2_chanisaligned : STD_LOGIC;
  signal pipe_rx2_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx2_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx2_polarity : STD_LOGIC;
  signal pipe_rx2_valid : STD_LOGIC;
  signal pipe_rx3_chanisaligned : STD_LOGIC;
  signal pipe_rx3_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx3_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx3_polarity : STD_LOGIC;
  signal pipe_rx3_valid : STD_LOGIC;
  signal pipe_rx4_chanisaligned : STD_LOGIC;
  signal pipe_rx4_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx4_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx4_polarity : STD_LOGIC;
  signal pipe_rx4_valid : STD_LOGIC;
  signal pipe_rx5_chanisaligned : STD_LOGIC;
  signal pipe_rx5_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx5_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx5_polarity : STD_LOGIC;
  signal pipe_rx5_valid : STD_LOGIC;
  signal pipe_rx6_chanisaligned : STD_LOGIC;
  signal pipe_rx6_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx6_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx6_polarity : STD_LOGIC;
  signal pipe_rx6_valid : STD_LOGIC;
  signal pipe_rx7_chanisaligned : STD_LOGIC;
  signal pipe_rx7_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx7_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx7_polarity : STD_LOGIC;
  signal pipe_rx7_valid : STD_LOGIC;
  signal pipe_tx0_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx0_compliance : STD_LOGIC;
  signal pipe_tx0_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx0_elec_idle : STD_LOGIC;
  signal pipe_tx0_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx1_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx1_compliance : STD_LOGIC;
  signal pipe_tx1_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx1_elec_idle : STD_LOGIC;
  signal pipe_tx1_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx2_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx2_compliance : STD_LOGIC;
  signal pipe_tx2_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx2_elec_idle : STD_LOGIC;
  signal pipe_tx2_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx3_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx3_compliance : STD_LOGIC;
  signal pipe_tx3_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx3_elec_idle : STD_LOGIC;
  signal pipe_tx3_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx4_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx4_compliance : STD_LOGIC;
  signal pipe_tx4_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx4_elec_idle : STD_LOGIC;
  signal pipe_tx4_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx5_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx5_compliance : STD_LOGIC;
  signal pipe_tx5_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx5_elec_idle : STD_LOGIC;
  signal pipe_tx5_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx6_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx6_compliance : STD_LOGIC;
  signal pipe_tx6_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx6_elec_idle : STD_LOGIC;
  signal pipe_tx6_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx7_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx7_compliance : STD_LOGIC;
  signal pipe_tx7_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx7_elec_idle : STD_LOGIC;
  signal pipe_tx7_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx_deemph : STD_LOGIC;
  signal pipe_tx_margin : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_tx_rate : STD_LOGIC;
  signal pipe_tx_rcvr_det : STD_LOGIC;
  signal \^pl_ltssm_state\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^pl_phy_lnk_up\ : STD_LOGIC;
  signal \^pl_received_hot_rst\ : STD_LOGIC;
  signal sys_rst_n_0 : STD_LOGIC;
  signal trn_lnk_up : STD_LOGIC;
  signal \^user_lnk_up\ : STD_LOGIC;
  signal user_lnk_up_d : STD_LOGIC;
  signal \^user_reset_out\ : STD_LOGIC;
  signal user_reset_out_i_1_n_0 : STD_LOGIC;
begin
  INT_OOBCLK_OUT <= \^int_oobclk_out\;
  INT_USERCLK2_OUT <= \^int_userclk2_out\;
  pl_ltssm_state(5 downto 0) <= \^pl_ltssm_state\(5 downto 0);
  pl_phy_lnk_up <= \^pl_phy_lnk_up\;
  pl_received_hot_rst <= \^pl_received_hot_rst\;
  user_lnk_up <= \^user_lnk_up\;
  user_reset_out <= \^user_reset_out\;
gt_top_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_gt_top
     port map (
      CLK_DCLK => ext_ch_gt_drpclk,
      CLK_MMCM_LOCK => int_mmcm_lock_out,
      CLK_PCLK => \^int_oobclk_out\,
      CLK_USERCLK1 => \^int_userclk2_out\,
      D(1 downto 0) => pipe_rx0_char_is_k(1 downto 0),
      INT_QPLLOUTCLK_OUT(1 downto 0) => int_qplloutclk_out(1 downto 0),
      INT_QPLLOUTREFCLK_OUT(1 downto 0) => int_qplloutrefclk_out(1 downto 0),
      PIPE_CPLL_LOCK(7 downto 0) => pipe_cpll_lock(7 downto 0),
      PIPE_POWERDOWN(15 downto 14) => pipe_tx7_powerdown(1 downto 0),
      PIPE_POWERDOWN(13 downto 12) => pipe_tx6_powerdown(1 downto 0),
      PIPE_POWERDOWN(11 downto 10) => pipe_tx5_powerdown(1 downto 0),
      PIPE_POWERDOWN(9 downto 8) => pipe_tx4_powerdown(1 downto 0),
      PIPE_POWERDOWN(7 downto 6) => pipe_tx3_powerdown(1 downto 0),
      PIPE_POWERDOWN(5 downto 4) => pipe_tx2_powerdown(1 downto 0),
      PIPE_POWERDOWN(3 downto 2) => pipe_tx1_powerdown(1 downto 0),
      PIPE_POWERDOWN(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      PIPE_QPLL_LOCK(1 downto 0) => int_qplllock_out(1 downto 0),
      PIPE_RXCHANISALIGNED(7) => pipe_rx7_chanisaligned,
      PIPE_RXCHANISALIGNED(6) => pipe_rx6_chanisaligned,
      PIPE_RXCHANISALIGNED(5) => pipe_rx5_chanisaligned,
      PIPE_RXCHANISALIGNED(4) => pipe_rx4_chanisaligned,
      PIPE_RXCHANISALIGNED(3) => pipe_rx3_chanisaligned,
      PIPE_RXCHANISALIGNED(2) => pipe_rx2_chanisaligned,
      PIPE_RXCHANISALIGNED(1) => pipe_rx1_chanisaligned,
      PIPE_RXCHANISALIGNED(0) => pipe_rx0_chanisaligned,
      PIPE_RXPOLARITY(7) => pipe_rx7_polarity,
      PIPE_RXPOLARITY(6) => pipe_rx6_polarity,
      PIPE_RXPOLARITY(5) => pipe_rx5_polarity,
      PIPE_RXPOLARITY(4) => pipe_rx4_polarity,
      PIPE_RXPOLARITY(3) => pipe_rx3_polarity,
      PIPE_RXPOLARITY(2) => pipe_rx2_polarity,
      PIPE_RXPOLARITY(1) => pipe_rx1_polarity,
      PIPE_RXPOLARITY(0) => pipe_rx0_polarity,
      PIPE_TXCOMPLIANCE(7) => pipe_tx7_compliance,
      PIPE_TXCOMPLIANCE(6) => pipe_tx6_compliance,
      PIPE_TXCOMPLIANCE(5) => pipe_tx5_compliance,
      PIPE_TXCOMPLIANCE(4) => pipe_tx4_compliance,
      PIPE_TXCOMPLIANCE(3) => pipe_tx3_compliance,
      PIPE_TXCOMPLIANCE(2) => pipe_tx2_compliance,
      PIPE_TXCOMPLIANCE(1) => pipe_tx1_compliance,
      PIPE_TXCOMPLIANCE(0) => pipe_tx0_compliance,
      PIPE_TXDATA(127 downto 112) => pipe_tx7_data(15 downto 0),
      PIPE_TXDATA(111 downto 96) => pipe_tx6_data(15 downto 0),
      PIPE_TXDATA(95 downto 80) => pipe_tx5_data(15 downto 0),
      PIPE_TXDATA(79 downto 64) => pipe_tx4_data(15 downto 0),
      PIPE_TXDATA(63 downto 48) => pipe_tx3_data(15 downto 0),
      PIPE_TXDATA(47 downto 32) => pipe_tx2_data(15 downto 0),
      PIPE_TXDATA(31 downto 16) => pipe_tx1_data(15 downto 0),
      PIPE_TXDATA(15 downto 0) => pipe_tx0_data(15 downto 0),
      PIPE_TXDATAK(15 downto 14) => pipe_tx7_char_is_k(1 downto 0),
      PIPE_TXDATAK(13 downto 12) => pipe_tx6_char_is_k(1 downto 0),
      PIPE_TXDATAK(11 downto 10) => pipe_tx5_char_is_k(1 downto 0),
      PIPE_TXDATAK(9 downto 8) => pipe_tx4_char_is_k(1 downto 0),
      PIPE_TXDATAK(7 downto 6) => pipe_tx3_char_is_k(1 downto 0),
      PIPE_TXDATAK(5 downto 4) => pipe_tx2_char_is_k(1 downto 0),
      PIPE_TXDATAK(3 downto 2) => pipe_tx1_char_is_k(1 downto 0),
      PIPE_TXDATAK(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      PIPE_TXDEEMPH(3) => pcie_top_i_n_6,
      PIPE_TXDEEMPH(2) => pcie_top_i_n_7,
      PIPE_TXDEEMPH(1) => pcie_top_i_n_8,
      PIPE_TXDEEMPH(0) => pipe_tx_deemph,
      PIPE_TXDETECTRX => pcie_top_i_n_36,
      PIPE_TXELECIDLE(7) => pipe_tx7_elec_idle,
      PIPE_TXELECIDLE(6) => pipe_tx6_elec_idle,
      PIPE_TXELECIDLE(5) => pipe_tx5_elec_idle,
      PIPE_TXELECIDLE(4) => pipe_tx4_elec_idle,
      PIPE_TXELECIDLE(3) => pipe_tx3_elec_idle,
      PIPE_TXELECIDLE(2) => pipe_tx2_elec_idle,
      PIPE_TXELECIDLE(1) => pipe_tx1_elec_idle,
      PIPE_TXELECIDLE(0) => pipe_tx0_elec_idle,
      PIPE_TXMARGIN(2) => pcie_top_i_n_190,
      PIPE_TXMARGIN(1) => pcie_top_i_n_191,
      PIPE_TXMARGIN(0) => pcie_top_i_n_192,
      Q => phy_rdy_n,
      TXMARGIN(2) => pcie_top_i_n_187,
      TXMARGIN(1) => pcie_top_i_n_188,
      TXMARGIN(0) => pcie_top_i_n_189,
      ext_ch_gt_drpaddr(71 downto 0) => ext_ch_gt_drpaddr(71 downto 0),
      ext_ch_gt_drpdi(127 downto 0) => ext_ch_gt_drpdi(127 downto 0),
      ext_ch_gt_drpdo(127 downto 0) => ext_ch_gt_drpdo(127 downto 0),
      ext_ch_gt_drpen(7 downto 0) => ext_ch_gt_drpen(7 downto 0),
      ext_ch_gt_drprdy(7 downto 0) => ext_ch_gt_drprdy(7 downto 0),
      ext_ch_gt_drpwe(7 downto 0) => ext_ch_gt_drpwe(7 downto 0),
      gt_ch_drp_rdy(7 downto 0) => gt_ch_drp_rdy(7 downto 0),
      gt_rx_phy_status_q => gt_rx_phy_status_q,
      gt_rxelecidle_q => gt_rxelecidle_q,
      \index_reg[1]\(2 downto 0) => PIPE_DRP_FSM(2 downto 0),
      \index_reg[1]_0\(2 downto 0) => PIPE_DRP_FSM(5 downto 3),
      \index_reg[1]_1\(2 downto 0) => PIPE_DRP_FSM(8 downto 6),
      \index_reg[1]_2\(2 downto 0) => PIPE_DRP_FSM(11 downto 9),
      \index_reg[1]_3\(2 downto 0) => PIPE_DRP_FSM(14 downto 12),
      \index_reg[1]_4\(2 downto 0) => PIPE_DRP_FSM(17 downto 15),
      \index_reg[1]_5\(2 downto 0) => PIPE_DRP_FSM(20 downto 18),
      \index_reg[1]_6\(2 downto 0) => PIPE_DRP_FSM(23 downto 21),
      int_pclk_sel_slave(7 downto 0) => int_pclk_sel_slave(7 downto 0),
      \out\(1 downto 0) => \out\(1 downto 0),
      pci_exp_rxn(7 downto 0) => pci_exp_rxn(7 downto 0),
      pci_exp_rxp(7 downto 0) => pci_exp_rxp(7 downto 0),
      pci_exp_txn(7 downto 0) => pci_exp_txn(7 downto 0),
      pci_exp_txp(7 downto 0) => pci_exp_txp(7 downto 0),
      pclk_sel_reg1_reg(7 downto 0) => pipe_pclk_sel_out(7 downto 0),
      pipe_dmonitorout(63 downto 0) => pipe_dmonitorout(63 downto 0),
      pipe_eyescandataerror(7 downto 0) => pipe_eyescandataerror(7 downto 0),
      pipe_mmcm_rst_n => pipe_mmcm_rst_n,
      pipe_qrst_fsm(3 downto 0) => pipe_qrst_fsm(3 downto 0),
      pipe_qrst_idle => pipe_qrst_idle,
      pipe_rate_idle => pipe_rate_idle,
      pipe_rst_fsm(3 downto 0) => pipe_rst_fsm(3 downto 0),
      pipe_rx0_valid => pipe_rx0_valid,
      pipe_rx1_valid => pipe_rx1_valid,
      pipe_rx2_valid => pipe_rx2_valid,
      pipe_rx3_valid => pipe_rx3_valid,
      pipe_rx4_valid => pipe_rx4_valid,
      pipe_rx5_valid => pipe_rx5_valid,
      pipe_rx6_valid => pipe_rx6_valid,
      pipe_rx7_valid => pipe_rx7_valid,
      pipe_rxbufstatus(23 downto 0) => pipe_rxbufstatus(23 downto 0),
      pipe_rxcommadet(7 downto 0) => pipe_rxcommadet(7 downto 0),
      pipe_rxdisperr(63 downto 0) => pipe_rxdisperr(63 downto 0),
      pipe_rxdlysresetdone(7 downto 0) => pipe_rxdlysresetdone(7 downto 0),
      pipe_rxnotintable(63 downto 0) => pipe_rxnotintable(63 downto 0),
      pipe_rxoutclk_out(7 downto 0) => pipe_rxoutclk_out(7 downto 0),
      pipe_rxphaligndone(7 downto 0) => pipe_rxphaligndone(7 downto 0),
      pipe_rxprbserr(7 downto 0) => pipe_rxprbserr(7 downto 0),
      pipe_rxstatus(23 downto 0) => pipe_rxstatus(23 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]\(1 downto 0) => pipe_rx1_char_is_k(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0\(1 downto 0) => pipe_rx2_char_is_k(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1\(1 downto 0) => pipe_rx3_char_is_k(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2\(1 downto 0) => pipe_rx4_char_is_k(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3\(1 downto 0) => pipe_rx5_char_is_k(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4\(1 downto 0) => pipe_rx6_char_is_k(1 downto 0),
      \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5\(1 downto 0) => pipe_rx7_char_is_k(1 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]\(15 downto 0) => pipe_rx0_data(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_0\(15 downto 0) => pipe_rx1_data(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_1\(15 downto 0) => pipe_rx2_data(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_2\(15 downto 0) => pipe_rx3_data(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_3\(15 downto 0) => pipe_rx4_data(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_4\(15 downto 0) => pipe_rx5_data(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_5\(15 downto 0) => pipe_rx6_data(15 downto 0),
      \pipe_stages_1.pipe_rx_data_q_reg[15]_6\(15 downto 0) => pipe_rx7_data(15 downto 0),
      \pipe_stages_1.pipe_rx_elec_idle_q_reg\ => gt_top_i_n_13,
      \pipe_stages_1.pipe_rx_elec_idle_q_reg_0\ => gt_top_i_n_15,
      \pipe_stages_1.pipe_rx_elec_idle_q_reg_1\ => gt_top_i_n_17,
      \pipe_stages_1.pipe_rx_elec_idle_q_reg_2\ => gt_top_i_n_19,
      \pipe_stages_1.pipe_rx_elec_idle_q_reg_3\ => gt_top_i_n_21,
      \pipe_stages_1.pipe_rx_elec_idle_q_reg_4\ => gt_top_i_n_23,
      \pipe_stages_1.pipe_rx_elec_idle_q_reg_5\ => gt_top_i_n_25,
      \pipe_stages_1.pipe_rx_phy_status_q_reg\ => gt_top_i_n_12,
      \pipe_stages_1.pipe_rx_phy_status_q_reg_0\ => gt_top_i_n_14,
      \pipe_stages_1.pipe_rx_phy_status_q_reg_1\ => gt_top_i_n_16,
      \pipe_stages_1.pipe_rx_phy_status_q_reg_2\ => gt_top_i_n_18,
      \pipe_stages_1.pipe_rx_phy_status_q_reg_3\ => gt_top_i_n_20,
      \pipe_stages_1.pipe_rx_phy_status_q_reg_4\ => gt_top_i_n_22,
      \pipe_stages_1.pipe_rx_phy_status_q_reg_5\ => gt_top_i_n_24,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(2) => gt_top_i_n_296,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(1) => gt_top_i_n_297,
      \pipe_stages_1.pipe_rx_status_q_reg[2]\(0) => gt_top_i_n_298,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(2) => gt_top_i_n_299,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(1) => gt_top_i_n_300,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_0\(0) => gt_top_i_n_301,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(2) => gt_top_i_n_302,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(1) => gt_top_i_n_303,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_1\(0) => gt_top_i_n_304,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(2) => gt_top_i_n_305,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(1) => gt_top_i_n_306,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_2\(0) => gt_top_i_n_307,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_3\(2) => gt_top_i_n_308,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_3\(1) => gt_top_i_n_309,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_3\(0) => gt_top_i_n_310,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_4\(2) => gt_top_i_n_311,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_4\(1) => gt_top_i_n_312,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_4\(0) => gt_top_i_n_313,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_5\(2) => gt_top_i_n_314,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_5\(1) => gt_top_i_n_315,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_5\(0) => gt_top_i_n_316,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_6\(2) => gt_top_i_n_317,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_6\(1) => gt_top_i_n_318,
      \pipe_stages_1.pipe_rx_status_q_reg[2]_6\(0) => gt_top_i_n_319,
      \pipe_stages_1.pipe_tx_margin_q_reg[2]\(2 downto 0) => pipe_tx_margin(2 downto 0),
      \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(2) => pcie_top_i_n_184,
      \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(1) => pcie_top_i_n_185,
      \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep\(0) => pcie_top_i_n_186,
      \pipe_stages_1.pipe_tx_rate_q_reg\(0) => pipe_tx_rate,
      \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep\ => pcie_top_i_n_34,
      \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0\ => pcie_top_i_n_35,
      pipe_sync_fsm_rx(55 downto 0) => pipe_sync_fsm_rx(55 downto 0),
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_txdlysresetdone(7 downto 0) => pipe_txdlysresetdone(7 downto 0),
      pipe_txinhibit(7 downto 0) => pipe_txinhibit(7 downto 0),
      pipe_txoutclk_out => pipe_txoutclk_out,
      pipe_txphaligndone(7 downto 0) => pipe_txphaligndone(7 downto 0),
      pipe_txphinitdone(7 downto 0) => pipe_txphinitdone(7 downto 0),
      pl_ltssm_state(5 downto 0) => \^pl_ltssm_state\(5 downto 0),
      rate_gen3(0) => EQ_GEN3,
      reset_n_reg2_reg => gt_top_i_n_874,
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n_0,
      sys_rst_n_0 => sys_rst_n,
      \sysclksel_reg[1]\(4 downto 0) => PIPE_RATE_FSM(4 downto 0),
      \sysclksel_reg[1]_0\(4 downto 0) => PIPE_RATE_FSM(9 downto 5),
      \sysclksel_reg[1]_1\(4 downto 0) => PIPE_RATE_FSM(14 downto 10),
      \sysclksel_reg[1]_2\(4 downto 0) => PIPE_RATE_FSM(19 downto 15),
      \sysclksel_reg[1]_3\(4 downto 0) => PIPE_RATE_FSM(24 downto 20),
      \sysclksel_reg[1]_4\(4 downto 0) => PIPE_RATE_FSM(29 downto 25),
      \sysclksel_reg[1]_5\(4 downto 0) => PIPE_RATE_FSM(34 downto 30),
      \sysclksel_reg[1]_6\(4 downto 0) => PIPE_RATE_FSM(39 downto 35),
      \txsync_fsm.txdlyen_reg\(5 downto 0) => PIPE_SYNC_FSM_TX(11 downto 6),
      \txsync_fsm.txdlyen_reg_0\(5 downto 0) => PIPE_SYNC_FSM_TX(17 downto 12),
      \txsync_fsm.txdlyen_reg_1\(5 downto 0) => PIPE_SYNC_FSM_TX(23 downto 18),
      \txsync_fsm.txdlyen_reg_2\(5 downto 0) => PIPE_SYNC_FSM_TX(29 downto 24),
      \txsync_fsm.txdlyen_reg_3\(5 downto 0) => PIPE_SYNC_FSM_TX(35 downto 30),
      \txsync_fsm.txdlyen_reg_4\(5 downto 0) => PIPE_SYNC_FSM_TX(41 downto 36),
      \txsync_fsm.txdlyen_reg_5\(5 downto 0) => PIPE_SYNC_FSM_TX(47 downto 42),
      \txsync_fsm.txsync_done_reg\(5 downto 0) => PIPE_SYNC_FSM_TX(5 downto 0)
    );
pcie_block_i_i_32: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(3),
      O => cfg_mgmt_byte_en_n(3)
    );
pcie_block_i_i_33: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(2),
      O => cfg_mgmt_byte_en_n(2)
    );
pcie_block_i_i_34: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(1),
      O => cfg_mgmt_byte_en_n(1)
    );
pcie_block_i_i_35: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(0),
      O => cfg_mgmt_byte_en_n(0)
    );
pcie_top_i: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie_top
     port map (
      CLK => \^int_oobclk_out\,
      D(1 downto 0) => pipe_rx0_char_is_k(1 downto 0),
      PIPE_POWERDOWN(15 downto 14) => pipe_tx7_powerdown(1 downto 0),
      PIPE_POWERDOWN(13 downto 12) => pipe_tx6_powerdown(1 downto 0),
      PIPE_POWERDOWN(11 downto 10) => pipe_tx5_powerdown(1 downto 0),
      PIPE_POWERDOWN(9 downto 8) => pipe_tx4_powerdown(1 downto 0),
      PIPE_POWERDOWN(7 downto 6) => pipe_tx3_powerdown(1 downto 0),
      PIPE_POWERDOWN(5 downto 4) => pipe_tx2_powerdown(1 downto 0),
      PIPE_POWERDOWN(3 downto 2) => pipe_tx1_powerdown(1 downto 0),
      PIPE_POWERDOWN(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      PIPE_RXCHANISALIGNED(7) => pipe_rx7_chanisaligned,
      PIPE_RXCHANISALIGNED(6) => pipe_rx6_chanisaligned,
      PIPE_RXCHANISALIGNED(5) => pipe_rx5_chanisaligned,
      PIPE_RXCHANISALIGNED(4) => pipe_rx4_chanisaligned,
      PIPE_RXCHANISALIGNED(3) => pipe_rx3_chanisaligned,
      PIPE_RXCHANISALIGNED(2) => pipe_rx2_chanisaligned,
      PIPE_RXCHANISALIGNED(1) => pipe_rx1_chanisaligned,
      PIPE_RXCHANISALIGNED(0) => pipe_rx0_chanisaligned,
      PIPE_RXPOLARITY(7) => pipe_rx7_polarity,
      PIPE_RXPOLARITY(6) => pipe_rx6_polarity,
      PIPE_RXPOLARITY(5) => pipe_rx5_polarity,
      PIPE_RXPOLARITY(4) => pipe_rx4_polarity,
      PIPE_RXPOLARITY(3) => pipe_rx3_polarity,
      PIPE_RXPOLARITY(2) => pipe_rx2_polarity,
      PIPE_RXPOLARITY(1) => pipe_rx1_polarity,
      PIPE_RXPOLARITY(0) => pipe_rx0_polarity,
      PIPE_TXCOMPLIANCE(7) => pipe_tx7_compliance,
      PIPE_TXCOMPLIANCE(6) => pipe_tx6_compliance,
      PIPE_TXCOMPLIANCE(5) => pipe_tx5_compliance,
      PIPE_TXCOMPLIANCE(4) => pipe_tx4_compliance,
      PIPE_TXCOMPLIANCE(3) => pipe_tx3_compliance,
      PIPE_TXCOMPLIANCE(2) => pipe_tx2_compliance,
      PIPE_TXCOMPLIANCE(1) => pipe_tx1_compliance,
      PIPE_TXCOMPLIANCE(0) => pipe_tx0_compliance,
      PIPE_TXDATA(127 downto 112) => pipe_tx7_data(15 downto 0),
      PIPE_TXDATA(111 downto 96) => pipe_tx6_data(15 downto 0),
      PIPE_TXDATA(95 downto 80) => pipe_tx5_data(15 downto 0),
      PIPE_TXDATA(79 downto 64) => pipe_tx4_data(15 downto 0),
      PIPE_TXDATA(63 downto 48) => pipe_tx3_data(15 downto 0),
      PIPE_TXDATA(47 downto 32) => pipe_tx2_data(15 downto 0),
      PIPE_TXDATA(31 downto 16) => pipe_tx1_data(15 downto 0),
      PIPE_TXDATA(15 downto 0) => pipe_tx0_data(15 downto 0),
      PIPE_TXDATAK(15 downto 14) => pipe_tx7_char_is_k(1 downto 0),
      PIPE_TXDATAK(13 downto 12) => pipe_tx6_char_is_k(1 downto 0),
      PIPE_TXDATAK(11 downto 10) => pipe_tx5_char_is_k(1 downto 0),
      PIPE_TXDATAK(9 downto 8) => pipe_tx4_char_is_k(1 downto 0),
      PIPE_TXDATAK(7 downto 6) => pipe_tx3_char_is_k(1 downto 0),
      PIPE_TXDATAK(5 downto 4) => pipe_tx2_char_is_k(1 downto 0),
      PIPE_TXDATAK(3 downto 2) => pipe_tx1_char_is_k(1 downto 0),
      PIPE_TXDATAK(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      PIPE_TXDEEMPH(3) => pcie_top_i_n_6,
      PIPE_TXDEEMPH(2) => pcie_top_i_n_7,
      PIPE_TXDEEMPH(1) => pcie_top_i_n_8,
      PIPE_TXDEEMPH(0) => pipe_tx_deemph,
      PIPE_TXELECIDLE(7) => pipe_tx7_elec_idle,
      PIPE_TXELECIDLE(6) => pipe_tx6_elec_idle,
      PIPE_TXELECIDLE(5) => pipe_tx5_elec_idle,
      PIPE_TXELECIDLE(4) => pipe_tx4_elec_idle,
      PIPE_TXELECIDLE(3) => pipe_tx3_elec_idle,
      PIPE_TXELECIDLE(2) => pipe_tx2_elec_idle,
      PIPE_TXELECIDLE(1) => pipe_tx1_elec_idle,
      PIPE_TXELECIDLE(0) => pipe_tx0_elec_idle,
      PIPE_TXMARGIN(2) => pcie_top_i_n_190,
      PIPE_TXMARGIN(1) => pcie_top_i_n_191,
      PIPE_TXMARGIN(0) => pcie_top_i_n_192,
      Q(2 downto 0) => pipe_tx_margin(2 downto 0),
      TXMARGIN(2) => pcie_top_i_n_187,
      TXMARGIN(1) => pcie_top_i_n_188,
      TXMARGIN(0) => pcie_top_i_n_189,
      bridge_reset_int => bridge_reset_int,
      cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en,
      cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en,
      cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0),
      cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received,
      cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en,
      cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received,
      cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en,
      cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received,
      cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en,
      cfg_bridge_serr_en => cfg_bridge_serr_en,
      cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0),
      cfg_command(4 downto 0) => cfg_command(4 downto 0),
      cfg_dcommand(14 downto 0) => cfg_dcommand(14 downto 0),
      cfg_dcommand2(11 downto 0) => cfg_dcommand2(11 downto 0),
      cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0),
      cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0),
      cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0),
      cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0),
      cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0),
      cfg_dstatus(3 downto 0) => cfg_dstatus(3 downto 0),
      cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0),
      cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set,
      cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked,
      cfg_err_cor => cfg_err_cor,
      cfg_err_cpl_abort => cfg_err_cpl_abort,
      cfg_err_cpl_rdy => cfg_err_cpl_rdy,
      cfg_err_cpl_timeout => cfg_err_cpl_timeout,
      cfg_err_cpl_unexpect => cfg_err_cpl_unexpect,
      cfg_err_ecrc => cfg_err_ecrc,
      cfg_err_internal_cor => cfg_err_internal_cor,
      cfg_err_internal_uncor => cfg_err_internal_uncor,
      cfg_err_locked => cfg_err_locked,
      cfg_err_malformed => cfg_err_malformed,
      cfg_err_mc_blocked => cfg_err_mc_blocked,
      cfg_err_norecovery => cfg_err_norecovery,
      cfg_err_poisoned => cfg_err_poisoned,
      cfg_err_posted => cfg_err_posted,
      cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0),
      cfg_err_ur => cfg_err_ur,
      cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0),
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0),
      cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_msixenable => cfg_interrupt_msixenable,
      cfg_interrupt_msixfm => cfg_interrupt_msixfm,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_interrupt_stat => cfg_interrupt_stat,
      cfg_lcommand(10 downto 0) => cfg_lcommand(10 downto 0),
      cfg_lstatus(9 downto 0) => cfg_lstatus(9 downto 0),
      cfg_mgmt_byte_en_n(3 downto 0) => cfg_mgmt_byte_en_n(3 downto 0),
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw,
      cfg_msg_data(15 downto 0) => cfg_msg_data(15 downto 0),
      cfg_msg_received => cfg_msg_received,
      cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a,
      cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b,
      cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c,
      cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d,
      cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a,
      cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b,
      cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c,
      cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d,
      cfg_msg_received_err_cor => cfg_msg_received_err_cor,
      cfg_msg_received_err_fatal => cfg_msg_received_err_fatal,
      cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal,
      cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak,
      cfg_msg_received_pm_pme => cfg_msg_received_pm_pme,
      cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack,
      cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit,
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0),
      cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0),
      cfg_pm_force_state_en => cfg_pm_force_state_en,
      cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s,
      cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1,
      cfg_pm_wake => cfg_pm_wake,
      cfg_pmcsr_pme_en => cfg_pmcsr_pme_en,
      cfg_pmcsr_pme_status => cfg_pmcsr_pme_status,
      cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0),
      cfg_received_func_lvl_rst => cfg_received_func_lvl_rst,
      cfg_root_control_pme_int_en => cfg_root_control_pme_int_en,
      cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en,
      cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en,
      cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en,
      cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse,
      cfg_to_turnoff => cfg_to_turnoff,
      cfg_trn_pending => cfg_trn_pending,
      cfg_turnoff_ok => cfg_turnoff_ok,
      cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0),
      \cplllock_reg1_reg[2]\ => pcie_top_i_n_35,
      \cplllock_reg1_reg[3]\ => pcie_top_i_n_34,
      \cplllock_reg1_reg[3]_0\(2) => pcie_top_i_n_184,
      \cplllock_reg1_reg[3]_0\(1) => pcie_top_i_n_185,
      \cplllock_reg1_reg[3]_0\(0) => pcie_top_i_n_186,
      \cplllock_reg1_reg[6]\ => pcie_top_i_n_36,
      fc_cpld(11 downto 0) => fc_cpld(11 downto 0),
      fc_cplh(7 downto 0) => fc_cplh(7 downto 0),
      fc_npd(11 downto 0) => fc_npd(11 downto 0),
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_pd(11 downto 0) => fc_pd(11 downto 0),
      fc_ph(7 downto 0) => fc_ph(7 downto 0),
      fc_sel(2 downto 0) => fc_sel(2 downto 0),
      gt_rx_phy_status_q => gt_rx_phy_status_q,
      gt_rx_phy_status_q_reg => gt_top_i_n_12,
      gt_rx_phy_status_q_reg_0 => gt_top_i_n_14,
      gt_rx_phy_status_q_reg_1 => gt_top_i_n_16,
      gt_rx_phy_status_q_reg_2 => gt_top_i_n_18,
      gt_rx_phy_status_q_reg_3 => gt_top_i_n_20,
      gt_rx_phy_status_q_reg_4 => gt_top_i_n_22,
      gt_rx_phy_status_q_reg_5 => gt_top_i_n_24,
      \gt_rx_status_q_reg[2]\(2) => gt_top_i_n_296,
      \gt_rx_status_q_reg[2]\(1) => gt_top_i_n_297,
      \gt_rx_status_q_reg[2]\(0) => gt_top_i_n_298,
      \gt_rx_status_q_reg[2]_0\(2) => gt_top_i_n_299,
      \gt_rx_status_q_reg[2]_0\(1) => gt_top_i_n_300,
      \gt_rx_status_q_reg[2]_0\(0) => gt_top_i_n_301,
      \gt_rx_status_q_reg[2]_1\(2) => gt_top_i_n_302,
      \gt_rx_status_q_reg[2]_1\(1) => gt_top_i_n_303,
      \gt_rx_status_q_reg[2]_1\(0) => gt_top_i_n_304,
      \gt_rx_status_q_reg[2]_2\(2) => gt_top_i_n_305,
      \gt_rx_status_q_reg[2]_2\(1) => gt_top_i_n_306,
      \gt_rx_status_q_reg[2]_2\(0) => gt_top_i_n_307,
      \gt_rx_status_q_reg[2]_3\(2) => gt_top_i_n_308,
      \gt_rx_status_q_reg[2]_3\(1) => gt_top_i_n_309,
      \gt_rx_status_q_reg[2]_3\(0) => gt_top_i_n_310,
      \gt_rx_status_q_reg[2]_4\(2) => gt_top_i_n_311,
      \gt_rx_status_q_reg[2]_4\(1) => gt_top_i_n_312,
      \gt_rx_status_q_reg[2]_4\(0) => gt_top_i_n_313,
      \gt_rx_status_q_reg[2]_5\(2) => gt_top_i_n_314,
      \gt_rx_status_q_reg[2]_5\(1) => gt_top_i_n_315,
      \gt_rx_status_q_reg[2]_5\(0) => gt_top_i_n_316,
      \gt_rx_status_q_reg[2]_6\(2) => gt_top_i_n_317,
      \gt_rx_status_q_reg[2]_6\(1) => gt_top_i_n_318,
      \gt_rx_status_q_reg[2]_6\(0) => gt_top_i_n_319,
      \gt_rxcharisk_q_reg[1]\(1 downto 0) => pipe_rx1_char_is_k(1 downto 0),
      \gt_rxcharisk_q_reg[1]_0\(1 downto 0) => pipe_rx2_char_is_k(1 downto 0),
      \gt_rxcharisk_q_reg[1]_1\(1 downto 0) => pipe_rx3_char_is_k(1 downto 0),
      \gt_rxcharisk_q_reg[1]_2\(1 downto 0) => pipe_rx4_char_is_k(1 downto 0),
      \gt_rxcharisk_q_reg[1]_3\(1 downto 0) => pipe_rx5_char_is_k(1 downto 0),
      \gt_rxcharisk_q_reg[1]_4\(1 downto 0) => pipe_rx6_char_is_k(1 downto 0),
      \gt_rxcharisk_q_reg[1]_5\(1 downto 0) => pipe_rx7_char_is_k(1 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => pipe_rx0_data(15 downto 0),
      \gt_rxdata_q_reg[15]_0\(15 downto 0) => pipe_rx1_data(15 downto 0),
      \gt_rxdata_q_reg[15]_1\(15 downto 0) => pipe_rx2_data(15 downto 0),
      \gt_rxdata_q_reg[15]_2\(15 downto 0) => pipe_rx3_data(15 downto 0),
      \gt_rxdata_q_reg[15]_3\(15 downto 0) => pipe_rx4_data(15 downto 0),
      \gt_rxdata_q_reg[15]_4\(15 downto 0) => pipe_rx5_data(15 downto 0),
      \gt_rxdata_q_reg[15]_5\(15 downto 0) => pipe_rx6_data(15 downto 0),
      \gt_rxdata_q_reg[15]_6\(15 downto 0) => pipe_rx7_data(15 downto 0),
      gt_rxelecidle_q => gt_rxelecidle_q,
      gt_rxelecidle_q_reg => gt_top_i_n_13,
      gt_rxelecidle_q_reg_0 => gt_top_i_n_15,
      gt_rxelecidle_q_reg_1 => gt_top_i_n_17,
      gt_rxelecidle_q_reg_2 => gt_top_i_n_19,
      gt_rxelecidle_q_reg_3 => gt_top_i_n_21,
      gt_rxelecidle_q_reg_4 => gt_top_i_n_23,
      gt_rxelecidle_q_reg_5 => gt_top_i_n_25,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(7 downto 0) => m_axis_rx_tkeep(7 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(21 downto 0) => m_axis_rx_tuser(21 downto 0),
      m_axis_rx_tvalid => m_axis_rx_tvalid,
      pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0),
      pcie_drp_clk => pcie_drp_clk,
      pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0),
      pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0),
      pcie_drp_en => pcie_drp_en,
      pcie_drp_rdy => pcie_drp_rdy,
      pcie_drp_we => pcie_drp_we,
      phy_rdy_n => phy_rdy_n,
      pipe_rx0_valid => pipe_rx0_valid,
      pipe_rx1_valid => pipe_rx1_valid,
      pipe_rx2_valid => pipe_rx2_valid,
      pipe_rx3_valid => pipe_rx3_valid,
      pipe_rx4_valid => pipe_rx4_valid,
      pipe_rx5_valid => pipe_rx5_valid,
      pipe_rx6_valid => pipe_rx6_valid,
      pipe_rx7_valid => pipe_rx7_valid,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pl_directed_change_done => pl_directed_change_done,
      pl_directed_link_auton => pl_directed_link_auton,
      pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0),
      pl_directed_link_speed => pl_directed_link_speed,
      pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0),
      pl_downstream_deemph_source => pl_downstream_deemph_source,
      pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0),
      pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0),
      pl_link_gen2_cap => pl_link_gen2_cap,
      pl_link_partner_gen2_supported => pl_link_partner_gen2_supported,
      pl_link_upcfg_cap => pl_link_upcfg_cap,
      pl_ltssm_state(5 downto 0) => \^pl_ltssm_state\(5 downto 0),
      pl_phy_lnk_up => \^pl_phy_lnk_up\,
      pl_phy_lnk_up_q_reg => pcie_top_i_n_53,
      pl_received_hot_rst => pcie_top_i_n_449,
      pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0),
      pl_sel_lnk_rate => pl_sel_lnk_rate,
      pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0),
      pl_transmit_hot_rst => pl_transmit_hot_rst,
      pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0),
      pl_upstream_prefer_deemph => pl_upstream_prefer_deemph,
      \rate_reg1_reg[0]\(0) => pipe_tx_rate,
      rx_np_ok => rx_np_ok,
      rx_np_req => rx_np_req,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => s_axis_tx_tready,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      sys_rst_n => sys_rst_n_0,
      trn_lnk_up => trn_lnk_up,
      trn_tbuf_av(5 downto 0) => tx_buf_av(5 downto 0),
      trn_tcfg_req => tx_cfg_req,
      tx_cfg_gnt => tx_cfg_gnt,
      tx_err_drop => tx_err_drop,
      user_clk => \^int_userclk2_out\,
      user_lnk_up_int_reg => \^user_lnk_up\,
      user_reset_int_reg => pcie_top_i_n_37,
      user_reset_out_reg => \^user_reset_out\
    );
pl_phy_lnk_up_q_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk2_out\,
      CE => '1',
      D => pcie_top_i_n_53,
      Q => \^pl_phy_lnk_up\,
      R => gt_top_i_n_874
    );
pl_received_hot_rst_q_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk2_out\,
      CE => '1',
      D => pcie_top_i_n_449,
      Q => \^pl_received_hot_rst\,
      R => gt_top_i_n_874
    );
user_lnk_up_d_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk2_out\,
      CE => '1',
      D => trn_lnk_up,
      Q => user_lnk_up_d,
      R => gt_top_i_n_874
    );
user_lnk_up_int_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk2_out\,
      CE => '1',
      D => user_lnk_up_d,
      Q => \^user_lnk_up\,
      R => gt_top_i_n_874
    );
user_reset_int_reg: unisim.vcomponents.FDPE
     port map (
      C => \^int_userclk2_out\,
      CE => '1',
      D => pcie_top_i_n_37,
      PRE => user_reset_out_i_1_n_0,
      Q => bridge_reset_int
    );
user_reset_out_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^pl_received_hot_rst\,
      I1 => sys_rst_n,
      O => user_reset_out_i_1_n_0
    );
user_reset_out_reg: unisim.vcomponents.FDPE
     port map (
      C => \^int_userclk2_out\,
      CE => '1',
      D => bridge_reset_int,
      PRE => user_reset_out_i_1_n_0,
      Q => \^user_reset_out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top is
  port (
    pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 );
    int_pclk_out_slave : out STD_LOGIC;
    int_pipe_rxusrclk_out : out STD_LOGIC;
    int_rxoutclk_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
    int_dclk_out : out STD_LOGIC;
    int_userclk1_out : out STD_LOGIC;
    int_userclk2_out : out STD_LOGIC;
    int_oobclk_out : out STD_LOGIC;
    int_mmcm_lock_out : out STD_LOGIC;
    int_qplllock_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_qplloutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_pclk_in : in STD_LOGIC;
    pipe_rxusrclk_in : in STD_LOGIC;
    pipe_rxoutclk_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_dclk_in : in STD_LOGIC;
    pipe_userclk1_in : in STD_LOGIC;
    pipe_userclk2_in : in STD_LOGIC;
    pipe_oobclk_in : in STD_LOGIC;
    pipe_mmcm_lock_in : in STD_LOGIC;
    pipe_txoutclk_out : out STD_LOGIC;
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_gen3_out : out STD_LOGIC;
    user_clk_out : out STD_LOGIC;
    user_reset_out : out STD_LOGIC;
    user_lnk_up : out STD_LOGIC;
    user_app_rdy : out STD_LOGIC;
    tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    tx_cfg_req : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    s_axis_tx_tready : out STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tx_cfg_gnt : in STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    m_axis_rx_tvalid : out STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_acs : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_trn_pending : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_to_turnoff : out STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pm_wake : in STD_LOGIC;
    cfg_pm_send_pme_to : in STD_LOGIC;
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_msg_received : out STD_LOGIC;
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_msg_received_err_cor : out STD_LOGIC;
    cfg_msg_received_err_non_fatal : out STD_LOGIC;
    cfg_msg_received_err_fatal : out STD_LOGIC;
    cfg_msg_received_pm_as_nak : out STD_LOGIC;
    cfg_msg_received_pm_pme : out STD_LOGIC;
    cfg_msg_received_pme_to_ack : out STD_LOGIC;
    cfg_msg_received_assert_int_a : out STD_LOGIC;
    cfg_msg_received_assert_int_b : out STD_LOGIC;
    cfg_msg_received_assert_int_c : out STD_LOGIC;
    cfg_msg_received_assert_int_d : out STD_LOGIC;
    cfg_msg_received_deassert_int_a : out STD_LOGIC;
    cfg_msg_received_deassert_int_b : out STD_LOGIC;
    cfg_msg_received_deassert_int_c : out STD_LOGIC;
    cfg_msg_received_deassert_int_d : out STD_LOGIC;
    cfg_msg_received_setslotpowerlimit : out STD_LOGIC;
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_speed : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_phy_lnk_up : out STD_LOGIC;
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_directed_change_done : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    sys_clk : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    pipe_mmcm_rst_n : in STD_LOGIC;
    common_commands_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_rx_0_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_1_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_2_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_3_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_4_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_5_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_6_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_7_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    common_commands_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_tx_0_sigs : out STD_LOGIC_VECTOR ( 22 downto 0 );
    pipe_tx_1_sigs : out STD_LOGIC_VECTOR ( 22 downto 0 );
    pipe_tx_2_sigs : out STD_LOGIC_VECTOR ( 22 downto 0 );
    pipe_tx_3_sigs : out STD_LOGIC_VECTOR ( 22 downto 0 );
    pipe_tx_4_sigs : out STD_LOGIC_VECTOR ( 22 downto 0 );
    pipe_tx_5_sigs : out STD_LOGIC_VECTOR ( 22 downto 0 );
    pipe_tx_6_sigs : out STD_LOGIC_VECTOR ( 22 downto 0 );
    pipe_tx_7_sigs : out STD_LOGIC_VECTOR ( 22 downto 0 );
    startup_eos_in : in STD_LOGIC;
    startup_cfgclk : out STD_LOGIC;
    startup_cfgmclk : out STD_LOGIC;
    startup_eos : out STD_LOGIC;
    startup_preq : out STD_LOGIC;
    startup_clk : in STD_LOGIC;
    startup_gsr : in STD_LOGIC;
    startup_gts : in STD_LOGIC;
    startup_keyclearb : in STD_LOGIC;
    startup_pack : in STD_LOGIC;
    startup_usrcclko : in STD_LOGIC;
    startup_usrcclkts : in STD_LOGIC;
    startup_usrdoneo : in STD_LOGIC;
    startup_usrdonets : in STD_LOGIC;
    icap_clk : in STD_LOGIC;
    icap_csib : in STD_LOGIC;
    icap_rdwrb : in STD_LOGIC;
    icap_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    icap_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    qpll_drp_crscode : in STD_LOGIC_VECTOR ( 11 downto 0 );
    qpll_drp_fsm : in STD_LOGIC_VECTOR ( 17 downto 0 );
    qpll_drp_done : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_drp_reset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplllock : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplloutclk : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplloutrefclk : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplld : out STD_LOGIC;
    qpll_qpllreset : out STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_drp_clk : out STD_LOGIC;
    qpll_drp_rst_n : out STD_LOGIC;
    qpll_drp_ovrd : out STD_LOGIC;
    qpll_drp_gen3 : out STD_LOGIC;
    qpll_drp_start : out STD_LOGIC;
    pipe_txprbssel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxprbssel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_txprbsforceerr : in STD_LOGIC;
    pipe_rxprbscntreset : in STD_LOGIC;
    pipe_loopback : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 4 downto 0 );
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_rate_fsm : out STD_LOGIC_VECTOR ( 39 downto 0 );
    pipe_sync_fsm_tx : out STD_LOGIC_VECTOR ( 47 downto 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 55 downto 0 );
    pipe_drp_fsm : out STD_LOGIC_VECTOR ( 55 downto 0 );
    pipe_rst_idle : out STD_LOGIC;
    pipe_qrst_idle : out STD_LOGIC;
    pipe_rate_idle : out STD_LOGIC;
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 23 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 119 downto 0 );
    pipe_cpll_lock : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_qpll_lock : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxpmaresetdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 23 downto 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxsyncdone : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 63 downto 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_4 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_5 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_6 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_7 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug_9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_debug : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ext_ch_gt_drpclk : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 71 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 127 downto 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 127 downto 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pcie_drp_clk : in STD_LOGIC;
    pcie_drp_en : in STD_LOGIC;
    pcie_drp_we : in STD_LOGIC;
    pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_rdy : out STD_LOGIC
  );
  attribute CFG_CTL_IF : string;
  attribute CFG_CTL_IF of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute CFG_FC_IF : string;
  attribute CFG_FC_IF of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute CFG_MGMT_IF : string;
  attribute CFG_MGMT_IF of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute CFG_STATUS_IF : string;
  attribute CFG_STATUS_IF of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute C_DATA_WIDTH : integer;
  attribute C_DATA_WIDTH of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is 64;
  attribute ERR_REPORTING_IF : string;
  attribute ERR_REPORTING_IF of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute EXT_CH_GT_DRP : string;
  attribute EXT_CH_GT_DRP of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute EXT_PIPE_INTERFACE : string;
  attribute EXT_PIPE_INTERFACE of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute EXT_STARTUP_PRIMITIVE : string;
  attribute EXT_STARTUP_PRIMITIVE of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute KEEP_WIDTH : integer;
  attribute KEEP_WIDTH of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is 8;
  attribute LINK_CAP_MAX_LINK_WIDTH : integer;
  attribute LINK_CAP_MAX_LINK_WIDTH of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is 8;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "PCIeGen1x8If64_pcie2_top";
  attribute PCIE_ASYNC_EN : string;
  attribute PCIE_ASYNC_EN of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute PCIE_EXT_CLK : string;
  attribute PCIE_EXT_CLK of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute PCIE_EXT_GT_COMMON : string;
  attribute PCIE_EXT_GT_COMMON of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute PIPE_SIM : string;
  attribute PIPE_SIM of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute PL_INTERFACE : string;
  attribute PL_INTERFACE of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute RCV_MSG_IF : string;
  attribute RCV_MSG_IF of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute SHARED_LOGIC_IN_CORE : string;
  attribute SHARED_LOGIC_IN_CORE of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute TRANSCEIVER_CTRL_STATUS_PORTS : string;
  attribute TRANSCEIVER_CTRL_STATUS_PORTS of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute bar_0 : string;
  attribute bar_0 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FFFFFC00";
  attribute bar_1 : string;
  attribute bar_1 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00000000";
  attribute bar_2 : string;
  attribute bar_2 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00000000";
  attribute bar_3 : string;
  attribute bar_3 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00000000";
  attribute bar_4 : string;
  attribute bar_4 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00000000";
  attribute bar_5 : string;
  attribute bar_5 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00000000";
  attribute bram_lat : string;
  attribute bram_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_aer_base_ptr : string;
  attribute c_aer_base_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute c_aer_cap_ecrc_check_capable : string;
  attribute c_aer_cap_ecrc_check_capable of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_ecrc_gen_capable : string;
  attribute c_aer_cap_ecrc_gen_capable of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_multiheader : string;
  attribute c_aer_cap_multiheader of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_nextptr : string;
  attribute c_aer_cap_nextptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute c_aer_cap_on : string;
  attribute c_aer_cap_on of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_optional_err_support : string;
  attribute c_aer_cap_optional_err_support of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000000";
  attribute c_aer_cap_permit_rooterr_update : string;
  attribute c_aer_cap_permit_rooterr_update of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_buf_opt_bma : string;
  attribute c_buf_opt_bma of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_component_name : string;
  attribute c_component_name of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "PCIeGen1x8If64";
  attribute c_cpl_inf : string;
  attribute c_cpl_inf of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_cpl_infinite : string;
  attribute c_cpl_infinite of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_cpl_timeout_disable_sup : string;
  attribute c_cpl_timeout_disable_sup of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_cpl_timeout_range : string;
  attribute c_cpl_timeout_range of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0010";
  attribute c_cpl_timeout_ranges_sup : string;
  attribute c_cpl_timeout_ranges_sup of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "2";
  attribute c_d1_support : string;
  attribute c_d1_support of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_d2_support : string;
  attribute c_d2_support of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_de_emph : string;
  attribute c_de_emph of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_ari_forwarding_supported : string;
  attribute c_dev_cap2_ari_forwarding_supported of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_atomicop32_completer_supported : string;
  attribute c_dev_cap2_atomicop32_completer_supported of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_atomicop64_completer_supported : string;
  attribute c_dev_cap2_atomicop64_completer_supported of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_atomicop_routing_supported : string;
  attribute c_dev_cap2_atomicop_routing_supported of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_cas128_completer_supported : string;
  attribute c_dev_cap2_cas128_completer_supported of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_tph_completer_supported : string;
  attribute c_dev_cap2_tph_completer_supported of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute c_dev_control_ext_tag_default : string;
  attribute c_dev_control_ext_tag_default of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_dev_port_type : string;
  attribute c_dev_port_type of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_dis_lane_reverse : string;
  attribute c_dis_lane_reverse of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_disable_rx_poisoned_resp : string;
  attribute c_disable_rx_poisoned_resp of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_disable_scrambling : string;
  attribute c_disable_scrambling of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_disable_tx_aspm_l0s : string;
  attribute c_disable_tx_aspm_l0s of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_dll_lnk_actv_cap : string;
  attribute c_dll_lnk_actv_cap of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_dsi_bool : string;
  attribute c_dsi_bool of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_dsn_base_ptr : string;
  attribute c_dsn_base_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "100";
  attribute c_dsn_cap_enabled : string;
  attribute c_dsn_cap_enabled of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_dsn_next_ptr : string;
  attribute c_dsn_next_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute c_enable_msg_route : string;
  attribute c_enable_msg_route of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00000000000";
  attribute c_ep_l0s_accpt_lat : string;
  attribute c_ep_l0s_accpt_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_ep_l1_accpt_lat : string;
  attribute c_ep_l1_accpt_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "7";
  attribute c_ext_pci_cfg_space_addr : string;
  attribute c_ext_pci_cfg_space_addr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "3FF";
  attribute c_external_clocking : string;
  attribute c_external_clocking of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_fc_cpld : string;
  attribute c_fc_cpld of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "850";
  attribute c_fc_cplh : string;
  attribute c_fc_cplh of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "72";
  attribute c_fc_npd : string;
  attribute c_fc_npd of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "8";
  attribute c_fc_nph : string;
  attribute c_fc_nph of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "4";
  attribute c_fc_pd : string;
  attribute c_fc_pd of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "64";
  attribute c_fc_ph : string;
  attribute c_fc_ph of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "4";
  attribute c_gen1 : string;
  attribute c_gen1 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_header_type : string;
  attribute c_header_type of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute c_hw_auton_spd_disable : string;
  attribute c_hw_auton_spd_disable of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_int_width : integer;
  attribute c_int_width of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is 64;
  attribute c_last_cfg_dw : string;
  attribute c_last_cfg_dw of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "10C";
  attribute c_link_cap_aspm_optionality : string;
  attribute c_link_cap_aspm_optionality of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_ll_ack_timeout : string;
  attribute c_ll_ack_timeout of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0000";
  attribute c_ll_ack_timeout_enable : string;
  attribute c_ll_ack_timeout_enable of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_ll_ack_timeout_function : string;
  attribute c_ll_ack_timeout_function of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_ll_replay_timeout : string;
  attribute c_ll_replay_timeout of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0000";
  attribute c_ll_replay_timeout_enable : string;
  attribute c_ll_replay_timeout_enable of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_ll_replay_timeout_func : string;
  attribute c_ll_replay_timeout_func of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "1";
  attribute c_lnk_bndwdt_notif : string;
  attribute c_lnk_bndwdt_notif of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_msi : string;
  attribute c_msi of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_msi_64b_addr : string;
  attribute c_msi_64b_addr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_msi_cap_on : string;
  attribute c_msi_cap_on of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_msi_mult_msg_extn : string;
  attribute c_msi_mult_msg_extn of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_msi_per_vctr_mask_cap : string;
  attribute c_msi_per_vctr_mask_cap of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_msix_cap_on : string;
  attribute c_msix_cap_on of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_msix_next_ptr : string;
  attribute c_msix_next_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute c_msix_pba_bir : string;
  attribute c_msix_pba_bir of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_msix_pba_offset : string;
  attribute c_msix_pba_offset of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_msix_table_bir : string;
  attribute c_msix_table_bir of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_msix_table_offset : string;
  attribute c_msix_table_offset of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_msix_table_size : string;
  attribute c_msix_table_size of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute c_pci_cfg_space_addr : string;
  attribute c_pci_cfg_space_addr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "3F";
  attribute c_pcie_blk_locn : string;
  attribute c_pcie_blk_locn of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "3";
  attribute c_pcie_cap_next_ptr : string;
  attribute c_pcie_cap_next_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute c_pcie_cap_slot_implemented : string;
  attribute c_pcie_cap_slot_implemented of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_pcie_dbg_ports : string;
  attribute c_pcie_dbg_ports of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_pcie_fast_config : integer;
  attribute c_pcie_fast_config of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is 0;
  attribute c_perf_level_high : string;
  attribute c_perf_level_high of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_phantom_functions : string;
  attribute c_phantom_functions of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_pm_cap_next_ptr : string;
  attribute c_pm_cap_next_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "48";
  attribute c_pme_support : string;
  attribute c_pme_support of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0F";
  attribute c_rbar_base_ptr : string;
  attribute c_rbar_base_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute c_rbar_cap_control_encodedbar0 : string;
  attribute c_rbar_cap_control_encodedbar0 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar1 : string;
  attribute c_rbar_cap_control_encodedbar1 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar2 : string;
  attribute c_rbar_cap_control_encodedbar2 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar3 : string;
  attribute c_rbar_cap_control_encodedbar3 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar4 : string;
  attribute c_rbar_cap_control_encodedbar4 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar5 : string;
  attribute c_rbar_cap_control_encodedbar5 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute c_rbar_cap_index0 : string;
  attribute c_rbar_cap_index0 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_rbar_cap_index1 : string;
  attribute c_rbar_cap_index1 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_rbar_cap_index2 : string;
  attribute c_rbar_cap_index2 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_rbar_cap_index3 : string;
  attribute c_rbar_cap_index3 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_rbar_cap_index4 : string;
  attribute c_rbar_cap_index4 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_rbar_cap_index5 : string;
  attribute c_rbar_cap_index5 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_rbar_cap_nextptr : string;
  attribute c_rbar_cap_nextptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute c_rbar_cap_on : string;
  attribute c_rbar_cap_on of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_rbar_cap_sup0 : string;
  attribute c_rbar_cap_sup0 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup1 : string;
  attribute c_rbar_cap_sup1 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup2 : string;
  attribute c_rbar_cap_sup2 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup3 : string;
  attribute c_rbar_cap_sup3 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup4 : string;
  attribute c_rbar_cap_sup4 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup5 : string;
  attribute c_rbar_cap_sup5 of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00001";
  attribute c_rbar_num : string;
  attribute c_rbar_num of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_rcb : string;
  attribute c_rcb of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_recrc_check : string;
  attribute c_recrc_check of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_recrc_check_trim : string;
  attribute c_recrc_check_trim of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_rev_gt_order : string;
  attribute c_rev_gt_order of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_root_cap_crs : string;
  attribute c_root_cap_crs of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_rx_raddr_lat : string;
  attribute c_rx_raddr_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_rx_ram_limit : string;
  attribute c_rx_ram_limit of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "7FF";
  attribute c_rx_rdata_lat : string;
  attribute c_rx_rdata_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "2";
  attribute c_rx_write_lat : string;
  attribute c_rx_write_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_silicon_rev : string;
  attribute c_silicon_rev of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "2";
  attribute c_slot_cap_attn_butn : string;
  attribute c_slot_cap_attn_butn of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_attn_ind : string;
  attribute c_slot_cap_attn_ind of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_elec_interlock : string;
  attribute c_slot_cap_elec_interlock of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_hotplug_cap : string;
  attribute c_slot_cap_hotplug_cap of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_hotplug_surprise : string;
  attribute c_slot_cap_hotplug_surprise of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_mrl : string;
  attribute c_slot_cap_mrl of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_no_cmd_comp_sup : string;
  attribute c_slot_cap_no_cmd_comp_sup of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_physical_slot_num : string;
  attribute c_slot_cap_physical_slot_num of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_slot_cap_pwr_ctrl : string;
  attribute c_slot_cap_pwr_ctrl of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_pwr_ind : string;
  attribute c_slot_cap_pwr_ind of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_pwr_limit_scale : string;
  attribute c_slot_cap_pwr_limit_scale of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_slot_cap_pwr_limit_value : string;
  attribute c_slot_cap_pwr_limit_value of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_surprise_dn_err_cap : string;
  attribute c_surprise_dn_err_cap of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_trgt_lnk_spd : string;
  attribute c_trgt_lnk_spd of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_trn_np_fc : string;
  attribute c_trn_np_fc of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_tx_last_tlp : string;
  attribute c_tx_last_tlp of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "29";
  attribute c_tx_raddr_lat : string;
  attribute c_tx_raddr_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_tx_rdata_lat : string;
  attribute c_tx_rdata_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "2";
  attribute c_tx_write_lat : string;
  attribute c_tx_write_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute c_upconfig_capable : string;
  attribute c_upconfig_capable of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_upstream_facing : string;
  attribute c_upstream_facing of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_ur_atomic : string;
  attribute c_ur_atomic of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_ur_inv_req : string;
  attribute c_ur_inv_req of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_ur_prs_response : string;
  attribute c_ur_prs_response of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute c_vc_base_ptr : string;
  attribute c_vc_base_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute c_vc_cap_enabled : string;
  attribute c_vc_cap_enabled of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_vc_cap_reject_snoop : string;
  attribute c_vc_cap_reject_snoop of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_vc_next_ptr : string;
  attribute c_vc_next_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute c_vsec_base_ptr : string;
  attribute c_vsec_base_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute c_vsec_cap_enabled : string;
  attribute c_vsec_cap_enabled of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute c_vsec_next_ptr : string;
  attribute c_vsec_next_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute c_xlnx_ref_board : string;
  attribute c_xlnx_ref_board of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "VC707";
  attribute cap_ver : string;
  attribute cap_ver of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "2";
  attribute cardbus_cis_ptr : string;
  attribute cardbus_cis_ptr of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00000000";
  attribute class_code : string;
  attribute class_code of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "058000";
  attribute cmps : string;
  attribute cmps of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "2";
  attribute con_scl_fctr_d0_state : string;
  attribute con_scl_fctr_d0_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute con_scl_fctr_d1_state : string;
  attribute con_scl_fctr_d1_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute con_scl_fctr_d2_state : string;
  attribute con_scl_fctr_d2_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute con_scl_fctr_d3_state : string;
  attribute con_scl_fctr_d3_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute cost_table : integer;
  attribute cost_table of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is 1;
  attribute d1_sup : string;
  attribute d1_sup of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute d2_sup : string;
  attribute d2_sup of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute dev_id : string;
  attribute dev_id of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "7018";
  attribute dev_port_type : string;
  attribute dev_port_type of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0000";
  attribute dis_scl_fctr_d0_state : string;
  attribute dis_scl_fctr_d0_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute dis_scl_fctr_d1_state : string;
  attribute dis_scl_fctr_d1_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute dis_scl_fctr_d2_state : string;
  attribute dis_scl_fctr_d2_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute dis_scl_fctr_d3_state : string;
  attribute dis_scl_fctr_d3_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "yes";
  attribute dsi : string;
  attribute dsi of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute ep_l0s_accpt_lat : string;
  attribute ep_l0s_accpt_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "000";
  attribute ep_l1_accpt_lat : string;
  attribute ep_l1_accpt_lat of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "111";
  attribute ext_tag_fld_sup : string;
  attribute ext_tag_fld_sup of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute int_pin : string;
  attribute int_pin of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute intx : string;
  attribute intx of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "FALSE";
  attribute max_lnk_spd : string;
  attribute max_lnk_spd of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "1";
  attribute max_lnk_wdt : string;
  attribute max_lnk_wdt of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "001000";
  attribute mps : string;
  attribute mps of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "010";
  attribute no_soft_rst : string;
  attribute no_soft_rst of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute pci_exp_int_freq : integer;
  attribute pci_exp_int_freq of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is 3;
  attribute pci_exp_ref_freq : string;
  attribute pci_exp_ref_freq of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0";
  attribute phantm_func_sup : string;
  attribute phantm_func_sup of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute pme_sup : string;
  attribute pme_sup of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0F";
  attribute pwr_con_d0_state : string;
  attribute pwr_con_d0_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute pwr_con_d1_state : string;
  attribute pwr_con_d1_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute pwr_con_d2_state : string;
  attribute pwr_con_d2_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute pwr_con_d3_state : string;
  attribute pwr_con_d3_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute pwr_dis_d0_state : string;
  attribute pwr_dis_d0_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute pwr_dis_d1_state : string;
  attribute pwr_dis_d1_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute pwr_dis_d2_state : string;
  attribute pwr_dis_d2_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute pwr_dis_d3_state : string;
  attribute pwr_dis_d3_state of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute rev_id : string;
  attribute rev_id of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00";
  attribute slot_clk : string;
  attribute slot_clk of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "TRUE";
  attribute subsys_id : string;
  attribute subsys_id of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "0007";
  attribute subsys_ven_id : string;
  attribute subsys_ven_id of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "10EE";
  attribute ven_id : string;
  attribute ven_id of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "10EE";
  attribute xrom_bar : string;
  attribute xrom_bar of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top : entity is "00000000";
end PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top;

architecture STRUCTURE of PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^cfg_command\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \^cfg_dcommand\ : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal \^cfg_dcommand2\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \^cfg_dstatus\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^cfg_lcommand\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \^cfg_lstatus\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^cfg_trn_pending\ : STD_LOGIC;
  signal \^ext_ch_gt_drpclk\ : STD_LOGIC;
  signal \^int_pipe_rxusrclk_out\ : STD_LOGIC;
  signal \^int_qplllock_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^int_userclk2_out\ : STD_LOGIC;
  signal \^pipe_dmonitorout\ : STD_LOGIC_VECTOR ( 112 downto 0 );
  signal \^pipe_drp_fsm\ : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal \^pipe_qrst_fsm\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
  \^cfg_trn_pending\ <= cfg_trn_pending;
  cfg_command(15) <= \<const0>\;
  cfg_command(14) <= \<const0>\;
  cfg_command(13) <= \<const0>\;
  cfg_command(12) <= \<const0>\;
  cfg_command(11) <= \<const0>\;
  cfg_command(10) <= \^cfg_command\(10);
  cfg_command(9) <= \<const0>\;
  cfg_command(8) <= \^cfg_command\(8);
  cfg_command(7) <= \<const0>\;
  cfg_command(6) <= \<const0>\;
  cfg_command(5) <= \<const0>\;
  cfg_command(4) <= \<const0>\;
  cfg_command(3) <= \<const0>\;
  cfg_command(2 downto 0) <= \^cfg_command\(2 downto 0);
  cfg_dcommand(15) <= \<const0>\;
  cfg_dcommand(14 downto 0) <= \^cfg_dcommand\(14 downto 0);
  cfg_dcommand2(15) <= \<const0>\;
  cfg_dcommand2(14) <= \<const0>\;
  cfg_dcommand2(13) <= \<const0>\;
  cfg_dcommand2(12) <= \<const0>\;
  cfg_dcommand2(11 downto 0) <= \^cfg_dcommand2\(11 downto 0);
  cfg_dstatus(15) <= \<const0>\;
  cfg_dstatus(14) <= \<const0>\;
  cfg_dstatus(13) <= \<const0>\;
  cfg_dstatus(12) <= \<const0>\;
  cfg_dstatus(11) <= \<const0>\;
  cfg_dstatus(10) <= \<const0>\;
  cfg_dstatus(9) <= \<const0>\;
  cfg_dstatus(8) <= \<const0>\;
  cfg_dstatus(7) <= \<const0>\;
  cfg_dstatus(6) <= \<const0>\;
  cfg_dstatus(5) <= \^cfg_trn_pending\;
  cfg_dstatus(4) <= \<const0>\;
  cfg_dstatus(3 downto 0) <= \^cfg_dstatus\(3 downto 0);
  cfg_lcommand(15) <= \<const0>\;
  cfg_lcommand(14) <= \<const0>\;
  cfg_lcommand(13) <= \<const0>\;
  cfg_lcommand(12) <= \<const0>\;
  cfg_lcommand(11 downto 3) <= \^cfg_lcommand\(11 downto 3);
  cfg_lcommand(2) <= \<const0>\;
  cfg_lcommand(1 downto 0) <= \^cfg_lcommand\(1 downto 0);
  cfg_lstatus(15 downto 13) <= \^cfg_lstatus\(15 downto 13);
  cfg_lstatus(12) <= \<const1>\;
  cfg_lstatus(11) <= \^cfg_lstatus\(11);
  cfg_lstatus(10) <= \<const0>\;
  cfg_lstatus(9) <= \<const0>\;
  cfg_lstatus(8) <= \<const0>\;
  cfg_lstatus(7 downto 4) <= \^cfg_lstatus\(7 downto 4);
  cfg_lstatus(3) <= \<const0>\;
  cfg_lstatus(2) <= \<const0>\;
  cfg_lstatus(1 downto 0) <= \^cfg_lstatus\(1 downto 0);
  cfg_status(15) <= \<const0>\;
  cfg_status(14) <= \<const0>\;
  cfg_status(13) <= \<const0>\;
  cfg_status(12) <= \<const0>\;
  cfg_status(11) <= \<const0>\;
  cfg_status(10) <= \<const0>\;
  cfg_status(9) <= \<const0>\;
  cfg_status(8) <= \<const0>\;
  cfg_status(7) <= \<const0>\;
  cfg_status(6) <= \<const0>\;
  cfg_status(5) <= \<const0>\;
  cfg_status(4) <= \<const0>\;
  cfg_status(3) <= \<const0>\;
  cfg_status(2) <= \<const0>\;
  cfg_status(1) <= \<const0>\;
  cfg_status(0) <= \<const0>\;
  common_commands_out(11) <= \<const0>\;
  common_commands_out(10) <= \<const0>\;
  common_commands_out(9) <= \<const0>\;
  common_commands_out(8) <= \<const0>\;
  common_commands_out(7) <= \<const0>\;
  common_commands_out(6) <= \<const0>\;
  common_commands_out(5) <= \<const0>\;
  common_commands_out(4) <= \<const0>\;
  common_commands_out(3) <= \<const0>\;
  common_commands_out(2) <= \<const0>\;
  common_commands_out(1) <= \<const0>\;
  common_commands_out(0) <= \<const0>\;
  ext_ch_gt_drpclk <= \^ext_ch_gt_drpclk\;
  icap_o(31) <= \<const0>\;
  icap_o(30) <= \<const0>\;
  icap_o(29) <= \<const0>\;
  icap_o(28) <= \<const0>\;
  icap_o(27) <= \<const0>\;
  icap_o(26) <= \<const0>\;
  icap_o(25) <= \<const0>\;
  icap_o(24) <= \<const0>\;
  icap_o(23) <= \<const0>\;
  icap_o(22) <= \<const0>\;
  icap_o(21) <= \<const0>\;
  icap_o(20) <= \<const0>\;
  icap_o(19) <= \<const0>\;
  icap_o(18) <= \<const0>\;
  icap_o(17) <= \<const0>\;
  icap_o(16) <= \<const0>\;
  icap_o(15) <= \<const0>\;
  icap_o(14) <= \<const0>\;
  icap_o(13) <= \<const0>\;
  icap_o(12) <= \<const0>\;
  icap_o(11) <= \<const0>\;
  icap_o(10) <= \<const0>\;
  icap_o(9) <= \<const0>\;
  icap_o(8) <= \<const0>\;
  icap_o(7) <= \<const0>\;
  icap_o(6) <= \<const0>\;
  icap_o(5) <= \<const0>\;
  icap_o(4) <= \<const0>\;
  icap_o(3) <= \<const0>\;
  icap_o(2) <= \<const0>\;
  icap_o(1) <= \<const0>\;
  icap_o(0) <= \<const0>\;
  int_dclk_out <= \^ext_ch_gt_drpclk\;
  int_oobclk_out <= \^int_pipe_rxusrclk_out\;
  int_pclk_out_slave <= \<const0>\;
  int_pipe_rxusrclk_out <= \^int_pipe_rxusrclk_out\;
  int_qplllock_out(1 downto 0) <= \^int_qplllock_out\(1 downto 0);
  int_rxoutclk_out(7) <= \<const0>\;
  int_rxoutclk_out(6) <= \<const0>\;
  int_rxoutclk_out(5) <= \<const0>\;
  int_rxoutclk_out(4) <= \<const0>\;
  int_rxoutclk_out(3) <= \<const0>\;
  int_rxoutclk_out(2) <= \<const0>\;
  int_rxoutclk_out(1) <= \<const0>\;
  int_rxoutclk_out(0) <= \<const0>\;
  int_userclk1_out <= \^int_userclk2_out\;
  int_userclk2_out <= \^int_userclk2_out\;
  pipe_debug(31) <= \<const0>\;
  pipe_debug(30) <= \<const0>\;
  pipe_debug(29) <= \<const0>\;
  pipe_debug(28) <= \<const0>\;
  pipe_debug(27) <= \<const0>\;
  pipe_debug(26) <= \<const0>\;
  pipe_debug(25) <= \<const0>\;
  pipe_debug(24) <= \<const0>\;
  pipe_debug(23) <= \<const0>\;
  pipe_debug(22) <= \<const0>\;
  pipe_debug(21) <= \<const0>\;
  pipe_debug(20) <= \<const0>\;
  pipe_debug(19) <= \<const0>\;
  pipe_debug(18) <= \<const0>\;
  pipe_debug(17) <= \<const0>\;
  pipe_debug(16) <= \<const0>\;
  pipe_debug(15) <= \<const0>\;
  pipe_debug(14) <= \<const0>\;
  pipe_debug(13) <= \<const0>\;
  pipe_debug(12) <= \<const0>\;
  pipe_debug(11) <= \<const0>\;
  pipe_debug(10) <= \<const0>\;
  pipe_debug(9) <= \<const0>\;
  pipe_debug(8) <= \<const0>\;
  pipe_debug(7) <= \<const0>\;
  pipe_debug(6) <= \<const0>\;
  pipe_debug(5) <= \<const0>\;
  pipe_debug(4) <= \<const0>\;
  pipe_debug(3) <= \<const0>\;
  pipe_debug(2) <= \<const0>\;
  pipe_debug(1) <= \<const0>\;
  pipe_debug(0) <= \<const0>\;
  pipe_debug_0(7) <= \<const0>\;
  pipe_debug_0(6) <= \<const0>\;
  pipe_debug_0(5) <= \<const0>\;
  pipe_debug_0(4) <= \<const0>\;
  pipe_debug_0(3) <= \<const0>\;
  pipe_debug_0(2) <= \<const0>\;
  pipe_debug_0(1) <= \<const0>\;
  pipe_debug_0(0) <= \<const0>\;
  pipe_debug_1(7) <= \<const0>\;
  pipe_debug_1(6) <= \<const0>\;
  pipe_debug_1(5) <= \<const0>\;
  pipe_debug_1(4) <= \<const0>\;
  pipe_debug_1(3) <= \<const0>\;
  pipe_debug_1(2) <= \<const0>\;
  pipe_debug_1(1) <= \<const0>\;
  pipe_debug_1(0) <= \<const0>\;
  pipe_debug_2(7) <= \<const0>\;
  pipe_debug_2(6) <= \<const0>\;
  pipe_debug_2(5) <= \<const0>\;
  pipe_debug_2(4) <= \<const0>\;
  pipe_debug_2(3) <= \<const0>\;
  pipe_debug_2(2) <= \<const0>\;
  pipe_debug_2(1) <= \<const0>\;
  pipe_debug_2(0) <= \<const0>\;
  pipe_debug_3(7) <= \<const0>\;
  pipe_debug_3(6) <= \<const0>\;
  pipe_debug_3(5) <= \<const0>\;
  pipe_debug_3(4) <= \<const0>\;
  pipe_debug_3(3) <= \<const0>\;
  pipe_debug_3(2) <= \<const0>\;
  pipe_debug_3(1) <= \<const0>\;
  pipe_debug_3(0) <= \<const0>\;
  pipe_debug_4(7) <= \<const0>\;
  pipe_debug_4(6) <= \<const0>\;
  pipe_debug_4(5) <= \<const0>\;
  pipe_debug_4(4) <= \<const0>\;
  pipe_debug_4(3) <= \<const0>\;
  pipe_debug_4(2) <= \<const0>\;
  pipe_debug_4(1) <= \<const0>\;
  pipe_debug_4(0) <= \<const0>\;
  pipe_debug_5(7) <= \<const0>\;
  pipe_debug_5(6) <= \<const0>\;
  pipe_debug_5(5) <= \<const0>\;
  pipe_debug_5(4) <= \<const0>\;
  pipe_debug_5(3) <= \<const0>\;
  pipe_debug_5(2) <= \<const0>\;
  pipe_debug_5(1) <= \<const0>\;
  pipe_debug_5(0) <= \<const0>\;
  pipe_debug_6(7) <= \<const0>\;
  pipe_debug_6(6) <= \<const0>\;
  pipe_debug_6(5) <= \<const0>\;
  pipe_debug_6(4) <= \<const0>\;
  pipe_debug_6(3) <= \<const0>\;
  pipe_debug_6(2) <= \<const0>\;
  pipe_debug_6(1) <= \<const0>\;
  pipe_debug_6(0) <= \<const0>\;
  pipe_debug_7(7) <= \<const0>\;
  pipe_debug_7(6) <= \<const0>\;
  pipe_debug_7(5) <= \<const0>\;
  pipe_debug_7(4) <= \<const0>\;
  pipe_debug_7(3) <= \<const0>\;
  pipe_debug_7(2) <= \<const0>\;
  pipe_debug_7(1) <= \<const0>\;
  pipe_debug_7(0) <= \<const0>\;
  pipe_debug_8(7) <= \<const0>\;
  pipe_debug_8(6) <= \<const0>\;
  pipe_debug_8(5) <= \<const0>\;
  pipe_debug_8(4) <= \<const0>\;
  pipe_debug_8(3) <= \<const0>\;
  pipe_debug_8(2) <= \<const0>\;
  pipe_debug_8(1) <= \<const0>\;
  pipe_debug_8(0) <= \<const0>\;
  pipe_debug_9(7) <= \<const0>\;
  pipe_debug_9(6) <= \<const0>\;
  pipe_debug_9(5) <= \<const0>\;
  pipe_debug_9(4) <= \<const0>\;
  pipe_debug_9(3) <= \<const0>\;
  pipe_debug_9(2) <= \<const0>\;
  pipe_debug_9(1) <= \<const0>\;
  pipe_debug_9(0) <= \<const0>\;
  pipe_dmonitorout(119) <= \<const0>\;
  pipe_dmonitorout(118) <= \<const0>\;
  pipe_dmonitorout(117) <= \<const0>\;
  pipe_dmonitorout(116) <= \<const0>\;
  pipe_dmonitorout(115) <= \<const0>\;
  pipe_dmonitorout(114) <= \<const0>\;
  pipe_dmonitorout(113) <= \<const0>\;
  pipe_dmonitorout(112 downto 105) <= \^pipe_dmonitorout\(112 downto 105);
  pipe_dmonitorout(104) <= \<const0>\;
  pipe_dmonitorout(103) <= \<const0>\;
  pipe_dmonitorout(102) <= \<const0>\;
  pipe_dmonitorout(101) <= \<const0>\;
  pipe_dmonitorout(100) <= \<const0>\;
  pipe_dmonitorout(99) <= \<const0>\;
  pipe_dmonitorout(98) <= \<const0>\;
  pipe_dmonitorout(97 downto 90) <= \^pipe_dmonitorout\(97 downto 90);
  pipe_dmonitorout(89) <= \<const0>\;
  pipe_dmonitorout(88) <= \<const0>\;
  pipe_dmonitorout(87) <= \<const0>\;
  pipe_dmonitorout(86) <= \<const0>\;
  pipe_dmonitorout(85) <= \<const0>\;
  pipe_dmonitorout(84) <= \<const0>\;
  pipe_dmonitorout(83) <= \<const0>\;
  pipe_dmonitorout(82 downto 75) <= \^pipe_dmonitorout\(82 downto 75);
  pipe_dmonitorout(74) <= \<const0>\;
  pipe_dmonitorout(73) <= \<const0>\;
  pipe_dmonitorout(72) <= \<const0>\;
  pipe_dmonitorout(71) <= \<const0>\;
  pipe_dmonitorout(70) <= \<const0>\;
  pipe_dmonitorout(69) <= \<const0>\;
  pipe_dmonitorout(68) <= \<const0>\;
  pipe_dmonitorout(67 downto 60) <= \^pipe_dmonitorout\(67 downto 60);
  pipe_dmonitorout(59) <= \<const0>\;
  pipe_dmonitorout(58) <= \<const0>\;
  pipe_dmonitorout(57) <= \<const0>\;
  pipe_dmonitorout(56) <= \<const0>\;
  pipe_dmonitorout(55) <= \<const0>\;
  pipe_dmonitorout(54) <= \<const0>\;
  pipe_dmonitorout(53) <= \<const0>\;
  pipe_dmonitorout(52 downto 45) <= \^pipe_dmonitorout\(52 downto 45);
  pipe_dmonitorout(44) <= \<const0>\;
  pipe_dmonitorout(43) <= \<const0>\;
  pipe_dmonitorout(42) <= \<const0>\;
  pipe_dmonitorout(41) <= \<const0>\;
  pipe_dmonitorout(40) <= \<const0>\;
  pipe_dmonitorout(39) <= \<const0>\;
  pipe_dmonitorout(38) <= \<const0>\;
  pipe_dmonitorout(37 downto 30) <= \^pipe_dmonitorout\(37 downto 30);
  pipe_dmonitorout(29) <= \<const0>\;
  pipe_dmonitorout(28) <= \<const0>\;
  pipe_dmonitorout(27) <= \<const0>\;
  pipe_dmonitorout(26) <= \<const0>\;
  pipe_dmonitorout(25) <= \<const0>\;
  pipe_dmonitorout(24) <= \<const0>\;
  pipe_dmonitorout(23) <= \<const0>\;
  pipe_dmonitorout(22 downto 15) <= \^pipe_dmonitorout\(22 downto 15);
  pipe_dmonitorout(14) <= \<const0>\;
  pipe_dmonitorout(13) <= \<const0>\;
  pipe_dmonitorout(12) <= \<const0>\;
  pipe_dmonitorout(11) <= \<const0>\;
  pipe_dmonitorout(10) <= \<const0>\;
  pipe_dmonitorout(9) <= \<const0>\;
  pipe_dmonitorout(8) <= \<const0>\;
  pipe_dmonitorout(7 downto 0) <= \^pipe_dmonitorout\(7 downto 0);
  pipe_drp_fsm(55) <= \<const0>\;
  pipe_drp_fsm(54) <= \<const0>\;
  pipe_drp_fsm(53) <= \<const0>\;
  pipe_drp_fsm(52) <= \<const0>\;
  pipe_drp_fsm(51) <= \<const0>\;
  pipe_drp_fsm(50) <= \<const0>\;
  pipe_drp_fsm(49) <= \<const0>\;
  pipe_drp_fsm(48) <= \<const0>\;
  pipe_drp_fsm(47) <= \<const0>\;
  pipe_drp_fsm(46) <= \<const0>\;
  pipe_drp_fsm(45) <= \<const0>\;
  pipe_drp_fsm(44) <= \<const0>\;
  pipe_drp_fsm(43) <= \<const0>\;
  pipe_drp_fsm(42) <= \<const0>\;
  pipe_drp_fsm(41) <= \<const0>\;
  pipe_drp_fsm(40) <= \<const0>\;
  pipe_drp_fsm(39) <= \<const0>\;
  pipe_drp_fsm(38) <= \<const0>\;
  pipe_drp_fsm(37) <= \<const0>\;
  pipe_drp_fsm(36) <= \<const0>\;
  pipe_drp_fsm(35) <= \<const0>\;
  pipe_drp_fsm(34) <= \<const0>\;
  pipe_drp_fsm(33) <= \<const0>\;
  pipe_drp_fsm(32) <= \<const0>\;
  pipe_drp_fsm(31) <= \<const0>\;
  pipe_drp_fsm(30) <= \<const0>\;
  pipe_drp_fsm(29) <= \<const0>\;
  pipe_drp_fsm(28) <= \<const0>\;
  pipe_drp_fsm(27) <= \<const0>\;
  pipe_drp_fsm(26) <= \<const0>\;
  pipe_drp_fsm(25) <= \<const0>\;
  pipe_drp_fsm(24) <= \<const0>\;
  pipe_drp_fsm(23 downto 0) <= \^pipe_drp_fsm\(23 downto 0);
  pipe_qpll_lock(1 downto 0) <= \^int_qplllock_out\(1 downto 0);
  pipe_qrst_fsm(11) <= \<const0>\;
  pipe_qrst_fsm(10) <= \<const0>\;
  pipe_qrst_fsm(9) <= \<const0>\;
  pipe_qrst_fsm(8) <= \<const0>\;
  pipe_qrst_fsm(7) <= \<const0>\;
  pipe_qrst_fsm(6) <= \<const0>\;
  pipe_qrst_fsm(5) <= \<const0>\;
  pipe_qrst_fsm(4) <= \<const0>\;
  pipe_qrst_fsm(3 downto 0) <= \^pipe_qrst_fsm\(3 downto 0);
  pipe_rxpmaresetdone(7) <= \<const0>\;
  pipe_rxpmaresetdone(6) <= \<const0>\;
  pipe_rxpmaresetdone(5) <= \<const0>\;
  pipe_rxpmaresetdone(4) <= \<const0>\;
  pipe_rxpmaresetdone(3) <= \<const0>\;
  pipe_rxpmaresetdone(2) <= \<const0>\;
  pipe_rxpmaresetdone(1) <= \<const0>\;
  pipe_rxpmaresetdone(0) <= \<const0>\;
  pipe_rxsyncdone(7) <= \<const0>\;
  pipe_rxsyncdone(6) <= \<const0>\;
  pipe_rxsyncdone(5) <= \<const0>\;
  pipe_rxsyncdone(4) <= \<const0>\;
  pipe_rxsyncdone(3) <= \<const0>\;
  pipe_rxsyncdone(2) <= \<const0>\;
  pipe_rxsyncdone(1) <= \<const0>\;
  pipe_rxsyncdone(0) <= \<const0>\;
  pipe_tx_0_sigs(22) <= \<const0>\;
  pipe_tx_0_sigs(21) <= \<const0>\;
  pipe_tx_0_sigs(20) <= \<const0>\;
  pipe_tx_0_sigs(19) <= \<const0>\;
  pipe_tx_0_sigs(18) <= \<const0>\;
  pipe_tx_0_sigs(17) <= \<const0>\;
  pipe_tx_0_sigs(16) <= \<const0>\;
  pipe_tx_0_sigs(15) <= \<const0>\;
  pipe_tx_0_sigs(14) <= \<const0>\;
  pipe_tx_0_sigs(13) <= \<const0>\;
  pipe_tx_0_sigs(12) <= \<const0>\;
  pipe_tx_0_sigs(11) <= \<const0>\;
  pipe_tx_0_sigs(10) <= \<const0>\;
  pipe_tx_0_sigs(9) <= \<const0>\;
  pipe_tx_0_sigs(8) <= \<const0>\;
  pipe_tx_0_sigs(7) <= \<const0>\;
  pipe_tx_0_sigs(6) <= \<const0>\;
  pipe_tx_0_sigs(5) <= \<const0>\;
  pipe_tx_0_sigs(4) <= \<const0>\;
  pipe_tx_0_sigs(3) <= \<const0>\;
  pipe_tx_0_sigs(2) <= \<const0>\;
  pipe_tx_0_sigs(1) <= \<const0>\;
  pipe_tx_0_sigs(0) <= \<const0>\;
  pipe_tx_1_sigs(22) <= \<const0>\;
  pipe_tx_1_sigs(21) <= \<const0>\;
  pipe_tx_1_sigs(20) <= \<const0>\;
  pipe_tx_1_sigs(19) <= \<const0>\;
  pipe_tx_1_sigs(18) <= \<const0>\;
  pipe_tx_1_sigs(17) <= \<const0>\;
  pipe_tx_1_sigs(16) <= \<const0>\;
  pipe_tx_1_sigs(15) <= \<const0>\;
  pipe_tx_1_sigs(14) <= \<const0>\;
  pipe_tx_1_sigs(13) <= \<const0>\;
  pipe_tx_1_sigs(12) <= \<const0>\;
  pipe_tx_1_sigs(11) <= \<const0>\;
  pipe_tx_1_sigs(10) <= \<const0>\;
  pipe_tx_1_sigs(9) <= \<const0>\;
  pipe_tx_1_sigs(8) <= \<const0>\;
  pipe_tx_1_sigs(7) <= \<const0>\;
  pipe_tx_1_sigs(6) <= \<const0>\;
  pipe_tx_1_sigs(5) <= \<const0>\;
  pipe_tx_1_sigs(4) <= \<const0>\;
  pipe_tx_1_sigs(3) <= \<const0>\;
  pipe_tx_1_sigs(2) <= \<const0>\;
  pipe_tx_1_sigs(1) <= \<const0>\;
  pipe_tx_1_sigs(0) <= \<const0>\;
  pipe_tx_2_sigs(22) <= \<const0>\;
  pipe_tx_2_sigs(21) <= \<const0>\;
  pipe_tx_2_sigs(20) <= \<const0>\;
  pipe_tx_2_sigs(19) <= \<const0>\;
  pipe_tx_2_sigs(18) <= \<const0>\;
  pipe_tx_2_sigs(17) <= \<const0>\;
  pipe_tx_2_sigs(16) <= \<const0>\;
  pipe_tx_2_sigs(15) <= \<const0>\;
  pipe_tx_2_sigs(14) <= \<const0>\;
  pipe_tx_2_sigs(13) <= \<const0>\;
  pipe_tx_2_sigs(12) <= \<const0>\;
  pipe_tx_2_sigs(11) <= \<const0>\;
  pipe_tx_2_sigs(10) <= \<const0>\;
  pipe_tx_2_sigs(9) <= \<const0>\;
  pipe_tx_2_sigs(8) <= \<const0>\;
  pipe_tx_2_sigs(7) <= \<const0>\;
  pipe_tx_2_sigs(6) <= \<const0>\;
  pipe_tx_2_sigs(5) <= \<const0>\;
  pipe_tx_2_sigs(4) <= \<const0>\;
  pipe_tx_2_sigs(3) <= \<const0>\;
  pipe_tx_2_sigs(2) <= \<const0>\;
  pipe_tx_2_sigs(1) <= \<const0>\;
  pipe_tx_2_sigs(0) <= \<const0>\;
  pipe_tx_3_sigs(22) <= \<const0>\;
  pipe_tx_3_sigs(21) <= \<const0>\;
  pipe_tx_3_sigs(20) <= \<const0>\;
  pipe_tx_3_sigs(19) <= \<const0>\;
  pipe_tx_3_sigs(18) <= \<const0>\;
  pipe_tx_3_sigs(17) <= \<const0>\;
  pipe_tx_3_sigs(16) <= \<const0>\;
  pipe_tx_3_sigs(15) <= \<const0>\;
  pipe_tx_3_sigs(14) <= \<const0>\;
  pipe_tx_3_sigs(13) <= \<const0>\;
  pipe_tx_3_sigs(12) <= \<const0>\;
  pipe_tx_3_sigs(11) <= \<const0>\;
  pipe_tx_3_sigs(10) <= \<const0>\;
  pipe_tx_3_sigs(9) <= \<const0>\;
  pipe_tx_3_sigs(8) <= \<const0>\;
  pipe_tx_3_sigs(7) <= \<const0>\;
  pipe_tx_3_sigs(6) <= \<const0>\;
  pipe_tx_3_sigs(5) <= \<const0>\;
  pipe_tx_3_sigs(4) <= \<const0>\;
  pipe_tx_3_sigs(3) <= \<const0>\;
  pipe_tx_3_sigs(2) <= \<const0>\;
  pipe_tx_3_sigs(1) <= \<const0>\;
  pipe_tx_3_sigs(0) <= \<const0>\;
  pipe_tx_4_sigs(22) <= \<const0>\;
  pipe_tx_4_sigs(21) <= \<const0>\;
  pipe_tx_4_sigs(20) <= \<const0>\;
  pipe_tx_4_sigs(19) <= \<const0>\;
  pipe_tx_4_sigs(18) <= \<const0>\;
  pipe_tx_4_sigs(17) <= \<const0>\;
  pipe_tx_4_sigs(16) <= \<const0>\;
  pipe_tx_4_sigs(15) <= \<const0>\;
  pipe_tx_4_sigs(14) <= \<const0>\;
  pipe_tx_4_sigs(13) <= \<const0>\;
  pipe_tx_4_sigs(12) <= \<const0>\;
  pipe_tx_4_sigs(11) <= \<const0>\;
  pipe_tx_4_sigs(10) <= \<const0>\;
  pipe_tx_4_sigs(9) <= \<const0>\;
  pipe_tx_4_sigs(8) <= \<const0>\;
  pipe_tx_4_sigs(7) <= \<const0>\;
  pipe_tx_4_sigs(6) <= \<const0>\;
  pipe_tx_4_sigs(5) <= \<const0>\;
  pipe_tx_4_sigs(4) <= \<const0>\;
  pipe_tx_4_sigs(3) <= \<const0>\;
  pipe_tx_4_sigs(2) <= \<const0>\;
  pipe_tx_4_sigs(1) <= \<const0>\;
  pipe_tx_4_sigs(0) <= \<const0>\;
  pipe_tx_5_sigs(22) <= \<const0>\;
  pipe_tx_5_sigs(21) <= \<const0>\;
  pipe_tx_5_sigs(20) <= \<const0>\;
  pipe_tx_5_sigs(19) <= \<const0>\;
  pipe_tx_5_sigs(18) <= \<const0>\;
  pipe_tx_5_sigs(17) <= \<const0>\;
  pipe_tx_5_sigs(16) <= \<const0>\;
  pipe_tx_5_sigs(15) <= \<const0>\;
  pipe_tx_5_sigs(14) <= \<const0>\;
  pipe_tx_5_sigs(13) <= \<const0>\;
  pipe_tx_5_sigs(12) <= \<const0>\;
  pipe_tx_5_sigs(11) <= \<const0>\;
  pipe_tx_5_sigs(10) <= \<const0>\;
  pipe_tx_5_sigs(9) <= \<const0>\;
  pipe_tx_5_sigs(8) <= \<const0>\;
  pipe_tx_5_sigs(7) <= \<const0>\;
  pipe_tx_5_sigs(6) <= \<const0>\;
  pipe_tx_5_sigs(5) <= \<const0>\;
  pipe_tx_5_sigs(4) <= \<const0>\;
  pipe_tx_5_sigs(3) <= \<const0>\;
  pipe_tx_5_sigs(2) <= \<const0>\;
  pipe_tx_5_sigs(1) <= \<const0>\;
  pipe_tx_5_sigs(0) <= \<const0>\;
  pipe_tx_6_sigs(22) <= \<const0>\;
  pipe_tx_6_sigs(21) <= \<const0>\;
  pipe_tx_6_sigs(20) <= \<const0>\;
  pipe_tx_6_sigs(19) <= \<const0>\;
  pipe_tx_6_sigs(18) <= \<const0>\;
  pipe_tx_6_sigs(17) <= \<const0>\;
  pipe_tx_6_sigs(16) <= \<const0>\;
  pipe_tx_6_sigs(15) <= \<const0>\;
  pipe_tx_6_sigs(14) <= \<const0>\;
  pipe_tx_6_sigs(13) <= \<const0>\;
  pipe_tx_6_sigs(12) <= \<const0>\;
  pipe_tx_6_sigs(11) <= \<const0>\;
  pipe_tx_6_sigs(10) <= \<const0>\;
  pipe_tx_6_sigs(9) <= \<const0>\;
  pipe_tx_6_sigs(8) <= \<const0>\;
  pipe_tx_6_sigs(7) <= \<const0>\;
  pipe_tx_6_sigs(6) <= \<const0>\;
  pipe_tx_6_sigs(5) <= \<const0>\;
  pipe_tx_6_sigs(4) <= \<const0>\;
  pipe_tx_6_sigs(3) <= \<const0>\;
  pipe_tx_6_sigs(2) <= \<const0>\;
  pipe_tx_6_sigs(1) <= \<const0>\;
  pipe_tx_6_sigs(0) <= \<const0>\;
  pipe_tx_7_sigs(22) <= \<const0>\;
  pipe_tx_7_sigs(21) <= \<const0>\;
  pipe_tx_7_sigs(20) <= \<const0>\;
  pipe_tx_7_sigs(19) <= \<const0>\;
  pipe_tx_7_sigs(18) <= \<const0>\;
  pipe_tx_7_sigs(17) <= \<const0>\;
  pipe_tx_7_sigs(16) <= \<const0>\;
  pipe_tx_7_sigs(15) <= \<const0>\;
  pipe_tx_7_sigs(14) <= \<const0>\;
  pipe_tx_7_sigs(13) <= \<const0>\;
  pipe_tx_7_sigs(12) <= \<const0>\;
  pipe_tx_7_sigs(11) <= \<const0>\;
  pipe_tx_7_sigs(10) <= \<const0>\;
  pipe_tx_7_sigs(9) <= \<const0>\;
  pipe_tx_7_sigs(8) <= \<const0>\;
  pipe_tx_7_sigs(7) <= \<const0>\;
  pipe_tx_7_sigs(6) <= \<const0>\;
  pipe_tx_7_sigs(5) <= \<const0>\;
  pipe_tx_7_sigs(4) <= \<const0>\;
  pipe_tx_7_sigs(3) <= \<const0>\;
  pipe_tx_7_sigs(2) <= \<const0>\;
  pipe_tx_7_sigs(1) <= \<const0>\;
  pipe_tx_7_sigs(0) <= \<const0>\;
  qpll_drp_clk <= \<const0>\;
  qpll_drp_gen3 <= \<const0>\;
  qpll_drp_ovrd <= \<const0>\;
  qpll_drp_rst_n <= \<const0>\;
  qpll_drp_start <= \<const0>\;
  qpll_qplld <= \<const0>\;
  qpll_qpllreset(1) <= \<const0>\;
  qpll_qpllreset(0) <= \<const0>\;
  startup_cfgclk <= \<const0>\;
  startup_cfgmclk <= \<const0>\;
  startup_eos <= \<const0>\;
  startup_preq <= \<const0>\;
  user_app_rdy <= \<const1>\;
  user_clk_out <= \^int_userclk2_out\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
inst: entity work.PCIeGen1x8If64_PCIeGen1x8If64_core_top
     port map (
      EQ_GEN3 => pipe_gen3_out,
      INT_OOBCLK_OUT => \^int_pipe_rxusrclk_out\,
      INT_USERCLK2_OUT => \^int_userclk2_out\,
      PIPE_DRP_FSM(23 downto 0) => \^pipe_drp_fsm\(23 downto 0),
      PIPE_RATE_FSM(39 downto 0) => pipe_rate_fsm(39 downto 0),
      PIPE_SYNC_FSM_TX(47 downto 0) => pipe_sync_fsm_tx(47 downto 0),
      cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en,
      cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en,
      cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0),
      cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received,
      cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en,
      cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received,
      cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en,
      cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received,
      cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en,
      cfg_bridge_serr_en => cfg_bridge_serr_en,
      cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0),
      cfg_command(4) => \^cfg_command\(10),
      cfg_command(3) => \^cfg_command\(8),
      cfg_command(2 downto 0) => \^cfg_command\(2 downto 0),
      cfg_dcommand(14 downto 0) => \^cfg_dcommand\(14 downto 0),
      cfg_dcommand2(11 downto 0) => \^cfg_dcommand2\(11 downto 0),
      cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0),
      cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0),
      cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0),
      cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0),
      cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0),
      cfg_dstatus(3 downto 0) => \^cfg_dstatus\(3 downto 0),
      cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0),
      cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set,
      cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked,
      cfg_err_cor => cfg_err_cor,
      cfg_err_cpl_abort => cfg_err_cpl_abort,
      cfg_err_cpl_rdy => cfg_err_cpl_rdy,
      cfg_err_cpl_timeout => cfg_err_cpl_timeout,
      cfg_err_cpl_unexpect => cfg_err_cpl_unexpect,
      cfg_err_ecrc => cfg_err_ecrc,
      cfg_err_internal_cor => cfg_err_internal_cor,
      cfg_err_internal_uncor => cfg_err_internal_uncor,
      cfg_err_locked => cfg_err_locked,
      cfg_err_malformed => cfg_err_malformed,
      cfg_err_mc_blocked => cfg_err_mc_blocked,
      cfg_err_norecovery => cfg_err_norecovery,
      cfg_err_poisoned => cfg_err_poisoned,
      cfg_err_posted => cfg_err_posted,
      cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0),
      cfg_err_ur => cfg_err_ur,
      cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0),
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0),
      cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_msixenable => cfg_interrupt_msixenable,
      cfg_interrupt_msixfm => cfg_interrupt_msixfm,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_interrupt_stat => cfg_interrupt_stat,
      cfg_lcommand(10 downto 2) => \^cfg_lcommand\(11 downto 3),
      cfg_lcommand(1 downto 0) => \^cfg_lcommand\(1 downto 0),
      cfg_lstatus(9 downto 7) => \^cfg_lstatus\(15 downto 13),
      cfg_lstatus(6) => \^cfg_lstatus\(11),
      cfg_lstatus(5 downto 2) => \^cfg_lstatus\(7 downto 4),
      cfg_lstatus(1 downto 0) => \^cfg_lstatus\(1 downto 0),
      cfg_mgmt_byte_en(3 downto 0) => cfg_mgmt_byte_en(3 downto 0),
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw,
      cfg_msg_data(15 downto 0) => cfg_msg_data(15 downto 0),
      cfg_msg_received => cfg_msg_received,
      cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a,
      cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b,
      cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c,
      cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d,
      cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a,
      cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b,
      cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c,
      cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d,
      cfg_msg_received_err_cor => cfg_msg_received_err_cor,
      cfg_msg_received_err_fatal => cfg_msg_received_err_fatal,
      cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal,
      cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak,
      cfg_msg_received_pm_pme => cfg_msg_received_pm_pme,
      cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack,
      cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit,
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0),
      cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0),
      cfg_pm_force_state_en => cfg_pm_force_state_en,
      cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s,
      cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1,
      cfg_pm_wake => cfg_pm_wake,
      cfg_pmcsr_pme_en => cfg_pmcsr_pme_en,
      cfg_pmcsr_pme_status => cfg_pmcsr_pme_status,
      cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0),
      cfg_received_func_lvl_rst => cfg_received_func_lvl_rst,
      cfg_root_control_pme_int_en => cfg_root_control_pme_int_en,
      cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en,
      cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en,
      cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en,
      cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse,
      cfg_to_turnoff => cfg_to_turnoff,
      cfg_trn_pending => \^cfg_trn_pending\,
      cfg_turnoff_ok => cfg_turnoff_ok,
      cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0),
      ext_ch_gt_drpaddr(71 downto 0) => ext_ch_gt_drpaddr(71 downto 0),
      ext_ch_gt_drpclk => \^ext_ch_gt_drpclk\,
      ext_ch_gt_drpdi(127 downto 0) => ext_ch_gt_drpdi(127 downto 0),
      ext_ch_gt_drpdo(127 downto 0) => ext_ch_gt_drpdo(127 downto 0),
      ext_ch_gt_drpen(7 downto 0) => ext_ch_gt_drpen(7 downto 0),
      ext_ch_gt_drprdy(7 downto 0) => ext_ch_gt_drprdy(7 downto 0),
      ext_ch_gt_drpwe(7 downto 0) => ext_ch_gt_drpwe(7 downto 0),
      fc_cpld(11 downto 0) => fc_cpld(11 downto 0),
      fc_cplh(7 downto 0) => fc_cplh(7 downto 0),
      fc_npd(11 downto 0) => fc_npd(11 downto 0),
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_pd(11 downto 0) => fc_pd(11 downto 0),
      fc_ph(7 downto 0) => fc_ph(7 downto 0),
      fc_sel(2 downto 0) => fc_sel(2 downto 0),
      gt_ch_drp_rdy(7 downto 0) => gt_ch_drp_rdy(7 downto 0),
      int_mmcm_lock_out => int_mmcm_lock_out,
      int_pclk_sel_slave(7 downto 0) => int_pclk_sel_slave(7 downto 0),
      int_qplllock_out(1 downto 0) => \^int_qplllock_out\(1 downto 0),
      int_qplloutclk_out(1 downto 0) => int_qplloutclk_out(1 downto 0),
      int_qplloutrefclk_out(1 downto 0) => int_qplloutrefclk_out(1 downto 0),
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(7 downto 0) => m_axis_rx_tkeep(7 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(21 downto 0) => m_axis_rx_tuser(21 downto 0),
      m_axis_rx_tvalid => m_axis_rx_tvalid,
      \out\(1) => pipe_rst_fsm(4),
      \out\(0) => pipe_rst_idle,
      pci_exp_rxn(7 downto 0) => pci_exp_rxn(7 downto 0),
      pci_exp_rxp(7 downto 0) => pci_exp_rxp(7 downto 0),
      pci_exp_txn(7 downto 0) => pci_exp_txn(7 downto 0),
      pci_exp_txp(7 downto 0) => pci_exp_txp(7 downto 0),
      pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0),
      pcie_drp_clk => pcie_drp_clk,
      pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0),
      pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0),
      pcie_drp_en => pcie_drp_en,
      pcie_drp_rdy => pcie_drp_rdy,
      pcie_drp_we => pcie_drp_we,
      pipe_cpll_lock(7 downto 0) => pipe_cpll_lock(7 downto 0),
      pipe_dmonitorout(63 downto 56) => \^pipe_dmonitorout\(112 downto 105),
      pipe_dmonitorout(55 downto 48) => \^pipe_dmonitorout\(97 downto 90),
      pipe_dmonitorout(47 downto 40) => \^pipe_dmonitorout\(82 downto 75),
      pipe_dmonitorout(39 downto 32) => \^pipe_dmonitorout\(67 downto 60),
      pipe_dmonitorout(31 downto 24) => \^pipe_dmonitorout\(52 downto 45),
      pipe_dmonitorout(23 downto 16) => \^pipe_dmonitorout\(37 downto 30),
      pipe_dmonitorout(15 downto 8) => \^pipe_dmonitorout\(22 downto 15),
      pipe_dmonitorout(7 downto 0) => \^pipe_dmonitorout\(7 downto 0),
      pipe_eyescandataerror(7 downto 0) => pipe_eyescandataerror(7 downto 0),
      pipe_mmcm_rst_n => pipe_mmcm_rst_n,
      pipe_pclk_sel_out(7 downto 0) => pipe_pclk_sel_out(7 downto 0),
      pipe_qrst_fsm(3 downto 0) => \^pipe_qrst_fsm\(3 downto 0),
      pipe_qrst_idle => pipe_qrst_idle,
      pipe_rate_idle => pipe_rate_idle,
      pipe_rst_fsm(3 downto 0) => pipe_rst_fsm(3 downto 0),
      pipe_rxbufstatus(23 downto 0) => pipe_rxbufstatus(23 downto 0),
      pipe_rxcommadet(7 downto 0) => pipe_rxcommadet(7 downto 0),
      pipe_rxdisperr(63 downto 0) => pipe_rxdisperr(63 downto 0),
      pipe_rxdlysresetdone(7 downto 0) => pipe_rxdlysresetdone(7 downto 0),
      pipe_rxnotintable(63 downto 0) => pipe_rxnotintable(63 downto 0),
      pipe_rxoutclk_out(7 downto 0) => pipe_rxoutclk_out(7 downto 0),
      pipe_rxphaligndone(7 downto 0) => pipe_rxphaligndone(7 downto 0),
      pipe_rxprbserr(7 downto 0) => pipe_rxprbserr(7 downto 0),
      pipe_rxstatus(23 downto 0) => pipe_rxstatus(23 downto 0),
      pipe_sync_fsm_rx(55 downto 0) => pipe_sync_fsm_rx(55 downto 0),
      pipe_txdlysresetdone(7 downto 0) => pipe_txdlysresetdone(7 downto 0),
      pipe_txinhibit(7 downto 0) => pipe_txinhibit(7 downto 0),
      pipe_txoutclk_out => pipe_txoutclk_out,
      pipe_txphaligndone(7 downto 0) => pipe_txphaligndone(7 downto 0),
      pipe_txphinitdone(7 downto 0) => pipe_txphinitdone(7 downto 0),
      pl_directed_change_done => pl_directed_change_done,
      pl_directed_link_auton => pl_directed_link_auton,
      pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0),
      pl_directed_link_speed => pl_directed_link_speed,
      pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0),
      pl_downstream_deemph_source => pl_downstream_deemph_source,
      pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0),
      pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0),
      pl_link_gen2_cap => pl_link_gen2_cap,
      pl_link_partner_gen2_supported => pl_link_partner_gen2_supported,
      pl_link_upcfg_cap => pl_link_upcfg_cap,
      pl_ltssm_state(5 downto 0) => pl_ltssm_state(5 downto 0),
      pl_phy_lnk_up => pl_phy_lnk_up,
      pl_received_hot_rst => pl_received_hot_rst,
      pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0),
      pl_sel_lnk_rate => pl_sel_lnk_rate,
      pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0),
      pl_transmit_hot_rst => pl_transmit_hot_rst,
      pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0),
      pl_upstream_prefer_deemph => pl_upstream_prefer_deemph,
      rx_np_ok => rx_np_ok,
      rx_np_req => rx_np_req,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(7),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => s_axis_tx_tready,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n,
      tx_buf_av(5 downto 0) => tx_buf_av(5 downto 0),
      tx_cfg_gnt => tx_cfg_gnt,
      tx_cfg_req => tx_cfg_req,
      tx_err_drop => tx_err_drop,
      user_lnk_up => user_lnk_up,
      user_reset_out => user_reset_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PCIeGen1x8If64 is
  port (
    pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 );
    user_clk_out : out STD_LOGIC;
    user_reset_out : out STD_LOGIC;
    user_lnk_up : out STD_LOGIC;
    user_app_rdy : out STD_LOGIC;
    tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    tx_cfg_req : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    s_axis_tx_tready : out STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tx_cfg_gnt : in STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    m_axis_rx_tvalid : out STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    cfg_trn_pending : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_to_turnoff : out STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pm_wake : in STD_LOGIC;
    cfg_pm_send_pme_to : in STD_LOGIC;
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    sys_clk : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    pcie_drp_clk : in STD_LOGIC;
    pcie_drp_en : in STD_LOGIC;
    pcie_drp_we : in STD_LOGIC;
    pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_rdy : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of PCIeGen1x8If64 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of PCIeGen1x8If64 : entity is "PCIeGen1x8If64,PCIeGen1x8If64_pcie2_top,{}";
  attribute core_generation_info : string;
  attribute core_generation_info of PCIeGen1x8If64 : entity is "PCIeGen1x8If64,PCIeGen1x8If64_pcie2_top,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=pcie_7x,x_ipVersion=3.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,c_component_name=PCIeGen1x8If64,dev_port_type=0000,c_dev_port_type=0,c_header_type=00,c_upstream_facing=TRUE,max_lnk_wdt=001000,max_lnk_spd=1,c_gen1=false,pci_exp_int_freq=3,c_pcie_fast_config=0,bar_0=FFFFFC00,bar_1=00000000,bar_2=00000000,bar_3=00000000,bar_4=00000000,bar_5=00000000,xrom_bar=00000000,cost_table=1,ven_id=10EE,dev_id=7018,rev_id=00,subsys_ven_id=10EE,subsys_id=0007,class_code=058000,cardbus_cis_ptr=00000000,cap_ver=2,c_pcie_cap_slot_implemented=FALSE,mps=010,cmps=2,ext_tag_fld_sup=TRUE,c_dev_control_ext_tag_default=FALSE,phantm_func_sup=00,c_phantom_functions=0,ep_l0s_accpt_lat=000,c_ep_l0s_accpt_lat=0,ep_l1_accpt_lat=111,c_ep_l1_accpt_lat=7,c_cpl_timeout_disable_sup=FALSE,c_cpl_timeout_range=0010,c_cpl_timeout_ranges_sup=2,c_buf_opt_bma=FALSE,c_perf_level_high=TRUE,c_tx_last_tlp=29,c_rx_ram_limit=7FF,c_fc_ph=4,c_fc_pd=64,c_fc_nph=4,c_fc_npd=8,c_fc_cplh=72,c_fc_cpld=850,c_cpl_inf=TRUE,c_cpl_infinite=TRUE,c_dll_lnk_actv_cap=FALSE,c_trgt_lnk_spd=0,c_hw_auton_spd_disable=FALSE,c_de_emph=FALSE,slot_clk=TRUE,c_rcb=0,c_root_cap_crs=FALSE,c_slot_cap_attn_butn=FALSE,c_slot_cap_attn_ind=FALSE,c_slot_cap_pwr_ctrl=FALSE,c_slot_cap_pwr_ind=FALSE,c_slot_cap_hotplug_surprise=FALSE,c_slot_cap_hotplug_cap=FALSE,c_slot_cap_mrl=FALSE,c_slot_cap_elec_interlock=FALSE,c_slot_cap_no_cmd_comp_sup=FALSE,c_slot_cap_pwr_limit_value=0,c_slot_cap_pwr_limit_scale=0,c_slot_cap_physical_slot_num=0,intx=FALSE,int_pin=0,c_msi_cap_on=TRUE,c_pm_cap_next_ptr=48,c_msi_64b_addr=TRUE,c_msi=0,c_msi_mult_msg_extn=0,c_msi_per_vctr_mask_cap=FALSE,c_msix_cap_on=FALSE,c_msix_next_ptr=00,c_pcie_cap_next_ptr=00,c_msix_table_size=000,c_msix_table_offset=0,c_msix_table_bir=0,c_msix_pba_offset=0,c_msix_pba_bir=0,dsi=0,c_dsi_bool=FALSE,d1_sup=0,c_d1_support=FALSE,d2_sup=0,c_d2_support=FALSE,pme_sup=0F,c_pme_support=0F,no_soft_rst=TRUE,pwr_con_d0_state=00,con_scl_fctr_d0_state=0,pwr_con_d1_state=00,con_scl_fctr_d1_state=0,pwr_con_d2_state=00,con_scl_fctr_d2_state=0,pwr_con_d3_state=00,con_scl_fctr_d3_state=0,pwr_dis_d0_state=00,dis_scl_fctr_d0_state=0,pwr_dis_d1_state=00,dis_scl_fctr_d1_state=0,pwr_dis_d2_state=00,dis_scl_fctr_d2_state=0,pwr_dis_d3_state=00,dis_scl_fctr_d3_state=0,c_dsn_cap_enabled=TRUE,c_dsn_base_ptr=100,c_vc_cap_enabled=FALSE,c_vc_base_ptr=000,c_vc_cap_reject_snoop=FALSE,c_vsec_cap_enabled=FALSE,c_vsec_base_ptr=000,c_vsec_next_ptr=000,c_dsn_next_ptr=000,c_vc_next_ptr=000,c_pci_cfg_space_addr=3F,c_ext_pci_cfg_space_addr=3FF,c_last_cfg_dw=10C,c_enable_msg_route=00000000000,bram_lat=0,c_rx_raddr_lat=0,c_rx_rdata_lat=2,c_rx_write_lat=0,c_tx_raddr_lat=0,c_tx_rdata_lat=2,c_tx_write_lat=0,c_ll_ack_timeout_enable=FALSE,c_ll_ack_timeout_function=0,c_ll_ack_timeout=0000,c_ll_replay_timeout_enable=FALSE,c_ll_replay_timeout_func=1,c_ll_replay_timeout=0000,c_dis_lane_reverse=TRUE,c_upconfig_capable=TRUE,c_disable_scrambling=FALSE,c_disable_tx_aspm_l0s=FALSE,c_pcie_dbg_ports=TRUE,pci_exp_ref_freq=0,c_xlnx_ref_board=VC707,c_pcie_blk_locn=3,c_ur_atomic=FALSE,c_dev_cap2_atomicop32_completer_supported=FALSE,c_dev_cap2_atomicop64_completer_supported=FALSE,c_dev_cap2_cas128_completer_supported=FALSE,c_dev_cap2_tph_completer_supported=00,c_dev_cap2_ari_forwarding_supported=FALSE,c_dev_cap2_atomicop_routing_supported=FALSE,c_link_cap_aspm_optionality=FALSE,c_aer_cap_on=FALSE,c_aer_base_ptr=000,c_aer_cap_nextptr=000,c_aer_cap_ecrc_check_capable=FALSE,c_aer_cap_ecrc_gen_capable=FALSE,c_aer_cap_multiheader=FALSE,c_aer_cap_permit_rooterr_update=FALSE,c_rbar_cap_on=FALSE,c_rbar_base_ptr=000,c_rbar_cap_nextptr=000,c_rbar_num=0,c_rbar_cap_sup0=00001,c_rbar_cap_index0=0,c_rbar_cap_control_encodedbar0=00,c_rbar_cap_sup1=00001,c_rbar_cap_index1=0,c_rbar_cap_control_encodedbar1=00,c_rbar_cap_sup2=00001,c_rbar_cap_index2=0,c_rbar_cap_control_encodedbar2=00,c_rbar_cap_sup3=00001,c_rbar_cap_index3=0,c_rbar_cap_control_encodedbar3=00,c_rbar_cap_sup4=00001,c_rbar_cap_index4=0,c_rbar_cap_control_encodedbar4=00,c_rbar_cap_sup5=00001,c_rbar_cap_index5=0,c_rbar_cap_control_encodedbar5=00,c_recrc_check=0,c_recrc_check_trim=FALSE,c_disable_rx_poisoned_resp=FALSE,c_trn_np_fc=TRUE,c_ur_inv_req=TRUE,c_ur_prs_response=TRUE,c_silicon_rev=2,c_aer_cap_optional_err_support=000000,LINK_CAP_MAX_LINK_WIDTH=8,C_DATA_WIDTH=64,PIPE_SIM=FALSE,PCIE_EXT_CLK=FALSE,PCIE_EXT_GT_COMMON=FALSE,EXT_CH_GT_DRP=FALSE,TRANSCEIVER_CTRL_STATUS_PORTS=FALSE,SHARED_LOGIC_IN_CORE=FALSE,ERR_REPORTING_IF=FALSE,PL_INTERFACE=FALSE,CFG_MGMT_IF=FALSE,CFG_CTL_IF=TRUE,CFG_STATUS_IF=TRUE,RCV_MSG_IF=FALSE,CFG_FC_IF=TRUE,EXT_PIPE_INTERFACE=FALSE,EXT_STARTUP_PRIMITIVE=FALSE,KEEP_WIDTH=8,PCIE_ASYNC_EN=FALSE}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of PCIeGen1x8If64 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of PCIeGen1x8If64 : entity is "PCIeGen1x8If64_pcie2_top,Vivado 2015.2";
end PCIeGen1x8If64;

architecture STRUCTURE of PCIeGen1x8If64 is
  signal NLW_U0_cfg_aer_ecrc_check_en_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_aer_ecrc_gen_en_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_err_aer_headerlog_set_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_err_cpl_rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_mgmt_rd_wr_done_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_assert_int_a_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_assert_int_b_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_assert_int_c_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_assert_int_d_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_deassert_int_a_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_deassert_int_b_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_deassert_int_c_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_deassert_int_d_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_err_cor_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_err_fatal_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_err_non_fatal_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_pm_as_nak_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_pm_pme_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_pme_to_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_setslotpowerlimit_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_ext_ch_gt_drpclk_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_dclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_mmcm_lock_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_oobclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_pclk_out_slave_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_pipe_rxusrclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_userclk1_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_userclk2_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pipe_gen3_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pipe_qrst_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pipe_rate_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pipe_rst_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pipe_txoutclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pl_directed_change_done_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pl_link_gen2_cap_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pl_link_partner_gen2_supported_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pl_link_upcfg_cap_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pl_phy_lnk_up_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pl_received_hot_rst_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pl_sel_lnk_rate_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_drp_clk_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_drp_gen3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_drp_ovrd_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_drp_rst_n_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_drp_start_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_qplld_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_startup_cfgclk_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_startup_cfgmclk_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_startup_eos_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_startup_preq_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_mgmt_do_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_cfg_msg_data_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_U0_common_commands_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_U0_ext_ch_gt_drpdo_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
  signal NLW_U0_ext_ch_gt_drprdy_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_gt_ch_drp_rdy_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_icap_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_int_qplllock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_int_qplloutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_int_qplloutrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_int_rxoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_cpll_lock_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_debug_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_pipe_debug_0_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_debug_1_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_debug_2_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_debug_3_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_debug_4_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_debug_5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_debug_6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_debug_7_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_debug_8_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_debug_9_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_dmonitorout_UNCONNECTED : STD_LOGIC_VECTOR ( 119 downto 0 );
  signal NLW_U0_pipe_drp_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 55 downto 0 );
  signal NLW_U0_pipe_eyescandataerror_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_pclk_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_qpll_lock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_qrst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_U0_pipe_rate_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 39 downto 0 );
  signal NLW_U0_pipe_rst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_pipe_rxbufstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal NLW_U0_pipe_rxcommadet_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_rxdisperr_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_pipe_rxdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_rxnotintable_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_pipe_rxoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_rxphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_rxpmaresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_rxprbserr_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_rxstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal NLW_U0_pipe_rxsyncdone_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_sync_fsm_rx_UNCONNECTED : STD_LOGIC_VECTOR ( 55 downto 0 );
  signal NLW_U0_pipe_sync_fsm_tx_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal NLW_U0_pipe_tx_0_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal NLW_U0_pipe_tx_1_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal NLW_U0_pipe_tx_2_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal NLW_U0_pipe_tx_3_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal NLW_U0_pipe_tx_4_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal NLW_U0_pipe_tx_5_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal NLW_U0_pipe_tx_6_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal NLW_U0_pipe_tx_7_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal NLW_U0_pipe_txdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_txphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pipe_txphinitdone_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_pl_initial_link_width_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_pl_lane_reversal_mode_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pl_ltssm_state_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_U0_pl_rx_pm_state_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pl_sel_lnk_width_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pl_tx_pm_state_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_qpll_qpllreset_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute CFG_CTL_IF : string;
  attribute CFG_CTL_IF of U0 : label is "TRUE";
  attribute CFG_FC_IF : string;
  attribute CFG_FC_IF of U0 : label is "TRUE";
  attribute CFG_MGMT_IF : string;
  attribute CFG_MGMT_IF of U0 : label is "FALSE";
  attribute CFG_STATUS_IF : string;
  attribute CFG_STATUS_IF of U0 : label is "TRUE";
  attribute CLASS_CODE : string;
  attribute CLASS_CODE of U0 : label is "058000";
  attribute C_DATA_WIDTH : integer;
  attribute C_DATA_WIDTH of U0 : label is 64;
  attribute ERR_REPORTING_IF : string;
  attribute ERR_REPORTING_IF of U0 : label is "FALSE";
  attribute EXT_CH_GT_DRP : string;
  attribute EXT_CH_GT_DRP of U0 : label is "FALSE";
  attribute EXT_PIPE_INTERFACE : string;
  attribute EXT_PIPE_INTERFACE of U0 : label is "FALSE";
  attribute EXT_STARTUP_PRIMITIVE : string;
  attribute EXT_STARTUP_PRIMITIVE of U0 : label is "FALSE";
  attribute KEEP_WIDTH : integer;
  attribute KEEP_WIDTH of U0 : label is 8;
  attribute LINK_CAP_MAX_LINK_WIDTH : integer;
  attribute LINK_CAP_MAX_LINK_WIDTH of U0 : label is 8;
  attribute PCIE_ASYNC_EN : string;
  attribute PCIE_ASYNC_EN of U0 : label is "FALSE";
  attribute PCIE_EXT_CLK : string;
  attribute PCIE_EXT_CLK of U0 : label is "FALSE";
  attribute PCIE_EXT_GT_COMMON : string;
  attribute PCIE_EXT_GT_COMMON of U0 : label is "FALSE";
  attribute PIPE_SIM : string;
  attribute PIPE_SIM of U0 : label is "FALSE";
  attribute PL_INTERFACE : string;
  attribute PL_INTERFACE of U0 : label is "FALSE";
  attribute RCV_MSG_IF : string;
  attribute RCV_MSG_IF of U0 : label is "FALSE";
  attribute SHARED_LOGIC_IN_CORE : string;
  attribute SHARED_LOGIC_IN_CORE of U0 : label is "FALSE";
  attribute TRANSCEIVER_CTRL_STATUS_PORTS : string;
  attribute TRANSCEIVER_CTRL_STATUS_PORTS of U0 : label is "FALSE";
  attribute bar_0 : string;
  attribute bar_0 of U0 : label is "FFFFFC00";
  attribute bar_1 : string;
  attribute bar_1 of U0 : label is "00000000";
  attribute bar_2 : string;
  attribute bar_2 of U0 : label is "00000000";
  attribute bar_3 : string;
  attribute bar_3 of U0 : label is "00000000";
  attribute bar_4 : string;
  attribute bar_4 of U0 : label is "00000000";
  attribute bar_5 : string;
  attribute bar_5 of U0 : label is "00000000";
  attribute bram_lat : string;
  attribute bram_lat of U0 : label is "0";
  attribute c_aer_base_ptr : string;
  attribute c_aer_base_ptr of U0 : label is "000";
  attribute c_aer_cap_ecrc_check_capable : string;
  attribute c_aer_cap_ecrc_check_capable of U0 : label is "FALSE";
  attribute c_aer_cap_ecrc_gen_capable : string;
  attribute c_aer_cap_ecrc_gen_capable of U0 : label is "FALSE";
  attribute c_aer_cap_multiheader : string;
  attribute c_aer_cap_multiheader of U0 : label is "FALSE";
  attribute c_aer_cap_nextptr : string;
  attribute c_aer_cap_nextptr of U0 : label is "000";
  attribute c_aer_cap_on : string;
  attribute c_aer_cap_on of U0 : label is "FALSE";
  attribute c_aer_cap_optional_err_support : string;
  attribute c_aer_cap_optional_err_support of U0 : label is "000000";
  attribute c_aer_cap_permit_rooterr_update : string;
  attribute c_aer_cap_permit_rooterr_update of U0 : label is "FALSE";
  attribute c_buf_opt_bma : string;
  attribute c_buf_opt_bma of U0 : label is "FALSE";
  attribute c_component_name : string;
  attribute c_component_name of U0 : label is "PCIeGen1x8If64";
  attribute c_cpl_inf : string;
  attribute c_cpl_inf of U0 : label is "TRUE";
  attribute c_cpl_infinite : string;
  attribute c_cpl_infinite of U0 : label is "TRUE";
  attribute c_cpl_timeout_disable_sup : string;
  attribute c_cpl_timeout_disable_sup of U0 : label is "FALSE";
  attribute c_cpl_timeout_range : string;
  attribute c_cpl_timeout_range of U0 : label is "0010";
  attribute c_cpl_timeout_ranges_sup : string;
  attribute c_cpl_timeout_ranges_sup of U0 : label is "2";
  attribute c_d1_support : string;
  attribute c_d1_support of U0 : label is "FALSE";
  attribute c_d2_support : string;
  attribute c_d2_support of U0 : label is "FALSE";
  attribute c_de_emph : string;
  attribute c_de_emph of U0 : label is "FALSE";
  attribute c_dev_cap2_ari_forwarding_supported : string;
  attribute c_dev_cap2_ari_forwarding_supported of U0 : label is "FALSE";
  attribute c_dev_cap2_atomicop32_completer_supported : string;
  attribute c_dev_cap2_atomicop32_completer_supported of U0 : label is "FALSE";
  attribute c_dev_cap2_atomicop64_completer_supported : string;
  attribute c_dev_cap2_atomicop64_completer_supported of U0 : label is "FALSE";
  attribute c_dev_cap2_atomicop_routing_supported : string;
  attribute c_dev_cap2_atomicop_routing_supported of U0 : label is "FALSE";
  attribute c_dev_cap2_cas128_completer_supported : string;
  attribute c_dev_cap2_cas128_completer_supported of U0 : label is "FALSE";
  attribute c_dev_cap2_tph_completer_supported : string;
  attribute c_dev_cap2_tph_completer_supported of U0 : label is "00";
  attribute c_dev_control_ext_tag_default : string;
  attribute c_dev_control_ext_tag_default of U0 : label is "FALSE";
  attribute c_dev_port_type : string;
  attribute c_dev_port_type of U0 : label is "0";
  attribute c_dis_lane_reverse : string;
  attribute c_dis_lane_reverse of U0 : label is "TRUE";
  attribute c_disable_rx_poisoned_resp : string;
  attribute c_disable_rx_poisoned_resp of U0 : label is "FALSE";
  attribute c_disable_scrambling : string;
  attribute c_disable_scrambling of U0 : label is "FALSE";
  attribute c_disable_tx_aspm_l0s : string;
  attribute c_disable_tx_aspm_l0s of U0 : label is "FALSE";
  attribute c_dll_lnk_actv_cap : string;
  attribute c_dll_lnk_actv_cap of U0 : label is "FALSE";
  attribute c_dsi_bool : string;
  attribute c_dsi_bool of U0 : label is "FALSE";
  attribute c_dsn_base_ptr : string;
  attribute c_dsn_base_ptr of U0 : label is "100";
  attribute c_dsn_cap_enabled : string;
  attribute c_dsn_cap_enabled of U0 : label is "TRUE";
  attribute c_dsn_next_ptr : string;
  attribute c_dsn_next_ptr of U0 : label is "000";
  attribute c_enable_msg_route : string;
  attribute c_enable_msg_route of U0 : label is "00000000000";
  attribute c_ep_l0s_accpt_lat : string;
  attribute c_ep_l0s_accpt_lat of U0 : label is "0";
  attribute c_ep_l1_accpt_lat : string;
  attribute c_ep_l1_accpt_lat of U0 : label is "7";
  attribute c_ext_pci_cfg_space_addr : string;
  attribute c_ext_pci_cfg_space_addr of U0 : label is "3FF";
  attribute c_external_clocking : string;
  attribute c_external_clocking of U0 : label is "TRUE";
  attribute c_fc_cpld : string;
  attribute c_fc_cpld of U0 : label is "850";
  attribute c_fc_cplh : string;
  attribute c_fc_cplh of U0 : label is "72";
  attribute c_fc_npd : string;
  attribute c_fc_npd of U0 : label is "8";
  attribute c_fc_nph : string;
  attribute c_fc_nph of U0 : label is "4";
  attribute c_fc_pd : string;
  attribute c_fc_pd of U0 : label is "64";
  attribute c_fc_ph : string;
  attribute c_fc_ph of U0 : label is "4";
  attribute c_gen1 : string;
  attribute c_gen1 of U0 : label is "FALSE";
  attribute c_header_type : string;
  attribute c_header_type of U0 : label is "00";
  attribute c_hw_auton_spd_disable : string;
  attribute c_hw_auton_spd_disable of U0 : label is "FALSE";
  attribute c_int_width : integer;
  attribute c_int_width of U0 : label is 64;
  attribute c_last_cfg_dw : string;
  attribute c_last_cfg_dw of U0 : label is "10C";
  attribute c_link_cap_aspm_optionality : string;
  attribute c_link_cap_aspm_optionality of U0 : label is "FALSE";
  attribute c_ll_ack_timeout : string;
  attribute c_ll_ack_timeout of U0 : label is "0000";
  attribute c_ll_ack_timeout_enable : string;
  attribute c_ll_ack_timeout_enable of U0 : label is "FALSE";
  attribute c_ll_ack_timeout_function : string;
  attribute c_ll_ack_timeout_function of U0 : label is "0";
  attribute c_ll_replay_timeout : string;
  attribute c_ll_replay_timeout of U0 : label is "0000";
  attribute c_ll_replay_timeout_enable : string;
  attribute c_ll_replay_timeout_enable of U0 : label is "FALSE";
  attribute c_ll_replay_timeout_func : string;
  attribute c_ll_replay_timeout_func of U0 : label is "1";
  attribute c_lnk_bndwdt_notif : string;
  attribute c_lnk_bndwdt_notif of U0 : label is "FALSE";
  attribute c_msi : string;
  attribute c_msi of U0 : label is "0";
  attribute c_msi_64b_addr : string;
  attribute c_msi_64b_addr of U0 : label is "TRUE";
  attribute c_msi_cap_on : string;
  attribute c_msi_cap_on of U0 : label is "TRUE";
  attribute c_msi_mult_msg_extn : string;
  attribute c_msi_mult_msg_extn of U0 : label is "0";
  attribute c_msi_per_vctr_mask_cap : string;
  attribute c_msi_per_vctr_mask_cap of U0 : label is "FALSE";
  attribute c_msix_cap_on : string;
  attribute c_msix_cap_on of U0 : label is "FALSE";
  attribute c_msix_next_ptr : string;
  attribute c_msix_next_ptr of U0 : label is "00";
  attribute c_msix_pba_bir : string;
  attribute c_msix_pba_bir of U0 : label is "0";
  attribute c_msix_pba_offset : string;
  attribute c_msix_pba_offset of U0 : label is "0";
  attribute c_msix_table_bir : string;
  attribute c_msix_table_bir of U0 : label is "0";
  attribute c_msix_table_offset : string;
  attribute c_msix_table_offset of U0 : label is "0";
  attribute c_msix_table_size : string;
  attribute c_msix_table_size of U0 : label is "000";
  attribute c_pci_cfg_space_addr : string;
  attribute c_pci_cfg_space_addr of U0 : label is "3F";
  attribute c_pcie_blk_locn : string;
  attribute c_pcie_blk_locn of U0 : label is "3";
  attribute c_pcie_cap_next_ptr : string;
  attribute c_pcie_cap_next_ptr of U0 : label is "00";
  attribute c_pcie_cap_slot_implemented : string;
  attribute c_pcie_cap_slot_implemented of U0 : label is "FALSE";
  attribute c_pcie_dbg_ports : string;
  attribute c_pcie_dbg_ports of U0 : label is "TRUE";
  attribute c_pcie_fast_config : integer;
  attribute c_pcie_fast_config of U0 : label is 0;
  attribute c_perf_level_high : string;
  attribute c_perf_level_high of U0 : label is "TRUE";
  attribute c_phantom_functions : string;
  attribute c_phantom_functions of U0 : label is "0";
  attribute c_pm_cap_next_ptr : string;
  attribute c_pm_cap_next_ptr of U0 : label is "48";
  attribute c_pme_support : string;
  attribute c_pme_support of U0 : label is "0F";
  attribute c_rbar_base_ptr : string;
  attribute c_rbar_base_ptr of U0 : label is "000";
  attribute c_rbar_cap_control_encodedbar0 : string;
  attribute c_rbar_cap_control_encodedbar0 of U0 : label is "00";
  attribute c_rbar_cap_control_encodedbar1 : string;
  attribute c_rbar_cap_control_encodedbar1 of U0 : label is "00";
  attribute c_rbar_cap_control_encodedbar2 : string;
  attribute c_rbar_cap_control_encodedbar2 of U0 : label is "00";
  attribute c_rbar_cap_control_encodedbar3 : string;
  attribute c_rbar_cap_control_encodedbar3 of U0 : label is "00";
  attribute c_rbar_cap_control_encodedbar4 : string;
  attribute c_rbar_cap_control_encodedbar4 of U0 : label is "00";
  attribute c_rbar_cap_control_encodedbar5 : string;
  attribute c_rbar_cap_control_encodedbar5 of U0 : label is "00";
  attribute c_rbar_cap_index0 : string;
  attribute c_rbar_cap_index0 of U0 : label is "0";
  attribute c_rbar_cap_index1 : string;
  attribute c_rbar_cap_index1 of U0 : label is "0";
  attribute c_rbar_cap_index2 : string;
  attribute c_rbar_cap_index2 of U0 : label is "0";
  attribute c_rbar_cap_index3 : string;
  attribute c_rbar_cap_index3 of U0 : label is "0";
  attribute c_rbar_cap_index4 : string;
  attribute c_rbar_cap_index4 of U0 : label is "0";
  attribute c_rbar_cap_index5 : string;
  attribute c_rbar_cap_index5 of U0 : label is "0";
  attribute c_rbar_cap_nextptr : string;
  attribute c_rbar_cap_nextptr of U0 : label is "000";
  attribute c_rbar_cap_on : string;
  attribute c_rbar_cap_on of U0 : label is "FALSE";
  attribute c_rbar_cap_sup0 : string;
  attribute c_rbar_cap_sup0 of U0 : label is "00001";
  attribute c_rbar_cap_sup1 : string;
  attribute c_rbar_cap_sup1 of U0 : label is "00001";
  attribute c_rbar_cap_sup2 : string;
  attribute c_rbar_cap_sup2 of U0 : label is "00001";
  attribute c_rbar_cap_sup3 : string;
  attribute c_rbar_cap_sup3 of U0 : label is "00001";
  attribute c_rbar_cap_sup4 : string;
  attribute c_rbar_cap_sup4 of U0 : label is "00001";
  attribute c_rbar_cap_sup5 : string;
  attribute c_rbar_cap_sup5 of U0 : label is "00001";
  attribute c_rbar_num : string;
  attribute c_rbar_num of U0 : label is "0";
  attribute c_rcb : string;
  attribute c_rcb of U0 : label is "0";
  attribute c_recrc_check : string;
  attribute c_recrc_check of U0 : label is "0";
  attribute c_recrc_check_trim : string;
  attribute c_recrc_check_trim of U0 : label is "FALSE";
  attribute c_rev_gt_order : string;
  attribute c_rev_gt_order of U0 : label is "FALSE";
  attribute c_root_cap_crs : string;
  attribute c_root_cap_crs of U0 : label is "FALSE";
  attribute c_rx_raddr_lat : string;
  attribute c_rx_raddr_lat of U0 : label is "0";
  attribute c_rx_ram_limit : string;
  attribute c_rx_ram_limit of U0 : label is "7FF";
  attribute c_rx_rdata_lat : string;
  attribute c_rx_rdata_lat of U0 : label is "2";
  attribute c_rx_write_lat : string;
  attribute c_rx_write_lat of U0 : label is "0";
  attribute c_silicon_rev : string;
  attribute c_silicon_rev of U0 : label is "2";
  attribute c_slot_cap_attn_butn : string;
  attribute c_slot_cap_attn_butn of U0 : label is "FALSE";
  attribute c_slot_cap_attn_ind : string;
  attribute c_slot_cap_attn_ind of U0 : label is "FALSE";
  attribute c_slot_cap_elec_interlock : string;
  attribute c_slot_cap_elec_interlock of U0 : label is "FALSE";
  attribute c_slot_cap_hotplug_cap : string;
  attribute c_slot_cap_hotplug_cap of U0 : label is "FALSE";
  attribute c_slot_cap_hotplug_surprise : string;
  attribute c_slot_cap_hotplug_surprise of U0 : label is "FALSE";
  attribute c_slot_cap_mrl : string;
  attribute c_slot_cap_mrl of U0 : label is "FALSE";
  attribute c_slot_cap_no_cmd_comp_sup : string;
  attribute c_slot_cap_no_cmd_comp_sup of U0 : label is "FALSE";
  attribute c_slot_cap_physical_slot_num : string;
  attribute c_slot_cap_physical_slot_num of U0 : label is "0";
  attribute c_slot_cap_pwr_ctrl : string;
  attribute c_slot_cap_pwr_ctrl of U0 : label is "FALSE";
  attribute c_slot_cap_pwr_ind : string;
  attribute c_slot_cap_pwr_ind of U0 : label is "FALSE";
  attribute c_slot_cap_pwr_limit_scale : string;
  attribute c_slot_cap_pwr_limit_scale of U0 : label is "0";
  attribute c_slot_cap_pwr_limit_value : string;
  attribute c_slot_cap_pwr_limit_value of U0 : label is "0";
  attribute c_surprise_dn_err_cap : string;
  attribute c_surprise_dn_err_cap of U0 : label is "FALSE";
  attribute c_trgt_lnk_spd : string;
  attribute c_trgt_lnk_spd of U0 : label is "0";
  attribute c_trn_np_fc : string;
  attribute c_trn_np_fc of U0 : label is "TRUE";
  attribute c_tx_last_tlp : string;
  attribute c_tx_last_tlp of U0 : label is "29";
  attribute c_tx_raddr_lat : string;
  attribute c_tx_raddr_lat of U0 : label is "0";
  attribute c_tx_rdata_lat : string;
  attribute c_tx_rdata_lat of U0 : label is "2";
  attribute c_tx_write_lat : string;
  attribute c_tx_write_lat of U0 : label is "0";
  attribute c_upconfig_capable : string;
  attribute c_upconfig_capable of U0 : label is "TRUE";
  attribute c_upstream_facing : string;
  attribute c_upstream_facing of U0 : label is "TRUE";
  attribute c_ur_atomic : string;
  attribute c_ur_atomic of U0 : label is "FALSE";
  attribute c_ur_inv_req : string;
  attribute c_ur_inv_req of U0 : label is "TRUE";
  attribute c_ur_prs_response : string;
  attribute c_ur_prs_response of U0 : label is "TRUE";
  attribute c_vc_base_ptr : string;
  attribute c_vc_base_ptr of U0 : label is "000";
  attribute c_vc_cap_enabled : string;
  attribute c_vc_cap_enabled of U0 : label is "FALSE";
  attribute c_vc_cap_reject_snoop : string;
  attribute c_vc_cap_reject_snoop of U0 : label is "FALSE";
  attribute c_vc_next_ptr : string;
  attribute c_vc_next_ptr of U0 : label is "000";
  attribute c_vsec_base_ptr : string;
  attribute c_vsec_base_ptr of U0 : label is "000";
  attribute c_vsec_cap_enabled : string;
  attribute c_vsec_cap_enabled of U0 : label is "FALSE";
  attribute c_vsec_next_ptr : string;
  attribute c_vsec_next_ptr of U0 : label is "000";
  attribute c_xlnx_ref_board : string;
  attribute c_xlnx_ref_board of U0 : label is "VC707";
  attribute cap_ver : string;
  attribute cap_ver of U0 : label is "2";
  attribute cardbus_cis_ptr : string;
  attribute cardbus_cis_ptr of U0 : label is "00000000";
  attribute cmps : string;
  attribute cmps of U0 : label is "2";
  attribute con_scl_fctr_d0_state : string;
  attribute con_scl_fctr_d0_state of U0 : label is "0";
  attribute con_scl_fctr_d1_state : string;
  attribute con_scl_fctr_d1_state of U0 : label is "0";
  attribute con_scl_fctr_d2_state : string;
  attribute con_scl_fctr_d2_state of U0 : label is "0";
  attribute con_scl_fctr_d3_state : string;
  attribute con_scl_fctr_d3_state of U0 : label is "0";
  attribute cost_table : integer;
  attribute cost_table of U0 : label is 1;
  attribute d1_sup : string;
  attribute d1_sup of U0 : label is "0";
  attribute d2_sup : string;
  attribute d2_sup of U0 : label is "0";
  attribute dev_id : string;
  attribute dev_id of U0 : label is "7018";
  attribute dev_port_type : string;
  attribute dev_port_type of U0 : label is "0000";
  attribute dis_scl_fctr_d0_state : string;
  attribute dis_scl_fctr_d0_state of U0 : label is "0";
  attribute dis_scl_fctr_d1_state : string;
  attribute dis_scl_fctr_d1_state of U0 : label is "0";
  attribute dis_scl_fctr_d2_state : string;
  attribute dis_scl_fctr_d2_state of U0 : label is "0";
  attribute dis_scl_fctr_d3_state : string;
  attribute dis_scl_fctr_d3_state of U0 : label is "0";
  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
  attribute dsi : string;
  attribute dsi of U0 : label is "0";
  attribute ep_l0s_accpt_lat : string;
  attribute ep_l0s_accpt_lat of U0 : label is "000";
  attribute ep_l1_accpt_lat : string;
  attribute ep_l1_accpt_lat of U0 : label is "111";
  attribute ext_tag_fld_sup : string;
  attribute ext_tag_fld_sup of U0 : label is "TRUE";
  attribute int_pin : string;
  attribute int_pin of U0 : label is "0";
  attribute intx : string;
  attribute intx of U0 : label is "FALSE";
  attribute max_lnk_spd : string;
  attribute max_lnk_spd of U0 : label is "1";
  attribute max_lnk_wdt : string;
  attribute max_lnk_wdt of U0 : label is "001000";
  attribute mps : string;
  attribute mps of U0 : label is "010";
  attribute no_soft_rst : string;
  attribute no_soft_rst of U0 : label is "TRUE";
  attribute pci_exp_int_freq : integer;
  attribute pci_exp_int_freq of U0 : label is 3;
  attribute pci_exp_ref_freq : string;
  attribute pci_exp_ref_freq of U0 : label is "0";
  attribute phantm_func_sup : string;
  attribute phantm_func_sup of U0 : label is "00";
  attribute pme_sup : string;
  attribute pme_sup of U0 : label is "0F";
  attribute pwr_con_d0_state : string;
  attribute pwr_con_d0_state of U0 : label is "00";
  attribute pwr_con_d1_state : string;
  attribute pwr_con_d1_state of U0 : label is "00";
  attribute pwr_con_d2_state : string;
  attribute pwr_con_d2_state of U0 : label is "00";
  attribute pwr_con_d3_state : string;
  attribute pwr_con_d3_state of U0 : label is "00";
  attribute pwr_dis_d0_state : string;
  attribute pwr_dis_d0_state of U0 : label is "00";
  attribute pwr_dis_d1_state : string;
  attribute pwr_dis_d1_state of U0 : label is "00";
  attribute pwr_dis_d2_state : string;
  attribute pwr_dis_d2_state of U0 : label is "00";
  attribute pwr_dis_d3_state : string;
  attribute pwr_dis_d3_state of U0 : label is "00";
  attribute rev_id : string;
  attribute rev_id of U0 : label is "00";
  attribute slot_clk : string;
  attribute slot_clk of U0 : label is "TRUE";
  attribute subsys_id : string;
  attribute subsys_id of U0 : label is "0007";
  attribute subsys_ven_id : string;
  attribute subsys_ven_id of U0 : label is "10EE";
  attribute ven_id : string;
  attribute ven_id of U0 : label is "10EE";
  attribute xrom_bar : string;
  attribute xrom_bar of U0 : label is "00000000";
begin
U0: entity work.PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top
     port map (
      cfg_aer_ecrc_check_en => NLW_U0_cfg_aer_ecrc_check_en_UNCONNECTED,
      cfg_aer_ecrc_gen_en => NLW_U0_cfg_aer_ecrc_gen_en_UNCONNECTED,
      cfg_aer_interrupt_msgnum(4) => '0',
      cfg_aer_interrupt_msgnum(3) => '0',
      cfg_aer_interrupt_msgnum(2) => '0',
      cfg_aer_interrupt_msgnum(1) => '0',
      cfg_aer_interrupt_msgnum(0) => '0',
      cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received,
      cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en,
      cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received,
      cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en,
      cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received,
      cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en,
      cfg_bridge_serr_en => cfg_bridge_serr_en,
      cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0),
      cfg_command(15 downto 0) => cfg_command(15 downto 0),
      cfg_dcommand(15 downto 0) => cfg_dcommand(15 downto 0),
      cfg_dcommand2(15 downto 0) => cfg_dcommand2(15 downto 0),
      cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0),
      cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0),
      cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0),
      cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0),
      cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0),
      cfg_dstatus(15 downto 0) => cfg_dstatus(15 downto 0),
      cfg_err_acs => '0',
      cfg_err_aer_headerlog(127) => '0',
      cfg_err_aer_headerlog(126) => '0',
      cfg_err_aer_headerlog(125) => '0',
      cfg_err_aer_headerlog(124) => '0',
      cfg_err_aer_headerlog(123) => '0',
      cfg_err_aer_headerlog(122) => '0',
      cfg_err_aer_headerlog(121) => '0',
      cfg_err_aer_headerlog(120) => '0',
      cfg_err_aer_headerlog(119) => '0',
      cfg_err_aer_headerlog(118) => '0',
      cfg_err_aer_headerlog(117) => '0',
      cfg_err_aer_headerlog(116) => '0',
      cfg_err_aer_headerlog(115) => '0',
      cfg_err_aer_headerlog(114) => '0',
      cfg_err_aer_headerlog(113) => '0',
      cfg_err_aer_headerlog(112) => '0',
      cfg_err_aer_headerlog(111) => '0',
      cfg_err_aer_headerlog(110) => '0',
      cfg_err_aer_headerlog(109) => '0',
      cfg_err_aer_headerlog(108) => '0',
      cfg_err_aer_headerlog(107) => '0',
      cfg_err_aer_headerlog(106) => '0',
      cfg_err_aer_headerlog(105) => '0',
      cfg_err_aer_headerlog(104) => '0',
      cfg_err_aer_headerlog(103) => '0',
      cfg_err_aer_headerlog(102) => '0',
      cfg_err_aer_headerlog(101) => '0',
      cfg_err_aer_headerlog(100) => '0',
      cfg_err_aer_headerlog(99) => '0',
      cfg_err_aer_headerlog(98) => '0',
      cfg_err_aer_headerlog(97) => '0',
      cfg_err_aer_headerlog(96) => '0',
      cfg_err_aer_headerlog(95) => '0',
      cfg_err_aer_headerlog(94) => '0',
      cfg_err_aer_headerlog(93) => '0',
      cfg_err_aer_headerlog(92) => '0',
      cfg_err_aer_headerlog(91) => '0',
      cfg_err_aer_headerlog(90) => '0',
      cfg_err_aer_headerlog(89) => '0',
      cfg_err_aer_headerlog(88) => '0',
      cfg_err_aer_headerlog(87) => '0',
      cfg_err_aer_headerlog(86) => '0',
      cfg_err_aer_headerlog(85) => '0',
      cfg_err_aer_headerlog(84) => '0',
      cfg_err_aer_headerlog(83) => '0',
      cfg_err_aer_headerlog(82) => '0',
      cfg_err_aer_headerlog(81) => '0',
      cfg_err_aer_headerlog(80) => '0',
      cfg_err_aer_headerlog(79) => '0',
      cfg_err_aer_headerlog(78) => '0',
      cfg_err_aer_headerlog(77) => '0',
      cfg_err_aer_headerlog(76) => '0',
      cfg_err_aer_headerlog(75) => '0',
      cfg_err_aer_headerlog(74) => '0',
      cfg_err_aer_headerlog(73) => '0',
      cfg_err_aer_headerlog(72) => '0',
      cfg_err_aer_headerlog(71) => '0',
      cfg_err_aer_headerlog(70) => '0',
      cfg_err_aer_headerlog(69) => '0',
      cfg_err_aer_headerlog(68) => '0',
      cfg_err_aer_headerlog(67) => '0',
      cfg_err_aer_headerlog(66) => '0',
      cfg_err_aer_headerlog(65) => '0',
      cfg_err_aer_headerlog(64) => '0',
      cfg_err_aer_headerlog(63) => '0',
      cfg_err_aer_headerlog(62) => '0',
      cfg_err_aer_headerlog(61) => '0',
      cfg_err_aer_headerlog(60) => '0',
      cfg_err_aer_headerlog(59) => '0',
      cfg_err_aer_headerlog(58) => '0',
      cfg_err_aer_headerlog(57) => '0',
      cfg_err_aer_headerlog(56) => '0',
      cfg_err_aer_headerlog(55) => '0',
      cfg_err_aer_headerlog(54) => '0',
      cfg_err_aer_headerlog(53) => '0',
      cfg_err_aer_headerlog(52) => '0',
      cfg_err_aer_headerlog(51) => '0',
      cfg_err_aer_headerlog(50) => '0',
      cfg_err_aer_headerlog(49) => '0',
      cfg_err_aer_headerlog(48) => '0',
      cfg_err_aer_headerlog(47) => '0',
      cfg_err_aer_headerlog(46) => '0',
      cfg_err_aer_headerlog(45) => '0',
      cfg_err_aer_headerlog(44) => '0',
      cfg_err_aer_headerlog(43) => '0',
      cfg_err_aer_headerlog(42) => '0',
      cfg_err_aer_headerlog(41) => '0',
      cfg_err_aer_headerlog(40) => '0',
      cfg_err_aer_headerlog(39) => '0',
      cfg_err_aer_headerlog(38) => '0',
      cfg_err_aer_headerlog(37) => '0',
      cfg_err_aer_headerlog(36) => '0',
      cfg_err_aer_headerlog(35) => '0',
      cfg_err_aer_headerlog(34) => '0',
      cfg_err_aer_headerlog(33) => '0',
      cfg_err_aer_headerlog(32) => '0',
      cfg_err_aer_headerlog(31) => '0',
      cfg_err_aer_headerlog(30) => '0',
      cfg_err_aer_headerlog(29) => '0',
      cfg_err_aer_headerlog(28) => '0',
      cfg_err_aer_headerlog(27) => '0',
      cfg_err_aer_headerlog(26) => '0',
      cfg_err_aer_headerlog(25) => '0',
      cfg_err_aer_headerlog(24) => '0',
      cfg_err_aer_headerlog(23) => '0',
      cfg_err_aer_headerlog(22) => '0',
      cfg_err_aer_headerlog(21) => '0',
      cfg_err_aer_headerlog(20) => '0',
      cfg_err_aer_headerlog(19) => '0',
      cfg_err_aer_headerlog(18) => '0',
      cfg_err_aer_headerlog(17) => '0',
      cfg_err_aer_headerlog(16) => '0',
      cfg_err_aer_headerlog(15) => '0',
      cfg_err_aer_headerlog(14) => '0',
      cfg_err_aer_headerlog(13) => '0',
      cfg_err_aer_headerlog(12) => '0',
      cfg_err_aer_headerlog(11) => '0',
      cfg_err_aer_headerlog(10) => '0',
      cfg_err_aer_headerlog(9) => '0',
      cfg_err_aer_headerlog(8) => '0',
      cfg_err_aer_headerlog(7) => '0',
      cfg_err_aer_headerlog(6) => '0',
      cfg_err_aer_headerlog(5) => '0',
      cfg_err_aer_headerlog(4) => '0',
      cfg_err_aer_headerlog(3) => '0',
      cfg_err_aer_headerlog(2) => '0',
      cfg_err_aer_headerlog(1) => '0',
      cfg_err_aer_headerlog(0) => '0',
      cfg_err_aer_headerlog_set => NLW_U0_cfg_err_aer_headerlog_set_UNCONNECTED,
      cfg_err_atomic_egress_blocked => '0',
      cfg_err_cor => '0',
      cfg_err_cpl_abort => '0',
      cfg_err_cpl_rdy => NLW_U0_cfg_err_cpl_rdy_UNCONNECTED,
      cfg_err_cpl_timeout => '0',
      cfg_err_cpl_unexpect => '0',
      cfg_err_ecrc => '0',
      cfg_err_internal_cor => '0',
      cfg_err_internal_uncor => '0',
      cfg_err_locked => '0',
      cfg_err_malformed => '0',
      cfg_err_mc_blocked => '0',
      cfg_err_norecovery => '0',
      cfg_err_poisoned => '0',
      cfg_err_posted => '0',
      cfg_err_tlp_cpl_header(47) => '0',
      cfg_err_tlp_cpl_header(46) => '0',
      cfg_err_tlp_cpl_header(45) => '0',
      cfg_err_tlp_cpl_header(44) => '0',
      cfg_err_tlp_cpl_header(43) => '0',
      cfg_err_tlp_cpl_header(42) => '0',
      cfg_err_tlp_cpl_header(41) => '0',
      cfg_err_tlp_cpl_header(40) => '0',
      cfg_err_tlp_cpl_header(39) => '0',
      cfg_err_tlp_cpl_header(38) => '0',
      cfg_err_tlp_cpl_header(37) => '0',
      cfg_err_tlp_cpl_header(36) => '0',
      cfg_err_tlp_cpl_header(35) => '0',
      cfg_err_tlp_cpl_header(34) => '0',
      cfg_err_tlp_cpl_header(33) => '0',
      cfg_err_tlp_cpl_header(32) => '0',
      cfg_err_tlp_cpl_header(31) => '0',
      cfg_err_tlp_cpl_header(30) => '0',
      cfg_err_tlp_cpl_header(29) => '0',
      cfg_err_tlp_cpl_header(28) => '0',
      cfg_err_tlp_cpl_header(27) => '0',
      cfg_err_tlp_cpl_header(26) => '0',
      cfg_err_tlp_cpl_header(25) => '0',
      cfg_err_tlp_cpl_header(24) => '0',
      cfg_err_tlp_cpl_header(23) => '0',
      cfg_err_tlp_cpl_header(22) => '0',
      cfg_err_tlp_cpl_header(21) => '0',
      cfg_err_tlp_cpl_header(20) => '0',
      cfg_err_tlp_cpl_header(19) => '0',
      cfg_err_tlp_cpl_header(18) => '0',
      cfg_err_tlp_cpl_header(17) => '0',
      cfg_err_tlp_cpl_header(16) => '0',
      cfg_err_tlp_cpl_header(15) => '0',
      cfg_err_tlp_cpl_header(14) => '0',
      cfg_err_tlp_cpl_header(13) => '0',
      cfg_err_tlp_cpl_header(12) => '0',
      cfg_err_tlp_cpl_header(11) => '0',
      cfg_err_tlp_cpl_header(10) => '0',
      cfg_err_tlp_cpl_header(9) => '0',
      cfg_err_tlp_cpl_header(8) => '0',
      cfg_err_tlp_cpl_header(7) => '0',
      cfg_err_tlp_cpl_header(6) => '0',
      cfg_err_tlp_cpl_header(5) => '0',
      cfg_err_tlp_cpl_header(4) => '0',
      cfg_err_tlp_cpl_header(3) => '0',
      cfg_err_tlp_cpl_header(2) => '0',
      cfg_err_tlp_cpl_header(1) => '0',
      cfg_err_tlp_cpl_header(0) => '0',
      cfg_err_ur => '0',
      cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0),
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0),
      cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_msixenable => cfg_interrupt_msixenable,
      cfg_interrupt_msixfm => cfg_interrupt_msixfm,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_interrupt_stat => cfg_interrupt_stat,
      cfg_lcommand(15 downto 0) => cfg_lcommand(15 downto 0),
      cfg_lstatus(15 downto 0) => cfg_lstatus(15 downto 0),
      cfg_mgmt_byte_en(3) => '0',
      cfg_mgmt_byte_en(2) => '0',
      cfg_mgmt_byte_en(1) => '0',
      cfg_mgmt_byte_en(0) => '0',
      cfg_mgmt_di(31) => '0',
      cfg_mgmt_di(30) => '0',
      cfg_mgmt_di(29) => '0',
      cfg_mgmt_di(28) => '0',
      cfg_mgmt_di(27) => '0',
      cfg_mgmt_di(26) => '0',
      cfg_mgmt_di(25) => '0',
      cfg_mgmt_di(24) => '0',
      cfg_mgmt_di(23) => '0',
      cfg_mgmt_di(22) => '0',
      cfg_mgmt_di(21) => '0',
      cfg_mgmt_di(20) => '0',
      cfg_mgmt_di(19) => '0',
      cfg_mgmt_di(18) => '0',
      cfg_mgmt_di(17) => '0',
      cfg_mgmt_di(16) => '0',
      cfg_mgmt_di(15) => '0',
      cfg_mgmt_di(14) => '0',
      cfg_mgmt_di(13) => '0',
      cfg_mgmt_di(12) => '0',
      cfg_mgmt_di(11) => '0',
      cfg_mgmt_di(10) => '0',
      cfg_mgmt_di(9) => '0',
      cfg_mgmt_di(8) => '0',
      cfg_mgmt_di(7) => '0',
      cfg_mgmt_di(6) => '0',
      cfg_mgmt_di(5) => '0',
      cfg_mgmt_di(4) => '0',
      cfg_mgmt_di(3) => '0',
      cfg_mgmt_di(2) => '0',
      cfg_mgmt_di(1) => '0',
      cfg_mgmt_di(0) => '0',
      cfg_mgmt_do(31 downto 0) => NLW_U0_cfg_mgmt_do_UNCONNECTED(31 downto 0),
      cfg_mgmt_dwaddr(9) => '0',
      cfg_mgmt_dwaddr(8) => '0',
      cfg_mgmt_dwaddr(7) => '0',
      cfg_mgmt_dwaddr(6) => '0',
      cfg_mgmt_dwaddr(5) => '0',
      cfg_mgmt_dwaddr(4) => '0',
      cfg_mgmt_dwaddr(3) => '0',
      cfg_mgmt_dwaddr(2) => '0',
      cfg_mgmt_dwaddr(1) => '0',
      cfg_mgmt_dwaddr(0) => '0',
      cfg_mgmt_rd_en => '0',
      cfg_mgmt_rd_wr_done => NLW_U0_cfg_mgmt_rd_wr_done_UNCONNECTED,
      cfg_mgmt_wr_en => '0',
      cfg_mgmt_wr_readonly => '0',
      cfg_mgmt_wr_rw1c_as_rw => '0',
      cfg_msg_data(15 downto 0) => NLW_U0_cfg_msg_data_UNCONNECTED(15 downto 0),
      cfg_msg_received => NLW_U0_cfg_msg_received_UNCONNECTED,
      cfg_msg_received_assert_int_a => NLW_U0_cfg_msg_received_assert_int_a_UNCONNECTED,
      cfg_msg_received_assert_int_b => NLW_U0_cfg_msg_received_assert_int_b_UNCONNECTED,
      cfg_msg_received_assert_int_c => NLW_U0_cfg_msg_received_assert_int_c_UNCONNECTED,
      cfg_msg_received_assert_int_d => NLW_U0_cfg_msg_received_assert_int_d_UNCONNECTED,
      cfg_msg_received_deassert_int_a => NLW_U0_cfg_msg_received_deassert_int_a_UNCONNECTED,
      cfg_msg_received_deassert_int_b => NLW_U0_cfg_msg_received_deassert_int_b_UNCONNECTED,
      cfg_msg_received_deassert_int_c => NLW_U0_cfg_msg_received_deassert_int_c_UNCONNECTED,
      cfg_msg_received_deassert_int_d => NLW_U0_cfg_msg_received_deassert_int_d_UNCONNECTED,
      cfg_msg_received_err_cor => NLW_U0_cfg_msg_received_err_cor_UNCONNECTED,
      cfg_msg_received_err_fatal => NLW_U0_cfg_msg_received_err_fatal_UNCONNECTED,
      cfg_msg_received_err_non_fatal => NLW_U0_cfg_msg_received_err_non_fatal_UNCONNECTED,
      cfg_msg_received_pm_as_nak => NLW_U0_cfg_msg_received_pm_as_nak_UNCONNECTED,
      cfg_msg_received_pm_pme => NLW_U0_cfg_msg_received_pm_pme_UNCONNECTED,
      cfg_msg_received_pme_to_ack => NLW_U0_cfg_msg_received_pme_to_ack_UNCONNECTED,
      cfg_msg_received_setslotpowerlimit => NLW_U0_cfg_msg_received_setslotpowerlimit_UNCONNECTED,
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0),
      cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0),
      cfg_pm_force_state_en => cfg_pm_force_state_en,
      cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s,
      cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1,
      cfg_pm_send_pme_to => cfg_pm_send_pme_to,
      cfg_pm_wake => cfg_pm_wake,
      cfg_pmcsr_pme_en => cfg_pmcsr_pme_en,
      cfg_pmcsr_pme_status => cfg_pmcsr_pme_status,
      cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0),
      cfg_received_func_lvl_rst => cfg_received_func_lvl_rst,
      cfg_root_control_pme_int_en => cfg_root_control_pme_int_en,
      cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en,
      cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en,
      cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en,
      cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse,
      cfg_status(15 downto 0) => cfg_status(15 downto 0),
      cfg_to_turnoff => cfg_to_turnoff,
      cfg_trn_pending => cfg_trn_pending,
      cfg_turnoff_ok => cfg_turnoff_ok,
      cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0),
      common_commands_in(3) => '0',
      common_commands_in(2) => '0',
      common_commands_in(1) => '0',
      common_commands_in(0) => '0',
      common_commands_out(11 downto 0) => NLW_U0_common_commands_out_UNCONNECTED(11 downto 0),
      ext_ch_gt_drpaddr(71) => '0',
      ext_ch_gt_drpaddr(70) => '0',
      ext_ch_gt_drpaddr(69) => '0',
      ext_ch_gt_drpaddr(68) => '0',
      ext_ch_gt_drpaddr(67) => '0',
      ext_ch_gt_drpaddr(66) => '0',
      ext_ch_gt_drpaddr(65) => '0',
      ext_ch_gt_drpaddr(64) => '0',
      ext_ch_gt_drpaddr(63) => '0',
      ext_ch_gt_drpaddr(62) => '0',
      ext_ch_gt_drpaddr(61) => '0',
      ext_ch_gt_drpaddr(60) => '0',
      ext_ch_gt_drpaddr(59) => '0',
      ext_ch_gt_drpaddr(58) => '0',
      ext_ch_gt_drpaddr(57) => '0',
      ext_ch_gt_drpaddr(56) => '0',
      ext_ch_gt_drpaddr(55) => '0',
      ext_ch_gt_drpaddr(54) => '0',
      ext_ch_gt_drpaddr(53) => '0',
      ext_ch_gt_drpaddr(52) => '0',
      ext_ch_gt_drpaddr(51) => '0',
      ext_ch_gt_drpaddr(50) => '0',
      ext_ch_gt_drpaddr(49) => '0',
      ext_ch_gt_drpaddr(48) => '0',
      ext_ch_gt_drpaddr(47) => '0',
      ext_ch_gt_drpaddr(46) => '0',
      ext_ch_gt_drpaddr(45) => '0',
      ext_ch_gt_drpaddr(44) => '0',
      ext_ch_gt_drpaddr(43) => '0',
      ext_ch_gt_drpaddr(42) => '0',
      ext_ch_gt_drpaddr(41) => '0',
      ext_ch_gt_drpaddr(40) => '0',
      ext_ch_gt_drpaddr(39) => '0',
      ext_ch_gt_drpaddr(38) => '0',
      ext_ch_gt_drpaddr(37) => '0',
      ext_ch_gt_drpaddr(36) => '0',
      ext_ch_gt_drpaddr(35) => '0',
      ext_ch_gt_drpaddr(34) => '0',
      ext_ch_gt_drpaddr(33) => '0',
      ext_ch_gt_drpaddr(32) => '0',
      ext_ch_gt_drpaddr(31) => '0',
      ext_ch_gt_drpaddr(30) => '0',
      ext_ch_gt_drpaddr(29) => '0',
      ext_ch_gt_drpaddr(28) => '0',
      ext_ch_gt_drpaddr(27) => '0',
      ext_ch_gt_drpaddr(26) => '0',
      ext_ch_gt_drpaddr(25) => '0',
      ext_ch_gt_drpaddr(24) => '0',
      ext_ch_gt_drpaddr(23) => '0',
      ext_ch_gt_drpaddr(22) => '0',
      ext_ch_gt_drpaddr(21) => '0',
      ext_ch_gt_drpaddr(20) => '0',
      ext_ch_gt_drpaddr(19) => '0',
      ext_ch_gt_drpaddr(18) => '0',
      ext_ch_gt_drpaddr(17) => '0',
      ext_ch_gt_drpaddr(16) => '0',
      ext_ch_gt_drpaddr(15) => '0',
      ext_ch_gt_drpaddr(14) => '0',
      ext_ch_gt_drpaddr(13) => '0',
      ext_ch_gt_drpaddr(12) => '0',
      ext_ch_gt_drpaddr(11) => '0',
      ext_ch_gt_drpaddr(10) => '0',
      ext_ch_gt_drpaddr(9) => '0',
      ext_ch_gt_drpaddr(8) => '0',
      ext_ch_gt_drpaddr(7) => '0',
      ext_ch_gt_drpaddr(6) => '0',
      ext_ch_gt_drpaddr(5) => '0',
      ext_ch_gt_drpaddr(4) => '0',
      ext_ch_gt_drpaddr(3) => '0',
      ext_ch_gt_drpaddr(2) => '0',
      ext_ch_gt_drpaddr(1) => '0',
      ext_ch_gt_drpaddr(0) => '0',
      ext_ch_gt_drpclk => NLW_U0_ext_ch_gt_drpclk_UNCONNECTED,
      ext_ch_gt_drpdi(127) => '0',
      ext_ch_gt_drpdi(126) => '0',
      ext_ch_gt_drpdi(125) => '0',
      ext_ch_gt_drpdi(124) => '0',
      ext_ch_gt_drpdi(123) => '0',
      ext_ch_gt_drpdi(122) => '0',
      ext_ch_gt_drpdi(121) => '0',
      ext_ch_gt_drpdi(120) => '0',
      ext_ch_gt_drpdi(119) => '0',
      ext_ch_gt_drpdi(118) => '0',
      ext_ch_gt_drpdi(117) => '0',
      ext_ch_gt_drpdi(116) => '0',
      ext_ch_gt_drpdi(115) => '0',
      ext_ch_gt_drpdi(114) => '0',
      ext_ch_gt_drpdi(113) => '0',
      ext_ch_gt_drpdi(112) => '0',
      ext_ch_gt_drpdi(111) => '0',
      ext_ch_gt_drpdi(110) => '0',
      ext_ch_gt_drpdi(109) => '0',
      ext_ch_gt_drpdi(108) => '0',
      ext_ch_gt_drpdi(107) => '0',
      ext_ch_gt_drpdi(106) => '0',
      ext_ch_gt_drpdi(105) => '0',
      ext_ch_gt_drpdi(104) => '0',
      ext_ch_gt_drpdi(103) => '0',
      ext_ch_gt_drpdi(102) => '0',
      ext_ch_gt_drpdi(101) => '0',
      ext_ch_gt_drpdi(100) => '0',
      ext_ch_gt_drpdi(99) => '0',
      ext_ch_gt_drpdi(98) => '0',
      ext_ch_gt_drpdi(97) => '0',
      ext_ch_gt_drpdi(96) => '0',
      ext_ch_gt_drpdi(95) => '0',
      ext_ch_gt_drpdi(94) => '0',
      ext_ch_gt_drpdi(93) => '0',
      ext_ch_gt_drpdi(92) => '0',
      ext_ch_gt_drpdi(91) => '0',
      ext_ch_gt_drpdi(90) => '0',
      ext_ch_gt_drpdi(89) => '0',
      ext_ch_gt_drpdi(88) => '0',
      ext_ch_gt_drpdi(87) => '0',
      ext_ch_gt_drpdi(86) => '0',
      ext_ch_gt_drpdi(85) => '0',
      ext_ch_gt_drpdi(84) => '0',
      ext_ch_gt_drpdi(83) => '0',
      ext_ch_gt_drpdi(82) => '0',
      ext_ch_gt_drpdi(81) => '0',
      ext_ch_gt_drpdi(80) => '0',
      ext_ch_gt_drpdi(79) => '0',
      ext_ch_gt_drpdi(78) => '0',
      ext_ch_gt_drpdi(77) => '0',
      ext_ch_gt_drpdi(76) => '0',
      ext_ch_gt_drpdi(75) => '0',
      ext_ch_gt_drpdi(74) => '0',
      ext_ch_gt_drpdi(73) => '0',
      ext_ch_gt_drpdi(72) => '0',
      ext_ch_gt_drpdi(71) => '0',
      ext_ch_gt_drpdi(70) => '0',
      ext_ch_gt_drpdi(69) => '0',
      ext_ch_gt_drpdi(68) => '0',
      ext_ch_gt_drpdi(67) => '0',
      ext_ch_gt_drpdi(66) => '0',
      ext_ch_gt_drpdi(65) => '0',
      ext_ch_gt_drpdi(64) => '0',
      ext_ch_gt_drpdi(63) => '0',
      ext_ch_gt_drpdi(62) => '0',
      ext_ch_gt_drpdi(61) => '0',
      ext_ch_gt_drpdi(60) => '0',
      ext_ch_gt_drpdi(59) => '0',
      ext_ch_gt_drpdi(58) => '0',
      ext_ch_gt_drpdi(57) => '0',
      ext_ch_gt_drpdi(56) => '0',
      ext_ch_gt_drpdi(55) => '0',
      ext_ch_gt_drpdi(54) => '0',
      ext_ch_gt_drpdi(53) => '0',
      ext_ch_gt_drpdi(52) => '0',
      ext_ch_gt_drpdi(51) => '0',
      ext_ch_gt_drpdi(50) => '0',
      ext_ch_gt_drpdi(49) => '0',
      ext_ch_gt_drpdi(48) => '0',
      ext_ch_gt_drpdi(47) => '0',
      ext_ch_gt_drpdi(46) => '0',
      ext_ch_gt_drpdi(45) => '0',
      ext_ch_gt_drpdi(44) => '0',
      ext_ch_gt_drpdi(43) => '0',
      ext_ch_gt_drpdi(42) => '0',
      ext_ch_gt_drpdi(41) => '0',
      ext_ch_gt_drpdi(40) => '0',
      ext_ch_gt_drpdi(39) => '0',
      ext_ch_gt_drpdi(38) => '0',
      ext_ch_gt_drpdi(37) => '0',
      ext_ch_gt_drpdi(36) => '0',
      ext_ch_gt_drpdi(35) => '0',
      ext_ch_gt_drpdi(34) => '0',
      ext_ch_gt_drpdi(33) => '0',
      ext_ch_gt_drpdi(32) => '0',
      ext_ch_gt_drpdi(31) => '0',
      ext_ch_gt_drpdi(30) => '0',
      ext_ch_gt_drpdi(29) => '0',
      ext_ch_gt_drpdi(28) => '0',
      ext_ch_gt_drpdi(27) => '0',
      ext_ch_gt_drpdi(26) => '0',
      ext_ch_gt_drpdi(25) => '0',
      ext_ch_gt_drpdi(24) => '0',
      ext_ch_gt_drpdi(23) => '0',
      ext_ch_gt_drpdi(22) => '0',
      ext_ch_gt_drpdi(21) => '0',
      ext_ch_gt_drpdi(20) => '0',
      ext_ch_gt_drpdi(19) => '0',
      ext_ch_gt_drpdi(18) => '0',
      ext_ch_gt_drpdi(17) => '0',
      ext_ch_gt_drpdi(16) => '0',
      ext_ch_gt_drpdi(15) => '0',
      ext_ch_gt_drpdi(14) => '0',
      ext_ch_gt_drpdi(13) => '0',
      ext_ch_gt_drpdi(12) => '0',
      ext_ch_gt_drpdi(11) => '0',
      ext_ch_gt_drpdi(10) => '0',
      ext_ch_gt_drpdi(9) => '0',
      ext_ch_gt_drpdi(8) => '0',
      ext_ch_gt_drpdi(7) => '0',
      ext_ch_gt_drpdi(6) => '0',
      ext_ch_gt_drpdi(5) => '0',
      ext_ch_gt_drpdi(4) => '0',
      ext_ch_gt_drpdi(3) => '0',
      ext_ch_gt_drpdi(2) => '0',
      ext_ch_gt_drpdi(1) => '0',
      ext_ch_gt_drpdi(0) => '0',
      ext_ch_gt_drpdo(127 downto 0) => NLW_U0_ext_ch_gt_drpdo_UNCONNECTED(127 downto 0),
      ext_ch_gt_drpen(7) => '0',
      ext_ch_gt_drpen(6) => '0',
      ext_ch_gt_drpen(5) => '0',
      ext_ch_gt_drpen(4) => '0',
      ext_ch_gt_drpen(3) => '0',
      ext_ch_gt_drpen(2) => '0',
      ext_ch_gt_drpen(1) => '0',
      ext_ch_gt_drpen(0) => '0',
      ext_ch_gt_drprdy(7 downto 0) => NLW_U0_ext_ch_gt_drprdy_UNCONNECTED(7 downto 0),
      ext_ch_gt_drpwe(7) => '0',
      ext_ch_gt_drpwe(6) => '0',
      ext_ch_gt_drpwe(5) => '0',
      ext_ch_gt_drpwe(4) => '0',
      ext_ch_gt_drpwe(3) => '0',
      ext_ch_gt_drpwe(2) => '0',
      ext_ch_gt_drpwe(1) => '0',
      ext_ch_gt_drpwe(0) => '0',
      fc_cpld(11 downto 0) => fc_cpld(11 downto 0),
      fc_cplh(7 downto 0) => fc_cplh(7 downto 0),
      fc_npd(11 downto 0) => fc_npd(11 downto 0),
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_pd(11 downto 0) => fc_pd(11 downto 0),
      fc_ph(7 downto 0) => fc_ph(7 downto 0),
      fc_sel(2 downto 0) => fc_sel(2 downto 0),
      gt_ch_drp_rdy(7 downto 0) => NLW_U0_gt_ch_drp_rdy_UNCONNECTED(7 downto 0),
      icap_clk => '0',
      icap_csib => '0',
      icap_i(31) => '0',
      icap_i(30) => '0',
      icap_i(29) => '0',
      icap_i(28) => '0',
      icap_i(27) => '0',
      icap_i(26) => '0',
      icap_i(25) => '0',
      icap_i(24) => '0',
      icap_i(23) => '0',
      icap_i(22) => '0',
      icap_i(21) => '0',
      icap_i(20) => '0',
      icap_i(19) => '0',
      icap_i(18) => '0',
      icap_i(17) => '0',
      icap_i(16) => '0',
      icap_i(15) => '0',
      icap_i(14) => '0',
      icap_i(13) => '0',
      icap_i(12) => '0',
      icap_i(11) => '0',
      icap_i(10) => '0',
      icap_i(9) => '0',
      icap_i(8) => '0',
      icap_i(7) => '0',
      icap_i(6) => '0',
      icap_i(5) => '0',
      icap_i(4) => '0',
      icap_i(3) => '0',
      icap_i(2) => '0',
      icap_i(1) => '0',
      icap_i(0) => '0',
      icap_o(31 downto 0) => NLW_U0_icap_o_UNCONNECTED(31 downto 0),
      icap_rdwrb => '0',
      int_dclk_out => NLW_U0_int_dclk_out_UNCONNECTED,
      int_mmcm_lock_out => NLW_U0_int_mmcm_lock_out_UNCONNECTED,
      int_oobclk_out => NLW_U0_int_oobclk_out_UNCONNECTED,
      int_pclk_out_slave => NLW_U0_int_pclk_out_slave_UNCONNECTED,
      int_pclk_sel_slave(7) => '0',
      int_pclk_sel_slave(6) => '0',
      int_pclk_sel_slave(5) => '0',
      int_pclk_sel_slave(4) => '0',
      int_pclk_sel_slave(3) => '0',
      int_pclk_sel_slave(2) => '0',
      int_pclk_sel_slave(1) => '0',
      int_pclk_sel_slave(0) => '0',
      int_pipe_rxusrclk_out => NLW_U0_int_pipe_rxusrclk_out_UNCONNECTED,
      int_qplllock_out(1 downto 0) => NLW_U0_int_qplllock_out_UNCONNECTED(1 downto 0),
      int_qplloutclk_out(1 downto 0) => NLW_U0_int_qplloutclk_out_UNCONNECTED(1 downto 0),
      int_qplloutrefclk_out(1 downto 0) => NLW_U0_int_qplloutrefclk_out_UNCONNECTED(1 downto 0),
      int_rxoutclk_out(7 downto 0) => NLW_U0_int_rxoutclk_out_UNCONNECTED(7 downto 0),
      int_userclk1_out => NLW_U0_int_userclk1_out_UNCONNECTED,
      int_userclk2_out => NLW_U0_int_userclk2_out_UNCONNECTED,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(7 downto 0) => m_axis_rx_tkeep(7 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(21 downto 0) => m_axis_rx_tuser(21 downto 0),
      m_axis_rx_tvalid => m_axis_rx_tvalid,
      pci_exp_rxn(7 downto 0) => pci_exp_rxn(7 downto 0),
      pci_exp_rxp(7 downto 0) => pci_exp_rxp(7 downto 0),
      pci_exp_txn(7 downto 0) => pci_exp_txn(7 downto 0),
      pci_exp_txp(7 downto 0) => pci_exp_txp(7 downto 0),
      pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0),
      pcie_drp_clk => pcie_drp_clk,
      pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0),
      pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0),
      pcie_drp_en => pcie_drp_en,
      pcie_drp_rdy => pcie_drp_rdy,
      pcie_drp_we => pcie_drp_we,
      pipe_cpll_lock(7 downto 0) => NLW_U0_pipe_cpll_lock_UNCONNECTED(7 downto 0),
      pipe_dclk_in => '0',
      pipe_debug(31 downto 0) => NLW_U0_pipe_debug_UNCONNECTED(31 downto 0),
      pipe_debug_0(7 downto 0) => NLW_U0_pipe_debug_0_UNCONNECTED(7 downto 0),
      pipe_debug_1(7 downto 0) => NLW_U0_pipe_debug_1_UNCONNECTED(7 downto 0),
      pipe_debug_2(7 downto 0) => NLW_U0_pipe_debug_2_UNCONNECTED(7 downto 0),
      pipe_debug_3(7 downto 0) => NLW_U0_pipe_debug_3_UNCONNECTED(7 downto 0),
      pipe_debug_4(7 downto 0) => NLW_U0_pipe_debug_4_UNCONNECTED(7 downto 0),
      pipe_debug_5(7 downto 0) => NLW_U0_pipe_debug_5_UNCONNECTED(7 downto 0),
      pipe_debug_6(7 downto 0) => NLW_U0_pipe_debug_6_UNCONNECTED(7 downto 0),
      pipe_debug_7(7 downto 0) => NLW_U0_pipe_debug_7_UNCONNECTED(7 downto 0),
      pipe_debug_8(7 downto 0) => NLW_U0_pipe_debug_8_UNCONNECTED(7 downto 0),
      pipe_debug_9(7 downto 0) => NLW_U0_pipe_debug_9_UNCONNECTED(7 downto 0),
      pipe_dmonitorout(119 downto 0) => NLW_U0_pipe_dmonitorout_UNCONNECTED(119 downto 0),
      pipe_drp_fsm(55 downto 0) => NLW_U0_pipe_drp_fsm_UNCONNECTED(55 downto 0),
      pipe_eyescandataerror(7 downto 0) => NLW_U0_pipe_eyescandataerror_UNCONNECTED(7 downto 0),
      pipe_gen3_out => NLW_U0_pipe_gen3_out_UNCONNECTED,
      pipe_loopback(2) => '0',
      pipe_loopback(1) => '0',
      pipe_loopback(0) => '0',
      pipe_mmcm_lock_in => '1',
      pipe_mmcm_rst_n => '1',
      pipe_oobclk_in => '0',
      pipe_pclk_in => '0',
      pipe_pclk_sel_out(7 downto 0) => NLW_U0_pipe_pclk_sel_out_UNCONNECTED(7 downto 0),
      pipe_qpll_lock(1 downto 0) => NLW_U0_pipe_qpll_lock_UNCONNECTED(1 downto 0),
      pipe_qrst_fsm(11 downto 0) => NLW_U0_pipe_qrst_fsm_UNCONNECTED(11 downto 0),
      pipe_qrst_idle => NLW_U0_pipe_qrst_idle_UNCONNECTED,
      pipe_rate_fsm(39 downto 0) => NLW_U0_pipe_rate_fsm_UNCONNECTED(39 downto 0),
      pipe_rate_idle => NLW_U0_pipe_rate_idle_UNCONNECTED,
      pipe_rst_fsm(4 downto 0) => NLW_U0_pipe_rst_fsm_UNCONNECTED(4 downto 0),
      pipe_rst_idle => NLW_U0_pipe_rst_idle_UNCONNECTED,
      pipe_rx_0_sigs(24) => '0',
      pipe_rx_0_sigs(23) => '0',
      pipe_rx_0_sigs(22) => '0',
      pipe_rx_0_sigs(21) => '0',
      pipe_rx_0_sigs(20) => '0',
      pipe_rx_0_sigs(19) => '0',
      pipe_rx_0_sigs(18) => '0',
      pipe_rx_0_sigs(17) => '0',
      pipe_rx_0_sigs(16) => '0',
      pipe_rx_0_sigs(15) => '0',
      pipe_rx_0_sigs(14) => '0',
      pipe_rx_0_sigs(13) => '0',
      pipe_rx_0_sigs(12) => '0',
      pipe_rx_0_sigs(11) => '0',
      pipe_rx_0_sigs(10) => '0',
      pipe_rx_0_sigs(9) => '0',
      pipe_rx_0_sigs(8) => '0',
      pipe_rx_0_sigs(7) => '0',
      pipe_rx_0_sigs(6) => '0',
      pipe_rx_0_sigs(5) => '0',
      pipe_rx_0_sigs(4) => '0',
      pipe_rx_0_sigs(3) => '0',
      pipe_rx_0_sigs(2) => '0',
      pipe_rx_0_sigs(1) => '0',
      pipe_rx_0_sigs(0) => '0',
      pipe_rx_1_sigs(24) => '0',
      pipe_rx_1_sigs(23) => '0',
      pipe_rx_1_sigs(22) => '0',
      pipe_rx_1_sigs(21) => '0',
      pipe_rx_1_sigs(20) => '0',
      pipe_rx_1_sigs(19) => '0',
      pipe_rx_1_sigs(18) => '0',
      pipe_rx_1_sigs(17) => '0',
      pipe_rx_1_sigs(16) => '0',
      pipe_rx_1_sigs(15) => '0',
      pipe_rx_1_sigs(14) => '0',
      pipe_rx_1_sigs(13) => '0',
      pipe_rx_1_sigs(12) => '0',
      pipe_rx_1_sigs(11) => '0',
      pipe_rx_1_sigs(10) => '0',
      pipe_rx_1_sigs(9) => '0',
      pipe_rx_1_sigs(8) => '0',
      pipe_rx_1_sigs(7) => '0',
      pipe_rx_1_sigs(6) => '0',
      pipe_rx_1_sigs(5) => '0',
      pipe_rx_1_sigs(4) => '0',
      pipe_rx_1_sigs(3) => '0',
      pipe_rx_1_sigs(2) => '0',
      pipe_rx_1_sigs(1) => '0',
      pipe_rx_1_sigs(0) => '0',
      pipe_rx_2_sigs(24) => '0',
      pipe_rx_2_sigs(23) => '0',
      pipe_rx_2_sigs(22) => '0',
      pipe_rx_2_sigs(21) => '0',
      pipe_rx_2_sigs(20) => '0',
      pipe_rx_2_sigs(19) => '0',
      pipe_rx_2_sigs(18) => '0',
      pipe_rx_2_sigs(17) => '0',
      pipe_rx_2_sigs(16) => '0',
      pipe_rx_2_sigs(15) => '0',
      pipe_rx_2_sigs(14) => '0',
      pipe_rx_2_sigs(13) => '0',
      pipe_rx_2_sigs(12) => '0',
      pipe_rx_2_sigs(11) => '0',
      pipe_rx_2_sigs(10) => '0',
      pipe_rx_2_sigs(9) => '0',
      pipe_rx_2_sigs(8) => '0',
      pipe_rx_2_sigs(7) => '0',
      pipe_rx_2_sigs(6) => '0',
      pipe_rx_2_sigs(5) => '0',
      pipe_rx_2_sigs(4) => '0',
      pipe_rx_2_sigs(3) => '0',
      pipe_rx_2_sigs(2) => '0',
      pipe_rx_2_sigs(1) => '0',
      pipe_rx_2_sigs(0) => '0',
      pipe_rx_3_sigs(24) => '0',
      pipe_rx_3_sigs(23) => '0',
      pipe_rx_3_sigs(22) => '0',
      pipe_rx_3_sigs(21) => '0',
      pipe_rx_3_sigs(20) => '0',
      pipe_rx_3_sigs(19) => '0',
      pipe_rx_3_sigs(18) => '0',
      pipe_rx_3_sigs(17) => '0',
      pipe_rx_3_sigs(16) => '0',
      pipe_rx_3_sigs(15) => '0',
      pipe_rx_3_sigs(14) => '0',
      pipe_rx_3_sigs(13) => '0',
      pipe_rx_3_sigs(12) => '0',
      pipe_rx_3_sigs(11) => '0',
      pipe_rx_3_sigs(10) => '0',
      pipe_rx_3_sigs(9) => '0',
      pipe_rx_3_sigs(8) => '0',
      pipe_rx_3_sigs(7) => '0',
      pipe_rx_3_sigs(6) => '0',
      pipe_rx_3_sigs(5) => '0',
      pipe_rx_3_sigs(4) => '0',
      pipe_rx_3_sigs(3) => '0',
      pipe_rx_3_sigs(2) => '0',
      pipe_rx_3_sigs(1) => '0',
      pipe_rx_3_sigs(0) => '0',
      pipe_rx_4_sigs(24) => '0',
      pipe_rx_4_sigs(23) => '0',
      pipe_rx_4_sigs(22) => '0',
      pipe_rx_4_sigs(21) => '0',
      pipe_rx_4_sigs(20) => '0',
      pipe_rx_4_sigs(19) => '0',
      pipe_rx_4_sigs(18) => '0',
      pipe_rx_4_sigs(17) => '0',
      pipe_rx_4_sigs(16) => '0',
      pipe_rx_4_sigs(15) => '0',
      pipe_rx_4_sigs(14) => '0',
      pipe_rx_4_sigs(13) => '0',
      pipe_rx_4_sigs(12) => '0',
      pipe_rx_4_sigs(11) => '0',
      pipe_rx_4_sigs(10) => '0',
      pipe_rx_4_sigs(9) => '0',
      pipe_rx_4_sigs(8) => '0',
      pipe_rx_4_sigs(7) => '0',
      pipe_rx_4_sigs(6) => '0',
      pipe_rx_4_sigs(5) => '0',
      pipe_rx_4_sigs(4) => '0',
      pipe_rx_4_sigs(3) => '0',
      pipe_rx_4_sigs(2) => '0',
      pipe_rx_4_sigs(1) => '0',
      pipe_rx_4_sigs(0) => '0',
      pipe_rx_5_sigs(24) => '0',
      pipe_rx_5_sigs(23) => '0',
      pipe_rx_5_sigs(22) => '0',
      pipe_rx_5_sigs(21) => '0',
      pipe_rx_5_sigs(20) => '0',
      pipe_rx_5_sigs(19) => '0',
      pipe_rx_5_sigs(18) => '0',
      pipe_rx_5_sigs(17) => '0',
      pipe_rx_5_sigs(16) => '0',
      pipe_rx_5_sigs(15) => '0',
      pipe_rx_5_sigs(14) => '0',
      pipe_rx_5_sigs(13) => '0',
      pipe_rx_5_sigs(12) => '0',
      pipe_rx_5_sigs(11) => '0',
      pipe_rx_5_sigs(10) => '0',
      pipe_rx_5_sigs(9) => '0',
      pipe_rx_5_sigs(8) => '0',
      pipe_rx_5_sigs(7) => '0',
      pipe_rx_5_sigs(6) => '0',
      pipe_rx_5_sigs(5) => '0',
      pipe_rx_5_sigs(4) => '0',
      pipe_rx_5_sigs(3) => '0',
      pipe_rx_5_sigs(2) => '0',
      pipe_rx_5_sigs(1) => '0',
      pipe_rx_5_sigs(0) => '0',
      pipe_rx_6_sigs(24) => '0',
      pipe_rx_6_sigs(23) => '0',
      pipe_rx_6_sigs(22) => '0',
      pipe_rx_6_sigs(21) => '0',
      pipe_rx_6_sigs(20) => '0',
      pipe_rx_6_sigs(19) => '0',
      pipe_rx_6_sigs(18) => '0',
      pipe_rx_6_sigs(17) => '0',
      pipe_rx_6_sigs(16) => '0',
      pipe_rx_6_sigs(15) => '0',
      pipe_rx_6_sigs(14) => '0',
      pipe_rx_6_sigs(13) => '0',
      pipe_rx_6_sigs(12) => '0',
      pipe_rx_6_sigs(11) => '0',
      pipe_rx_6_sigs(10) => '0',
      pipe_rx_6_sigs(9) => '0',
      pipe_rx_6_sigs(8) => '0',
      pipe_rx_6_sigs(7) => '0',
      pipe_rx_6_sigs(6) => '0',
      pipe_rx_6_sigs(5) => '0',
      pipe_rx_6_sigs(4) => '0',
      pipe_rx_6_sigs(3) => '0',
      pipe_rx_6_sigs(2) => '0',
      pipe_rx_6_sigs(1) => '0',
      pipe_rx_6_sigs(0) => '0',
      pipe_rx_7_sigs(24) => '0',
      pipe_rx_7_sigs(23) => '0',
      pipe_rx_7_sigs(22) => '0',
      pipe_rx_7_sigs(21) => '0',
      pipe_rx_7_sigs(20) => '0',
      pipe_rx_7_sigs(19) => '0',
      pipe_rx_7_sigs(18) => '0',
      pipe_rx_7_sigs(17) => '0',
      pipe_rx_7_sigs(16) => '0',
      pipe_rx_7_sigs(15) => '0',
      pipe_rx_7_sigs(14) => '0',
      pipe_rx_7_sigs(13) => '0',
      pipe_rx_7_sigs(12) => '0',
      pipe_rx_7_sigs(11) => '0',
      pipe_rx_7_sigs(10) => '0',
      pipe_rx_7_sigs(9) => '0',
      pipe_rx_7_sigs(8) => '0',
      pipe_rx_7_sigs(7) => '0',
      pipe_rx_7_sigs(6) => '0',
      pipe_rx_7_sigs(5) => '0',
      pipe_rx_7_sigs(4) => '0',
      pipe_rx_7_sigs(3) => '0',
      pipe_rx_7_sigs(2) => '0',
      pipe_rx_7_sigs(1) => '0',
      pipe_rx_7_sigs(0) => '0',
      pipe_rxbufstatus(23 downto 0) => NLW_U0_pipe_rxbufstatus_UNCONNECTED(23 downto 0),
      pipe_rxcommadet(7 downto 0) => NLW_U0_pipe_rxcommadet_UNCONNECTED(7 downto 0),
      pipe_rxdisperr(63 downto 0) => NLW_U0_pipe_rxdisperr_UNCONNECTED(63 downto 0),
      pipe_rxdlysresetdone(7 downto 0) => NLW_U0_pipe_rxdlysresetdone_UNCONNECTED(7 downto 0),
      pipe_rxnotintable(63 downto 0) => NLW_U0_pipe_rxnotintable_UNCONNECTED(63 downto 0),
      pipe_rxoutclk_in(7) => '0',
      pipe_rxoutclk_in(6) => '0',
      pipe_rxoutclk_in(5) => '0',
      pipe_rxoutclk_in(4) => '0',
      pipe_rxoutclk_in(3) => '0',
      pipe_rxoutclk_in(2) => '0',
      pipe_rxoutclk_in(1) => '0',
      pipe_rxoutclk_in(0) => '0',
      pipe_rxoutclk_out(7 downto 0) => NLW_U0_pipe_rxoutclk_out_UNCONNECTED(7 downto 0),
      pipe_rxphaligndone(7 downto 0) => NLW_U0_pipe_rxphaligndone_UNCONNECTED(7 downto 0),
      pipe_rxpmaresetdone(7 downto 0) => NLW_U0_pipe_rxpmaresetdone_UNCONNECTED(7 downto 0),
      pipe_rxprbscntreset => '0',
      pipe_rxprbserr(7 downto 0) => NLW_U0_pipe_rxprbserr_UNCONNECTED(7 downto 0),
      pipe_rxprbssel(2) => '0',
      pipe_rxprbssel(1) => '0',
      pipe_rxprbssel(0) => '0',
      pipe_rxstatus(23 downto 0) => NLW_U0_pipe_rxstatus_UNCONNECTED(23 downto 0),
      pipe_rxsyncdone(7 downto 0) => NLW_U0_pipe_rxsyncdone_UNCONNECTED(7 downto 0),
      pipe_rxusrclk_in => '0',
      pipe_sync_fsm_rx(55 downto 0) => NLW_U0_pipe_sync_fsm_rx_UNCONNECTED(55 downto 0),
      pipe_sync_fsm_tx(47 downto 0) => NLW_U0_pipe_sync_fsm_tx_UNCONNECTED(47 downto 0),
      pipe_tx_0_sigs(22 downto 0) => NLW_U0_pipe_tx_0_sigs_UNCONNECTED(22 downto 0),
      pipe_tx_1_sigs(22 downto 0) => NLW_U0_pipe_tx_1_sigs_UNCONNECTED(22 downto 0),
      pipe_tx_2_sigs(22 downto 0) => NLW_U0_pipe_tx_2_sigs_UNCONNECTED(22 downto 0),
      pipe_tx_3_sigs(22 downto 0) => NLW_U0_pipe_tx_3_sigs_UNCONNECTED(22 downto 0),
      pipe_tx_4_sigs(22 downto 0) => NLW_U0_pipe_tx_4_sigs_UNCONNECTED(22 downto 0),
      pipe_tx_5_sigs(22 downto 0) => NLW_U0_pipe_tx_5_sigs_UNCONNECTED(22 downto 0),
      pipe_tx_6_sigs(22 downto 0) => NLW_U0_pipe_tx_6_sigs_UNCONNECTED(22 downto 0),
      pipe_tx_7_sigs(22 downto 0) => NLW_U0_pipe_tx_7_sigs_UNCONNECTED(22 downto 0),
      pipe_txdlysresetdone(7 downto 0) => NLW_U0_pipe_txdlysresetdone_UNCONNECTED(7 downto 0),
      pipe_txinhibit(7) => '0',
      pipe_txinhibit(6) => '0',
      pipe_txinhibit(5) => '0',
      pipe_txinhibit(4) => '0',
      pipe_txinhibit(3) => '0',
      pipe_txinhibit(2) => '0',
      pipe_txinhibit(1) => '0',
      pipe_txinhibit(0) => '0',
      pipe_txoutclk_out => NLW_U0_pipe_txoutclk_out_UNCONNECTED,
      pipe_txphaligndone(7 downto 0) => NLW_U0_pipe_txphaligndone_UNCONNECTED(7 downto 0),
      pipe_txphinitdone(7 downto 0) => NLW_U0_pipe_txphinitdone_UNCONNECTED(7 downto 0),
      pipe_txprbsforceerr => '0',
      pipe_txprbssel(2) => '0',
      pipe_txprbssel(1) => '0',
      pipe_txprbssel(0) => '0',
      pipe_userclk1_in => '1',
      pipe_userclk2_in => '0',
      pl_directed_change_done => NLW_U0_pl_directed_change_done_UNCONNECTED,
      pl_directed_link_auton => '0',
      pl_directed_link_change(1) => '0',
      pl_directed_link_change(0) => '0',
      pl_directed_link_speed => '0',
      pl_directed_link_width(1) => '0',
      pl_directed_link_width(0) => '0',
      pl_downstream_deemph_source => '0',
      pl_initial_link_width(2 downto 0) => NLW_U0_pl_initial_link_width_UNCONNECTED(2 downto 0),
      pl_lane_reversal_mode(1 downto 0) => NLW_U0_pl_lane_reversal_mode_UNCONNECTED(1 downto 0),
      pl_link_gen2_cap => NLW_U0_pl_link_gen2_cap_UNCONNECTED,
      pl_link_partner_gen2_supported => NLW_U0_pl_link_partner_gen2_supported_UNCONNECTED,
      pl_link_upcfg_cap => NLW_U0_pl_link_upcfg_cap_UNCONNECTED,
      pl_ltssm_state(5 downto 0) => NLW_U0_pl_ltssm_state_UNCONNECTED(5 downto 0),
      pl_phy_lnk_up => NLW_U0_pl_phy_lnk_up_UNCONNECTED,
      pl_received_hot_rst => NLW_U0_pl_received_hot_rst_UNCONNECTED,
      pl_rx_pm_state(1 downto 0) => NLW_U0_pl_rx_pm_state_UNCONNECTED(1 downto 0),
      pl_sel_lnk_rate => NLW_U0_pl_sel_lnk_rate_UNCONNECTED,
      pl_sel_lnk_width(1 downto 0) => NLW_U0_pl_sel_lnk_width_UNCONNECTED(1 downto 0),
      pl_transmit_hot_rst => '0',
      pl_tx_pm_state(2 downto 0) => NLW_U0_pl_tx_pm_state_UNCONNECTED(2 downto 0),
      pl_upstream_prefer_deemph => '1',
      qpll_drp_clk => NLW_U0_qpll_drp_clk_UNCONNECTED,
      qpll_drp_crscode(11) => '0',
      qpll_drp_crscode(10) => '0',
      qpll_drp_crscode(9) => '0',
      qpll_drp_crscode(8) => '0',
      qpll_drp_crscode(7) => '0',
      qpll_drp_crscode(6) => '0',
      qpll_drp_crscode(5) => '0',
      qpll_drp_crscode(4) => '0',
      qpll_drp_crscode(3) => '0',
      qpll_drp_crscode(2) => '0',
      qpll_drp_crscode(1) => '0',
      qpll_drp_crscode(0) => '0',
      qpll_drp_done(1) => '0',
      qpll_drp_done(0) => '0',
      qpll_drp_fsm(17) => '0',
      qpll_drp_fsm(16) => '0',
      qpll_drp_fsm(15) => '0',
      qpll_drp_fsm(14) => '0',
      qpll_drp_fsm(13) => '0',
      qpll_drp_fsm(12) => '0',
      qpll_drp_fsm(11) => '0',
      qpll_drp_fsm(10) => '0',
      qpll_drp_fsm(9) => '0',
      qpll_drp_fsm(8) => '0',
      qpll_drp_fsm(7) => '0',
      qpll_drp_fsm(6) => '0',
      qpll_drp_fsm(5) => '0',
      qpll_drp_fsm(4) => '0',
      qpll_drp_fsm(3) => '0',
      qpll_drp_fsm(2) => '0',
      qpll_drp_fsm(1) => '0',
      qpll_drp_fsm(0) => '0',
      qpll_drp_gen3 => NLW_U0_qpll_drp_gen3_UNCONNECTED,
      qpll_drp_ovrd => NLW_U0_qpll_drp_ovrd_UNCONNECTED,
      qpll_drp_reset(1) => '0',
      qpll_drp_reset(0) => '0',
      qpll_drp_rst_n => NLW_U0_qpll_drp_rst_n_UNCONNECTED,
      qpll_drp_start => NLW_U0_qpll_drp_start_UNCONNECTED,
      qpll_qplld => NLW_U0_qpll_qplld_UNCONNECTED,
      qpll_qplllock(1) => '0',
      qpll_qplllock(0) => '0',
      qpll_qplloutclk(1) => '0',
      qpll_qplloutclk(0) => '0',
      qpll_qplloutrefclk(1) => '0',
      qpll_qplloutrefclk(0) => '0',
      qpll_qpllreset(1 downto 0) => NLW_U0_qpll_qpllreset_UNCONNECTED(1 downto 0),
      rx_np_ok => rx_np_ok,
      rx_np_req => rx_np_req,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(7 downto 0) => s_axis_tx_tkeep(7 downto 0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => s_axis_tx_tready,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      startup_cfgclk => NLW_U0_startup_cfgclk_UNCONNECTED,
      startup_cfgmclk => NLW_U0_startup_cfgmclk_UNCONNECTED,
      startup_clk => '0',
      startup_eos => NLW_U0_startup_eos_UNCONNECTED,
      startup_eos_in => '0',
      startup_gsr => '0',
      startup_gts => '0',
      startup_keyclearb => '1',
      startup_pack => '0',
      startup_preq => NLW_U0_startup_preq_UNCONNECTED,
      startup_usrcclko => '1',
      startup_usrcclkts => '0',
      startup_usrdoneo => '0',
      startup_usrdonets => '1',
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n,
      tx_buf_av(5 downto 0) => tx_buf_av(5 downto 0),
      tx_cfg_gnt => tx_cfg_gnt,
      tx_cfg_req => tx_cfg_req,
      tx_err_drop => tx_err_drop,
      user_app_rdy => user_app_rdy,
      user_clk_out => user_clk_out,
      user_lnk_up => user_lnk_up,
      user_reset_out => user_reset_out
    );
end STRUCTURE;
