[Common]

Architecture  = VC707
FPGAId        = XC7VX485T
FPGAFullId    = xc7vx485tffg1761-2
ImplementFlow = Vivado
Connections   = ./VC707.co
;BaseCtrlConstraints = ./ML605_BaseConstraints.ucf
BaseCtrlConstraints = 
AvailableRegister   = 607200
AvailableLUT        = 303600
AvailableRAM        = 1030


[MiniX_Mono]
AcceptedTargetArchitectures      = MiniX
Binary      			 = ./MiniX/ctrl_096s-096t-000b-100m_mono/ctrl_096s-096t-000b-100m_mono.bit
CtrlIO      			 = ./MiniX/ctrl_096s-096t-000b-100m_mono/ctrl_096s-096t-000b-100m_mono.ucf
Frequency			 = 100	
ClockMode                        = mono
MinDividor			 = 2
Communications			 = SPI
MaxStimuli			 = 96
MaxTraces			 = 96
MaxBiDir			 = 0
NbMemoryLines			 = 1
NbMemoryBlocksPerLine		 = 2
MemoryBlockWidth		 = 4
NbMemoryRepetitionFieldsPerBlock = 1
MemoryBlockDepth		 = 250

