
use work.BOPM_pkg.all;

----------------------------------------------------------------------------------------------------
-- Actual File Name      = BOPM.vhd
-- Title & purpose       =  - 
-- Author                = Automaticaly generated by YANGO netlist generator - made by Matthieu PAYET (ADACSYS) - matthieu.payet@adacsys.com
-- Creation Date         = 2016-03-15 16:55
-- Version               = 0.1
-- Simple Description    = 
-- Specific issues       = 
-- Speed                 = 
-- Area estimates        = 
-- Tools (version)       = ISE 13.1
-- HDL standard followed = VHDL 2001 standard
-- Revisions & ECOs      = 0.01
----------------------------------------------------------------------------------------------------
	
library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
-- ENTITY: BOPM - 
--------------------------------------------------------------------------------
entity BOPMTest is 
	generic(
		FlitWidth            : natural             := 16;
		DimX                 : natural             := 2;
		DimY                 : natural             := 1;
		InputFifoDepth_Table : DIMX_x_DIMY_NUMERIC := (32,32);
		NbOutputs_Table      : DIMX_x_DIMY_NUMERIC := (5,5);
		NbInputs_Table       : DIMX_x_DIMY_NUMERIC := (5,5));
	port(
		clock         : IN  std_logic;
		reset         : IN  std_logic;
		LED           : OUT std_logic_vector(7 downto 0);
		
		DataIn  : IN  std_logic_vector(FlitWidth-1 downto 0);
		Rx      : IN  std_logic;
		AckRx   : OUT std_logic;
		
		DataOut : OUT std_logic_vector(FlitWidth-1 downto 0);
		Tx      : OUT std_logic;
		AckTx   : IN  std_logic
	);
end entity BOPMTest;

--------------------------------------------------------------------------------
-- ARCHITECTURE: RTL - 
--------------------------------------------------------------------------------
architecture RTL of BOPMTest is

	signal NoC_0_AckRx : std_logic_vector(DimX*DimY-1 downto 0);
	signal NoC_0_AckTx : std_logic_vector(DimX*DimY-1 downto 0);
	signal NoC_0_DataIn : FLITS(DimX*DimY-1 downto 0);
	signal NoC_0_DataOut : FLITS(DimX*DimY-1 downto 0);
	signal NoC_0_Rx : std_logic_vector(DimX*DimY-1 downto 0);
	signal NoC_0_Tx : std_logic_vector(DimX*DimY-1 downto 0);
	signal PCIe_0_AckRx : std_logic;
	signal PCIe_0_AckTx : std_logic;
	signal PCIe_0_DataIn : std_logic_vector(15 downto 0);
	signal PCIe_0_DataOut : std_logic_vector(15 downto 0);
	signal PCIe_0_Rx : std_logic;
	signal PCIe_0_Tx : std_logic;
	signal Wrapped_BOPM_computation_unit_Service_1_AckRx : std_logic;
	signal Wrapped_BOPM_computation_unit_Service_1_AckTx : std_logic;
	signal Wrapped_BOPM_computation_unit_Service_1_DataIn : std_logic_vector(FlitWidth-1 downto 0);
	signal Wrapped_BOPM_computation_unit_Service_1_DataOut : std_logic_vector(FlitWidth-1 downto 0);
	signal Wrapped_BOPM_computation_unit_Service_1_Rx : std_logic;
	signal Wrapped_BOPM_computation_unit_Service_1_Tx : std_logic;

begin

	-- ADACSYS On-Chip-Network
	NoC_0: entity work.AdOCNet(RTL)
		generic map(
			FlitWidth => FlitWidth,
			DimX => DimX,
			DimY => DimY,
			InputFifoDepth_Table => InputFifoDepth_Table,
			NbOutputs_Table => NbOutputs_Table,
			NbInputs_Table => NbInputs_Table
			)
		port map(
			AckTx => NoC_0_AckTx,
			DataOut => NoC_0_DataOut,
			reset => reset,
			AckRx => NoC_0_AckRx,
			DataIn => NoC_0_DataIn,
			Rx => NoC_0_Rx,
			Tx => NoC_0_Tx,
			clock => clock
			);
	AckRx <= NoC_0_AckRx(0);
	Wrapped_BOPM_computation_unit_Service_1_AckTx <= NoC_0_AckRx(1);
	NoC_0_AckTx(0) <= AckTx;
	NoC_0_AckTx(1) <= Wrapped_BOPM_computation_unit_Service_1_AckRx;
	NoC_0_DataIn(0) <= DataIn;
	NoC_0_DataIn(1) <= Wrapped_BOPM_computation_unit_Service_1_DataOut;
	DataOut <= NoC_0_DataOut(0);
	Wrapped_BOPM_computation_unit_Service_1_DataIn <= NoC_0_DataOut(1);
	NoC_0_Rx(0) <= Rx;
	NoC_0_Rx(1) <= Wrapped_BOPM_computation_unit_Service_1_Tx;
	Tx <= NoC_0_Tx(0);
	Wrapped_BOPM_computation_unit_Service_1_Rx <= NoC_0_Tx(1);
	-----------------------------------------------------------------
	-- Wrapper for adaptation to interfaces ['HandShake_IN', 'HandShake_OUT']
	Wrapped_BOPM_computation_unit_Service_1: entity work.Wrapped_BOPM_computation_unit(RTL)
		port map(
			AckRx => Wrapped_BOPM_computation_unit_Service_1_AckRx,
			AckTx => Wrapped_BOPM_computation_unit_Service_1_AckTx,
			DataOut => Wrapped_BOPM_computation_unit_Service_1_DataOut,
			reset => reset,
			Rx => Wrapped_BOPM_computation_unit_Service_1_Rx,
			DataIn => Wrapped_BOPM_computation_unit_Service_1_DataIn,
			Tx => Wrapped_BOPM_computation_unit_Service_1_Tx,
			clock => clock
			);
	-----------------------------------------------------------------

end architecture RTL;

