
----------------------------------------------------------------------------------------------------
-- Actual File Name      = BOPM.vhd
-- Title & purpose       =  - 
-- Author                = Automaticaly generated by YANGO netlist generator - made by Matthieu PAYET (ADACSYS) - matthieu.payet@adacsys.com
-- Creation Date         = 2016-05-03 09:18
-- Version               = 0.1
-- Simple Description    = 
-- Specific issues       = 
-- Speed                 = 
-- Area estimates        = 
-- Tools (version)       = ISE 13.1
-- HDL standard followed = VHDL 2001 standard
-- Revisions & ECOs      = 0.01
----------------------------------------------------------------------------------------------------
	
library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
-- ENTITY: BOPM - 
--------------------------------------------------------------------------------
entity SingleNodeBopm is 
	generic(
		DimX                 : natural             := 2;
		DimY                 : natural             := 1;
		FlitWidth            : natural             := 16;
		NbInputs_Table       : DIMX_x_DIMY_NUMERIC := (5,5);
		NbOutputs_Table      : DIMX_x_DIMY_NUMERIC := (5,5);
		InputFifoDepth_Table : DIMX_x_DIMY_NUMERIC := (32,32);
		ComHeader            : std_logic_vector(15 downto 0)    := "0000000000000000");
	port(
		clock          : IN  std_logic;
		reset          : IN  std_logic;
		
		PCIe_0_DataIn  : OUT std_logic_vector(FlitWidth-1 downto 0);
		PCIe_0_Rx      : OUT std_logic;
		PCIe_0_AckRx   : IN  std_logic;
		
		PCIe_0_AckTx   : OUT std_logic;
		PCIe_0_DataOut : IN  std_logic_vector(FlitWidth-1 downto 0);
		PCIe_0_Tx      : IN  std_logic);
		
end entity SingleNodeBopm;

--------------------------------------------------------------------------------
-- ARCHITECTURE: RTL - 
--------------------------------------------------------------------------------
architecture RTL of SingleNodeBopm is

	signal NoC_0_AckRx   : std_logic_vector(DimX*DimY-1 downto 0);
	signal NoC_0_AckTx   : std_logic_vector(DimX*DimY-1 downto 0);
	signal NoC_0_DataIn  : FLITS(DimX*DimY-1 downto 0);
	signal NoC_0_DataOut : FLITS(DimX*DimY-1 downto 0);
	signal NoC_0_Rx      : std_logic_vector(DimX*DimY-1 downto 0);
	signal NoC_0_Tx      : std_logic_vector(DimX*DimY-1 downto 0);
	signal Wrapped_BOPM_computation_unit_dummy_Service_1_AckRx   : std_logic;
	signal Wrapped_BOPM_computation_unit_dummy_Service_1_AckTx   : std_logic;
	signal Wrapped_BOPM_computation_unit_dummy_Service_1_DataIn  : std_logic_vector(FlitWidth-1 downto 0);
	signal Wrapped_BOPM_computation_unit_dummy_Service_1_DataOut : std_logic_vector(FlitWidth-1 downto 0);
	signal Wrapped_BOPM_computation_unit_dummy_Service_1_Rx      : std_logic;
	signal Wrapped_BOPM_computation_unit_dummy_Service_1_Tx      : std_logic;

begin

	-- ADACSYS On-Chip-Network
	NoC_0: entity work.AdOCNet(RTL)
		generic map(
			InputFifoDepth_Table => InputFifoDepth_Table,
			NbOutputs_Table      => NbOutputs_Table,
			NbInputs_Table       => NbInputs_Table,
			FlitWidth            => FlitWidth,
			DimY                 => DimY,
			DimX                 => DimX
			)
		port map(
			clock   => clock,
			reset   => reset,
			DataIn  => NoC_0_DataIn,
			Rx      => NoC_0_Rx,
			AckRx   => NoC_0_AckRx,
			Tx      => NoC_0_Tx,
			DataOut => NoC_0_DataOut,
			AckTx   => NoC_0_AckTx
			);
			
	Wrapped_BOPM_computation_unit_dummy_Service_1_AckTx  <= NoC_0_AckRx(1);
	Wrapped_BOPM_computation_unit_dummy_Service_1_DataIn <= NoC_0_DataOut(1);
	Wrapped_BOPM_computation_unit_dummy_Service_1_Rx     <= NoC_0_Tx(1);
	NoC_0_AckTx(1)  <= Wrapped_BOPM_computation_unit_dummy_Service_1_AckRx;
	NoC_0_DataIn(1) <= Wrapped_BOPM_computation_unit_dummy_Service_1_DataOut;
	NoC_0_Rx(1)     <= Wrapped_BOPM_computation_unit_dummy_Service_1_Tx;
	
	-----------------------------------------------------------------
	-- Wrapper for adaptation to interfaces ['HandShake_IN', 'HandShake_OUT']
	Wrapped_BOPM_computation_unit_dummy_Service_1: entity work.Wrapped_BOPM_computation_unit_dummy(RTL)
		generic map(
			ComHeader => ComHeader,
			NBTask    => 5,
			FlitWidth => FlitWidth
			)
		port map(
			clock   => clock,
			reset   => reset,
			DataIn  => Wrapped_BOPM_computation_unit_dummy_Service_1_DataIn,
			Rx      => Wrapped_BOPM_computation_unit_dummy_Service_1_Rx,
			AckTx   => Wrapped_BOPM_computation_unit_dummy_Service_1_AckTx,
			AckRx   => Wrapped_BOPM_computation_unit_dummy_Service_1_AckRx,
			DataOut => Wrapped_BOPM_computation_unit_dummy_Service_1_DataOut,
			Tx      => Wrapped_BOPM_computation_unit_dummy_Service_1_Tx
			);
	-----------------------------------------------------------------

	NoC_0_DataIn(0) <= PCIe_0_DataOut;
	NoC_0_Rx(0) <= PCIe_0_Tx;
	PCIe_0_AckTx <= NoC_0_AckRx(0);
	
	PCIe_0_DataIn <= NoC_0_DataOut(0);
	PCIe_0_Rx <= NoC_0_Tx(0);
	NoC_0_AckTx(0) <= PCIe_0_AckRx;
	
end architecture RTL;

