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## Project    : Series-7 Integrated Block for PCI Express
## File       : PCIeGen1x8If64_ooc.xdc
## Version    : 3.1
#
# This constraints file contains default clock frequencies to be used during out-of-context flows such as
# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
# to match the target frequencies. 
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)

#
create_clock -name PCIeGen1x8If64_sys_clk -period 10 [get_ports sys_clk]
# 100/125/250 MHz

