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## Project    : Series-7 Integrated Block for PCI Express
## File       : PCIeGen1x8If64-PCIE_X1Y0.xdc
## Version    : 3.1
#
###############################################################################
# User Time Names / User Time Groups / Time Specs
###############################################################################

###############################################################################
# User Physical Constraints
###############################################################################


###############################################################################
# Pinout and Related I/O Constraints
###############################################################################


###############################################################################
# Physical Constraints
###############################################################################
#
# Transceiver instance placement.  This constraint selects the
# transceivers to be used, which also dictates the pinout for the
# transmit and receive differential pairs.  Please refer to the
# Virtex-7 GT Transceiver User Guide (UG) for more information.
#

# PCIe Lane 0
set_property LOC GTXE2_CHANNEL_X1Y11 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# PCIe Lane 1
set_property LOC GTXE2_CHANNEL_X1Y10 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# PCIe Lane 2
set_property LOC GTXE2_CHANNEL_X1Y9 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# PCIe Lane 3
set_property LOC GTXE2_CHANNEL_X1Y8 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# PCIe Lane 4
set_property LOC GTXE2_CHANNEL_X1Y7 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# PCIe Lane 5
set_property LOC GTXE2_CHANNEL_X1Y6 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# PCIe Lane 6
set_property LOC GTXE2_CHANNEL_X1Y5 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# PCIe Lane 7
set_property LOC GTXE2_CHANNEL_X1Y4 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]

#
# PCI Express Block placement. This constraint selects the PCI Express
# Block to be used.
#

set_property LOC PCIE_X1Y0 [get_cells $INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_block_i]

#
# BlockRAM placement
#
set_property LOC RAMB36_X14Y25 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[3].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl}]
set_property LOC RAMB36_X13Y26 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[2].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl}]
set_property LOC RAMB36_X13Y25 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[1].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl}]
#set_property LOC RAMB36_X13Y24 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[0].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl}]
set_property LOC RAMB36_X13Y23 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl}]
set_property LOC RAMB36_X13Y22 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[1].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl}]
set_property LOC RAMB36_X13Y21 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[2].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl}]
set_property LOC RAMB36_X13Y20 [get_cells {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl}]

###############################################################################
# Timing Constraints
###############################################################################
#
create_clock -period 10 [get_pins {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i/TXOUTCLK}]
#
#
set_false_path -to [get_pins {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}]
set_false_path -to [get_pins {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S1}]
#
#
set_case_analysis 1 [get_pins {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}]
set_case_analysis 0 [get_pins {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S1}]
set_property DONT_TOUCH true [get_cells -of [get_nets -of [get_pins {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}]]]
#
#
# Timing ignoring the below pins to avoid CDC analysis, but care has been taken in RTL to sync properly to other clock domain.
#
#
set_false_path -through [get_pins {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_block_i/PLPHYLNKUPN}]
set_false_path -through [get_pins {$INSTANCE_PATH_NAME/PCIe_Endpoint/PCIeGen1x8If64_i/U0/inst/pcie_top_i/pcie_7x_i/pcie_block_i/PLRECEIVEDHOTRST}]

#------------------------------------------------------------------------------
# Asynchronous Paths
#------------------------------------------------------------------------------
set_false_path -through [get_pins -hierarchical -filter {NAME=~*/RXELECIDLE}]
set_false_path -through [get_pins -hierarchical -filter {NAME=~*/TXPHINITDONE}]
set_false_path -through [get_pins -hierarchical -filter {NAME=~*/TXPHALIGNDONE}]
set_false_path -through [get_pins -hierarchical -filter {NAME=~*/TXDLYSRESETDONE}]
set_false_path -through [get_pins -hierarchical -filter {NAME=~*/RXDLYSRESETDONE}]
set_false_path -through [get_pins -hierarchical -filter {NAME=~*/RXPHALIGNDONE}]
set_false_path -through [get_pins -hierarchical -filter {NAME=~*/RXCDRLOCK}]
set_false_path -through [get_pins -hierarchical -filter {NAME=~*/CFGMSGRECEIVEDPMETO}]
set_false_path -through [get_pins -hierarchical -filter {NAME=~*/CPLLLOCK}]
set_false_path -through [get_pins -hierarchical -filter {NAME=~*/QPLLLOCK}]
###############################################################################
# End
###############################################################################
