[Common]

Architecture  = ML506
FPGAId        = xc5vsx50t
FPGAFullId    = xc5vsx50t-1-ff1136
ImplementFlow = ISE
Connections   = ./ML506.co
;BaseCtrlConstraints = ./ML506_BaseConstraints.ucf
BaseCtrlConstraints = ./ControlVerif_ML506.ucf
AvailableRegister   = 32640
AvailableLUT        = 32640
AvailableRAM        = 132



[MONO_FPGA]
AcceptedTargetArchitectures      = MiniX
Binary      			 = ./MiniX/ctrl_096s-096t-000b-100m_mono/ctrl_096s-096t-000b-100m_mono.bit
CtrlIO      			 = ./MiniX/ctrl_096s-096t-000b-100m_mono/ctrl_096s-096t-000b-100m_mono.ucf
Frequency			 = 100	
ClockMode                        = mono
MinDividor			 = 2
Communications			 = SPI
MaxStimuli			 = 96
MaxTraces			 = 96
MaxBiDir			 = 0
NbMemoryLines			 = 1
NbMemoryBlocksPerLine		 = 2
MemoryBlockWidth		 = 4
NbMemoryRepetitionFieldsPerBlock = 1
MemoryBlockDepth		 = 250

