[Common]

Architecture  = ML605
FPGAId        = xc6vlx240t
FPGAFullId    = xc6vlx240t-1-ff1156
ImplementFlow = ISE
Connections   = ./ML605.co
;BaseCtrlConstraints = ./ML605_BaseConstraints.ucf
BaseCtrlConstraints = ./ControlVerif_ML605_XM105.ucf
AvailableRegister   = 301440
AvailableLUT        = 150720
AvailableRAM        = 1248


[MiniX_Mono]
AcceptedTargetArchitectures      = MiniX
Binary      			 = ./MiniX/ctrl_096s-096t-000b-100m_mono/ctrl_096s-096t-000b-100m_mono.bit
CtrlIO      			 = ./MiniX/ctrl_096s-096t-000b-100m_mono/ctrl_096s-096t-000b-100m_mono.ucf
Frequency			 = 100	
ClockMode                        = mono
MinDividor			 = 2
Communications			 = SPI
MaxStimuli			 = 96
MaxTraces			 = 96
MaxBiDir			 = 0
NbMemoryLines			 = 1
NbMemoryBlocksPerLine		 = 2
MemoryBlockWidth		 = 4
NbMemoryRepetitionFieldsPerBlock = 1
MemoryBlockDepth		 = 250



[AT-DebugConfig]
AcceptedTargetArchitectures      = MiniX
Binary      			 = ./MiniX/AT-DebugConfig/ctrl_111s-111t-000b-200m_mono.bit
CtrlIO      			 = ./MiniX/AT-DebugConfig/ctrl_111s-111t-000b.ucf
Frequency			 = 200	
ClockMode                        = mono
MinDividor			 = 2
Communications			 = SPI
MaxStimuli			 = 111
MaxTraces			 = 111
MaxBiDir			 = 0
NbMemoryLines			 = 1
NbMemoryBlocksPerLine		 = 4
MemoryBlockWidth		 = 4
NbMemoryRepetitionFieldsPerBlock = 1
MemoryBlockDepth		 = 250

[LENA-XC6Config1]
AcceptedTargetArchitectures      = MiniX
Binary      			 				= ./MiniX/LENA-XC6Config1/ctrl_047s-102t-047b-200m_mono.bit
CtrlIO      			 				= ./MiniX/LENA-XC6Config1/ctrl_047s-102t-047b.ucf
Frequency			 					= 200	
ClockMode                        = mono
MinDividor			 					= 2
Communications			 				= SPI
MaxStimuli			 					= 47
MaxTraces			 					= 102
MaxBiDir			 						= 47
NbMemoryLines			 				= 1
NbMemoryBlocksPerLine		 		= 4
MemoryBlockWidth		 				= 4
NbMemoryRepetitionFieldsPerBlock = 1
MemoryBlockDepth		 				= 250
