// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date        : Fri Jan 15 09:35:20 2016
// Host        : cimepe30 running 64-bit Debian GNU/Linux 7.2 (wheezy)
// Command     : write_verilog -force -mode funcsim /tima/payet/VC707_IPs/PCIeGen1x8If64/PCIeGen1x8If64_funcsim.v
// Design      : PCIeGen1x8If64
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "PCIeGen1x8If64,PCIeGen1x8If64_pcie2_top,{}" *) (* core_generation_info = "PCIeGen1x8If64,PCIeGen1x8If64_pcie2_top,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=pcie_7x,x_ipVersion=3.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,c_component_name=PCIeGen1x8If64,dev_port_type=0000,c_dev_port_type=0,c_header_type=00,c_upstream_facing=TRUE,max_lnk_wdt=001000,max_lnk_spd=1,c_gen1=false,pci_exp_int_freq=3,c_pcie_fast_config=0,bar_0=FFFFFC00,bar_1=00000000,bar_2=00000000,bar_3=00000000,bar_4=00000000,bar_5=00000000,xrom_bar=00000000,cost_table=1,ven_id=10EE,dev_id=7018,rev_id=00,subsys_ven_id=10EE,subsys_id=0007,class_code=058000,cardbus_cis_ptr=00000000,cap_ver=2,c_pcie_cap_slot_implemented=FALSE,mps=010,cmps=2,ext_tag_fld_sup=TRUE,c_dev_control_ext_tag_default=FALSE,phantm_func_sup=00,c_phantom_functions=0,ep_l0s_accpt_lat=000,c_ep_l0s_accpt_lat=0,ep_l1_accpt_lat=111,c_ep_l1_accpt_lat=7,c_cpl_timeout_disable_sup=FALSE,c_cpl_timeout_range=0010,c_cpl_timeout_ranges_sup=2,c_buf_opt_bma=FALSE,c_perf_level_high=TRUE,c_tx_last_tlp=29,c_rx_ram_limit=7FF,c_fc_ph=4,c_fc_pd=64,c_fc_nph=4,c_fc_npd=8,c_fc_cplh=72,c_fc_cpld=850,c_cpl_inf=TRUE,c_cpl_infinite=TRUE,c_dll_lnk_actv_cap=FALSE,c_trgt_lnk_spd=0,c_hw_auton_spd_disable=FALSE,c_de_emph=FALSE,slot_clk=TRUE,c_rcb=0,c_root_cap_crs=FALSE,c_slot_cap_attn_butn=FALSE,c_slot_cap_attn_ind=FALSE,c_slot_cap_pwr_ctrl=FALSE,c_slot_cap_pwr_ind=FALSE,c_slot_cap_hotplug_surprise=FALSE,c_slot_cap_hotplug_cap=FALSE,c_slot_cap_mrl=FALSE,c_slot_cap_elec_interlock=FALSE,c_slot_cap_no_cmd_comp_sup=FALSE,c_slot_cap_pwr_limit_value=0,c_slot_cap_pwr_limit_scale=0,c_slot_cap_physical_slot_num=0,intx=FALSE,int_pin=0,c_msi_cap_on=TRUE,c_pm_cap_next_ptr=48,c_msi_64b_addr=TRUE,c_msi=0,c_msi_mult_msg_extn=0,c_msi_per_vctr_mask_cap=FALSE,c_msix_cap_on=FALSE,c_msix_next_ptr=00,c_pcie_cap_next_ptr=00,c_msix_table_size=000,c_msix_table_offset=0,c_msix_table_bir=0,c_msix_pba_offset=0,c_msix_pba_bir=0,dsi=0,c_dsi_bool=FALSE,d1_sup=0,c_d1_support=FALSE,d2_sup=0,c_d2_support=FALSE,pme_sup=0F,c_pme_support=0F,no_soft_rst=TRUE,pwr_con_d0_state=00,con_scl_fctr_d0_state=0,pwr_con_d1_state=00,con_scl_fctr_d1_state=0,pwr_con_d2_state=00,con_scl_fctr_d2_state=0,pwr_con_d3_state=00,con_scl_fctr_d3_state=0,pwr_dis_d0_state=00,dis_scl_fctr_d0_state=0,pwr_dis_d1_state=00,dis_scl_fctr_d1_state=0,pwr_dis_d2_state=00,dis_scl_fctr_d2_state=0,pwr_dis_d3_state=00,dis_scl_fctr_d3_state=0,c_dsn_cap_enabled=TRUE,c_dsn_base_ptr=100,c_vc_cap_enabled=FALSE,c_vc_base_ptr=000,c_vc_cap_reject_snoop=FALSE,c_vsec_cap_enabled=FALSE,c_vsec_base_ptr=000,c_vsec_next_ptr=000,c_dsn_next_ptr=000,c_vc_next_ptr=000,c_pci_cfg_space_addr=3F,c_ext_pci_cfg_space_addr=3FF,c_last_cfg_dw=10C,c_enable_msg_route=00000000000,bram_lat=0,c_rx_raddr_lat=0,c_rx_rdata_lat=2,c_rx_write_lat=0,c_tx_raddr_lat=0,c_tx_rdata_lat=2,c_tx_write_lat=0,c_ll_ack_timeout_enable=FALSE,c_ll_ack_timeout_function=0,c_ll_ack_timeout=0000,c_ll_replay_timeout_enable=FALSE,c_ll_replay_timeout_func=1,c_ll_replay_timeout=0000,c_dis_lane_reverse=TRUE,c_upconfig_capable=TRUE,c_disable_scrambling=FALSE,c_disable_tx_aspm_l0s=FALSE,c_pcie_dbg_ports=TRUE,pci_exp_ref_freq=0,c_xlnx_ref_board=VC707,c_pcie_blk_locn=3,c_ur_atomic=FALSE,c_dev_cap2_atomicop32_completer_supported=FALSE,c_dev_cap2_atomicop64_completer_supported=FALSE,c_dev_cap2_cas128_completer_supported=FALSE,c_dev_cap2_tph_completer_supported=00,c_dev_cap2_ari_forwarding_supported=FALSE,c_dev_cap2_atomicop_routing_supported=FALSE,c_link_cap_aspm_optionality=FALSE,c_aer_cap_on=FALSE,c_aer_base_ptr=000,c_aer_cap_nextptr=000,c_aer_cap_ecrc_check_capable=FALSE,c_aer_cap_ecrc_gen_capable=FALSE,c_aer_cap_multiheader=FALSE,c_aer_cap_permit_rooterr_update=FALSE,c_rbar_cap_on=FALSE,c_rbar_base_ptr=000,c_rbar_cap_nextptr=000,c_rbar_num=0,c_rbar_cap_sup0=00001,c_rbar_cap_index0=0,c_rbar_cap_control_encodedbar0=00,c_rbar_cap_sup1=00001,c_rbar_cap_index1=0,c_rbar_cap_control_encodedbar1=00,c_rbar_cap_sup2=00001,c_rbar_cap_index2=0,c_rbar_cap_control_encodedbar2=00,c_rbar_cap_sup3=00001,c_rbar_cap_index3=0,c_rbar_cap_control_encodedbar3=00,c_rbar_cap_sup4=00001,c_rbar_cap_index4=0,c_rbar_cap_control_encodedbar4=00,c_rbar_cap_sup5=00001,c_rbar_cap_index5=0,c_rbar_cap_control_encodedbar5=00,c_recrc_check=0,c_recrc_check_trim=FALSE,c_disable_rx_poisoned_resp=FALSE,c_trn_np_fc=TRUE,c_ur_inv_req=TRUE,c_ur_prs_response=TRUE,c_silicon_rev=2,c_aer_cap_optional_err_support=000000,LINK_CAP_MAX_LINK_WIDTH=8,C_DATA_WIDTH=64,PIPE_SIM=FALSE,PCIE_EXT_CLK=FALSE,PCIE_EXT_GT_COMMON=FALSE,EXT_CH_GT_DRP=FALSE,TRANSCEIVER_CTRL_STATUS_PORTS=FALSE,SHARED_LOGIC_IN_CORE=FALSE,ERR_REPORTING_IF=FALSE,PL_INTERFACE=FALSE,CFG_MGMT_IF=FALSE,CFG_CTL_IF=TRUE,CFG_STATUS_IF=TRUE,RCV_MSG_IF=FALSE,CFG_FC_IF=TRUE,EXT_PIPE_INTERFACE=FALSE,EXT_STARTUP_PRIMITIVE=FALSE,KEEP_WIDTH=8,PCIE_ASYNC_EN=FALSE}" *) (* downgradeipidentifiedwarnings = "yes" *) 
(* x_core_info = "PCIeGen1x8If64_pcie2_top,Vivado 2015.2" *) 
(* NotValidForBitStream *)
module PCIeGen1x8If64
   (pci_exp_txp,
    pci_exp_txn,
    pci_exp_rxp,
    pci_exp_rxn,
    user_clk_out,
    user_reset_out,
    user_lnk_up,
    user_app_rdy,
    tx_buf_av,
    tx_cfg_req,
    tx_err_drop,
    s_axis_tx_tready,
    s_axis_tx_tdata,
    s_axis_tx_tkeep,
    s_axis_tx_tlast,
    s_axis_tx_tvalid,
    s_axis_tx_tuser,
    tx_cfg_gnt,
    m_axis_rx_tdata,
    m_axis_rx_tkeep,
    m_axis_rx_tlast,
    m_axis_rx_tvalid,
    m_axis_rx_tready,
    m_axis_rx_tuser,
    rx_np_ok,
    rx_np_req,
    fc_cpld,
    fc_cplh,
    fc_npd,
    fc_nph,
    fc_pd,
    fc_ph,
    fc_sel,
    cfg_status,
    cfg_command,
    cfg_dstatus,
    cfg_dcommand,
    cfg_lstatus,
    cfg_lcommand,
    cfg_dcommand2,
    cfg_pcie_link_state,
    cfg_pmcsr_pme_en,
    cfg_pmcsr_powerstate,
    cfg_pmcsr_pme_status,
    cfg_received_func_lvl_rst,
    cfg_trn_pending,
    cfg_pm_halt_aspm_l0s,
    cfg_pm_halt_aspm_l1,
    cfg_pm_force_state_en,
    cfg_pm_force_state,
    cfg_dsn,
    cfg_interrupt,
    cfg_interrupt_rdy,
    cfg_interrupt_assert,
    cfg_interrupt_di,
    cfg_interrupt_do,
    cfg_interrupt_mmenable,
    cfg_interrupt_msienable,
    cfg_interrupt_msixenable,
    cfg_interrupt_msixfm,
    cfg_interrupt_stat,
    cfg_pciecap_interrupt_msgnum,
    cfg_to_turnoff,
    cfg_turnoff_ok,
    cfg_bus_number,
    cfg_device_number,
    cfg_function_number,
    cfg_pm_wake,
    cfg_pm_send_pme_to,
    cfg_ds_bus_number,
    cfg_ds_device_number,
    cfg_ds_function_number,
    cfg_bridge_serr_en,
    cfg_slot_control_electromech_il_ctl_pulse,
    cfg_root_control_syserr_corr_err_en,
    cfg_root_control_syserr_non_fatal_err_en,
    cfg_root_control_syserr_fatal_err_en,
    cfg_root_control_pme_int_en,
    cfg_aer_rooterr_corr_err_reporting_en,
    cfg_aer_rooterr_non_fatal_err_reporting_en,
    cfg_aer_rooterr_fatal_err_reporting_en,
    cfg_aer_rooterr_corr_err_received,
    cfg_aer_rooterr_non_fatal_err_received,
    cfg_aer_rooterr_fatal_err_received,
    cfg_vc_tcvc_map,
    sys_clk,
    sys_rst_n,
    pcie_drp_clk,
    pcie_drp_en,
    pcie_drp_we,
    pcie_drp_addr,
    pcie_drp_di,
    pcie_drp_do,
    pcie_drp_rdy);
  (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txp" *) output [7:0]pci_exp_txp;
  (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txn" *) output [7:0]pci_exp_txn;
  (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxp" *) input [7:0]pci_exp_rxp;
  (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxn" *) input [7:0]pci_exp_rxn;
  (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.user_clk_out CLK" *) output user_clk_out;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.user_reset_out RST" *) output user_reset_out;
  output user_lnk_up;
  output user_app_rdy;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_buf_av" *) output [5:0]tx_buf_av;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_cfg_req" *) output tx_cfg_req;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_err_drop" *) output tx_err_drop;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 s_axis_tx TREADY" *) output s_axis_tx_tready;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 s_axis_tx TDATA" *) input [63:0]s_axis_tx_tdata;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 s_axis_tx TKEEP" *) input [7:0]s_axis_tx_tkeep;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 s_axis_tx TLAST" *) input s_axis_tx_tlast;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 s_axis_tx TVALID" *) input s_axis_tx_tvalid;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 s_axis_tx TUSER" *) input [3:0]s_axis_tx_tuser;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control tx_cfg_gnt" *) input tx_cfg_gnt;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 m_axis_rx TDATA" *) output [63:0]m_axis_rx_tdata;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 m_axis_rx TKEEP" *) output [7:0]m_axis_rx_tkeep;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 m_axis_rx TLAST" *) output m_axis_rx_tlast;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 m_axis_rx TVALID" *) output m_axis_rx_tvalid;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 m_axis_rx TREADY" *) input m_axis_rx_tready;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 m_axis_rx TUSER" *) output [21:0]m_axis_rx_tuser;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_ok" *) input rx_np_ok;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_req" *) input rx_np_req;
  (* x_interface_info = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLD" *) output [11:0]fc_cpld;
  (* x_interface_info = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLH" *) output [7:0]fc_cplh;
  (* x_interface_info = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPD" *) output [11:0]fc_npd;
  (* x_interface_info = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPH" *) output [7:0]fc_nph;
  (* x_interface_info = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PD" *) output [11:0]fc_pd;
  (* x_interface_info = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PH" *) output [7:0]fc_ph;
  (* x_interface_info = "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc SEL" *) input [2:0]fc_sel;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status status" *) output [15:0]cfg_status;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status command" *) output [15:0]cfg_command;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dstatus" *) output [15:0]cfg_dstatus;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand" *) output [15:0]cfg_dcommand;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lstatus" *) output [15:0]cfg_lstatus;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lcommand" *) output [15:0]cfg_lcommand;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand2" *) output [15:0]cfg_dcommand2;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pcie_link_state" *) output [2:0]cfg_pcie_link_state;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_en" *) output cfg_pmcsr_pme_en;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_powerstate" *) output [1:0]cfg_pmcsr_powerstate;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_status" *) output cfg_pmcsr_pme_status;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status received_func_lvl_rst" *) output cfg_received_func_lvl_rst;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control trn_pending" *) input cfg_trn_pending;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l0s" *) input cfg_pm_halt_aspm_l0s;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l1" *) input cfg_pm_halt_aspm_l1;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state_en" *) input cfg_pm_force_state_en;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state" *) input [1:0]cfg_pm_force_state;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control dsn" *) input [63:0]cfg_dsn;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt interrupt" *) input cfg_interrupt;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt rdy" *) output cfg_interrupt_rdy;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt assert" *) input cfg_interrupt_assert;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt write_data" *) input [7:0]cfg_interrupt_di;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt read_data" *) output [7:0]cfg_interrupt_do;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt mmenable" *) output [2:0]cfg_interrupt_mmenable;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msienable" *) output cfg_interrupt_msienable;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixenable" *) output cfg_interrupt_msixenable;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixfm" *) output cfg_interrupt_msixfm;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt stat" *) input cfg_interrupt_stat;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt pciecap_interrupt_msgnum" *) input [4:0]cfg_pciecap_interrupt_msgnum;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status turnoff" *) output cfg_to_turnoff;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control turnoff_ok" *) input cfg_turnoff_ok;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bus_number" *) output [7:0]cfg_bus_number;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status device_number" *) output [4:0]cfg_device_number;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status function_number" *) output [2:0]cfg_function_number;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_wake" *) input cfg_pm_wake;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_send_pme_to" *) input cfg_pm_send_pme_to;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_bus_number" *) input [7:0]cfg_ds_bus_number;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_device_number" *) input [4:0]cfg_ds_device_number;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_function_number" *) input [2:0]cfg_ds_function_number;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bridge_serr_en" *) output cfg_bridge_serr_en;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status slot_control_electromech_il_ctl_pulse" *) output cfg_slot_control_electromech_il_ctl_pulse;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_corr_err_en" *) output cfg_root_control_syserr_corr_err_en;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_non_fatal_err_en" *) output cfg_root_control_syserr_non_fatal_err_en;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_fatal_err_en" *) output cfg_root_control_syserr_fatal_err_en;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_pme_int_en" *) output cfg_root_control_pme_int_en;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_reporting_en" *) output cfg_aer_rooterr_corr_err_reporting_en;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_reporting_en" *) output cfg_aer_rooterr_non_fatal_err_reporting_en;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_reporting_en" *) output cfg_aer_rooterr_fatal_err_reporting_en;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_received" *) output cfg_aer_rooterr_corr_err_received;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_received" *) output cfg_aer_rooterr_non_fatal_err_received;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_received" *) output cfg_aer_rooterr_fatal_err_received;
  (* x_interface_info = "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status vc_tcvc_map" *) output [6:0]cfg_vc_tcvc_map;
  (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.sys_clk CLK" *) input sys_clk;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST" *) input sys_rst_n;
  input pcie_drp_clk;
  (* x_interface_info = "xilinx.com:interface:drp:1.0 drp DEN" *) input pcie_drp_en;
  (* x_interface_info = "xilinx.com:interface:drp:1.0 drp DWE" *) input pcie_drp_we;
  (* x_interface_info = "xilinx.com:interface:drp:1.0 drp DADDR" *) input [8:0]pcie_drp_addr;
  (* x_interface_info = "xilinx.com:interface:drp:1.0 drp DI" *) input [15:0]pcie_drp_di;
  (* x_interface_info = "xilinx.com:interface:drp:1.0 drp DO" *) output [15:0]pcie_drp_do;
  (* x_interface_info = "xilinx.com:interface:drp:1.0 drp DRDY" *) output pcie_drp_rdy;

  wire cfg_aer_rooterr_corr_err_received;
  wire cfg_aer_rooterr_corr_err_reporting_en;
  wire cfg_aer_rooterr_fatal_err_received;
  wire cfg_aer_rooterr_fatal_err_reporting_en;
  wire cfg_aer_rooterr_non_fatal_err_received;
  wire cfg_aer_rooterr_non_fatal_err_reporting_en;
  wire cfg_bridge_serr_en;
  wire [7:0]cfg_bus_number;
  wire [15:0]cfg_command;
  wire [15:0]cfg_dcommand;
  wire [15:0]cfg_dcommand2;
  wire [4:0]cfg_device_number;
  wire [7:0]cfg_ds_bus_number;
  wire [4:0]cfg_ds_device_number;
  wire [2:0]cfg_ds_function_number;
  wire [63:0]cfg_dsn;
  wire [15:0]cfg_dstatus;
  wire [2:0]cfg_function_number;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire [7:0]cfg_interrupt_di;
  wire [7:0]cfg_interrupt_do;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_msixenable;
  wire cfg_interrupt_msixfm;
  wire cfg_interrupt_rdy;
  wire cfg_interrupt_stat;
  wire [15:0]cfg_lcommand;
  wire [15:0]cfg_lstatus;
  wire [2:0]cfg_pcie_link_state;
  wire [4:0]cfg_pciecap_interrupt_msgnum;
  wire [1:0]cfg_pm_force_state;
  wire cfg_pm_force_state_en;
  wire cfg_pm_halt_aspm_l0s;
  wire cfg_pm_halt_aspm_l1;
  wire cfg_pm_send_pme_to;
  wire cfg_pm_wake;
  wire cfg_pmcsr_pme_en;
  wire cfg_pmcsr_pme_status;
  wire [1:0]cfg_pmcsr_powerstate;
  wire cfg_received_func_lvl_rst;
  wire cfg_root_control_pme_int_en;
  wire cfg_root_control_syserr_corr_err_en;
  wire cfg_root_control_syserr_fatal_err_en;
  wire cfg_root_control_syserr_non_fatal_err_en;
  wire cfg_slot_control_electromech_il_ctl_pulse;
  wire [15:0]cfg_status;
  wire cfg_to_turnoff;
  wire cfg_trn_pending;
  wire cfg_turnoff_ok;
  wire [6:0]cfg_vc_tcvc_map;
  wire [11:0]fc_cpld;
  wire [7:0]fc_cplh;
  wire [11:0]fc_npd;
  wire [7:0]fc_nph;
  wire [11:0]fc_pd;
  wire [7:0]fc_ph;
  wire [2:0]fc_sel;
  wire [63:0]m_axis_rx_tdata;
  wire [7:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [21:0]m_axis_rx_tuser;
  wire m_axis_rx_tvalid;
  wire [7:0]pci_exp_rxn;
  wire [7:0]pci_exp_rxp;
  wire [7:0]pci_exp_txn;
  wire [7:0]pci_exp_txp;
  wire [8:0]pcie_drp_addr;
  wire pcie_drp_clk;
  wire [15:0]pcie_drp_di;
  wire [15:0]pcie_drp_do;
  wire pcie_drp_en;
  wire pcie_drp_rdy;
  wire pcie_drp_we;
  wire rx_np_ok;
  wire rx_np_req;
  wire [63:0]s_axis_tx_tdata;
  wire [7:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tready;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire sys_clk;
  wire sys_rst_n;
  wire [5:0]tx_buf_av;
  wire tx_cfg_gnt;
  wire tx_cfg_req;
  wire tx_err_drop;
  wire user_app_rdy;
  wire user_clk_out;
  wire user_lnk_up;
  wire user_reset_out;
  wire NLW_U0_cfg_aer_ecrc_check_en_UNCONNECTED;
  wire NLW_U0_cfg_aer_ecrc_gen_en_UNCONNECTED;
  wire NLW_U0_cfg_err_aer_headerlog_set_UNCONNECTED;
  wire NLW_U0_cfg_err_cpl_rdy_UNCONNECTED;
  wire NLW_U0_cfg_mgmt_rd_wr_done_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_assert_int_a_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_assert_int_b_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_assert_int_c_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_assert_int_d_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_deassert_int_a_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_deassert_int_b_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_deassert_int_c_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_deassert_int_d_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_err_cor_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_err_fatal_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_err_non_fatal_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_pm_as_nak_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_pm_pme_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_pme_to_ack_UNCONNECTED;
  wire NLW_U0_cfg_msg_received_setslotpowerlimit_UNCONNECTED;
  wire NLW_U0_ext_ch_gt_drpclk_UNCONNECTED;
  wire NLW_U0_int_dclk_out_UNCONNECTED;
  wire NLW_U0_int_mmcm_lock_out_UNCONNECTED;
  wire NLW_U0_int_oobclk_out_UNCONNECTED;
  wire NLW_U0_int_pclk_out_slave_UNCONNECTED;
  wire NLW_U0_int_pipe_rxusrclk_out_UNCONNECTED;
  wire NLW_U0_int_userclk1_out_UNCONNECTED;
  wire NLW_U0_int_userclk2_out_UNCONNECTED;
  wire NLW_U0_pipe_gen3_out_UNCONNECTED;
  wire NLW_U0_pipe_qrst_idle_UNCONNECTED;
  wire NLW_U0_pipe_rate_idle_UNCONNECTED;
  wire NLW_U0_pipe_rst_idle_UNCONNECTED;
  wire NLW_U0_pipe_txoutclk_out_UNCONNECTED;
  wire NLW_U0_pl_directed_change_done_UNCONNECTED;
  wire NLW_U0_pl_link_gen2_cap_UNCONNECTED;
  wire NLW_U0_pl_link_partner_gen2_supported_UNCONNECTED;
  wire NLW_U0_pl_link_upcfg_cap_UNCONNECTED;
  wire NLW_U0_pl_phy_lnk_up_UNCONNECTED;
  wire NLW_U0_pl_received_hot_rst_UNCONNECTED;
  wire NLW_U0_pl_sel_lnk_rate_UNCONNECTED;
  wire NLW_U0_qpll_drp_clk_UNCONNECTED;
  wire NLW_U0_qpll_drp_gen3_UNCONNECTED;
  wire NLW_U0_qpll_drp_ovrd_UNCONNECTED;
  wire NLW_U0_qpll_drp_rst_n_UNCONNECTED;
  wire NLW_U0_qpll_drp_start_UNCONNECTED;
  wire NLW_U0_qpll_qplld_UNCONNECTED;
  wire NLW_U0_startup_cfgclk_UNCONNECTED;
  wire NLW_U0_startup_cfgmclk_UNCONNECTED;
  wire NLW_U0_startup_eos_UNCONNECTED;
  wire NLW_U0_startup_preq_UNCONNECTED;
  wire [31:0]NLW_U0_cfg_mgmt_do_UNCONNECTED;
  wire [15:0]NLW_U0_cfg_msg_data_UNCONNECTED;
  wire [11:0]NLW_U0_common_commands_out_UNCONNECTED;
  wire [127:0]NLW_U0_ext_ch_gt_drpdo_UNCONNECTED;
  wire [7:0]NLW_U0_ext_ch_gt_drprdy_UNCONNECTED;
  wire [7:0]NLW_U0_gt_ch_drp_rdy_UNCONNECTED;
  wire [31:0]NLW_U0_icap_o_UNCONNECTED;
  wire [1:0]NLW_U0_int_qplllock_out_UNCONNECTED;
  wire [1:0]NLW_U0_int_qplloutclk_out_UNCONNECTED;
  wire [1:0]NLW_U0_int_qplloutrefclk_out_UNCONNECTED;
  wire [7:0]NLW_U0_int_rxoutclk_out_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_cpll_lock_UNCONNECTED;
  wire [31:0]NLW_U0_pipe_debug_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_debug_0_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_debug_1_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_debug_2_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_debug_3_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_debug_4_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_debug_5_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_debug_6_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_debug_7_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_debug_8_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_debug_9_UNCONNECTED;
  wire [119:0]NLW_U0_pipe_dmonitorout_UNCONNECTED;
  wire [55:0]NLW_U0_pipe_drp_fsm_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_eyescandataerror_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_pclk_sel_out_UNCONNECTED;
  wire [1:0]NLW_U0_pipe_qpll_lock_UNCONNECTED;
  wire [11:0]NLW_U0_pipe_qrst_fsm_UNCONNECTED;
  wire [39:0]NLW_U0_pipe_rate_fsm_UNCONNECTED;
  wire [4:0]NLW_U0_pipe_rst_fsm_UNCONNECTED;
  wire [23:0]NLW_U0_pipe_rxbufstatus_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_rxcommadet_UNCONNECTED;
  wire [63:0]NLW_U0_pipe_rxdisperr_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_rxdlysresetdone_UNCONNECTED;
  wire [63:0]NLW_U0_pipe_rxnotintable_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_rxoutclk_out_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_rxphaligndone_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_rxpmaresetdone_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_rxprbserr_UNCONNECTED;
  wire [23:0]NLW_U0_pipe_rxstatus_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_rxsyncdone_UNCONNECTED;
  wire [55:0]NLW_U0_pipe_sync_fsm_rx_UNCONNECTED;
  wire [47:0]NLW_U0_pipe_sync_fsm_tx_UNCONNECTED;
  wire [22:0]NLW_U0_pipe_tx_0_sigs_UNCONNECTED;
  wire [22:0]NLW_U0_pipe_tx_1_sigs_UNCONNECTED;
  wire [22:0]NLW_U0_pipe_tx_2_sigs_UNCONNECTED;
  wire [22:0]NLW_U0_pipe_tx_3_sigs_UNCONNECTED;
  wire [22:0]NLW_U0_pipe_tx_4_sigs_UNCONNECTED;
  wire [22:0]NLW_U0_pipe_tx_5_sigs_UNCONNECTED;
  wire [22:0]NLW_U0_pipe_tx_6_sigs_UNCONNECTED;
  wire [22:0]NLW_U0_pipe_tx_7_sigs_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_txdlysresetdone_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_txphaligndone_UNCONNECTED;
  wire [7:0]NLW_U0_pipe_txphinitdone_UNCONNECTED;
  wire [2:0]NLW_U0_pl_initial_link_width_UNCONNECTED;
  wire [1:0]NLW_U0_pl_lane_reversal_mode_UNCONNECTED;
  wire [5:0]NLW_U0_pl_ltssm_state_UNCONNECTED;
  wire [1:0]NLW_U0_pl_rx_pm_state_UNCONNECTED;
  wire [1:0]NLW_U0_pl_sel_lnk_width_UNCONNECTED;
  wire [2:0]NLW_U0_pl_tx_pm_state_UNCONNECTED;
  wire [1:0]NLW_U0_qpll_qpllreset_UNCONNECTED;

  (* CFG_CTL_IF = "TRUE" *) 
  (* CFG_FC_IF = "TRUE" *) 
  (* CFG_MGMT_IF = "FALSE" *) 
  (* CFG_STATUS_IF = "TRUE" *) 
  (* CLASS_CODE = "058000" *) 
  (* C_DATA_WIDTH = "64" *) 
  (* ERR_REPORTING_IF = "FALSE" *) 
  (* EXT_CH_GT_DRP = "FALSE" *) 
  (* EXT_PIPE_INTERFACE = "FALSE" *) 
  (* EXT_STARTUP_PRIMITIVE = "FALSE" *) 
  (* KEEP_WIDTH = "8" *) 
  (* LINK_CAP_MAX_LINK_WIDTH = "8" *) 
  (* PCIE_ASYNC_EN = "FALSE" *) 
  (* PCIE_EXT_CLK = "FALSE" *) 
  (* PCIE_EXT_GT_COMMON = "FALSE" *) 
  (* PIPE_SIM = "FALSE" *) 
  (* PL_INTERFACE = "FALSE" *) 
  (* RCV_MSG_IF = "FALSE" *) 
  (* SHARED_LOGIC_IN_CORE = "FALSE" *) 
  (* TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE" *) 
  (* bar_0 = "FFFFFC00" *) 
  (* bar_1 = "00000000" *) 
  (* bar_2 = "00000000" *) 
  (* bar_3 = "00000000" *) 
  (* bar_4 = "00000000" *) 
  (* bar_5 = "00000000" *) 
  (* bram_lat = "0" *) 
  (* c_aer_base_ptr = "000" *) 
  (* c_aer_cap_ecrc_check_capable = "FALSE" *) 
  (* c_aer_cap_ecrc_gen_capable = "FALSE" *) 
  (* c_aer_cap_multiheader = "FALSE" *) 
  (* c_aer_cap_nextptr = "000" *) 
  (* c_aer_cap_on = "FALSE" *) 
  (* c_aer_cap_optional_err_support = "000000" *) 
  (* c_aer_cap_permit_rooterr_update = "FALSE" *) 
  (* c_buf_opt_bma = "FALSE" *) 
  (* c_component_name = "PCIeGen1x8If64" *) 
  (* c_cpl_inf = "TRUE" *) 
  (* c_cpl_infinite = "TRUE" *) 
  (* c_cpl_timeout_disable_sup = "FALSE" *) 
  (* c_cpl_timeout_range = "0010" *) 
  (* c_cpl_timeout_ranges_sup = "2" *) 
  (* c_d1_support = "FALSE" *) 
  (* c_d2_support = "FALSE" *) 
  (* c_de_emph = "FALSE" *) 
  (* c_dev_cap2_ari_forwarding_supported = "FALSE" *) 
  (* c_dev_cap2_atomicop32_completer_supported = "FALSE" *) 
  (* c_dev_cap2_atomicop64_completer_supported = "FALSE" *) 
  (* c_dev_cap2_atomicop_routing_supported = "FALSE" *) 
  (* c_dev_cap2_cas128_completer_supported = "FALSE" *) 
  (* c_dev_cap2_tph_completer_supported = "00" *) 
  (* c_dev_control_ext_tag_default = "FALSE" *) 
  (* c_dev_port_type = "0" *) 
  (* c_dis_lane_reverse = "TRUE" *) 
  (* c_disable_rx_poisoned_resp = "FALSE" *) 
  (* c_disable_scrambling = "FALSE" *) 
  (* c_disable_tx_aspm_l0s = "FALSE" *) 
  (* c_dll_lnk_actv_cap = "FALSE" *) 
  (* c_dsi_bool = "FALSE" *) 
  (* c_dsn_base_ptr = "100" *) 
  (* c_dsn_cap_enabled = "TRUE" *) 
  (* c_dsn_next_ptr = "000" *) 
  (* c_enable_msg_route = "00000000000" *) 
  (* c_ep_l0s_accpt_lat = "0" *) 
  (* c_ep_l1_accpt_lat = "7" *) 
  (* c_ext_pci_cfg_space_addr = "3FF" *) 
  (* c_external_clocking = "TRUE" *) 
  (* c_fc_cpld = "850" *) 
  (* c_fc_cplh = "72" *) 
  (* c_fc_npd = "8" *) 
  (* c_fc_nph = "4" *) 
  (* c_fc_pd = "64" *) 
  (* c_fc_ph = "4" *) 
  (* c_gen1 = "FALSE" *) 
  (* c_header_type = "00" *) 
  (* c_hw_auton_spd_disable = "FALSE" *) 
  (* c_int_width = "64" *) 
  (* c_last_cfg_dw = "10C" *) 
  (* c_link_cap_aspm_optionality = "FALSE" *) 
  (* c_ll_ack_timeout = "0000" *) 
  (* c_ll_ack_timeout_enable = "FALSE" *) 
  (* c_ll_ack_timeout_function = "0" *) 
  (* c_ll_replay_timeout = "0000" *) 
  (* c_ll_replay_timeout_enable = "FALSE" *) 
  (* c_ll_replay_timeout_func = "1" *) 
  (* c_lnk_bndwdt_notif = "FALSE" *) 
  (* c_msi = "0" *) 
  (* c_msi_64b_addr = "TRUE" *) 
  (* c_msi_cap_on = "TRUE" *) 
  (* c_msi_mult_msg_extn = "0" *) 
  (* c_msi_per_vctr_mask_cap = "FALSE" *) 
  (* c_msix_cap_on = "FALSE" *) 
  (* c_msix_next_ptr = "00" *) 
  (* c_msix_pba_bir = "0" *) 
  (* c_msix_pba_offset = "0" *) 
  (* c_msix_table_bir = "0" *) 
  (* c_msix_table_offset = "0" *) 
  (* c_msix_table_size = "000" *) 
  (* c_pci_cfg_space_addr = "3F" *) 
  (* c_pcie_blk_locn = "3" *) 
  (* c_pcie_cap_next_ptr = "00" *) 
  (* c_pcie_cap_slot_implemented = "FALSE" *) 
  (* c_pcie_dbg_ports = "TRUE" *) 
  (* c_pcie_fast_config = "0" *) 
  (* c_perf_level_high = "TRUE" *) 
  (* c_phantom_functions = "0" *) 
  (* c_pm_cap_next_ptr = "48" *) 
  (* c_pme_support = "0F" *) 
  (* c_rbar_base_ptr = "000" *) 
  (* c_rbar_cap_control_encodedbar0 = "00" *) 
  (* c_rbar_cap_control_encodedbar1 = "00" *) 
  (* c_rbar_cap_control_encodedbar2 = "00" *) 
  (* c_rbar_cap_control_encodedbar3 = "00" *) 
  (* c_rbar_cap_control_encodedbar4 = "00" *) 
  (* c_rbar_cap_control_encodedbar5 = "00" *) 
  (* c_rbar_cap_index0 = "0" *) 
  (* c_rbar_cap_index1 = "0" *) 
  (* c_rbar_cap_index2 = "0" *) 
  (* c_rbar_cap_index3 = "0" *) 
  (* c_rbar_cap_index4 = "0" *) 
  (* c_rbar_cap_index5 = "0" *) 
  (* c_rbar_cap_nextptr = "000" *) 
  (* c_rbar_cap_on = "FALSE" *) 
  (* c_rbar_cap_sup0 = "00001" *) 
  (* c_rbar_cap_sup1 = "00001" *) 
  (* c_rbar_cap_sup2 = "00001" *) 
  (* c_rbar_cap_sup3 = "00001" *) 
  (* c_rbar_cap_sup4 = "00001" *) 
  (* c_rbar_cap_sup5 = "00001" *) 
  (* c_rbar_num = "0" *) 
  (* c_rcb = "0" *) 
  (* c_recrc_check = "0" *) 
  (* c_recrc_check_trim = "FALSE" *) 
  (* c_rev_gt_order = "FALSE" *) 
  (* c_root_cap_crs = "FALSE" *) 
  (* c_rx_raddr_lat = "0" *) 
  (* c_rx_ram_limit = "7FF" *) 
  (* c_rx_rdata_lat = "2" *) 
  (* c_rx_write_lat = "0" *) 
  (* c_silicon_rev = "2" *) 
  (* c_slot_cap_attn_butn = "FALSE" *) 
  (* c_slot_cap_attn_ind = "FALSE" *) 
  (* c_slot_cap_elec_interlock = "FALSE" *) 
  (* c_slot_cap_hotplug_cap = "FALSE" *) 
  (* c_slot_cap_hotplug_surprise = "FALSE" *) 
  (* c_slot_cap_mrl = "FALSE" *) 
  (* c_slot_cap_no_cmd_comp_sup = "FALSE" *) 
  (* c_slot_cap_physical_slot_num = "0" *) 
  (* c_slot_cap_pwr_ctrl = "FALSE" *) 
  (* c_slot_cap_pwr_ind = "FALSE" *) 
  (* c_slot_cap_pwr_limit_scale = "0" *) 
  (* c_slot_cap_pwr_limit_value = "0" *) 
  (* c_surprise_dn_err_cap = "FALSE" *) 
  (* c_trgt_lnk_spd = "0" *) 
  (* c_trn_np_fc = "TRUE" *) 
  (* c_tx_last_tlp = "29" *) 
  (* c_tx_raddr_lat = "0" *) 
  (* c_tx_rdata_lat = "2" *) 
  (* c_tx_write_lat = "0" *) 
  (* c_upconfig_capable = "TRUE" *) 
  (* c_upstream_facing = "TRUE" *) 
  (* c_ur_atomic = "FALSE" *) 
  (* c_ur_inv_req = "TRUE" *) 
  (* c_ur_prs_response = "TRUE" *) 
  (* c_vc_base_ptr = "000" *) 
  (* c_vc_cap_enabled = "FALSE" *) 
  (* c_vc_cap_reject_snoop = "FALSE" *) 
  (* c_vc_next_ptr = "000" *) 
  (* c_vsec_base_ptr = "000" *) 
  (* c_vsec_cap_enabled = "FALSE" *) 
  (* c_vsec_next_ptr = "000" *) 
  (* c_xlnx_ref_board = "VC707" *) 
  (* cap_ver = "2" *) 
  (* cardbus_cis_ptr = "00000000" *) 
  (* cmps = "2" *) 
  (* con_scl_fctr_d0_state = "0" *) 
  (* con_scl_fctr_d1_state = "0" *) 
  (* con_scl_fctr_d2_state = "0" *) 
  (* con_scl_fctr_d3_state = "0" *) 
  (* cost_table = "1" *) 
  (* d1_sup = "0" *) 
  (* d2_sup = "0" *) 
  (* dev_id = "7018" *) 
  (* dev_port_type = "0000" *) 
  (* dis_scl_fctr_d0_state = "0" *) 
  (* dis_scl_fctr_d1_state = "0" *) 
  (* dis_scl_fctr_d2_state = "0" *) 
  (* dis_scl_fctr_d3_state = "0" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  (* dsi = "0" *) 
  (* ep_l0s_accpt_lat = "000" *) 
  (* ep_l1_accpt_lat = "111" *) 
  (* ext_tag_fld_sup = "TRUE" *) 
  (* int_pin = "0" *) 
  (* intx = "FALSE" *) 
  (* max_lnk_spd = "1" *) 
  (* max_lnk_wdt = "001000" *) 
  (* mps = "010" *) 
  (* no_soft_rst = "TRUE" *) 
  (* pci_exp_int_freq = "3" *) 
  (* pci_exp_ref_freq = "0" *) 
  (* phantm_func_sup = "00" *) 
  (* pme_sup = "0F" *) 
  (* pwr_con_d0_state = "00" *) 
  (* pwr_con_d1_state = "00" *) 
  (* pwr_con_d2_state = "00" *) 
  (* pwr_con_d3_state = "00" *) 
  (* pwr_dis_d0_state = "00" *) 
  (* pwr_dis_d1_state = "00" *) 
  (* pwr_dis_d2_state = "00" *) 
  (* pwr_dis_d3_state = "00" *) 
  (* rev_id = "00" *) 
  (* slot_clk = "TRUE" *) 
  (* subsys_id = "0007" *) 
  (* subsys_ven_id = "10EE" *) 
  (* ven_id = "10EE" *) 
  (* xrom_bar = "00000000" *) 
  PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top U0
       (.cfg_aer_ecrc_check_en(NLW_U0_cfg_aer_ecrc_check_en_UNCONNECTED),
        .cfg_aer_ecrc_gen_en(NLW_U0_cfg_aer_ecrc_gen_en_UNCONNECTED),
        .cfg_aer_interrupt_msgnum({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received),
        .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en),
        .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received),
        .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en),
        .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received),
        .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en),
        .cfg_bridge_serr_en(cfg_bridge_serr_en),
        .cfg_bus_number(cfg_bus_number),
        .cfg_command(cfg_command),
        .cfg_dcommand(cfg_dcommand),
        .cfg_dcommand2(cfg_dcommand2),
        .cfg_device_number(cfg_device_number),
        .cfg_ds_bus_number(cfg_ds_bus_number),
        .cfg_ds_device_number(cfg_ds_device_number),
        .cfg_ds_function_number(cfg_ds_function_number),
        .cfg_dsn(cfg_dsn),
        .cfg_dstatus(cfg_dstatus),
        .cfg_err_acs(1'b0),
        .cfg_err_aer_headerlog({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_err_aer_headerlog_set(NLW_U0_cfg_err_aer_headerlog_set_UNCONNECTED),
        .cfg_err_atomic_egress_blocked(1'b0),
        .cfg_err_cor(1'b0),
        .cfg_err_cpl_abort(1'b0),
        .cfg_err_cpl_rdy(NLW_U0_cfg_err_cpl_rdy_UNCONNECTED),
        .cfg_err_cpl_timeout(1'b0),
        .cfg_err_cpl_unexpect(1'b0),
        .cfg_err_ecrc(1'b0),
        .cfg_err_internal_cor(1'b0),
        .cfg_err_internal_uncor(1'b0),
        .cfg_err_locked(1'b0),
        .cfg_err_malformed(1'b0),
        .cfg_err_mc_blocked(1'b0),
        .cfg_err_norecovery(1'b0),
        .cfg_err_poisoned(1'b0),
        .cfg_err_posted(1'b0),
        .cfg_err_tlp_cpl_header({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_err_ur(1'b0),
        .cfg_function_number(cfg_function_number),
        .cfg_interrupt(cfg_interrupt),
        .cfg_interrupt_assert(cfg_interrupt_assert),
        .cfg_interrupt_di(cfg_interrupt_di),
        .cfg_interrupt_do(cfg_interrupt_do),
        .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
        .cfg_interrupt_msienable(cfg_interrupt_msienable),
        .cfg_interrupt_msixenable(cfg_interrupt_msixenable),
        .cfg_interrupt_msixfm(cfg_interrupt_msixfm),
        .cfg_interrupt_rdy(cfg_interrupt_rdy),
        .cfg_interrupt_stat(cfg_interrupt_stat),
        .cfg_lcommand(cfg_lcommand),
        .cfg_lstatus(cfg_lstatus),
        .cfg_mgmt_byte_en({1'b0,1'b0,1'b0,1'b0}),
        .cfg_mgmt_di({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_mgmt_do(NLW_U0_cfg_mgmt_do_UNCONNECTED[31:0]),
        .cfg_mgmt_dwaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .cfg_mgmt_rd_en(1'b0),
        .cfg_mgmt_rd_wr_done(NLW_U0_cfg_mgmt_rd_wr_done_UNCONNECTED),
        .cfg_mgmt_wr_en(1'b0),
        .cfg_mgmt_wr_readonly(1'b0),
        .cfg_mgmt_wr_rw1c_as_rw(1'b0),
        .cfg_msg_data(NLW_U0_cfg_msg_data_UNCONNECTED[15:0]),
        .cfg_msg_received(NLW_U0_cfg_msg_received_UNCONNECTED),
        .cfg_msg_received_assert_int_a(NLW_U0_cfg_msg_received_assert_int_a_UNCONNECTED),
        .cfg_msg_received_assert_int_b(NLW_U0_cfg_msg_received_assert_int_b_UNCONNECTED),
        .cfg_msg_received_assert_int_c(NLW_U0_cfg_msg_received_assert_int_c_UNCONNECTED),
        .cfg_msg_received_assert_int_d(NLW_U0_cfg_msg_received_assert_int_d_UNCONNECTED),
        .cfg_msg_received_deassert_int_a(NLW_U0_cfg_msg_received_deassert_int_a_UNCONNECTED),
        .cfg_msg_received_deassert_int_b(NLW_U0_cfg_msg_received_deassert_int_b_UNCONNECTED),
        .cfg_msg_received_deassert_int_c(NLW_U0_cfg_msg_received_deassert_int_c_UNCONNECTED),
        .cfg_msg_received_deassert_int_d(NLW_U0_cfg_msg_received_deassert_int_d_UNCONNECTED),
        .cfg_msg_received_err_cor(NLW_U0_cfg_msg_received_err_cor_UNCONNECTED),
        .cfg_msg_received_err_fatal(NLW_U0_cfg_msg_received_err_fatal_UNCONNECTED),
        .cfg_msg_received_err_non_fatal(NLW_U0_cfg_msg_received_err_non_fatal_UNCONNECTED),
        .cfg_msg_received_pm_as_nak(NLW_U0_cfg_msg_received_pm_as_nak_UNCONNECTED),
        .cfg_msg_received_pm_pme(NLW_U0_cfg_msg_received_pm_pme_UNCONNECTED),
        .cfg_msg_received_pme_to_ack(NLW_U0_cfg_msg_received_pme_to_ack_UNCONNECTED),
        .cfg_msg_received_setslotpowerlimit(NLW_U0_cfg_msg_received_setslotpowerlimit_UNCONNECTED),
        .cfg_pcie_link_state(cfg_pcie_link_state),
        .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
        .cfg_pm_force_state(cfg_pm_force_state),
        .cfg_pm_force_state_en(cfg_pm_force_state_en),
        .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s),
        .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1),
        .cfg_pm_send_pme_to(cfg_pm_send_pme_to),
        .cfg_pm_wake(cfg_pm_wake),
        .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en),
        .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status),
        .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate),
        .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst),
        .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en),
        .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en),
        .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en),
        .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en),
        .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse),
        .cfg_status(cfg_status),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_trn_pending(cfg_trn_pending),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .cfg_vc_tcvc_map(cfg_vc_tcvc_map),
        .common_commands_in({1'b0,1'b0,1'b0,1'b0}),
        .common_commands_out(NLW_U0_common_commands_out_UNCONNECTED[11:0]),
        .ext_ch_gt_drpaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ext_ch_gt_drpclk(NLW_U0_ext_ch_gt_drpclk_UNCONNECTED),
        .ext_ch_gt_drpdi({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ext_ch_gt_drpdo(NLW_U0_ext_ch_gt_drpdo_UNCONNECTED[127:0]),
        .ext_ch_gt_drpen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ext_ch_gt_drprdy(NLW_U0_ext_ch_gt_drprdy_UNCONNECTED[7:0]),
        .ext_ch_gt_drpwe({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .fc_cpld(fc_cpld),
        .fc_cplh(fc_cplh),
        .fc_npd(fc_npd),
        .fc_nph(fc_nph),
        .fc_pd(fc_pd),
        .fc_ph(fc_ph),
        .fc_sel(fc_sel),
        .gt_ch_drp_rdy(NLW_U0_gt_ch_drp_rdy_UNCONNECTED[7:0]),
        .icap_clk(1'b0),
        .icap_csib(1'b0),
        .icap_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .icap_o(NLW_U0_icap_o_UNCONNECTED[31:0]),
        .icap_rdwrb(1'b0),
        .int_dclk_out(NLW_U0_int_dclk_out_UNCONNECTED),
        .int_mmcm_lock_out(NLW_U0_int_mmcm_lock_out_UNCONNECTED),
        .int_oobclk_out(NLW_U0_int_oobclk_out_UNCONNECTED),
        .int_pclk_out_slave(NLW_U0_int_pclk_out_slave_UNCONNECTED),
        .int_pclk_sel_slave({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .int_pipe_rxusrclk_out(NLW_U0_int_pipe_rxusrclk_out_UNCONNECTED),
        .int_qplllock_out(NLW_U0_int_qplllock_out_UNCONNECTED[1:0]),
        .int_qplloutclk_out(NLW_U0_int_qplloutclk_out_UNCONNECTED[1:0]),
        .int_qplloutrefclk_out(NLW_U0_int_qplloutrefclk_out_UNCONNECTED[1:0]),
        .int_rxoutclk_out(NLW_U0_int_rxoutclk_out_UNCONNECTED[7:0]),
        .int_userclk1_out(NLW_U0_int_userclk1_out_UNCONNECTED),
        .int_userclk2_out(NLW_U0_int_userclk2_out_UNCONNECTED),
        .m_axis_rx_tdata(m_axis_rx_tdata),
        .m_axis_rx_tkeep(m_axis_rx_tkeep),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser),
        .m_axis_rx_tvalid(m_axis_rx_tvalid),
        .pci_exp_rxn(pci_exp_rxn),
        .pci_exp_rxp(pci_exp_rxp),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .pcie_drp_addr(pcie_drp_addr),
        .pcie_drp_clk(pcie_drp_clk),
        .pcie_drp_di(pcie_drp_di),
        .pcie_drp_do(pcie_drp_do),
        .pcie_drp_en(pcie_drp_en),
        .pcie_drp_rdy(pcie_drp_rdy),
        .pcie_drp_we(pcie_drp_we),
        .pipe_cpll_lock(NLW_U0_pipe_cpll_lock_UNCONNECTED[7:0]),
        .pipe_dclk_in(1'b0),
        .pipe_debug(NLW_U0_pipe_debug_UNCONNECTED[31:0]),
        .pipe_debug_0(NLW_U0_pipe_debug_0_UNCONNECTED[7:0]),
        .pipe_debug_1(NLW_U0_pipe_debug_1_UNCONNECTED[7:0]),
        .pipe_debug_2(NLW_U0_pipe_debug_2_UNCONNECTED[7:0]),
        .pipe_debug_3(NLW_U0_pipe_debug_3_UNCONNECTED[7:0]),
        .pipe_debug_4(NLW_U0_pipe_debug_4_UNCONNECTED[7:0]),
        .pipe_debug_5(NLW_U0_pipe_debug_5_UNCONNECTED[7:0]),
        .pipe_debug_6(NLW_U0_pipe_debug_6_UNCONNECTED[7:0]),
        .pipe_debug_7(NLW_U0_pipe_debug_7_UNCONNECTED[7:0]),
        .pipe_debug_8(NLW_U0_pipe_debug_8_UNCONNECTED[7:0]),
        .pipe_debug_9(NLW_U0_pipe_debug_9_UNCONNECTED[7:0]),
        .pipe_dmonitorout(NLW_U0_pipe_dmonitorout_UNCONNECTED[119:0]),
        .pipe_drp_fsm(NLW_U0_pipe_drp_fsm_UNCONNECTED[55:0]),
        .pipe_eyescandataerror(NLW_U0_pipe_eyescandataerror_UNCONNECTED[7:0]),
        .pipe_gen3_out(NLW_U0_pipe_gen3_out_UNCONNECTED),
        .pipe_loopback({1'b0,1'b0,1'b0}),
        .pipe_mmcm_lock_in(1'b1),
        .pipe_mmcm_rst_n(1'b1),
        .pipe_oobclk_in(1'b0),
        .pipe_pclk_in(1'b0),
        .pipe_pclk_sel_out(NLW_U0_pipe_pclk_sel_out_UNCONNECTED[7:0]),
        .pipe_qpll_lock(NLW_U0_pipe_qpll_lock_UNCONNECTED[1:0]),
        .pipe_qrst_fsm(NLW_U0_pipe_qrst_fsm_UNCONNECTED[11:0]),
        .pipe_qrst_idle(NLW_U0_pipe_qrst_idle_UNCONNECTED),
        .pipe_rate_fsm(NLW_U0_pipe_rate_fsm_UNCONNECTED[39:0]),
        .pipe_rate_idle(NLW_U0_pipe_rate_idle_UNCONNECTED),
        .pipe_rst_fsm(NLW_U0_pipe_rst_fsm_UNCONNECTED[4:0]),
        .pipe_rst_idle(NLW_U0_pipe_rst_idle_UNCONNECTED),
        .pipe_rx_0_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_1_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_2_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_3_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_4_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_5_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_6_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rx_7_sigs({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rxbufstatus(NLW_U0_pipe_rxbufstatus_UNCONNECTED[23:0]),
        .pipe_rxcommadet(NLW_U0_pipe_rxcommadet_UNCONNECTED[7:0]),
        .pipe_rxdisperr(NLW_U0_pipe_rxdisperr_UNCONNECTED[63:0]),
        .pipe_rxdlysresetdone(NLW_U0_pipe_rxdlysresetdone_UNCONNECTED[7:0]),
        .pipe_rxnotintable(NLW_U0_pipe_rxnotintable_UNCONNECTED[63:0]),
        .pipe_rxoutclk_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_rxoutclk_out(NLW_U0_pipe_rxoutclk_out_UNCONNECTED[7:0]),
        .pipe_rxphaligndone(NLW_U0_pipe_rxphaligndone_UNCONNECTED[7:0]),
        .pipe_rxpmaresetdone(NLW_U0_pipe_rxpmaresetdone_UNCONNECTED[7:0]),
        .pipe_rxprbscntreset(1'b0),
        .pipe_rxprbserr(NLW_U0_pipe_rxprbserr_UNCONNECTED[7:0]),
        .pipe_rxprbssel({1'b0,1'b0,1'b0}),
        .pipe_rxstatus(NLW_U0_pipe_rxstatus_UNCONNECTED[23:0]),
        .pipe_rxsyncdone(NLW_U0_pipe_rxsyncdone_UNCONNECTED[7:0]),
        .pipe_rxusrclk_in(1'b0),
        .pipe_sync_fsm_rx(NLW_U0_pipe_sync_fsm_rx_UNCONNECTED[55:0]),
        .pipe_sync_fsm_tx(NLW_U0_pipe_sync_fsm_tx_UNCONNECTED[47:0]),
        .pipe_tx_0_sigs(NLW_U0_pipe_tx_0_sigs_UNCONNECTED[22:0]),
        .pipe_tx_1_sigs(NLW_U0_pipe_tx_1_sigs_UNCONNECTED[22:0]),
        .pipe_tx_2_sigs(NLW_U0_pipe_tx_2_sigs_UNCONNECTED[22:0]),
        .pipe_tx_3_sigs(NLW_U0_pipe_tx_3_sigs_UNCONNECTED[22:0]),
        .pipe_tx_4_sigs(NLW_U0_pipe_tx_4_sigs_UNCONNECTED[22:0]),
        .pipe_tx_5_sigs(NLW_U0_pipe_tx_5_sigs_UNCONNECTED[22:0]),
        .pipe_tx_6_sigs(NLW_U0_pipe_tx_6_sigs_UNCONNECTED[22:0]),
        .pipe_tx_7_sigs(NLW_U0_pipe_tx_7_sigs_UNCONNECTED[22:0]),
        .pipe_txdlysresetdone(NLW_U0_pipe_txdlysresetdone_UNCONNECTED[7:0]),
        .pipe_txinhibit({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .pipe_txoutclk_out(NLW_U0_pipe_txoutclk_out_UNCONNECTED),
        .pipe_txphaligndone(NLW_U0_pipe_txphaligndone_UNCONNECTED[7:0]),
        .pipe_txphinitdone(NLW_U0_pipe_txphinitdone_UNCONNECTED[7:0]),
        .pipe_txprbsforceerr(1'b0),
        .pipe_txprbssel({1'b0,1'b0,1'b0}),
        .pipe_userclk1_in(1'b1),
        .pipe_userclk2_in(1'b0),
        .pl_directed_change_done(NLW_U0_pl_directed_change_done_UNCONNECTED),
        .pl_directed_link_auton(1'b0),
        .pl_directed_link_change({1'b0,1'b0}),
        .pl_directed_link_speed(1'b0),
        .pl_directed_link_width({1'b0,1'b0}),
        .pl_downstream_deemph_source(1'b0),
        .pl_initial_link_width(NLW_U0_pl_initial_link_width_UNCONNECTED[2:0]),
        .pl_lane_reversal_mode(NLW_U0_pl_lane_reversal_mode_UNCONNECTED[1:0]),
        .pl_link_gen2_cap(NLW_U0_pl_link_gen2_cap_UNCONNECTED),
        .pl_link_partner_gen2_supported(NLW_U0_pl_link_partner_gen2_supported_UNCONNECTED),
        .pl_link_upcfg_cap(NLW_U0_pl_link_upcfg_cap_UNCONNECTED),
        .pl_ltssm_state(NLW_U0_pl_ltssm_state_UNCONNECTED[5:0]),
        .pl_phy_lnk_up(NLW_U0_pl_phy_lnk_up_UNCONNECTED),
        .pl_received_hot_rst(NLW_U0_pl_received_hot_rst_UNCONNECTED),
        .pl_rx_pm_state(NLW_U0_pl_rx_pm_state_UNCONNECTED[1:0]),
        .pl_sel_lnk_rate(NLW_U0_pl_sel_lnk_rate_UNCONNECTED),
        .pl_sel_lnk_width(NLW_U0_pl_sel_lnk_width_UNCONNECTED[1:0]),
        .pl_transmit_hot_rst(1'b0),
        .pl_tx_pm_state(NLW_U0_pl_tx_pm_state_UNCONNECTED[2:0]),
        .pl_upstream_prefer_deemph(1'b1),
        .qpll_drp_clk(NLW_U0_qpll_drp_clk_UNCONNECTED),
        .qpll_drp_crscode({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .qpll_drp_done({1'b0,1'b0}),
        .qpll_drp_fsm({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .qpll_drp_gen3(NLW_U0_qpll_drp_gen3_UNCONNECTED),
        .qpll_drp_ovrd(NLW_U0_qpll_drp_ovrd_UNCONNECTED),
        .qpll_drp_reset({1'b0,1'b0}),
        .qpll_drp_rst_n(NLW_U0_qpll_drp_rst_n_UNCONNECTED),
        .qpll_drp_start(NLW_U0_qpll_drp_start_UNCONNECTED),
        .qpll_qplld(NLW_U0_qpll_qplld_UNCONNECTED),
        .qpll_qplllock({1'b0,1'b0}),
        .qpll_qplloutclk({1'b0,1'b0}),
        .qpll_qplloutrefclk({1'b0,1'b0}),
        .qpll_qpllreset(NLW_U0_qpll_qpllreset_UNCONNECTED[1:0]),
        .rx_np_ok(rx_np_ok),
        .rx_np_req(rx_np_req),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tready(s_axis_tx_tready),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .startup_cfgclk(NLW_U0_startup_cfgclk_UNCONNECTED),
        .startup_cfgmclk(NLW_U0_startup_cfgmclk_UNCONNECTED),
        .startup_clk(1'b0),
        .startup_eos(NLW_U0_startup_eos_UNCONNECTED),
        .startup_eos_in(1'b0),
        .startup_gsr(1'b0),
        .startup_gts(1'b0),
        .startup_keyclearb(1'b1),
        .startup_pack(1'b0),
        .startup_preq(NLW_U0_startup_preq_UNCONNECTED),
        .startup_usrcclko(1'b1),
        .startup_usrcclkts(1'b0),
        .startup_usrdoneo(1'b0),
        .startup_usrdonets(1'b1),
        .sys_clk(sys_clk),
        .sys_rst_n(sys_rst_n),
        .tx_buf_av(tx_buf_av),
        .tx_cfg_gnt(tx_cfg_gnt),
        .tx_cfg_req(tx_cfg_req),
        .tx_err_drop(tx_err_drop),
        .user_app_rdy(user_app_rdy),
        .user_clk_out(user_clk_out),
        .user_lnk_up(user_lnk_up),
        .user_reset_out(user_reset_out));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_axi_basic_rx" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx
   (E,
    m_axis_rx_tvalid,
    m_axis_rx_tlast,
    trn_in_packet_reg,
    m_axis_rx_tuser,
    m_axis_rx_tdata,
    m_axis_rx_tkeep,
    user_reset_out_reg,
    trn_rsrc_dsc,
    user_clk,
    rsrc_rdy_filtered10_out,
    trn_rrem,
    trn_reof,
    trn_rsof,
    trn_recrc_err,
    trn_rerrfwd,
    user_reset_out_reg_0,
    m_axis_rx_tready,
    trn_rdst_rdy_xhdl4_reg,
    trn_rbar_hit,
    trn_rd);
  output [0:0]E;
  output m_axis_rx_tvalid;
  output m_axis_rx_tlast;
  output trn_in_packet_reg;
  output [21:0]m_axis_rx_tuser;
  output [63:0]m_axis_rx_tdata;
  output [7:0]m_axis_rx_tkeep;
  input user_reset_out_reg;
  input trn_rsrc_dsc;
  input user_clk;
  input rsrc_rdy_filtered10_out;
  input [0:0]trn_rrem;
  input trn_reof;
  input trn_rsof;
  input trn_recrc_err;
  input trn_rerrfwd;
  input user_reset_out_reg_0;
  input m_axis_rx_tready;
  input trn_rdst_rdy_xhdl4_reg;
  input [6:0]trn_rbar_hit;
  input [63:0]trn_rd;

  wire [0:0]E;
  wire [63:0]m_axis_rx_tdata;
  wire [7:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [21:0]m_axis_rx_tuser;
  wire m_axis_rx_tvalid;
  wire null_mux_sel;
  wire [9:5]payload_len;
  wire [4:0]plusOp;
  wire rsrc_rdy_filtered10_out;
  wire rx_null_gen_inst_n_0;
  wire rx_null_gen_inst_n_1;
  wire rx_null_gen_inst_n_2;
  wire rx_null_gen_inst_n_3;
  wire rx_null_gen_inst_n_4;
  wire rx_null_gen_inst_n_5;
  wire rx_null_gen_inst_n_6;
  wire rx_null_gen_inst_n_7;
  wire rx_null_gen_inst_n_8;
  wire rx_pipeline_inst_n_5;
  wire rx_pipeline_inst_n_6;
  wire rx_pipeline_inst_n_7;
  wire rx_pipeline_inst_n_8;
  wire rx_pipeline_inst_n_9;
  wire trn_in_packet_reg;
  wire [6:0]trn_rbar_hit;
  wire [63:0]trn_rd;
  wire trn_rdst_rdy_xhdl4_reg;
  wire trn_recrc_err;
  wire trn_reof;
  wire trn_rerrfwd;
  wire [0:0]trn_rrem;
  wire trn_rsof;
  wire trn_rsrc_dsc;
  wire user_clk;
  wire user_reset_out_reg;
  wire user_reset_out_reg_0;

  PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_null_gen rx_null_gen_inst
       (.D({rx_null_gen_inst_n_3,rx_null_gen_inst_n_4,rx_null_gen_inst_n_5,rx_null_gen_inst_n_6}),
        .data_prev_reg(rx_pipeline_inst_n_7),
        .data_prev_reg_0(rx_pipeline_inst_n_8),
        .in0(plusOp),
        .\m_axis_rx_tdata_xhdl0_reg[30] (payload_len),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser[21]),
        .\m_axis_rx_tuser_xhdl1_reg[19] (rx_null_gen_inst_n_8),
        .\m_axis_rx_tuser_xhdl1_reg[21] (rx_null_gen_inst_n_2),
        .m_axis_rx_tvalid_xhdl2_reg(m_axis_rx_tvalid),
        .null_mux_sel(null_mux_sel),
        .null_mux_sel_reg(rx_null_gen_inst_n_0),
        .null_mux_sel_reg_0(rx_pipeline_inst_n_6),
        .reg_tlast_reg(rx_null_gen_inst_n_7),
        .trn_rdst_rdy_xhdl4_reg(rx_null_gen_inst_n_1),
        .\trn_rrem_prev_reg[0] (rx_pipeline_inst_n_9),
        .user_clk(user_clk),
        .user_reset_out_reg(user_reset_out_reg),
        .user_reset_out_reg_0(rx_pipeline_inst_n_5));
  PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_pipeline rx_pipeline_inst
       (.D({rx_null_gen_inst_n_3,rx_null_gen_inst_n_4,rx_null_gen_inst_n_5,rx_null_gen_inst_n_6}),
        .E(E),
        .data_prev_reg_0(rx_null_gen_inst_n_7),
        .data_prev_reg_1(rx_null_gen_inst_n_2),
        .in0(plusOp),
        .m_axis_rx_tdata(m_axis_rx_tdata),
        .m_axis_rx_tkeep(m_axis_rx_tkeep),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser),
        .\m_axis_rx_tuser_xhdl1_reg[19]_0 (rx_pipeline_inst_n_9),
        .\m_axis_rx_tuser_xhdl1_reg[21]_0 (rx_pipeline_inst_n_7),
        .m_axis_rx_tvalid(m_axis_rx_tvalid),
        .null_mux_sel(null_mux_sel),
        .null_mux_sel_reg_0(rx_pipeline_inst_n_5),
        .null_mux_sel_reg_1(rx_null_gen_inst_n_1),
        .null_mux_sel_reg_2(rx_null_gen_inst_n_8),
        .\reg_pkt_len_counter_reg[0] (rx_null_gen_inst_n_0),
        .\reg_pkt_len_counter_reg[9] (payload_len),
        .reg_tlast_reg_0(rx_pipeline_inst_n_8),
        .rsrc_rdy_filtered10_out(rsrc_rdy_filtered10_out),
        .trn_in_packet_reg_0(trn_in_packet_reg),
        .trn_rbar_hit(trn_rbar_hit),
        .trn_rd(trn_rd),
        .trn_rdst_rdy_xhdl4_reg_0(rx_pipeline_inst_n_6),
        .trn_rdst_rdy_xhdl4_reg_1(trn_rdst_rdy_xhdl4_reg),
        .trn_recrc_err(trn_recrc_err),
        .trn_reof(trn_reof),
        .trn_rerrfwd(trn_rerrfwd),
        .trn_rrem(trn_rrem),
        .trn_rsof(trn_rsof),
        .trn_rsrc_dsc(trn_rsrc_dsc),
        .user_clk(user_clk),
        .user_reset_out_reg(user_reset_out_reg),
        .user_reset_out_reg_0(user_reset_out_reg_0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_axi_basic_rx_null_gen" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_null_gen
   (null_mux_sel_reg,
    trn_rdst_rdy_xhdl4_reg,
    \m_axis_rx_tuser_xhdl1_reg[21] ,
    D,
    reg_tlast_reg,
    \m_axis_rx_tuser_xhdl1_reg[19] ,
    in0,
    \m_axis_rx_tdata_xhdl0_reg[30] ,
    user_reset_out_reg,
    user_clk,
    user_reset_out_reg_0,
    null_mux_sel_reg_0,
    null_mux_sel,
    m_axis_rx_tready,
    data_prev_reg,
    \trn_rrem_prev_reg[0] ,
    data_prev_reg_0,
    m_axis_rx_tvalid_xhdl2_reg,
    m_axis_rx_tuser);
  output null_mux_sel_reg;
  output trn_rdst_rdy_xhdl4_reg;
  output \m_axis_rx_tuser_xhdl1_reg[21] ;
  output [3:0]D;
  output reg_tlast_reg;
  output \m_axis_rx_tuser_xhdl1_reg[19] ;
  input [4:0]in0;
  input [4:0]\m_axis_rx_tdata_xhdl0_reg[30] ;
  input user_reset_out_reg;
  input user_clk;
  input user_reset_out_reg_0;
  input null_mux_sel_reg_0;
  input null_mux_sel;
  input m_axis_rx_tready;
  input data_prev_reg;
  input \trn_rrem_prev_reg[0] ;
  input data_prev_reg_0;
  input m_axis_rx_tvalid_xhdl2_reg;
  input [0:0]m_axis_rx_tuser;

  wire [3:0]D;
  wire cur_state;
  wire data_prev_reg;
  wire data_prev_reg_0;
  wire m_axis_rx_tready;
  wire [0:0]m_axis_rx_tuser;
  wire \m_axis_rx_tuser_xhdl1[19]_i_2_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[19]_i_3_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[21]_i_4_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[21]_i_5_n_0 ;
  wire \m_axis_rx_tuser_xhdl1_reg[19] ;
  wire \m_axis_rx_tuser_xhdl1_reg[21] ;
  wire m_axis_rx_tvalid_xhdl2_reg;
  (* RTL_KEEP = "true" *) wire [11:0]new_pkt_len;
  (* RTL_KEEP = "true" *) wire [4:0]new_pkt_len_1;
  wire next_state;
  wire null_mux_sel;
  wire null_mux_sel_i_2_n_0;
  wire null_mux_sel_reg;
  wire null_mux_sel_reg_0;
  wire [1:0]pkt_len_counter;
  wire [11:0]reg_pkt_len_counter;
  wire \reg_pkt_len_counter[10]_i_1_n_0 ;
  wire \reg_pkt_len_counter[10]_i_2_n_0 ;
  wire \reg_pkt_len_counter[10]_i_3_n_0 ;
  wire \reg_pkt_len_counter[10]_i_4_n_0 ;
  wire \reg_pkt_len_counter[11]_i_1_n_0 ;
  wire \reg_pkt_len_counter[11]_i_2_n_0 ;
  wire \reg_pkt_len_counter[11]_i_4_n_0 ;
  wire \reg_pkt_len_counter[11]_i_5_n_0 ;
  wire \reg_pkt_len_counter[11]_i_6_n_0 ;
  wire \reg_pkt_len_counter[11]_i_7_n_0 ;
  wire \reg_pkt_len_counter[2]_i_1_n_0 ;
  wire \reg_pkt_len_counter[3]_i_1_n_0 ;
  wire \reg_pkt_len_counter[4]_i_1_n_0 ;
  wire \reg_pkt_len_counter[4]_i_3_n_0 ;
  wire \reg_pkt_len_counter[4]_i_4_n_0 ;
  wire \reg_pkt_len_counter[4]_i_5_n_0 ;
  wire \reg_pkt_len_counter[4]_i_6_n_0 ;
  wire \reg_pkt_len_counter[4]_i_7_n_0 ;
  wire \reg_pkt_len_counter[5]_i_1_n_0 ;
  wire \reg_pkt_len_counter[6]_i_1_n_0 ;
  wire \reg_pkt_len_counter[7]_i_1_n_0 ;
  wire \reg_pkt_len_counter[8]_i_1_n_0 ;
  wire \reg_pkt_len_counter[8]_i_3_n_0 ;
  wire \reg_pkt_len_counter[8]_i_4_n_0 ;
  wire \reg_pkt_len_counter[8]_i_5_n_0 ;
  wire \reg_pkt_len_counter[8]_i_6_n_0 ;
  wire \reg_pkt_len_counter[9]_i_1_n_0 ;
  wire \reg_pkt_len_counter_reg[11]_i_3_n_1 ;
  wire \reg_pkt_len_counter_reg[11]_i_3_n_2 ;
  wire \reg_pkt_len_counter_reg[11]_i_3_n_3 ;
  wire \reg_pkt_len_counter_reg[11]_i_3_n_4 ;
  wire \reg_pkt_len_counter_reg[11]_i_3_n_5 ;
  wire \reg_pkt_len_counter_reg[11]_i_3_n_6 ;
  wire \reg_pkt_len_counter_reg[11]_i_3_n_7 ;
  wire \reg_pkt_len_counter_reg[4]_i_2_n_0 ;
  wire \reg_pkt_len_counter_reg[4]_i_2_n_1 ;
  wire \reg_pkt_len_counter_reg[4]_i_2_n_2 ;
  wire \reg_pkt_len_counter_reg[4]_i_2_n_3 ;
  wire \reg_pkt_len_counter_reg[4]_i_2_n_4 ;
  wire \reg_pkt_len_counter_reg[4]_i_2_n_5 ;
  wire \reg_pkt_len_counter_reg[4]_i_2_n_6 ;
  wire \reg_pkt_len_counter_reg[4]_i_2_n_7 ;
  wire \reg_pkt_len_counter_reg[8]_i_2_n_0 ;
  wire \reg_pkt_len_counter_reg[8]_i_2_n_1 ;
  wire \reg_pkt_len_counter_reg[8]_i_2_n_2 ;
  wire \reg_pkt_len_counter_reg[8]_i_2_n_3 ;
  wire \reg_pkt_len_counter_reg[8]_i_2_n_4 ;
  wire \reg_pkt_len_counter_reg[8]_i_2_n_5 ;
  wire \reg_pkt_len_counter_reg[8]_i_2_n_6 ;
  wire \reg_pkt_len_counter_reg[8]_i_2_n_7 ;
  wire \reg_tkeep[4]_i_2_n_0 ;
  wire \reg_tkeep[5]_i_2_n_0 ;
  wire \reg_tkeep[6]_i_2_n_0 ;
  wire \reg_tkeep[7]_i_3_n_0 ;
  wire \reg_tkeep[7]_i_4_n_0 ;
  wire \reg_tkeep[7]_i_5_n_0 ;
  wire reg_tlast_i_3_n_0;
  wire reg_tlast_i_4_n_0;
  wire reg_tlast_i_5_n_0;
  wire reg_tlast_i_6_n_0;
  wire reg_tlast_reg;
  wire trn_rdst_rdy_xhdl4_i_3_n_0;
  wire trn_rdst_rdy_xhdl4_reg;
  wire \trn_rrem_prev_reg[0] ;
  wire user_clk;
  wire user_reset_out_reg;
  wire user_reset_out_reg_0;
  wire [3:3]\NLW_reg_pkt_len_counter_reg[11]_i_3_CO_UNCONNECTED ;

  assign new_pkt_len[9:5] = \m_axis_rx_tdata_xhdl0_reg[30] [4:0];
  assign new_pkt_len_1 = in0[4:0];
  LUT5 #(
    .INIT(32'h555D5555)) 
    cur_state_i_1
       (.I0(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I1(m_axis_rx_tvalid_xhdl2_reg),
        .I2(cur_state),
        .I3(m_axis_rx_tuser),
        .I4(m_axis_rx_tready),
        .O(next_state));
  FDRE #(
    .INIT(1'b0)) 
    cur_state_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(next_state),
        .Q(cur_state),
        .R(user_reset_out_reg));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(new_pkt_len_1[4]),
        .O(new_pkt_len[4]));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(new_pkt_len_1[3]),
        .O(new_pkt_len[3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(new_pkt_len_1[2]),
        .O(new_pkt_len[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(new_pkt_len_1[1]),
        .O(new_pkt_len[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_4
       (.I0(new_pkt_len_1[0]),
        .O(new_pkt_len[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_5
       (.I0(1'b0),
        .O(new_pkt_len[11]));
  LUT1 #(
    .INIT(2'h2)) 
    i_6
       (.I0(1'b0),
        .O(new_pkt_len[10]));
  LUT6 #(
    .INIT(64'h1000FFFF10000000)) 
    \m_axis_rx_tuser_xhdl1[19]_i_1 
       (.I0(reg_tlast_i_6_n_0),
        .I1(\reg_tkeep[7]_i_5_n_0 ),
        .I2(\m_axis_rx_tuser_xhdl1[19]_i_2_n_0 ),
        .I3(\m_axis_rx_tuser_xhdl1[19]_i_3_n_0 ),
        .I4(null_mux_sel),
        .I5(\trn_rrem_prev_reg[0] ),
        .O(\m_axis_rx_tuser_xhdl1_reg[19] ));
  LUT6 #(
    .INIT(64'h0000000047034400)) 
    \m_axis_rx_tuser_xhdl1[19]_i_2 
       (.I0(new_pkt_len[0]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(reg_pkt_len_counter[0]),
        .I3(new_pkt_len[1]),
        .I4(\reg_pkt_len_counter_reg[4]_i_2_n_7 ),
        .I5(\reg_pkt_len_counter[3]_i_1_n_0 ),
        .O(\m_axis_rx_tuser_xhdl1[19]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0001000000010101)) 
    \m_axis_rx_tuser_xhdl1[19]_i_3 
       (.I0(\reg_pkt_len_counter[4]_i_1_n_0 ),
        .I1(\reg_pkt_len_counter[2]_i_1_n_0 ),
        .I2(\reg_pkt_len_counter[5]_i_1_n_0 ),
        .I3(new_pkt_len[6]),
        .I4(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I5(\reg_pkt_len_counter_reg[8]_i_2_n_6 ),
        .O(\m_axis_rx_tuser_xhdl1[19]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT6 #(
    .INIT(64'hAAAAAAAEAAAAAAAA)) 
    \m_axis_rx_tuser_xhdl1[21]_i_2 
       (.I0(data_prev_reg),
        .I1(\m_axis_rx_tuser_xhdl1[21]_i_4_n_0 ),
        .I2(\reg_tkeep[7]_i_5_n_0 ),
        .I3(reg_tlast_i_5_n_0),
        .I4(reg_tlast_i_6_n_0),
        .I5(\m_axis_rx_tuser_xhdl1[21]_i_5_n_0 ),
        .O(\m_axis_rx_tuser_xhdl1_reg[21] ));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    \m_axis_rx_tuser_xhdl1[21]_i_4 
       (.I0(new_pkt_len[2]),
        .I1(\reg_pkt_len_counter_reg[4]_i_2_n_6 ),
        .I2(null_mux_sel),
        .I3(\reg_pkt_len_counter_reg[4]_i_2_n_4 ),
        .I4(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I5(new_pkt_len[4]),
        .O(\m_axis_rx_tuser_xhdl1[21]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000478B74B8)) 
    \m_axis_rx_tuser_xhdl1[21]_i_5 
       (.I0(new_pkt_len[1]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter_reg[4]_i_2_n_7 ),
        .I3(new_pkt_len[0]),
        .I4(reg_pkt_len_counter[0]),
        .I5(\reg_pkt_len_counter[3]_i_1_n_0 ),
        .O(\m_axis_rx_tuser_xhdl1[21]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFFFFE)) 
    null_mux_sel_i_1
       (.I0(reg_tlast_i_4_n_0),
        .I1(reg_tlast_i_5_n_0),
        .I2(reg_tlast_i_6_n_0),
        .I3(\reg_tkeep[7]_i_5_n_0 ),
        .I4(null_mux_sel_i_2_n_0),
        .I5(user_reset_out_reg_0),
        .O(null_mux_sel_reg));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    null_mux_sel_i_2
       (.I0(null_mux_sel),
        .I1(m_axis_rx_tready),
        .I2(\reg_pkt_len_counter[4]_i_1_n_0 ),
        .I3(\reg_pkt_len_counter[3]_i_1_n_0 ),
        .I4(\reg_pkt_len_counter[2]_i_1_n_0 ),
        .O(null_mux_sel_i_2_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[0]_i_1 
       (.I0(new_pkt_len[0]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(reg_pkt_len_counter[0]),
        .O(pkt_len_counter[0]));
  LUT6 #(
    .INIT(64'hBFFFAAAA8000AAAA)) 
    \reg_pkt_len_counter[10]_i_1 
       (.I0(new_pkt_len[10]),
        .I1(\reg_pkt_len_counter[10]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter[10]_i_3_n_0 ),
        .I3(\reg_pkt_len_counter[10]_i_4_n_0 ),
        .I4(cur_state),
        .I5(\reg_pkt_len_counter_reg[11]_i_3_n_6 ),
        .O(\reg_pkt_len_counter[10]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \reg_pkt_len_counter[10]_i_2 
       (.I0(reg_pkt_len_counter[9]),
        .I1(reg_pkt_len_counter[6]),
        .I2(reg_pkt_len_counter[11]),
        .I3(reg_pkt_len_counter[5]),
        .I4(reg_pkt_len_counter[10]),
        .O(\reg_pkt_len_counter[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \reg_pkt_len_counter[10]_i_3 
       (.I0(reg_pkt_len_counter[3]),
        .I1(reg_pkt_len_counter[2]),
        .I2(m_axis_rx_tready),
        .I3(reg_pkt_len_counter[7]),
        .I4(reg_pkt_len_counter[4]),
        .I5(reg_pkt_len_counter[8]),
        .O(\reg_pkt_len_counter[10]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \reg_pkt_len_counter[10]_i_4 
       (.I0(reg_pkt_len_counter[1]),
        .I1(reg_pkt_len_counter[0]),
        .O(\reg_pkt_len_counter[10]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[11]_i_1 
       (.I0(new_pkt_len[11]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter_reg[11]_i_3_n_5 ),
        .O(\reg_pkt_len_counter[11]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0888FFFF)) 
    \reg_pkt_len_counter[11]_i_2 
       (.I0(\reg_pkt_len_counter[10]_i_2_n_0 ),
        .I1(\reg_pkt_len_counter[10]_i_3_n_0 ),
        .I2(reg_pkt_len_counter[1]),
        .I3(reg_pkt_len_counter[0]),
        .I4(cur_state),
        .O(\reg_pkt_len_counter[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \reg_pkt_len_counter[11]_i_4 
       (.I0(reg_pkt_len_counter[11]),
        .O(\reg_pkt_len_counter[11]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \reg_pkt_len_counter[11]_i_5 
       (.I0(reg_pkt_len_counter[10]),
        .I1(reg_pkt_len_counter[11]),
        .O(\reg_pkt_len_counter[11]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \reg_pkt_len_counter[11]_i_6 
       (.I0(reg_pkt_len_counter[9]),
        .I1(reg_pkt_len_counter[10]),
        .O(\reg_pkt_len_counter[11]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \reg_pkt_len_counter[11]_i_7 
       (.I0(reg_pkt_len_counter[8]),
        .I1(reg_pkt_len_counter[9]),
        .O(\reg_pkt_len_counter[11]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFAAAA8000AAAA)) 
    \reg_pkt_len_counter[1]_i_1 
       (.I0(new_pkt_len[1]),
        .I1(\reg_pkt_len_counter[10]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter[10]_i_3_n_0 ),
        .I3(\reg_pkt_len_counter[10]_i_4_n_0 ),
        .I4(cur_state),
        .I5(\reg_pkt_len_counter_reg[4]_i_2_n_7 ),
        .O(pkt_len_counter[1]));
  LUT6 #(
    .INIT(64'hBFFFAAAA8000AAAA)) 
    \reg_pkt_len_counter[2]_i_1 
       (.I0(new_pkt_len[2]),
        .I1(\reg_pkt_len_counter[10]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter[10]_i_3_n_0 ),
        .I3(\reg_pkt_len_counter[10]_i_4_n_0 ),
        .I4(cur_state),
        .I5(\reg_pkt_len_counter_reg[4]_i_2_n_6 ),
        .O(\reg_pkt_len_counter[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFAAAA8000AAAA)) 
    \reg_pkt_len_counter[3]_i_1 
       (.I0(new_pkt_len[3]),
        .I1(\reg_pkt_len_counter[10]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter[10]_i_3_n_0 ),
        .I3(\reg_pkt_len_counter[10]_i_4_n_0 ),
        .I4(cur_state),
        .I5(\reg_pkt_len_counter_reg[4]_i_2_n_5 ),
        .O(\reg_pkt_len_counter[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFAAAA8000AAAA)) 
    \reg_pkt_len_counter[4]_i_1 
       (.I0(new_pkt_len[4]),
        .I1(\reg_pkt_len_counter[10]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter[10]_i_3_n_0 ),
        .I3(\reg_pkt_len_counter[10]_i_4_n_0 ),
        .I4(cur_state),
        .I5(\reg_pkt_len_counter_reg[4]_i_2_n_4 ),
        .O(\reg_pkt_len_counter[4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \reg_pkt_len_counter[4]_i_3 
       (.I0(reg_pkt_len_counter[1]),
        .I1(m_axis_rx_tready),
        .O(\reg_pkt_len_counter[4]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \reg_pkt_len_counter[4]_i_4 
       (.I0(reg_pkt_len_counter[3]),
        .I1(reg_pkt_len_counter[4]),
        .O(\reg_pkt_len_counter[4]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \reg_pkt_len_counter[4]_i_5 
       (.I0(reg_pkt_len_counter[2]),
        .I1(reg_pkt_len_counter[3]),
        .O(\reg_pkt_len_counter[4]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hD2)) 
    \reg_pkt_len_counter[4]_i_6 
       (.I0(m_axis_rx_tready),
        .I1(reg_pkt_len_counter[1]),
        .I2(reg_pkt_len_counter[2]),
        .O(\reg_pkt_len_counter[4]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \reg_pkt_len_counter[4]_i_7 
       (.I0(m_axis_rx_tready),
        .I1(reg_pkt_len_counter[1]),
        .O(\reg_pkt_len_counter[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFAAAA8000AAAA)) 
    \reg_pkt_len_counter[5]_i_1 
       (.I0(new_pkt_len[5]),
        .I1(\reg_pkt_len_counter[10]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter[10]_i_3_n_0 ),
        .I3(\reg_pkt_len_counter[10]_i_4_n_0 ),
        .I4(cur_state),
        .I5(\reg_pkt_len_counter_reg[8]_i_2_n_7 ),
        .O(\reg_pkt_len_counter[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFAAAA8000AAAA)) 
    \reg_pkt_len_counter[6]_i_1 
       (.I0(new_pkt_len[6]),
        .I1(\reg_pkt_len_counter[10]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter[10]_i_3_n_0 ),
        .I3(\reg_pkt_len_counter[10]_i_4_n_0 ),
        .I4(cur_state),
        .I5(\reg_pkt_len_counter_reg[8]_i_2_n_6 ),
        .O(\reg_pkt_len_counter[6]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_pkt_len_counter[7]_i_1 
       (.I0(new_pkt_len[7]),
        .I1(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter_reg[8]_i_2_n_5 ),
        .O(\reg_pkt_len_counter[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFAAAA8000AAAA)) 
    \reg_pkt_len_counter[8]_i_1 
       (.I0(new_pkt_len[8]),
        .I1(\reg_pkt_len_counter[10]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter[10]_i_3_n_0 ),
        .I3(\reg_pkt_len_counter[10]_i_4_n_0 ),
        .I4(cur_state),
        .I5(\reg_pkt_len_counter_reg[8]_i_2_n_4 ),
        .O(\reg_pkt_len_counter[8]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \reg_pkt_len_counter[8]_i_3 
       (.I0(reg_pkt_len_counter[7]),
        .I1(reg_pkt_len_counter[8]),
        .O(\reg_pkt_len_counter[8]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \reg_pkt_len_counter[8]_i_4 
       (.I0(reg_pkt_len_counter[6]),
        .I1(reg_pkt_len_counter[7]),
        .O(\reg_pkt_len_counter[8]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \reg_pkt_len_counter[8]_i_5 
       (.I0(reg_pkt_len_counter[5]),
        .I1(reg_pkt_len_counter[6]),
        .O(\reg_pkt_len_counter[8]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \reg_pkt_len_counter[8]_i_6 
       (.I0(reg_pkt_len_counter[4]),
        .I1(reg_pkt_len_counter[5]),
        .O(\reg_pkt_len_counter[8]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFAAAA8000AAAA)) 
    \reg_pkt_len_counter[9]_i_1 
       (.I0(new_pkt_len[9]),
        .I1(\reg_pkt_len_counter[10]_i_2_n_0 ),
        .I2(\reg_pkt_len_counter[10]_i_3_n_0 ),
        .I3(\reg_pkt_len_counter[10]_i_4_n_0 ),
        .I4(cur_state),
        .I5(\reg_pkt_len_counter_reg[11]_i_3_n_7 ),
        .O(\reg_pkt_len_counter[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(pkt_len_counter[0]),
        .Q(reg_pkt_len_counter[0]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter[10]_i_1_n_0 ),
        .Q(reg_pkt_len_counter[10]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter[11]_i_1_n_0 ),
        .Q(reg_pkt_len_counter[11]),
        .R(user_reset_out_reg));
  CARRY4 \reg_pkt_len_counter_reg[11]_i_3 
       (.CI(\reg_pkt_len_counter_reg[8]_i_2_n_0 ),
        .CO({\NLW_reg_pkt_len_counter_reg[11]_i_3_CO_UNCONNECTED [3],\reg_pkt_len_counter_reg[11]_i_3_n_1 ,\reg_pkt_len_counter_reg[11]_i_3_n_2 ,\reg_pkt_len_counter_reg[11]_i_3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,reg_pkt_len_counter[10:8]}),
        .O({\reg_pkt_len_counter_reg[11]_i_3_n_4 ,\reg_pkt_len_counter_reg[11]_i_3_n_5 ,\reg_pkt_len_counter_reg[11]_i_3_n_6 ,\reg_pkt_len_counter_reg[11]_i_3_n_7 }),
        .S({\reg_pkt_len_counter[11]_i_4_n_0 ,\reg_pkt_len_counter[11]_i_5_n_0 ,\reg_pkt_len_counter[11]_i_6_n_0 ,\reg_pkt_len_counter[11]_i_7_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(pkt_len_counter[1]),
        .Q(reg_pkt_len_counter[1]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter[2]_i_1_n_0 ),
        .Q(reg_pkt_len_counter[2]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter[3]_i_1_n_0 ),
        .Q(reg_pkt_len_counter[3]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter[4]_i_1_n_0 ),
        .Q(reg_pkt_len_counter[4]),
        .R(user_reset_out_reg));
  CARRY4 \reg_pkt_len_counter_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\reg_pkt_len_counter_reg[4]_i_2_n_0 ,\reg_pkt_len_counter_reg[4]_i_2_n_1 ,\reg_pkt_len_counter_reg[4]_i_2_n_2 ,\reg_pkt_len_counter_reg[4]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({reg_pkt_len_counter[3:2],\reg_pkt_len_counter[4]_i_3_n_0 ,1'b0}),
        .O({\reg_pkt_len_counter_reg[4]_i_2_n_4 ,\reg_pkt_len_counter_reg[4]_i_2_n_5 ,\reg_pkt_len_counter_reg[4]_i_2_n_6 ,\reg_pkt_len_counter_reg[4]_i_2_n_7 }),
        .S({\reg_pkt_len_counter[4]_i_4_n_0 ,\reg_pkt_len_counter[4]_i_5_n_0 ,\reg_pkt_len_counter[4]_i_6_n_0 ,\reg_pkt_len_counter[4]_i_7_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter[5]_i_1_n_0 ),
        .Q(reg_pkt_len_counter[5]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter[6]_i_1_n_0 ),
        .Q(reg_pkt_len_counter[6]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter[7]_i_1_n_0 ),
        .Q(reg_pkt_len_counter[7]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter[8]_i_1_n_0 ),
        .Q(reg_pkt_len_counter[8]),
        .R(user_reset_out_reg));
  CARRY4 \reg_pkt_len_counter_reg[8]_i_2 
       (.CI(\reg_pkt_len_counter_reg[4]_i_2_n_0 ),
        .CO({\reg_pkt_len_counter_reg[8]_i_2_n_0 ,\reg_pkt_len_counter_reg[8]_i_2_n_1 ,\reg_pkt_len_counter_reg[8]_i_2_n_2 ,\reg_pkt_len_counter_reg[8]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI(reg_pkt_len_counter[7:4]),
        .O({\reg_pkt_len_counter_reg[8]_i_2_n_4 ,\reg_pkt_len_counter_reg[8]_i_2_n_5 ,\reg_pkt_len_counter_reg[8]_i_2_n_6 ,\reg_pkt_len_counter_reg[8]_i_2_n_7 }),
        .S({\reg_pkt_len_counter[8]_i_3_n_0 ,\reg_pkt_len_counter[8]_i_4_n_0 ,\reg_pkt_len_counter[8]_i_5_n_0 ,\reg_pkt_len_counter[8]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \reg_pkt_len_counter_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter[9]_i_1_n_0 ),
        .Q(reg_pkt_len_counter[9]),
        .R(user_reset_out_reg));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT6 #(
    .INIT(64'hFFAAFFAAFFAAFCAA)) 
    \reg_tkeep[4]_i_1 
       (.I0(\trn_rrem_prev_reg[0] ),
        .I1(\reg_tkeep[7]_i_3_n_0 ),
        .I2(\reg_tkeep[4]_i_2_n_0 ),
        .I3(null_mux_sel),
        .I4(\reg_pkt_len_counter[4]_i_1_n_0 ),
        .I5(\reg_tkeep[7]_i_5_n_0 ),
        .O(D[0]));
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \reg_tkeep[4]_i_2 
       (.I0(\reg_pkt_len_counter_reg[4]_i_2_n_6 ),
        .I1(new_pkt_len[2]),
        .I2(\reg_pkt_len_counter_reg[4]_i_2_n_5 ),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(new_pkt_len[3]),
        .O(\reg_tkeep[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT6 #(
    .INIT(64'hFFAAFFAAFFAAFCAA)) 
    \reg_tkeep[5]_i_1 
       (.I0(\trn_rrem_prev_reg[0] ),
        .I1(\reg_tkeep[7]_i_3_n_0 ),
        .I2(\reg_tkeep[5]_i_2_n_0 ),
        .I3(null_mux_sel),
        .I4(\reg_pkt_len_counter[4]_i_1_n_0 ),
        .I5(\reg_tkeep[7]_i_5_n_0 ),
        .O(D[1]));
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \reg_tkeep[5]_i_2 
       (.I0(\reg_pkt_len_counter_reg[4]_i_2_n_6 ),
        .I1(new_pkt_len[2]),
        .I2(\reg_pkt_len_counter_reg[4]_i_2_n_5 ),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(new_pkt_len[3]),
        .O(\reg_tkeep[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT6 #(
    .INIT(64'hFFAAFFAAFFAAFCAA)) 
    \reg_tkeep[6]_i_1 
       (.I0(\trn_rrem_prev_reg[0] ),
        .I1(\reg_tkeep[7]_i_3_n_0 ),
        .I2(\reg_tkeep[6]_i_2_n_0 ),
        .I3(null_mux_sel),
        .I4(\reg_pkt_len_counter[4]_i_1_n_0 ),
        .I5(\reg_tkeep[7]_i_5_n_0 ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \reg_tkeep[6]_i_2 
       (.I0(\reg_pkt_len_counter_reg[4]_i_2_n_6 ),
        .I1(new_pkt_len[2]),
        .I2(\reg_pkt_len_counter_reg[4]_i_2_n_5 ),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(new_pkt_len[3]),
        .O(\reg_tkeep[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT6 #(
    .INIT(64'hFFAAFFAAFFAAFCAA)) 
    \reg_tkeep[7]_i_1 
       (.I0(\trn_rrem_prev_reg[0] ),
        .I1(\reg_tkeep[7]_i_3_n_0 ),
        .I2(\reg_tkeep[7]_i_4_n_0 ),
        .I3(null_mux_sel),
        .I4(\reg_pkt_len_counter[4]_i_1_n_0 ),
        .I5(\reg_tkeep[7]_i_5_n_0 ),
        .O(D[3]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \reg_tkeep[7]_i_3 
       (.I0(\reg_pkt_len_counter[10]_i_1_n_0 ),
        .I1(\reg_pkt_len_counter[8]_i_1_n_0 ),
        .I2(pkt_len_counter[1]),
        .I3(\reg_pkt_len_counter[6]_i_1_n_0 ),
        .I4(\reg_pkt_len_counter[5]_i_1_n_0 ),
        .O(\reg_tkeep[7]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \reg_tkeep[7]_i_4 
       (.I0(\reg_pkt_len_counter_reg[4]_i_2_n_6 ),
        .I1(new_pkt_len[2]),
        .I2(\reg_pkt_len_counter_reg[4]_i_2_n_5 ),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(new_pkt_len[3]),
        .O(\reg_tkeep[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFCFFFFFFFCFAFA)) 
    \reg_tkeep[7]_i_5 
       (.I0(\reg_pkt_len_counter_reg[8]_i_2_n_5 ),
        .I1(new_pkt_len[7]),
        .I2(\reg_pkt_len_counter[9]_i_1_n_0 ),
        .I3(new_pkt_len[11]),
        .I4(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I5(\reg_pkt_len_counter_reg[11]_i_3_n_5 ),
        .O(\reg_tkeep[7]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAAB)) 
    reg_tlast_i_1
       (.I0(data_prev_reg_0),
        .I1(\reg_tkeep[7]_i_5_n_0 ),
        .I2(reg_tlast_i_3_n_0),
        .I3(reg_tlast_i_4_n_0),
        .I4(reg_tlast_i_5_n_0),
        .I5(reg_tlast_i_6_n_0),
        .O(reg_tlast_reg));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFDFD5)) 
    reg_tlast_i_3
       (.I0(null_mux_sel),
        .I1(new_pkt_len[4]),
        .I2(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I3(\reg_pkt_len_counter_reg[4]_i_2_n_4 ),
        .I4(\reg_pkt_len_counter[3]_i_1_n_0 ),
        .I5(\reg_pkt_len_counter[2]_i_1_n_0 ),
        .O(reg_tlast_i_3_n_0));
  LUT5 #(
    .INIT(32'hCCA000A0)) 
    reg_tlast_i_4
       (.I0(reg_pkt_len_counter[0]),
        .I1(new_pkt_len[0]),
        .I2(\reg_pkt_len_counter_reg[4]_i_2_n_7 ),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(new_pkt_len[1]),
        .O(reg_tlast_i_4_n_0));
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    reg_tlast_i_5
       (.I0(\reg_pkt_len_counter_reg[8]_i_2_n_6 ),
        .I1(new_pkt_len[6]),
        .I2(\reg_pkt_len_counter_reg[8]_i_2_n_7 ),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(new_pkt_len[5]),
        .O(reg_tlast_i_5_n_0));
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    reg_tlast_i_6
       (.I0(\reg_pkt_len_counter_reg[8]_i_2_n_4 ),
        .I1(new_pkt_len[8]),
        .I2(\reg_pkt_len_counter_reg[11]_i_3_n_6 ),
        .I3(\reg_pkt_len_counter[11]_i_2_n_0 ),
        .I4(new_pkt_len[10]),
        .O(reg_tlast_i_6_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAAB)) 
    trn_rdst_rdy_xhdl4_i_1
       (.I0(null_mux_sel_reg_0),
        .I1(\reg_tkeep[7]_i_5_n_0 ),
        .I2(trn_rdst_rdy_xhdl4_i_3_n_0),
        .I3(reg_tlast_i_4_n_0),
        .I4(reg_tlast_i_5_n_0),
        .I5(reg_tlast_i_6_n_0),
        .O(trn_rdst_rdy_xhdl4_reg));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    trn_rdst_rdy_xhdl4_i_3
       (.I0(null_mux_sel),
        .I1(m_axis_rx_tready),
        .I2(\reg_pkt_len_counter[4]_i_1_n_0 ),
        .I3(\reg_pkt_len_counter[3]_i_1_n_0 ),
        .I4(\reg_pkt_len_counter[2]_i_1_n_0 ),
        .O(trn_rdst_rdy_xhdl4_i_3_n_0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_axi_basic_rx_pipeline" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx_pipeline
   (null_mux_sel,
    E,
    m_axis_rx_tvalid,
    m_axis_rx_tlast,
    trn_in_packet_reg_0,
    null_mux_sel_reg_0,
    trn_rdst_rdy_xhdl4_reg_0,
    \m_axis_rx_tuser_xhdl1_reg[21]_0 ,
    reg_tlast_reg_0,
    \m_axis_rx_tuser_xhdl1_reg[19]_0 ,
    m_axis_rx_tdata,
    m_axis_rx_tkeep,
    m_axis_rx_tuser,
    \reg_pkt_len_counter_reg[9] ,
    in0,
    user_reset_out_reg,
    trn_rsrc_dsc,
    user_clk,
    \reg_pkt_len_counter_reg[0] ,
    null_mux_sel_reg_1,
    rsrc_rdy_filtered10_out,
    trn_rrem,
    trn_reof,
    data_prev_reg_0,
    trn_rsof,
    trn_recrc_err,
    trn_rerrfwd,
    user_reset_out_reg_0,
    m_axis_rx_tready,
    trn_rdst_rdy_xhdl4_reg_1,
    trn_rbar_hit,
    trn_rd,
    D,
    data_prev_reg_1,
    null_mux_sel_reg_2);
  output null_mux_sel;
  output [0:0]E;
  output m_axis_rx_tvalid;
  output m_axis_rx_tlast;
  output trn_in_packet_reg_0;
  output null_mux_sel_reg_0;
  output trn_rdst_rdy_xhdl4_reg_0;
  output \m_axis_rx_tuser_xhdl1_reg[21]_0 ;
  output reg_tlast_reg_0;
  output \m_axis_rx_tuser_xhdl1_reg[19]_0 ;
  output [63:0]m_axis_rx_tdata;
  output [7:0]m_axis_rx_tkeep;
  output [21:0]m_axis_rx_tuser;
  output [4:0]\reg_pkt_len_counter_reg[9] ;
  output [4:0]in0;
  input user_reset_out_reg;
  input trn_rsrc_dsc;
  input user_clk;
  input \reg_pkt_len_counter_reg[0] ;
  input null_mux_sel_reg_1;
  input rsrc_rdy_filtered10_out;
  input [0:0]trn_rrem;
  input trn_reof;
  input data_prev_reg_0;
  input trn_rsof;
  input trn_recrc_err;
  input trn_rerrfwd;
  input user_reset_out_reg_0;
  input m_axis_rx_tready;
  input trn_rdst_rdy_xhdl4_reg_1;
  input [6:0]trn_rbar_hit;
  input [63:0]trn_rd;
  input [3:0]D;
  input data_prev_reg_1;
  input null_mux_sel_reg_2;

  wire [3:0]D;
  wire [0:0]E;
  wire data_hold;
  wire data_prev;
  wire data_prev_reg_0;
  wire data_prev_reg_1;
  wire [4:0]in0;
  wire [4:2]is_eof_prev;
  wire [63:0]m_axis_rx_tdata;
  wire \m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ;
  wire [7:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [21:0]m_axis_rx_tuser;
  wire \m_axis_rx_tuser_xhdl1[0]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[14]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[1]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[2]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[3]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[4]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[5]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[6]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[7]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1[8]_i_1_n_0 ;
  wire \m_axis_rx_tuser_xhdl1_reg[19]_0 ;
  wire \m_axis_rx_tuser_xhdl1_reg[21]_0 ;
  wire m_axis_rx_tvalid;
  wire m_axis_rx_tvalid_xhdl2_i_1_n_0;
  wire m_axis_rx_tvalid_xhdl2_i_2_n_0;
  wire new_pkt_len_1_inferred_i_6_n_0;
  wire null_mux_sel;
  wire null_mux_sel_reg_0;
  wire null_mux_sel_reg_1;
  wire null_mux_sel_reg_2;
  wire [63:0]p_1_in;
  wire reg_dsc_detect_i_1_n_0;
  wire reg_dsc_detect_i_3_n_0;
  wire reg_dsc_detect_reg_n_0;
  wire \reg_pkt_len_counter_reg[0] ;
  wire [4:0]\reg_pkt_len_counter_reg[9] ;
  wire reg_tlast_reg_0;
  wire rsrc_rdy_filtered10_out;
  wire trn_in_packet_reg_0;
  wire [6:0]trn_rbar_hit;
  wire [6:0]trn_rbar_hit_prev;
  wire [63:0]trn_rd;
  wire [63:0]trn_rd_prev;
  wire trn_rdst_rdy_xhdl4_i_4_n_0;
  wire trn_rdst_rdy_xhdl4_reg_0;
  wire trn_rdst_rdy_xhdl4_reg_1;
  wire trn_recrc_err;
  wire trn_recrc_err_prev;
  wire trn_reof;
  wire trn_rerrfwd;
  wire trn_rerrfwd_prev;
  wire [0:0]trn_rrem;
  wire trn_rsof;
  wire trn_rsof_prev;
  wire trn_rsrc_dsc;
  wire trn_rsrc_dsc_d;
  wire trn_rsrc_dsc_prev;
  wire trn_rsrc_dsc_prev0;
  wire trn_rsrc_rdy_prev;
  wire user_clk;
  wire user_reset_out_reg;
  wire user_reset_out_reg_0;

  LUT2 #(
    .INIT(4'h2)) 
    data_prev_i_1
       (.I0(m_axis_rx_tvalid),
        .I1(m_axis_rx_tready),
        .O(data_hold));
  FDRE #(
    .INIT(1'b0)) 
    data_prev_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(data_hold),
        .Q(data_prev),
        .R(user_reset_out_reg));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[0]_i_1 
       (.I0(trn_rd_prev[0]),
        .I1(data_prev),
        .I2(trn_rd[32]),
        .O(p_1_in[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[10]_i_1 
       (.I0(trn_rd_prev[10]),
        .I1(data_prev),
        .I2(trn_rd[42]),
        .O(p_1_in[10]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[11]_i_1 
       (.I0(trn_rd_prev[11]),
        .I1(data_prev),
        .I2(trn_rd[43]),
        .O(p_1_in[11]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[12]_i_1 
       (.I0(trn_rd_prev[12]),
        .I1(data_prev),
        .I2(trn_rd[44]),
        .O(p_1_in[12]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[13]_i_1 
       (.I0(trn_rd_prev[13]),
        .I1(data_prev),
        .I2(trn_rd[45]),
        .O(p_1_in[13]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[14]_i_1 
       (.I0(trn_rd_prev[14]),
        .I1(data_prev),
        .I2(trn_rd[46]),
        .O(p_1_in[14]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[15]_i_1 
       (.I0(trn_rd_prev[15]),
        .I1(data_prev),
        .I2(trn_rd[47]),
        .O(p_1_in[15]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[16]_i_1 
       (.I0(trn_rd_prev[16]),
        .I1(data_prev),
        .I2(trn_rd[48]),
        .O(p_1_in[16]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[17]_i_1 
       (.I0(trn_rd_prev[17]),
        .I1(data_prev),
        .I2(trn_rd[49]),
        .O(p_1_in[17]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[18]_i_1 
       (.I0(trn_rd_prev[18]),
        .I1(data_prev),
        .I2(trn_rd[50]),
        .O(p_1_in[18]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[19]_i_1 
       (.I0(trn_rd_prev[19]),
        .I1(data_prev),
        .I2(trn_rd[51]),
        .O(p_1_in[19]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[1]_i_1 
       (.I0(trn_rd_prev[1]),
        .I1(data_prev),
        .I2(trn_rd[33]),
        .O(p_1_in[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[20]_i_1 
       (.I0(trn_rd_prev[20]),
        .I1(data_prev),
        .I2(trn_rd[52]),
        .O(p_1_in[20]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[21]_i_1 
       (.I0(trn_rd_prev[21]),
        .I1(data_prev),
        .I2(trn_rd[53]),
        .O(p_1_in[21]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[22]_i_1 
       (.I0(trn_rd_prev[22]),
        .I1(data_prev),
        .I2(trn_rd[54]),
        .O(p_1_in[22]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[23]_i_1 
       (.I0(trn_rd_prev[23]),
        .I1(data_prev),
        .I2(trn_rd[55]),
        .O(p_1_in[23]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[24]_i_1 
       (.I0(trn_rd_prev[24]),
        .I1(data_prev),
        .I2(trn_rd[56]),
        .O(p_1_in[24]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[25]_i_1 
       (.I0(trn_rd_prev[25]),
        .I1(data_prev),
        .I2(trn_rd[57]),
        .O(p_1_in[25]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[26]_i_1 
       (.I0(trn_rd_prev[26]),
        .I1(data_prev),
        .I2(trn_rd[58]),
        .O(p_1_in[26]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[27]_i_1 
       (.I0(trn_rd_prev[27]),
        .I1(data_prev),
        .I2(trn_rd[59]),
        .O(p_1_in[27]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[28]_i_1 
       (.I0(trn_rd_prev[28]),
        .I1(data_prev),
        .I2(trn_rd[60]),
        .O(p_1_in[28]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[29]_i_1 
       (.I0(trn_rd_prev[29]),
        .I1(data_prev),
        .I2(trn_rd[61]),
        .O(p_1_in[29]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[2]_i_1 
       (.I0(trn_rd_prev[2]),
        .I1(data_prev),
        .I2(trn_rd[34]),
        .O(p_1_in[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[30]_i_1 
       (.I0(trn_rd_prev[30]),
        .I1(data_prev),
        .I2(trn_rd[62]),
        .O(p_1_in[30]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[31]_i_1 
       (.I0(trn_rd_prev[31]),
        .I1(data_prev),
        .I2(trn_rd[63]),
        .O(p_1_in[31]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[32]_i_1 
       (.I0(trn_rd_prev[32]),
        .I1(data_prev),
        .I2(trn_rd[0]),
        .O(p_1_in[32]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[33]_i_1 
       (.I0(trn_rd_prev[33]),
        .I1(data_prev),
        .I2(trn_rd[1]),
        .O(p_1_in[33]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[34]_i_1 
       (.I0(trn_rd_prev[34]),
        .I1(data_prev),
        .I2(trn_rd[2]),
        .O(p_1_in[34]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[35]_i_1 
       (.I0(trn_rd_prev[35]),
        .I1(data_prev),
        .I2(trn_rd[3]),
        .O(p_1_in[35]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[36]_i_1 
       (.I0(trn_rd_prev[36]),
        .I1(data_prev),
        .I2(trn_rd[4]),
        .O(p_1_in[36]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[37]_i_1 
       (.I0(trn_rd_prev[37]),
        .I1(data_prev),
        .I2(trn_rd[5]),
        .O(p_1_in[37]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[38]_i_1 
       (.I0(trn_rd_prev[38]),
        .I1(data_prev),
        .I2(trn_rd[6]),
        .O(p_1_in[38]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[39]_i_1 
       (.I0(trn_rd_prev[39]),
        .I1(data_prev),
        .I2(trn_rd[7]),
        .O(p_1_in[39]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[3]_i_1 
       (.I0(trn_rd_prev[3]),
        .I1(data_prev),
        .I2(trn_rd[35]),
        .O(p_1_in[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[40]_i_1 
       (.I0(trn_rd_prev[40]),
        .I1(data_prev),
        .I2(trn_rd[8]),
        .O(p_1_in[40]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[41]_i_1 
       (.I0(trn_rd_prev[41]),
        .I1(data_prev),
        .I2(trn_rd[9]),
        .O(p_1_in[41]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[42]_i_1 
       (.I0(trn_rd_prev[42]),
        .I1(data_prev),
        .I2(trn_rd[10]),
        .O(p_1_in[42]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[43]_i_1 
       (.I0(trn_rd_prev[43]),
        .I1(data_prev),
        .I2(trn_rd[11]),
        .O(p_1_in[43]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[44]_i_1 
       (.I0(trn_rd_prev[44]),
        .I1(data_prev),
        .I2(trn_rd[12]),
        .O(p_1_in[44]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[45]_i_1 
       (.I0(trn_rd_prev[45]),
        .I1(data_prev),
        .I2(trn_rd[13]),
        .O(p_1_in[45]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[46]_i_1 
       (.I0(trn_rd_prev[46]),
        .I1(data_prev),
        .I2(trn_rd[14]),
        .O(p_1_in[46]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[47]_i_1 
       (.I0(trn_rd_prev[47]),
        .I1(data_prev),
        .I2(trn_rd[15]),
        .O(p_1_in[47]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[48]_i_1 
       (.I0(trn_rd_prev[48]),
        .I1(data_prev),
        .I2(trn_rd[16]),
        .O(p_1_in[48]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[49]_i_1 
       (.I0(trn_rd_prev[49]),
        .I1(data_prev),
        .I2(trn_rd[17]),
        .O(p_1_in[49]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[4]_i_1 
       (.I0(trn_rd_prev[4]),
        .I1(data_prev),
        .I2(trn_rd[36]),
        .O(p_1_in[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[50]_i_1 
       (.I0(trn_rd_prev[50]),
        .I1(data_prev),
        .I2(trn_rd[18]),
        .O(p_1_in[50]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[51]_i_1 
       (.I0(trn_rd_prev[51]),
        .I1(data_prev),
        .I2(trn_rd[19]),
        .O(p_1_in[51]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[52]_i_1 
       (.I0(trn_rd_prev[52]),
        .I1(data_prev),
        .I2(trn_rd[20]),
        .O(p_1_in[52]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[53]_i_1 
       (.I0(trn_rd_prev[53]),
        .I1(data_prev),
        .I2(trn_rd[21]),
        .O(p_1_in[53]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[54]_i_1 
       (.I0(trn_rd_prev[54]),
        .I1(data_prev),
        .I2(trn_rd[22]),
        .O(p_1_in[54]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[55]_i_1 
       (.I0(trn_rd_prev[55]),
        .I1(data_prev),
        .I2(trn_rd[23]),
        .O(p_1_in[55]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[56]_i_1 
       (.I0(trn_rd_prev[56]),
        .I1(data_prev),
        .I2(trn_rd[24]),
        .O(p_1_in[56]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[57]_i_1 
       (.I0(trn_rd_prev[57]),
        .I1(data_prev),
        .I2(trn_rd[25]),
        .O(p_1_in[57]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[58]_i_1 
       (.I0(trn_rd_prev[58]),
        .I1(data_prev),
        .I2(trn_rd[26]),
        .O(p_1_in[58]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[59]_i_1 
       (.I0(trn_rd_prev[59]),
        .I1(data_prev),
        .I2(trn_rd[27]),
        .O(p_1_in[59]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[5]_i_1 
       (.I0(trn_rd_prev[5]),
        .I1(data_prev),
        .I2(trn_rd[37]),
        .O(p_1_in[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[60]_i_1 
       (.I0(trn_rd_prev[60]),
        .I1(data_prev),
        .I2(trn_rd[28]),
        .O(p_1_in[60]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[61]_i_1 
       (.I0(trn_rd_prev[61]),
        .I1(data_prev),
        .I2(trn_rd[29]),
        .O(p_1_in[61]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[62]_i_1 
       (.I0(trn_rd_prev[62]),
        .I1(data_prev),
        .I2(trn_rd[30]),
        .O(p_1_in[62]));
  LUT2 #(
    .INIT(4'hB)) 
    \m_axis_rx_tdata_xhdl0[63]_i_1 
       (.I0(m_axis_rx_tready),
        .I1(m_axis_rx_tvalid),
        .O(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[63]_i_2 
       (.I0(trn_rd_prev[63]),
        .I1(data_prev),
        .I2(trn_rd[31]),
        .O(p_1_in[63]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[6]_i_1 
       (.I0(trn_rd_prev[6]),
        .I1(data_prev),
        .I2(trn_rd[38]),
        .O(p_1_in[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[7]_i_1 
       (.I0(trn_rd_prev[7]),
        .I1(data_prev),
        .I2(trn_rd[39]),
        .O(p_1_in[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[8]_i_1 
       (.I0(trn_rd_prev[8]),
        .I1(data_prev),
        .I2(trn_rd[40]),
        .O(p_1_in[8]));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tdata_xhdl0[9]_i_1 
       (.I0(trn_rd_prev[9]),
        .I1(data_prev),
        .I2(trn_rd[41]),
        .O(p_1_in[9]));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[0] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(m_axis_rx_tdata[0]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[10] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[10]),
        .Q(m_axis_rx_tdata[10]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[11] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[11]),
        .Q(m_axis_rx_tdata[11]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[12] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[12]),
        .Q(m_axis_rx_tdata[12]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[13] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[13]),
        .Q(m_axis_rx_tdata[13]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[14] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[14]),
        .Q(m_axis_rx_tdata[14]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[15] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[15]),
        .Q(m_axis_rx_tdata[15]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[16] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[16]),
        .Q(m_axis_rx_tdata[16]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[17] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[17]),
        .Q(m_axis_rx_tdata[17]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[18] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[18]),
        .Q(m_axis_rx_tdata[18]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[19] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[19]),
        .Q(m_axis_rx_tdata[19]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[1] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(m_axis_rx_tdata[1]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[20] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[20]),
        .Q(m_axis_rx_tdata[20]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[21] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[21]),
        .Q(m_axis_rx_tdata[21]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[22] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[22]),
        .Q(m_axis_rx_tdata[22]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[23] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[23]),
        .Q(m_axis_rx_tdata[23]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[24] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[24]),
        .Q(m_axis_rx_tdata[24]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[25] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[25]),
        .Q(m_axis_rx_tdata[25]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[26] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[26]),
        .Q(m_axis_rx_tdata[26]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[27] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[27]),
        .Q(m_axis_rx_tdata[27]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[28] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[28]),
        .Q(m_axis_rx_tdata[28]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[29] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[29]),
        .Q(m_axis_rx_tdata[29]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[2] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(m_axis_rx_tdata[2]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[30] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[30]),
        .Q(m_axis_rx_tdata[30]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[31] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[31]),
        .Q(m_axis_rx_tdata[31]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[32] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[32]),
        .Q(m_axis_rx_tdata[32]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[33] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[33]),
        .Q(m_axis_rx_tdata[33]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[34] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[34]),
        .Q(m_axis_rx_tdata[34]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[35] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[35]),
        .Q(m_axis_rx_tdata[35]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[36] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[36]),
        .Q(m_axis_rx_tdata[36]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[37] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[37]),
        .Q(m_axis_rx_tdata[37]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[38] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[38]),
        .Q(m_axis_rx_tdata[38]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[39] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[39]),
        .Q(m_axis_rx_tdata[39]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[3] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(m_axis_rx_tdata[3]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[40] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[40]),
        .Q(m_axis_rx_tdata[40]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[41] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[41]),
        .Q(m_axis_rx_tdata[41]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[42] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[42]),
        .Q(m_axis_rx_tdata[42]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[43] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[43]),
        .Q(m_axis_rx_tdata[43]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[44] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[44]),
        .Q(m_axis_rx_tdata[44]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[45] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[45]),
        .Q(m_axis_rx_tdata[45]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[46] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[46]),
        .Q(m_axis_rx_tdata[46]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[47] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[47]),
        .Q(m_axis_rx_tdata[47]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[48] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[48]),
        .Q(m_axis_rx_tdata[48]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[49] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[49]),
        .Q(m_axis_rx_tdata[49]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[4] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(m_axis_rx_tdata[4]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[50] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[50]),
        .Q(m_axis_rx_tdata[50]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[51] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[51]),
        .Q(m_axis_rx_tdata[51]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[52] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[52]),
        .Q(m_axis_rx_tdata[52]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[53] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[53]),
        .Q(m_axis_rx_tdata[53]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[54] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[54]),
        .Q(m_axis_rx_tdata[54]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[55] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[55]),
        .Q(m_axis_rx_tdata[55]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[56] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[56]),
        .Q(m_axis_rx_tdata[56]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[57] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[57]),
        .Q(m_axis_rx_tdata[57]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[58] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[58]),
        .Q(m_axis_rx_tdata[58]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[59] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[59]),
        .Q(m_axis_rx_tdata[59]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[5] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(m_axis_rx_tdata[5]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[60] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[60]),
        .Q(m_axis_rx_tdata[60]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[61] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[61]),
        .Q(m_axis_rx_tdata[61]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[62] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[62]),
        .Q(m_axis_rx_tdata[62]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[63] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[63]),
        .Q(m_axis_rx_tdata[63]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[6] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(m_axis_rx_tdata[6]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[7] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(m_axis_rx_tdata[7]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[8] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[8]),
        .Q(m_axis_rx_tdata[8]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tdata_xhdl0_reg[9] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(p_1_in[9]),
        .Q(m_axis_rx_tdata[9]),
        .R(user_reset_out_reg));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tuser_xhdl1[0]_i_1 
       (.I0(trn_recrc_err_prev),
        .I1(data_prev),
        .I2(trn_recrc_err),
        .O(\m_axis_rx_tuser_xhdl1[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0F002222)) 
    \m_axis_rx_tuser_xhdl1[14]_i_1 
       (.I0(trn_rsof),
        .I1(trn_rsrc_dsc),
        .I2(trn_rsrc_dsc_prev),
        .I3(trn_rsof_prev),
        .I4(data_prev),
        .O(\m_axis_rx_tuser_xhdl1[14]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tuser_xhdl1[1]_i_1 
       (.I0(trn_rerrfwd_prev),
        .I1(data_prev),
        .I2(trn_rerrfwd),
        .O(\m_axis_rx_tuser_xhdl1[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFD0)) 
    \m_axis_rx_tuser_xhdl1[20]_i_1 
       (.I0(m_axis_rx_tvalid),
        .I1(m_axis_rx_tready),
        .I2(null_mux_sel),
        .I3(user_reset_out_reg),
        .O(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hEF)) 
    \m_axis_rx_tuser_xhdl1[21]_i_1 
       (.I0(user_reset_out_reg),
        .I1(m_axis_rx_tready),
        .I2(m_axis_rx_tvalid),
        .O(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \m_axis_rx_tuser_xhdl1[21]_i_3 
       (.I0(trn_reof),
        .I1(data_prev),
        .I2(is_eof_prev[4]),
        .I3(null_mux_sel),
        .O(\m_axis_rx_tuser_xhdl1_reg[21]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tuser_xhdl1[2]_i_1 
       (.I0(trn_rbar_hit_prev[0]),
        .I1(data_prev),
        .I2(trn_rbar_hit[0]),
        .O(\m_axis_rx_tuser_xhdl1[2]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tuser_xhdl1[3]_i_1 
       (.I0(trn_rbar_hit_prev[1]),
        .I1(data_prev),
        .I2(trn_rbar_hit[1]),
        .O(\m_axis_rx_tuser_xhdl1[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tuser_xhdl1[4]_i_1 
       (.I0(trn_rbar_hit_prev[2]),
        .I1(data_prev),
        .I2(trn_rbar_hit[2]),
        .O(\m_axis_rx_tuser_xhdl1[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tuser_xhdl1[5]_i_1 
       (.I0(trn_rbar_hit_prev[3]),
        .I1(data_prev),
        .I2(trn_rbar_hit[3]),
        .O(\m_axis_rx_tuser_xhdl1[5]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tuser_xhdl1[6]_i_1 
       (.I0(trn_rbar_hit_prev[4]),
        .I1(data_prev),
        .I2(trn_rbar_hit[4]),
        .O(\m_axis_rx_tuser_xhdl1[6]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tuser_xhdl1[7]_i_1 
       (.I0(trn_rbar_hit_prev[5]),
        .I1(data_prev),
        .I2(trn_rbar_hit[5]),
        .O(\m_axis_rx_tuser_xhdl1[7]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axis_rx_tuser_xhdl1[8]_i_1 
       (.I0(trn_rbar_hit_prev[6]),
        .I1(data_prev),
        .I2(trn_rbar_hit[6]),
        .O(\m_axis_rx_tuser_xhdl1[8]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[0] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser_xhdl1[0]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[0]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[10] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(1'b0),
        .Q(m_axis_rx_tuser[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[11] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(1'b0),
        .Q(m_axis_rx_tuser[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[12] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(1'b0),
        .Q(m_axis_rx_tuser[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[13] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(1'b0),
        .Q(m_axis_rx_tuser[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[14] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser_xhdl1[14]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[14]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[15] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(1'b0),
        .Q(m_axis_rx_tuser[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[16] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(1'b0),
        .Q(m_axis_rx_tuser[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[17] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(1'b1),
        .Q(m_axis_rx_tuser[17]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[18] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(1'b1),
        .Q(m_axis_rx_tuser[18]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[19] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(null_mux_sel_reg_2),
        .Q(m_axis_rx_tuser[19]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[1] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser_xhdl1[1]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[1]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[20] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(1'b0),
        .Q(m_axis_rx_tuser[20]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[21] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(data_prev_reg_1),
        .Q(m_axis_rx_tuser[21]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[2] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser_xhdl1[2]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[2]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[3] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser_xhdl1[3]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[3]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[4] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser_xhdl1[4]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[4]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[5] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser_xhdl1[5]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[5]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[6] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser_xhdl1[6]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[6]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[7] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser_xhdl1[7]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[7]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[8] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(\m_axis_rx_tuser_xhdl1[8]_i_1_n_0 ),
        .Q(m_axis_rx_tuser[8]),
        .R(\m_axis_rx_tuser_xhdl1[20]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \m_axis_rx_tuser_xhdl1_reg[9] 
       (.C(user_clk),
        .CE(\m_axis_rx_tuser_xhdl1[21]_i_1_n_0 ),
        .D(1'b0),
        .Q(m_axis_rx_tuser[9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFE2)) 
    m_axis_rx_tvalid_xhdl2_i_1
       (.I0(rsrc_rdy_filtered10_out),
        .I1(data_prev),
        .I2(trn_rsrc_rdy_prev),
        .I3(null_mux_sel),
        .I4(reg_dsc_detect_reg_n_0),
        .I5(m_axis_rx_tvalid_xhdl2_i_2_n_0),
        .O(m_axis_rx_tvalid_xhdl2_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000002020200020)) 
    m_axis_rx_tvalid_xhdl2_i_2
       (.I0(trn_in_packet_reg_0),
        .I1(trn_rsrc_dsc_d),
        .I2(trn_rsrc_dsc),
        .I3(trn_rsof),
        .I4(trn_reof),
        .I5(E),
        .O(m_axis_rx_tvalid_xhdl2_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    m_axis_rx_tvalid_xhdl2_reg
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(m_axis_rx_tvalid_xhdl2_i_1_n_0),
        .Q(m_axis_rx_tvalid),
        .R(user_reset_out_reg));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT4 #(
    .INIT(16'h7888)) 
    new_pkt_len_1_inferred_i_1
       (.I0(m_axis_rx_tdata[4]),
        .I1(m_axis_rx_tdata[30]),
        .I2(new_pkt_len_1_inferred_i_6_n_0),
        .I3(m_axis_rx_tdata[3]),
        .O(in0[4]));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    new_pkt_len_1_inferred_i_2
       (.I0(new_pkt_len_1_inferred_i_6_n_0),
        .I1(m_axis_rx_tdata[3]),
        .I2(m_axis_rx_tdata[30]),
        .O(in0[3]));
  LUT6 #(
    .INIT(64'h0444444CC8888880)) 
    new_pkt_len_1_inferred_i_3
       (.I0(m_axis_rx_tdata[1]),
        .I1(m_axis_rx_tdata[30]),
        .I2(m_axis_rx_tdata[0]),
        .I3(m_axis_rx_tdata[15]),
        .I4(m_axis_rx_tdata[29]),
        .I5(m_axis_rx_tdata[2]),
        .O(in0[2]));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT5 #(
    .INIT(32'hB73F3F48)) 
    new_pkt_len_1_inferred_i_4
       (.I0(m_axis_rx_tdata[0]),
        .I1(m_axis_rx_tdata[30]),
        .I2(m_axis_rx_tdata[1]),
        .I3(m_axis_rx_tdata[29]),
        .I4(m_axis_rx_tdata[15]),
        .O(in0[1]));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT4 #(
    .INIT(16'h7887)) 
    new_pkt_len_1_inferred_i_5
       (.I0(m_axis_rx_tdata[30]),
        .I1(m_axis_rx_tdata[0]),
        .I2(m_axis_rx_tdata[15]),
        .I3(m_axis_rx_tdata[29]),
        .O(in0[0]));
  LUT6 #(
    .INIT(64'hFE80000000000000)) 
    new_pkt_len_1_inferred_i_6
       (.I0(m_axis_rx_tdata[29]),
        .I1(m_axis_rx_tdata[15]),
        .I2(m_axis_rx_tdata[0]),
        .I3(m_axis_rx_tdata[1]),
        .I4(m_axis_rx_tdata[2]),
        .I5(m_axis_rx_tdata[30]),
        .O(new_pkt_len_1_inferred_i_6_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    new_pkt_len_inferred_i_1
       (.I0(m_axis_rx_tdata[30]),
        .I1(m_axis_rx_tdata[9]),
        .O(\reg_pkt_len_counter_reg[9] [4]));
  LUT2 #(
    .INIT(4'h8)) 
    new_pkt_len_inferred_i_2
       (.I0(m_axis_rx_tdata[30]),
        .I1(m_axis_rx_tdata[8]),
        .O(\reg_pkt_len_counter_reg[9] [3]));
  LUT2 #(
    .INIT(4'h8)) 
    new_pkt_len_inferred_i_3
       (.I0(m_axis_rx_tdata[30]),
        .I1(m_axis_rx_tdata[7]),
        .O(\reg_pkt_len_counter_reg[9] [2]));
  LUT2 #(
    .INIT(4'h8)) 
    new_pkt_len_inferred_i_4
       (.I0(m_axis_rx_tdata[30]),
        .I1(m_axis_rx_tdata[6]),
        .O(\reg_pkt_len_counter_reg[9] [1]));
  LUT2 #(
    .INIT(4'h8)) 
    new_pkt_len_inferred_i_5
       (.I0(m_axis_rx_tdata[30]),
        .I1(m_axis_rx_tdata[5]),
        .O(\reg_pkt_len_counter_reg[9] [0]));
  LUT6 #(
    .INIT(64'hAABAAABAAABABBBB)) 
    null_mux_sel_i_3
       (.I0(user_reset_out_reg),
        .I1(null_mux_sel),
        .I2(m_axis_rx_tvalid),
        .I3(m_axis_rx_tready),
        .I4(reg_dsc_detect_reg_n_0),
        .I5(m_axis_rx_tvalid_xhdl2_i_2_n_0),
        .O(null_mux_sel_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    null_mux_sel_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(\reg_pkt_len_counter_reg[0] ),
        .Q(null_mux_sel),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000040FF00004040)) 
    reg_dsc_detect_i_1
       (.I0(trn_rdst_rdy_xhdl4_reg_1),
        .I1(trn_rsrc_dsc),
        .I2(reg_dsc_detect_i_3_n_0),
        .I3(null_mux_sel),
        .I4(user_reset_out_reg),
        .I5(reg_dsc_detect_reg_n_0),
        .O(reg_dsc_detect_i_1_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    reg_dsc_detect_i_3
       (.I0(trn_in_packet_reg_0),
        .I1(trn_rsrc_dsc_d),
        .O(reg_dsc_detect_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    reg_dsc_detect_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(reg_dsc_detect_i_1_n_0),
        .Q(reg_dsc_detect_reg_n_0),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    \reg_tkeep[7]_i_2 
       (.I0(is_eof_prev[2]),
        .I1(data_prev),
        .I2(trn_rrem),
        .O(\m_axis_rx_tuser_xhdl1_reg[19]_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \reg_tkeep_reg[0] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(1'b1),
        .Q(m_axis_rx_tkeep[0]),
        .S(user_reset_out_reg));
  FDSE #(
    .INIT(1'b0)) 
    \reg_tkeep_reg[1] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(1'b1),
        .Q(m_axis_rx_tkeep[1]),
        .S(user_reset_out_reg));
  FDSE #(
    .INIT(1'b0)) 
    \reg_tkeep_reg[2] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(1'b1),
        .Q(m_axis_rx_tkeep[2]),
        .S(user_reset_out_reg));
  FDSE #(
    .INIT(1'b0)) 
    \reg_tkeep_reg[3] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(1'b1),
        .Q(m_axis_rx_tkeep[3]),
        .S(user_reset_out_reg));
  FDSE #(
    .INIT(1'b0)) 
    \reg_tkeep_reg[4] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(D[0]),
        .Q(m_axis_rx_tkeep[4]),
        .S(user_reset_out_reg));
  FDSE #(
    .INIT(1'b0)) 
    \reg_tkeep_reg[5] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(D[1]),
        .Q(m_axis_rx_tkeep[5]),
        .S(user_reset_out_reg));
  FDSE #(
    .INIT(1'b0)) 
    \reg_tkeep_reg[6] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(D[2]),
        .Q(m_axis_rx_tkeep[6]),
        .S(user_reset_out_reg));
  FDSE #(
    .INIT(1'b0)) 
    \reg_tkeep_reg[7] 
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(D[3]),
        .Q(m_axis_rx_tkeep[7]),
        .S(user_reset_out_reg));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    reg_tlast_i_2
       (.I0(trn_reof),
        .I1(data_prev),
        .I2(is_eof_prev[4]),
        .I3(null_mux_sel),
        .O(reg_tlast_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    reg_tlast_reg
       (.C(user_clk),
        .CE(\m_axis_rx_tdata_xhdl0[63]_i_1_n_0 ),
        .D(data_prev_reg_0),
        .Q(m_axis_rx_tlast),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    trn_in_packet_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(user_reset_out_reg_0),
        .Q(trn_in_packet_reg_0),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rbar_hit_prev_reg[0] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rbar_hit[0]),
        .Q(trn_rbar_hit_prev[0]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rbar_hit_prev_reg[1] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rbar_hit[1]),
        .Q(trn_rbar_hit_prev[1]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rbar_hit_prev_reg[2] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rbar_hit[2]),
        .Q(trn_rbar_hit_prev[2]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rbar_hit_prev_reg[3] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rbar_hit[3]),
        .Q(trn_rbar_hit_prev[3]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rbar_hit_prev_reg[4] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rbar_hit[4]),
        .Q(trn_rbar_hit_prev[4]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rbar_hit_prev_reg[5] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rbar_hit[5]),
        .Q(trn_rbar_hit_prev[5]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rbar_hit_prev_reg[6] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rbar_hit[6]),
        .Q(trn_rbar_hit_prev[6]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[0] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[32]),
        .Q(trn_rd_prev[0]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[10] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[42]),
        .Q(trn_rd_prev[10]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[11] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[43]),
        .Q(trn_rd_prev[11]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[12] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[44]),
        .Q(trn_rd_prev[12]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[13] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[45]),
        .Q(trn_rd_prev[13]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[14] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[46]),
        .Q(trn_rd_prev[14]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[15] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[47]),
        .Q(trn_rd_prev[15]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[16] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[48]),
        .Q(trn_rd_prev[16]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[17] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[49]),
        .Q(trn_rd_prev[17]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[18] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[50]),
        .Q(trn_rd_prev[18]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[19] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[51]),
        .Q(trn_rd_prev[19]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[1] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[33]),
        .Q(trn_rd_prev[1]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[20] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[52]),
        .Q(trn_rd_prev[20]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[21] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[53]),
        .Q(trn_rd_prev[21]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[22] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[54]),
        .Q(trn_rd_prev[22]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[23] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[55]),
        .Q(trn_rd_prev[23]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[24] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[56]),
        .Q(trn_rd_prev[24]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[25] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[57]),
        .Q(trn_rd_prev[25]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[26] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[58]),
        .Q(trn_rd_prev[26]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[27] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[59]),
        .Q(trn_rd_prev[27]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[28] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[60]),
        .Q(trn_rd_prev[28]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[29] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[61]),
        .Q(trn_rd_prev[29]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[2] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[34]),
        .Q(trn_rd_prev[2]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[30] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[62]),
        .Q(trn_rd_prev[30]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[31] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[63]),
        .Q(trn_rd_prev[31]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[32] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[0]),
        .Q(trn_rd_prev[32]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[33] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[1]),
        .Q(trn_rd_prev[33]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[34] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[2]),
        .Q(trn_rd_prev[34]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[35] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[3]),
        .Q(trn_rd_prev[35]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[36] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[4]),
        .Q(trn_rd_prev[36]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[37] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[5]),
        .Q(trn_rd_prev[37]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[38] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[6]),
        .Q(trn_rd_prev[38]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[39] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[7]),
        .Q(trn_rd_prev[39]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[3] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[35]),
        .Q(trn_rd_prev[3]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[40] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[8]),
        .Q(trn_rd_prev[40]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[41] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[9]),
        .Q(trn_rd_prev[41]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[42] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[10]),
        .Q(trn_rd_prev[42]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[43] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[11]),
        .Q(trn_rd_prev[43]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[44] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[12]),
        .Q(trn_rd_prev[44]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[45] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[13]),
        .Q(trn_rd_prev[45]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[46] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[14]),
        .Q(trn_rd_prev[46]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[47] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[15]),
        .Q(trn_rd_prev[47]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[48] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[16]),
        .Q(trn_rd_prev[48]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[49] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[17]),
        .Q(trn_rd_prev[49]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[4] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[36]),
        .Q(trn_rd_prev[4]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[50] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[18]),
        .Q(trn_rd_prev[50]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[51] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[19]),
        .Q(trn_rd_prev[51]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[52] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[20]),
        .Q(trn_rd_prev[52]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[53] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[21]),
        .Q(trn_rd_prev[53]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[54] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[22]),
        .Q(trn_rd_prev[54]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[55] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[23]),
        .Q(trn_rd_prev[55]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[56] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[24]),
        .Q(trn_rd_prev[56]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[57] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[25]),
        .Q(trn_rd_prev[57]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[58] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[26]),
        .Q(trn_rd_prev[58]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[59] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[27]),
        .Q(trn_rd_prev[59]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[5] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[37]),
        .Q(trn_rd_prev[5]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[60] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[28]),
        .Q(trn_rd_prev[60]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[61] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[29]),
        .Q(trn_rd_prev[61]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[62] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[30]),
        .Q(trn_rd_prev[62]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[63] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[31]),
        .Q(trn_rd_prev[63]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[6] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[38]),
        .Q(trn_rd_prev[6]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[7] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[39]),
        .Q(trn_rd_prev[7]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[8] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[40]),
        .Q(trn_rd_prev[8]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rd_prev_reg[9] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rd[41]),
        .Q(trn_rd_prev[9]),
        .R(user_reset_out_reg));
  LUT6 #(
    .INIT(64'h00000E0000000EEE)) 
    trn_rdst_rdy_xhdl4_i_2
       (.I0(trn_rdst_rdy_xhdl4_reg_1),
        .I1(trn_rdst_rdy_xhdl4_i_4_n_0),
        .I2(null_mux_sel),
        .I3(m_axis_rx_tready),
        .I4(reg_dsc_detect_reg_n_0),
        .I5(m_axis_rx_tvalid),
        .O(trn_rdst_rdy_xhdl4_reg_0));
  LUT3 #(
    .INIT(8'hDF)) 
    trn_rdst_rdy_xhdl4_i_4
       (.I0(trn_rsrc_dsc),
        .I1(trn_rsrc_dsc_d),
        .I2(trn_in_packet_reg_0),
        .O(trn_rdst_rdy_xhdl4_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    trn_rdst_rdy_xhdl4_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(null_mux_sel_reg_1),
        .Q(E),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    trn_recrc_err_prev_reg
       (.C(user_clk),
        .CE(E),
        .D(trn_recrc_err),
        .Q(trn_recrc_err_prev),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    trn_reof_prev_reg
       (.C(user_clk),
        .CE(E),
        .D(trn_reof),
        .Q(is_eof_prev[4]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    trn_rerrfwd_prev_reg
       (.C(user_clk),
        .CE(E),
        .D(trn_rerrfwd),
        .Q(trn_rerrfwd_prev),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \trn_rrem_prev_reg[0] 
       (.C(user_clk),
        .CE(E),
        .D(trn_rrem),
        .Q(is_eof_prev[2]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    trn_rsof_prev_reg
       (.C(user_clk),
        .CE(E),
        .D(trn_rsof),
        .Q(trn_rsof_prev),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    trn_rsrc_dsc_d_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(trn_rsrc_dsc),
        .Q(trn_rsrc_dsc_d),
        .R(user_reset_out_reg));
  LUT2 #(
    .INIT(4'hE)) 
    trn_rsrc_dsc_prev_i_1
       (.I0(reg_dsc_detect_reg_n_0),
        .I1(trn_rsrc_dsc),
        .O(trn_rsrc_dsc_prev0));
  FDRE #(
    .INIT(1'b0)) 
    trn_rsrc_dsc_prev_reg
       (.C(user_clk),
        .CE(E),
        .D(trn_rsrc_dsc_prev0),
        .Q(trn_rsrc_dsc_prev),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    trn_rsrc_rdy_prev_reg
       (.C(user_clk),
        .CE(E),
        .D(rsrc_rdy_filtered10_out),
        .Q(trn_rsrc_rdy_prev),
        .R(user_reset_out_reg));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_axi_basic_top" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_top
   (trn_rdst_rdy,
    m_axis_rx_tvalid,
    m_axis_rx_tlast,
    trn_teof,
    trn_tsrc_rdy,
    trn_trem,
    s_axis_tx_tready,
    trn_in_packet_reg,
    tbuf_av_gap_thrtl_reg,
    tbuf_av_gap_thrtl_reg_0,
    trn_tcfg_gnt,
    m_axis_rx_tuser,
    cfg_pm_turnoff_ok_n,
    trn_tsof,
    m_axis_rx_tdata,
    m_axis_rx_tkeep,
    Q,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    user_reset_out_reg,
    trn_rsrc_dsc,
    user_clk,
    rsrc_rdy_filtered10_out,
    trn_rrem,
    trn_reof,
    trn_rsof,
    trn_recrc_err,
    trn_rerrfwd,
    s_axis_tx_tlast,
    s_axis_tx_tvalid,
    s_axis_tx_tkeep,
    tx_cfg_gnt,
    trn_tcfg_req,
    trn_tdst_rdy,
    cfg_turnoff_ok,
    tbuf_av_min_trig,
    user_reset_out_reg_0,
    m_axis_rx_tready,
    trn_rdst_rdy_xhdl4_reg,
    s_axis_tx_tuser,
    s_axis_tx_tdata,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg ,
    user_lnk_up_int_reg,
    cfg_pcie_link_state,
    user_reset_out_reg_1,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \tcfg_req_cnt_reg[1] ,
    trn_rbar_hit,
    trn_rd,
    trn_tbuf_av,
    cfg_to_turnoff);
  output trn_rdst_rdy;
  output m_axis_rx_tvalid;
  output m_axis_rx_tlast;
  output trn_teof;
  output trn_tsrc_rdy;
  output [0:0]trn_trem;
  output s_axis_tx_tready;
  output trn_in_packet_reg;
  output tbuf_av_gap_thrtl_reg;
  output tbuf_av_gap_thrtl_reg_0;
  output trn_tcfg_gnt;
  output [21:0]m_axis_rx_tuser;
  output cfg_pm_turnoff_ok_n;
  output trn_tsof;
  output [63:0]m_axis_rx_tdata;
  output [7:0]m_axis_rx_tkeep;
  output [63:0]Q;
  output [3:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  input user_reset_out_reg;
  input trn_rsrc_dsc;
  input user_clk;
  input rsrc_rdy_filtered10_out;
  input [0:0]trn_rrem;
  input trn_reof;
  input trn_rsof;
  input trn_recrc_err;
  input trn_rerrfwd;
  input s_axis_tx_tlast;
  input s_axis_tx_tvalid;
  input [0:0]s_axis_tx_tkeep;
  input tx_cfg_gnt;
  input trn_tcfg_req;
  input trn_tdst_rdy;
  input cfg_turnoff_ok;
  input tbuf_av_min_trig;
  input user_reset_out_reg_0;
  input m_axis_rx_tready;
  input trn_rdst_rdy_xhdl4_reg;
  input [3:0]s_axis_tx_tuser;
  input [63:0]s_axis_tx_tdata;
  input \pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  input user_lnk_up_int_reg;
  input [2:0]cfg_pcie_link_state;
  input user_reset_out_reg_1;
  input \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input \tcfg_req_cnt_reg[1] ;
  input [6:0]trn_rbar_hit;
  input [63:0]trn_rd;
  input [5:0]trn_tbuf_av;
  input cfg_to_turnoff;

  wire [63:0]Q;
  wire [2:0]cfg_pcie_link_state;
  wire cfg_pm_turnoff_ok_n;
  wire cfg_to_turnoff;
  wire cfg_turnoff_ok;
  wire [63:0]m_axis_rx_tdata;
  wire [7:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [21:0]m_axis_rx_tuser;
  wire m_axis_rx_tvalid;
  wire \pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [3:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire rsrc_rdy_filtered10_out;
  wire [63:0]s_axis_tx_tdata;
  wire [0:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tready;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire tbuf_av_gap_thrtl_reg;
  wire tbuf_av_gap_thrtl_reg_0;
  wire tbuf_av_min_trig;
  wire \tcfg_req_cnt_reg[1] ;
  wire trn_in_packet_reg;
  wire [6:0]trn_rbar_hit;
  wire [63:0]trn_rd;
  wire trn_rdst_rdy;
  wire trn_rdst_rdy_xhdl4_reg;
  wire trn_recrc_err;
  wire trn_reof;
  wire trn_rerrfwd;
  wire [0:0]trn_rrem;
  wire trn_rsof;
  wire trn_rsrc_dsc;
  wire [5:0]trn_tbuf_av;
  wire trn_tcfg_gnt;
  wire trn_tcfg_req;
  wire trn_tdst_rdy;
  wire trn_teof;
  wire [0:0]trn_trem;
  wire trn_tsof;
  wire trn_tsrc_rdy;
  wire tx_cfg_gnt;
  wire user_clk;
  wire user_lnk_up_int_reg;
  wire user_reset_out_reg;
  wire user_reset_out_reg_0;
  wire user_reset_out_reg_1;

  PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_rx rx_inst
       (.E(trn_rdst_rdy),
        .m_axis_rx_tdata(m_axis_rx_tdata),
        .m_axis_rx_tkeep(m_axis_rx_tkeep),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser),
        .m_axis_rx_tvalid(m_axis_rx_tvalid),
        .rsrc_rdy_filtered10_out(rsrc_rdy_filtered10_out),
        .trn_in_packet_reg(trn_in_packet_reg),
        .trn_rbar_hit(trn_rbar_hit),
        .trn_rd(trn_rd),
        .trn_rdst_rdy_xhdl4_reg(trn_rdst_rdy_xhdl4_reg),
        .trn_recrc_err(trn_recrc_err),
        .trn_reof(trn_reof),
        .trn_rerrfwd(trn_rerrfwd),
        .trn_rrem(trn_rrem),
        .trn_rsof(trn_rsof),
        .trn_rsrc_dsc(trn_rsrc_dsc),
        .user_clk(user_clk),
        .user_reset_out_reg(user_reset_out_reg),
        .user_reset_out_reg_0(user_reset_out_reg_0));
  PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx tx_inst
       (.Q(Q),
        .cfg_pcie_link_state(cfg_pcie_link_state),
        .cfg_pm_turnoff_ok_n(cfg_pm_turnoff_ok_n),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl ),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tready(s_axis_tx_tready),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .tbuf_av_gap_thrtl_reg(tbuf_av_gap_thrtl_reg),
        .tbuf_av_gap_thrtl_reg_0(tbuf_av_gap_thrtl_reg_0),
        .tbuf_av_min_trig(tbuf_av_min_trig),
        .\tcfg_req_cnt_reg[1] (\tcfg_req_cnt_reg[1] ),
        .trn_tbuf_av(trn_tbuf_av),
        .trn_tcfg_gnt(trn_tcfg_gnt),
        .trn_tcfg_req(trn_tcfg_req),
        .trn_tdst_rdy(trn_tdst_rdy),
        .trn_teof(trn_teof),
        .trn_trem(trn_trem),
        .trn_tsof(trn_tsof),
        .trn_tsrc_rdy(trn_tsrc_rdy),
        .tx_cfg_gnt(tx_cfg_gnt),
        .user_clk(user_clk),
        .user_lnk_up_int_reg(user_lnk_up_int_reg),
        .user_reset_out_reg(user_reset_out_reg),
        .user_reset_out_reg_0(user_reset_out_reg_1));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_axi_basic_tx" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx
   (trn_teof,
    trn_tsrc_rdy,
    trn_trem,
    s_axis_tx_tready,
    tbuf_av_gap_thrtl_reg,
    tbuf_av_gap_thrtl_reg_0,
    trn_tcfg_gnt,
    cfg_pm_turnoff_ok_n,
    trn_tsof,
    Q,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    user_reset_out_reg,
    s_axis_tx_tlast,
    user_clk,
    s_axis_tx_tvalid,
    s_axis_tx_tkeep,
    tx_cfg_gnt,
    trn_tcfg_req,
    trn_tdst_rdy,
    cfg_turnoff_ok,
    tbuf_av_min_trig,
    s_axis_tx_tuser,
    s_axis_tx_tdata,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg ,
    user_lnk_up_int_reg,
    cfg_pcie_link_state,
    user_reset_out_reg_0,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \tcfg_req_cnt_reg[1] ,
    trn_tbuf_av,
    cfg_to_turnoff);
  output trn_teof;
  output trn_tsrc_rdy;
  output [0:0]trn_trem;
  output s_axis_tx_tready;
  output tbuf_av_gap_thrtl_reg;
  output tbuf_av_gap_thrtl_reg_0;
  output trn_tcfg_gnt;
  output cfg_pm_turnoff_ok_n;
  output trn_tsof;
  output [63:0]Q;
  output [3:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  input user_reset_out_reg;
  input s_axis_tx_tlast;
  input user_clk;
  input s_axis_tx_tvalid;
  input [0:0]s_axis_tx_tkeep;
  input tx_cfg_gnt;
  input trn_tcfg_req;
  input trn_tdst_rdy;
  input cfg_turnoff_ok;
  input tbuf_av_min_trig;
  input [3:0]s_axis_tx_tuser;
  input [63:0]s_axis_tx_tdata;
  input \pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  input user_lnk_up_int_reg;
  input [2:0]cfg_pcie_link_state;
  input user_reset_out_reg_0;
  input \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input \tcfg_req_cnt_reg[1] ;
  input [5:0]trn_tbuf_av;
  input cfg_to_turnoff;

  wire [63:0]Q;
  wire [2:0]cfg_pcie_link_state;
  wire cfg_pm_turnoff_ok_n;
  wire cfg_to_turnoff;
  wire cfg_turnoff_ok;
  wire p_5_out;
  wire \pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [3:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [63:0]s_axis_tx_tdata;
  wire [0:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tready;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire tbuf_av_gap_thrtl_reg;
  wire tbuf_av_gap_thrtl_reg_0;
  wire tbuf_av_min_trig;
  wire \tcfg_req_cnt_reg[1] ;
  wire [5:0]trn_tbuf_av;
  wire trn_tcfg_gnt;
  wire trn_tcfg_req;
  wire trn_tdst_rdy;
  wire trn_teof;
  wire [0:0]trn_trem;
  wire trn_tsof;
  wire trn_tsrc_rdy;
  wire tx_cfg_gnt;
  wire tx_pipeline_inst_n_3;
  wire tx_pipeline_inst_n_4;
  wire user_clk;
  wire user_lnk_up_int_reg;
  wire user_reset_out_reg;
  wire user_reset_out_reg_0;
  wire \xhdl12.tx_thrl_ctl_inst_n_1 ;
  wire \xhdl12.tx_thrl_ctl_inst_n_4 ;

  PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_pipeline tx_pipeline_inst
       (.Q(Q),
        .\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0 (tx_pipeline_inst_n_3),
        .\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_1 (tx_pipeline_inst_n_4),
        .p_5_out(p_5_out),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl ),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .tready_thrtl_xhdl1_reg(\xhdl12.tx_thrl_ctl_inst_n_1 ),
        .trn_tdst_rdy(trn_tdst_rdy),
        .trn_teof(trn_teof),
        .trn_trem(trn_trem),
        .trn_tsof(trn_tsof),
        .trn_tsrc_rdy(trn_tsrc_rdy),
        .user_clk(user_clk),
        .user_lnk_up_int_reg(user_lnk_up_int_reg),
        .user_reset_out_reg(user_reset_out_reg),
        .user_reset_out_reg_0(\xhdl12.tx_thrl_ctl_inst_n_4 ));
  PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_thrtl_ctl \xhdl12.tx_thrl_ctl_inst 
       (.\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg (tx_pipeline_inst_n_4),
        .axi_in_packet_reg(\xhdl12.tx_thrl_ctl_inst_n_4 ),
        .axi_in_packet_reg_0(tx_pipeline_inst_n_3),
        .cfg_pcie_link_state(cfg_pcie_link_state),
        .cfg_pm_turnoff_ok_n(cfg_pm_turnoff_ok_n),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .p_5_out(p_5_out),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ),
        .s_axis_tx_tdata({s_axis_tx_tdata[30:29],s_axis_tx_tdata[15],s_axis_tx_tdata[0]}),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tready(s_axis_tx_tready),
        .s_axis_tx_tuser(s_axis_tx_tuser[0]),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .tbuf_av_gap_thrtl_reg_0(tbuf_av_gap_thrtl_reg),
        .tbuf_av_gap_thrtl_reg_1(tbuf_av_gap_thrtl_reg_0),
        .tbuf_av_min_trig(tbuf_av_min_trig),
        .\tcfg_req_cnt_reg[1]_0 (\tcfg_req_cnt_reg[1] ),
        .tready_thrtl_xhdl1_reg_0(\xhdl12.tx_thrl_ctl_inst_n_1 ),
        .trn_tbuf_av(trn_tbuf_av),
        .trn_tcfg_gnt(trn_tcfg_gnt),
        .trn_tcfg_req(trn_tcfg_req),
        .trn_tdst_rdy(trn_tdst_rdy),
        .tx_cfg_gnt(tx_cfg_gnt),
        .user_clk(user_clk),
        .user_lnk_up_int_reg(user_lnk_up_int_reg),
        .user_reset_out_reg(user_reset_out_reg),
        .user_reset_out_reg_0(user_reset_out_reg_0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_axi_basic_tx_pipeline" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_pipeline
   (trn_teof,
    trn_tsrc_rdy,
    trn_trem,
    \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0 ,
    \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_1 ,
    trn_tsof,
    Q,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    user_reset_out_reg,
    s_axis_tx_tlast,
    user_clk,
    p_5_out,
    s_axis_tx_tvalid,
    s_axis_tx_tkeep,
    user_reset_out_reg_0,
    tready_thrtl_xhdl1_reg,
    user_lnk_up_int_reg,
    trn_tdst_rdy,
    s_axis_tx_tdata,
    s_axis_tx_tuser);
  output trn_teof;
  output trn_tsrc_rdy;
  output [0:0]trn_trem;
  output \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0 ;
  output \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_1 ;
  output trn_tsof;
  output [63:0]Q;
  output [3:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  input user_reset_out_reg;
  input s_axis_tx_tlast;
  input user_clk;
  input p_5_out;
  input s_axis_tx_tvalid;
  input [0:0]s_axis_tx_tkeep;
  input user_reset_out_reg_0;
  input tready_thrtl_xhdl1_reg;
  input user_lnk_up_int_reg;
  input trn_tdst_rdy;
  input [63:0]s_axis_tx_tdata;
  input [3:0]s_axis_tx_tuser;

  wire [63:0]Q;
  wire \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1_n_0 ;
  wire \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0 ;
  wire \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_1 ;
  wire p_5_out;
  wire [3:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire reg_tvalid;
  wire [63:0]s_axis_tx_tdata;
  wire [0:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire tready_thrtl_xhdl1_reg;
  wire trn_in_packet_i_1__0_n_0;
  wire trn_in_packet_i_2__0_n_0;
  wire trn_in_packet_i_3_n_0;
  wire trn_in_packet_reg_n_0;
  wire trn_tdst_rdy;
  wire trn_teof;
  wire [0:0]trn_trem;
  wire trn_tsof;
  wire trn_tsrc_rdy;
  wire user_clk;
  wire user_lnk_up_int_reg;
  wire user_reset_out_reg;
  wire user_reset_out_reg_0;

  LUT5 #(
    .INIT(32'h11110010)) 
    \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1 
       (.I0(user_reset_out_reg),
        .I1(tready_thrtl_xhdl1_reg),
        .I2(\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0 ),
        .I3(user_lnk_up_int_reg),
        .I4(\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_1 ),
        .O(\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1_n_0 ),
        .Q(\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_1 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    axi_in_packet_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(user_reset_out_reg_0),
        .Q(\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0 ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    pcie_block_i_i_31
       (.I0(reg_tvalid),
        .I1(trn_in_packet_reg_n_0),
        .O(trn_tsof));
  LUT5 #(
    .INIT(32'h10DF1010)) 
    trn_in_packet_i_1__0
       (.I0(user_reset_out_reg),
        .I1(trn_in_packet_i_2__0_n_0),
        .I2(trn_tdst_rdy),
        .I3(trn_in_packet_i_3_n_0),
        .I4(trn_in_packet_reg_n_0),
        .O(trn_in_packet_i_1__0_n_0));
  LUT4 #(
    .INIT(16'hFBFF)) 
    trn_in_packet_i_2__0
       (.I0(trn_teof),
        .I1(trn_tsrc_rdy),
        .I2(trn_in_packet_reg_n_0),
        .I3(reg_tvalid),
        .O(trn_in_packet_i_2__0_n_0));
  LUT5 #(
    .INIT(32'hFDDDDDDD)) 
    trn_in_packet_i_3
       (.I0(user_lnk_up_int_reg),
        .I1(user_reset_out_reg),
        .I2(trn_teof),
        .I3(trn_in_packet_reg_n_0),
        .I4(trn_tsrc_rdy),
        .O(trn_in_packet_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    trn_in_packet_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(trn_in_packet_i_1__0_n_0),
        .Q(trn_in_packet_reg_n_0),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[0]),
        .Q(Q[0]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[10] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[10]),
        .Q(Q[10]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[11] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[11]),
        .Q(Q[11]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[12] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[12]),
        .Q(Q[12]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[13] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[13]),
        .Q(Q[13]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[14] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[14]),
        .Q(Q[14]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[15] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[15]),
        .Q(Q[15]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[16] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[16]),
        .Q(Q[16]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[17] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[17]),
        .Q(Q[17]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[18] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[18]),
        .Q(Q[18]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[19] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[19]),
        .Q(Q[19]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[1]),
        .Q(Q[1]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[20] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[20]),
        .Q(Q[20]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[21] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[21]),
        .Q(Q[21]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[22] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[22]),
        .Q(Q[22]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[23] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[23]),
        .Q(Q[23]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[24] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[24]),
        .Q(Q[24]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[25] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[25]),
        .Q(Q[25]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[26] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[26]),
        .Q(Q[26]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[27] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[27]),
        .Q(Q[27]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[28] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[28]),
        .Q(Q[28]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[29] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[29]),
        .Q(Q[29]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[2]),
        .Q(Q[2]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[30] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[30]),
        .Q(Q[30]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[31] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[31]),
        .Q(Q[31]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[32] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[32]),
        .Q(Q[32]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[33] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[33]),
        .Q(Q[33]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[34] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[34]),
        .Q(Q[34]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[35] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[35]),
        .Q(Q[35]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[36] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[36]),
        .Q(Q[36]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[37] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[37]),
        .Q(Q[37]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[38] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[38]),
        .Q(Q[38]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[39] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[39]),
        .Q(Q[39]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[3]),
        .Q(Q[3]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[40] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[40]),
        .Q(Q[40]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[41] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[41]),
        .Q(Q[41]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[42] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[42]),
        .Q(Q[42]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[43] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[43]),
        .Q(Q[43]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[44] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[44]),
        .Q(Q[44]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[45] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[45]),
        .Q(Q[45]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[46] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[46]),
        .Q(Q[46]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[47] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[47]),
        .Q(Q[47]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[48] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[48]),
        .Q(Q[48]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[49] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[49]),
        .Q(Q[49]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[4]),
        .Q(Q[4]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[50] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[50]),
        .Q(Q[50]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[51] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[51]),
        .Q(Q[51]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[52] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[52]),
        .Q(Q[52]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[53] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[53]),
        .Q(Q[53]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[54] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[54]),
        .Q(Q[54]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[55] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[55]),
        .Q(Q[55]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[56] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[56]),
        .Q(Q[56]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[57] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[57]),
        .Q(Q[57]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[58] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[58]),
        .Q(Q[58]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[59] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[59]),
        .Q(Q[59]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[5]),
        .Q(Q[5]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[60] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[60]),
        .Q(Q[60]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[61] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[61]),
        .Q(Q[61]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[62] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[62]),
        .Q(Q[62]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[63] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[63]),
        .Q(Q[63]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[6] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[6]),
        .Q(Q[6]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[7]),
        .Q(Q[7]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[8] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[8]),
        .Q(Q[8]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tdata_reg[9] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tdata[9]),
        .Q(Q[9]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tkeep_reg[7] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tkeep),
        .Q(trn_trem),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tlast_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tlast),
        .Q(trn_teof),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tsrc_rdy_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(p_5_out),
        .Q(trn_tsrc_rdy),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tuser_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tuser[0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [0]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tuser_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tuser[1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [1]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tuser_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tuser[2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [2]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tuser_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tuser[3]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [3]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.reg_tvalid_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(s_axis_tx_tvalid),
        .Q(reg_tvalid),
        .R(user_reset_out_reg));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_axi_basic_tx_thrtl_ctl" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_tx_thrtl_ctl
   (s_axis_tx_tready,
    tready_thrtl_xhdl1_reg_0,
    tbuf_av_gap_thrtl_reg_0,
    tbuf_av_gap_thrtl_reg_1,
    axi_in_packet_reg,
    trn_tcfg_gnt,
    p_5_out,
    cfg_pm_turnoff_ok_n,
    user_reset_out_reg,
    tx_cfg_gnt,
    user_clk,
    trn_tcfg_req,
    trn_tdst_rdy,
    cfg_turnoff_ok,
    tbuf_av_min_trig,
    s_axis_tx_tvalid,
    s_axis_tx_tuser,
    s_axis_tx_tdata,
    s_axis_tx_tlast,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg ,
    user_lnk_up_int_reg,
    cfg_pcie_link_state,
    axi_in_packet_reg_0,
    user_reset_out_reg_0,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \tcfg_req_cnt_reg[1]_0 ,
    \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg ,
    trn_tbuf_av,
    cfg_to_turnoff);
  output s_axis_tx_tready;
  output tready_thrtl_xhdl1_reg_0;
  output tbuf_av_gap_thrtl_reg_0;
  output tbuf_av_gap_thrtl_reg_1;
  output axi_in_packet_reg;
  output trn_tcfg_gnt;
  output p_5_out;
  output cfg_pm_turnoff_ok_n;
  input user_reset_out_reg;
  input tx_cfg_gnt;
  input user_clk;
  input trn_tcfg_req;
  input trn_tdst_rdy;
  input cfg_turnoff_ok;
  input tbuf_av_min_trig;
  input s_axis_tx_tvalid;
  input [0:0]s_axis_tx_tuser;
  input [3:0]s_axis_tx_tdata;
  input s_axis_tx_tlast;
  input \pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  input user_lnk_up_int_reg;
  input [2:0]cfg_pcie_link_state;
  input axi_in_packet_reg_0;
  input user_reset_out_reg_0;
  input \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input \tcfg_req_cnt_reg[1]_0 ;
  input \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg ;
  input [5:0]trn_tbuf_av;
  input cfg_to_turnoff;

  wire CUR_STATE_A;
  wire CUR_STATE_A_i_2_n_0;
  wire NEXT_STATE_A;
  wire \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg ;
  wire axi_in_packet_reg;
  wire axi_in_packet_reg_0;
  wire [2:0]cfg_pcie_link_state;
  wire [2:0]cfg_pcie_link_state_d;
  wire cfg_pm_turnoff_ok_n;
  wire cfg_to_turnoff;
  wire cfg_turnoff_ok;
  wire cfg_turnoff_ok_pending;
  wire cfg_turnoff_ok_pending_i_1_n_0;
  wire lnk_up_thrtl;
  wire lnk_up_thrtl_i_1_n_0;
  wire p_5_out;
  wire pcie_block_i_i_36_n_0;
  wire pcie_block_i_i_37_n_0;
  wire \pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire ppm_L1_thrtl_i_1_n_0;
  wire ppm_L1_thrtl_i_2_n_0;
  wire ppm_L1_thrtl_i_3_n_0;
  wire ppm_L1_thrtl_reg_n_0;
  wire ppm_L23_thrtl;
  wire ppm_L23_thrtl_i_1_n_0;
  wire reg_axi_in_pkt;
  wire reg_axi_in_pkt_i_1_n_0;
  wire reg_tcfg_gnt;
  wire reg_to_turnoff;
  wire reg_turnoff_ok;
  wire [3:0]s_axis_tx_tdata;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tready;
  wire [0:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire [5:0]tbuf_av_d;
  wire tbuf_av_gap_thrtl_i_1_n_0;
  wire tbuf_av_gap_thrtl_i_4_n_0;
  wire tbuf_av_gap_thrtl_reg_0;
  wire tbuf_av_gap_thrtl_reg_1;
  wire tbuf_av_gap_thrtl_reg_n_0;
  wire tbuf_av_min_thrtl;
  wire tbuf_av_min_trig;
  wire \tbuf_gap_cnt[0]_i_1_n_0 ;
  wire \tbuf_gap_cnt[1]_i_1_n_0 ;
  wire \tbuf_gap_cnt[2]_i_1_n_0 ;
  wire \tbuf_gap_cnt_reg_n_0_[0] ;
  wire \tbuf_gap_cnt_reg_n_0_[1] ;
  wire \tbuf_gap_cnt_reg_n_0_[2] ;
  wire tcfg_gnt_pending_i_1_n_0;
  wire tcfg_gnt_pending_reg_n_0;
  wire [1:0]tcfg_req_cnt;
  wire \tcfg_req_cnt[0]_i_1_n_0 ;
  wire \tcfg_req_cnt[1]_i_1_n_0 ;
  wire \tcfg_req_cnt_reg[1]_0 ;
  wire tcfg_req_thrtl;
  wire tcfg_req_thrtl_i_1_n_0;
  wire tcfg_req_thrtl_i_2_n_0;
  wire tready_thrtl_xhdl10;
  wire tready_thrtl_xhdl1_i_3_n_0;
  wire tready_thrtl_xhdl1_i_4_n_0;
  wire tready_thrtl_xhdl1_i_6_n_0;
  wire tready_thrtl_xhdl1_i_7_n_0;
  wire tready_thrtl_xhdl1_i_9_n_0;
  wire tready_thrtl_xhdl1_reg_0;
  wire [5:0]trn_tbuf_av;
  wire trn_tcfg_gnt;
  wire trn_tcfg_req;
  wire trn_tcfg_req_d;
  wire trn_tdst_rdy;
  wire trn_tdst_rdy_d;
  wire tx_cfg_gnt;
  wire user_clk;
  wire user_lnk_up_int_reg;
  wire user_reset_out_reg;
  wire user_reset_out_reg_0;
  wire \xhdl12.xhdl14.xhdl15.reg_to_turnoff_i_1_n_0 ;
  wire \xhdl17.reg_tx_ecrc_pkt_i_1_n_0 ;
  wire \xhdl17.reg_tx_ecrc_pkt_reg_n_0 ;

  LUT6 #(
    .INIT(64'hA8AA88AAA8AAAAAA)) 
    CUR_STATE_A_i_1
       (.I0(CUR_STATE_A_i_2_n_0),
        .I1(CUR_STATE_A),
        .I2(s_axis_tx_tlast),
        .I3(s_axis_tx_tready),
        .I4(s_axis_tx_tvalid),
        .I5(reg_axi_in_pkt),
        .O(NEXT_STATE_A));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    CUR_STATE_A_i_2
       (.I0(lnk_up_thrtl),
        .I1(ppm_L1_thrtl_reg_n_0),
        .I2(tbuf_av_gap_thrtl_reg_n_0),
        .I3(ppm_L23_thrtl),
        .I4(tcfg_req_thrtl),
        .I5(tbuf_av_min_thrtl),
        .O(CUR_STATE_A_i_2_n_0));
  FDSE CUR_STATE_A_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(NEXT_STATE_A),
        .Q(CUR_STATE_A),
        .S(user_reset_out_reg));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT5 #(
    .INIT(32'h13331000)) 
    axi_in_packet_i_1
       (.I0(s_axis_tx_tlast),
        .I1(user_reset_out_reg),
        .I2(s_axis_tx_tvalid),
        .I3(s_axis_tx_tready),
        .I4(axi_in_packet_reg_0),
        .O(axi_in_packet_reg));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_pcie_link_state_d_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(cfg_pcie_link_state[0]),
        .Q(cfg_pcie_link_state_d[0]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_pcie_link_state_d_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(cfg_pcie_link_state[1]),
        .Q(cfg_pcie_link_state_d[1]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_pcie_link_state_d_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(cfg_pcie_link_state[2]),
        .Q(cfg_pcie_link_state_d[2]),
        .R(user_reset_out_reg));
  LUT5 #(
    .INIT(32'hFF404040)) 
    cfg_turnoff_ok_pending_i_1
       (.I0(ppm_L23_thrtl),
        .I1(reg_to_turnoff),
        .I2(reg_turnoff_ok),
        .I3(cfg_pm_turnoff_ok_n),
        .I4(cfg_turnoff_ok_pending),
        .O(cfg_turnoff_ok_pending_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    cfg_turnoff_ok_pending_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(cfg_turnoff_ok_pending_i_1_n_0),
        .Q(cfg_turnoff_ok_pending),
        .R(user_reset_out_reg));
  LUT4 #(
    .INIT(16'hFF4F)) 
    lnk_up_thrtl_i_1
       (.I0(trn_tdst_rdy),
        .I1(lnk_up_thrtl),
        .I2(user_lnk_up_int_reg),
        .I3(user_reset_out_reg),
        .O(lnk_up_thrtl_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    lnk_up_thrtl_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(lnk_up_thrtl_i_1_n_0),
        .Q(lnk_up_thrtl),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hDFDF505FDFDF5F5F)) 
    pcie_block_i_i_26
       (.I0(cfg_turnoff_ok_pending),
        .I1(tcfg_gnt_pending_reg_n_0),
        .I2(CUR_STATE_A),
        .I3(ppm_L23_thrtl),
        .I4(tcfg_req_thrtl),
        .I5(pcie_block_i_i_36_n_0),
        .O(cfg_pm_turnoff_ok_n));
  LUT6 #(
    .INIT(64'hAAAA222A0000222A)) 
    pcie_block_i_i_30
       (.I0(tcfg_req_thrtl),
        .I1(pcie_block_i_i_37_n_0),
        .I2(s_axis_tx_tvalid),
        .I3(reg_axi_in_pkt),
        .I4(CUR_STATE_A),
        .I5(tcfg_gnt_pending_reg_n_0),
        .O(trn_tcfg_gnt));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT4 #(
    .INIT(16'hD1FF)) 
    pcie_block_i_i_36
       (.I0(reg_axi_in_pkt),
        .I1(s_axis_tx_tvalid),
        .I2(s_axis_tx_tlast),
        .I3(s_axis_tx_tready),
        .O(pcie_block_i_i_36_n_0));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    pcie_block_i_i_37
       (.I0(s_axis_tx_tready),
        .I1(s_axis_tx_tlast),
        .I2(s_axis_tx_tvalid),
        .O(pcie_block_i_i_37_n_0));
  LUT6 #(
    .INIT(64'h808080FF80808000)) 
    ppm_L1_thrtl_i_1
       (.I0(ppm_L1_thrtl_i_2_n_0),
        .I1(cfg_pcie_link_state[0]),
        .I2(cfg_pcie_link_state[2]),
        .I3(ppm_L1_thrtl_i_3_n_0),
        .I4(user_reset_out_reg_0),
        .I5(ppm_L1_thrtl_reg_n_0),
        .O(ppm_L1_thrtl_i_1_n_0));
  LUT5 #(
    .INIT(32'h00000001)) 
    ppm_L1_thrtl_i_2
       (.I0(cfg_pcie_link_state_d[2]),
        .I1(cfg_pcie_link_state[1]),
        .I2(user_reset_out_reg),
        .I3(cfg_pcie_link_state_d[0]),
        .I4(cfg_pcie_link_state_d[1]),
        .O(ppm_L1_thrtl_i_2_n_0));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    ppm_L1_thrtl_i_3
       (.I0(cfg_pcie_link_state_d[2]),
        .I1(cfg_pcie_link_state[1]),
        .I2(cfg_pcie_link_state_d[0]),
        .I3(cfg_pcie_link_state_d[1]),
        .I4(cfg_pcie_link_state[2]),
        .I5(cfg_pcie_link_state[0]),
        .O(ppm_L1_thrtl_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ppm_L1_thrtl_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(ppm_L1_thrtl_i_1_n_0),
        .Q(ppm_L1_thrtl_reg_n_0),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF8)) 
    ppm_L23_thrtl_i_1
       (.I0(reg_to_turnoff),
        .I1(reg_turnoff_ok),
        .I2(ppm_L23_thrtl),
        .O(ppm_L23_thrtl_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ppm_L23_thrtl_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(ppm_L23_thrtl_i_1_n_0),
        .Q(ppm_L23_thrtl),
        .R(user_reset_out_reg));
  LUT5 #(
    .INIT(32'h00000AEA)) 
    reg_axi_in_pkt_i_1
       (.I0(reg_axi_in_pkt),
        .I1(s_axis_tx_tready),
        .I2(s_axis_tx_tvalid),
        .I3(s_axis_tx_tlast),
        .I4(user_reset_out_reg),
        .O(reg_axi_in_pkt_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    reg_axi_in_pkt_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(reg_axi_in_pkt_i_1_n_0),
        .Q(reg_axi_in_pkt),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    reg_tcfg_gnt_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tx_cfg_gnt),
        .Q(reg_tcfg_gnt),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \tbuf_av_d_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(trn_tbuf_av[0]),
        .Q(tbuf_av_d[0]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \tbuf_av_d_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(trn_tbuf_av[1]),
        .Q(tbuf_av_d[1]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \tbuf_av_d_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(trn_tbuf_av[2]),
        .Q(tbuf_av_d[2]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \tbuf_av_d_reg[3] 
       (.C(user_clk),
        .CE(1'b1),
        .D(trn_tbuf_av[3]),
        .Q(tbuf_av_d[3]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \tbuf_av_d_reg[4] 
       (.C(user_clk),
        .CE(1'b1),
        .D(trn_tbuf_av[4]),
        .Q(tbuf_av_d[4]),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \tbuf_av_d_reg[5] 
       (.C(user_clk),
        .CE(1'b1),
        .D(trn_tbuf_av[5]),
        .Q(tbuf_av_d[5]),
        .R(user_reset_out_reg));
  LUT6 #(
    .INIT(64'h00EF00FF00EE00FF)) 
    tbuf_av_gap_thrtl_i_1
       (.I0(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ),
        .I1(tbuf_av_gap_thrtl_reg_0),
        .I2(tbuf_av_gap_thrtl_i_4_n_0),
        .I3(user_reset_out_reg),
        .I4(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ),
        .I5(tbuf_av_gap_thrtl_reg_n_0),
        .O(tbuf_av_gap_thrtl_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT5 #(
    .INIT(32'h00020000)) 
    tbuf_av_gap_thrtl_i_3
       (.I0(trn_tdst_rdy),
        .I1(tcfg_req_cnt[1]),
        .I2(tcfg_req_cnt[0]),
        .I3(trn_tdst_rdy_d),
        .I4(tcfg_req_thrtl),
        .O(tbuf_av_gap_thrtl_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT3 #(
    .INIT(8'h01)) 
    tbuf_av_gap_thrtl_i_4
       (.I0(\tbuf_gap_cnt_reg_n_0_[1] ),
        .I1(\tbuf_gap_cnt_reg_n_0_[0] ),
        .I2(\tbuf_gap_cnt_reg_n_0_[2] ),
        .O(tbuf_av_gap_thrtl_i_4_n_0));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    tbuf_av_gap_thrtl_i_7
       (.I0(tbuf_av_d[4]),
        .I1(tbuf_av_d[2]),
        .I2(tbuf_av_d[1]),
        .I3(tbuf_av_d[0]),
        .I4(tbuf_av_d[3]),
        .I5(tbuf_av_d[5]),
        .O(tbuf_av_gap_thrtl_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    tbuf_av_gap_thrtl_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tbuf_av_gap_thrtl_i_1_n_0),
        .Q(tbuf_av_gap_thrtl_reg_n_0),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    tbuf_av_min_thrtl_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tbuf_av_min_trig),
        .Q(tbuf_av_min_thrtl),
        .R(user_reset_out_reg));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT5 #(
    .INIT(32'h32FFFFFF)) 
    \tbuf_gap_cnt[0]_i_1 
       (.I0(\tbuf_gap_cnt_reg_n_0_[1] ),
        .I1(\tbuf_gap_cnt_reg_n_0_[0] ),
        .I2(\tbuf_gap_cnt_reg_n_0_[2] ),
        .I3(CUR_STATE_A),
        .I4(tbuf_av_gap_thrtl_reg_n_0),
        .O(\tbuf_gap_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000098000000)) 
    \tbuf_gap_cnt[1]_i_1 
       (.I0(\tbuf_gap_cnt_reg_n_0_[1] ),
        .I1(\tbuf_gap_cnt_reg_n_0_[0] ),
        .I2(\tbuf_gap_cnt_reg_n_0_[2] ),
        .I3(tbuf_av_gap_thrtl_reg_n_0),
        .I4(CUR_STATE_A),
        .I5(user_reset_out_reg),
        .O(\tbuf_gap_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000E0000000)) 
    \tbuf_gap_cnt[2]_i_1 
       (.I0(\tbuf_gap_cnt_reg_n_0_[1] ),
        .I1(\tbuf_gap_cnt_reg_n_0_[0] ),
        .I2(\tbuf_gap_cnt_reg_n_0_[2] ),
        .I3(tbuf_av_gap_thrtl_reg_n_0),
        .I4(CUR_STATE_A),
        .I5(user_reset_out_reg),
        .O(\tbuf_gap_cnt[2]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \tbuf_gap_cnt_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tbuf_gap_cnt[0]_i_1_n_0 ),
        .Q(\tbuf_gap_cnt_reg_n_0_[0] ),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    \tbuf_gap_cnt_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tbuf_gap_cnt[1]_i_1_n_0 ),
        .Q(\tbuf_gap_cnt_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \tbuf_gap_cnt_reg[2] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tbuf_gap_cnt[2]_i_1_n_0 ),
        .Q(\tbuf_gap_cnt_reg_n_0_[2] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h004F0044)) 
    tcfg_gnt_pending_i_1
       (.I0(trn_tcfg_req_d),
        .I1(trn_tcfg_req),
        .I2(trn_tcfg_gnt),
        .I3(user_reset_out_reg),
        .I4(tcfg_gnt_pending_reg_n_0),
        .O(tcfg_gnt_pending_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    tcfg_gnt_pending_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tcfg_gnt_pending_i_1_n_0),
        .Q(tcfg_gnt_pending_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000D00)) 
    \tcfg_req_cnt[0]_i_1 
       (.I0(trn_tcfg_req),
        .I1(trn_tcfg_req_d),
        .I2(tcfg_req_cnt[0]),
        .I3(tcfg_req_cnt[1]),
        .I4(user_reset_out_reg),
        .I5(tcfg_gnt_pending_reg_n_0),
        .O(\tcfg_req_cnt[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF444)) 
    \tcfg_req_cnt[1]_i_1 
       (.I0(trn_tcfg_req_d),
        .I1(trn_tcfg_req),
        .I2(tcfg_req_cnt[0]),
        .I3(tcfg_req_cnt[1]),
        .I4(tcfg_gnt_pending_reg_n_0),
        .O(\tcfg_req_cnt[1]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \tcfg_req_cnt_reg[0] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tcfg_req_cnt[0]_i_1_n_0 ),
        .Q(tcfg_req_cnt[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \tcfg_req_cnt_reg[1] 
       (.C(user_clk),
        .CE(1'b1),
        .D(\tcfg_req_cnt[1]_i_1_n_0 ),
        .Q(tcfg_req_cnt[1]),
        .R(user_reset_out_reg));
  LUT5 #(
    .INIT(32'h00D500C0)) 
    tcfg_req_thrtl_i_1
       (.I0(tcfg_req_thrtl_i_2_n_0),
        .I1(reg_tcfg_gnt),
        .I2(trn_tcfg_req),
        .I3(user_reset_out_reg),
        .I4(tcfg_req_thrtl),
        .O(tcfg_req_thrtl_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    tcfg_req_thrtl_i_2
       (.I0(trn_tdst_rdy),
        .I1(tcfg_req_cnt[0]),
        .I2(tcfg_req_cnt[1]),
        .I3(trn_tdst_rdy_d),
        .O(tcfg_req_thrtl_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    tcfg_req_thrtl_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tcfg_req_thrtl_i_1_n_0),
        .Q(tcfg_req_thrtl),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h5D005D005D005D5D)) 
    tready_thrtl_xhdl1_i_1
       (.I0(tready_thrtl_xhdl1_reg_0),
        .I1(tready_thrtl_xhdl1_i_3_n_0),
        .I2(\xhdl17.reg_tx_ecrc_pkt_reg_n_0 ),
        .I3(tready_thrtl_xhdl1_i_4_n_0),
        .I4(\tcfg_req_cnt_reg[1]_0 ),
        .I5(tready_thrtl_xhdl1_i_6_n_0),
        .O(tready_thrtl_xhdl10));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT3 #(
    .INIT(8'h80)) 
    tready_thrtl_xhdl1_i_2
       (.I0(s_axis_tx_tlast),
        .I1(s_axis_tx_tvalid),
        .I2(s_axis_tx_tready),
        .O(tready_thrtl_xhdl1_reg_0));
  LUT4 #(
    .INIT(16'hFF87)) 
    tready_thrtl_xhdl1_i_3
       (.I0(s_axis_tx_tdata[0]),
        .I1(s_axis_tx_tdata[3]),
        .I2(s_axis_tx_tdata[2]),
        .I3(tready_thrtl_xhdl1_i_7_n_0),
        .O(tready_thrtl_xhdl1_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT5 #(
    .INIT(32'h000020E0)) 
    tready_thrtl_xhdl1_i_4
       (.I0(reg_axi_in_pkt),
        .I1(s_axis_tx_tvalid),
        .I2(s_axis_tx_tready),
        .I3(s_axis_tx_tlast),
        .I4(CUR_STATE_A),
        .O(tready_thrtl_xhdl1_i_4_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFD5)) 
    tready_thrtl_xhdl1_i_6
       (.I0(\pipe_stages_1.pipe_rx_chanisaligned_q_reg ),
        .I1(trn_tcfg_req),
        .I2(reg_tcfg_gnt),
        .I3(CUR_STATE_A_i_2_n_0),
        .I4(tready_thrtl_xhdl1_i_9_n_0),
        .I5(ppm_L1_thrtl_i_3_n_0),
        .O(tready_thrtl_xhdl1_i_6_n_0));
  LUT5 #(
    .INIT(32'hFFFFF7FF)) 
    tready_thrtl_xhdl1_i_7
       (.I0(s_axis_tx_tvalid),
        .I1(s_axis_tx_tready),
        .I2(reg_axi_in_pkt),
        .I3(s_axis_tx_tuser),
        .I4(s_axis_tx_tdata[1]),
        .O(tready_thrtl_xhdl1_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT3 #(
    .INIT(8'h8F)) 
    tready_thrtl_xhdl1_i_9
       (.I0(reg_turnoff_ok),
        .I1(reg_to_turnoff),
        .I2(user_lnk_up_int_reg),
        .O(tready_thrtl_xhdl1_i_9_n_0));
  FDRE #(
    .INIT(1'b0)) 
    tready_thrtl_xhdl1_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(tready_thrtl_xhdl10),
        .Q(s_axis_tx_tready),
        .R(user_reset_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    trn_tcfg_req_d_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(trn_tcfg_req),
        .Q(trn_tcfg_req_d),
        .R(user_reset_out_reg));
  FDSE #(
    .INIT(1'b0)) 
    trn_tdst_rdy_d_reg
       (.C(user_clk),
        .CE(1'b1),
        .D(trn_tdst_rdy),
        .Q(trn_tdst_rdy_d),
        .S(user_reset_out_reg));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \xhdl12.reg_tsrc_rdy_i_1 
       (.I0(s_axis_tx_tvalid),
        .I1(s_axis_tx_tready),
        .I2(user_lnk_up_int_reg),
        .I3(\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg ),
        .O(p_5_out));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.xhdl14.reg_turnoff_ok_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(cfg_turnoff_ok),
        .Q(reg_turnoff_ok),
        .R(user_reset_out_reg));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \xhdl12.xhdl14.xhdl15.reg_to_turnoff_i_1 
       (.I0(cfg_to_turnoff),
        .I1(reg_to_turnoff),
        .O(\xhdl12.xhdl14.xhdl15.reg_to_turnoff_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\xhdl12.xhdl14.xhdl15.reg_to_turnoff_i_1_n_0 ),
        .Q(reg_to_turnoff),
        .R(user_reset_out_reg));
  LUT6 #(
    .INIT(64'h07070F0F0000000F)) 
    \xhdl17.reg_tx_ecrc_pkt_i_1 
       (.I0(s_axis_tx_tvalid),
        .I1(s_axis_tx_tready),
        .I2(user_reset_out_reg),
        .I3(tready_thrtl_xhdl1_i_3_n_0),
        .I4(s_axis_tx_tlast),
        .I5(\xhdl17.reg_tx_ecrc_pkt_reg_n_0 ),
        .O(\xhdl17.reg_tx_ecrc_pkt_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xhdl17.reg_tx_ecrc_pkt_reg 
       (.C(user_clk),
        .CE(1'b1),
        .D(\xhdl17.reg_tx_ecrc_pkt_i_1_n_0 ),
        .Q(\xhdl17.reg_tx_ecrc_pkt_reg_n_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_core_top" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_core_top
   (pipe_qrst_fsm,
    pipe_txphinitdone,
    pipe_txphaligndone,
    PIPE_SYNC_FSM_TX,
    PIPE_RATE_FSM,
    PIPE_DRP_FSM,
    pl_phy_lnk_up,
    user_reset_out,
    m_axis_rx_tvalid,
    tx_cfg_req,
    s_axis_tx_tready,
    tx_buf_av,
    user_lnk_up,
    cfg_pcie_link_state,
    pl_received_hot_rst,
    pipe_rxphaligndone,
    INT_USERCLK2_OUT,
    cfg_aer_ecrc_check_en,
    cfg_aer_ecrc_gen_en,
    cfg_aer_rooterr_corr_err_received,
    cfg_aer_rooterr_corr_err_reporting_en,
    cfg_aer_rooterr_fatal_err_received,
    cfg_aer_rooterr_fatal_err_reporting_en,
    cfg_aer_rooterr_non_fatal_err_received,
    cfg_aer_rooterr_non_fatal_err_reporting_en,
    cfg_bridge_serr_en,
    cfg_command,
    cfg_dcommand2,
    cfg_dcommand,
    cfg_dstatus,
    cfg_interrupt_msienable,
    cfg_interrupt_msixenable,
    cfg_interrupt_msixfm,
    cfg_lcommand,
    cfg_lstatus,
    cfg_msg_received,
    cfg_msg_received_assert_int_a,
    cfg_msg_received_assert_int_b,
    cfg_msg_received_assert_int_c,
    cfg_msg_received_assert_int_d,
    cfg_msg_received_deassert_int_a,
    cfg_msg_received_deassert_int_b,
    cfg_msg_received_deassert_int_c,
    cfg_msg_received_deassert_int_d,
    cfg_msg_received_err_cor,
    cfg_msg_received_err_fatal,
    cfg_msg_received_err_non_fatal,
    cfg_msg_received_pm_as_nak,
    cfg_to_turnoff,
    cfg_msg_received_pme_to_ack,
    cfg_msg_received_pm_pme,
    cfg_msg_received_setslotpowerlimit,
    cfg_pmcsr_pme_en,
    cfg_pmcsr_pme_status,
    cfg_root_control_pme_int_en,
    cfg_root_control_syserr_corr_err_en,
    cfg_root_control_syserr_fatal_err_en,
    cfg_root_control_syserr_non_fatal_err_en,
    cfg_slot_control_electromech_il_ctl_pulse,
    pcie_drp_rdy,
    pl_directed_change_done,
    pl_link_gen2_cap,
    pl_link_partner_gen2_supported,
    pl_link_upcfg_cap,
    pl_sel_lnk_rate,
    tx_err_drop,
    fc_cpld,
    fc_npd,
    fc_pd,
    cfg_msg_data,
    pcie_drp_do,
    cfg_pmcsr_powerstate,
    pl_lane_reversal_mode,
    pl_rx_pm_state,
    pl_sel_lnk_width,
    cfg_interrupt_mmenable,
    pl_initial_link_width,
    pl_tx_pm_state,
    cfg_mgmt_do,
    pl_ltssm_state,
    cfg_vc_tcvc_map,
    cfg_interrupt_do,
    fc_cplh,
    fc_nph,
    fc_ph,
    INT_OOBCLK_OUT,
    pipe_txoutclk_out,
    int_mmcm_lock_out,
    ext_ch_gt_drpclk,
    pipe_pclk_sel_out,
    EQ_GEN3,
    out,
    pipe_rst_fsm,
    pipe_cpll_lock,
    pipe_qrst_idle,
    int_qplllock_out,
    pipe_rxstatus,
    pipe_sync_fsm_rx,
    ext_ch_gt_drprdy,
    ext_ch_gt_drpdo,
    int_qplloutclk_out,
    int_qplloutrefclk_out,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    pipe_rxoutclk_out,
    pipe_rxprbserr,
    pipe_txdlysresetdone,
    pipe_rxbufstatus,
    pipe_dmonitorout,
    pipe_rxdisperr,
    pipe_rxnotintable,
    pipe_rate_idle,
    gt_ch_drp_rdy,
    m_axis_rx_tdata,
    m_axis_rx_tkeep,
    m_axis_rx_tlast,
    m_axis_rx_tuser,
    cfg_bus_number,
    cfg_device_number,
    cfg_function_number,
    cfg_mgmt_rd_wr_done,
    cfg_err_aer_headerlog_set,
    cfg_err_cpl_rdy,
    cfg_interrupt_rdy,
    cfg_received_func_lvl_rst,
    ext_ch_gt_drpaddr,
    m_axis_rx_tready,
    s_axis_tx_tvalid,
    s_axis_tx_tuser,
    s_axis_tx_tdata,
    s_axis_tx_tlast,
    sys_rst_n,
    pcie_drp_clk,
    pcie_drp_en,
    pcie_drp_we,
    pl_directed_link_auton,
    pl_directed_link_speed,
    pl_downstream_deemph_source,
    pl_transmit_hot_rst,
    pl_upstream_prefer_deemph,
    rx_np_ok,
    rx_np_req,
    cfg_err_aer_headerlog,
    pcie_drp_di,
    cfg_pm_force_state,
    pl_directed_link_change,
    pl_directed_link_width,
    cfg_ds_function_number,
    fc_sel,
    cfg_mgmt_di,
    cfg_err_tlp_cpl_header,
    cfg_aer_interrupt_msgnum,
    cfg_ds_device_number,
    cfg_pciecap_interrupt_msgnum,
    cfg_dsn,
    cfg_ds_bus_number,
    cfg_interrupt_di,
    pcie_drp_addr,
    cfg_mgmt_dwaddr,
    int_pclk_sel_slave,
    pipe_mmcm_rst_n,
    sys_clk,
    pci_exp_rxn,
    pci_exp_rxp,
    pipe_txinhibit,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi,
    s_axis_tx_tkeep,
    tx_cfg_gnt,
    cfg_turnoff_ok,
    cfg_mgmt_byte_en,
    cfg_trn_pending,
    cfg_mgmt_wr_rw1c_as_rw,
    cfg_mgmt_wr_readonly,
    cfg_mgmt_wr_en,
    cfg_mgmt_rd_en,
    cfg_err_malformed,
    cfg_err_cor,
    cfg_err_ur,
    cfg_err_ecrc,
    cfg_err_cpl_timeout,
    cfg_err_cpl_abort,
    cfg_err_cpl_unexpect,
    cfg_err_poisoned,
    cfg_err_atomic_egress_blocked,
    cfg_err_mc_blocked,
    cfg_err_internal_uncor,
    cfg_err_internal_cor,
    cfg_err_posted,
    cfg_err_locked,
    cfg_err_norecovery,
    cfg_interrupt,
    cfg_interrupt_assert,
    cfg_interrupt_stat,
    cfg_pm_halt_aspm_l0s,
    cfg_pm_halt_aspm_l1,
    cfg_pm_force_state_en,
    cfg_pm_wake);
  output [3:0]pipe_qrst_fsm;
  output [7:0]pipe_txphinitdone;
  output [7:0]pipe_txphaligndone;
  output [47:0]PIPE_SYNC_FSM_TX;
  output [39:0]PIPE_RATE_FSM;
  output [23:0]PIPE_DRP_FSM;
  output pl_phy_lnk_up;
  output user_reset_out;
  output m_axis_rx_tvalid;
  output tx_cfg_req;
  output s_axis_tx_tready;
  output [5:0]tx_buf_av;
  output user_lnk_up;
  output [2:0]cfg_pcie_link_state;
  output pl_received_hot_rst;
  output [7:0]pipe_rxphaligndone;
  output INT_USERCLK2_OUT;
  output cfg_aer_ecrc_check_en;
  output cfg_aer_ecrc_gen_en;
  output cfg_aer_rooterr_corr_err_received;
  output cfg_aer_rooterr_corr_err_reporting_en;
  output cfg_aer_rooterr_fatal_err_received;
  output cfg_aer_rooterr_fatal_err_reporting_en;
  output cfg_aer_rooterr_non_fatal_err_received;
  output cfg_aer_rooterr_non_fatal_err_reporting_en;
  output cfg_bridge_serr_en;
  output [4:0]cfg_command;
  output [11:0]cfg_dcommand2;
  output [14:0]cfg_dcommand;
  output [3:0]cfg_dstatus;
  output cfg_interrupt_msienable;
  output cfg_interrupt_msixenable;
  output cfg_interrupt_msixfm;
  output [10:0]cfg_lcommand;
  output [9:0]cfg_lstatus;
  output cfg_msg_received;
  output cfg_msg_received_assert_int_a;
  output cfg_msg_received_assert_int_b;
  output cfg_msg_received_assert_int_c;
  output cfg_msg_received_assert_int_d;
  output cfg_msg_received_deassert_int_a;
  output cfg_msg_received_deassert_int_b;
  output cfg_msg_received_deassert_int_c;
  output cfg_msg_received_deassert_int_d;
  output cfg_msg_received_err_cor;
  output cfg_msg_received_err_fatal;
  output cfg_msg_received_err_non_fatal;
  output cfg_msg_received_pm_as_nak;
  output cfg_to_turnoff;
  output cfg_msg_received_pme_to_ack;
  output cfg_msg_received_pm_pme;
  output cfg_msg_received_setslotpowerlimit;
  output cfg_pmcsr_pme_en;
  output cfg_pmcsr_pme_status;
  output cfg_root_control_pme_int_en;
  output cfg_root_control_syserr_corr_err_en;
  output cfg_root_control_syserr_fatal_err_en;
  output cfg_root_control_syserr_non_fatal_err_en;
  output cfg_slot_control_electromech_il_ctl_pulse;
  output pcie_drp_rdy;
  output pl_directed_change_done;
  output pl_link_gen2_cap;
  output pl_link_partner_gen2_supported;
  output pl_link_upcfg_cap;
  output pl_sel_lnk_rate;
  output tx_err_drop;
  output [11:0]fc_cpld;
  output [11:0]fc_npd;
  output [11:0]fc_pd;
  output [15:0]cfg_msg_data;
  output [15:0]pcie_drp_do;
  output [1:0]cfg_pmcsr_powerstate;
  output [1:0]pl_lane_reversal_mode;
  output [1:0]pl_rx_pm_state;
  output [1:0]pl_sel_lnk_width;
  output [2:0]cfg_interrupt_mmenable;
  output [2:0]pl_initial_link_width;
  output [2:0]pl_tx_pm_state;
  output [31:0]cfg_mgmt_do;
  output [5:0]pl_ltssm_state;
  output [6:0]cfg_vc_tcvc_map;
  output [7:0]cfg_interrupt_do;
  output [7:0]fc_cplh;
  output [7:0]fc_nph;
  output [7:0]fc_ph;
  output INT_OOBCLK_OUT;
  output pipe_txoutclk_out;
  output int_mmcm_lock_out;
  output ext_ch_gt_drpclk;
  output [7:0]pipe_pclk_sel_out;
  output EQ_GEN3;
  output [1:0]out;
  output [3:0]pipe_rst_fsm;
  output [7:0]pipe_cpll_lock;
  output pipe_qrst_idle;
  output [1:0]int_qplllock_out;
  output [23:0]pipe_rxstatus;
  output [55:0]pipe_sync_fsm_rx;
  output [7:0]ext_ch_gt_drprdy;
  output [127:0]ext_ch_gt_drpdo;
  output [1:0]int_qplloutclk_out;
  output [1:0]int_qplloutrefclk_out;
  output [7:0]pipe_eyescandataerror;
  output [7:0]pci_exp_txn;
  output [7:0]pci_exp_txp;
  output [7:0]pipe_rxcommadet;
  output [7:0]pipe_rxdlysresetdone;
  output [7:0]pipe_rxoutclk_out;
  output [7:0]pipe_rxprbserr;
  output [7:0]pipe_txdlysresetdone;
  output [23:0]pipe_rxbufstatus;
  output [63:0]pipe_dmonitorout;
  output [63:0]pipe_rxdisperr;
  output [63:0]pipe_rxnotintable;
  output pipe_rate_idle;
  output [7:0]gt_ch_drp_rdy;
  output [63:0]m_axis_rx_tdata;
  output [7:0]m_axis_rx_tkeep;
  output m_axis_rx_tlast;
  output [21:0]m_axis_rx_tuser;
  output [7:0]cfg_bus_number;
  output [4:0]cfg_device_number;
  output [2:0]cfg_function_number;
  output cfg_mgmt_rd_wr_done;
  output cfg_err_aer_headerlog_set;
  output cfg_err_cpl_rdy;
  output cfg_interrupt_rdy;
  output cfg_received_func_lvl_rst;
  input [71:0]ext_ch_gt_drpaddr;
  input m_axis_rx_tready;
  input s_axis_tx_tvalid;
  input [3:0]s_axis_tx_tuser;
  input [63:0]s_axis_tx_tdata;
  input s_axis_tx_tlast;
  input sys_rst_n;
  input pcie_drp_clk;
  input pcie_drp_en;
  input pcie_drp_we;
  input pl_directed_link_auton;
  input pl_directed_link_speed;
  input pl_downstream_deemph_source;
  input pl_transmit_hot_rst;
  input pl_upstream_prefer_deemph;
  input rx_np_ok;
  input rx_np_req;
  input [127:0]cfg_err_aer_headerlog;
  input [15:0]pcie_drp_di;
  input [1:0]cfg_pm_force_state;
  input [1:0]pl_directed_link_change;
  input [1:0]pl_directed_link_width;
  input [2:0]cfg_ds_function_number;
  input [2:0]fc_sel;
  input [31:0]cfg_mgmt_di;
  input [47:0]cfg_err_tlp_cpl_header;
  input [4:0]cfg_aer_interrupt_msgnum;
  input [4:0]cfg_ds_device_number;
  input [4:0]cfg_pciecap_interrupt_msgnum;
  input [63:0]cfg_dsn;
  input [7:0]cfg_ds_bus_number;
  input [7:0]cfg_interrupt_di;
  input [8:0]pcie_drp_addr;
  input [9:0]cfg_mgmt_dwaddr;
  input [7:0]int_pclk_sel_slave;
  input pipe_mmcm_rst_n;
  input sys_clk;
  input [7:0]pci_exp_rxn;
  input [7:0]pci_exp_rxp;
  input [7:0]pipe_txinhibit;
  input [7:0]ext_ch_gt_drpen;
  input [7:0]ext_ch_gt_drpwe;
  input [127:0]ext_ch_gt_drpdi;
  input [0:0]s_axis_tx_tkeep;
  input tx_cfg_gnt;
  input cfg_turnoff_ok;
  input [3:0]cfg_mgmt_byte_en;
  input cfg_trn_pending;
  input cfg_mgmt_wr_rw1c_as_rw;
  input cfg_mgmt_wr_readonly;
  input cfg_mgmt_wr_en;
  input cfg_mgmt_rd_en;
  input cfg_err_malformed;
  input cfg_err_cor;
  input cfg_err_ur;
  input cfg_err_ecrc;
  input cfg_err_cpl_timeout;
  input cfg_err_cpl_abort;
  input cfg_err_cpl_unexpect;
  input cfg_err_poisoned;
  input cfg_err_atomic_egress_blocked;
  input cfg_err_mc_blocked;
  input cfg_err_internal_uncor;
  input cfg_err_internal_cor;
  input cfg_err_posted;
  input cfg_err_locked;
  input cfg_err_norecovery;
  input cfg_interrupt;
  input cfg_interrupt_assert;
  input cfg_interrupt_stat;
  input cfg_pm_halt_aspm_l0s;
  input cfg_pm_halt_aspm_l1;
  input cfg_pm_force_state_en;
  input cfg_pm_wake;

  wire EQ_GEN3;
  wire INT_OOBCLK_OUT;
  wire INT_USERCLK2_OUT;
  wire [23:0]PIPE_DRP_FSM;
  wire [39:0]PIPE_RATE_FSM;
  wire [47:0]PIPE_SYNC_FSM_TX;
  wire bridge_reset_int;
  wire cfg_aer_ecrc_check_en;
  wire cfg_aer_ecrc_gen_en;
  wire [4:0]cfg_aer_interrupt_msgnum;
  wire cfg_aer_rooterr_corr_err_received;
  wire cfg_aer_rooterr_corr_err_reporting_en;
  wire cfg_aer_rooterr_fatal_err_received;
  wire cfg_aer_rooterr_fatal_err_reporting_en;
  wire cfg_aer_rooterr_non_fatal_err_received;
  wire cfg_aer_rooterr_non_fatal_err_reporting_en;
  wire cfg_bridge_serr_en;
  wire [7:0]cfg_bus_number;
  wire [4:0]cfg_command;
  wire [14:0]cfg_dcommand;
  wire [11:0]cfg_dcommand2;
  wire [4:0]cfg_device_number;
  wire [7:0]cfg_ds_bus_number;
  wire [4:0]cfg_ds_device_number;
  wire [2:0]cfg_ds_function_number;
  wire [63:0]cfg_dsn;
  wire [3:0]cfg_dstatus;
  wire [127:0]cfg_err_aer_headerlog;
  wire cfg_err_aer_headerlog_set;
  wire cfg_err_atomic_egress_blocked;
  wire cfg_err_cor;
  wire cfg_err_cpl_abort;
  wire cfg_err_cpl_rdy;
  wire cfg_err_cpl_timeout;
  wire cfg_err_cpl_unexpect;
  wire cfg_err_ecrc;
  wire cfg_err_internal_cor;
  wire cfg_err_internal_uncor;
  wire cfg_err_locked;
  wire cfg_err_malformed;
  wire cfg_err_mc_blocked;
  wire cfg_err_norecovery;
  wire cfg_err_poisoned;
  wire cfg_err_posted;
  wire [47:0]cfg_err_tlp_cpl_header;
  wire cfg_err_ur;
  wire [2:0]cfg_function_number;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire [7:0]cfg_interrupt_di;
  wire [7:0]cfg_interrupt_do;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_msixenable;
  wire cfg_interrupt_msixfm;
  wire cfg_interrupt_rdy;
  wire cfg_interrupt_stat;
  wire [10:0]cfg_lcommand;
  wire [9:0]cfg_lstatus;
  wire [3:0]cfg_mgmt_byte_en;
  wire [3:0]cfg_mgmt_byte_en_n;
  wire [31:0]cfg_mgmt_di;
  wire [31:0]cfg_mgmt_do;
  wire [9:0]cfg_mgmt_dwaddr;
  wire cfg_mgmt_rd_en;
  wire cfg_mgmt_rd_wr_done;
  wire cfg_mgmt_wr_en;
  wire cfg_mgmt_wr_readonly;
  wire cfg_mgmt_wr_rw1c_as_rw;
  wire [15:0]cfg_msg_data;
  wire cfg_msg_received;
  wire cfg_msg_received_assert_int_a;
  wire cfg_msg_received_assert_int_b;
  wire cfg_msg_received_assert_int_c;
  wire cfg_msg_received_assert_int_d;
  wire cfg_msg_received_deassert_int_a;
  wire cfg_msg_received_deassert_int_b;
  wire cfg_msg_received_deassert_int_c;
  wire cfg_msg_received_deassert_int_d;
  wire cfg_msg_received_err_cor;
  wire cfg_msg_received_err_fatal;
  wire cfg_msg_received_err_non_fatal;
  wire cfg_msg_received_pm_as_nak;
  wire cfg_msg_received_pm_pme;
  wire cfg_msg_received_pme_to_ack;
  wire cfg_msg_received_setslotpowerlimit;
  wire [2:0]cfg_pcie_link_state;
  wire [4:0]cfg_pciecap_interrupt_msgnum;
  wire [1:0]cfg_pm_force_state;
  wire cfg_pm_force_state_en;
  wire cfg_pm_halt_aspm_l0s;
  wire cfg_pm_halt_aspm_l1;
  wire cfg_pm_wake;
  wire cfg_pmcsr_pme_en;
  wire cfg_pmcsr_pme_status;
  wire [1:0]cfg_pmcsr_powerstate;
  wire cfg_received_func_lvl_rst;
  wire cfg_root_control_pme_int_en;
  wire cfg_root_control_syserr_corr_err_en;
  wire cfg_root_control_syserr_fatal_err_en;
  wire cfg_root_control_syserr_non_fatal_err_en;
  wire cfg_slot_control_electromech_il_ctl_pulse;
  wire cfg_to_turnoff;
  wire cfg_trn_pending;
  wire cfg_turnoff_ok;
  wire [6:0]cfg_vc_tcvc_map;
  wire [71:0]ext_ch_gt_drpaddr;
  wire ext_ch_gt_drpclk;
  wire [127:0]ext_ch_gt_drpdi;
  wire [127:0]ext_ch_gt_drpdo;
  wire [7:0]ext_ch_gt_drpen;
  wire [7:0]ext_ch_gt_drprdy;
  wire [7:0]ext_ch_gt_drpwe;
  wire [11:0]fc_cpld;
  wire [7:0]fc_cplh;
  wire [11:0]fc_npd;
  wire [7:0]fc_nph;
  wire [11:0]fc_pd;
  wire [7:0]fc_ph;
  wire [2:0]fc_sel;
  wire [7:0]gt_ch_drp_rdy;
  wire gt_rx_phy_status_q;
  wire gt_rxelecidle_q;
  wire gt_top_i_n_12;
  wire gt_top_i_n_13;
  wire gt_top_i_n_14;
  wire gt_top_i_n_15;
  wire gt_top_i_n_16;
  wire gt_top_i_n_17;
  wire gt_top_i_n_18;
  wire gt_top_i_n_19;
  wire gt_top_i_n_20;
  wire gt_top_i_n_21;
  wire gt_top_i_n_22;
  wire gt_top_i_n_23;
  wire gt_top_i_n_24;
  wire gt_top_i_n_25;
  wire gt_top_i_n_296;
  wire gt_top_i_n_297;
  wire gt_top_i_n_298;
  wire gt_top_i_n_299;
  wire gt_top_i_n_300;
  wire gt_top_i_n_301;
  wire gt_top_i_n_302;
  wire gt_top_i_n_303;
  wire gt_top_i_n_304;
  wire gt_top_i_n_305;
  wire gt_top_i_n_306;
  wire gt_top_i_n_307;
  wire gt_top_i_n_308;
  wire gt_top_i_n_309;
  wire gt_top_i_n_310;
  wire gt_top_i_n_311;
  wire gt_top_i_n_312;
  wire gt_top_i_n_313;
  wire gt_top_i_n_314;
  wire gt_top_i_n_315;
  wire gt_top_i_n_316;
  wire gt_top_i_n_317;
  wire gt_top_i_n_318;
  wire gt_top_i_n_319;
  wire gt_top_i_n_874;
  wire int_mmcm_lock_out;
  wire [7:0]int_pclk_sel_slave;
  wire [1:0]int_qplllock_out;
  wire [1:0]int_qplloutclk_out;
  wire [1:0]int_qplloutrefclk_out;
  wire [63:0]m_axis_rx_tdata;
  wire [7:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [21:0]m_axis_rx_tuser;
  wire m_axis_rx_tvalid;
  wire [1:0]out;
  wire [7:0]pci_exp_rxn;
  wire [7:0]pci_exp_rxp;
  wire [7:0]pci_exp_txn;
  wire [7:0]pci_exp_txp;
  wire [8:0]pcie_drp_addr;
  wire pcie_drp_clk;
  wire [15:0]pcie_drp_di;
  wire [15:0]pcie_drp_do;
  wire pcie_drp_en;
  wire pcie_drp_rdy;
  wire pcie_drp_we;
  wire pcie_top_i_n_184;
  wire pcie_top_i_n_185;
  wire pcie_top_i_n_186;
  wire pcie_top_i_n_187;
  wire pcie_top_i_n_188;
  wire pcie_top_i_n_189;
  wire pcie_top_i_n_190;
  wire pcie_top_i_n_191;
  wire pcie_top_i_n_192;
  wire pcie_top_i_n_34;
  wire pcie_top_i_n_35;
  wire pcie_top_i_n_36;
  wire pcie_top_i_n_37;
  wire pcie_top_i_n_449;
  wire pcie_top_i_n_53;
  wire pcie_top_i_n_6;
  wire pcie_top_i_n_7;
  wire pcie_top_i_n_8;
  wire phy_rdy_n;
  wire [7:0]pipe_cpll_lock;
  wire [63:0]pipe_dmonitorout;
  wire [7:0]pipe_eyescandataerror;
  wire pipe_mmcm_rst_n;
  wire [7:0]pipe_pclk_sel_out;
  wire [3:0]pipe_qrst_fsm;
  wire pipe_qrst_idle;
  wire pipe_rate_idle;
  wire [3:0]pipe_rst_fsm;
  wire pipe_rx0_chanisaligned;
  wire [1:0]pipe_rx0_char_is_k;
  wire [15:0]pipe_rx0_data;
  wire pipe_rx0_polarity;
  wire pipe_rx0_valid;
  wire pipe_rx1_chanisaligned;
  wire [1:0]pipe_rx1_char_is_k;
  wire [15:0]pipe_rx1_data;
  wire pipe_rx1_polarity;
  wire pipe_rx1_valid;
  wire pipe_rx2_chanisaligned;
  wire [1:0]pipe_rx2_char_is_k;
  wire [15:0]pipe_rx2_data;
  wire pipe_rx2_polarity;
  wire pipe_rx2_valid;
  wire pipe_rx3_chanisaligned;
  wire [1:0]pipe_rx3_char_is_k;
  wire [15:0]pipe_rx3_data;
  wire pipe_rx3_polarity;
  wire pipe_rx3_valid;
  wire pipe_rx4_chanisaligned;
  wire [1:0]pipe_rx4_char_is_k;
  wire [15:0]pipe_rx4_data;
  wire pipe_rx4_polarity;
  wire pipe_rx4_valid;
  wire pipe_rx5_chanisaligned;
  wire [1:0]pipe_rx5_char_is_k;
  wire [15:0]pipe_rx5_data;
  wire pipe_rx5_polarity;
  wire pipe_rx5_valid;
  wire pipe_rx6_chanisaligned;
  wire [1:0]pipe_rx6_char_is_k;
  wire [15:0]pipe_rx6_data;
  wire pipe_rx6_polarity;
  wire pipe_rx6_valid;
  wire pipe_rx7_chanisaligned;
  wire [1:0]pipe_rx7_char_is_k;
  wire [15:0]pipe_rx7_data;
  wire pipe_rx7_polarity;
  wire pipe_rx7_valid;
  wire [23:0]pipe_rxbufstatus;
  wire [7:0]pipe_rxcommadet;
  wire [63:0]pipe_rxdisperr;
  wire [7:0]pipe_rxdlysresetdone;
  wire [63:0]pipe_rxnotintable;
  wire [7:0]pipe_rxoutclk_out;
  wire [7:0]pipe_rxphaligndone;
  wire [7:0]pipe_rxprbserr;
  wire [23:0]pipe_rxstatus;
  wire [55:0]pipe_sync_fsm_rx;
  wire [1:0]pipe_tx0_char_is_k;
  wire pipe_tx0_compliance;
  wire [15:0]pipe_tx0_data;
  wire pipe_tx0_elec_idle;
  wire [1:0]pipe_tx0_powerdown;
  wire [1:0]pipe_tx1_char_is_k;
  wire pipe_tx1_compliance;
  wire [15:0]pipe_tx1_data;
  wire pipe_tx1_elec_idle;
  wire [1:0]pipe_tx1_powerdown;
  wire [1:0]pipe_tx2_char_is_k;
  wire pipe_tx2_compliance;
  wire [15:0]pipe_tx2_data;
  wire pipe_tx2_elec_idle;
  wire [1:0]pipe_tx2_powerdown;
  wire [1:0]pipe_tx3_char_is_k;
  wire pipe_tx3_compliance;
  wire [15:0]pipe_tx3_data;
  wire pipe_tx3_elec_idle;
  wire [1:0]pipe_tx3_powerdown;
  wire [1:0]pipe_tx4_char_is_k;
  wire pipe_tx4_compliance;
  wire [15:0]pipe_tx4_data;
  wire pipe_tx4_elec_idle;
  wire [1:0]pipe_tx4_powerdown;
  wire [1:0]pipe_tx5_char_is_k;
  wire pipe_tx5_compliance;
  wire [15:0]pipe_tx5_data;
  wire pipe_tx5_elec_idle;
  wire [1:0]pipe_tx5_powerdown;
  wire [1:0]pipe_tx6_char_is_k;
  wire pipe_tx6_compliance;
  wire [15:0]pipe_tx6_data;
  wire pipe_tx6_elec_idle;
  wire [1:0]pipe_tx6_powerdown;
  wire [1:0]pipe_tx7_char_is_k;
  wire pipe_tx7_compliance;
  wire [15:0]pipe_tx7_data;
  wire pipe_tx7_elec_idle;
  wire [1:0]pipe_tx7_powerdown;
  wire pipe_tx_deemph;
  wire [2:0]pipe_tx_margin;
  wire pipe_tx_rate;
  wire pipe_tx_rcvr_det;
  wire [7:0]pipe_txdlysresetdone;
  wire [7:0]pipe_txinhibit;
  wire pipe_txoutclk_out;
  wire [7:0]pipe_txphaligndone;
  wire [7:0]pipe_txphinitdone;
  wire pl_directed_change_done;
  wire pl_directed_link_auton;
  wire [1:0]pl_directed_link_change;
  wire pl_directed_link_speed;
  wire [1:0]pl_directed_link_width;
  wire pl_downstream_deemph_source;
  wire [2:0]pl_initial_link_width;
  wire [1:0]pl_lane_reversal_mode;
  wire pl_link_gen2_cap;
  wire pl_link_partner_gen2_supported;
  wire pl_link_upcfg_cap;
  wire [5:0]pl_ltssm_state;
  wire pl_phy_lnk_up;
  wire pl_received_hot_rst;
  wire [1:0]pl_rx_pm_state;
  wire pl_sel_lnk_rate;
  wire [1:0]pl_sel_lnk_width;
  wire pl_transmit_hot_rst;
  wire [2:0]pl_tx_pm_state;
  wire pl_upstream_prefer_deemph;
  wire rx_np_ok;
  wire rx_np_req;
  wire [63:0]s_axis_tx_tdata;
  wire [0:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tready;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire sys_clk;
  wire sys_rst_n;
  wire sys_rst_n_0;
  wire trn_lnk_up;
  wire [5:0]tx_buf_av;
  wire tx_cfg_gnt;
  wire tx_cfg_req;
  wire tx_err_drop;
  wire user_lnk_up;
  wire user_lnk_up_d;
  wire user_reset_out;
  wire user_reset_out_i_1_n_0;

  PCIeGen1x8If64_PCIeGen1x8If64_gt_top gt_top_i
       (.CLK_DCLK(ext_ch_gt_drpclk),
        .CLK_MMCM_LOCK(int_mmcm_lock_out),
        .CLK_PCLK(INT_OOBCLK_OUT),
        .CLK_USERCLK1(INT_USERCLK2_OUT),
        .D(pipe_rx0_char_is_k),
        .INT_QPLLOUTCLK_OUT(int_qplloutclk_out),
        .INT_QPLLOUTREFCLK_OUT(int_qplloutrefclk_out),
        .PIPE_CPLL_LOCK(pipe_cpll_lock),
        .PIPE_POWERDOWN({pipe_tx7_powerdown,pipe_tx6_powerdown,pipe_tx5_powerdown,pipe_tx4_powerdown,pipe_tx3_powerdown,pipe_tx2_powerdown,pipe_tx1_powerdown,pipe_tx0_powerdown}),
        .PIPE_QPLL_LOCK(int_qplllock_out),
        .PIPE_RXCHANISALIGNED({pipe_rx7_chanisaligned,pipe_rx6_chanisaligned,pipe_rx5_chanisaligned,pipe_rx4_chanisaligned,pipe_rx3_chanisaligned,pipe_rx2_chanisaligned,pipe_rx1_chanisaligned,pipe_rx0_chanisaligned}),
        .PIPE_RXPOLARITY({pipe_rx7_polarity,pipe_rx6_polarity,pipe_rx5_polarity,pipe_rx4_polarity,pipe_rx3_polarity,pipe_rx2_polarity,pipe_rx1_polarity,pipe_rx0_polarity}),
        .PIPE_TXCOMPLIANCE({pipe_tx7_compliance,pipe_tx6_compliance,pipe_tx5_compliance,pipe_tx4_compliance,pipe_tx3_compliance,pipe_tx2_compliance,pipe_tx1_compliance,pipe_tx0_compliance}),
        .PIPE_TXDATA({pipe_tx7_data,pipe_tx6_data,pipe_tx5_data,pipe_tx4_data,pipe_tx3_data,pipe_tx2_data,pipe_tx1_data,pipe_tx0_data}),
        .PIPE_TXDATAK({pipe_tx7_char_is_k,pipe_tx6_char_is_k,pipe_tx5_char_is_k,pipe_tx4_char_is_k,pipe_tx3_char_is_k,pipe_tx2_char_is_k,pipe_tx1_char_is_k,pipe_tx0_char_is_k}),
        .PIPE_TXDEEMPH({pcie_top_i_n_6,pcie_top_i_n_7,pcie_top_i_n_8,pipe_tx_deemph}),
        .PIPE_TXDETECTRX(pcie_top_i_n_36),
        .PIPE_TXELECIDLE({pipe_tx7_elec_idle,pipe_tx6_elec_idle,pipe_tx5_elec_idle,pipe_tx4_elec_idle,pipe_tx3_elec_idle,pipe_tx2_elec_idle,pipe_tx1_elec_idle,pipe_tx0_elec_idle}),
        .PIPE_TXMARGIN({pcie_top_i_n_190,pcie_top_i_n_191,pcie_top_i_n_192}),
        .Q(phy_rdy_n),
        .TXMARGIN({pcie_top_i_n_187,pcie_top_i_n_188,pcie_top_i_n_189}),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo),
        .ext_ch_gt_drpen(ext_ch_gt_drpen),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe),
        .gt_ch_drp_rdy(gt_ch_drp_rdy),
        .gt_rx_phy_status_q(gt_rx_phy_status_q),
        .gt_rxelecidle_q(gt_rxelecidle_q),
        .\index_reg[1] (PIPE_DRP_FSM[2:0]),
        .\index_reg[1]_0 (PIPE_DRP_FSM[5:3]),
        .\index_reg[1]_1 (PIPE_DRP_FSM[8:6]),
        .\index_reg[1]_2 (PIPE_DRP_FSM[11:9]),
        .\index_reg[1]_3 (PIPE_DRP_FSM[14:12]),
        .\index_reg[1]_4 (PIPE_DRP_FSM[17:15]),
        .\index_reg[1]_5 (PIPE_DRP_FSM[20:18]),
        .\index_reg[1]_6 (PIPE_DRP_FSM[23:21]),
        .int_pclk_sel_slave(int_pclk_sel_slave),
        .out(out),
        .pci_exp_rxn(pci_exp_rxn),
        .pci_exp_rxp(pci_exp_rxp),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .pclk_sel_reg1_reg(pipe_pclk_sel_out),
        .pipe_dmonitorout(pipe_dmonitorout),
        .pipe_eyescandataerror(pipe_eyescandataerror),
        .pipe_mmcm_rst_n(pipe_mmcm_rst_n),
        .pipe_qrst_fsm(pipe_qrst_fsm),
        .pipe_qrst_idle(pipe_qrst_idle),
        .pipe_rate_idle(pipe_rate_idle),
        .pipe_rst_fsm(pipe_rst_fsm),
        .pipe_rx0_valid(pipe_rx0_valid),
        .pipe_rx1_valid(pipe_rx1_valid),
        .pipe_rx2_valid(pipe_rx2_valid),
        .pipe_rx3_valid(pipe_rx3_valid),
        .pipe_rx4_valid(pipe_rx4_valid),
        .pipe_rx5_valid(pipe_rx5_valid),
        .pipe_rx6_valid(pipe_rx6_valid),
        .pipe_rx7_valid(pipe_rx7_valid),
        .pipe_rxbufstatus(pipe_rxbufstatus),
        .pipe_rxcommadet(pipe_rxcommadet),
        .pipe_rxdisperr(pipe_rxdisperr),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone),
        .pipe_rxnotintable(pipe_rxnotintable),
        .pipe_rxoutclk_out(pipe_rxoutclk_out),
        .pipe_rxphaligndone(pipe_rxphaligndone),
        .pipe_rxprbserr(pipe_rxprbserr),
        .pipe_rxstatus(pipe_rxstatus),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (pipe_rx1_char_is_k),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (pipe_rx2_char_is_k),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 (pipe_rx3_char_is_k),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 (pipe_rx4_char_is_k),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 (pipe_rx5_char_is_k),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 (pipe_rx6_char_is_k),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5 (pipe_rx7_char_is_k),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (pipe_rx0_data),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (pipe_rx1_data),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (pipe_rx2_data),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_2 (pipe_rx3_data),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_3 (pipe_rx4_data),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_4 (pipe_rx5_data),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_5 (pipe_rx6_data),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_6 (pipe_rx7_data),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg (gt_top_i_n_13),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 (gt_top_i_n_15),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg_1 (gt_top_i_n_17),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg_2 (gt_top_i_n_19),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg_3 (gt_top_i_n_21),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg_4 (gt_top_i_n_23),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg_5 (gt_top_i_n_25),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg (gt_top_i_n_12),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg_0 (gt_top_i_n_14),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg_1 (gt_top_i_n_16),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg_2 (gt_top_i_n_18),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg_3 (gt_top_i_n_20),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg_4 (gt_top_i_n_22),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg_5 (gt_top_i_n_24),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] ({gt_top_i_n_296,gt_top_i_n_297,gt_top_i_n_298}),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ({gt_top_i_n_299,gt_top_i_n_300,gt_top_i_n_301}),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ({gt_top_i_n_302,gt_top_i_n_303,gt_top_i_n_304}),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ({gt_top_i_n_305,gt_top_i_n_306,gt_top_i_n_307}),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_3 ({gt_top_i_n_308,gt_top_i_n_309,gt_top_i_n_310}),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_4 ({gt_top_i_n_311,gt_top_i_n_312,gt_top_i_n_313}),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_5 ({gt_top_i_n_314,gt_top_i_n_315,gt_top_i_n_316}),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_6 ({gt_top_i_n_317,gt_top_i_n_318,gt_top_i_n_319}),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2] (pipe_tx_margin),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ({pcie_top_i_n_184,pcie_top_i_n_185,pcie_top_i_n_186}),
        .\pipe_stages_1.pipe_tx_rate_q_reg (pipe_tx_rate),
        .\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep (pcie_top_i_n_34),
        .\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 (pcie_top_i_n_35),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det),
        .pipe_txdlysresetdone(pipe_txdlysresetdone),
        .pipe_txinhibit(pipe_txinhibit),
        .pipe_txoutclk_out(pipe_txoutclk_out),
        .pipe_txphaligndone(pipe_txphaligndone),
        .pipe_txphinitdone(pipe_txphinitdone),
        .pl_ltssm_state(pl_ltssm_state),
        .rate_gen3(EQ_GEN3),
        .reset_n_reg2_reg(gt_top_i_n_874),
        .sys_clk(sys_clk),
        .sys_rst_n(sys_rst_n_0),
        .sys_rst_n_0(sys_rst_n),
        .\sysclksel_reg[1] (PIPE_RATE_FSM[4:0]),
        .\sysclksel_reg[1]_0 (PIPE_RATE_FSM[9:5]),
        .\sysclksel_reg[1]_1 (PIPE_RATE_FSM[14:10]),
        .\sysclksel_reg[1]_2 (PIPE_RATE_FSM[19:15]),
        .\sysclksel_reg[1]_3 (PIPE_RATE_FSM[24:20]),
        .\sysclksel_reg[1]_4 (PIPE_RATE_FSM[29:25]),
        .\sysclksel_reg[1]_5 (PIPE_RATE_FSM[34:30]),
        .\sysclksel_reg[1]_6 (PIPE_RATE_FSM[39:35]),
        .\txsync_fsm.txdlyen_reg (PIPE_SYNC_FSM_TX[11:6]),
        .\txsync_fsm.txdlyen_reg_0 (PIPE_SYNC_FSM_TX[17:12]),
        .\txsync_fsm.txdlyen_reg_1 (PIPE_SYNC_FSM_TX[23:18]),
        .\txsync_fsm.txdlyen_reg_2 (PIPE_SYNC_FSM_TX[29:24]),
        .\txsync_fsm.txdlyen_reg_3 (PIPE_SYNC_FSM_TX[35:30]),
        .\txsync_fsm.txdlyen_reg_4 (PIPE_SYNC_FSM_TX[41:36]),
        .\txsync_fsm.txdlyen_reg_5 (PIPE_SYNC_FSM_TX[47:42]),
        .\txsync_fsm.txsync_done_reg (PIPE_SYNC_FSM_TX[5:0]));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_32
       (.I0(cfg_mgmt_byte_en[3]),
        .O(cfg_mgmt_byte_en_n[3]));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_33
       (.I0(cfg_mgmt_byte_en[2]),
        .O(cfg_mgmt_byte_en_n[2]));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_34
       (.I0(cfg_mgmt_byte_en[1]),
        .O(cfg_mgmt_byte_en_n[1]));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_35
       (.I0(cfg_mgmt_byte_en[0]),
        .O(cfg_mgmt_byte_en_n[0]));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_top pcie_top_i
       (.CLK(INT_OOBCLK_OUT),
        .D(pipe_rx0_char_is_k),
        .PIPE_POWERDOWN({pipe_tx7_powerdown,pipe_tx6_powerdown,pipe_tx5_powerdown,pipe_tx4_powerdown,pipe_tx3_powerdown,pipe_tx2_powerdown,pipe_tx1_powerdown,pipe_tx0_powerdown}),
        .PIPE_RXCHANISALIGNED({pipe_rx7_chanisaligned,pipe_rx6_chanisaligned,pipe_rx5_chanisaligned,pipe_rx4_chanisaligned,pipe_rx3_chanisaligned,pipe_rx2_chanisaligned,pipe_rx1_chanisaligned,pipe_rx0_chanisaligned}),
        .PIPE_RXPOLARITY({pipe_rx7_polarity,pipe_rx6_polarity,pipe_rx5_polarity,pipe_rx4_polarity,pipe_rx3_polarity,pipe_rx2_polarity,pipe_rx1_polarity,pipe_rx0_polarity}),
        .PIPE_TXCOMPLIANCE({pipe_tx7_compliance,pipe_tx6_compliance,pipe_tx5_compliance,pipe_tx4_compliance,pipe_tx3_compliance,pipe_tx2_compliance,pipe_tx1_compliance,pipe_tx0_compliance}),
        .PIPE_TXDATA({pipe_tx7_data,pipe_tx6_data,pipe_tx5_data,pipe_tx4_data,pipe_tx3_data,pipe_tx2_data,pipe_tx1_data,pipe_tx0_data}),
        .PIPE_TXDATAK({pipe_tx7_char_is_k,pipe_tx6_char_is_k,pipe_tx5_char_is_k,pipe_tx4_char_is_k,pipe_tx3_char_is_k,pipe_tx2_char_is_k,pipe_tx1_char_is_k,pipe_tx0_char_is_k}),
        .PIPE_TXDEEMPH({pcie_top_i_n_6,pcie_top_i_n_7,pcie_top_i_n_8,pipe_tx_deemph}),
        .PIPE_TXELECIDLE({pipe_tx7_elec_idle,pipe_tx6_elec_idle,pipe_tx5_elec_idle,pipe_tx4_elec_idle,pipe_tx3_elec_idle,pipe_tx2_elec_idle,pipe_tx1_elec_idle,pipe_tx0_elec_idle}),
        .PIPE_TXMARGIN({pcie_top_i_n_190,pcie_top_i_n_191,pcie_top_i_n_192}),
        .Q(pipe_tx_margin),
        .TXMARGIN({pcie_top_i_n_187,pcie_top_i_n_188,pcie_top_i_n_189}),
        .bridge_reset_int(bridge_reset_int),
        .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en),
        .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en),
        .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
        .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received),
        .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en),
        .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received),
        .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en),
        .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received),
        .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en),
        .cfg_bridge_serr_en(cfg_bridge_serr_en),
        .cfg_bus_number(cfg_bus_number),
        .cfg_command(cfg_command),
        .cfg_dcommand(cfg_dcommand),
        .cfg_dcommand2(cfg_dcommand2),
        .cfg_device_number(cfg_device_number),
        .cfg_ds_bus_number(cfg_ds_bus_number),
        .cfg_ds_device_number(cfg_ds_device_number),
        .cfg_ds_function_number(cfg_ds_function_number),
        .cfg_dsn(cfg_dsn),
        .cfg_dstatus(cfg_dstatus),
        .cfg_err_aer_headerlog(cfg_err_aer_headerlog),
        .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set),
        .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked),
        .cfg_err_cor(cfg_err_cor),
        .cfg_err_cpl_abort(cfg_err_cpl_abort),
        .cfg_err_cpl_rdy(cfg_err_cpl_rdy),
        .cfg_err_cpl_timeout(cfg_err_cpl_timeout),
        .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect),
        .cfg_err_ecrc(cfg_err_ecrc),
        .cfg_err_internal_cor(cfg_err_internal_cor),
        .cfg_err_internal_uncor(cfg_err_internal_uncor),
        .cfg_err_locked(cfg_err_locked),
        .cfg_err_malformed(cfg_err_malformed),
        .cfg_err_mc_blocked(cfg_err_mc_blocked),
        .cfg_err_norecovery(cfg_err_norecovery),
        .cfg_err_poisoned(cfg_err_poisoned),
        .cfg_err_posted(cfg_err_posted),
        .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
        .cfg_err_ur(cfg_err_ur),
        .cfg_function_number(cfg_function_number),
        .cfg_interrupt(cfg_interrupt),
        .cfg_interrupt_assert(cfg_interrupt_assert),
        .cfg_interrupt_di(cfg_interrupt_di),
        .cfg_interrupt_do(cfg_interrupt_do),
        .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
        .cfg_interrupt_msienable(cfg_interrupt_msienable),
        .cfg_interrupt_msixenable(cfg_interrupt_msixenable),
        .cfg_interrupt_msixfm(cfg_interrupt_msixfm),
        .cfg_interrupt_rdy(cfg_interrupt_rdy),
        .cfg_interrupt_stat(cfg_interrupt_stat),
        .cfg_lcommand(cfg_lcommand),
        .cfg_lstatus(cfg_lstatus),
        .cfg_mgmt_byte_en_n(cfg_mgmt_byte_en_n),
        .cfg_mgmt_di(cfg_mgmt_di),
        .cfg_mgmt_do(cfg_mgmt_do),
        .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
        .cfg_mgmt_rd_en(cfg_mgmt_rd_en),
        .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
        .cfg_mgmt_wr_en(cfg_mgmt_wr_en),
        .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
        .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw),
        .cfg_msg_data(cfg_msg_data),
        .cfg_msg_received(cfg_msg_received),
        .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a),
        .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b),
        .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c),
        .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d),
        .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a),
        .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b),
        .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c),
        .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d),
        .cfg_msg_received_err_cor(cfg_msg_received_err_cor),
        .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal),
        .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal),
        .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak),
        .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme),
        .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack),
        .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit),
        .cfg_pcie_link_state(cfg_pcie_link_state),
        .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
        .cfg_pm_force_state(cfg_pm_force_state),
        .cfg_pm_force_state_en(cfg_pm_force_state_en),
        .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s),
        .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1),
        .cfg_pm_wake(cfg_pm_wake),
        .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en),
        .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status),
        .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate),
        .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst),
        .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en),
        .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en),
        .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en),
        .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en),
        .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_trn_pending(cfg_trn_pending),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .cfg_vc_tcvc_map(cfg_vc_tcvc_map),
        .\cplllock_reg1_reg[2] (pcie_top_i_n_35),
        .\cplllock_reg1_reg[3] (pcie_top_i_n_34),
        .\cplllock_reg1_reg[3]_0 ({pcie_top_i_n_184,pcie_top_i_n_185,pcie_top_i_n_186}),
        .\cplllock_reg1_reg[6] (pcie_top_i_n_36),
        .fc_cpld(fc_cpld),
        .fc_cplh(fc_cplh),
        .fc_npd(fc_npd),
        .fc_nph(fc_nph),
        .fc_pd(fc_pd),
        .fc_ph(fc_ph),
        .fc_sel(fc_sel),
        .gt_rx_phy_status_q(gt_rx_phy_status_q),
        .gt_rx_phy_status_q_reg(gt_top_i_n_12),
        .gt_rx_phy_status_q_reg_0(gt_top_i_n_14),
        .gt_rx_phy_status_q_reg_1(gt_top_i_n_16),
        .gt_rx_phy_status_q_reg_2(gt_top_i_n_18),
        .gt_rx_phy_status_q_reg_3(gt_top_i_n_20),
        .gt_rx_phy_status_q_reg_4(gt_top_i_n_22),
        .gt_rx_phy_status_q_reg_5(gt_top_i_n_24),
        .\gt_rx_status_q_reg[2] ({gt_top_i_n_296,gt_top_i_n_297,gt_top_i_n_298}),
        .\gt_rx_status_q_reg[2]_0 ({gt_top_i_n_299,gt_top_i_n_300,gt_top_i_n_301}),
        .\gt_rx_status_q_reg[2]_1 ({gt_top_i_n_302,gt_top_i_n_303,gt_top_i_n_304}),
        .\gt_rx_status_q_reg[2]_2 ({gt_top_i_n_305,gt_top_i_n_306,gt_top_i_n_307}),
        .\gt_rx_status_q_reg[2]_3 ({gt_top_i_n_308,gt_top_i_n_309,gt_top_i_n_310}),
        .\gt_rx_status_q_reg[2]_4 ({gt_top_i_n_311,gt_top_i_n_312,gt_top_i_n_313}),
        .\gt_rx_status_q_reg[2]_5 ({gt_top_i_n_314,gt_top_i_n_315,gt_top_i_n_316}),
        .\gt_rx_status_q_reg[2]_6 ({gt_top_i_n_317,gt_top_i_n_318,gt_top_i_n_319}),
        .\gt_rxcharisk_q_reg[1] (pipe_rx1_char_is_k),
        .\gt_rxcharisk_q_reg[1]_0 (pipe_rx2_char_is_k),
        .\gt_rxcharisk_q_reg[1]_1 (pipe_rx3_char_is_k),
        .\gt_rxcharisk_q_reg[1]_2 (pipe_rx4_char_is_k),
        .\gt_rxcharisk_q_reg[1]_3 (pipe_rx5_char_is_k),
        .\gt_rxcharisk_q_reg[1]_4 (pipe_rx6_char_is_k),
        .\gt_rxcharisk_q_reg[1]_5 (pipe_rx7_char_is_k),
        .\gt_rxdata_q_reg[15] (pipe_rx0_data),
        .\gt_rxdata_q_reg[15]_0 (pipe_rx1_data),
        .\gt_rxdata_q_reg[15]_1 (pipe_rx2_data),
        .\gt_rxdata_q_reg[15]_2 (pipe_rx3_data),
        .\gt_rxdata_q_reg[15]_3 (pipe_rx4_data),
        .\gt_rxdata_q_reg[15]_4 (pipe_rx5_data),
        .\gt_rxdata_q_reg[15]_5 (pipe_rx6_data),
        .\gt_rxdata_q_reg[15]_6 (pipe_rx7_data),
        .gt_rxelecidle_q(gt_rxelecidle_q),
        .gt_rxelecidle_q_reg(gt_top_i_n_13),
        .gt_rxelecidle_q_reg_0(gt_top_i_n_15),
        .gt_rxelecidle_q_reg_1(gt_top_i_n_17),
        .gt_rxelecidle_q_reg_2(gt_top_i_n_19),
        .gt_rxelecidle_q_reg_3(gt_top_i_n_21),
        .gt_rxelecidle_q_reg_4(gt_top_i_n_23),
        .gt_rxelecidle_q_reg_5(gt_top_i_n_25),
        .m_axis_rx_tdata(m_axis_rx_tdata),
        .m_axis_rx_tkeep(m_axis_rx_tkeep),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser),
        .m_axis_rx_tvalid(m_axis_rx_tvalid),
        .pcie_drp_addr(pcie_drp_addr),
        .pcie_drp_clk(pcie_drp_clk),
        .pcie_drp_di(pcie_drp_di),
        .pcie_drp_do(pcie_drp_do),
        .pcie_drp_en(pcie_drp_en),
        .pcie_drp_rdy(pcie_drp_rdy),
        .pcie_drp_we(pcie_drp_we),
        .phy_rdy_n(phy_rdy_n),
        .pipe_rx0_valid(pipe_rx0_valid),
        .pipe_rx1_valid(pipe_rx1_valid),
        .pipe_rx2_valid(pipe_rx2_valid),
        .pipe_rx3_valid(pipe_rx3_valid),
        .pipe_rx4_valid(pipe_rx4_valid),
        .pipe_rx5_valid(pipe_rx5_valid),
        .pipe_rx6_valid(pipe_rx6_valid),
        .pipe_rx7_valid(pipe_rx7_valid),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det),
        .pl_directed_change_done(pl_directed_change_done),
        .pl_directed_link_auton(pl_directed_link_auton),
        .pl_directed_link_change(pl_directed_link_change),
        .pl_directed_link_speed(pl_directed_link_speed),
        .pl_directed_link_width(pl_directed_link_width),
        .pl_downstream_deemph_source(pl_downstream_deemph_source),
        .pl_initial_link_width(pl_initial_link_width),
        .pl_lane_reversal_mode(pl_lane_reversal_mode),
        .pl_link_gen2_cap(pl_link_gen2_cap),
        .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported),
        .pl_link_upcfg_cap(pl_link_upcfg_cap),
        .pl_ltssm_state(pl_ltssm_state),
        .pl_phy_lnk_up(pl_phy_lnk_up),
        .pl_phy_lnk_up_q_reg(pcie_top_i_n_53),
        .pl_received_hot_rst(pcie_top_i_n_449),
        .pl_rx_pm_state(pl_rx_pm_state),
        .pl_sel_lnk_rate(pl_sel_lnk_rate),
        .pl_sel_lnk_width(pl_sel_lnk_width),
        .pl_transmit_hot_rst(pl_transmit_hot_rst),
        .pl_tx_pm_state(pl_tx_pm_state),
        .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
        .\rate_reg1_reg[0] (pipe_tx_rate),
        .rx_np_ok(rx_np_ok),
        .rx_np_req(rx_np_req),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tready(s_axis_tx_tready),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .sys_rst_n(sys_rst_n_0),
        .trn_lnk_up(trn_lnk_up),
        .trn_tbuf_av(tx_buf_av),
        .trn_tcfg_req(tx_cfg_req),
        .tx_cfg_gnt(tx_cfg_gnt),
        .tx_err_drop(tx_err_drop),
        .user_clk(INT_USERCLK2_OUT),
        .user_lnk_up_int_reg(user_lnk_up),
        .user_reset_int_reg(pcie_top_i_n_37),
        .user_reset_out_reg(user_reset_out));
  FDRE pl_phy_lnk_up_q_reg
       (.C(INT_USERCLK2_OUT),
        .CE(1'b1),
        .D(pcie_top_i_n_53),
        .Q(pl_phy_lnk_up),
        .R(gt_top_i_n_874));
  FDRE pl_received_hot_rst_q_reg
       (.C(INT_USERCLK2_OUT),
        .CE(1'b1),
        .D(pcie_top_i_n_449),
        .Q(pl_received_hot_rst),
        .R(gt_top_i_n_874));
  FDRE user_lnk_up_d_reg
       (.C(INT_USERCLK2_OUT),
        .CE(1'b1),
        .D(trn_lnk_up),
        .Q(user_lnk_up_d),
        .R(gt_top_i_n_874));
  FDRE user_lnk_up_int_reg
       (.C(INT_USERCLK2_OUT),
        .CE(1'b1),
        .D(user_lnk_up_d),
        .Q(user_lnk_up),
        .R(gt_top_i_n_874));
  FDPE user_reset_int_reg
       (.C(INT_USERCLK2_OUT),
        .CE(1'b1),
        .D(pcie_top_i_n_37),
        .PRE(user_reset_out_i_1_n_0),
        .Q(bridge_reset_int));
  LUT2 #(
    .INIT(4'hB)) 
    user_reset_out_i_1
       (.I0(pl_received_hot_rst),
        .I1(sys_rst_n),
        .O(user_reset_out_i_1_n_0));
  FDPE user_reset_out_reg
       (.C(INT_USERCLK2_OUT),
        .CE(1'b1),
        .D(bridge_reset_int),
        .PRE(user_reset_out_i_1_n_0),
        .Q(user_reset_out));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_common" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_common
   (RATE_QPLLLOCK,
    \cplllock_reg1_reg[3] ,
    \cplllock_reg1_reg[3]_0 ,
    DRP_DONE,
    \resetovrd_disble.reset_reg[4] ,
    sys_clk,
    qpllpd,
    qrst_qpllreset,
    RST_DCLK_RESET,
    DRP_START,
    O1687,
    DRP_OVRD);
  output RATE_QPLLLOCK;
  output \cplllock_reg1_reg[3] ;
  output \cplllock_reg1_reg[3]_0 ;
  output DRP_DONE;
  input \resetovrd_disble.reset_reg[4] ;
  input sys_clk;
  input qpllpd;
  input qrst_qpllreset;
  input RST_DCLK_RESET;
  input DRP_START;
  input O1687;
  input DRP_OVRD;

  wire DRP_DONE;
  wire DRP_OVRD;
  wire DRP_START;
  wire O1687;
  wire QPLL_QPLLRESET0126_out;
  wire RATE_QPLLLOCK;
  wire RST_DCLK_RESET;
  wire \cplllock_reg1_reg[3] ;
  wire \cplllock_reg1_reg[3]_0 ;
  wire [7:0]qpll_drp_addr;
  wire [15:0]qpll_drp_di;
  wire [15:0]qpll_drp_do;
  wire qpll_drp_en;
  wire qpll_drp_rdy;
  wire qpll_drp_we;
  wire qpllpd;
  wire qrst_qpllreset;
  wire \resetovrd_disble.reset_reg[4] ;
  wire sys_clk;

  PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp_84 qpll_drp_i
       (.DRP_ADDR(qpll_drp_addr),
        .DRP_DI(qpll_drp_di),
        .DRP_DO(qpll_drp_do),
        .DRP_DONE(DRP_DONE),
        .DRP_OVRD(DRP_OVRD),
        .DRP_RDY(qpll_drp_rdy),
        .DRP_START(DRP_START),
        .O1687(O1687),
        .QPLL_QPLLRESET0126_out(QPLL_QPLLRESET0126_out),
        .RATE_QPLLLOCK(RATE_QPLLLOCK),
        .RST_DCLK_RESET(RST_DCLK_RESET),
        .qpll_drp_en(qpll_drp_en),
        .qpll_drp_we(qpll_drp_we),
        .qrst_qpllreset(qrst_qpllreset),
        .\resetovrd_disble.reset_reg[4] (\resetovrd_disble.reset_reg[4] ));
  PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper_85 qpll_wrapper_i
       (.DRP_ADDR(qpll_drp_addr),
        .DRP_DI(qpll_drp_di),
        .DRP_DO(qpll_drp_do),
        .QPLL_QPLLRESET0126_out(QPLL_QPLLRESET0126_out),
        .RATE_QPLLLOCK(RATE_QPLLLOCK),
        .\cplllock_reg1_reg[3] (\cplllock_reg1_reg[3] ),
        .\cplllock_reg1_reg[3]_0 (\cplllock_reg1_reg[3]_0 ),
        .qpll_drp_en(qpll_drp_en),
        .qpll_drp_rdy(qpll_drp_rdy),
        .qpll_drp_we(qpll_drp_we),
        .qpllpd(qpllpd),
        .\resetovrd_disble.reset_reg[4] (\resetovrd_disble.reset_reg[4] ),
        .sys_clk(sys_clk));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_common" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_common_50
   (RATE_QPLLLOCK,
    \cplllock_reg1_reg[7] ,
    \cplllock_reg1_reg[7]_0 ,
    DRP_DONE,
    \resetovrd_disble.reset_reg[4] ,
    sys_clk,
    qpllpd,
    qrst_qpllreset,
    RST_DCLK_RESET,
    DRP_START,
    DRP_GEN3,
    DRP_OVRD);
  output RATE_QPLLLOCK;
  output \cplllock_reg1_reg[7] ;
  output \cplllock_reg1_reg[7]_0 ;
  output DRP_DONE;
  input \resetovrd_disble.reset_reg[4] ;
  input sys_clk;
  input qpllpd;
  input qrst_qpllreset;
  input RST_DCLK_RESET;
  input DRP_START;
  input DRP_GEN3;
  input DRP_OVRD;

  wire DRP_DONE;
  wire DRP_GEN3;
  wire DRP_OVRD;
  wire DRP_START;
  wire QPLL_QPLLRESET0;
  wire RATE_QPLLLOCK;
  wire RST_DCLK_RESET;
  wire \cplllock_reg1_reg[7] ;
  wire \cplllock_reg1_reg[7]_0 ;
  wire [7:0]qpll_drp_addr;
  wire [15:0]qpll_drp_di;
  wire [15:0]qpll_drp_do;
  wire qpll_drp_en;
  wire qpll_drp_rdy;
  wire qpll_drp_we;
  wire qpllpd;
  wire qrst_qpllreset;
  wire \resetovrd_disble.reset_reg[4] ;
  wire sys_clk;

  PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp qpll_drp_i
       (.DRP_ADDR(qpll_drp_addr),
        .DRP_DI(qpll_drp_di),
        .DRP_DO(qpll_drp_do),
        .DRP_DONE(DRP_DONE),
        .DRP_GEN3(DRP_GEN3),
        .DRP_OVRD(DRP_OVRD),
        .DRP_RDY(qpll_drp_rdy),
        .DRP_START(DRP_START),
        .QPLL_QPLLRESET0(QPLL_QPLLRESET0),
        .RATE_QPLLLOCK(RATE_QPLLLOCK),
        .RST_DCLK_RESET(RST_DCLK_RESET),
        .qpll_drp_en(qpll_drp_en),
        .qpll_drp_we(qpll_drp_we),
        .qrst_qpllreset(qrst_qpllreset),
        .\resetovrd_disble.reset_reg[4] (\resetovrd_disble.reset_reg[4] ));
  PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper qpll_wrapper_i
       (.DRP_ADDR(qpll_drp_addr),
        .DRP_DI(qpll_drp_di),
        .DRP_DO(qpll_drp_do),
        .QPLL_QPLLRESET0(QPLL_QPLLRESET0),
        .RATE_QPLLLOCK(RATE_QPLLLOCK),
        .\cplllock_reg1_reg[7] (\cplllock_reg1_reg[7] ),
        .\cplllock_reg1_reg[7]_0 (\cplllock_reg1_reg[7]_0 ),
        .qpll_drp_en(qpll_drp_en),
        .qpll_drp_rdy(qpll_drp_rdy),
        .qpll_drp_we(qpll_drp_we),
        .qpllpd(qpllpd),
        .\resetovrd_disble.reset_reg[4] (\resetovrd_disble.reset_reg[4] ),
        .sys_clk(sys_clk));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_rx_valid_filter_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x
   (\pipe_stages_1.pipe_rx_valid_q_reg ,
    gt_rx_phy_status_q,
    gt_rxelecidle_q,
    \gt_rx_status_q_reg[2]_0 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    D,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    Q,
    CLK_PCLK,
    gt_rx_phy_status_wire_filter,
    PIPE_RXELECIDLE,
    gt_rxvalid_q_reg_0,
    \pl_ltssm_state_q_reg[5] ,
    PIPE_RXDATA,
    PIPE_RXDATAK,
    \pl_ltssm_state_q_reg[5]_0 );
  output \pipe_stages_1.pipe_rx_valid_q_reg ;
  output gt_rx_phy_status_q;
  output gt_rxelecidle_q;
  output \gt_rx_status_q_reg[2]_0 ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  output [1:0]D;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  input Q;
  input CLK_PCLK;
  input [0:0]gt_rx_phy_status_wire_filter;
  input [0:0]PIPE_RXELECIDLE;
  input gt_rxvalid_q_reg_0;
  input [5:0]\pl_ltssm_state_q_reg[5] ;
  input [15:0]PIPE_RXDATA;
  input [1:0]PIPE_RXDATAK;
  input [2:0]\pl_ltssm_state_q_reg[5]_0 ;

  wire CLK_PCLK;
  wire [1:0]D;
  wire \FSM_sequential_reg_state_eios_det[0]_i_1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_2_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_4_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_5_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_2_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_4_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_5_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[2] ;
  wire [15:0]PIPE_RXDATA;
  wire [1:0]PIPE_RXDATAK;
  wire [0:0]PIPE_RXELECIDLE;
  wire Q;
  wire gt_rx_phy_status_q;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire \gt_rx_status_q_reg[2]_0 ;
  wire \gt_rxcharisk_q_reg_n_0_[0] ;
  wire gt_rxelecidle_q;
  wire gt_rxvalid_q;
  wire gt_rxvalid_q_i_2_n_0;
  wire gt_rxvalid_q_i_3_n_0;
  wire gt_rxvalid_q_i_5_n_0;
  wire gt_rxvalid_q_reg_0;
  wire p_0_in;
  wire p_15_in;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire \pipe_stages_1.pipe_rx_valid_q_reg ;
  wire [5:0]\pl_ltssm_state_q_reg[5] ;
  wire [2:0]\pl_ltssm_state_q_reg[5]_0 ;
  wire reg_state_eios_det119_out;
  wire reg_symbol_after_eios;
  wire symbol_after_eios;

  LUT6 #(
    .INIT(64'hFF73FFF3FF7FFFFF)) 
    \FSM_sequential_reg_state_eios_det[0]_i_1 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .I5(reg_state_eios_det119_out),
        .O(\FSM_sequential_reg_state_eios_det[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF0010)) 
    \FSM_sequential_reg_state_eios_det[1]_i_1 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I3(\FSM_sequential_reg_state_eios_det[1]_i_2_n_0 ),
        .I4(reg_state_eios_det119_out),
        .I5(\FSM_sequential_reg_state_eios_det[1]_i_4_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[1]_i_2 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \FSM_sequential_reg_state_eios_det[1]_i_3 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det[1]_i_5_n_0 ),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I4(\FSM_sequential_reg_state_eios_det[2]_i_5_n_0 ),
        .O(reg_state_eios_det119_out));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_4 
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_5 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h03B00000)) 
    \FSM_sequential_reg_state_eios_det[2]_i_1 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \FSM_sequential_reg_state_eios_det[2]_i_2 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I3(\FSM_sequential_reg_state_eios_det[2]_i_4_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \FSM_sequential_reg_state_eios_det[2]_i_3 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .I5(\FSM_sequential_reg_state_eios_det[2]_i_5_n_0 ),
        .O(p_15_in));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_4 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_5 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .I3(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_5_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[0]_i_1_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .S(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[1]_i_1_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .R(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[2]_i_1_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rx_phy_status_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_wire_filter),
        .Q(gt_rx_phy_status_q),
        .R(Q));
  LUT4 #(
    .INIT(16'hFF7F)) 
    \gt_rx_status_q[2]_i_2 
       (.I0(\pl_ltssm_state_q_reg[5] [4]),
        .I1(\pl_ltssm_state_q_reg[5] [1]),
        .I2(\pl_ltssm_state_q_reg[5] [2]),
        .I3(\pl_ltssm_state_q_reg[5] [3]),
        .O(\gt_rx_status_q_reg[2]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\pl_ltssm_state_q_reg[5]_0 [0]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\pl_ltssm_state_q_reg[5]_0 [1]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\pl_ltssm_state_q_reg[5]_0 [2]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[0]),
        .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[1]),
        .Q(p_0_in),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[0]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[10] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[10]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[11] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[11]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[12] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[12]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[13] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[13]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[14] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[14]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[15] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[15]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[1]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[2]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[3]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[4]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[5]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[6]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[7]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[8] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[8]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[9] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[9]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxelecidle_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXELECIDLE),
        .Q(gt_rxelecidle_q),
        .R(Q));
  LUT6 #(
    .INIT(64'hA2000000AA00AA00)) 
    gt_rxvalid_q_i_1
       (.I0(gt_rxvalid_q_i_2_n_0),
        .I1(\FSM_sequential_reg_state_eios_det[2]_i_2_n_0 ),
        .I2(gt_rxvalid_q_i_3_n_0),
        .I3(gt_rxvalid_q_reg_0),
        .I4(gt_rxvalid_q_i_5_n_0),
        .I5(p_15_in),
        .O(gt_rxvalid_q));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    gt_rxvalid_q_i_2
       (.I0(\gt_rx_status_q_reg[2]_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I4(\pl_ltssm_state_q_reg[5] [0]),
        .I5(\pl_ltssm_state_q_reg[5] [5]),
        .O(gt_rxvalid_q_i_2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    gt_rxvalid_q_i_3
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(gt_rxvalid_q_i_3_n_0));
  LUT3 #(
    .INIT(8'hEB)) 
    gt_rxvalid_q_i_5
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .O(gt_rxvalid_q_i_5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxvalid_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rxvalid_q),
        .Q(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .R(Q));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1 
       (.I0(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(D[0]));
  LUT3 #(
    .INIT(8'h08)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1 
       (.I0(p_0_in),
        .I1(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I2(symbol_after_eios),
        .O(D[1]));
  LUT5 #(
    .INIT(32'h00800000)) 
    reg_symbol_after_eios_i_1
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(reg_symbol_after_eios));
  FDRE #(
    .INIT(1'b0)) 
    reg_symbol_after_eios_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(reg_symbol_after_eios),
        .Q(symbol_after_eios),
        .R(Q));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_rx_valid_filter_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_22
   (\pipe_stages_1.pipe_rx_valid_q_reg ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg ,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    Q,
    CLK_PCLK,
    gt_rx_phy_status_wire_filter,
    PIPE_RXELECIDLE,
    gt_rxvalid_q_reg_0,
    \pl_ltssm_state_q_reg[4] ,
    \pl_ltssm_state_q_reg[5] ,
    PIPE_RXDATA,
    PIPE_RXDATAK,
    D);
  output \pipe_stages_1.pipe_rx_valid_q_reg ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  input Q;
  input CLK_PCLK;
  input [0:0]gt_rx_phy_status_wire_filter;
  input [0:0]PIPE_RXELECIDLE;
  input gt_rxvalid_q_reg_0;
  input \pl_ltssm_state_q_reg[4] ;
  input [1:0]\pl_ltssm_state_q_reg[5] ;
  input [15:0]PIPE_RXDATA;
  input [1:0]PIPE_RXDATAK;
  input [2:0]D;

  wire CLK_PCLK;
  wire [2:0]D;
  wire \FSM_sequential_reg_state_eios_det[0]_i_1__0_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_1__0_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_2__0_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_4__0_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_5__0_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_1__0_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_4__0_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_5__0_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[2] ;
  wire [15:0]PIPE_RXDATA;
  wire [1:0]PIPE_RXDATAK;
  wire [0:0]PIPE_RXELECIDLE;
  wire Q;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire \gt_rxcharisk_q_reg_n_0_[0] ;
  wire gt_rxvalid_q;
  wire gt_rxvalid_q_i_2__0_n_0;
  wire gt_rxvalid_q_i_3__0_n_0;
  wire gt_rxvalid_q_i_5__0_n_0;
  wire gt_rxvalid_q_reg_0;
  wire p_0_in;
  wire p_15_in;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire \pipe_stages_1.pipe_rx_valid_q_reg ;
  wire \pl_ltssm_state_q_reg[4] ;
  wire [1:0]\pl_ltssm_state_q_reg[5] ;
  wire reg_state_eios_det119_out;
  wire reg_symbol_after_eios;
  wire symbol_after_eios;

  LUT6 #(
    .INIT(64'hFF73FFF3FF7FFFFF)) 
    \FSM_sequential_reg_state_eios_det[0]_i_1__0 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .I5(reg_state_eios_det119_out),
        .O(\FSM_sequential_reg_state_eios_det[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF0010)) 
    \FSM_sequential_reg_state_eios_det[1]_i_1__0 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I3(\FSM_sequential_reg_state_eios_det[1]_i_2__0_n_0 ),
        .I4(reg_state_eios_det119_out),
        .I5(\FSM_sequential_reg_state_eios_det[1]_i_4__0_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[1]_i_2__0 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \FSM_sequential_reg_state_eios_det[1]_i_3__0 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det[1]_i_5__0_n_0 ),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I4(\FSM_sequential_reg_state_eios_det[2]_i_5__0_n_0 ),
        .O(reg_state_eios_det119_out));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_4__0 
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_4__0_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_5__0 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_5__0_n_0 ));
  LUT5 #(
    .INIT(32'h03B00000)) 
    \FSM_sequential_reg_state_eios_det[2]_i_1__0 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \FSM_sequential_reg_state_eios_det[2]_i_2__0 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I3(\FSM_sequential_reg_state_eios_det[2]_i_4__0_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \FSM_sequential_reg_state_eios_det[2]_i_3__0 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .I5(\FSM_sequential_reg_state_eios_det[2]_i_5__0_n_0 ),
        .O(p_15_in));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_4__0 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_4__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_5__0 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .I3(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_5__0_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[0]_i_1__0_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .S(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[1]_i_1__0_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .R(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[2]_i_1__0_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rx_phy_status_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_wire_filter),
        .Q(\pipe_stages_1.pipe_rx_phy_status_q_reg ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[0]),
        .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[1]),
        .Q(p_0_in),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[0]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[10] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[10]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[11] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[11]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[12] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[12]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[13] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[13]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[14] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[14]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[15] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[15]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[1]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[2]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[3]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[4]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[5]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[6]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[7]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[8] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[8]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[9] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[9]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxelecidle_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXELECIDLE),
        .Q(\pipe_stages_1.pipe_rx_elec_idle_q_reg ),
        .R(Q));
  LUT6 #(
    .INIT(64'hA2000000AA00AA00)) 
    gt_rxvalid_q_i_1__0
       (.I0(gt_rxvalid_q_i_2__0_n_0),
        .I1(\FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0 ),
        .I2(gt_rxvalid_q_i_3__0_n_0),
        .I3(gt_rxvalid_q_reg_0),
        .I4(gt_rxvalid_q_i_5__0_n_0),
        .I5(p_15_in),
        .O(gt_rxvalid_q));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    gt_rxvalid_q_i_2__0
       (.I0(\pl_ltssm_state_q_reg[4] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I4(\pl_ltssm_state_q_reg[5] [0]),
        .I5(\pl_ltssm_state_q_reg[5] [1]),
        .O(gt_rxvalid_q_i_2__0_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    gt_rxvalid_q_i_3__0
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(gt_rxvalid_q_i_3__0_n_0));
  LUT3 #(
    .INIT(8'hEB)) 
    gt_rxvalid_q_i_5__0
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .O(gt_rxvalid_q_i_5__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxvalid_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rxvalid_q),
        .Q(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .R(Q));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__0 
       (.I0(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [0]));
  LUT3 #(
    .INIT(8'h08)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__0 
       (.I0(p_0_in),
        .I1(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I2(symbol_after_eios),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [1]));
  LUT5 #(
    .INIT(32'h00800000)) 
    reg_symbol_after_eios_i_1__0
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__0_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(reg_symbol_after_eios));
  FDRE #(
    .INIT(1'b0)) 
    reg_symbol_after_eios_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(reg_symbol_after_eios),
        .Q(symbol_after_eios),
        .R(Q));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_rx_valid_filter_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_23
   (\pipe_stages_1.pipe_rx_valid_q_reg ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg ,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    Q,
    CLK_PCLK,
    gt_rx_phy_status_wire_filter,
    PIPE_RXELECIDLE,
    gt_rxvalid_q_reg_0,
    \pl_ltssm_state_q_reg[4] ,
    \pl_ltssm_state_q_reg[5] ,
    PIPE_RXDATA,
    PIPE_RXDATAK,
    D);
  output \pipe_stages_1.pipe_rx_valid_q_reg ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  input Q;
  input CLK_PCLK;
  input [0:0]gt_rx_phy_status_wire_filter;
  input [0:0]PIPE_RXELECIDLE;
  input gt_rxvalid_q_reg_0;
  input \pl_ltssm_state_q_reg[4] ;
  input [1:0]\pl_ltssm_state_q_reg[5] ;
  input [15:0]PIPE_RXDATA;
  input [1:0]PIPE_RXDATAK;
  input [2:0]D;

  wire CLK_PCLK;
  wire [2:0]D;
  wire \FSM_sequential_reg_state_eios_det[0]_i_1__1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_1__1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_2__1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_4__1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_5__1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_1__1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_4__1_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_5__1_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[2] ;
  wire [15:0]PIPE_RXDATA;
  wire [1:0]PIPE_RXDATAK;
  wire [0:0]PIPE_RXELECIDLE;
  wire Q;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire \gt_rxcharisk_q_reg_n_0_[0] ;
  wire gt_rxvalid_q;
  wire gt_rxvalid_q_i_2__1_n_0;
  wire gt_rxvalid_q_i_3__1_n_0;
  wire gt_rxvalid_q_i_5__1_n_0;
  wire gt_rxvalid_q_reg_0;
  wire p_0_in;
  wire p_15_in;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire \pipe_stages_1.pipe_rx_valid_q_reg ;
  wire \pl_ltssm_state_q_reg[4] ;
  wire [1:0]\pl_ltssm_state_q_reg[5] ;
  wire reg_state_eios_det119_out;
  wire reg_symbol_after_eios;
  wire symbol_after_eios;

  LUT6 #(
    .INIT(64'hFF73FFF3FF7FFFFF)) 
    \FSM_sequential_reg_state_eios_det[0]_i_1__1 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .I5(reg_state_eios_det119_out),
        .O(\FSM_sequential_reg_state_eios_det[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF0010)) 
    \FSM_sequential_reg_state_eios_det[1]_i_1__1 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I3(\FSM_sequential_reg_state_eios_det[1]_i_2__1_n_0 ),
        .I4(reg_state_eios_det119_out),
        .I5(\FSM_sequential_reg_state_eios_det[1]_i_4__1_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[1]_i_2__1 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \FSM_sequential_reg_state_eios_det[1]_i_3__1 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det[1]_i_5__1_n_0 ),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I4(\FSM_sequential_reg_state_eios_det[2]_i_5__1_n_0 ),
        .O(reg_state_eios_det119_out));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_4__1 
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_4__1_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_5__1 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_5__1_n_0 ));
  LUT5 #(
    .INIT(32'h03B00000)) 
    \FSM_sequential_reg_state_eios_det[2]_i_1__1 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \FSM_sequential_reg_state_eios_det[2]_i_2__1 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I3(\FSM_sequential_reg_state_eios_det[2]_i_4__1_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \FSM_sequential_reg_state_eios_det[2]_i_3__1 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .I5(\FSM_sequential_reg_state_eios_det[2]_i_5__1_n_0 ),
        .O(p_15_in));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_4__1 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_4__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_5__1 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .I3(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_5__1_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[0]_i_1__1_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .S(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[1]_i_1__1_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .R(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[2]_i_1__1_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rx_phy_status_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_wire_filter),
        .Q(\pipe_stages_1.pipe_rx_phy_status_q_reg ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[0]),
        .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[1]),
        .Q(p_0_in),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[0]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[10] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[10]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[11] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[11]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[12] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[12]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[13] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[13]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[14] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[14]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[15] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[15]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[1]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[2]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[3]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[4]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[5]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[6]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[7]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[8] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[8]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[9] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[9]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxelecidle_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXELECIDLE),
        .Q(\pipe_stages_1.pipe_rx_elec_idle_q_reg ),
        .R(Q));
  LUT6 #(
    .INIT(64'hA2000000AA00AA00)) 
    gt_rxvalid_q_i_1__1
       (.I0(gt_rxvalid_q_i_2__1_n_0),
        .I1(\FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0 ),
        .I2(gt_rxvalid_q_i_3__1_n_0),
        .I3(gt_rxvalid_q_reg_0),
        .I4(gt_rxvalid_q_i_5__1_n_0),
        .I5(p_15_in),
        .O(gt_rxvalid_q));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    gt_rxvalid_q_i_2__1
       (.I0(\pl_ltssm_state_q_reg[4] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I4(\pl_ltssm_state_q_reg[5] [0]),
        .I5(\pl_ltssm_state_q_reg[5] [1]),
        .O(gt_rxvalid_q_i_2__1_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    gt_rxvalid_q_i_3__1
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(gt_rxvalid_q_i_3__1_n_0));
  LUT3 #(
    .INIT(8'hEB)) 
    gt_rxvalid_q_i_5__1
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .O(gt_rxvalid_q_i_5__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxvalid_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rxvalid_q),
        .Q(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .R(Q));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__1 
       (.I0(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [0]));
  LUT3 #(
    .INIT(8'h08)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__1 
       (.I0(p_0_in),
        .I1(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I2(symbol_after_eios),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [1]));
  LUT5 #(
    .INIT(32'h00800000)) 
    reg_symbol_after_eios_i_1__1
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__1_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(reg_symbol_after_eios));
  FDRE #(
    .INIT(1'b0)) 
    reg_symbol_after_eios_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(reg_symbol_after_eios),
        .Q(symbol_after_eios),
        .R(Q));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_rx_valid_filter_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_24
   (\pipe_stages_1.pipe_rx_valid_q_reg ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg ,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    Q,
    CLK_PCLK,
    gt_rx_phy_status_wire_filter,
    PIPE_RXELECIDLE,
    gt_rxvalid_q_reg_0,
    \pl_ltssm_state_q_reg[4] ,
    \pl_ltssm_state_q_reg[5] ,
    PIPE_RXDATA,
    PIPE_RXDATAK,
    D);
  output \pipe_stages_1.pipe_rx_valid_q_reg ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  input Q;
  input CLK_PCLK;
  input [0:0]gt_rx_phy_status_wire_filter;
  input [0:0]PIPE_RXELECIDLE;
  input gt_rxvalid_q_reg_0;
  input \pl_ltssm_state_q_reg[4] ;
  input [1:0]\pl_ltssm_state_q_reg[5] ;
  input [15:0]PIPE_RXDATA;
  input [1:0]PIPE_RXDATAK;
  input [2:0]D;

  wire CLK_PCLK;
  wire [2:0]D;
  wire \FSM_sequential_reg_state_eios_det[0]_i_1__2_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_1__2_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_2__2_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_4__2_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_5__2_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_1__2_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_4__2_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_5__2_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[2] ;
  wire [15:0]PIPE_RXDATA;
  wire [1:0]PIPE_RXDATAK;
  wire [0:0]PIPE_RXELECIDLE;
  wire Q;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire \gt_rxcharisk_q_reg_n_0_[0] ;
  wire gt_rxvalid_q;
  wire gt_rxvalid_q_i_2__2_n_0;
  wire gt_rxvalid_q_i_3__2_n_0;
  wire gt_rxvalid_q_i_5__2_n_0;
  wire gt_rxvalid_q_reg_0;
  wire p_0_in;
  wire p_15_in;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire \pipe_stages_1.pipe_rx_valid_q_reg ;
  wire \pl_ltssm_state_q_reg[4] ;
  wire [1:0]\pl_ltssm_state_q_reg[5] ;
  wire reg_state_eios_det119_out;
  wire reg_symbol_after_eios;
  wire symbol_after_eios;

  LUT6 #(
    .INIT(64'hFF73FFF3FF7FFFFF)) 
    \FSM_sequential_reg_state_eios_det[0]_i_1__2 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .I5(reg_state_eios_det119_out),
        .O(\FSM_sequential_reg_state_eios_det[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF0010)) 
    \FSM_sequential_reg_state_eios_det[1]_i_1__2 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I3(\FSM_sequential_reg_state_eios_det[1]_i_2__2_n_0 ),
        .I4(reg_state_eios_det119_out),
        .I5(\FSM_sequential_reg_state_eios_det[1]_i_4__2_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[1]_i_2__2 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \FSM_sequential_reg_state_eios_det[1]_i_3__2 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det[1]_i_5__2_n_0 ),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I4(\FSM_sequential_reg_state_eios_det[2]_i_5__2_n_0 ),
        .O(reg_state_eios_det119_out));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_4__2 
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_4__2_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_5__2 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_5__2_n_0 ));
  LUT5 #(
    .INIT(32'h03B00000)) 
    \FSM_sequential_reg_state_eios_det[2]_i_1__2 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \FSM_sequential_reg_state_eios_det[2]_i_2__2 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I3(\FSM_sequential_reg_state_eios_det[2]_i_4__2_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \FSM_sequential_reg_state_eios_det[2]_i_3__2 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .I5(\FSM_sequential_reg_state_eios_det[2]_i_5__2_n_0 ),
        .O(p_15_in));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_4__2 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_4__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_5__2 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .I3(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_5__2_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[0]_i_1__2_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .S(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[1]_i_1__2_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .R(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[2]_i_1__2_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rx_phy_status_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_wire_filter),
        .Q(\pipe_stages_1.pipe_rx_phy_status_q_reg ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[0]),
        .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[1]),
        .Q(p_0_in),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[0]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[10] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[10]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[11] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[11]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[12] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[12]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[13] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[13]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[14] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[14]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[15] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[15]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[1]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[2]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[3]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[4]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[5]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[6]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[7]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[8] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[8]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[9] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[9]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxelecidle_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXELECIDLE),
        .Q(\pipe_stages_1.pipe_rx_elec_idle_q_reg ),
        .R(Q));
  LUT6 #(
    .INIT(64'hA2000000AA00AA00)) 
    gt_rxvalid_q_i_1__2
       (.I0(gt_rxvalid_q_i_2__2_n_0),
        .I1(\FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0 ),
        .I2(gt_rxvalid_q_i_3__2_n_0),
        .I3(gt_rxvalid_q_reg_0),
        .I4(gt_rxvalid_q_i_5__2_n_0),
        .I5(p_15_in),
        .O(gt_rxvalid_q));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    gt_rxvalid_q_i_2__2
       (.I0(\pl_ltssm_state_q_reg[4] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I4(\pl_ltssm_state_q_reg[5] [0]),
        .I5(\pl_ltssm_state_q_reg[5] [1]),
        .O(gt_rxvalid_q_i_2__2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    gt_rxvalid_q_i_3__2
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(gt_rxvalid_q_i_3__2_n_0));
  LUT3 #(
    .INIT(8'hEB)) 
    gt_rxvalid_q_i_5__2
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .O(gt_rxvalid_q_i_5__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxvalid_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rxvalid_q),
        .Q(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .R(Q));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__2 
       (.I0(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [0]));
  LUT3 #(
    .INIT(8'h08)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__2 
       (.I0(p_0_in),
        .I1(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I2(symbol_after_eios),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [1]));
  LUT5 #(
    .INIT(32'h00800000)) 
    reg_symbol_after_eios_i_1__2
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__2_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(reg_symbol_after_eios));
  FDRE #(
    .INIT(1'b0)) 
    reg_symbol_after_eios_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(reg_symbol_after_eios),
        .Q(symbol_after_eios),
        .R(Q));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_rx_valid_filter_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_25
   (\pipe_stages_1.pipe_rx_valid_q_reg ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg ,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    Q,
    CLK_PCLK,
    gt_rx_phy_status_wire_filter,
    PIPE_RXELECIDLE,
    gt_rxvalid_q_reg_0,
    \pl_ltssm_state_q_reg[4] ,
    \pl_ltssm_state_q_reg[5] ,
    PIPE_RXDATA,
    PIPE_RXDATAK,
    D);
  output \pipe_stages_1.pipe_rx_valid_q_reg ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  input Q;
  input CLK_PCLK;
  input [0:0]gt_rx_phy_status_wire_filter;
  input [0:0]PIPE_RXELECIDLE;
  input gt_rxvalid_q_reg_0;
  input \pl_ltssm_state_q_reg[4] ;
  input [1:0]\pl_ltssm_state_q_reg[5] ;
  input [15:0]PIPE_RXDATA;
  input [1:0]PIPE_RXDATAK;
  input [2:0]D;

  wire CLK_PCLK;
  wire [2:0]D;
  wire \FSM_sequential_reg_state_eios_det[0]_i_1__3_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_1__3_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_2__3_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_4__3_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_5__3_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_1__3_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_4__3_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_5__3_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[2] ;
  wire [15:0]PIPE_RXDATA;
  wire [1:0]PIPE_RXDATAK;
  wire [0:0]PIPE_RXELECIDLE;
  wire Q;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire \gt_rxcharisk_q_reg_n_0_[0] ;
  wire gt_rxvalid_q;
  wire gt_rxvalid_q_i_2__3_n_0;
  wire gt_rxvalid_q_i_3__3_n_0;
  wire gt_rxvalid_q_i_5__3_n_0;
  wire gt_rxvalid_q_reg_0;
  wire p_0_in;
  wire p_15_in;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire \pipe_stages_1.pipe_rx_valid_q_reg ;
  wire \pl_ltssm_state_q_reg[4] ;
  wire [1:0]\pl_ltssm_state_q_reg[5] ;
  wire reg_state_eios_det119_out;
  wire reg_symbol_after_eios;
  wire symbol_after_eios;

  LUT6 #(
    .INIT(64'hFF73FFF3FF7FFFFF)) 
    \FSM_sequential_reg_state_eios_det[0]_i_1__3 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .I5(reg_state_eios_det119_out),
        .O(\FSM_sequential_reg_state_eios_det[0]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF0004)) 
    \FSM_sequential_reg_state_eios_det[1]_i_1__3 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I3(\FSM_sequential_reg_state_eios_det[1]_i_2__3_n_0 ),
        .I4(reg_state_eios_det119_out),
        .I5(\FSM_sequential_reg_state_eios_det[1]_i_4__3_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[1]_i_2__3 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \FSM_sequential_reg_state_eios_det[1]_i_3__3 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det[1]_i_5__3_n_0 ),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I4(\FSM_sequential_reg_state_eios_det[2]_i_5__3_n_0 ),
        .O(reg_state_eios_det119_out));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_4__3 
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_4__3_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_5__3 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_5__3_n_0 ));
  LUT5 #(
    .INIT(32'h03B00000)) 
    \FSM_sequential_reg_state_eios_det[2]_i_1__3 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \FSM_sequential_reg_state_eios_det[2]_i_2__3 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I3(\FSM_sequential_reg_state_eios_det[2]_i_4__3_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \FSM_sequential_reg_state_eios_det[2]_i_3__3 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .I5(\FSM_sequential_reg_state_eios_det[2]_i_5__3_n_0 ),
        .O(p_15_in));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_4__3 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_4__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_5__3 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .I3(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_5__3_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[0]_i_1__3_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .S(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[1]_i_1__3_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .R(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[2]_i_1__3_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rx_phy_status_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_wire_filter),
        .Q(\pipe_stages_1.pipe_rx_phy_status_q_reg ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[0]),
        .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[1]),
        .Q(p_0_in),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[0]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[10] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[10]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[11] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[11]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[12] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[12]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[13] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[13]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[14] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[14]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[15] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[15]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[1]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[2]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[3]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[4]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[5]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[6]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[7]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[8] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[8]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[9] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[9]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxelecidle_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXELECIDLE),
        .Q(\pipe_stages_1.pipe_rx_elec_idle_q_reg ),
        .R(Q));
  LUT6 #(
    .INIT(64'hA2000000AA00AA00)) 
    gt_rxvalid_q_i_1__3
       (.I0(gt_rxvalid_q_i_2__3_n_0),
        .I1(\FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0 ),
        .I2(gt_rxvalid_q_i_3__3_n_0),
        .I3(gt_rxvalid_q_reg_0),
        .I4(gt_rxvalid_q_i_5__3_n_0),
        .I5(p_15_in),
        .O(gt_rxvalid_q));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    gt_rxvalid_q_i_2__3
       (.I0(\pl_ltssm_state_q_reg[4] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I4(\pl_ltssm_state_q_reg[5] [0]),
        .I5(\pl_ltssm_state_q_reg[5] [1]),
        .O(gt_rxvalid_q_i_2__3_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    gt_rxvalid_q_i_3__3
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(gt_rxvalid_q_i_3__3_n_0));
  LUT3 #(
    .INIT(8'hEB)) 
    gt_rxvalid_q_i_5__3
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .O(gt_rxvalid_q_i_5__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxvalid_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rxvalid_q),
        .Q(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .R(Q));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__3 
       (.I0(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [0]));
  LUT3 #(
    .INIT(8'h08)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__3 
       (.I0(p_0_in),
        .I1(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I2(symbol_after_eios),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [1]));
  LUT5 #(
    .INIT(32'h00800000)) 
    reg_symbol_after_eios_i_1__3
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__3_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(reg_symbol_after_eios));
  FDRE #(
    .INIT(1'b0)) 
    reg_symbol_after_eios_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(reg_symbol_after_eios),
        .Q(symbol_after_eios),
        .R(Q));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_rx_valid_filter_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_26
   (\pipe_stages_1.pipe_rx_valid_q_reg ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg ,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    Q,
    CLK_PCLK,
    gt_rx_phy_status_wire_filter,
    PIPE_RXELECIDLE,
    gt_rxvalid_q_reg_0,
    \pl_ltssm_state_q_reg[4] ,
    \pl_ltssm_state_q_reg[5] ,
    PIPE_RXDATA,
    PIPE_RXDATAK,
    D);
  output \pipe_stages_1.pipe_rx_valid_q_reg ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  input Q;
  input CLK_PCLK;
  input [0:0]gt_rx_phy_status_wire_filter;
  input [0:0]PIPE_RXELECIDLE;
  input gt_rxvalid_q_reg_0;
  input \pl_ltssm_state_q_reg[4] ;
  input [1:0]\pl_ltssm_state_q_reg[5] ;
  input [15:0]PIPE_RXDATA;
  input [1:0]PIPE_RXDATAK;
  input [2:0]D;

  wire CLK_PCLK;
  wire [2:0]D;
  wire \FSM_sequential_reg_state_eios_det[0]_i_1__4_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_1__4_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_2__4_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_4__4_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_5__4_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_1__4_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_4__4_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_5__4_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[2] ;
  wire [15:0]PIPE_RXDATA;
  wire [1:0]PIPE_RXDATAK;
  wire [0:0]PIPE_RXELECIDLE;
  wire Q;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire \gt_rxcharisk_q_reg_n_0_[0] ;
  wire gt_rxvalid_q;
  wire gt_rxvalid_q_i_2__4_n_0;
  wire gt_rxvalid_q_i_3__4_n_0;
  wire gt_rxvalid_q_i_5__4_n_0;
  wire gt_rxvalid_q_reg_0;
  wire p_0_in;
  wire p_15_in;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire \pipe_stages_1.pipe_rx_valid_q_reg ;
  wire \pl_ltssm_state_q_reg[4] ;
  wire [1:0]\pl_ltssm_state_q_reg[5] ;
  wire reg_state_eios_det119_out;
  wire reg_symbol_after_eios;
  wire symbol_after_eios;

  LUT6 #(
    .INIT(64'hFF73FFF3FF7FFFFF)) 
    \FSM_sequential_reg_state_eios_det[0]_i_1__4 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .I5(reg_state_eios_det119_out),
        .O(\FSM_sequential_reg_state_eios_det[0]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF0004)) 
    \FSM_sequential_reg_state_eios_det[1]_i_1__4 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I3(\FSM_sequential_reg_state_eios_det[1]_i_2__4_n_0 ),
        .I4(reg_state_eios_det119_out),
        .I5(\FSM_sequential_reg_state_eios_det[1]_i_4__4_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[1]_i_2__4 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \FSM_sequential_reg_state_eios_det[1]_i_3__4 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det[1]_i_5__4_n_0 ),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I4(\FSM_sequential_reg_state_eios_det[2]_i_5__4_n_0 ),
        .O(reg_state_eios_det119_out));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_4__4 
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_4__4_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_5__4 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_5__4_n_0 ));
  LUT5 #(
    .INIT(32'h03B00000)) 
    \FSM_sequential_reg_state_eios_det[2]_i_1__4 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_1__4_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \FSM_sequential_reg_state_eios_det[2]_i_2__4 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I3(\FSM_sequential_reg_state_eios_det[2]_i_4__4_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \FSM_sequential_reg_state_eios_det[2]_i_3__4 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .I5(\FSM_sequential_reg_state_eios_det[2]_i_5__4_n_0 ),
        .O(p_15_in));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_4__4 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_4__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_5__4 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .I3(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_5__4_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[0]_i_1__4_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .S(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[1]_i_1__4_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .R(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[2]_i_1__4_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rx_phy_status_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_wire_filter),
        .Q(\pipe_stages_1.pipe_rx_phy_status_q_reg ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[0]),
        .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[1]),
        .Q(p_0_in),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[0]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[10] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[10]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[11] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[11]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[12] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[12]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[13] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[13]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[14] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[14]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[15] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[15]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[1]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[2]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[3]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[4]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[5]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[6]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[7]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[8] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[8]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[9] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[9]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxelecidle_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXELECIDLE),
        .Q(\pipe_stages_1.pipe_rx_elec_idle_q_reg ),
        .R(Q));
  LUT6 #(
    .INIT(64'hA2000000AA00AA00)) 
    gt_rxvalid_q_i_1__4
       (.I0(gt_rxvalid_q_i_2__4_n_0),
        .I1(\FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0 ),
        .I2(gt_rxvalid_q_i_3__4_n_0),
        .I3(gt_rxvalid_q_reg_0),
        .I4(gt_rxvalid_q_i_5__4_n_0),
        .I5(p_15_in),
        .O(gt_rxvalid_q));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    gt_rxvalid_q_i_2__4
       (.I0(\pl_ltssm_state_q_reg[4] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I4(\pl_ltssm_state_q_reg[5] [0]),
        .I5(\pl_ltssm_state_q_reg[5] [1]),
        .O(gt_rxvalid_q_i_2__4_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    gt_rxvalid_q_i_3__4
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(gt_rxvalid_q_i_3__4_n_0));
  LUT3 #(
    .INIT(8'hEB)) 
    gt_rxvalid_q_i_5__4
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .O(gt_rxvalid_q_i_5__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxvalid_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rxvalid_q),
        .Q(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .R(Q));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__4 
       (.I0(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [0]));
  LUT3 #(
    .INIT(8'h08)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__4 
       (.I0(p_0_in),
        .I1(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I2(symbol_after_eios),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [1]));
  LUT5 #(
    .INIT(32'h00800000)) 
    reg_symbol_after_eios_i_1__4
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__4_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(reg_symbol_after_eios));
  FDRE #(
    .INIT(1'b0)) 
    reg_symbol_after_eios_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(reg_symbol_after_eios),
        .Q(symbol_after_eios),
        .R(Q));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_rx_valid_filter_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_27
   (\pipe_stages_1.pipe_rx_valid_q_reg ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg ,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    Q,
    CLK_PCLK,
    gt_rx_phy_status_wire_filter,
    PIPE_RXELECIDLE,
    gt_rxvalid_q_reg_0,
    \pl_ltssm_state_q_reg[4] ,
    \pl_ltssm_state_q_reg[5] ,
    PIPE_RXDATA,
    PIPE_RXDATAK,
    D);
  output \pipe_stages_1.pipe_rx_valid_q_reg ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  input Q;
  input CLK_PCLK;
  input [0:0]gt_rx_phy_status_wire_filter;
  input [0:0]PIPE_RXELECIDLE;
  input gt_rxvalid_q_reg_0;
  input \pl_ltssm_state_q_reg[4] ;
  input [1:0]\pl_ltssm_state_q_reg[5] ;
  input [15:0]PIPE_RXDATA;
  input [1:0]PIPE_RXDATAK;
  input [2:0]D;

  wire CLK_PCLK;
  wire [2:0]D;
  wire \FSM_sequential_reg_state_eios_det[0]_i_1__5_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_1__5_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_2__5_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_4__5_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_5__5_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_1__5_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_4__5_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_5__5_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[2] ;
  wire [15:0]PIPE_RXDATA;
  wire [1:0]PIPE_RXDATAK;
  wire [0:0]PIPE_RXELECIDLE;
  wire Q;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire \gt_rxcharisk_q_reg_n_0_[0] ;
  wire gt_rxvalid_q;
  wire gt_rxvalid_q_i_2__5_n_0;
  wire gt_rxvalid_q_i_3__5_n_0;
  wire gt_rxvalid_q_i_5__5_n_0;
  wire gt_rxvalid_q_reg_0;
  wire p_0_in;
  wire p_15_in;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire \pipe_stages_1.pipe_rx_valid_q_reg ;
  wire \pl_ltssm_state_q_reg[4] ;
  wire [1:0]\pl_ltssm_state_q_reg[5] ;
  wire reg_state_eios_det119_out;
  wire reg_symbol_after_eios;
  wire symbol_after_eios;

  LUT6 #(
    .INIT(64'hFF73FFF3FF7FFFFF)) 
    \FSM_sequential_reg_state_eios_det[0]_i_1__5 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .I5(reg_state_eios_det119_out),
        .O(\FSM_sequential_reg_state_eios_det[0]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF0010)) 
    \FSM_sequential_reg_state_eios_det[1]_i_1__5 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I3(\FSM_sequential_reg_state_eios_det[1]_i_2__5_n_0 ),
        .I4(reg_state_eios_det119_out),
        .I5(\FSM_sequential_reg_state_eios_det[1]_i_4__5_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[1]_i_2__5 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \FSM_sequential_reg_state_eios_det[1]_i_3__5 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det[1]_i_5__5_n_0 ),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I4(\FSM_sequential_reg_state_eios_det[2]_i_5__5_n_0 ),
        .O(reg_state_eios_det119_out));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_4__5 
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_4__5_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_5__5 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_5__5_n_0 ));
  LUT5 #(
    .INIT(32'h03B00000)) 
    \FSM_sequential_reg_state_eios_det[2]_i_1__5 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_1__5_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \FSM_sequential_reg_state_eios_det[2]_i_2__5 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I3(\FSM_sequential_reg_state_eios_det[2]_i_4__5_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \FSM_sequential_reg_state_eios_det[2]_i_3__5 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .I5(\FSM_sequential_reg_state_eios_det[2]_i_5__5_n_0 ),
        .O(p_15_in));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_4__5 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_4__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_5__5 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .I3(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_5__5_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[0]_i_1__5_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .S(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[1]_i_1__5_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .R(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[2]_i_1__5_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rx_phy_status_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_wire_filter),
        .Q(\pipe_stages_1.pipe_rx_phy_status_q_reg ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[0]),
        .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[1]),
        .Q(p_0_in),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[0]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[10] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[10]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[11] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[11]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[12] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[12]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[13] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[13]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[14] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[14]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[15] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[15]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[1]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[2]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[3]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[4]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[5]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[6]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[7]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[8] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[8]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[9] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[9]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxelecidle_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXELECIDLE),
        .Q(\pipe_stages_1.pipe_rx_elec_idle_q_reg ),
        .R(Q));
  LUT6 #(
    .INIT(64'hA2000000AA00AA00)) 
    gt_rxvalid_q_i_1__5
       (.I0(gt_rxvalid_q_i_2__5_n_0),
        .I1(\FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0 ),
        .I2(gt_rxvalid_q_i_3__5_n_0),
        .I3(gt_rxvalid_q_reg_0),
        .I4(gt_rxvalid_q_i_5__5_n_0),
        .I5(p_15_in),
        .O(gt_rxvalid_q));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    gt_rxvalid_q_i_2__5
       (.I0(\pl_ltssm_state_q_reg[4] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I4(\pl_ltssm_state_q_reg[5] [0]),
        .I5(\pl_ltssm_state_q_reg[5] [1]),
        .O(gt_rxvalid_q_i_2__5_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    gt_rxvalid_q_i_3__5
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(gt_rxvalid_q_i_3__5_n_0));
  LUT3 #(
    .INIT(8'hEB)) 
    gt_rxvalid_q_i_5__5
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .O(gt_rxvalid_q_i_5__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxvalid_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rxvalid_q),
        .Q(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .R(Q));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__5 
       (.I0(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [0]));
  LUT3 #(
    .INIT(8'h08)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__5 
       (.I0(p_0_in),
        .I1(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I2(symbol_after_eios),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [1]));
  LUT5 #(
    .INIT(32'h00800000)) 
    reg_symbol_after_eios_i_1__5
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__5_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(reg_symbol_after_eios));
  FDRE #(
    .INIT(1'b0)) 
    reg_symbol_after_eios_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(reg_symbol_after_eios),
        .Q(symbol_after_eios),
        .R(Q));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_rx_valid_filter_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_28
   (\pipe_stages_1.pipe_rx_valid_q_reg ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg ,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    Q,
    CLK_PCLK,
    gt_rx_phy_status_wire_filter,
    PIPE_RXELECIDLE,
    gt_rxvalid_q_reg_0,
    \pl_ltssm_state_q_reg[4] ,
    \pl_ltssm_state_q_reg[5] ,
    PIPE_RXDATA,
    PIPE_RXDATAK,
    D);
  output \pipe_stages_1.pipe_rx_valid_q_reg ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  input Q;
  input CLK_PCLK;
  input [0:0]gt_rx_phy_status_wire_filter;
  input [0:0]PIPE_RXELECIDLE;
  input gt_rxvalid_q_reg_0;
  input \pl_ltssm_state_q_reg[4] ;
  input [1:0]\pl_ltssm_state_q_reg[5] ;
  input [15:0]PIPE_RXDATA;
  input [1:0]PIPE_RXDATAK;
  input [2:0]D;

  wire CLK_PCLK;
  wire [2:0]D;
  wire \FSM_sequential_reg_state_eios_det[0]_i_1__6_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_1__6_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_2__6_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_4__6_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[1]_i_5__6_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_1__6_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_4__6_n_0 ;
  wire \FSM_sequential_reg_state_eios_det[2]_i_5__6_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_reg_state_eios_det_reg_n_0_[2] ;
  wire [15:0]PIPE_RXDATA;
  wire [1:0]PIPE_RXDATAK;
  wire [0:0]PIPE_RXELECIDLE;
  wire Q;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire \gt_rxcharisk_q_reg_n_0_[0] ;
  wire gt_rxvalid_q;
  wire gt_rxvalid_q_i_2__6_n_0;
  wire gt_rxvalid_q_i_3__6_n_0;
  wire gt_rxvalid_q_i_5__6_n_0;
  wire gt_rxvalid_q_reg_0;
  wire p_0_in;
  wire p_15_in;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire \pipe_stages_1.pipe_rx_valid_q_reg ;
  wire \pl_ltssm_state_q_reg[4] ;
  wire [1:0]\pl_ltssm_state_q_reg[5] ;
  wire reg_state_eios_det119_out;
  wire reg_symbol_after_eios;
  wire symbol_after_eios;

  LUT6 #(
    .INIT(64'hFF73FFF3FF7FFFFF)) 
    \FSM_sequential_reg_state_eios_det[0]_i_1__6 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .I5(reg_state_eios_det119_out),
        .O(\FSM_sequential_reg_state_eios_det[0]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF0004)) 
    \FSM_sequential_reg_state_eios_det[1]_i_1__6 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I3(\FSM_sequential_reg_state_eios_det[1]_i_2__6_n_0 ),
        .I4(reg_state_eios_det119_out),
        .I5(\FSM_sequential_reg_state_eios_det[1]_i_4__6_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[1]_i_2__6 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \FSM_sequential_reg_state_eios_det[1]_i_3__6 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det[1]_i_5__6_n_0 ),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I4(\FSM_sequential_reg_state_eios_det[2]_i_5__6_n_0 ),
        .O(reg_state_eios_det119_out));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_4__6 
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_4__6_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_sequential_reg_state_eios_det[1]_i_5__6 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .O(\FSM_sequential_reg_state_eios_det[1]_i_5__6_n_0 ));
  LUT5 #(
    .INIT(32'h03B00000)) 
    \FSM_sequential_reg_state_eios_det[2]_i_1__6 
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_1__6_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \FSM_sequential_reg_state_eios_det[2]_i_2__6 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .I3(\FSM_sequential_reg_state_eios_det[2]_i_4__6_n_0 ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \FSM_sequential_reg_state_eios_det[2]_i_3__6 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .I5(\FSM_sequential_reg_state_eios_det[2]_i_5__6_n_0 ),
        .O(p_15_in));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_4__6 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .I2(p_0_in),
        .I3(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .I4(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .I5(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_4__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \FSM_sequential_reg_state_eios_det[2]_i_5__6 
       (.I0(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .I1(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .I2(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .I3(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\FSM_sequential_reg_state_eios_det[2]_i_5__6_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[0]_i_1__6_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .S(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[1]_i_1__6_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .R(Q));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_reg_state_eios_det_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(\FSM_sequential_reg_state_eios_det[2]_i_1__6_n_0 ),
        .Q(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rx_phy_status_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_wire_filter),
        .Q(\pipe_stages_1.pipe_rx_phy_status_q_reg ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rx_status_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\pipe_stages_1.pipe_rx_status_q_reg[2] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[0]),
        .Q(\gt_rxcharisk_q_reg_n_0_[0] ),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxcharisk_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATAK[1]),
        .Q(p_0_in),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[0]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [0]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[10] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[10]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [10]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[11] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[11]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [11]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[12] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[12]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [12]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[13] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[13]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [13]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[14] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[14]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [14]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[15] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[15]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [15]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[1]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [1]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[2]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [2]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[3]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [3]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[4]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [4]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[5]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [5]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[6]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [6]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[7]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [7]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[8] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[8]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [8]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    \gt_rxdata_q_reg[9] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXDATA[9]),
        .Q(\pipe_stages_1.pipe_rx_data_q_reg[15] [9]),
        .R(Q));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxelecidle_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(PIPE_RXELECIDLE),
        .Q(\pipe_stages_1.pipe_rx_elec_idle_q_reg ),
        .R(Q));
  LUT6 #(
    .INIT(64'hA2000000AA00AA00)) 
    gt_rxvalid_q_i_1__6
       (.I0(gt_rxvalid_q_i_2__6_n_0),
        .I1(\FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0 ),
        .I2(gt_rxvalid_q_i_3__6_n_0),
        .I3(gt_rxvalid_q_reg_0),
        .I4(gt_rxvalid_q_i_5__6_n_0),
        .I5(p_15_in),
        .O(gt_rxvalid_q));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    gt_rxvalid_q_i_2__6
       (.I0(\pl_ltssm_state_q_reg[4] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I4(\pl_ltssm_state_q_reg[5] [0]),
        .I5(\pl_ltssm_state_q_reg[5] [1]),
        .O(gt_rxvalid_q_i_2__6_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    gt_rxvalid_q_i_3__6
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .O(gt_rxvalid_q_i_3__6_n_0));
  LUT3 #(
    .INIT(8'hEB)) 
    gt_rxvalid_q_i_5__6
       (.I0(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .O(gt_rxvalid_q_i_5__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gt_rxvalid_q_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gt_rxvalid_q),
        .Q(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .R(Q));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[0]_i_1__6 
       (.I0(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I1(\gt_rxcharisk_q_reg_n_0_[0] ),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [0]));
  LUT3 #(
    .INIT(8'h08)) 
    \pipe_stages_1.pipe_rx_char_is_k_q[1]_i_1__6 
       (.I0(p_0_in),
        .I1(\pipe_stages_1.pipe_rx_valid_q_reg ),
        .I2(symbol_after_eios),
        .O(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] [1]));
  LUT5 #(
    .INIT(32'h00800000)) 
    reg_symbol_after_eios_i_1__6
       (.I0(\FSM_sequential_reg_state_eios_det[2]_i_2__6_n_0 ),
        .I1(\FSM_sequential_reg_state_eios_det_reg_n_0_[0] ),
        .I2(\FSM_sequential_reg_state_eios_det_reg_n_0_[1] ),
        .I3(\FSM_sequential_reg_state_eios_det_reg_n_0_[2] ),
        .I4(p_15_in),
        .O(reg_symbol_after_eios));
  FDRE #(
    .INIT(1'b0)) 
    reg_symbol_after_eios_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(reg_symbol_after_eios),
        .Q(symbol_after_eios),
        .R(Q));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_top" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_top
   (pipe_rx0_valid,
    Q,
    CLK_PCLK,
    pipe_rx1_valid,
    pipe_rx2_valid,
    pipe_rx3_valid,
    pipe_rx4_valid,
    pipe_rx5_valid,
    pipe_rx6_valid,
    pipe_rx7_valid,
    gt_rx_phy_status_q,
    gt_rxelecidle_q,
    \pipe_stages_1.pipe_rx_phy_status_q_reg ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg_1 ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_1 ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg_2 ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_2 ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg_3 ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_3 ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg_4 ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_4 ,
    \pipe_stages_1.pipe_rx_phy_status_q_reg_5 ,
    \pipe_stages_1.pipe_rx_elec_idle_q_reg_5 ,
    pipe_qrst_fsm,
    pipe_txphinitdone,
    pipe_txphaligndone,
    \txsync_fsm.txsync_done_reg ,
    \sysclksel_reg[1] ,
    \index_reg[1] ,
    \txsync_fsm.txdlyen_reg ,
    \sysclksel_reg[1]_0 ,
    \index_reg[1]_0 ,
    \txsync_fsm.txdlyen_reg_0 ,
    \sysclksel_reg[1]_1 ,
    \index_reg[1]_1 ,
    \txsync_fsm.txdlyen_reg_1 ,
    \sysclksel_reg[1]_2 ,
    \index_reg[1]_2 ,
    \txsync_fsm.txdlyen_reg_2 ,
    \sysclksel_reg[1]_3 ,
    \index_reg[1]_3 ,
    \txsync_fsm.txdlyen_reg_3 ,
    \sysclksel_reg[1]_4 ,
    \index_reg[1]_4 ,
    \txsync_fsm.txdlyen_reg_4 ,
    \sysclksel_reg[1]_5 ,
    \index_reg[1]_5 ,
    \txsync_fsm.txdlyen_reg_5 ,
    \sysclksel_reg[1]_6 ,
    \index_reg[1]_6 ,
    pipe_rxphaligndone,
    sys_rst_n,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_1 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_2 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_3 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_4 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_5 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_6 ,
    CLK_MMCM_LOCK,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_1 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_2 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_3 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_4 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_5 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_6 ,
    pipe_rxstatus,
    D,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5 ,
    pipe_txoutclk_out,
    CLK_DCLK,
    CLK_USERCLK1,
    pclk_sel_reg1_reg,
    rate_gen3,
    out,
    pipe_rst_fsm,
    PIPE_CPLL_LOCK,
    pipe_qrst_idle,
    PIPE_QPLL_LOCK,
    pipe_sync_fsm_rx,
    ext_ch_gt_drprdy,
    ext_ch_gt_drpdo,
    INT_QPLLOUTCLK_OUT,
    INT_QPLLOUTREFCLK_OUT,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    PIPE_RXCHANISALIGNED,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    pipe_rxoutclk_out,
    pipe_rxprbserr,
    pipe_txdlysresetdone,
    pipe_rxbufstatus,
    pipe_dmonitorout,
    pipe_rxdisperr,
    pipe_rxnotintable,
    pipe_rate_idle,
    reset_n_reg2_reg,
    gt_ch_drp_rdy,
    ext_ch_gt_drpaddr,
    pl_ltssm_state,
    int_pclk_sel_slave,
    pipe_mmcm_rst_n,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    sys_clk,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    pci_exp_rxn,
    pci_exp_rxp,
    PIPE_RXPOLARITY,
    PIPE_TXDEEMPH,
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ,
    pipe_txinhibit,
    PIPE_POWERDOWN,
    TXMARGIN,
    PIPE_TXDATA,
    PIPE_TXDATAK,
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ,
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ,
    PIPE_TXDETECTRX,
    PIPE_TXMARGIN,
    pipe_tx_rcvr_det,
    \pipe_stages_1.pipe_tx_margin_q_reg[2] ,
    sys_rst_n_0,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi);
  output pipe_rx0_valid;
  output Q;
  output CLK_PCLK;
  output pipe_rx1_valid;
  output pipe_rx2_valid;
  output pipe_rx3_valid;
  output pipe_rx4_valid;
  output pipe_rx5_valid;
  output pipe_rx6_valid;
  output pipe_rx7_valid;
  output gt_rx_phy_status_q;
  output gt_rxelecidle_q;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg_1 ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg_1 ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg_2 ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg_2 ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg_3 ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg_3 ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg_4 ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg_4 ;
  output \pipe_stages_1.pipe_rx_phy_status_q_reg_5 ;
  output \pipe_stages_1.pipe_rx_elec_idle_q_reg_5 ;
  output [3:0]pipe_qrst_fsm;
  output [7:0]pipe_txphinitdone;
  output [7:0]pipe_txphaligndone;
  output [5:0]\txsync_fsm.txsync_done_reg ;
  output [4:0]\sysclksel_reg[1] ;
  output [2:0]\index_reg[1] ;
  output [5:0]\txsync_fsm.txdlyen_reg ;
  output [4:0]\sysclksel_reg[1]_0 ;
  output [2:0]\index_reg[1]_0 ;
  output [5:0]\txsync_fsm.txdlyen_reg_0 ;
  output [4:0]\sysclksel_reg[1]_1 ;
  output [2:0]\index_reg[1]_1 ;
  output [5:0]\txsync_fsm.txdlyen_reg_1 ;
  output [4:0]\sysclksel_reg[1]_2 ;
  output [2:0]\index_reg[1]_2 ;
  output [5:0]\txsync_fsm.txdlyen_reg_2 ;
  output [4:0]\sysclksel_reg[1]_3 ;
  output [2:0]\index_reg[1]_3 ;
  output [5:0]\txsync_fsm.txdlyen_reg_3 ;
  output [4:0]\sysclksel_reg[1]_4 ;
  output [2:0]\index_reg[1]_4 ;
  output [5:0]\txsync_fsm.txdlyen_reg_4 ;
  output [4:0]\sysclksel_reg[1]_5 ;
  output [2:0]\index_reg[1]_5 ;
  output [5:0]\txsync_fsm.txdlyen_reg_5 ;
  output [4:0]\sysclksel_reg[1]_6 ;
  output [2:0]\index_reg[1]_6 ;
  output [7:0]pipe_rxphaligndone;
  output sys_rst_n;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_3 ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_4 ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_5 ;
  output [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_6 ;
  output CLK_MMCM_LOCK;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_3 ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_4 ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_5 ;
  output [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_6 ;
  output [23:0]pipe_rxstatus;
  output [1:0]D;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ;
  output [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5 ;
  output pipe_txoutclk_out;
  output CLK_DCLK;
  output CLK_USERCLK1;
  output [7:0]pclk_sel_reg1_reg;
  output [0:0]rate_gen3;
  output [1:0]out;
  output [3:0]pipe_rst_fsm;
  output [7:0]PIPE_CPLL_LOCK;
  output pipe_qrst_idle;
  output [1:0]PIPE_QPLL_LOCK;
  output [55:0]pipe_sync_fsm_rx;
  output [7:0]ext_ch_gt_drprdy;
  output [127:0]ext_ch_gt_drpdo;
  output [1:0]INT_QPLLOUTCLK_OUT;
  output [1:0]INT_QPLLOUTREFCLK_OUT;
  output [7:0]pipe_eyescandataerror;
  output [7:0]pci_exp_txn;
  output [7:0]pci_exp_txp;
  output [7:0]PIPE_RXCHANISALIGNED;
  output [7:0]pipe_rxcommadet;
  output [7:0]pipe_rxdlysresetdone;
  output [7:0]pipe_rxoutclk_out;
  output [7:0]pipe_rxprbserr;
  output [7:0]pipe_txdlysresetdone;
  output [23:0]pipe_rxbufstatus;
  output [63:0]pipe_dmonitorout;
  output [63:0]pipe_rxdisperr;
  output [63:0]pipe_rxnotintable;
  output pipe_rate_idle;
  output reset_n_reg2_reg;
  output [7:0]gt_ch_drp_rdy;
  input [71:0]ext_ch_gt_drpaddr;
  input [5:0]pl_ltssm_state;
  input [7:0]int_pclk_sel_slave;
  input pipe_mmcm_rst_n;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input sys_clk;
  input [7:0]PIPE_TXCOMPLIANCE;
  input [7:0]PIPE_TXELECIDLE;
  input [7:0]pci_exp_rxn;
  input [7:0]pci_exp_rxp;
  input [7:0]PIPE_RXPOLARITY;
  input [3:0]PIPE_TXDEEMPH;
  input \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ;
  input [7:0]pipe_txinhibit;
  input [15:0]PIPE_POWERDOWN;
  input [2:0]TXMARGIN;
  input [127:0]PIPE_TXDATA;
  input [15:0]PIPE_TXDATAK;
  input \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ;
  input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ;
  input PIPE_TXDETECTRX;
  input [2:0]PIPE_TXMARGIN;
  input pipe_tx_rcvr_det;
  input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  input sys_rst_n_0;
  input [7:0]ext_ch_gt_drpen;
  input [7:0]ext_ch_gt_drpwe;
  input [127:0]ext_ch_gt_drpdi;

  wire CLK_DCLK;
  wire CLK_MMCM_LOCK;
  wire CLK_PCLK;
  wire CLK_USERCLK1;
  wire [1:0]D;
  wire [1:0]GT_RXCHARISK;
  wire [15:0]GT_RXDATA;
  wire GT_RXPMARESET0;
  wire GT_RXPMARESET0117_out;
  wire GT_RXPMARESET014_out;
  wire GT_RXPMARESET032_out;
  wire GT_RXPMARESET043_out;
  wire GT_RXPMARESET061_out;
  wire GT_RXPMARESET071_out;
  wire GT_RXPMARESET089_out;
  wire GT_TXPMARESET0;
  wire GT_TXPMARESET0120_out;
  wire GT_TXPMARESET017_out;
  wire GT_TXPMARESET035_out;
  wire GT_TXPMARESET046_out;
  wire GT_TXPMARESET064_out;
  wire GT_TXPMARESET074_out;
  wire GT_TXPMARESET092_out;
  wire [1:0]INT_QPLLOUTCLK_OUT;
  wire [1:0]INT_QPLLOUTREFCLK_OUT;
  wire [7:0]PIPE_CPLL_LOCK;
  wire [15:0]PIPE_POWERDOWN;
  wire [1:0]PIPE_QPLL_LOCK;
  wire [7:0]PIPE_RXCHANISALIGNED;
  wire [7:0]PIPE_RXPOLARITY;
  wire [7:0]PIPE_TXCOMPLIANCE;
  wire [127:0]PIPE_TXDATA;
  wire [15:0]PIPE_TXDATAK;
  wire [3:0]PIPE_TXDEEMPH;
  wire PIPE_TXDETECTRX;
  wire [7:0]PIPE_TXELECIDLE;
  wire [2:0]PIPE_TXMARGIN;
  wire Q;
  wire [2:0]TXMARGIN;
  wire all_phystatus_rst;
  wire [71:0]ext_ch_gt_drpaddr;
  wire [127:0]ext_ch_gt_drpdi;
  wire [127:0]ext_ch_gt_drpdo;
  wire [7:0]ext_ch_gt_drpen;
  wire [7:0]ext_ch_gt_drprdy;
  wire [7:0]ext_ch_gt_drpwe;
  wire [7:0]gt_ch_drp_rdy;
  wire [7:0]gt_rx_elec_idle_wire_filter;
  wire gt_rx_phy_status_q;
  wire [7:0]gt_rx_phy_status_wire_filter;
  wire \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ;
  wire gt_rxelecidle_q;
  wire [2:0]\index_reg[1] ;
  wire [2:0]\index_reg[1]_0 ;
  wire [2:0]\index_reg[1]_1 ;
  wire [2:0]\index_reg[1]_2 ;
  wire [2:0]\index_reg[1]_3 ;
  wire [2:0]\index_reg[1]_4 ;
  wire [2:0]\index_reg[1]_5 ;
  wire [2:0]\index_reg[1]_6 ;
  wire [7:0]int_pclk_sel_slave;
  wire [1:0]out;
  wire p_1_in;
  wire p_1_in116_in;
  wire p_1_in13_in;
  wire p_1_in31_in;
  wire p_1_in42_in;
  wire p_1_in60_in;
  wire p_1_in70_in;
  wire p_1_in88_in;
  wire [7:0]pci_exp_rxn;
  wire [7:0]pci_exp_rxp;
  wire [7:0]pci_exp_txn;
  wire [7:0]pci_exp_txp;
  wire [7:0]pclk_sel_reg1_reg;
  wire phy_rdy_n_int_i_2_n_0;
  wire [63:0]pipe_dmonitorout;
  wire [7:0]pipe_eyescandataerror;
  wire pipe_mmcm_rst_n;
  wire [3:0]pipe_qrst_fsm;
  wire pipe_qrst_idle;
  wire pipe_rate_idle;
  wire [3:0]pipe_rst_fsm;
  wire pipe_rx0_valid;
  wire pipe_rx1_valid;
  wire pipe_rx2_valid;
  wire pipe_rx3_valid;
  wire pipe_rx4_valid;
  wire pipe_rx5_valid;
  wire pipe_rx6_valid;
  wire pipe_rx7_valid;
  wire [23:0]pipe_rxbufstatus;
  wire [7:0]pipe_rxcommadet;
  wire [63:0]pipe_rxdisperr;
  wire [7:0]pipe_rxdlysresetdone;
  wire [63:0]pipe_rxnotintable;
  wire [7:0]pipe_rxoutclk_out;
  wire [7:0]pipe_rxphaligndone;
  wire [7:0]pipe_rxprbserr;
  wire [23:0]pipe_rxstatus;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_3 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_4 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_5 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_6 ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_1 ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_2 ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_3 ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_4 ;
  wire \pipe_stages_1.pipe_rx_elec_idle_q_reg_5 ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg_0 ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg_1 ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg_2 ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg_3 ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg_4 ;
  wire \pipe_stages_1.pipe_rx_phy_status_q_reg_5 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_3 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_4 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_5 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_6 ;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ;
  wire \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ;
  wire [55:0]pipe_sync_fsm_rx;
  wire pipe_tx_rcvr_det;
  wire [7:0]pipe_txdlysresetdone;
  wire [7:0]pipe_txinhibit;
  wire pipe_txoutclk_out;
  wire [7:0]pipe_txphaligndone;
  wire [7:0]pipe_txphinitdone;
  wire pipe_wrapper_i_n_295;
  wire pipe_wrapper_i_n_296;
  wire pipe_wrapper_i_n_297;
  wire pipe_wrapper_i_n_298;
  wire pipe_wrapper_i_n_299;
  wire pipe_wrapper_i_n_300;
  wire pipe_wrapper_i_n_301;
  wire pipe_wrapper_i_n_302;
  wire pipe_wrapper_i_n_303;
  wire pipe_wrapper_i_n_304;
  wire pipe_wrapper_i_n_305;
  wire pipe_wrapper_i_n_306;
  wire pipe_wrapper_i_n_307;
  wire pipe_wrapper_i_n_308;
  wire pipe_wrapper_i_n_309;
  wire pipe_wrapper_i_n_310;
  wire pipe_wrapper_i_n_375;
  wire pipe_wrapper_i_n_376;
  wire pipe_wrapper_i_n_533;
  wire pipe_wrapper_i_n_534;
  wire pipe_wrapper_i_n_535;
  wire pipe_wrapper_i_n_536;
  wire pipe_wrapper_i_n_537;
  wire pipe_wrapper_i_n_538;
  wire pipe_wrapper_i_n_539;
  wire pipe_wrapper_i_n_540;
  wire pipe_wrapper_i_n_541;
  wire pipe_wrapper_i_n_542;
  wire pipe_wrapper_i_n_543;
  wire pipe_wrapper_i_n_544;
  wire pipe_wrapper_i_n_545;
  wire pipe_wrapper_i_n_546;
  wire pipe_wrapper_i_n_547;
  wire pipe_wrapper_i_n_548;
  wire pipe_wrapper_i_n_549;
  wire pipe_wrapper_i_n_550;
  wire pipe_wrapper_i_n_552;
  wire pipe_wrapper_i_n_553;
  wire pipe_wrapper_i_n_554;
  wire pipe_wrapper_i_n_555;
  wire pipe_wrapper_i_n_556;
  wire pipe_wrapper_i_n_557;
  wire pipe_wrapper_i_n_558;
  wire pipe_wrapper_i_n_559;
  wire pipe_wrapper_i_n_560;
  wire pipe_wrapper_i_n_561;
  wire pipe_wrapper_i_n_562;
  wire pipe_wrapper_i_n_563;
  wire pipe_wrapper_i_n_564;
  wire pipe_wrapper_i_n_565;
  wire pipe_wrapper_i_n_566;
  wire pipe_wrapper_i_n_567;
  wire pipe_wrapper_i_n_568;
  wire pipe_wrapper_i_n_569;
  wire pipe_wrapper_i_n_573;
  wire pipe_wrapper_i_n_574;
  wire pipe_wrapper_i_n_575;
  wire pipe_wrapper_i_n_576;
  wire pipe_wrapper_i_n_577;
  wire pipe_wrapper_i_n_578;
  wire pipe_wrapper_i_n_579;
  wire pipe_wrapper_i_n_580;
  wire pipe_wrapper_i_n_581;
  wire pipe_wrapper_i_n_582;
  wire pipe_wrapper_i_n_583;
  wire pipe_wrapper_i_n_584;
  wire pipe_wrapper_i_n_585;
  wire pipe_wrapper_i_n_586;
  wire pipe_wrapper_i_n_587;
  wire pipe_wrapper_i_n_588;
  wire pipe_wrapper_i_n_589;
  wire pipe_wrapper_i_n_590;
  wire pipe_wrapper_i_n_592;
  wire pipe_wrapper_i_n_593;
  wire pipe_wrapper_i_n_594;
  wire pipe_wrapper_i_n_595;
  wire pipe_wrapper_i_n_596;
  wire pipe_wrapper_i_n_597;
  wire pipe_wrapper_i_n_598;
  wire pipe_wrapper_i_n_599;
  wire pipe_wrapper_i_n_600;
  wire pipe_wrapper_i_n_601;
  wire pipe_wrapper_i_n_602;
  wire pipe_wrapper_i_n_603;
  wire pipe_wrapper_i_n_604;
  wire pipe_wrapper_i_n_605;
  wire pipe_wrapper_i_n_606;
  wire pipe_wrapper_i_n_607;
  wire pipe_wrapper_i_n_608;
  wire pipe_wrapper_i_n_609;
  wire pipe_wrapper_i_n_611;
  wire pipe_wrapper_i_n_612;
  wire pipe_wrapper_i_n_613;
  wire pipe_wrapper_i_n_614;
  wire pipe_wrapper_i_n_615;
  wire pipe_wrapper_i_n_616;
  wire pipe_wrapper_i_n_617;
  wire pipe_wrapper_i_n_618;
  wire pipe_wrapper_i_n_619;
  wire pipe_wrapper_i_n_620;
  wire pipe_wrapper_i_n_621;
  wire pipe_wrapper_i_n_622;
  wire pipe_wrapper_i_n_623;
  wire pipe_wrapper_i_n_624;
  wire pipe_wrapper_i_n_625;
  wire pipe_wrapper_i_n_626;
  wire pipe_wrapper_i_n_627;
  wire pipe_wrapper_i_n_628;
  wire pipe_wrapper_i_n_630;
  wire pipe_wrapper_i_n_631;
  wire pipe_wrapper_i_n_632;
  wire pipe_wrapper_i_n_633;
  wire pipe_wrapper_i_n_634;
  wire pipe_wrapper_i_n_635;
  wire pipe_wrapper_i_n_636;
  wire pipe_wrapper_i_n_637;
  wire pipe_wrapper_i_n_638;
  wire pipe_wrapper_i_n_639;
  wire pipe_wrapper_i_n_640;
  wire pipe_wrapper_i_n_641;
  wire pipe_wrapper_i_n_642;
  wire pipe_wrapper_i_n_643;
  wire pipe_wrapper_i_n_644;
  wire pipe_wrapper_i_n_645;
  wire pipe_wrapper_i_n_646;
  wire pipe_wrapper_i_n_647;
  wire pipe_wrapper_i_n_665;
  wire pipe_wrapper_i_n_680;
  wire pipe_wrapper_i_n_695;
  wire pipe_wrapper_i_n_710;
  wire pipe_wrapper_i_n_725;
  wire pipe_wrapper_i_n_740;
  wire pipe_wrapper_i_n_755;
  wire pipe_wrapper_i_n_770;
  wire pipe_wrapper_i_n_775;
  wire pipe_wrapper_i_n_776;
  wire pipe_wrapper_i_n_777;
  wire pipe_wrapper_i_n_778;
  wire pipe_wrapper_i_n_779;
  wire pipe_wrapper_i_n_780;
  wire pipe_wrapper_i_n_781;
  wire pipe_wrapper_i_n_782;
  wire pipe_wrapper_i_n_783;
  wire pipe_wrapper_i_n_784;
  wire pipe_wrapper_i_n_785;
  wire pipe_wrapper_i_n_786;
  wire pipe_wrapper_i_n_787;
  wire pipe_wrapper_i_n_788;
  wire pipe_wrapper_i_n_789;
  wire pipe_wrapper_i_n_790;
  wire pipe_wrapper_i_n_791;
  wire pipe_wrapper_i_n_792;
  wire pipe_wrapper_i_n_793;
  wire pipe_wrapper_i_n_794;
  wire pipe_wrapper_i_n_795;
  wire pipe_wrapper_i_n_796;
  wire pipe_wrapper_i_n_797;
  wire pipe_wrapper_i_n_798;
  wire [5:0]pl_ltssm_state;
  wire [5:0]pl_ltssm_state_q;
  wire \pl_ltssm_state_q[5]_i_1_n_0 ;
  wire [0:0]rate_gen3;
  wire reg_clock_locked;
  wire reset_n_reg2_reg;
  wire sys_clk;
  wire sys_rst_n;
  wire sys_rst_n_0;
  wire [4:0]\sysclksel_reg[1] ;
  wire [4:0]\sysclksel_reg[1]_0 ;
  wire [4:0]\sysclksel_reg[1]_1 ;
  wire [4:0]\sysclksel_reg[1]_2 ;
  wire [4:0]\sysclksel_reg[1]_3 ;
  wire [4:0]\sysclksel_reg[1]_4 ;
  wire [4:0]\sysclksel_reg[1]_5 ;
  wire [4:0]\sysclksel_reg[1]_6 ;
  wire [5:0]\txsync_fsm.txdlyen_reg ;
  wire [5:0]\txsync_fsm.txdlyen_reg_0 ;
  wire [5:0]\txsync_fsm.txdlyen_reg_1 ;
  wire [5:0]\txsync_fsm.txdlyen_reg_2 ;
  wire [5:0]\txsync_fsm.txdlyen_reg_3 ;
  wire [5:0]\txsync_fsm.txdlyen_reg_4 ;
  wire [5:0]\txsync_fsm.txdlyen_reg_5 ;
  wire [5:0]\txsync_fsm.txsync_done_reg ;

  PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst 
       (.CLK_PCLK(CLK_PCLK),
        .D(D),
        .PIPE_RXDATA({pipe_wrapper_i_n_295,pipe_wrapper_i_n_296,pipe_wrapper_i_n_297,pipe_wrapper_i_n_298,pipe_wrapper_i_n_299,pipe_wrapper_i_n_300,pipe_wrapper_i_n_301,pipe_wrapper_i_n_302,pipe_wrapper_i_n_303,pipe_wrapper_i_n_304,pipe_wrapper_i_n_305,pipe_wrapper_i_n_306,pipe_wrapper_i_n_307,pipe_wrapper_i_n_308,pipe_wrapper_i_n_309,pipe_wrapper_i_n_310}),
        .PIPE_RXDATAK({pipe_wrapper_i_n_375,pipe_wrapper_i_n_376}),
        .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[0]),
        .Q(Q),
        .gt_rx_phy_status_q(gt_rx_phy_status_q),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[0]),
        .\gt_rx_status_q_reg[2]_0 (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
        .gt_rxelecidle_q(gt_rxelecidle_q),
        .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_665),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (\pipe_stages_1.pipe_rx_data_q_reg[15] ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] (\pipe_stages_1.pipe_rx_status_q_reg[2] ),
        .\pipe_stages_1.pipe_rx_valid_q_reg (pipe_rx0_valid),
        .\pl_ltssm_state_q_reg[5] (pl_ltssm_state_q),
        .\pl_ltssm_state_q_reg[5]_0 ({pipe_wrapper_i_n_796,pipe_wrapper_i_n_797,pipe_wrapper_i_n_798}));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_22 \gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst 
       (.CLK_PCLK(CLK_PCLK),
        .D({pipe_wrapper_i_n_793,pipe_wrapper_i_n_794,pipe_wrapper_i_n_795}),
        .PIPE_RXDATA(GT_RXDATA),
        .PIPE_RXDATAK(GT_RXCHARISK),
        .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[1]),
        .Q(Q),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[1]),
        .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_680),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg (\pipe_stages_1.pipe_rx_elec_idle_q_reg ),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg (\pipe_stages_1.pipe_rx_phy_status_q_reg ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] (\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ),
        .\pipe_stages_1.pipe_rx_valid_q_reg (pipe_rx1_valid),
        .\pl_ltssm_state_q_reg[4] (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
        .\pl_ltssm_state_q_reg[5] ({pl_ltssm_state_q[5],pl_ltssm_state_q[0]}));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_23 \gt_rx_valid_filter[2].GT_RX_VALID_FILTER_7x_inst 
       (.CLK_PCLK(CLK_PCLK),
        .D({pipe_wrapper_i_n_790,pipe_wrapper_i_n_791,pipe_wrapper_i_n_792}),
        .PIPE_RXDATA({pipe_wrapper_i_n_533,pipe_wrapper_i_n_534,pipe_wrapper_i_n_535,pipe_wrapper_i_n_536,pipe_wrapper_i_n_537,pipe_wrapper_i_n_538,pipe_wrapper_i_n_539,pipe_wrapper_i_n_540,pipe_wrapper_i_n_541,pipe_wrapper_i_n_542,pipe_wrapper_i_n_543,pipe_wrapper_i_n_544,pipe_wrapper_i_n_545,pipe_wrapper_i_n_546,pipe_wrapper_i_n_547,pipe_wrapper_i_n_548}),
        .PIPE_RXDATAK({pipe_wrapper_i_n_549,pipe_wrapper_i_n_550}),
        .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[2]),
        .Q(Q),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[2]),
        .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_695),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg (\pipe_stages_1.pipe_rx_elec_idle_q_reg_0 ),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg (\pipe_stages_1.pipe_rx_phy_status_q_reg_0 ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] (\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ),
        .\pipe_stages_1.pipe_rx_valid_q_reg (pipe_rx2_valid),
        .\pl_ltssm_state_q_reg[4] (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
        .\pl_ltssm_state_q_reg[5] ({pl_ltssm_state_q[5],pl_ltssm_state_q[0]}));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_24 \gt_rx_valid_filter[3].GT_RX_VALID_FILTER_7x_inst 
       (.CLK_PCLK(CLK_PCLK),
        .D({pipe_wrapper_i_n_787,pipe_wrapper_i_n_788,pipe_wrapper_i_n_789}),
        .PIPE_RXDATA({pipe_wrapper_i_n_552,pipe_wrapper_i_n_553,pipe_wrapper_i_n_554,pipe_wrapper_i_n_555,pipe_wrapper_i_n_556,pipe_wrapper_i_n_557,pipe_wrapper_i_n_558,pipe_wrapper_i_n_559,pipe_wrapper_i_n_560,pipe_wrapper_i_n_561,pipe_wrapper_i_n_562,pipe_wrapper_i_n_563,pipe_wrapper_i_n_564,pipe_wrapper_i_n_565,pipe_wrapper_i_n_566,pipe_wrapper_i_n_567}),
        .PIPE_RXDATAK({pipe_wrapper_i_n_568,pipe_wrapper_i_n_569}),
        .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[3]),
        .Q(Q),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[3]),
        .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_710),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg (\pipe_stages_1.pipe_rx_elec_idle_q_reg_1 ),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg (\pipe_stages_1.pipe_rx_phy_status_q_reg_1 ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] (\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ),
        .\pipe_stages_1.pipe_rx_valid_q_reg (pipe_rx3_valid),
        .\pl_ltssm_state_q_reg[4] (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
        .\pl_ltssm_state_q_reg[5] ({pl_ltssm_state_q[5],pl_ltssm_state_q[0]}));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_25 \gt_rx_valid_filter[4].GT_RX_VALID_FILTER_7x_inst 
       (.CLK_PCLK(CLK_PCLK),
        .D({pipe_wrapper_i_n_784,pipe_wrapper_i_n_785,pipe_wrapper_i_n_786}),
        .PIPE_RXDATA({pipe_wrapper_i_n_573,pipe_wrapper_i_n_574,pipe_wrapper_i_n_575,pipe_wrapper_i_n_576,pipe_wrapper_i_n_577,pipe_wrapper_i_n_578,pipe_wrapper_i_n_579,pipe_wrapper_i_n_580,pipe_wrapper_i_n_581,pipe_wrapper_i_n_582,pipe_wrapper_i_n_583,pipe_wrapper_i_n_584,pipe_wrapper_i_n_585,pipe_wrapper_i_n_586,pipe_wrapper_i_n_587,pipe_wrapper_i_n_588}),
        .PIPE_RXDATAK({pipe_wrapper_i_n_589,pipe_wrapper_i_n_590}),
        .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[4]),
        .Q(Q),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[4]),
        .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_725),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (\pipe_stages_1.pipe_rx_data_q_reg[15]_3 ),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg (\pipe_stages_1.pipe_rx_elec_idle_q_reg_2 ),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg (\pipe_stages_1.pipe_rx_phy_status_q_reg_2 ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] (\pipe_stages_1.pipe_rx_status_q_reg[2]_3 ),
        .\pipe_stages_1.pipe_rx_valid_q_reg (pipe_rx4_valid),
        .\pl_ltssm_state_q_reg[4] (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
        .\pl_ltssm_state_q_reg[5] ({pl_ltssm_state_q[5],pl_ltssm_state_q[0]}));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_26 \gt_rx_valid_filter[5].GT_RX_VALID_FILTER_7x_inst 
       (.CLK_PCLK(CLK_PCLK),
        .D({pipe_wrapper_i_n_781,pipe_wrapper_i_n_782,pipe_wrapper_i_n_783}),
        .PIPE_RXDATA({pipe_wrapper_i_n_592,pipe_wrapper_i_n_593,pipe_wrapper_i_n_594,pipe_wrapper_i_n_595,pipe_wrapper_i_n_596,pipe_wrapper_i_n_597,pipe_wrapper_i_n_598,pipe_wrapper_i_n_599,pipe_wrapper_i_n_600,pipe_wrapper_i_n_601,pipe_wrapper_i_n_602,pipe_wrapper_i_n_603,pipe_wrapper_i_n_604,pipe_wrapper_i_n_605,pipe_wrapper_i_n_606,pipe_wrapper_i_n_607}),
        .PIPE_RXDATAK({pipe_wrapper_i_n_608,pipe_wrapper_i_n_609}),
        .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[5]),
        .Q(Q),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[5]),
        .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_740),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (\pipe_stages_1.pipe_rx_data_q_reg[15]_4 ),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg (\pipe_stages_1.pipe_rx_elec_idle_q_reg_3 ),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg (\pipe_stages_1.pipe_rx_phy_status_q_reg_3 ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] (\pipe_stages_1.pipe_rx_status_q_reg[2]_4 ),
        .\pipe_stages_1.pipe_rx_valid_q_reg (pipe_rx5_valid),
        .\pl_ltssm_state_q_reg[4] (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
        .\pl_ltssm_state_q_reg[5] ({pl_ltssm_state_q[5],pl_ltssm_state_q[0]}));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_27 \gt_rx_valid_filter[6].GT_RX_VALID_FILTER_7x_inst 
       (.CLK_PCLK(CLK_PCLK),
        .D({pipe_wrapper_i_n_778,pipe_wrapper_i_n_779,pipe_wrapper_i_n_780}),
        .PIPE_RXDATA({pipe_wrapper_i_n_611,pipe_wrapper_i_n_612,pipe_wrapper_i_n_613,pipe_wrapper_i_n_614,pipe_wrapper_i_n_615,pipe_wrapper_i_n_616,pipe_wrapper_i_n_617,pipe_wrapper_i_n_618,pipe_wrapper_i_n_619,pipe_wrapper_i_n_620,pipe_wrapper_i_n_621,pipe_wrapper_i_n_622,pipe_wrapper_i_n_623,pipe_wrapper_i_n_624,pipe_wrapper_i_n_625,pipe_wrapper_i_n_626}),
        .PIPE_RXDATAK({pipe_wrapper_i_n_627,pipe_wrapper_i_n_628}),
        .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[6]),
        .Q(Q),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[6]),
        .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_755),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (\pipe_stages_1.pipe_rx_data_q_reg[15]_5 ),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg (\pipe_stages_1.pipe_rx_elec_idle_q_reg_4 ),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg (\pipe_stages_1.pipe_rx_phy_status_q_reg_4 ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] (\pipe_stages_1.pipe_rx_status_q_reg[2]_5 ),
        .\pipe_stages_1.pipe_rx_valid_q_reg (pipe_rx6_valid),
        .\pl_ltssm_state_q_reg[4] (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
        .\pl_ltssm_state_q_reg[5] ({pl_ltssm_state_q[5],pl_ltssm_state_q[0]}));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_rx_valid_filter_7x_28 \gt_rx_valid_filter[7].GT_RX_VALID_FILTER_7x_inst 
       (.CLK_PCLK(CLK_PCLK),
        .D({pipe_wrapper_i_n_775,pipe_wrapper_i_n_776,pipe_wrapper_i_n_777}),
        .PIPE_RXDATA({pipe_wrapper_i_n_630,pipe_wrapper_i_n_631,pipe_wrapper_i_n_632,pipe_wrapper_i_n_633,pipe_wrapper_i_n_634,pipe_wrapper_i_n_635,pipe_wrapper_i_n_636,pipe_wrapper_i_n_637,pipe_wrapper_i_n_638,pipe_wrapper_i_n_639,pipe_wrapper_i_n_640,pipe_wrapper_i_n_641,pipe_wrapper_i_n_642,pipe_wrapper_i_n_643,pipe_wrapper_i_n_644,pipe_wrapper_i_n_645}),
        .PIPE_RXDATAK({pipe_wrapper_i_n_646,pipe_wrapper_i_n_647}),
        .PIPE_RXELECIDLE(gt_rx_elec_idle_wire_filter[7]),
        .Q(Q),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[7]),
        .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_770),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5 ),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (\pipe_stages_1.pipe_rx_data_q_reg[15]_6 ),
        .\pipe_stages_1.pipe_rx_elec_idle_q_reg (\pipe_stages_1.pipe_rx_elec_idle_q_reg_5 ),
        .\pipe_stages_1.pipe_rx_phy_status_q_reg (\pipe_stages_1.pipe_rx_phy_status_q_reg_5 ),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] (\pipe_stages_1.pipe_rx_status_q_reg[2]_6 ),
        .\pipe_stages_1.pipe_rx_valid_q_reg (pipe_rx7_valid),
        .\pl_ltssm_state_q_reg[4] (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
        .\pl_ltssm_state_q_reg[5] ({pl_ltssm_state_q[5],pl_ltssm_state_q[0]}));
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_10__0__0 
       (.I0(GT_TXPMARESET092_out),
        .I1(p_1_in88_in),
        .O(GT_RXPMARESET089_out));
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_10__1__0 
       (.I0(GT_TXPMARESET064_out),
        .I1(p_1_in60_in),
        .O(GT_RXPMARESET061_out));
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_10__2__0 
       (.I0(GT_TXPMARESET046_out),
        .I1(p_1_in42_in),
        .O(GT_RXPMARESET043_out));
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_10__3 
       (.I0(GT_TXPMARESET0),
        .I1(p_1_in),
        .O(GT_RXPMARESET0));
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_11__0__0 
       (.I0(GT_TXPMARESET074_out),
        .I1(p_1_in70_in),
        .O(GT_RXPMARESET071_out));
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_11__1__0 
       (.I0(GT_TXPMARESET035_out),
        .I1(p_1_in31_in),
        .O(GT_RXPMARESET032_out));
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_11__2__0 
       (.I0(GT_TXPMARESET017_out),
        .I1(p_1_in13_in),
        .O(GT_RXPMARESET014_out));
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_11__3 
       (.I0(GT_TXPMARESET0120_out),
        .I1(p_1_in116_in),
        .O(GT_RXPMARESET0117_out));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_29
       (.I0(Q),
        .O(sys_rst_n));
  LUT1 #(
    .INIT(2'h1)) 
    phy_rdy_n_int_i_2
       (.I0(reg_clock_locked),
        .O(phy_rdy_n_int_i_2_n_0));
  FDCE #(
    .INIT(1'b0)) 
    phy_rdy_n_int_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .CLR(phy_rdy_n_int_i_2_n_0),
        .D(all_phystatus_rst),
        .Q(Q));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_wrapper pipe_wrapper_i
       (.CLK_DCLK(CLK_DCLK),
        .CLK_MMCM_LOCK(CLK_MMCM_LOCK),
        .CLK_OOBCLK(CLK_PCLK),
        .CLK_PCLK_SEL(pclk_sel_reg1_reg),
        .CLK_USERCLK1(CLK_USERCLK1),
        .D(all_phystatus_rst),
        .DRP_FSM(\index_reg[1] ),
        .EQ_GEN3(rate_gen3),
        .GT_RXPMARESET0(GT_RXPMARESET0),
        .GT_RXPMARESET0117_out(GT_RXPMARESET0117_out),
        .GT_RXPMARESET014_out(GT_RXPMARESET014_out),
        .GT_RXPMARESET032_out(GT_RXPMARESET032_out),
        .GT_RXPMARESET043_out(GT_RXPMARESET043_out),
        .GT_RXPMARESET061_out(GT_RXPMARESET061_out),
        .GT_RXPMARESET071_out(GT_RXPMARESET071_out),
        .GT_RXPMARESET089_out(GT_RXPMARESET089_out),
        .GT_TXPMARESET0(GT_TXPMARESET0),
        .GT_TXPMARESET0120_out(GT_TXPMARESET0120_out),
        .GT_TXPMARESET017_out(GT_TXPMARESET017_out),
        .GT_TXPMARESET035_out(GT_TXPMARESET035_out),
        .GT_TXPMARESET046_out(GT_TXPMARESET046_out),
        .GT_TXPMARESET064_out(GT_TXPMARESET064_out),
        .GT_TXPMARESET074_out(GT_TXPMARESET074_out),
        .GT_TXPMARESET092_out(GT_TXPMARESET092_out),
        .PIPE_POWERDOWN(PIPE_POWERDOWN),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
        .PIPE_RXDATA({pipe_wrapper_i_n_295,pipe_wrapper_i_n_296,pipe_wrapper_i_n_297,pipe_wrapper_i_n_298,pipe_wrapper_i_n_299,pipe_wrapper_i_n_300,pipe_wrapper_i_n_301,pipe_wrapper_i_n_302,pipe_wrapper_i_n_303,pipe_wrapper_i_n_304,pipe_wrapper_i_n_305,pipe_wrapper_i_n_306,pipe_wrapper_i_n_307,pipe_wrapper_i_n_308,pipe_wrapper_i_n_309,pipe_wrapper_i_n_310}),
        .PIPE_RXDATAK({pipe_wrapper_i_n_375,pipe_wrapper_i_n_376}),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE),
        .PIPE_TXDATA(PIPE_TXDATA),
        .PIPE_TXDATAK(PIPE_TXDATAK),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH),
        .PIPE_TXDETECTRX(PIPE_TXDETECTRX),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE),
        .PIPE_TXMARGIN(PIPE_TXMARGIN),
        .Q({pl_ltssm_state_q[5],pl_ltssm_state_q[0]}),
        .QRST_CPLLLOCK(PIPE_CPLL_LOCK),
        .QRST_QPLLLOCK(PIPE_QPLL_LOCK),
        .RATE_FSM(\sysclksel_reg[1] ),
        .SYNC_FSM_TX(\txsync_fsm.txsync_done_reg ),
        .SYNC_RXPHALIGNDONE_M(pipe_rxphaligndone[0]),
        .TXMARGIN(TXMARGIN),
        .USER_RXPMARESET(p_1_in),
        .\cplllock_reg1_reg[1] (p_1_in88_in),
        .\cplllock_reg1_reg[2] (p_1_in116_in),
        .\cplllock_reg1_reg[3] (INT_QPLLOUTCLK_OUT[0]),
        .\cplllock_reg1_reg[3]_0 (INT_QPLLOUTREFCLK_OUT[0]),
        .\cplllock_reg1_reg[3]_1 (p_1_in70_in),
        .\cplllock_reg1_reg[4] (p_1_in60_in),
        .\cplllock_reg1_reg[5] (p_1_in42_in),
        .\cplllock_reg1_reg[6] (p_1_in31_in),
        .\cplllock_reg1_reg[7] (INT_QPLLOUTCLK_OUT[1]),
        .\cplllock_reg1_reg[7]_0 (INT_QPLLOUTREFCLK_OUT[1]),
        .\cplllock_reg1_reg[7]_1 (p_1_in13_in),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo),
        .ext_ch_gt_drpen(ext_ch_gt_drpen),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe),
        .gt_ch_drp_rdy(gt_ch_drp_rdy),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter),
        .\gt_rx_status_q_reg[2] ({pipe_wrapper_i_n_775,pipe_wrapper_i_n_776,pipe_wrapper_i_n_777}),
        .\gt_rx_status_q_reg[2]_0 ({pipe_wrapper_i_n_778,pipe_wrapper_i_n_779,pipe_wrapper_i_n_780}),
        .\gt_rx_status_q_reg[2]_1 ({pipe_wrapper_i_n_781,pipe_wrapper_i_n_782,pipe_wrapper_i_n_783}),
        .\gt_rx_status_q_reg[2]_2 ({pipe_wrapper_i_n_784,pipe_wrapper_i_n_785,pipe_wrapper_i_n_786}),
        .\gt_rx_status_q_reg[2]_3 ({pipe_wrapper_i_n_787,pipe_wrapper_i_n_788,pipe_wrapper_i_n_789}),
        .\gt_rx_status_q_reg[2]_4 ({pipe_wrapper_i_n_790,pipe_wrapper_i_n_791,pipe_wrapper_i_n_792}),
        .\gt_rx_status_q_reg[2]_5 ({pipe_wrapper_i_n_793,pipe_wrapper_i_n_794,pipe_wrapper_i_n_795}),
        .\gt_rx_status_q_reg[2]_6 ({pipe_wrapper_i_n_796,pipe_wrapper_i_n_797,pipe_wrapper_i_n_798}),
        .\gt_rxcharisk_q_reg[1] (GT_RXCHARISK),
        .\gt_rxcharisk_q_reg[1]_0 ({pipe_wrapper_i_n_549,pipe_wrapper_i_n_550}),
        .\gt_rxcharisk_q_reg[1]_1 ({pipe_wrapper_i_n_568,pipe_wrapper_i_n_569}),
        .\gt_rxcharisk_q_reg[1]_2 ({pipe_wrapper_i_n_589,pipe_wrapper_i_n_590}),
        .\gt_rxcharisk_q_reg[1]_3 ({pipe_wrapper_i_n_608,pipe_wrapper_i_n_609}),
        .\gt_rxcharisk_q_reg[1]_4 ({pipe_wrapper_i_n_627,pipe_wrapper_i_n_628}),
        .\gt_rxcharisk_q_reg[1]_5 ({pipe_wrapper_i_n_646,pipe_wrapper_i_n_647}),
        .\gt_rxdata_q_reg[15] (GT_RXDATA),
        .\gt_rxdata_q_reg[15]_0 ({pipe_wrapper_i_n_533,pipe_wrapper_i_n_534,pipe_wrapper_i_n_535,pipe_wrapper_i_n_536,pipe_wrapper_i_n_537,pipe_wrapper_i_n_538,pipe_wrapper_i_n_539,pipe_wrapper_i_n_540,pipe_wrapper_i_n_541,pipe_wrapper_i_n_542,pipe_wrapper_i_n_543,pipe_wrapper_i_n_544,pipe_wrapper_i_n_545,pipe_wrapper_i_n_546,pipe_wrapper_i_n_547,pipe_wrapper_i_n_548}),
        .\gt_rxdata_q_reg[15]_1 ({pipe_wrapper_i_n_552,pipe_wrapper_i_n_553,pipe_wrapper_i_n_554,pipe_wrapper_i_n_555,pipe_wrapper_i_n_556,pipe_wrapper_i_n_557,pipe_wrapper_i_n_558,pipe_wrapper_i_n_559,pipe_wrapper_i_n_560,pipe_wrapper_i_n_561,pipe_wrapper_i_n_562,pipe_wrapper_i_n_563,pipe_wrapper_i_n_564,pipe_wrapper_i_n_565,pipe_wrapper_i_n_566,pipe_wrapper_i_n_567}),
        .\gt_rxdata_q_reg[15]_2 ({pipe_wrapper_i_n_573,pipe_wrapper_i_n_574,pipe_wrapper_i_n_575,pipe_wrapper_i_n_576,pipe_wrapper_i_n_577,pipe_wrapper_i_n_578,pipe_wrapper_i_n_579,pipe_wrapper_i_n_580,pipe_wrapper_i_n_581,pipe_wrapper_i_n_582,pipe_wrapper_i_n_583,pipe_wrapper_i_n_584,pipe_wrapper_i_n_585,pipe_wrapper_i_n_586,pipe_wrapper_i_n_587,pipe_wrapper_i_n_588}),
        .\gt_rxdata_q_reg[15]_3 ({pipe_wrapper_i_n_592,pipe_wrapper_i_n_593,pipe_wrapper_i_n_594,pipe_wrapper_i_n_595,pipe_wrapper_i_n_596,pipe_wrapper_i_n_597,pipe_wrapper_i_n_598,pipe_wrapper_i_n_599,pipe_wrapper_i_n_600,pipe_wrapper_i_n_601,pipe_wrapper_i_n_602,pipe_wrapper_i_n_603,pipe_wrapper_i_n_604,pipe_wrapper_i_n_605,pipe_wrapper_i_n_606,pipe_wrapper_i_n_607}),
        .\gt_rxdata_q_reg[15]_4 ({pipe_wrapper_i_n_611,pipe_wrapper_i_n_612,pipe_wrapper_i_n_613,pipe_wrapper_i_n_614,pipe_wrapper_i_n_615,pipe_wrapper_i_n_616,pipe_wrapper_i_n_617,pipe_wrapper_i_n_618,pipe_wrapper_i_n_619,pipe_wrapper_i_n_620,pipe_wrapper_i_n_621,pipe_wrapper_i_n_622,pipe_wrapper_i_n_623,pipe_wrapper_i_n_624,pipe_wrapper_i_n_625,pipe_wrapper_i_n_626}),
        .\gt_rxdata_q_reg[15]_5 ({pipe_wrapper_i_n_630,pipe_wrapper_i_n_631,pipe_wrapper_i_n_632,pipe_wrapper_i_n_633,pipe_wrapper_i_n_634,pipe_wrapper_i_n_635,pipe_wrapper_i_n_636,pipe_wrapper_i_n_637,pipe_wrapper_i_n_638,pipe_wrapper_i_n_639,pipe_wrapper_i_n_640,pipe_wrapper_i_n_641,pipe_wrapper_i_n_642,pipe_wrapper_i_n_643,pipe_wrapper_i_n_644,pipe_wrapper_i_n_645}),
        .gt_rxvalid_q_reg(pipe_wrapper_i_n_665),
        .gt_rxvalid_q_reg_0(pipe_wrapper_i_n_680),
        .gt_rxvalid_q_reg_1(pipe_wrapper_i_n_695),
        .gt_rxvalid_q_reg_10(pipe_rx3_valid),
        .gt_rxvalid_q_reg_11(pipe_rx4_valid),
        .gt_rxvalid_q_reg_12(pipe_rx5_valid),
        .gt_rxvalid_q_reg_13(pipe_rx6_valid),
        .gt_rxvalid_q_reg_14(pipe_rx7_valid),
        .gt_rxvalid_q_reg_2(pipe_wrapper_i_n_710),
        .gt_rxvalid_q_reg_3(pipe_wrapper_i_n_725),
        .gt_rxvalid_q_reg_4(pipe_wrapper_i_n_740),
        .gt_rxvalid_q_reg_5(pipe_wrapper_i_n_755),
        .gt_rxvalid_q_reg_6(pipe_wrapper_i_n_770),
        .gt_rxvalid_q_reg_7(pipe_rx0_valid),
        .gt_rxvalid_q_reg_8(pipe_rx1_valid),
        .gt_rxvalid_q_reg_9(pipe_rx2_valid),
        .\index_reg[1] (\index_reg[1]_0 ),
        .\index_reg[1]_0 (\index_reg[1]_1 ),
        .\index_reg[1]_1 (\index_reg[1]_2 ),
        .\index_reg[1]_2 (\index_reg[1]_3 ),
        .\index_reg[1]_3 (\index_reg[1]_4 ),
        .\index_reg[1]_4 (\index_reg[1]_5 ),
        .\index_reg[1]_5 (\index_reg[1]_6 ),
        .int_pclk_sel_slave(int_pclk_sel_slave),
        .out(out),
        .pci_exp_rxn(pci_exp_rxn),
        .pci_exp_rxp(pci_exp_rxp),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .pipe_dmonitorout(pipe_dmonitorout),
        .pipe_eyescandataerror(pipe_eyescandataerror),
        .pipe_mmcm_rst_n(pipe_mmcm_rst_n),
        .pipe_qrst_fsm(pipe_qrst_fsm),
        .pipe_qrst_idle(pipe_qrst_idle),
        .pipe_rate_idle(pipe_rate_idle),
        .pipe_rst_fsm(pipe_rst_fsm),
        .pipe_rxbufstatus(pipe_rxbufstatus),
        .pipe_rxcommadet(pipe_rxcommadet),
        .pipe_rxdisperr(pipe_rxdisperr),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone),
        .pipe_rxnotintable(pipe_rxnotintable),
        .pipe_rxoutclk_out(pipe_rxoutclk_out),
        .pipe_rxphaligndone(pipe_rxphaligndone[7:1]),
        .pipe_rxprbserr(pipe_rxprbserr),
        .pipe_rxstatus(pipe_rxstatus),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2] (\pipe_stages_1.pipe_tx_margin_q_reg[2] ),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep (\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep (\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ),
        .\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 (\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det),
        .pipe_txdlysresetdone(pipe_txdlysresetdone),
        .pipe_txinhibit(pipe_txinhibit),
        .pipe_txoutclk_out(pipe_txoutclk_out),
        .pipe_txphaligndone(pipe_txphaligndone),
        .pipe_txphinitdone(pipe_txphinitdone),
        .\pl_ltssm_state_q_reg[4] (\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_3 ),
        .reset_n_reg2_reg_0(reset_n_reg2_reg),
        .sys_clk(sys_clk),
        .sys_rst_n(sys_rst_n_0),
        .\sysclksel_reg[1] (\sysclksel_reg[1]_0 ),
        .\sysclksel_reg[1]_0 (\sysclksel_reg[1]_1 ),
        .\sysclksel_reg[1]_1 (\sysclksel_reg[1]_2 ),
        .\sysclksel_reg[1]_2 (\sysclksel_reg[1]_3 ),
        .\sysclksel_reg[1]_3 (\sysclksel_reg[1]_4 ),
        .\sysclksel_reg[1]_4 (\sysclksel_reg[1]_5 ),
        .\sysclksel_reg[1]_5 (\sysclksel_reg[1]_6 ),
        .\txsync_fsm.txdlyen_reg (\txsync_fsm.txdlyen_reg ),
        .\txsync_fsm.txdlyen_reg_0 (\txsync_fsm.txdlyen_reg_0 ),
        .\txsync_fsm.txdlyen_reg_1 (\txsync_fsm.txdlyen_reg_1 ),
        .\txsync_fsm.txdlyen_reg_2 (\txsync_fsm.txdlyen_reg_2 ),
        .\txsync_fsm.txdlyen_reg_3 (\txsync_fsm.txdlyen_reg_3 ),
        .\txsync_fsm.txdlyen_reg_4 (\txsync_fsm.txdlyen_reg_4 ),
        .\txsync_fsm.txdlyen_reg_5 (\txsync_fsm.txdlyen_reg_5 ));
  LUT1 #(
    .INIT(2'h1)) 
    \pl_ltssm_state_q[5]_i_1 
       (.I0(CLK_MMCM_LOCK),
        .O(\pl_ltssm_state_q[5]_i_1_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \pl_ltssm_state_q_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .CLR(\pl_ltssm_state_q[5]_i_1_n_0 ),
        .D(pl_ltssm_state[0]),
        .Q(pl_ltssm_state_q[0]));
  FDCE #(
    .INIT(1'b0)) 
    \pl_ltssm_state_q_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .CLR(\pl_ltssm_state_q[5]_i_1_n_0 ),
        .D(pl_ltssm_state[1]),
        .Q(pl_ltssm_state_q[1]));
  FDCE #(
    .INIT(1'b0)) 
    \pl_ltssm_state_q_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .CLR(\pl_ltssm_state_q[5]_i_1_n_0 ),
        .D(pl_ltssm_state[2]),
        .Q(pl_ltssm_state_q[2]));
  FDCE #(
    .INIT(1'b0)) 
    \pl_ltssm_state_q_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .CLR(\pl_ltssm_state_q[5]_i_1_n_0 ),
        .D(pl_ltssm_state[3]),
        .Q(pl_ltssm_state_q[3]));
  FDCE #(
    .INIT(1'b0)) 
    \pl_ltssm_state_q_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .CLR(\pl_ltssm_state_q[5]_i_1_n_0 ),
        .D(pl_ltssm_state[4]),
        .Q(pl_ltssm_state_q[4]));
  FDCE #(
    .INIT(1'b0)) 
    \pl_ltssm_state_q_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .CLR(\pl_ltssm_state_q[5]_i_1_n_0 ),
        .D(pl_ltssm_state[5]),
        .Q(pl_ltssm_state_q[5]));
  FDCE #(
    .INIT(1'b0)) 
    reg_clock_locked_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .CLR(\pl_ltssm_state_q[5]_i_1_n_0 ),
        .D(1'b1),
        .Q(reg_clock_locked));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper
   (RATE_CPLLLOCK,
    ext_ch_gt_drprdy,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    RATE_PHYSTATUS,
    rxcdrlock_reg1_reg,
    PIPE_RXCHANISALIGNED,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    gt_rx_elec_idle_wire_filter,
    pipe_rxoutclk_out,
    SYNC_RXPHALIGNDONE_M,
    pipe_rxprbserr,
    RATE_RXRATEDONE,
    USER_RXRESETDONE,
    rxvalid_reg1_reg,
    pipe_txdlysresetdone,
    pipe_txoutclk_out,
    pipe_txphaligndone,
    pipe_txphinitdone,
    RATE_TXRATEDONE,
    USER_TXRESETDONE,
    ext_ch_gt_drpdo,
    pipe_rxbufstatus,
    pipe_rxstatus,
    RXCHBONDO,
    PIPE_RXDATA,
    pipe_dmonitorout,
    PIPE_RXDATAK,
    pipe_rxdisperr,
    pipe_rxnotintable,
    \gt_rx_status_q_reg[2] ,
    gt_cpllpdrefclk,
    CLK,
    \fsm_reg[2] ,
    \fsm_reg[0] ,
    USER_EYESCANRESET,
    sys_clk,
    DRP_GTXRESET,
    pci_exp_rxn,
    pci_exp_rxp,
    qpllpd_reg,
    qpllpd_reg_0,
    \resetovrd_disble.fsm_reg[1] ,
    gen3_reg,
    USER_RXBUFRESET,
    USER_RXCDRFREQRESET,
    USER_RXCDRRESET,
    O1671,
    converge_gen3_reg,
    USER_RXDFELPMRESET,
    SYNC_RXSYNC_DONE,
    \rxsync_fsm_disable.fsm_rx_reg[2] ,
    USER_RXPCSRESET,
    \rxsync_fsm_disable.fsm_rx_reg[2]_0 ,
    GT_RXPMARESET0,
    PIPE_RXPOLARITY,
    userrdy_reg_rep__5,
    pclk_sel_reg,
    PIPE_TXDEEMPH,
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ,
    \txsync_fsm.txdlyen_reg ,
    \txsync_fsm.fsm_tx_reg[2] ,
    PIPE_TXELECIDLE,
    pipe_txinhibit,
    \txsync_fsm.fsm_tx_reg[4] ,
    \txsync_fsm.fsm_tx_reg[4]_0 ,
    GT_TXPMARESET0,
    DRPDI,
    PIPE_POWERDOWN,
    RXSYSCLKSEL,
    RXRATE,
    TXMARGIN,
    USER_OOBCLK,
    TXPOSTCURSOR,
    TXPRECURSOR,
    PIPE_TXDATA,
    TXMAINCURSOR,
    PIPE_TXCOMPLIANCE,
    PIPE_TXDATAK,
    DRPADDR,
    Q,
    \pl_ltssm_state_q_reg[4] ,
    gt_rxvalid_q_reg,
    rst_cpllpd,
    p_0_in3_in,
    RST_CPLLRESET,
    p_0_in2_in);
  output RATE_CPLLLOCK;
  output [0:0]ext_ch_gt_drprdy;
  output [0:0]pipe_eyescandataerror;
  output [0:0]pci_exp_txn;
  output [0:0]pci_exp_txp;
  output RATE_PHYSTATUS;
  output rxcdrlock_reg1_reg;
  output [0:0]PIPE_RXCHANISALIGNED;
  output [0:0]pipe_rxcommadet;
  output [0:0]pipe_rxdlysresetdone;
  output [0:0]gt_rx_elec_idle_wire_filter;
  output [0:0]pipe_rxoutclk_out;
  output SYNC_RXPHALIGNDONE_M;
  output [0:0]pipe_rxprbserr;
  output RATE_RXRATEDONE;
  output USER_RXRESETDONE;
  output rxvalid_reg1_reg;
  output [0:0]pipe_txdlysresetdone;
  output pipe_txoutclk_out;
  output [0:0]pipe_txphaligndone;
  output [0:0]pipe_txphinitdone;
  output RATE_TXRATEDONE;
  output USER_TXRESETDONE;
  output [15:0]ext_ch_gt_drpdo;
  output [2:0]pipe_rxbufstatus;
  output [2:0]pipe_rxstatus;
  output [4:0]RXCHBONDO;
  output [15:0]PIPE_RXDATA;
  output [7:0]pipe_dmonitorout;
  output [1:0]PIPE_RXDATAK;
  output [7:0]pipe_rxdisperr;
  output [7:0]pipe_rxnotintable;
  output [2:0]\gt_rx_status_q_reg[2] ;
  input gt_cpllpdrefclk;
  input CLK;
  input \fsm_reg[2] ;
  input \fsm_reg[0] ;
  input USER_EYESCANRESET;
  input sys_clk;
  input DRP_GTXRESET;
  input [0:0]pci_exp_rxn;
  input [0:0]pci_exp_rxp;
  input qpllpd_reg;
  input qpllpd_reg_0;
  input \resetovrd_disble.fsm_reg[1] ;
  input gen3_reg;
  input USER_RXBUFRESET;
  input USER_RXCDRFREQRESET;
  input USER_RXCDRRESET;
  input O1671;
  input converge_gen3_reg;
  input USER_RXDFELPMRESET;
  input SYNC_RXSYNC_DONE;
  input \rxsync_fsm_disable.fsm_rx_reg[2] ;
  input USER_RXPCSRESET;
  input \rxsync_fsm_disable.fsm_rx_reg[2]_0 ;
  input GT_RXPMARESET0;
  input [0:0]PIPE_RXPOLARITY;
  input userrdy_reg_rep__5;
  input pclk_sel_reg;
  input [0:0]PIPE_TXDEEMPH;
  input \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ;
  input \txsync_fsm.txdlyen_reg ;
  input \txsync_fsm.fsm_tx_reg[2] ;
  input [0:0]PIPE_TXELECIDLE;
  input [0:0]pipe_txinhibit;
  input \txsync_fsm.fsm_tx_reg[4] ;
  input \txsync_fsm.fsm_tx_reg[4]_0 ;
  input GT_TXPMARESET0;
  input [15:0]DRPDI;
  input [1:0]PIPE_POWERDOWN;
  input [1:0]RXSYSCLKSEL;
  input [2:0]RXRATE;
  input [2:0]TXMARGIN;
  input USER_OOBCLK;
  input [4:0]TXPOSTCURSOR;
  input [4:0]TXPRECURSOR;
  input [15:0]PIPE_TXDATA;
  input [6:0]TXMAINCURSOR;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [1:0]PIPE_TXDATAK;
  input [8:0]DRPADDR;
  input [1:0]Q;
  input \pl_ltssm_state_q_reg[4] ;
  input gt_rxvalid_q_reg;
  input rst_cpllpd;
  input p_0_in3_in;
  input RST_CPLLRESET;
  input p_0_in2_in;

  wire CLK;
  wire CPLLPD0;
  wire CPLLRESET0;
  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_GTXRESET;
  wire GT_RXPMARESET0;
  wire GT_TXPMARESET0;
  wire O1671;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [15:0]PIPE_RXDATA;
  wire [1:0]PIPE_RXDATAK;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXDEEMPH;
  wire [0:0]PIPE_TXELECIDLE;
  wire [1:0]Q;
  wire RATE_CPLLLOCK;
  wire RATE_PHYSTATUS;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RST_CPLLRESET;
  wire [4:0]RXCHBONDO;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXPHALIGNDONE_M;
  wire SYNC_RXSYNC_DONE;
  wire [6:0]TXMAINCURSOR;
  wire [2:0]TXMARGIN;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_EYESCANRESET;
  wire USER_OOBCLK;
  wire USER_RXBUFRESET;
  wire USER_RXCDRFREQRESET;
  wire USER_RXCDRRESET;
  wire USER_RXDFELPMRESET;
  wire USER_RXPCSRESET;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire converge_gen3_reg;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drprdy;
  wire \fsm_reg[0] ;
  wire \fsm_reg[2] ;
  wire gen3_reg;
  wire gt_cpllpdrefclk;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire gt_rxvalid_q_reg;
  wire \gtx_channel.gtxe2_channel_i_n_10 ;
  wire \gtx_channel.gtxe2_channel_i_n_138 ;
  wire \gtx_channel.gtxe2_channel_i_n_139 ;
  wire \gtx_channel.gtxe2_channel_i_n_140 ;
  wire \gtx_channel.gtxe2_channel_i_n_141 ;
  wire \gtx_channel.gtxe2_channel_i_n_142 ;
  wire \gtx_channel.gtxe2_channel_i_n_143 ;
  wire \gtx_channel.gtxe2_channel_i_n_144 ;
  wire \gtx_channel.gtxe2_channel_i_n_145 ;
  wire \gtx_channel.gtxe2_channel_i_n_146 ;
  wire \gtx_channel.gtxe2_channel_i_n_147 ;
  wire \gtx_channel.gtxe2_channel_i_n_148 ;
  wire \gtx_channel.gtxe2_channel_i_n_149 ;
  wire \gtx_channel.gtxe2_channel_i_n_150 ;
  wire \gtx_channel.gtxe2_channel_i_n_151 ;
  wire \gtx_channel.gtxe2_channel_i_n_152 ;
  wire \gtx_channel.gtxe2_channel_i_n_153 ;
  wire \gtx_channel.gtxe2_channel_i_n_189 ;
  wire \gtx_channel.gtxe2_channel_i_n_190 ;
  wire \gtx_channel.gtxe2_channel_i_n_191 ;
  wire \gtx_channel.gtxe2_channel_i_n_192 ;
  wire \gtx_channel.gtxe2_channel_i_n_197 ;
  wire \gtx_channel.gtxe2_channel_i_n_198 ;
  wire \gtx_channel.gtxe2_channel_i_n_9 ;
  wire p_0_in2_in;
  wire p_0_in3_in;
  wire [0:0]pci_exp_rxn;
  wire [0:0]pci_exp_rxp;
  wire [0:0]pci_exp_txn;
  wire [0:0]pci_exp_txp;
  wire pclk_sel_reg;
  wire [7:0]pipe_dmonitorout;
  wire [0:0]pipe_eyescandataerror;
  wire [2:0]pipe_rxbufstatus;
  wire [0:0]pipe_rxcommadet;
  wire [7:0]pipe_rxdisperr;
  wire [0:0]pipe_rxdlysresetdone;
  wire [7:0]pipe_rxnotintable;
  wire [0:0]pipe_rxoutclk_out;
  wire [0:0]pipe_rxprbserr;
  wire [2:0]pipe_rxstatus;
  wire \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ;
  wire [0:0]pipe_txdlysresetdone;
  wire [0:0]pipe_txinhibit;
  wire pipe_txoutclk_out;
  wire [0:0]pipe_txphaligndone;
  wire [0:0]pipe_txphinitdone;
  wire \pl_ltssm_state_q_reg[4] ;
  wire qpllpd_reg;
  wire qpllpd_reg_0;
  wire \resetovrd_disble.fsm_reg[1] ;
  wire rst_cpllpd;
  wire rxcdrlock_reg1_reg;
  wire \rxsync_fsm_disable.fsm_rx_reg[2] ;
  wire \rxsync_fsm_disable.fsm_rx_reg[2]_0 ;
  wire rxvalid_reg1_reg;
  wire sys_clk;
  wire \txsync_fsm.fsm_tx_reg[2] ;
  wire \txsync_fsm.fsm_tx_reg[4] ;
  wire \txsync_fsm.fsm_tx_reg[4]_0 ;
  wire \txsync_fsm.txdlyen_reg ;
  wire userrdy_reg_rep__5;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
  wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
  wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
  wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
  wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
  wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;

  PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_87 cpllPDInst
       (.CPLLPD0(CPLLPD0),
        .CPLLRESET0(CPLLRESET0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .p_0_in2_in(p_0_in2_in),
        .p_0_in3_in(p_0_in3_in),
        .rst_cpllpd(rst_cpllpd));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[0]_i_1__6 
       (.I0(pipe_rxstatus[0]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [0]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[1]_i_1__6 
       (.I0(pipe_rxstatus[1]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [1]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[2]_i_1__6 
       (.I0(pipe_rxstatus[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [2]));
  (* box_type = "PRIMITIVE" *) 
  GTXE2_CHANNEL #(
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(1),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CHAN_BOND_KEEP_ALIGN("TRUE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0001001010),
    .CHAN_BOND_SEQ_1_2(10'b0001001010),
    .CHAN_BOND_SEQ_1_3(10'b0001001010),
    .CHAN_BOND_SEQ_1_4(10'b0110111100),
    .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_1(10'b0001000101),
    .CHAN_BOND_SEQ_2_2(10'b0001000101),
    .CHAN_BOND_SEQ_2_3(10'b0001000101),
    .CHAN_BOND_SEQ_2_4(10'b0110111100),
    .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_USE("TRUE"),
    .CHAN_BOND_SEQ_LEN(4),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("TRUE"),
    .CLK_COR_MAX_LAT(20),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0100011100),
    .CLK_COR_SEQ_1_2(10'b0000000000),
    .CLK_COR_SEQ_1_3(10'b0000000000),
    .CLK_COR_SEQ_1_4(10'b0000000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0000000000),
    .CLK_COR_SEQ_2_2(10'b0000000000),
    .CLK_COR_SEQ_2_3(10'b0000000000),
    .CLK_COR_SEQ_2_4(10'b0000000000),
    .CLK_COR_SEQ_2_ENABLE(4'b0000),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(1),
    .CPLL_CFG(24'hA407CC),
    .CPLL_FBDIV(5),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000B01),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("FALSE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("TRUE"),
    .GEARBOX_MODE(3'b000),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("TRUE"),
    .PCS_RSVD_ATTR(48'h0000000001CF),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h09),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'h00018480),
    .PMA_RSV2(16'h2050),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(32'h00000000),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b0100),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("TRUE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(72'h03000023FF10200020),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b1),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00000011110000),
    .RXLPM_LF_CFG(14'b00000011110000),
    .RXOOB_CFG(7'b0000110),
    .RXOUT_DIV(2),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h004020),
    .RXPH_CFG(24'h000000),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("PMA"),
    .RX_BIAS_CFG(12'b000000000100),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(4),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(3'b010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(12'b000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFE_GAIN_CFG(23'h020FEA),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011110000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_KL_CFG(13'b0000011111110),
    .RX_DFE_KL_CFG2(32'h3290D86C),
    .RX_DFE_LPM_CFG(16'h0954),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
    .RX_DFE_UT_CFG(17'b10001111000000000),
    .RX_DFE_VP_CFG(17'b00011111100000011),
    .RX_DFE_XYD_CFG(13'b0000000000000),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(4),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b1111),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("FALSE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
    .SIM_VERSION("3.0"),
    .TERM_RCAL_CFG(5'b10000),
    .TERM_RCAL_OVRD(1'b0),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("FALSE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOUT_DIV(2),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPMARESET_TIME(5'b00011),
    .TX_CLK25_DIV(4),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(5'b10100),
    .TX_DEEMPH1(5'b01011),
    .TX_DRIVE_MODE("PIPE"),
    .TX_EIDLE_ASSERT_DELAY(3'b010),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001111),
    .TX_MARGIN_FULL_1(7'b1001110),
    .TX_MARGIN_FULL_2(7'b1001101),
    .TX_MARGIN_FULL_3(7'b1001100),
    .TX_MARGIN_FULL_4(7'b1000011),
    .TX_MARGIN_LOW_0(7'b1000101),
    .TX_MARGIN_LOW_1(7'b1000110),
    .TX_MARGIN_LOW_2(7'b1000011),
    .TX_MARGIN_LOW_3(7'b1000010),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_PREDRIVER_MODE(1'b0),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h0064),
    .TX_RXDETECT_REF(3'b011),
    .TX_XCLK_SEL("TXUSR"),
    .UCODEER_CLR(1'b0)) 
    \gtx_channel.gtxe2_channel_i 
       (.CFGRESET(1'b0),
        .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
        .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
        .CPLLLOCK(RATE_CPLLLOCK),
        .CPLLLOCKDETCLK(1'b0),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD0),
        .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET0),
        .DMONITOROUT(pipe_dmonitorout),
        .DRPADDR(DRPADDR),
        .DRPCLK(CLK),
        .DRPDI(DRPDI),
        .DRPDO(ext_ch_gt_drpdo),
        .DRPEN(\fsm_reg[2] ),
        .DRPRDY(ext_ch_gt_drprdy),
        .DRPWE(\fsm_reg[0] ),
        .EYESCANDATAERROR(pipe_eyescandataerror),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(USER_EYESCANRESET),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(DRP_GTXRESET),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(DRP_GTXRESET),
        .GTXRXN(pci_exp_rxn),
        .GTXRXP(pci_exp_rxp),
        .GTXTXN(pci_exp_txn),
        .GTXTXP(pci_exp_txp),
        .LOOPBACK({1'b0,1'b0,1'b0}),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
        .PHYSTATUS(RATE_PHYSTATUS),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(qpllpd_reg),
        .QPLLREFCLK(qpllpd_reg_0),
        .RESETOVRD(\resetovrd_disble.fsm_reg[1] ),
        .RX8B10BEN(gen3_reg),
        .RXBUFRESET(USER_RXBUFRESET),
        .RXBUFSTATUS(pipe_rxbufstatus),
        .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
        .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
        .RXCDRFREQRESET(USER_RXCDRFREQRESET),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(rxcdrlock_reg1_reg),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(USER_RXCDRRESET),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
        .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
        .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
        .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
        .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,PIPE_RXDATAK}),
        .RXCHBONDEN(gen3_reg),
        .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b1}),
        .RXCHBONDMASTER(O1671),
        .RXCHBONDO(RXCHBONDO),
        .RXCHBONDSLAVE(1'b0),
        .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
        .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
        .RXCOMMADET(pipe_rxcommadet),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
        .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
        .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,PIPE_RXDATA}),
        .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(converge_gen3_reg),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b1),
        .RXDFELPMRESET(USER_RXDFELPMRESET),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b0),
        .RXDFEXYDHOLD(1'b0),
        .RXDFEXYDOVRDEN(1'b0),
        .RXDISPERR(pipe_rxdisperr),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(SYNC_RXSYNC_DONE),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(\rxsync_fsm_disable.fsm_rx_reg[2] ),
        .RXDLYSRESETDONE(pipe_rxdlysresetdone),
        .RXELECIDLE(gt_rx_elec_idle_wire_filter),
        .RXELECIDLEMODE({1'b0,1'b0}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
        .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
        .RXLPMEN(O1671),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(gen3_reg),
        .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE(pipe_rxnotintable),
        .RXOOBRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(pipe_rxoutclk_out),
        .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
        .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
        .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .RXPCOMMAALIGNEN(O1671),
        .RXPCSRESET(USER_RXPCSRESET),
        .RXPD(PIPE_POWERDOWN),
        .RXPHALIGN(\rxsync_fsm_disable.fsm_rx_reg[2]_0 ),
        .RXPHALIGNDONE(SYNC_RXPHALIGNDONE_M),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
        .RXPMARESET(GT_RXPMARESET0),
        .RXPOLARITY(PIPE_RXPOLARITY),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(pipe_rxprbserr),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
        .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
        .RXRATE(RXRATE),
        .RXRATEDONE(RATE_RXRATEDONE),
        .RXRESETDONE(USER_RXRESETDONE),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
        .RXSTATUS(pipe_rxstatus),
        .RXSYSCLKSEL(RXSYSCLKSEL),
        .RXUSERRDY(userrdy_reg_rep__5),
        .RXUSRCLK(pclk_sel_reg),
        .RXUSRCLK2(pclk_sel_reg),
        .RXVALID(rxvalid_reg1_reg),
        .SETERRSTATUS(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(O1671),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
        .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
        .TXDEEMPH(PIPE_TXDEEMPH),
        .TXDETECTRX(\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ),
        .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b0),
        .TXDLYEN(\txsync_fsm.txdlyen_reg ),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(\txsync_fsm.fsm_tx_reg[2] ),
        .TXDLYSRESETDONE(pipe_txdlysresetdone),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(PIPE_TXELECIDLE),
        .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(pipe_txinhibit),
        .TXMAINCURSOR(TXMAINCURSOR),
        .TXMARGIN(TXMARGIN),
        .TXOUTCLK(pipe_txoutclk_out),
        .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
        .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
        .TXOUTCLKSEL({1'b0,1'b1,1'b1}),
        .TXPCSRESET(1'b0),
        .TXPD(PIPE_POWERDOWN),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(\txsync_fsm.fsm_tx_reg[4] ),
        .TXPHALIGNDONE(pipe_txphaligndone),
        .TXPHALIGNEN(1'b1),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(\txsync_fsm.fsm_tx_reg[4]_0 ),
        .TXPHINITDONE(pipe_txphinitdone),
        .TXPHOVRDEN(1'b0),
        .TXPISOPD(1'b0),
        .TXPMARESET(GT_TXPMARESET0),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR(TXPOSTCURSOR),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR(TXPRECURSOR),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
        .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE(RXRATE),
        .TXRATEDONE(RATE_TXRATEDONE),
        .TXRESETDONE(USER_TXRESETDONE),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYSCLKSEL(RXSYSCLKSEL),
        .TXUSERRDY(userrdy_reg_rep__5),
        .TXUSRCLK(pclk_sel_reg),
        .TXUSRCLK2(pclk_sel_reg));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_29
   (RATE_CPLLLOCK,
    ext_ch_gt_drprdy,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    RATE_PHYSTATUS,
    rxcdrlock_reg1_reg,
    PIPE_RXCHANISALIGNED,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    gt_rx_elec_idle_wire_filter,
    pipe_rxoutclk_out,
    pipe_rxphaligndone,
    pipe_rxprbserr,
    RATE_RXRATEDONE,
    USER_RXRESETDONE,
    rxvalid_reg1_reg,
    pipe_txdlysresetdone,
    pipe_txphaligndone,
    pipe_txphinitdone,
    RATE_TXRATEDONE,
    USER_TXRESETDONE,
    ext_ch_gt_drpdo,
    pipe_rxbufstatus,
    pipe_rxstatus,
    \gt_rxdata_q_reg[15] ,
    pipe_dmonitorout,
    \gt_rxcharisk_q_reg[1] ,
    pipe_rxdisperr,
    pipe_rxnotintable,
    \gt_rx_status_q_reg[2] ,
    gt_cpllpdrefclk,
    \resetovrd_disble.reset_reg[4] ,
    \fsm_reg[2] ,
    \fsm_reg[0] ,
    USER_EYESCANRESET,
    sys_clk,
    rst_gtreset,
    pci_exp_rxn,
    pci_exp_rxp,
    qpllpd_reg,
    qpllpd_reg_0,
    \resetovrd_disble.fsm_reg[1] ,
    gen3_reg,
    USER_RXBUFRESET,
    USER_RXCDRFREQRESET,
    USER_RXCDRRESET,
    gen3_reg_0,
    converge_gen3_reg,
    USER_RXDFELPMRESET,
    SYNC_RXSYNC_DONE,
    \rxsync_fsm_disable.fsm_rx_reg[2] ,
    USER_RXPCSRESET,
    rxsync_donem_reg2_reg,
    GT_RXPMARESET089_out,
    PIPE_RXPOLARITY,
    userrdy_reg_rep__4,
    pclk_sel_reg,
    PIPE_TXDEEMPH,
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ,
    \txsync_fsm.txdlyen_reg ,
    \txsync_fsm.fsm_tx_reg[2] ,
    PIPE_TXELECIDLE,
    pipe_txinhibit,
    \txsync_fsm.fsm_tx_reg[4] ,
    \txsync_fsm.fsm_tx_reg[4]_0 ,
    GT_TXPMARESET092_out,
    DRPDI,
    PIPE_POWERDOWN,
    RXSYSCLKSEL,
    RXRATE,
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ,
    USER_OOBCLK,
    RXCHBONDO,
    TXPOSTCURSOR,
    TXPRECURSOR,
    PIPE_TXDATA,
    TXMAINCURSOR,
    PIPE_TXCOMPLIANCE,
    PIPE_TXDATAK,
    DRPADDR,
    Q,
    \pl_ltssm_state_q_reg[4] ,
    gt_rxvalid_q_reg,
    rst_cpllpd,
    p_0_in95_in,
    RST_CPLLRESET,
    p_0_in93_in);
  output RATE_CPLLLOCK;
  output [0:0]ext_ch_gt_drprdy;
  output [0:0]pipe_eyescandataerror;
  output [0:0]pci_exp_txn;
  output [0:0]pci_exp_txp;
  output RATE_PHYSTATUS;
  output rxcdrlock_reg1_reg;
  output [0:0]PIPE_RXCHANISALIGNED;
  output [0:0]pipe_rxcommadet;
  output [0:0]pipe_rxdlysresetdone;
  output [0:0]gt_rx_elec_idle_wire_filter;
  output [0:0]pipe_rxoutclk_out;
  output [0:0]pipe_rxphaligndone;
  output [0:0]pipe_rxprbserr;
  output RATE_RXRATEDONE;
  output USER_RXRESETDONE;
  output rxvalid_reg1_reg;
  output [0:0]pipe_txdlysresetdone;
  output [0:0]pipe_txphaligndone;
  output [0:0]pipe_txphinitdone;
  output RATE_TXRATEDONE;
  output USER_TXRESETDONE;
  output [15:0]ext_ch_gt_drpdo;
  output [2:0]pipe_rxbufstatus;
  output [2:0]pipe_rxstatus;
  output [15:0]\gt_rxdata_q_reg[15] ;
  output [7:0]pipe_dmonitorout;
  output [1:0]\gt_rxcharisk_q_reg[1] ;
  output [7:0]pipe_rxdisperr;
  output [7:0]pipe_rxnotintable;
  output [2:0]\gt_rx_status_q_reg[2] ;
  input gt_cpllpdrefclk;
  input \resetovrd_disble.reset_reg[4] ;
  input \fsm_reg[2] ;
  input \fsm_reg[0] ;
  input USER_EYESCANRESET;
  input sys_clk;
  input rst_gtreset;
  input [0:0]pci_exp_rxn;
  input [0:0]pci_exp_rxp;
  input qpllpd_reg;
  input qpllpd_reg_0;
  input \resetovrd_disble.fsm_reg[1] ;
  input gen3_reg;
  input USER_RXBUFRESET;
  input USER_RXCDRFREQRESET;
  input USER_RXCDRRESET;
  input gen3_reg_0;
  input converge_gen3_reg;
  input USER_RXDFELPMRESET;
  input SYNC_RXSYNC_DONE;
  input \rxsync_fsm_disable.fsm_rx_reg[2] ;
  input USER_RXPCSRESET;
  input rxsync_donem_reg2_reg;
  input GT_RXPMARESET089_out;
  input [0:0]PIPE_RXPOLARITY;
  input userrdy_reg_rep__4;
  input pclk_sel_reg;
  input [0:0]PIPE_TXDEEMPH;
  input \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ;
  input \txsync_fsm.txdlyen_reg ;
  input \txsync_fsm.fsm_tx_reg[2] ;
  input [0:0]PIPE_TXELECIDLE;
  input [0:0]pipe_txinhibit;
  input \txsync_fsm.fsm_tx_reg[4] ;
  input \txsync_fsm.fsm_tx_reg[4]_0 ;
  input GT_TXPMARESET092_out;
  input [15:0]DRPDI;
  input [1:0]PIPE_POWERDOWN;
  input [1:0]RXSYSCLKSEL;
  input [2:0]RXRATE;
  input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ;
  input USER_OOBCLK;
  input [4:0]RXCHBONDO;
  input [4:0]TXPOSTCURSOR;
  input [4:0]TXPRECURSOR;
  input [15:0]PIPE_TXDATA;
  input [6:0]TXMAINCURSOR;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [1:0]PIPE_TXDATAK;
  input [8:0]DRPADDR;
  input [1:0]Q;
  input \pl_ltssm_state_q_reg[4] ;
  input gt_rxvalid_q_reg;
  input rst_cpllpd;
  input p_0_in95_in;
  input RST_CPLLRESET;
  input p_0_in93_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire GT_RXPMARESET089_out;
  wire GT_TXPMARESET092_out;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXDEEMPH;
  wire [0:0]PIPE_TXELECIDLE;
  wire [1:0]Q;
  wire RATE_CPLLLOCK;
  wire RATE_PHYSTATUS;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RST_CPLLRESET;
  wire [4:0]RXCHBONDO;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_EYESCANRESET;
  wire USER_OOBCLK;
  wire USER_RXBUFRESET;
  wire USER_RXCDRFREQRESET;
  wire USER_RXCDRRESET;
  wire USER_RXDFELPMRESET;
  wire USER_RXPCSRESET;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire converge_gen3_reg;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drprdy;
  wire \fsm_reg[0] ;
  wire \fsm_reg[2] ;
  wire gen3_reg;
  wire gen3_reg_0;
  wire gt_cpllpdrefclk;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxvalid_q_reg;
  wire \gtx_channel.gtxe2_channel_i_n_10 ;
  wire \gtx_channel.gtxe2_channel_i_n_138 ;
  wire \gtx_channel.gtxe2_channel_i_n_139 ;
  wire \gtx_channel.gtxe2_channel_i_n_140 ;
  wire \gtx_channel.gtxe2_channel_i_n_141 ;
  wire \gtx_channel.gtxe2_channel_i_n_142 ;
  wire \gtx_channel.gtxe2_channel_i_n_143 ;
  wire \gtx_channel.gtxe2_channel_i_n_144 ;
  wire \gtx_channel.gtxe2_channel_i_n_145 ;
  wire \gtx_channel.gtxe2_channel_i_n_146 ;
  wire \gtx_channel.gtxe2_channel_i_n_147 ;
  wire \gtx_channel.gtxe2_channel_i_n_148 ;
  wire \gtx_channel.gtxe2_channel_i_n_149 ;
  wire \gtx_channel.gtxe2_channel_i_n_150 ;
  wire \gtx_channel.gtxe2_channel_i_n_151 ;
  wire \gtx_channel.gtxe2_channel_i_n_152 ;
  wire \gtx_channel.gtxe2_channel_i_n_153 ;
  wire \gtx_channel.gtxe2_channel_i_n_189 ;
  wire \gtx_channel.gtxe2_channel_i_n_190 ;
  wire \gtx_channel.gtxe2_channel_i_n_191 ;
  wire \gtx_channel.gtxe2_channel_i_n_192 ;
  wire \gtx_channel.gtxe2_channel_i_n_197 ;
  wire \gtx_channel.gtxe2_channel_i_n_198 ;
  wire \gtx_channel.gtxe2_channel_i_n_37 ;
  wire \gtx_channel.gtxe2_channel_i_n_9 ;
  wire \gtx_channel.gtxe2_channel_i_n_91 ;
  wire \gtx_channel.gtxe2_channel_i_n_92 ;
  wire \gtx_channel.gtxe2_channel_i_n_93 ;
  wire \gtx_channel.gtxe2_channel_i_n_94 ;
  wire \gtx_channel.gtxe2_channel_i_n_95 ;
  wire p_0_in93_in;
  wire p_0_in95_in;
  wire [0:0]pci_exp_rxn;
  wire [0:0]pci_exp_rxp;
  wire [0:0]pci_exp_txn;
  wire [0:0]pci_exp_txp;
  wire pclk_sel_reg;
  wire [7:0]pipe_dmonitorout;
  wire [0:0]pipe_eyescandataerror;
  wire [2:0]pipe_rxbufstatus;
  wire [0:0]pipe_rxcommadet;
  wire [7:0]pipe_rxdisperr;
  wire [0:0]pipe_rxdlysresetdone;
  wire [7:0]pipe_rxnotintable;
  wire [0:0]pipe_rxoutclk_out;
  wire [0:0]pipe_rxphaligndone;
  wire [0:0]pipe_rxprbserr;
  wire [2:0]pipe_rxstatus;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ;
  wire \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ;
  wire [0:0]pipe_txdlysresetdone;
  wire [0:0]pipe_txinhibit;
  wire [0:0]pipe_txphaligndone;
  wire [0:0]pipe_txphinitdone;
  wire \pl_ltssm_state_q_reg[4] ;
  wire qpllpd_reg;
  wire qpllpd_reg_0;
  wire \resetovrd_disble.fsm_reg[1] ;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_cpllpd;
  wire rst_gtreset;
  wire rxcdrlock_reg1_reg;
  wire rxsync_donem_reg2_reg;
  wire \rxsync_fsm_disable.fsm_rx_reg[2] ;
  wire rxvalid_reg1_reg;
  wire sys_clk;
  wire \txsync_fsm.fsm_tx_reg[2] ;
  wire \txsync_fsm.fsm_tx_reg[4] ;
  wire \txsync_fsm.fsm_tx_reg[4]_0 ;
  wire \txsync_fsm.txdlyen_reg ;
  wire userrdy_reg_rep__4;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
  wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
  wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
  wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
  wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
  wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;

  PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_83 cpllPDInst
       (.CPLLPD0(CPLLPD0),
        .CPLLRESET0(CPLLRESET0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .p_0_in93_in(p_0_in93_in),
        .p_0_in95_in(p_0_in95_in),
        .rst_cpllpd(rst_cpllpd));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[0]_i_1__5 
       (.I0(pipe_rxstatus[0]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [0]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[1]_i_1__5 
       (.I0(pipe_rxstatus[1]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [1]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[2]_i_1__5 
       (.I0(pipe_rxstatus[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [2]));
  (* box_type = "PRIMITIVE" *) 
  GTXE2_CHANNEL #(
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(1),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CHAN_BOND_KEEP_ALIGN("TRUE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0001001010),
    .CHAN_BOND_SEQ_1_2(10'b0001001010),
    .CHAN_BOND_SEQ_1_3(10'b0001001010),
    .CHAN_BOND_SEQ_1_4(10'b0110111100),
    .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_1(10'b0001000101),
    .CHAN_BOND_SEQ_2_2(10'b0001000101),
    .CHAN_BOND_SEQ_2_3(10'b0001000101),
    .CHAN_BOND_SEQ_2_4(10'b0110111100),
    .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_USE("TRUE"),
    .CHAN_BOND_SEQ_LEN(4),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("TRUE"),
    .CLK_COR_MAX_LAT(20),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0100011100),
    .CLK_COR_SEQ_1_2(10'b0000000000),
    .CLK_COR_SEQ_1_3(10'b0000000000),
    .CLK_COR_SEQ_1_4(10'b0000000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0000000000),
    .CLK_COR_SEQ_2_2(10'b0000000000),
    .CLK_COR_SEQ_2_3(10'b0000000000),
    .CLK_COR_SEQ_2_4(10'b0000000000),
    .CLK_COR_SEQ_2_ENABLE(4'b0000),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(1),
    .CPLL_CFG(24'hA407CC),
    .CPLL_FBDIV(5),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000B01),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("FALSE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("TRUE"),
    .GEARBOX_MODE(3'b000),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("TRUE"),
    .PCS_RSVD_ATTR(48'h0000000001CF),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h09),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'h00018480),
    .PMA_RSV2(16'h2050),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(32'h00000000),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b0100),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("TRUE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(72'h03000023FF10200020),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b1),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00000011110000),
    .RXLPM_LF_CFG(14'b00000011110000),
    .RXOOB_CFG(7'b0000110),
    .RXOUT_DIV(2),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h004020),
    .RXPH_CFG(24'h000000),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("PMA"),
    .RX_BIAS_CFG(12'b000000000100),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(4),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(3'b010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(12'b000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFE_GAIN_CFG(23'h020FEA),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011110000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_KL_CFG(13'b0000011111110),
    .RX_DFE_KL_CFG2(32'h3290D86C),
    .RX_DFE_LPM_CFG(16'h0954),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
    .RX_DFE_UT_CFG(17'b10001111000000000),
    .RX_DFE_VP_CFG(17'b00011111100000011),
    .RX_DFE_XYD_CFG(13'b0000000000000),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(4),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b1111),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("FALSE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
    .SIM_VERSION("3.0"),
    .TERM_RCAL_CFG(5'b10000),
    .TERM_RCAL_OVRD(1'b0),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("FALSE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOUT_DIV(2),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPMARESET_TIME(5'b00011),
    .TX_CLK25_DIV(4),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(5'b10100),
    .TX_DEEMPH1(5'b01011),
    .TX_DRIVE_MODE("PIPE"),
    .TX_EIDLE_ASSERT_DELAY(3'b010),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001111),
    .TX_MARGIN_FULL_1(7'b1001110),
    .TX_MARGIN_FULL_2(7'b1001101),
    .TX_MARGIN_FULL_3(7'b1001100),
    .TX_MARGIN_FULL_4(7'b1000011),
    .TX_MARGIN_LOW_0(7'b1000101),
    .TX_MARGIN_LOW_1(7'b1000110),
    .TX_MARGIN_LOW_2(7'b1000011),
    .TX_MARGIN_LOW_3(7'b1000010),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_PREDRIVER_MODE(1'b0),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h0064),
    .TX_RXDETECT_REF(3'b011),
    .TX_XCLK_SEL("TXUSR"),
    .UCODEER_CLR(1'b0)) 
    \gtx_channel.gtxe2_channel_i 
       (.CFGRESET(1'b0),
        .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
        .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
        .CPLLLOCK(RATE_CPLLLOCK),
        .CPLLLOCKDETCLK(1'b0),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD0),
        .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET0),
        .DMONITOROUT(pipe_dmonitorout),
        .DRPADDR(DRPADDR),
        .DRPCLK(\resetovrd_disble.reset_reg[4] ),
        .DRPDI(DRPDI),
        .DRPDO(ext_ch_gt_drpdo),
        .DRPEN(\fsm_reg[2] ),
        .DRPRDY(ext_ch_gt_drprdy),
        .DRPWE(\fsm_reg[0] ),
        .EYESCANDATAERROR(pipe_eyescandataerror),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(USER_EYESCANRESET),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(rst_gtreset),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(rst_gtreset),
        .GTXRXN(pci_exp_rxn),
        .GTXRXP(pci_exp_rxp),
        .GTXTXN(pci_exp_txn),
        .GTXTXP(pci_exp_txp),
        .LOOPBACK({1'b0,1'b0,1'b0}),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
        .PHYSTATUS(RATE_PHYSTATUS),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(qpllpd_reg),
        .QPLLREFCLK(qpllpd_reg_0),
        .RESETOVRD(\resetovrd_disble.fsm_reg[1] ),
        .RX8B10BEN(gen3_reg),
        .RXBUFRESET(USER_RXBUFRESET),
        .RXBUFSTATUS(pipe_rxbufstatus),
        .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
        .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
        .RXCDRFREQRESET(USER_RXCDRFREQRESET),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(rxcdrlock_reg1_reg),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(USER_RXCDRRESET),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
        .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
        .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
        .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
        .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,\gt_rxcharisk_q_reg[1] }),
        .RXCHBONDEN(gen3_reg),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }),
        .RXCHBONDSLAVE(gen3_reg_0),
        .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
        .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
        .RXCOMMADET(pipe_rxcommadet),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
        .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
        .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,\gt_rxdata_q_reg[15] }),
        .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(converge_gen3_reg),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b1),
        .RXDFELPMRESET(USER_RXDFELPMRESET),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b0),
        .RXDFEXYDHOLD(1'b0),
        .RXDFEXYDOVRDEN(1'b0),
        .RXDISPERR(pipe_rxdisperr),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(SYNC_RXSYNC_DONE),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(\rxsync_fsm_disable.fsm_rx_reg[2] ),
        .RXDLYSRESETDONE(pipe_rxdlysresetdone),
        .RXELECIDLE(gt_rx_elec_idle_wire_filter),
        .RXELECIDLEMODE({1'b0,1'b0}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
        .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
        .RXLPMEN(gen3_reg_0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(gen3_reg),
        .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE(pipe_rxnotintable),
        .RXOOBRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(pipe_rxoutclk_out),
        .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
        .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
        .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .RXPCOMMAALIGNEN(gen3_reg_0),
        .RXPCSRESET(USER_RXPCSRESET),
        .RXPD(PIPE_POWERDOWN),
        .RXPHALIGN(rxsync_donem_reg2_reg),
        .RXPHALIGNDONE(pipe_rxphaligndone),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
        .RXPMARESET(GT_RXPMARESET089_out),
        .RXPOLARITY(PIPE_RXPOLARITY),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(pipe_rxprbserr),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
        .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
        .RXRATE(RXRATE),
        .RXRATEDONE(RATE_RXRATEDONE),
        .RXRESETDONE(USER_RXRESETDONE),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
        .RXSTATUS(pipe_rxstatus),
        .RXSYSCLKSEL(RXSYSCLKSEL),
        .RXUSERRDY(userrdy_reg_rep__4),
        .RXUSRCLK(pclk_sel_reg),
        .RXUSRCLK2(pclk_sel_reg),
        .RXVALID(rxvalid_reg1_reg),
        .SETERRSTATUS(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(gen3_reg_0),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
        .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
        .TXDEEMPH(PIPE_TXDEEMPH),
        .TXDETECTRX(\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ),
        .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b0),
        .TXDLYEN(\txsync_fsm.txdlyen_reg ),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(\txsync_fsm.fsm_tx_reg[2] ),
        .TXDLYSRESETDONE(pipe_txdlysresetdone),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(PIPE_TXELECIDLE),
        .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(pipe_txinhibit),
        .TXMAINCURSOR(TXMAINCURSOR),
        .TXMARGIN(\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ),
        .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ),
        .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
        .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
        .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD(PIPE_POWERDOWN),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(\txsync_fsm.fsm_tx_reg[4] ),
        .TXPHALIGNDONE(pipe_txphaligndone),
        .TXPHALIGNEN(1'b1),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(\txsync_fsm.fsm_tx_reg[4]_0 ),
        .TXPHINITDONE(pipe_txphinitdone),
        .TXPHOVRDEN(1'b0),
        .TXPISOPD(1'b0),
        .TXPMARESET(GT_TXPMARESET092_out),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR(TXPOSTCURSOR),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR(TXPRECURSOR),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
        .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE(RXRATE),
        .TXRATEDONE(RATE_TXRATEDONE),
        .TXRESETDONE(USER_TXRESETDONE),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYSCLKSEL(RXSYSCLKSEL),
        .TXUSERRDY(userrdy_reg_rep__4),
        .TXUSRCLK(pclk_sel_reg),
        .TXUSRCLK2(pclk_sel_reg));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_35
   (RATE_CPLLLOCK,
    ext_ch_gt_drprdy,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    RATE_PHYSTATUS,
    rxcdrlock_reg1_reg,
    PIPE_RXCHANISALIGNED,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    gt_rx_elec_idle_wire_filter,
    pipe_rxoutclk_out,
    pipe_rxphaligndone,
    pipe_rxprbserr,
    RATE_RXRATEDONE,
    USER_RXRESETDONE,
    rxvalid_reg1_reg,
    pipe_txdlysresetdone,
    pipe_txphaligndone,
    pipe_txphinitdone,
    RATE_TXRATEDONE,
    USER_TXRESETDONE,
    ext_ch_gt_drpdo,
    pipe_rxbufstatus,
    pipe_rxstatus,
    \gt_rxdata_q_reg[15] ,
    pipe_dmonitorout,
    \gt_rxcharisk_q_reg[1] ,
    pipe_rxdisperr,
    pipe_rxnotintable,
    \gt_rx_status_q_reg[2] ,
    gt_cpllpdrefclk,
    \resetovrd_disble.reset_reg[4] ,
    \fsm_reg[2] ,
    \fsm_reg[0] ,
    USER_EYESCANRESET,
    sys_clk,
    rst_gtreset,
    pci_exp_rxn,
    pci_exp_rxp,
    qpllpd_reg,
    qpllpd_reg_0,
    \resetovrd_disble.fsm_reg[1] ,
    gen3_reg,
    USER_RXBUFRESET,
    USER_RXCDRFREQRESET,
    USER_RXCDRRESET,
    gen3_reg_0,
    converge_gen3_reg,
    USER_RXDFELPMRESET,
    SYNC_RXSYNC_DONE,
    \rxsync_fsm_disable.fsm_rx_reg[2] ,
    USER_RXPCSRESET,
    rxsync_donem_reg2_reg,
    GT_RXPMARESET0117_out,
    PIPE_RXPOLARITY,
    userrdy_reg_rep__3,
    pclk_sel_reg,
    PIPE_TXDEEMPH,
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ,
    \txsync_fsm.txdlyen_reg ,
    \txsync_fsm.fsm_tx_reg[2] ,
    PIPE_TXELECIDLE,
    pipe_txinhibit,
    \txsync_fsm.fsm_tx_reg[4] ,
    \txsync_fsm.fsm_tx_reg[4]_0 ,
    GT_TXPMARESET0120_out,
    DRPDI,
    PIPE_POWERDOWN,
    RXSYSCLKSEL,
    RXRATE,
    TXMARGIN,
    USER_OOBCLK,
    RXCHBONDO,
    TXPOSTCURSOR,
    TXPRECURSOR,
    PIPE_TXDATA,
    TXMAINCURSOR,
    PIPE_TXCOMPLIANCE,
    PIPE_TXDATAK,
    DRPADDR,
    Q,
    \pl_ltssm_state_q_reg[4] ,
    gt_rxvalid_q_reg,
    rst_cpllpd,
    p_0_in123_in,
    RST_CPLLRESET,
    p_0_in121_in);
  output RATE_CPLLLOCK;
  output [0:0]ext_ch_gt_drprdy;
  output [0:0]pipe_eyescandataerror;
  output [0:0]pci_exp_txn;
  output [0:0]pci_exp_txp;
  output RATE_PHYSTATUS;
  output rxcdrlock_reg1_reg;
  output [0:0]PIPE_RXCHANISALIGNED;
  output [0:0]pipe_rxcommadet;
  output [0:0]pipe_rxdlysresetdone;
  output [0:0]gt_rx_elec_idle_wire_filter;
  output [0:0]pipe_rxoutclk_out;
  output [0:0]pipe_rxphaligndone;
  output [0:0]pipe_rxprbserr;
  output RATE_RXRATEDONE;
  output USER_RXRESETDONE;
  output rxvalid_reg1_reg;
  output [0:0]pipe_txdlysresetdone;
  output [0:0]pipe_txphaligndone;
  output [0:0]pipe_txphinitdone;
  output RATE_TXRATEDONE;
  output USER_TXRESETDONE;
  output [15:0]ext_ch_gt_drpdo;
  output [2:0]pipe_rxbufstatus;
  output [2:0]pipe_rxstatus;
  output [15:0]\gt_rxdata_q_reg[15] ;
  output [7:0]pipe_dmonitorout;
  output [1:0]\gt_rxcharisk_q_reg[1] ;
  output [7:0]pipe_rxdisperr;
  output [7:0]pipe_rxnotintable;
  output [2:0]\gt_rx_status_q_reg[2] ;
  input gt_cpllpdrefclk;
  input \resetovrd_disble.reset_reg[4] ;
  input \fsm_reg[2] ;
  input \fsm_reg[0] ;
  input USER_EYESCANRESET;
  input sys_clk;
  input rst_gtreset;
  input [0:0]pci_exp_rxn;
  input [0:0]pci_exp_rxp;
  input qpllpd_reg;
  input qpllpd_reg_0;
  input \resetovrd_disble.fsm_reg[1] ;
  input gen3_reg;
  input USER_RXBUFRESET;
  input USER_RXCDRFREQRESET;
  input USER_RXCDRRESET;
  input gen3_reg_0;
  input converge_gen3_reg;
  input USER_RXDFELPMRESET;
  input SYNC_RXSYNC_DONE;
  input \rxsync_fsm_disable.fsm_rx_reg[2] ;
  input USER_RXPCSRESET;
  input rxsync_donem_reg2_reg;
  input GT_RXPMARESET0117_out;
  input [0:0]PIPE_RXPOLARITY;
  input userrdy_reg_rep__3;
  input pclk_sel_reg;
  input [0:0]PIPE_TXDEEMPH;
  input \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ;
  input \txsync_fsm.txdlyen_reg ;
  input \txsync_fsm.fsm_tx_reg[2] ;
  input [0:0]PIPE_TXELECIDLE;
  input [0:0]pipe_txinhibit;
  input \txsync_fsm.fsm_tx_reg[4] ;
  input \txsync_fsm.fsm_tx_reg[4]_0 ;
  input GT_TXPMARESET0120_out;
  input [15:0]DRPDI;
  input [1:0]PIPE_POWERDOWN;
  input [1:0]RXSYSCLKSEL;
  input [2:0]RXRATE;
  input [2:0]TXMARGIN;
  input USER_OOBCLK;
  input [4:0]RXCHBONDO;
  input [4:0]TXPOSTCURSOR;
  input [4:0]TXPRECURSOR;
  input [15:0]PIPE_TXDATA;
  input [6:0]TXMAINCURSOR;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [1:0]PIPE_TXDATAK;
  input [8:0]DRPADDR;
  input [1:0]Q;
  input \pl_ltssm_state_q_reg[4] ;
  input gt_rxvalid_q_reg;
  input rst_cpllpd;
  input p_0_in123_in;
  input RST_CPLLRESET;
  input p_0_in121_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire GT_RXPMARESET0117_out;
  wire GT_TXPMARESET0120_out;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXDEEMPH;
  wire [0:0]PIPE_TXELECIDLE;
  wire [1:0]Q;
  wire RATE_CPLLLOCK;
  wire RATE_PHYSTATUS;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RST_CPLLRESET;
  wire [4:0]RXCHBONDO;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire [6:0]TXMAINCURSOR;
  wire [2:0]TXMARGIN;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_EYESCANRESET;
  wire USER_OOBCLK;
  wire USER_RXBUFRESET;
  wire USER_RXCDRFREQRESET;
  wire USER_RXCDRRESET;
  wire USER_RXDFELPMRESET;
  wire USER_RXPCSRESET;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire converge_gen3_reg;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drprdy;
  wire \fsm_reg[0] ;
  wire \fsm_reg[2] ;
  wire gen3_reg;
  wire gen3_reg_0;
  wire gt_cpllpdrefclk;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxvalid_q_reg;
  wire \gtx_channel.gtxe2_channel_i_n_10 ;
  wire \gtx_channel.gtxe2_channel_i_n_138 ;
  wire \gtx_channel.gtxe2_channel_i_n_139 ;
  wire \gtx_channel.gtxe2_channel_i_n_140 ;
  wire \gtx_channel.gtxe2_channel_i_n_141 ;
  wire \gtx_channel.gtxe2_channel_i_n_142 ;
  wire \gtx_channel.gtxe2_channel_i_n_143 ;
  wire \gtx_channel.gtxe2_channel_i_n_144 ;
  wire \gtx_channel.gtxe2_channel_i_n_145 ;
  wire \gtx_channel.gtxe2_channel_i_n_146 ;
  wire \gtx_channel.gtxe2_channel_i_n_147 ;
  wire \gtx_channel.gtxe2_channel_i_n_148 ;
  wire \gtx_channel.gtxe2_channel_i_n_149 ;
  wire \gtx_channel.gtxe2_channel_i_n_150 ;
  wire \gtx_channel.gtxe2_channel_i_n_151 ;
  wire \gtx_channel.gtxe2_channel_i_n_152 ;
  wire \gtx_channel.gtxe2_channel_i_n_153 ;
  wire \gtx_channel.gtxe2_channel_i_n_189 ;
  wire \gtx_channel.gtxe2_channel_i_n_190 ;
  wire \gtx_channel.gtxe2_channel_i_n_191 ;
  wire \gtx_channel.gtxe2_channel_i_n_192 ;
  wire \gtx_channel.gtxe2_channel_i_n_197 ;
  wire \gtx_channel.gtxe2_channel_i_n_198 ;
  wire \gtx_channel.gtxe2_channel_i_n_37 ;
  wire \gtx_channel.gtxe2_channel_i_n_9 ;
  wire \gtx_channel.gtxe2_channel_i_n_91 ;
  wire \gtx_channel.gtxe2_channel_i_n_92 ;
  wire \gtx_channel.gtxe2_channel_i_n_93 ;
  wire \gtx_channel.gtxe2_channel_i_n_94 ;
  wire \gtx_channel.gtxe2_channel_i_n_95 ;
  wire p_0_in121_in;
  wire p_0_in123_in;
  wire [0:0]pci_exp_rxn;
  wire [0:0]pci_exp_rxp;
  wire [0:0]pci_exp_txn;
  wire [0:0]pci_exp_txp;
  wire pclk_sel_reg;
  wire [7:0]pipe_dmonitorout;
  wire [0:0]pipe_eyescandataerror;
  wire [2:0]pipe_rxbufstatus;
  wire [0:0]pipe_rxcommadet;
  wire [7:0]pipe_rxdisperr;
  wire [0:0]pipe_rxdlysresetdone;
  wire [7:0]pipe_rxnotintable;
  wire [0:0]pipe_rxoutclk_out;
  wire [0:0]pipe_rxphaligndone;
  wire [0:0]pipe_rxprbserr;
  wire [2:0]pipe_rxstatus;
  wire \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ;
  wire [0:0]pipe_txdlysresetdone;
  wire [0:0]pipe_txinhibit;
  wire [0:0]pipe_txphaligndone;
  wire [0:0]pipe_txphinitdone;
  wire \pl_ltssm_state_q_reg[4] ;
  wire qpllpd_reg;
  wire qpllpd_reg_0;
  wire \resetovrd_disble.fsm_reg[1] ;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_cpllpd;
  wire rst_gtreset;
  wire rxcdrlock_reg1_reg;
  wire rxsync_donem_reg2_reg;
  wire \rxsync_fsm_disable.fsm_rx_reg[2] ;
  wire rxvalid_reg1_reg;
  wire sys_clk;
  wire \txsync_fsm.fsm_tx_reg[2] ;
  wire \txsync_fsm.fsm_tx_reg[4] ;
  wire \txsync_fsm.fsm_tx_reg[4]_0 ;
  wire \txsync_fsm.txdlyen_reg ;
  wire userrdy_reg_rep__3;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
  wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
  wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
  wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
  wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
  wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;

  PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_81 cpllPDInst
       (.CPLLPD0(CPLLPD0),
        .CPLLRESET0(CPLLRESET0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .p_0_in121_in(p_0_in121_in),
        .p_0_in123_in(p_0_in123_in),
        .rst_cpllpd(rst_cpllpd));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[0]_i_1__4 
       (.I0(pipe_rxstatus[0]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [0]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[1]_i_1__4 
       (.I0(pipe_rxstatus[1]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [1]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[2]_i_1__4 
       (.I0(pipe_rxstatus[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [2]));
  (* box_type = "PRIMITIVE" *) 
  GTXE2_CHANNEL #(
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(1),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CHAN_BOND_KEEP_ALIGN("TRUE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0001001010),
    .CHAN_BOND_SEQ_1_2(10'b0001001010),
    .CHAN_BOND_SEQ_1_3(10'b0001001010),
    .CHAN_BOND_SEQ_1_4(10'b0110111100),
    .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_1(10'b0001000101),
    .CHAN_BOND_SEQ_2_2(10'b0001000101),
    .CHAN_BOND_SEQ_2_3(10'b0001000101),
    .CHAN_BOND_SEQ_2_4(10'b0110111100),
    .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_USE("TRUE"),
    .CHAN_BOND_SEQ_LEN(4),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("TRUE"),
    .CLK_COR_MAX_LAT(20),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0100011100),
    .CLK_COR_SEQ_1_2(10'b0000000000),
    .CLK_COR_SEQ_1_3(10'b0000000000),
    .CLK_COR_SEQ_1_4(10'b0000000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0000000000),
    .CLK_COR_SEQ_2_2(10'b0000000000),
    .CLK_COR_SEQ_2_3(10'b0000000000),
    .CLK_COR_SEQ_2_4(10'b0000000000),
    .CLK_COR_SEQ_2_ENABLE(4'b0000),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(1),
    .CPLL_CFG(24'hA407CC),
    .CPLL_FBDIV(5),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000B01),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("FALSE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("TRUE"),
    .GEARBOX_MODE(3'b000),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("TRUE"),
    .PCS_RSVD_ATTR(48'h0000000001CF),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h09),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'h00018480),
    .PMA_RSV2(16'h2050),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(32'h00000000),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b0100),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("TRUE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(72'h03000023FF10200020),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b1),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00000011110000),
    .RXLPM_LF_CFG(14'b00000011110000),
    .RXOOB_CFG(7'b0000110),
    .RXOUT_DIV(2),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h004020),
    .RXPH_CFG(24'h000000),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("PMA"),
    .RX_BIAS_CFG(12'b000000000100),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(4),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(3'b010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(12'b000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFE_GAIN_CFG(23'h020FEA),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011110000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_KL_CFG(13'b0000011111110),
    .RX_DFE_KL_CFG2(32'h3290D86C),
    .RX_DFE_LPM_CFG(16'h0954),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
    .RX_DFE_UT_CFG(17'b10001111000000000),
    .RX_DFE_VP_CFG(17'b00011111100000011),
    .RX_DFE_XYD_CFG(13'b0000000000000),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(4),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b1111),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("FALSE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
    .SIM_VERSION("3.0"),
    .TERM_RCAL_CFG(5'b10000),
    .TERM_RCAL_OVRD(1'b0),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("FALSE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOUT_DIV(2),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPMARESET_TIME(5'b00011),
    .TX_CLK25_DIV(4),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(5'b10100),
    .TX_DEEMPH1(5'b01011),
    .TX_DRIVE_MODE("PIPE"),
    .TX_EIDLE_ASSERT_DELAY(3'b010),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001111),
    .TX_MARGIN_FULL_1(7'b1001110),
    .TX_MARGIN_FULL_2(7'b1001101),
    .TX_MARGIN_FULL_3(7'b1001100),
    .TX_MARGIN_FULL_4(7'b1000011),
    .TX_MARGIN_LOW_0(7'b1000101),
    .TX_MARGIN_LOW_1(7'b1000110),
    .TX_MARGIN_LOW_2(7'b1000011),
    .TX_MARGIN_LOW_3(7'b1000010),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_PREDRIVER_MODE(1'b0),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h0064),
    .TX_RXDETECT_REF(3'b011),
    .TX_XCLK_SEL("TXUSR"),
    .UCODEER_CLR(1'b0)) 
    \gtx_channel.gtxe2_channel_i 
       (.CFGRESET(1'b0),
        .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
        .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
        .CPLLLOCK(RATE_CPLLLOCK),
        .CPLLLOCKDETCLK(1'b0),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD0),
        .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET0),
        .DMONITOROUT(pipe_dmonitorout),
        .DRPADDR(DRPADDR),
        .DRPCLK(\resetovrd_disble.reset_reg[4] ),
        .DRPDI(DRPDI),
        .DRPDO(ext_ch_gt_drpdo),
        .DRPEN(\fsm_reg[2] ),
        .DRPRDY(ext_ch_gt_drprdy),
        .DRPWE(\fsm_reg[0] ),
        .EYESCANDATAERROR(pipe_eyescandataerror),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(USER_EYESCANRESET),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(rst_gtreset),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(rst_gtreset),
        .GTXRXN(pci_exp_rxn),
        .GTXRXP(pci_exp_rxp),
        .GTXTXN(pci_exp_txn),
        .GTXTXP(pci_exp_txp),
        .LOOPBACK({1'b0,1'b0,1'b0}),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
        .PHYSTATUS(RATE_PHYSTATUS),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(qpllpd_reg),
        .QPLLREFCLK(qpllpd_reg_0),
        .RESETOVRD(\resetovrd_disble.fsm_reg[1] ),
        .RX8B10BEN(gen3_reg),
        .RXBUFRESET(USER_RXBUFRESET),
        .RXBUFSTATUS(pipe_rxbufstatus),
        .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
        .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
        .RXCDRFREQRESET(USER_RXCDRFREQRESET),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(rxcdrlock_reg1_reg),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(USER_RXCDRRESET),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
        .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
        .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
        .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
        .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,\gt_rxcharisk_q_reg[1] }),
        .RXCHBONDEN(gen3_reg),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }),
        .RXCHBONDSLAVE(gen3_reg_0),
        .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
        .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
        .RXCOMMADET(pipe_rxcommadet),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
        .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
        .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,\gt_rxdata_q_reg[15] }),
        .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(converge_gen3_reg),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b1),
        .RXDFELPMRESET(USER_RXDFELPMRESET),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b0),
        .RXDFEXYDHOLD(1'b0),
        .RXDFEXYDOVRDEN(1'b0),
        .RXDISPERR(pipe_rxdisperr),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(SYNC_RXSYNC_DONE),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(\rxsync_fsm_disable.fsm_rx_reg[2] ),
        .RXDLYSRESETDONE(pipe_rxdlysresetdone),
        .RXELECIDLE(gt_rx_elec_idle_wire_filter),
        .RXELECIDLEMODE({1'b0,1'b0}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
        .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
        .RXLPMEN(gen3_reg_0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(gen3_reg),
        .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE(pipe_rxnotintable),
        .RXOOBRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(pipe_rxoutclk_out),
        .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
        .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
        .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .RXPCOMMAALIGNEN(gen3_reg_0),
        .RXPCSRESET(USER_RXPCSRESET),
        .RXPD(PIPE_POWERDOWN),
        .RXPHALIGN(rxsync_donem_reg2_reg),
        .RXPHALIGNDONE(pipe_rxphaligndone),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
        .RXPMARESET(GT_RXPMARESET0117_out),
        .RXPOLARITY(PIPE_RXPOLARITY),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(pipe_rxprbserr),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
        .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
        .RXRATE(RXRATE),
        .RXRATEDONE(RATE_RXRATEDONE),
        .RXRESETDONE(USER_RXRESETDONE),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
        .RXSTATUS(pipe_rxstatus),
        .RXSYSCLKSEL(RXSYSCLKSEL),
        .RXUSERRDY(userrdy_reg_rep__3),
        .RXUSRCLK(pclk_sel_reg),
        .RXUSRCLK2(pclk_sel_reg),
        .RXVALID(rxvalid_reg1_reg),
        .SETERRSTATUS(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(gen3_reg_0),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
        .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
        .TXDEEMPH(PIPE_TXDEEMPH),
        .TXDETECTRX(\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ),
        .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b0),
        .TXDLYEN(\txsync_fsm.txdlyen_reg ),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(\txsync_fsm.fsm_tx_reg[2] ),
        .TXDLYSRESETDONE(pipe_txdlysresetdone),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(PIPE_TXELECIDLE),
        .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(pipe_txinhibit),
        .TXMAINCURSOR(TXMAINCURSOR),
        .TXMARGIN(TXMARGIN),
        .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ),
        .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
        .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
        .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD(PIPE_POWERDOWN),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(\txsync_fsm.fsm_tx_reg[4] ),
        .TXPHALIGNDONE(pipe_txphaligndone),
        .TXPHALIGNEN(1'b1),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(\txsync_fsm.fsm_tx_reg[4]_0 ),
        .TXPHINITDONE(pipe_txphinitdone),
        .TXPHOVRDEN(1'b0),
        .TXPISOPD(1'b0),
        .TXPMARESET(GT_TXPMARESET0120_out),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR(TXPOSTCURSOR),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR(TXPRECURSOR),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
        .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE(RXRATE),
        .TXRATEDONE(RATE_TXRATEDONE),
        .TXRESETDONE(USER_TXRESETDONE),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYSCLKSEL(RXSYSCLKSEL),
        .TXUSERRDY(userrdy_reg_rep__3),
        .TXUSRCLK(pclk_sel_reg),
        .TXUSRCLK2(pclk_sel_reg));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_41
   (RATE_CPLLLOCK,
    ext_ch_gt_drprdy,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    RATE_PHYSTATUS,
    rxcdrlock_reg1_reg,
    PIPE_RXCHANISALIGNED,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    gt_rx_elec_idle_wire_filter,
    pipe_rxoutclk_out,
    pipe_rxphaligndone,
    pipe_rxprbserr,
    RATE_RXRATEDONE,
    USER_RXRESETDONE,
    rxvalid_reg1_reg,
    pipe_txdlysresetdone,
    pipe_txphaligndone,
    pipe_txphinitdone,
    RATE_TXRATEDONE,
    USER_TXRESETDONE,
    ext_ch_gt_drpdo,
    pipe_rxbufstatus,
    pipe_rxstatus,
    \gt_rxdata_q_reg[15] ,
    pipe_dmonitorout,
    \gt_rxcharisk_q_reg[1] ,
    pipe_rxdisperr,
    pipe_rxnotintable,
    rxphaligndone_s_reg1_reg,
    \gt_rx_status_q_reg[2] ,
    gt_cpllpdrefclk,
    \resetovrd_disble.reset_reg[4] ,
    \fsm_reg[2] ,
    \fsm_reg[0] ,
    USER_EYESCANRESET,
    sys_clk,
    rst_gtreset,
    pci_exp_rxn,
    pci_exp_rxp,
    qpllpd_reg,
    qpllpd_reg_0,
    \resetovrd_disble.fsm_reg[1] ,
    gen3_reg,
    USER_RXBUFRESET,
    USER_RXCDRFREQRESET,
    USER_RXCDRRESET,
    gen3_reg_0,
    converge_gen3_reg,
    USER_RXDFELPMRESET,
    SYNC_RXSYNC_DONE,
    \rxsync_fsm_disable.fsm_rx_reg[2] ,
    USER_RXPCSRESET,
    rxsync_donem_reg2_reg,
    GT_RXPMARESET071_out,
    PIPE_RXPOLARITY,
    userrdy_reg_rep__2,
    pclk_sel_reg,
    PIPE_TXDEEMPH,
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ,
    \txsync_fsm.txdlyen_reg ,
    \txsync_fsm.fsm_tx_reg[2] ,
    PIPE_TXELECIDLE,
    pipe_txinhibit,
    \txsync_fsm.fsm_tx_reg[4] ,
    \txsync_fsm.fsm_tx_reg[4]_0 ,
    GT_TXPMARESET074_out,
    DRPDI,
    PIPE_POWERDOWN,
    RXSYSCLKSEL,
    RXRATE,
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ,
    USER_OOBCLK,
    RXCHBONDO,
    TXPOSTCURSOR,
    TXPRECURSOR,
    PIPE_TXDATA,
    TXMAINCURSOR,
    PIPE_TXCOMPLIANCE,
    PIPE_TXDATAK,
    DRPADDR,
    \resetovrd_disble.reset_reg[4]_0 ,
    Q,
    \pl_ltssm_state_q_reg[4] ,
    gt_rxvalid_q_reg,
    rst_cpllpd,
    p_0_in77_in,
    RST_CPLLRESET,
    p_0_in75_in);
  output RATE_CPLLLOCK;
  output [0:0]ext_ch_gt_drprdy;
  output [0:0]pipe_eyescandataerror;
  output [0:0]pci_exp_txn;
  output [0:0]pci_exp_txp;
  output RATE_PHYSTATUS;
  output rxcdrlock_reg1_reg;
  output [0:0]PIPE_RXCHANISALIGNED;
  output [0:0]pipe_rxcommadet;
  output [0:0]pipe_rxdlysresetdone;
  output [0:0]gt_rx_elec_idle_wire_filter;
  output [0:0]pipe_rxoutclk_out;
  output [0:0]pipe_rxphaligndone;
  output [0:0]pipe_rxprbserr;
  output RATE_RXRATEDONE;
  output USER_RXRESETDONE;
  output rxvalid_reg1_reg;
  output [0:0]pipe_txdlysresetdone;
  output [0:0]pipe_txphaligndone;
  output [0:0]pipe_txphinitdone;
  output RATE_TXRATEDONE;
  output USER_TXRESETDONE;
  output [15:0]ext_ch_gt_drpdo;
  output [2:0]pipe_rxbufstatus;
  output [2:0]pipe_rxstatus;
  output [15:0]\gt_rxdata_q_reg[15] ;
  output [7:0]pipe_dmonitorout;
  output [1:0]\gt_rxcharisk_q_reg[1] ;
  output [7:0]pipe_rxdisperr;
  output [7:0]pipe_rxnotintable;
  output rxphaligndone_s_reg1_reg;
  output [2:0]\gt_rx_status_q_reg[2] ;
  input gt_cpllpdrefclk;
  input \resetovrd_disble.reset_reg[4] ;
  input \fsm_reg[2] ;
  input \fsm_reg[0] ;
  input USER_EYESCANRESET;
  input sys_clk;
  input rst_gtreset;
  input [0:0]pci_exp_rxn;
  input [0:0]pci_exp_rxp;
  input qpllpd_reg;
  input qpllpd_reg_0;
  input \resetovrd_disble.fsm_reg[1] ;
  input gen3_reg;
  input USER_RXBUFRESET;
  input USER_RXCDRFREQRESET;
  input USER_RXCDRRESET;
  input gen3_reg_0;
  input converge_gen3_reg;
  input USER_RXDFELPMRESET;
  input SYNC_RXSYNC_DONE;
  input \rxsync_fsm_disable.fsm_rx_reg[2] ;
  input USER_RXPCSRESET;
  input rxsync_donem_reg2_reg;
  input GT_RXPMARESET071_out;
  input [0:0]PIPE_RXPOLARITY;
  input userrdy_reg_rep__2;
  input pclk_sel_reg;
  input [0:0]PIPE_TXDEEMPH;
  input \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ;
  input \txsync_fsm.txdlyen_reg ;
  input \txsync_fsm.fsm_tx_reg[2] ;
  input [0:0]PIPE_TXELECIDLE;
  input [0:0]pipe_txinhibit;
  input \txsync_fsm.fsm_tx_reg[4] ;
  input \txsync_fsm.fsm_tx_reg[4]_0 ;
  input GT_TXPMARESET074_out;
  input [15:0]DRPDI;
  input [1:0]PIPE_POWERDOWN;
  input [1:0]RXSYSCLKSEL;
  input [2:0]RXRATE;
  input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ;
  input USER_OOBCLK;
  input [4:0]RXCHBONDO;
  input [4:0]TXPOSTCURSOR;
  input [4:0]TXPRECURSOR;
  input [15:0]PIPE_TXDATA;
  input [6:0]TXMAINCURSOR;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [1:0]PIPE_TXDATAK;
  input [8:0]DRPADDR;
  input [5:0]\resetovrd_disble.reset_reg[4]_0 ;
  input [1:0]Q;
  input \pl_ltssm_state_q_reg[4] ;
  input gt_rxvalid_q_reg;
  input rst_cpllpd;
  input p_0_in77_in;
  input RST_CPLLRESET;
  input p_0_in75_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire GT_RXPMARESET071_out;
  wire GT_TXPMARESET074_out;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXDEEMPH;
  wire [0:0]PIPE_TXELECIDLE;
  wire [1:0]Q;
  wire RATE_CPLLLOCK;
  wire RATE_PHYSTATUS;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RST_CPLLRESET;
  wire [4:0]RXCHBONDO;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_EYESCANRESET;
  wire USER_OOBCLK;
  wire USER_RXBUFRESET;
  wire USER_RXCDRFREQRESET;
  wire USER_RXCDRRESET;
  wire USER_RXDFELPMRESET;
  wire USER_RXPCSRESET;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire converge_gen3_reg;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drprdy;
  wire \fsm_reg[0] ;
  wire \fsm_reg[2] ;
  wire gen3_reg;
  wire gen3_reg_0;
  wire gt_cpllpdrefclk;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxvalid_q_reg;
  wire \gtx_channel.gtxe2_channel_i_n_10 ;
  wire \gtx_channel.gtxe2_channel_i_n_138 ;
  wire \gtx_channel.gtxe2_channel_i_n_139 ;
  wire \gtx_channel.gtxe2_channel_i_n_140 ;
  wire \gtx_channel.gtxe2_channel_i_n_141 ;
  wire \gtx_channel.gtxe2_channel_i_n_142 ;
  wire \gtx_channel.gtxe2_channel_i_n_143 ;
  wire \gtx_channel.gtxe2_channel_i_n_144 ;
  wire \gtx_channel.gtxe2_channel_i_n_145 ;
  wire \gtx_channel.gtxe2_channel_i_n_146 ;
  wire \gtx_channel.gtxe2_channel_i_n_147 ;
  wire \gtx_channel.gtxe2_channel_i_n_148 ;
  wire \gtx_channel.gtxe2_channel_i_n_149 ;
  wire \gtx_channel.gtxe2_channel_i_n_150 ;
  wire \gtx_channel.gtxe2_channel_i_n_151 ;
  wire \gtx_channel.gtxe2_channel_i_n_152 ;
  wire \gtx_channel.gtxe2_channel_i_n_153 ;
  wire \gtx_channel.gtxe2_channel_i_n_189 ;
  wire \gtx_channel.gtxe2_channel_i_n_190 ;
  wire \gtx_channel.gtxe2_channel_i_n_191 ;
  wire \gtx_channel.gtxe2_channel_i_n_192 ;
  wire \gtx_channel.gtxe2_channel_i_n_197 ;
  wire \gtx_channel.gtxe2_channel_i_n_198 ;
  wire \gtx_channel.gtxe2_channel_i_n_37 ;
  wire \gtx_channel.gtxe2_channel_i_n_9 ;
  wire \gtx_channel.gtxe2_channel_i_n_91 ;
  wire \gtx_channel.gtxe2_channel_i_n_92 ;
  wire \gtx_channel.gtxe2_channel_i_n_93 ;
  wire \gtx_channel.gtxe2_channel_i_n_94 ;
  wire \gtx_channel.gtxe2_channel_i_n_95 ;
  wire p_0_in75_in;
  wire p_0_in77_in;
  wire [0:0]pci_exp_rxn;
  wire [0:0]pci_exp_rxp;
  wire [0:0]pci_exp_txn;
  wire [0:0]pci_exp_txp;
  wire pclk_sel_reg;
  wire [7:0]pipe_dmonitorout;
  wire [0:0]pipe_eyescandataerror;
  wire [2:0]pipe_rxbufstatus;
  wire [0:0]pipe_rxcommadet;
  wire [7:0]pipe_rxdisperr;
  wire [0:0]pipe_rxdlysresetdone;
  wire [7:0]pipe_rxnotintable;
  wire [0:0]pipe_rxoutclk_out;
  wire [0:0]pipe_rxphaligndone;
  wire [0:0]pipe_rxprbserr;
  wire [2:0]pipe_rxstatus;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ;
  wire \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ;
  wire [0:0]pipe_txdlysresetdone;
  wire [0:0]pipe_txinhibit;
  wire [0:0]pipe_txphaligndone;
  wire [0:0]pipe_txphinitdone;
  wire \pl_ltssm_state_q_reg[4] ;
  wire qpllpd_reg;
  wire qpllpd_reg_0;
  wire \resetovrd_disble.fsm_reg[1] ;
  wire \resetovrd_disble.reset_reg[4] ;
  wire [5:0]\resetovrd_disble.reset_reg[4]_0 ;
  wire rst_cpllpd;
  wire rst_gtreset;
  wire rxcdrlock_reg1_reg;
  wire rxphaligndone_s_reg1_i_2_n_0;
  wire rxphaligndone_s_reg1_reg;
  wire rxsync_donem_reg2_reg;
  wire \rxsync_fsm_disable.fsm_rx_reg[2] ;
  wire rxvalid_reg1_reg;
  wire sys_clk;
  wire \txsync_fsm.fsm_tx_reg[2] ;
  wire \txsync_fsm.fsm_tx_reg[4] ;
  wire \txsync_fsm.fsm_tx_reg[4]_0 ;
  wire \txsync_fsm.txdlyen_reg ;
  wire userrdy_reg_rep__2;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
  wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
  wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
  wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
  wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
  wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;

  PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_79 cpllPDInst
       (.CPLLPD0(CPLLPD0),
        .CPLLRESET0(CPLLRESET0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .p_0_in75_in(p_0_in75_in),
        .p_0_in77_in(p_0_in77_in),
        .rst_cpllpd(rst_cpllpd));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[0]_i_1__3 
       (.I0(pipe_rxstatus[0]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [0]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[1]_i_1__3 
       (.I0(pipe_rxstatus[1]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [1]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[2]_i_1__3 
       (.I0(pipe_rxstatus[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [2]));
  (* box_type = "PRIMITIVE" *) 
  GTXE2_CHANNEL #(
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(1),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CHAN_BOND_KEEP_ALIGN("TRUE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0001001010),
    .CHAN_BOND_SEQ_1_2(10'b0001001010),
    .CHAN_BOND_SEQ_1_3(10'b0001001010),
    .CHAN_BOND_SEQ_1_4(10'b0110111100),
    .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_1(10'b0001000101),
    .CHAN_BOND_SEQ_2_2(10'b0001000101),
    .CHAN_BOND_SEQ_2_3(10'b0001000101),
    .CHAN_BOND_SEQ_2_4(10'b0110111100),
    .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_USE("TRUE"),
    .CHAN_BOND_SEQ_LEN(4),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("TRUE"),
    .CLK_COR_MAX_LAT(20),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0100011100),
    .CLK_COR_SEQ_1_2(10'b0000000000),
    .CLK_COR_SEQ_1_3(10'b0000000000),
    .CLK_COR_SEQ_1_4(10'b0000000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0000000000),
    .CLK_COR_SEQ_2_2(10'b0000000000),
    .CLK_COR_SEQ_2_3(10'b0000000000),
    .CLK_COR_SEQ_2_4(10'b0000000000),
    .CLK_COR_SEQ_2_ENABLE(4'b0000),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(1),
    .CPLL_CFG(24'hA407CC),
    .CPLL_FBDIV(5),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000B01),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("FALSE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("TRUE"),
    .GEARBOX_MODE(3'b000),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("TRUE"),
    .PCS_RSVD_ATTR(48'h0000000001CF),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h09),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'h00018480),
    .PMA_RSV2(16'h2050),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(32'h00000000),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b0100),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("TRUE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(72'h03000023FF10200020),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b1),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00000011110000),
    .RXLPM_LF_CFG(14'b00000011110000),
    .RXOOB_CFG(7'b0000110),
    .RXOUT_DIV(2),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h004020),
    .RXPH_CFG(24'h000000),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("PMA"),
    .RX_BIAS_CFG(12'b000000000100),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(4),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(3'b010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(12'b000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFE_GAIN_CFG(23'h020FEA),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011110000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_KL_CFG(13'b0000011111110),
    .RX_DFE_KL_CFG2(32'h3290D86C),
    .RX_DFE_LPM_CFG(16'h0954),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
    .RX_DFE_UT_CFG(17'b10001111000000000),
    .RX_DFE_VP_CFG(17'b00011111100000011),
    .RX_DFE_XYD_CFG(13'b0000000000000),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(4),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b1111),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("FALSE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
    .SIM_VERSION("3.0"),
    .TERM_RCAL_CFG(5'b10000),
    .TERM_RCAL_OVRD(1'b0),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("FALSE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOUT_DIV(2),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPMARESET_TIME(5'b00011),
    .TX_CLK25_DIV(4),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(5'b10100),
    .TX_DEEMPH1(5'b01011),
    .TX_DRIVE_MODE("PIPE"),
    .TX_EIDLE_ASSERT_DELAY(3'b010),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001111),
    .TX_MARGIN_FULL_1(7'b1001110),
    .TX_MARGIN_FULL_2(7'b1001101),
    .TX_MARGIN_FULL_3(7'b1001100),
    .TX_MARGIN_FULL_4(7'b1000011),
    .TX_MARGIN_LOW_0(7'b1000101),
    .TX_MARGIN_LOW_1(7'b1000110),
    .TX_MARGIN_LOW_2(7'b1000011),
    .TX_MARGIN_LOW_3(7'b1000010),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_PREDRIVER_MODE(1'b0),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h0064),
    .TX_RXDETECT_REF(3'b011),
    .TX_XCLK_SEL("TXUSR"),
    .UCODEER_CLR(1'b0)) 
    \gtx_channel.gtxe2_channel_i 
       (.CFGRESET(1'b0),
        .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
        .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
        .CPLLLOCK(RATE_CPLLLOCK),
        .CPLLLOCKDETCLK(1'b0),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD0),
        .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET0),
        .DMONITOROUT(pipe_dmonitorout),
        .DRPADDR(DRPADDR),
        .DRPCLK(\resetovrd_disble.reset_reg[4] ),
        .DRPDI(DRPDI),
        .DRPDO(ext_ch_gt_drpdo),
        .DRPEN(\fsm_reg[2] ),
        .DRPRDY(ext_ch_gt_drprdy),
        .DRPWE(\fsm_reg[0] ),
        .EYESCANDATAERROR(pipe_eyescandataerror),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(USER_EYESCANRESET),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(rst_gtreset),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(rst_gtreset),
        .GTXRXN(pci_exp_rxn),
        .GTXRXP(pci_exp_rxp),
        .GTXTXN(pci_exp_txn),
        .GTXTXP(pci_exp_txp),
        .LOOPBACK({1'b0,1'b0,1'b0}),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
        .PHYSTATUS(RATE_PHYSTATUS),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(qpllpd_reg),
        .QPLLREFCLK(qpllpd_reg_0),
        .RESETOVRD(\resetovrd_disble.fsm_reg[1] ),
        .RX8B10BEN(gen3_reg),
        .RXBUFRESET(USER_RXBUFRESET),
        .RXBUFSTATUS(pipe_rxbufstatus),
        .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
        .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
        .RXCDRFREQRESET(USER_RXCDRFREQRESET),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(rxcdrlock_reg1_reg),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(USER_RXCDRRESET),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
        .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
        .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
        .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
        .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,\gt_rxcharisk_q_reg[1] }),
        .RXCHBONDEN(gen3_reg),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }),
        .RXCHBONDSLAVE(gen3_reg_0),
        .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
        .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
        .RXCOMMADET(pipe_rxcommadet),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
        .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
        .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,\gt_rxdata_q_reg[15] }),
        .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(converge_gen3_reg),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b1),
        .RXDFELPMRESET(USER_RXDFELPMRESET),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b0),
        .RXDFEXYDHOLD(1'b0),
        .RXDFEXYDOVRDEN(1'b0),
        .RXDISPERR(pipe_rxdisperr),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(SYNC_RXSYNC_DONE),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(\rxsync_fsm_disable.fsm_rx_reg[2] ),
        .RXDLYSRESETDONE(pipe_rxdlysresetdone),
        .RXELECIDLE(gt_rx_elec_idle_wire_filter),
        .RXELECIDLEMODE({1'b0,1'b0}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
        .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
        .RXLPMEN(gen3_reg_0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(gen3_reg),
        .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE(pipe_rxnotintable),
        .RXOOBRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(pipe_rxoutclk_out),
        .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
        .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
        .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .RXPCOMMAALIGNEN(gen3_reg_0),
        .RXPCSRESET(USER_RXPCSRESET),
        .RXPD(PIPE_POWERDOWN),
        .RXPHALIGN(rxsync_donem_reg2_reg),
        .RXPHALIGNDONE(pipe_rxphaligndone),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
        .RXPMARESET(GT_RXPMARESET071_out),
        .RXPOLARITY(PIPE_RXPOLARITY),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(pipe_rxprbserr),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
        .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
        .RXRATE(RXRATE),
        .RXRATEDONE(RATE_RXRATEDONE),
        .RXRESETDONE(USER_RXRESETDONE),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
        .RXSTATUS(pipe_rxstatus),
        .RXSYSCLKSEL(RXSYSCLKSEL),
        .RXUSERRDY(userrdy_reg_rep__2),
        .RXUSRCLK(pclk_sel_reg),
        .RXUSRCLK2(pclk_sel_reg),
        .RXVALID(rxvalid_reg1_reg),
        .SETERRSTATUS(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(gen3_reg_0),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
        .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
        .TXDEEMPH(PIPE_TXDEEMPH),
        .TXDETECTRX(\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ),
        .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b0),
        .TXDLYEN(\txsync_fsm.txdlyen_reg ),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(\txsync_fsm.fsm_tx_reg[2] ),
        .TXDLYSRESETDONE(pipe_txdlysresetdone),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(PIPE_TXELECIDLE),
        .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(pipe_txinhibit),
        .TXMAINCURSOR(TXMAINCURSOR),
        .TXMARGIN(\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ),
        .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ),
        .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
        .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
        .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD(PIPE_POWERDOWN),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(\txsync_fsm.fsm_tx_reg[4] ),
        .TXPHALIGNDONE(pipe_txphaligndone),
        .TXPHALIGNEN(1'b1),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(\txsync_fsm.fsm_tx_reg[4]_0 ),
        .TXPHINITDONE(pipe_txphinitdone),
        .TXPHOVRDEN(1'b0),
        .TXPISOPD(1'b0),
        .TXPMARESET(GT_TXPMARESET074_out),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR(TXPOSTCURSOR),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR(TXPRECURSOR),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
        .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE(RXRATE),
        .TXRATEDONE(RATE_TXRATEDONE),
        .TXRESETDONE(USER_TXRESETDONE),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYSCLKSEL(RXSYSCLKSEL),
        .TXUSERRDY(userrdy_reg_rep__2),
        .TXUSRCLK(pclk_sel_reg),
        .TXUSRCLK2(pclk_sel_reg));
  LUT2 #(
    .INIT(4'h8)) 
    rxphaligndone_s_reg1_i_1
       (.I0(rxphaligndone_s_reg1_i_2_n_0),
        .I1(\resetovrd_disble.reset_reg[4]_0 [0]),
        .O(rxphaligndone_s_reg1_reg));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    rxphaligndone_s_reg1_i_2
       (.I0(pipe_rxphaligndone),
        .I1(\resetovrd_disble.reset_reg[4]_0 [1]),
        .I2(\resetovrd_disble.reset_reg[4]_0 [4]),
        .I3(\resetovrd_disble.reset_reg[4]_0 [5]),
        .I4(\resetovrd_disble.reset_reg[4]_0 [2]),
        .I5(\resetovrd_disble.reset_reg[4]_0 [3]),
        .O(rxphaligndone_s_reg1_i_2_n_0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_47
   (RATE_CPLLLOCK,
    ext_ch_gt_drprdy,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    RATE_PHYSTATUS,
    rxcdrlock_reg1_reg,
    PIPE_RXCHANISALIGNED,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    gt_rx_elec_idle_wire_filter,
    pipe_rxoutclk_out,
    pipe_rxphaligndone,
    pipe_rxprbserr,
    RATE_RXRATEDONE,
    USER_RXRESETDONE,
    rxvalid_reg1_reg,
    pipe_txdlysresetdone,
    pipe_txphaligndone,
    pipe_txphinitdone,
    RATE_TXRATEDONE,
    USER_TXRESETDONE,
    ext_ch_gt_drpdo,
    pipe_rxbufstatus,
    pipe_rxstatus,
    \gt_rxdata_q_reg[15] ,
    pipe_dmonitorout,
    \gt_rxcharisk_q_reg[1] ,
    pipe_rxdisperr,
    pipe_rxnotintable,
    \gt_rx_status_q_reg[2] ,
    gt_cpllpdrefclk,
    \resetovrd_disble.reset_reg[4] ,
    \fsm_reg[2] ,
    \fsm_reg[0] ,
    USER_EYESCANRESET,
    sys_clk,
    rst_gtreset,
    pci_exp_rxn,
    pci_exp_rxp,
    qpllpd_reg,
    qpllpd_reg_0,
    \resetovrd_disble.fsm_reg[1] ,
    gen3_reg,
    USER_RXBUFRESET,
    USER_RXCDRFREQRESET,
    USER_RXCDRRESET,
    gen3_reg_0,
    GT_RX_CONVERGE0,
    USER_RXDFELPMRESET,
    SYNC_RXSYNC_DONE,
    \rxsync_fsm_disable.fsm_rx_reg[2] ,
    USER_RXPCSRESET,
    rxsync_donem_reg2_reg,
    GT_RXPMARESET061_out,
    PIPE_RXPOLARITY,
    userrdy_reg_rep__1,
    pclk_sel_reg,
    PIPE_TXDEEMPH,
    PIPE_TXDETECTRX,
    \txsync_fsm.txdlyen_reg ,
    \txsync_fsm.fsm_tx_reg[2] ,
    PIPE_TXELECIDLE,
    pipe_txinhibit,
    \txsync_fsm.fsm_tx_reg[4] ,
    \txsync_fsm.fsm_tx_reg[4]_0 ,
    GT_TXPMARESET064_out,
    DRPDI,
    PIPE_POWERDOWN,
    RXSYSCLKSEL,
    RXRATE,
    PIPE_TXMARGIN,
    USER_OOBCLK,
    RXCHBONDO,
    TXPOSTCURSOR,
    TXPRECURSOR,
    PIPE_TXDATA,
    TXMAINCURSOR,
    PIPE_TXCOMPLIANCE,
    PIPE_TXDATAK,
    DRPADDR,
    Q,
    \pl_ltssm_state_q_reg[4] ,
    gt_rxvalid_q_reg,
    rst_cpllpd,
    p_0_in67_in,
    RST_CPLLRESET,
    p_0_in65_in);
  output RATE_CPLLLOCK;
  output [0:0]ext_ch_gt_drprdy;
  output [0:0]pipe_eyescandataerror;
  output [0:0]pci_exp_txn;
  output [0:0]pci_exp_txp;
  output RATE_PHYSTATUS;
  output rxcdrlock_reg1_reg;
  output [0:0]PIPE_RXCHANISALIGNED;
  output [0:0]pipe_rxcommadet;
  output [0:0]pipe_rxdlysresetdone;
  output [0:0]gt_rx_elec_idle_wire_filter;
  output [0:0]pipe_rxoutclk_out;
  output [0:0]pipe_rxphaligndone;
  output [0:0]pipe_rxprbserr;
  output RATE_RXRATEDONE;
  output USER_RXRESETDONE;
  output rxvalid_reg1_reg;
  output [0:0]pipe_txdlysresetdone;
  output [0:0]pipe_txphaligndone;
  output [0:0]pipe_txphinitdone;
  output RATE_TXRATEDONE;
  output USER_TXRESETDONE;
  output [15:0]ext_ch_gt_drpdo;
  output [2:0]pipe_rxbufstatus;
  output [2:0]pipe_rxstatus;
  output [15:0]\gt_rxdata_q_reg[15] ;
  output [7:0]pipe_dmonitorout;
  output [1:0]\gt_rxcharisk_q_reg[1] ;
  output [7:0]pipe_rxdisperr;
  output [7:0]pipe_rxnotintable;
  output [2:0]\gt_rx_status_q_reg[2] ;
  input gt_cpllpdrefclk;
  input \resetovrd_disble.reset_reg[4] ;
  input \fsm_reg[2] ;
  input \fsm_reg[0] ;
  input USER_EYESCANRESET;
  input sys_clk;
  input rst_gtreset;
  input [0:0]pci_exp_rxn;
  input [0:0]pci_exp_rxp;
  input qpllpd_reg;
  input qpllpd_reg_0;
  input \resetovrd_disble.fsm_reg[1] ;
  input gen3_reg;
  input USER_RXBUFRESET;
  input USER_RXCDRFREQRESET;
  input USER_RXCDRRESET;
  input gen3_reg_0;
  input GT_RX_CONVERGE0;
  input USER_RXDFELPMRESET;
  input SYNC_RXSYNC_DONE;
  input \rxsync_fsm_disable.fsm_rx_reg[2] ;
  input USER_RXPCSRESET;
  input rxsync_donem_reg2_reg;
  input GT_RXPMARESET061_out;
  input [0:0]PIPE_RXPOLARITY;
  input userrdy_reg_rep__1;
  input pclk_sel_reg;
  input [0:0]PIPE_TXDEEMPH;
  input PIPE_TXDETECTRX;
  input \txsync_fsm.txdlyen_reg ;
  input \txsync_fsm.fsm_tx_reg[2] ;
  input [0:0]PIPE_TXELECIDLE;
  input [0:0]pipe_txinhibit;
  input \txsync_fsm.fsm_tx_reg[4] ;
  input \txsync_fsm.fsm_tx_reg[4]_0 ;
  input GT_TXPMARESET064_out;
  input [15:0]DRPDI;
  input [1:0]PIPE_POWERDOWN;
  input [1:0]RXSYSCLKSEL;
  input [2:0]RXRATE;
  input [2:0]PIPE_TXMARGIN;
  input USER_OOBCLK;
  input [4:0]RXCHBONDO;
  input [4:0]TXPOSTCURSOR;
  input [4:0]TXPRECURSOR;
  input [15:0]PIPE_TXDATA;
  input [6:0]TXMAINCURSOR;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [1:0]PIPE_TXDATAK;
  input [8:0]DRPADDR;
  input [1:0]Q;
  input \pl_ltssm_state_q_reg[4] ;
  input gt_rxvalid_q_reg;
  input rst_cpllpd;
  input p_0_in67_in;
  input RST_CPLLRESET;
  input p_0_in65_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire GT_RXPMARESET061_out;
  wire GT_RX_CONVERGE0;
  wire GT_TXPMARESET064_out;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXDEEMPH;
  wire PIPE_TXDETECTRX;
  wire [0:0]PIPE_TXELECIDLE;
  wire [2:0]PIPE_TXMARGIN;
  wire [1:0]Q;
  wire RATE_CPLLLOCK;
  wire RATE_PHYSTATUS;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RST_CPLLRESET;
  wire [4:0]RXCHBONDO;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_EYESCANRESET;
  wire USER_OOBCLK;
  wire USER_RXBUFRESET;
  wire USER_RXCDRFREQRESET;
  wire USER_RXCDRRESET;
  wire USER_RXDFELPMRESET;
  wire USER_RXPCSRESET;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drprdy;
  wire \fsm_reg[0] ;
  wire \fsm_reg[2] ;
  wire gen3_reg;
  wire gen3_reg_0;
  wire gt_cpllpdrefclk;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxvalid_q_reg;
  wire \gtx_channel.gtxe2_channel_i_n_10 ;
  wire \gtx_channel.gtxe2_channel_i_n_138 ;
  wire \gtx_channel.gtxe2_channel_i_n_139 ;
  wire \gtx_channel.gtxe2_channel_i_n_140 ;
  wire \gtx_channel.gtxe2_channel_i_n_141 ;
  wire \gtx_channel.gtxe2_channel_i_n_142 ;
  wire \gtx_channel.gtxe2_channel_i_n_143 ;
  wire \gtx_channel.gtxe2_channel_i_n_144 ;
  wire \gtx_channel.gtxe2_channel_i_n_145 ;
  wire \gtx_channel.gtxe2_channel_i_n_146 ;
  wire \gtx_channel.gtxe2_channel_i_n_147 ;
  wire \gtx_channel.gtxe2_channel_i_n_148 ;
  wire \gtx_channel.gtxe2_channel_i_n_149 ;
  wire \gtx_channel.gtxe2_channel_i_n_150 ;
  wire \gtx_channel.gtxe2_channel_i_n_151 ;
  wire \gtx_channel.gtxe2_channel_i_n_152 ;
  wire \gtx_channel.gtxe2_channel_i_n_153 ;
  wire \gtx_channel.gtxe2_channel_i_n_189 ;
  wire \gtx_channel.gtxe2_channel_i_n_190 ;
  wire \gtx_channel.gtxe2_channel_i_n_191 ;
  wire \gtx_channel.gtxe2_channel_i_n_192 ;
  wire \gtx_channel.gtxe2_channel_i_n_197 ;
  wire \gtx_channel.gtxe2_channel_i_n_198 ;
  wire \gtx_channel.gtxe2_channel_i_n_37 ;
  wire \gtx_channel.gtxe2_channel_i_n_9 ;
  wire \gtx_channel.gtxe2_channel_i_n_91 ;
  wire \gtx_channel.gtxe2_channel_i_n_92 ;
  wire \gtx_channel.gtxe2_channel_i_n_93 ;
  wire \gtx_channel.gtxe2_channel_i_n_94 ;
  wire \gtx_channel.gtxe2_channel_i_n_95 ;
  wire p_0_in65_in;
  wire p_0_in67_in;
  wire [0:0]pci_exp_rxn;
  wire [0:0]pci_exp_rxp;
  wire [0:0]pci_exp_txn;
  wire [0:0]pci_exp_txp;
  wire pclk_sel_reg;
  wire [7:0]pipe_dmonitorout;
  wire [0:0]pipe_eyescandataerror;
  wire [2:0]pipe_rxbufstatus;
  wire [0:0]pipe_rxcommadet;
  wire [7:0]pipe_rxdisperr;
  wire [0:0]pipe_rxdlysresetdone;
  wire [7:0]pipe_rxnotintable;
  wire [0:0]pipe_rxoutclk_out;
  wire [0:0]pipe_rxphaligndone;
  wire [0:0]pipe_rxprbserr;
  wire [2:0]pipe_rxstatus;
  wire [0:0]pipe_txdlysresetdone;
  wire [0:0]pipe_txinhibit;
  wire [0:0]pipe_txphaligndone;
  wire [0:0]pipe_txphinitdone;
  wire \pl_ltssm_state_q_reg[4] ;
  wire qpllpd_reg;
  wire qpllpd_reg_0;
  wire \resetovrd_disble.fsm_reg[1] ;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_cpllpd;
  wire rst_gtreset;
  wire rxcdrlock_reg1_reg;
  wire rxsync_donem_reg2_reg;
  wire \rxsync_fsm_disable.fsm_rx_reg[2] ;
  wire rxvalid_reg1_reg;
  wire sys_clk;
  wire \txsync_fsm.fsm_tx_reg[2] ;
  wire \txsync_fsm.fsm_tx_reg[4] ;
  wire \txsync_fsm.fsm_tx_reg[4]_0 ;
  wire \txsync_fsm.txdlyen_reg ;
  wire userrdy_reg_rep__1;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
  wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
  wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
  wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
  wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
  wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;

  PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_77 cpllPDInst
       (.CPLLPD0(CPLLPD0),
        .CPLLRESET0(CPLLRESET0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .p_0_in65_in(p_0_in65_in),
        .p_0_in67_in(p_0_in67_in),
        .rst_cpllpd(rst_cpllpd));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[0]_i_1__2 
       (.I0(pipe_rxstatus[0]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [0]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[1]_i_1__2 
       (.I0(pipe_rxstatus[1]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [1]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[2]_i_1__2 
       (.I0(pipe_rxstatus[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [2]));
  (* box_type = "PRIMITIVE" *) 
  GTXE2_CHANNEL #(
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(1),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CHAN_BOND_KEEP_ALIGN("TRUE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0001001010),
    .CHAN_BOND_SEQ_1_2(10'b0001001010),
    .CHAN_BOND_SEQ_1_3(10'b0001001010),
    .CHAN_BOND_SEQ_1_4(10'b0110111100),
    .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_1(10'b0001000101),
    .CHAN_BOND_SEQ_2_2(10'b0001000101),
    .CHAN_BOND_SEQ_2_3(10'b0001000101),
    .CHAN_BOND_SEQ_2_4(10'b0110111100),
    .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_USE("TRUE"),
    .CHAN_BOND_SEQ_LEN(4),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("TRUE"),
    .CLK_COR_MAX_LAT(20),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0100011100),
    .CLK_COR_SEQ_1_2(10'b0000000000),
    .CLK_COR_SEQ_1_3(10'b0000000000),
    .CLK_COR_SEQ_1_4(10'b0000000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0000000000),
    .CLK_COR_SEQ_2_2(10'b0000000000),
    .CLK_COR_SEQ_2_3(10'b0000000000),
    .CLK_COR_SEQ_2_4(10'b0000000000),
    .CLK_COR_SEQ_2_ENABLE(4'b0000),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(1),
    .CPLL_CFG(24'hA407CC),
    .CPLL_FBDIV(5),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000B01),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("FALSE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("TRUE"),
    .GEARBOX_MODE(3'b000),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("TRUE"),
    .PCS_RSVD_ATTR(48'h0000000001CF),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h09),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'h00018480),
    .PMA_RSV2(16'h2050),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(32'h00000000),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b0100),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("TRUE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(72'h03000023FF10200020),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b1),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00000011110000),
    .RXLPM_LF_CFG(14'b00000011110000),
    .RXOOB_CFG(7'b0000110),
    .RXOUT_DIV(2),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h004020),
    .RXPH_CFG(24'h000000),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("PMA"),
    .RX_BIAS_CFG(12'b000000000100),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(4),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(3'b010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(12'b000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFE_GAIN_CFG(23'h020FEA),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011110000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_KL_CFG(13'b0000011111110),
    .RX_DFE_KL_CFG2(32'h3290D86C),
    .RX_DFE_LPM_CFG(16'h0954),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
    .RX_DFE_UT_CFG(17'b10001111000000000),
    .RX_DFE_VP_CFG(17'b00011111100000011),
    .RX_DFE_XYD_CFG(13'b0000000000000),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(4),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b1111),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("FALSE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
    .SIM_VERSION("3.0"),
    .TERM_RCAL_CFG(5'b10000),
    .TERM_RCAL_OVRD(1'b0),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("FALSE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOUT_DIV(2),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPMARESET_TIME(5'b00011),
    .TX_CLK25_DIV(4),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(5'b10100),
    .TX_DEEMPH1(5'b01011),
    .TX_DRIVE_MODE("PIPE"),
    .TX_EIDLE_ASSERT_DELAY(3'b010),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001111),
    .TX_MARGIN_FULL_1(7'b1001110),
    .TX_MARGIN_FULL_2(7'b1001101),
    .TX_MARGIN_FULL_3(7'b1001100),
    .TX_MARGIN_FULL_4(7'b1000011),
    .TX_MARGIN_LOW_0(7'b1000101),
    .TX_MARGIN_LOW_1(7'b1000110),
    .TX_MARGIN_LOW_2(7'b1000011),
    .TX_MARGIN_LOW_3(7'b1000010),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_PREDRIVER_MODE(1'b0),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h0064),
    .TX_RXDETECT_REF(3'b011),
    .TX_XCLK_SEL("TXUSR"),
    .UCODEER_CLR(1'b0)) 
    \gtx_channel.gtxe2_channel_i 
       (.CFGRESET(1'b0),
        .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
        .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
        .CPLLLOCK(RATE_CPLLLOCK),
        .CPLLLOCKDETCLK(1'b0),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD0),
        .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET0),
        .DMONITOROUT(pipe_dmonitorout),
        .DRPADDR(DRPADDR),
        .DRPCLK(\resetovrd_disble.reset_reg[4] ),
        .DRPDI(DRPDI),
        .DRPDO(ext_ch_gt_drpdo),
        .DRPEN(\fsm_reg[2] ),
        .DRPRDY(ext_ch_gt_drprdy),
        .DRPWE(\fsm_reg[0] ),
        .EYESCANDATAERROR(pipe_eyescandataerror),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(USER_EYESCANRESET),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(rst_gtreset),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(rst_gtreset),
        .GTXRXN(pci_exp_rxn),
        .GTXRXP(pci_exp_rxp),
        .GTXTXN(pci_exp_txn),
        .GTXTXP(pci_exp_txp),
        .LOOPBACK({1'b0,1'b0,1'b0}),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
        .PHYSTATUS(RATE_PHYSTATUS),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(qpllpd_reg),
        .QPLLREFCLK(qpllpd_reg_0),
        .RESETOVRD(\resetovrd_disble.fsm_reg[1] ),
        .RX8B10BEN(gen3_reg),
        .RXBUFRESET(USER_RXBUFRESET),
        .RXBUFSTATUS(pipe_rxbufstatus),
        .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
        .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
        .RXCDRFREQRESET(USER_RXCDRFREQRESET),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(rxcdrlock_reg1_reg),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(USER_RXCDRRESET),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
        .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
        .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
        .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
        .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,\gt_rxcharisk_q_reg[1] }),
        .RXCHBONDEN(gen3_reg),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }),
        .RXCHBONDSLAVE(gen3_reg_0),
        .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
        .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
        .RXCOMMADET(pipe_rxcommadet),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
        .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
        .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,\gt_rxdata_q_reg[15] }),
        .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(GT_RX_CONVERGE0),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b1),
        .RXDFELPMRESET(USER_RXDFELPMRESET),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b0),
        .RXDFEXYDHOLD(1'b0),
        .RXDFEXYDOVRDEN(1'b0),
        .RXDISPERR(pipe_rxdisperr),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(SYNC_RXSYNC_DONE),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(\rxsync_fsm_disable.fsm_rx_reg[2] ),
        .RXDLYSRESETDONE(pipe_rxdlysresetdone),
        .RXELECIDLE(gt_rx_elec_idle_wire_filter),
        .RXELECIDLEMODE({1'b0,1'b0}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
        .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
        .RXLPMEN(gen3_reg_0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(gen3_reg),
        .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE(pipe_rxnotintable),
        .RXOOBRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(pipe_rxoutclk_out),
        .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
        .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
        .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .RXPCOMMAALIGNEN(gen3_reg_0),
        .RXPCSRESET(USER_RXPCSRESET),
        .RXPD(PIPE_POWERDOWN),
        .RXPHALIGN(rxsync_donem_reg2_reg),
        .RXPHALIGNDONE(pipe_rxphaligndone),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
        .RXPMARESET(GT_RXPMARESET061_out),
        .RXPOLARITY(PIPE_RXPOLARITY),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(pipe_rxprbserr),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
        .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
        .RXRATE(RXRATE),
        .RXRATEDONE(RATE_RXRATEDONE),
        .RXRESETDONE(USER_RXRESETDONE),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
        .RXSTATUS(pipe_rxstatus),
        .RXSYSCLKSEL(RXSYSCLKSEL),
        .RXUSERRDY(userrdy_reg_rep__1),
        .RXUSRCLK(pclk_sel_reg),
        .RXUSRCLK2(pclk_sel_reg),
        .RXVALID(rxvalid_reg1_reg),
        .SETERRSTATUS(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(gen3_reg_0),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
        .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
        .TXDEEMPH(PIPE_TXDEEMPH),
        .TXDETECTRX(PIPE_TXDETECTRX),
        .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b0),
        .TXDLYEN(\txsync_fsm.txdlyen_reg ),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(\txsync_fsm.fsm_tx_reg[2] ),
        .TXDLYSRESETDONE(pipe_txdlysresetdone),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(PIPE_TXELECIDLE),
        .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(pipe_txinhibit),
        .TXMAINCURSOR(TXMAINCURSOR),
        .TXMARGIN(PIPE_TXMARGIN),
        .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ),
        .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
        .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
        .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD(PIPE_POWERDOWN),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(\txsync_fsm.fsm_tx_reg[4] ),
        .TXPHALIGNDONE(pipe_txphaligndone),
        .TXPHALIGNEN(1'b1),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(\txsync_fsm.fsm_tx_reg[4]_0 ),
        .TXPHINITDONE(pipe_txphinitdone),
        .TXPHOVRDEN(1'b0),
        .TXPISOPD(1'b0),
        .TXPMARESET(GT_TXPMARESET064_out),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR(TXPOSTCURSOR),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR(TXPRECURSOR),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
        .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE(RXRATE),
        .TXRATEDONE(RATE_TXRATEDONE),
        .TXRESETDONE(USER_TXRESETDONE),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYSCLKSEL(RXSYSCLKSEL),
        .TXUSERRDY(userrdy_reg_rep__1),
        .TXUSRCLK(pclk_sel_reg),
        .TXUSRCLK2(pclk_sel_reg));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_54
   (RATE_CPLLLOCK,
    ext_ch_gt_drprdy,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    RATE_PHYSTATUS,
    rxcdrlock_reg1_reg,
    PIPE_RXCHANISALIGNED,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    gt_rx_elec_idle_wire_filter,
    pipe_rxoutclk_out,
    pipe_rxphaligndone,
    pipe_rxprbserr,
    RATE_RXRATEDONE,
    USER_RXRESETDONE,
    rxvalid_reg1_reg,
    pipe_txdlysresetdone,
    pipe_txphaligndone,
    pipe_txphinitdone,
    RATE_TXRATEDONE,
    USER_TXRESETDONE,
    ext_ch_gt_drpdo,
    pipe_rxbufstatus,
    pipe_rxstatus,
    \gt_rxdata_q_reg[15] ,
    pipe_dmonitorout,
    \gt_rxcharisk_q_reg[1] ,
    pipe_rxdisperr,
    pipe_rxnotintable,
    \gt_rx_status_q_reg[2] ,
    gt_cpllpdrefclk,
    \resetovrd_disble.reset_reg[4] ,
    \fsm_reg[2] ,
    \fsm_reg[0] ,
    USER_EYESCANRESET,
    sys_clk,
    rst_gtreset,
    pci_exp_rxn,
    pci_exp_rxp,
    qpllpd_reg,
    qpllpd_reg_0,
    \resetovrd_disble.fsm_reg[1] ,
    gen3_reg,
    USER_RXBUFRESET,
    USER_RXCDRFREQRESET,
    USER_RXCDRRESET,
    gen3_reg_0,
    converge_gen3_reg,
    USER_RXDFELPMRESET,
    SYNC_RXSYNC_DONE,
    \rxsync_fsm_disable.fsm_rx_reg[2] ,
    USER_RXPCSRESET,
    rxsync_donem_reg2_reg,
    GT_RXPMARESET043_out,
    PIPE_RXPOLARITY,
    userrdy_reg_rep__0,
    pclk_sel_reg,
    PIPE_TXDEEMPH,
    pipe_tx_rcvr_det,
    \txsync_fsm.txdlyen_reg ,
    \txsync_fsm.fsm_tx_reg[2] ,
    PIPE_TXELECIDLE,
    pipe_txinhibit,
    \txsync_fsm.fsm_tx_reg[4] ,
    \txsync_fsm.fsm_tx_reg[4]_0 ,
    GT_TXPMARESET046_out,
    DRPDI,
    PIPE_POWERDOWN,
    RXSYSCLKSEL,
    RXRATE,
    \pipe_stages_1.pipe_tx_margin_q_reg[2] ,
    USER_OOBCLK,
    RXCHBONDO,
    TXPOSTCURSOR,
    TXPRECURSOR,
    PIPE_TXDATA,
    TXMAINCURSOR,
    PIPE_TXCOMPLIANCE,
    PIPE_TXDATAK,
    DRPADDR,
    Q,
    \pl_ltssm_state_q_reg[4] ,
    gt_rxvalid_q_reg,
    rst_cpllpd,
    p_0_in49_in,
    RST_CPLLRESET,
    p_0_in47_in);
  output RATE_CPLLLOCK;
  output [0:0]ext_ch_gt_drprdy;
  output [0:0]pipe_eyescandataerror;
  output [0:0]pci_exp_txn;
  output [0:0]pci_exp_txp;
  output RATE_PHYSTATUS;
  output rxcdrlock_reg1_reg;
  output [0:0]PIPE_RXCHANISALIGNED;
  output [0:0]pipe_rxcommadet;
  output [0:0]pipe_rxdlysresetdone;
  output [0:0]gt_rx_elec_idle_wire_filter;
  output [0:0]pipe_rxoutclk_out;
  output [0:0]pipe_rxphaligndone;
  output [0:0]pipe_rxprbserr;
  output RATE_RXRATEDONE;
  output USER_RXRESETDONE;
  output rxvalid_reg1_reg;
  output [0:0]pipe_txdlysresetdone;
  output [0:0]pipe_txphaligndone;
  output [0:0]pipe_txphinitdone;
  output RATE_TXRATEDONE;
  output USER_TXRESETDONE;
  output [15:0]ext_ch_gt_drpdo;
  output [2:0]pipe_rxbufstatus;
  output [2:0]pipe_rxstatus;
  output [15:0]\gt_rxdata_q_reg[15] ;
  output [7:0]pipe_dmonitorout;
  output [1:0]\gt_rxcharisk_q_reg[1] ;
  output [7:0]pipe_rxdisperr;
  output [7:0]pipe_rxnotintable;
  output [2:0]\gt_rx_status_q_reg[2] ;
  input gt_cpllpdrefclk;
  input \resetovrd_disble.reset_reg[4] ;
  input \fsm_reg[2] ;
  input \fsm_reg[0] ;
  input USER_EYESCANRESET;
  input sys_clk;
  input rst_gtreset;
  input [0:0]pci_exp_rxn;
  input [0:0]pci_exp_rxp;
  input qpllpd_reg;
  input qpllpd_reg_0;
  input \resetovrd_disble.fsm_reg[1] ;
  input gen3_reg;
  input USER_RXBUFRESET;
  input USER_RXCDRFREQRESET;
  input USER_RXCDRRESET;
  input gen3_reg_0;
  input converge_gen3_reg;
  input USER_RXDFELPMRESET;
  input SYNC_RXSYNC_DONE;
  input \rxsync_fsm_disable.fsm_rx_reg[2] ;
  input USER_RXPCSRESET;
  input rxsync_donem_reg2_reg;
  input GT_RXPMARESET043_out;
  input [0:0]PIPE_RXPOLARITY;
  input userrdy_reg_rep__0;
  input pclk_sel_reg;
  input [0:0]PIPE_TXDEEMPH;
  input pipe_tx_rcvr_det;
  input \txsync_fsm.txdlyen_reg ;
  input \txsync_fsm.fsm_tx_reg[2] ;
  input [0:0]PIPE_TXELECIDLE;
  input [0:0]pipe_txinhibit;
  input \txsync_fsm.fsm_tx_reg[4] ;
  input \txsync_fsm.fsm_tx_reg[4]_0 ;
  input GT_TXPMARESET046_out;
  input [15:0]DRPDI;
  input [1:0]PIPE_POWERDOWN;
  input [1:0]RXSYSCLKSEL;
  input [2:0]RXRATE;
  input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  input USER_OOBCLK;
  input [4:0]RXCHBONDO;
  input [4:0]TXPOSTCURSOR;
  input [4:0]TXPRECURSOR;
  input [15:0]PIPE_TXDATA;
  input [6:0]TXMAINCURSOR;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [1:0]PIPE_TXDATAK;
  input [8:0]DRPADDR;
  input [1:0]Q;
  input \pl_ltssm_state_q_reg[4] ;
  input gt_rxvalid_q_reg;
  input rst_cpllpd;
  input p_0_in49_in;
  input RST_CPLLRESET;
  input p_0_in47_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire GT_RXPMARESET043_out;
  wire GT_TXPMARESET046_out;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXDEEMPH;
  wire [0:0]PIPE_TXELECIDLE;
  wire [1:0]Q;
  wire RATE_CPLLLOCK;
  wire RATE_PHYSTATUS;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RST_CPLLRESET;
  wire [4:0]RXCHBONDO;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_EYESCANRESET;
  wire USER_OOBCLK;
  wire USER_RXBUFRESET;
  wire USER_RXCDRFREQRESET;
  wire USER_RXCDRRESET;
  wire USER_RXDFELPMRESET;
  wire USER_RXPCSRESET;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire converge_gen3_reg;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drprdy;
  wire \fsm_reg[0] ;
  wire \fsm_reg[2] ;
  wire gen3_reg;
  wire gen3_reg_0;
  wire gt_cpllpdrefclk;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxvalid_q_reg;
  wire \gtx_channel.gtxe2_channel_i_n_10 ;
  wire \gtx_channel.gtxe2_channel_i_n_138 ;
  wire \gtx_channel.gtxe2_channel_i_n_139 ;
  wire \gtx_channel.gtxe2_channel_i_n_140 ;
  wire \gtx_channel.gtxe2_channel_i_n_141 ;
  wire \gtx_channel.gtxe2_channel_i_n_142 ;
  wire \gtx_channel.gtxe2_channel_i_n_143 ;
  wire \gtx_channel.gtxe2_channel_i_n_144 ;
  wire \gtx_channel.gtxe2_channel_i_n_145 ;
  wire \gtx_channel.gtxe2_channel_i_n_146 ;
  wire \gtx_channel.gtxe2_channel_i_n_147 ;
  wire \gtx_channel.gtxe2_channel_i_n_148 ;
  wire \gtx_channel.gtxe2_channel_i_n_149 ;
  wire \gtx_channel.gtxe2_channel_i_n_150 ;
  wire \gtx_channel.gtxe2_channel_i_n_151 ;
  wire \gtx_channel.gtxe2_channel_i_n_152 ;
  wire \gtx_channel.gtxe2_channel_i_n_153 ;
  wire \gtx_channel.gtxe2_channel_i_n_189 ;
  wire \gtx_channel.gtxe2_channel_i_n_190 ;
  wire \gtx_channel.gtxe2_channel_i_n_191 ;
  wire \gtx_channel.gtxe2_channel_i_n_192 ;
  wire \gtx_channel.gtxe2_channel_i_n_197 ;
  wire \gtx_channel.gtxe2_channel_i_n_198 ;
  wire \gtx_channel.gtxe2_channel_i_n_37 ;
  wire \gtx_channel.gtxe2_channel_i_n_9 ;
  wire \gtx_channel.gtxe2_channel_i_n_91 ;
  wire \gtx_channel.gtxe2_channel_i_n_92 ;
  wire \gtx_channel.gtxe2_channel_i_n_93 ;
  wire \gtx_channel.gtxe2_channel_i_n_94 ;
  wire \gtx_channel.gtxe2_channel_i_n_95 ;
  wire p_0_in47_in;
  wire p_0_in49_in;
  wire [0:0]pci_exp_rxn;
  wire [0:0]pci_exp_rxp;
  wire [0:0]pci_exp_txn;
  wire [0:0]pci_exp_txp;
  wire pclk_sel_reg;
  wire [7:0]pipe_dmonitorout;
  wire [0:0]pipe_eyescandataerror;
  wire [2:0]pipe_rxbufstatus;
  wire [0:0]pipe_rxcommadet;
  wire [7:0]pipe_rxdisperr;
  wire [0:0]pipe_rxdlysresetdone;
  wire [7:0]pipe_rxnotintable;
  wire [0:0]pipe_rxoutclk_out;
  wire [0:0]pipe_rxphaligndone;
  wire [0:0]pipe_rxprbserr;
  wire [2:0]pipe_rxstatus;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  wire pipe_tx_rcvr_det;
  wire [0:0]pipe_txdlysresetdone;
  wire [0:0]pipe_txinhibit;
  wire [0:0]pipe_txphaligndone;
  wire [0:0]pipe_txphinitdone;
  wire \pl_ltssm_state_q_reg[4] ;
  wire qpllpd_reg;
  wire qpllpd_reg_0;
  wire \resetovrd_disble.fsm_reg[1] ;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_cpllpd;
  wire rst_gtreset;
  wire rxcdrlock_reg1_reg;
  wire rxsync_donem_reg2_reg;
  wire \rxsync_fsm_disable.fsm_rx_reg[2] ;
  wire rxvalid_reg1_reg;
  wire sys_clk;
  wire \txsync_fsm.fsm_tx_reg[2] ;
  wire \txsync_fsm.fsm_tx_reg[4] ;
  wire \txsync_fsm.fsm_tx_reg[4]_0 ;
  wire \txsync_fsm.txdlyen_reg ;
  wire userrdy_reg_rep__0;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
  wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
  wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
  wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
  wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
  wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;

  PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_75 cpllPDInst
       (.CPLLPD0(CPLLPD0),
        .CPLLRESET0(CPLLRESET0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .p_0_in47_in(p_0_in47_in),
        .p_0_in49_in(p_0_in49_in),
        .rst_cpllpd(rst_cpllpd));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[0]_i_1__1 
       (.I0(pipe_rxstatus[0]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [0]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[1]_i_1__1 
       (.I0(pipe_rxstatus[1]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [1]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[2]_i_1__1 
       (.I0(pipe_rxstatus[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [2]));
  (* box_type = "PRIMITIVE" *) 
  GTXE2_CHANNEL #(
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(1),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CHAN_BOND_KEEP_ALIGN("TRUE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0001001010),
    .CHAN_BOND_SEQ_1_2(10'b0001001010),
    .CHAN_BOND_SEQ_1_3(10'b0001001010),
    .CHAN_BOND_SEQ_1_4(10'b0110111100),
    .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_1(10'b0001000101),
    .CHAN_BOND_SEQ_2_2(10'b0001000101),
    .CHAN_BOND_SEQ_2_3(10'b0001000101),
    .CHAN_BOND_SEQ_2_4(10'b0110111100),
    .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_USE("TRUE"),
    .CHAN_BOND_SEQ_LEN(4),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("TRUE"),
    .CLK_COR_MAX_LAT(20),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0100011100),
    .CLK_COR_SEQ_1_2(10'b0000000000),
    .CLK_COR_SEQ_1_3(10'b0000000000),
    .CLK_COR_SEQ_1_4(10'b0000000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0000000000),
    .CLK_COR_SEQ_2_2(10'b0000000000),
    .CLK_COR_SEQ_2_3(10'b0000000000),
    .CLK_COR_SEQ_2_4(10'b0000000000),
    .CLK_COR_SEQ_2_ENABLE(4'b0000),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(1),
    .CPLL_CFG(24'hA407CC),
    .CPLL_FBDIV(5),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000B01),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("FALSE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("TRUE"),
    .GEARBOX_MODE(3'b000),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("TRUE"),
    .PCS_RSVD_ATTR(48'h0000000001CF),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h09),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'h00018480),
    .PMA_RSV2(16'h2050),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(32'h00000000),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b0100),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("TRUE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(72'h03000023FF10200020),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b1),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00000011110000),
    .RXLPM_LF_CFG(14'b00000011110000),
    .RXOOB_CFG(7'b0000110),
    .RXOUT_DIV(2),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h004020),
    .RXPH_CFG(24'h000000),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("PMA"),
    .RX_BIAS_CFG(12'b000000000100),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(4),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(3'b010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(12'b000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFE_GAIN_CFG(23'h020FEA),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011110000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_KL_CFG(13'b0000011111110),
    .RX_DFE_KL_CFG2(32'h3290D86C),
    .RX_DFE_LPM_CFG(16'h0954),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
    .RX_DFE_UT_CFG(17'b10001111000000000),
    .RX_DFE_VP_CFG(17'b00011111100000011),
    .RX_DFE_XYD_CFG(13'b0000000000000),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(4),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b1111),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("FALSE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
    .SIM_VERSION("3.0"),
    .TERM_RCAL_CFG(5'b10000),
    .TERM_RCAL_OVRD(1'b0),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("FALSE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOUT_DIV(2),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPMARESET_TIME(5'b00011),
    .TX_CLK25_DIV(4),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(5'b10100),
    .TX_DEEMPH1(5'b01011),
    .TX_DRIVE_MODE("PIPE"),
    .TX_EIDLE_ASSERT_DELAY(3'b010),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001111),
    .TX_MARGIN_FULL_1(7'b1001110),
    .TX_MARGIN_FULL_2(7'b1001101),
    .TX_MARGIN_FULL_3(7'b1001100),
    .TX_MARGIN_FULL_4(7'b1000011),
    .TX_MARGIN_LOW_0(7'b1000101),
    .TX_MARGIN_LOW_1(7'b1000110),
    .TX_MARGIN_LOW_2(7'b1000011),
    .TX_MARGIN_LOW_3(7'b1000010),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_PREDRIVER_MODE(1'b0),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h0064),
    .TX_RXDETECT_REF(3'b011),
    .TX_XCLK_SEL("TXUSR"),
    .UCODEER_CLR(1'b0)) 
    \gtx_channel.gtxe2_channel_i 
       (.CFGRESET(1'b0),
        .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
        .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
        .CPLLLOCK(RATE_CPLLLOCK),
        .CPLLLOCKDETCLK(1'b0),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD0),
        .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET0),
        .DMONITOROUT(pipe_dmonitorout),
        .DRPADDR(DRPADDR),
        .DRPCLK(\resetovrd_disble.reset_reg[4] ),
        .DRPDI(DRPDI),
        .DRPDO(ext_ch_gt_drpdo),
        .DRPEN(\fsm_reg[2] ),
        .DRPRDY(ext_ch_gt_drprdy),
        .DRPWE(\fsm_reg[0] ),
        .EYESCANDATAERROR(pipe_eyescandataerror),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(USER_EYESCANRESET),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(rst_gtreset),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(rst_gtreset),
        .GTXRXN(pci_exp_rxn),
        .GTXRXP(pci_exp_rxp),
        .GTXTXN(pci_exp_txn),
        .GTXTXP(pci_exp_txp),
        .LOOPBACK({1'b0,1'b0,1'b0}),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
        .PHYSTATUS(RATE_PHYSTATUS),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(qpllpd_reg),
        .QPLLREFCLK(qpllpd_reg_0),
        .RESETOVRD(\resetovrd_disble.fsm_reg[1] ),
        .RX8B10BEN(gen3_reg),
        .RXBUFRESET(USER_RXBUFRESET),
        .RXBUFSTATUS(pipe_rxbufstatus),
        .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
        .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
        .RXCDRFREQRESET(USER_RXCDRFREQRESET),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(rxcdrlock_reg1_reg),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(USER_RXCDRRESET),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
        .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
        .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
        .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
        .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,\gt_rxcharisk_q_reg[1] }),
        .RXCHBONDEN(gen3_reg),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }),
        .RXCHBONDSLAVE(gen3_reg_0),
        .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
        .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
        .RXCOMMADET(pipe_rxcommadet),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
        .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
        .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,\gt_rxdata_q_reg[15] }),
        .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(converge_gen3_reg),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b1),
        .RXDFELPMRESET(USER_RXDFELPMRESET),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b0),
        .RXDFEXYDHOLD(1'b0),
        .RXDFEXYDOVRDEN(1'b0),
        .RXDISPERR(pipe_rxdisperr),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(SYNC_RXSYNC_DONE),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(\rxsync_fsm_disable.fsm_rx_reg[2] ),
        .RXDLYSRESETDONE(pipe_rxdlysresetdone),
        .RXELECIDLE(gt_rx_elec_idle_wire_filter),
        .RXELECIDLEMODE({1'b0,1'b0}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
        .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
        .RXLPMEN(gen3_reg_0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(gen3_reg),
        .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE(pipe_rxnotintable),
        .RXOOBRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(pipe_rxoutclk_out),
        .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
        .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
        .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .RXPCOMMAALIGNEN(gen3_reg_0),
        .RXPCSRESET(USER_RXPCSRESET),
        .RXPD(PIPE_POWERDOWN),
        .RXPHALIGN(rxsync_donem_reg2_reg),
        .RXPHALIGNDONE(pipe_rxphaligndone),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
        .RXPMARESET(GT_RXPMARESET043_out),
        .RXPOLARITY(PIPE_RXPOLARITY),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(pipe_rxprbserr),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
        .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
        .RXRATE(RXRATE),
        .RXRATEDONE(RATE_RXRATEDONE),
        .RXRESETDONE(USER_RXRESETDONE),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
        .RXSTATUS(pipe_rxstatus),
        .RXSYSCLKSEL(RXSYSCLKSEL),
        .RXUSERRDY(userrdy_reg_rep__0),
        .RXUSRCLK(pclk_sel_reg),
        .RXUSRCLK2(pclk_sel_reg),
        .RXVALID(rxvalid_reg1_reg),
        .SETERRSTATUS(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(gen3_reg_0),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
        .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
        .TXDEEMPH(PIPE_TXDEEMPH),
        .TXDETECTRX(pipe_tx_rcvr_det),
        .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b0),
        .TXDLYEN(\txsync_fsm.txdlyen_reg ),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(\txsync_fsm.fsm_tx_reg[2] ),
        .TXDLYSRESETDONE(pipe_txdlysresetdone),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(PIPE_TXELECIDLE),
        .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(pipe_txinhibit),
        .TXMAINCURSOR(TXMAINCURSOR),
        .TXMARGIN(\pipe_stages_1.pipe_tx_margin_q_reg[2] ),
        .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ),
        .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
        .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
        .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD(PIPE_POWERDOWN),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(\txsync_fsm.fsm_tx_reg[4] ),
        .TXPHALIGNDONE(pipe_txphaligndone),
        .TXPHALIGNEN(1'b1),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(\txsync_fsm.fsm_tx_reg[4]_0 ),
        .TXPHINITDONE(pipe_txphinitdone),
        .TXPHOVRDEN(1'b0),
        .TXPISOPD(1'b0),
        .TXPMARESET(GT_TXPMARESET046_out),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR(TXPOSTCURSOR),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR(TXPRECURSOR),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
        .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE(RXRATE),
        .TXRATEDONE(RATE_TXRATEDONE),
        .TXRESETDONE(USER_TXRESETDONE),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYSCLKSEL(RXSYSCLKSEL),
        .TXUSERRDY(userrdy_reg_rep__0),
        .TXUSRCLK(pclk_sel_reg),
        .TXUSRCLK2(pclk_sel_reg));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_60
   (RATE_CPLLLOCK,
    ext_ch_gt_drprdy,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    RATE_PHYSTATUS,
    rxcdrlock_reg1_reg,
    PIPE_RXCHANISALIGNED,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    gt_rx_elec_idle_wire_filter,
    pipe_rxoutclk_out,
    pipe_rxphaligndone,
    pipe_rxprbserr,
    RATE_RXRATEDONE,
    USER_RXRESETDONE,
    rxvalid_reg1_reg,
    pipe_txdlysresetdone,
    pipe_txphaligndone,
    pipe_txphinitdone,
    RATE_TXRATEDONE,
    USER_TXRESETDONE,
    ext_ch_gt_drpdo,
    pipe_rxbufstatus,
    pipe_rxstatus,
    \gt_rxdata_q_reg[15] ,
    pipe_dmonitorout,
    \gt_rxcharisk_q_reg[1] ,
    pipe_rxdisperr,
    pipe_rxnotintable,
    \gt_rx_status_q_reg[2] ,
    SYNC_TXDLYSRESETDONE0,
    SYNC_RXDLYSRESETDONE0,
    gt_cpllpdrefclk,
    \resetovrd_disble.reset_reg[4] ,
    \fsm_reg[2] ,
    \fsm_reg[0] ,
    USER_EYESCANRESET,
    sys_clk,
    rst_gtreset,
    pci_exp_rxn,
    pci_exp_rxp,
    qpllpd_reg,
    qpllpd_reg_0,
    \resetovrd_disble.fsm_reg[1] ,
    gen3_reg,
    USER_RXBUFRESET,
    USER_RXCDRFREQRESET,
    USER_RXCDRRESET,
    gen3_reg_0,
    GT_RX_CONVERGE0,
    USER_RXDFELPMRESET,
    SYNC_RXSYNC_DONE,
    \rxsync_fsm_disable.fsm_rx_reg[2] ,
    USER_RXPCSRESET,
    rxsync_donem_reg2_reg,
    GT_RXPMARESET032_out,
    PIPE_RXPOLARITY,
    userrdy_reg_rep,
    pclk_sel_reg,
    PIPE_TXDEEMPH,
    PIPE_TXDETECTRX,
    \txsync_fsm.txdlyen_reg ,
    \txsync_fsm.fsm_tx_reg[2] ,
    PIPE_TXELECIDLE,
    pipe_txinhibit,
    \txsync_fsm.fsm_tx_reg[4] ,
    \txsync_fsm.fsm_tx_reg[4]_0 ,
    GT_TXPMARESET035_out,
    DRPDI,
    PIPE_POWERDOWN,
    RXSYSCLKSEL,
    RXRATE,
    PIPE_TXMARGIN,
    USER_OOBCLK,
    RXCHBONDO,
    TXPOSTCURSOR,
    TXPRECURSOR,
    PIPE_TXDATA,
    TXMAINCURSOR,
    PIPE_TXCOMPLIANCE,
    PIPE_TXDATAK,
    DRPADDR,
    Q,
    \pl_ltssm_state_q_reg[4] ,
    gt_rxvalid_q_reg,
    rst_cpllpd,
    p_0_in38_in,
    RST_CPLLRESET,
    p_0_in36_in,
    \resetovrd_disble.reset_reg[4]_0 ,
    \resetovrd_disble.reset_reg[4]_1 );
  output RATE_CPLLLOCK;
  output [0:0]ext_ch_gt_drprdy;
  output [0:0]pipe_eyescandataerror;
  output [0:0]pci_exp_txn;
  output [0:0]pci_exp_txp;
  output RATE_PHYSTATUS;
  output rxcdrlock_reg1_reg;
  output [0:0]PIPE_RXCHANISALIGNED;
  output [0:0]pipe_rxcommadet;
  output [0:0]pipe_rxdlysresetdone;
  output [0:0]gt_rx_elec_idle_wire_filter;
  output [0:0]pipe_rxoutclk_out;
  output [0:0]pipe_rxphaligndone;
  output [0:0]pipe_rxprbserr;
  output RATE_RXRATEDONE;
  output USER_RXRESETDONE;
  output rxvalid_reg1_reg;
  output [0:0]pipe_txdlysresetdone;
  output [0:0]pipe_txphaligndone;
  output [0:0]pipe_txphinitdone;
  output RATE_TXRATEDONE;
  output USER_TXRESETDONE;
  output [15:0]ext_ch_gt_drpdo;
  output [2:0]pipe_rxbufstatus;
  output [2:0]pipe_rxstatus;
  output [15:0]\gt_rxdata_q_reg[15] ;
  output [7:0]pipe_dmonitorout;
  output [1:0]\gt_rxcharisk_q_reg[1] ;
  output [7:0]pipe_rxdisperr;
  output [7:0]pipe_rxnotintable;
  output [2:0]\gt_rx_status_q_reg[2] ;
  output SYNC_TXDLYSRESETDONE0;
  output SYNC_RXDLYSRESETDONE0;
  input gt_cpllpdrefclk;
  input \resetovrd_disble.reset_reg[4] ;
  input \fsm_reg[2] ;
  input \fsm_reg[0] ;
  input USER_EYESCANRESET;
  input sys_clk;
  input rst_gtreset;
  input [0:0]pci_exp_rxn;
  input [0:0]pci_exp_rxp;
  input qpllpd_reg;
  input qpllpd_reg_0;
  input \resetovrd_disble.fsm_reg[1] ;
  input gen3_reg;
  input USER_RXBUFRESET;
  input USER_RXCDRFREQRESET;
  input USER_RXCDRRESET;
  input gen3_reg_0;
  input GT_RX_CONVERGE0;
  input USER_RXDFELPMRESET;
  input SYNC_RXSYNC_DONE;
  input \rxsync_fsm_disable.fsm_rx_reg[2] ;
  input USER_RXPCSRESET;
  input rxsync_donem_reg2_reg;
  input GT_RXPMARESET032_out;
  input [0:0]PIPE_RXPOLARITY;
  input userrdy_reg_rep;
  input pclk_sel_reg;
  input [0:0]PIPE_TXDEEMPH;
  input PIPE_TXDETECTRX;
  input \txsync_fsm.txdlyen_reg ;
  input \txsync_fsm.fsm_tx_reg[2] ;
  input [0:0]PIPE_TXELECIDLE;
  input [0:0]pipe_txinhibit;
  input \txsync_fsm.fsm_tx_reg[4] ;
  input \txsync_fsm.fsm_tx_reg[4]_0 ;
  input GT_TXPMARESET035_out;
  input [15:0]DRPDI;
  input [1:0]PIPE_POWERDOWN;
  input [1:0]RXSYSCLKSEL;
  input [2:0]RXRATE;
  input [2:0]PIPE_TXMARGIN;
  input USER_OOBCLK;
  input [4:0]RXCHBONDO;
  input [4:0]TXPOSTCURSOR;
  input [4:0]TXPRECURSOR;
  input [15:0]PIPE_TXDATA;
  input [6:0]TXMAINCURSOR;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [1:0]PIPE_TXDATAK;
  input [8:0]DRPADDR;
  input [1:0]Q;
  input \pl_ltssm_state_q_reg[4] ;
  input gt_rxvalid_q_reg;
  input rst_cpllpd;
  input p_0_in38_in;
  input RST_CPLLRESET;
  input p_0_in36_in;
  input [6:0]\resetovrd_disble.reset_reg[4]_0 ;
  input [6:0]\resetovrd_disble.reset_reg[4]_1 ;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire GT_RXPMARESET032_out;
  wire GT_RX_CONVERGE0;
  wire GT_TXPMARESET035_out;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXDEEMPH;
  wire PIPE_TXDETECTRX;
  wire [0:0]PIPE_TXELECIDLE;
  wire [2:0]PIPE_TXMARGIN;
  wire [1:0]Q;
  wire RATE_CPLLLOCK;
  wire RATE_PHYSTATUS;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RST_CPLLRESET;
  wire [4:0]RXCHBONDO;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXDLYSRESETDONE0;
  wire SYNC_RXSYNC_DONE;
  wire SYNC_TXDLYSRESETDONE0;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_EYESCANRESET;
  wire USER_OOBCLK;
  wire USER_RXBUFRESET;
  wire USER_RXCDRFREQRESET;
  wire USER_RXCDRRESET;
  wire USER_RXDFELPMRESET;
  wire USER_RXPCSRESET;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drprdy;
  wire \fsm_reg[0] ;
  wire \fsm_reg[2] ;
  wire gen3_reg;
  wire gen3_reg_0;
  wire gt_cpllpdrefclk;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxvalid_q_reg;
  wire \gtx_channel.gtxe2_channel_i_n_10 ;
  wire \gtx_channel.gtxe2_channel_i_n_138 ;
  wire \gtx_channel.gtxe2_channel_i_n_139 ;
  wire \gtx_channel.gtxe2_channel_i_n_140 ;
  wire \gtx_channel.gtxe2_channel_i_n_141 ;
  wire \gtx_channel.gtxe2_channel_i_n_142 ;
  wire \gtx_channel.gtxe2_channel_i_n_143 ;
  wire \gtx_channel.gtxe2_channel_i_n_144 ;
  wire \gtx_channel.gtxe2_channel_i_n_145 ;
  wire \gtx_channel.gtxe2_channel_i_n_146 ;
  wire \gtx_channel.gtxe2_channel_i_n_147 ;
  wire \gtx_channel.gtxe2_channel_i_n_148 ;
  wire \gtx_channel.gtxe2_channel_i_n_149 ;
  wire \gtx_channel.gtxe2_channel_i_n_150 ;
  wire \gtx_channel.gtxe2_channel_i_n_151 ;
  wire \gtx_channel.gtxe2_channel_i_n_152 ;
  wire \gtx_channel.gtxe2_channel_i_n_153 ;
  wire \gtx_channel.gtxe2_channel_i_n_189 ;
  wire \gtx_channel.gtxe2_channel_i_n_190 ;
  wire \gtx_channel.gtxe2_channel_i_n_191 ;
  wire \gtx_channel.gtxe2_channel_i_n_192 ;
  wire \gtx_channel.gtxe2_channel_i_n_197 ;
  wire \gtx_channel.gtxe2_channel_i_n_198 ;
  wire \gtx_channel.gtxe2_channel_i_n_37 ;
  wire \gtx_channel.gtxe2_channel_i_n_9 ;
  wire \gtx_channel.gtxe2_channel_i_n_91 ;
  wire \gtx_channel.gtxe2_channel_i_n_92 ;
  wire \gtx_channel.gtxe2_channel_i_n_93 ;
  wire \gtx_channel.gtxe2_channel_i_n_94 ;
  wire \gtx_channel.gtxe2_channel_i_n_95 ;
  wire p_0_in36_in;
  wire p_0_in38_in;
  wire [0:0]pci_exp_rxn;
  wire [0:0]pci_exp_rxp;
  wire [0:0]pci_exp_txn;
  wire [0:0]pci_exp_txp;
  wire pclk_sel_reg;
  wire [7:0]pipe_dmonitorout;
  wire [0:0]pipe_eyescandataerror;
  wire [2:0]pipe_rxbufstatus;
  wire [0:0]pipe_rxcommadet;
  wire [7:0]pipe_rxdisperr;
  wire [0:0]pipe_rxdlysresetdone;
  wire [7:0]pipe_rxnotintable;
  wire [0:0]pipe_rxoutclk_out;
  wire [0:0]pipe_rxphaligndone;
  wire [0:0]pipe_rxprbserr;
  wire [2:0]pipe_rxstatus;
  wire [0:0]pipe_txdlysresetdone;
  wire [0:0]pipe_txinhibit;
  wire [0:0]pipe_txphaligndone;
  wire [0:0]pipe_txphinitdone;
  wire \pl_ltssm_state_q_reg[4] ;
  wire qpllpd_reg;
  wire qpllpd_reg_0;
  wire \resetovrd_disble.fsm_reg[1] ;
  wire \resetovrd_disble.reset_reg[4] ;
  wire [6:0]\resetovrd_disble.reset_reg[4]_0 ;
  wire [6:0]\resetovrd_disble.reset_reg[4]_1 ;
  wire rst_cpllpd;
  wire rst_gtreset;
  wire rxcdrlock_reg1_reg;
  wire rxdlysresetdone_reg1_i_2_n_0;
  wire rxsync_donem_reg2_reg;
  wire \rxsync_fsm_disable.fsm_rx_reg[2] ;
  wire rxvalid_reg1_reg;
  wire sys_clk;
  wire txdlysresetdone_reg1_i_2_n_0;
  wire \txsync_fsm.fsm_tx_reg[2] ;
  wire \txsync_fsm.fsm_tx_reg[4] ;
  wire \txsync_fsm.fsm_tx_reg[4]_0 ;
  wire \txsync_fsm.txdlyen_reg ;
  wire userrdy_reg_rep;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
  wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
  wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
  wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
  wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
  wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;

  PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_73 cpllPDInst
       (.CPLLPD0(CPLLPD0),
        .CPLLRESET0(CPLLRESET0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .p_0_in36_in(p_0_in36_in),
        .p_0_in38_in(p_0_in38_in),
        .rst_cpllpd(rst_cpllpd));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[0]_i_1__0 
       (.I0(pipe_rxstatus[0]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [0]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[1]_i_1__0 
       (.I0(pipe_rxstatus[1]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [1]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[2]_i_1__0 
       (.I0(pipe_rxstatus[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [2]));
  (* box_type = "PRIMITIVE" *) 
  GTXE2_CHANNEL #(
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(1),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CHAN_BOND_KEEP_ALIGN("TRUE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0001001010),
    .CHAN_BOND_SEQ_1_2(10'b0001001010),
    .CHAN_BOND_SEQ_1_3(10'b0001001010),
    .CHAN_BOND_SEQ_1_4(10'b0110111100),
    .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_1(10'b0001000101),
    .CHAN_BOND_SEQ_2_2(10'b0001000101),
    .CHAN_BOND_SEQ_2_3(10'b0001000101),
    .CHAN_BOND_SEQ_2_4(10'b0110111100),
    .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_USE("TRUE"),
    .CHAN_BOND_SEQ_LEN(4),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("TRUE"),
    .CLK_COR_MAX_LAT(20),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0100011100),
    .CLK_COR_SEQ_1_2(10'b0000000000),
    .CLK_COR_SEQ_1_3(10'b0000000000),
    .CLK_COR_SEQ_1_4(10'b0000000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0000000000),
    .CLK_COR_SEQ_2_2(10'b0000000000),
    .CLK_COR_SEQ_2_3(10'b0000000000),
    .CLK_COR_SEQ_2_4(10'b0000000000),
    .CLK_COR_SEQ_2_ENABLE(4'b0000),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(1),
    .CPLL_CFG(24'hA407CC),
    .CPLL_FBDIV(5),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000B01),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("FALSE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("TRUE"),
    .GEARBOX_MODE(3'b000),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("TRUE"),
    .PCS_RSVD_ATTR(48'h0000000001CF),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h09),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'h00018480),
    .PMA_RSV2(16'h2050),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(32'h00000000),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b0100),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("TRUE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(72'h03000023FF10200020),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b1),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00000011110000),
    .RXLPM_LF_CFG(14'b00000011110000),
    .RXOOB_CFG(7'b0000110),
    .RXOUT_DIV(2),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h004020),
    .RXPH_CFG(24'h000000),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("PMA"),
    .RX_BIAS_CFG(12'b000000000100),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(4),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(3'b010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(12'b000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFE_GAIN_CFG(23'h020FEA),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011110000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_KL_CFG(13'b0000011111110),
    .RX_DFE_KL_CFG2(32'h3290D86C),
    .RX_DFE_LPM_CFG(16'h0954),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
    .RX_DFE_UT_CFG(17'b10001111000000000),
    .RX_DFE_VP_CFG(17'b00011111100000011),
    .RX_DFE_XYD_CFG(13'b0000000000000),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(4),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b1111),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("FALSE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
    .SIM_VERSION("3.0"),
    .TERM_RCAL_CFG(5'b10000),
    .TERM_RCAL_OVRD(1'b0),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("FALSE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOUT_DIV(2),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPMARESET_TIME(5'b00011),
    .TX_CLK25_DIV(4),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(5'b10100),
    .TX_DEEMPH1(5'b01011),
    .TX_DRIVE_MODE("PIPE"),
    .TX_EIDLE_ASSERT_DELAY(3'b010),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001111),
    .TX_MARGIN_FULL_1(7'b1001110),
    .TX_MARGIN_FULL_2(7'b1001101),
    .TX_MARGIN_FULL_3(7'b1001100),
    .TX_MARGIN_FULL_4(7'b1000011),
    .TX_MARGIN_LOW_0(7'b1000101),
    .TX_MARGIN_LOW_1(7'b1000110),
    .TX_MARGIN_LOW_2(7'b1000011),
    .TX_MARGIN_LOW_3(7'b1000010),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_PREDRIVER_MODE(1'b0),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h0064),
    .TX_RXDETECT_REF(3'b011),
    .TX_XCLK_SEL("TXUSR"),
    .UCODEER_CLR(1'b0)) 
    \gtx_channel.gtxe2_channel_i 
       (.CFGRESET(1'b0),
        .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
        .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
        .CPLLLOCK(RATE_CPLLLOCK),
        .CPLLLOCKDETCLK(1'b0),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD0),
        .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET0),
        .DMONITOROUT(pipe_dmonitorout),
        .DRPADDR(DRPADDR),
        .DRPCLK(\resetovrd_disble.reset_reg[4] ),
        .DRPDI(DRPDI),
        .DRPDO(ext_ch_gt_drpdo),
        .DRPEN(\fsm_reg[2] ),
        .DRPRDY(ext_ch_gt_drprdy),
        .DRPWE(\fsm_reg[0] ),
        .EYESCANDATAERROR(pipe_eyescandataerror),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(USER_EYESCANRESET),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(rst_gtreset),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(rst_gtreset),
        .GTXRXN(pci_exp_rxn),
        .GTXRXP(pci_exp_rxp),
        .GTXTXN(pci_exp_txn),
        .GTXTXP(pci_exp_txp),
        .LOOPBACK({1'b0,1'b0,1'b0}),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
        .PHYSTATUS(RATE_PHYSTATUS),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(qpllpd_reg),
        .QPLLREFCLK(qpllpd_reg_0),
        .RESETOVRD(\resetovrd_disble.fsm_reg[1] ),
        .RX8B10BEN(gen3_reg),
        .RXBUFRESET(USER_RXBUFRESET),
        .RXBUFSTATUS(pipe_rxbufstatus),
        .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
        .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
        .RXCDRFREQRESET(USER_RXCDRFREQRESET),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(rxcdrlock_reg1_reg),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(USER_RXCDRRESET),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
        .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
        .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
        .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
        .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,\gt_rxcharisk_q_reg[1] }),
        .RXCHBONDEN(gen3_reg),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }),
        .RXCHBONDSLAVE(gen3_reg_0),
        .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
        .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
        .RXCOMMADET(pipe_rxcommadet),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
        .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
        .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,\gt_rxdata_q_reg[15] }),
        .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(GT_RX_CONVERGE0),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b1),
        .RXDFELPMRESET(USER_RXDFELPMRESET),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b0),
        .RXDFEXYDHOLD(1'b0),
        .RXDFEXYDOVRDEN(1'b0),
        .RXDISPERR(pipe_rxdisperr),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(SYNC_RXSYNC_DONE),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(\rxsync_fsm_disable.fsm_rx_reg[2] ),
        .RXDLYSRESETDONE(pipe_rxdlysresetdone),
        .RXELECIDLE(gt_rx_elec_idle_wire_filter),
        .RXELECIDLEMODE({1'b0,1'b0}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
        .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
        .RXLPMEN(gen3_reg_0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(gen3_reg),
        .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE(pipe_rxnotintable),
        .RXOOBRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(pipe_rxoutclk_out),
        .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
        .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
        .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .RXPCOMMAALIGNEN(gen3_reg_0),
        .RXPCSRESET(USER_RXPCSRESET),
        .RXPD(PIPE_POWERDOWN),
        .RXPHALIGN(rxsync_donem_reg2_reg),
        .RXPHALIGNDONE(pipe_rxphaligndone),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
        .RXPMARESET(GT_RXPMARESET032_out),
        .RXPOLARITY(PIPE_RXPOLARITY),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(pipe_rxprbserr),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
        .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
        .RXRATE(RXRATE),
        .RXRATEDONE(RATE_RXRATEDONE),
        .RXRESETDONE(USER_RXRESETDONE),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
        .RXSTATUS(pipe_rxstatus),
        .RXSYSCLKSEL(RXSYSCLKSEL),
        .RXUSERRDY(userrdy_reg_rep),
        .RXUSRCLK(pclk_sel_reg),
        .RXUSRCLK2(pclk_sel_reg),
        .RXVALID(rxvalid_reg1_reg),
        .SETERRSTATUS(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(gen3_reg_0),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
        .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
        .TXDEEMPH(PIPE_TXDEEMPH),
        .TXDETECTRX(PIPE_TXDETECTRX),
        .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b0),
        .TXDLYEN(\txsync_fsm.txdlyen_reg ),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(\txsync_fsm.fsm_tx_reg[2] ),
        .TXDLYSRESETDONE(pipe_txdlysresetdone),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(PIPE_TXELECIDLE),
        .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(pipe_txinhibit),
        .TXMAINCURSOR(TXMAINCURSOR),
        .TXMARGIN(PIPE_TXMARGIN),
        .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ),
        .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
        .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
        .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD(PIPE_POWERDOWN),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(\txsync_fsm.fsm_tx_reg[4] ),
        .TXPHALIGNDONE(pipe_txphaligndone),
        .TXPHALIGNEN(1'b1),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(\txsync_fsm.fsm_tx_reg[4]_0 ),
        .TXPHINITDONE(pipe_txphinitdone),
        .TXPHOVRDEN(1'b0),
        .TXPISOPD(1'b0),
        .TXPMARESET(GT_TXPMARESET035_out),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR(TXPOSTCURSOR),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR(TXPRECURSOR),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
        .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE(RXRATE),
        .TXRATEDONE(RATE_TXRATEDONE),
        .TXRESETDONE(USER_TXRESETDONE),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYSCLKSEL(RXSYSCLKSEL),
        .TXUSERRDY(userrdy_reg_rep),
        .TXUSRCLK(pclk_sel_reg),
        .TXUSRCLK2(pclk_sel_reg));
  LUT3 #(
    .INIT(8'h80)) 
    rxdlysresetdone_reg1_i_1
       (.I0(rxdlysresetdone_reg1_i_2_n_0),
        .I1(\resetovrd_disble.reset_reg[4]_1 [4]),
        .I2(\resetovrd_disble.reset_reg[4]_1 [5]),
        .O(SYNC_RXDLYSRESETDONE0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    rxdlysresetdone_reg1_i_2
       (.I0(pipe_rxdlysresetdone),
        .I1(\resetovrd_disble.reset_reg[4]_1 [6]),
        .I2(\resetovrd_disble.reset_reg[4]_1 [1]),
        .I3(\resetovrd_disble.reset_reg[4]_1 [0]),
        .I4(\resetovrd_disble.reset_reg[4]_1 [3]),
        .I5(\resetovrd_disble.reset_reg[4]_1 [2]),
        .O(rxdlysresetdone_reg1_i_2_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    txdlysresetdone_reg1_i_1
       (.I0(txdlysresetdone_reg1_i_2_n_0),
        .I1(\resetovrd_disble.reset_reg[4]_0 [4]),
        .I2(\resetovrd_disble.reset_reg[4]_0 [5]),
        .O(SYNC_TXDLYSRESETDONE0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    txdlysresetdone_reg1_i_2
       (.I0(pipe_txdlysresetdone),
        .I1(\resetovrd_disble.reset_reg[4]_0 [6]),
        .I2(\resetovrd_disble.reset_reg[4]_0 [1]),
        .I3(\resetovrd_disble.reset_reg[4]_0 [0]),
        .I4(\resetovrd_disble.reset_reg[4]_0 [3]),
        .I5(\resetovrd_disble.reset_reg[4]_0 [2]),
        .O(txdlysresetdone_reg1_i_2_n_0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gt_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_66
   (RATE_CPLLLOCK,
    ext_ch_gt_drprdy,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    RATE_PHYSTATUS,
    rxcdrlock_reg1_reg,
    PIPE_RXCHANISALIGNED,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    gt_rx_elec_idle_wire_filter,
    pipe_rxoutclk_out,
    pipe_rxphaligndone,
    pipe_rxprbserr,
    RATE_RXRATEDONE,
    USER_RXRESETDONE,
    rxvalid_reg1_reg,
    pipe_txdlysresetdone,
    pipe_txphaligndone,
    pipe_txphinitdone,
    RATE_TXRATEDONE,
    USER_TXRESETDONE,
    ext_ch_gt_drpdo,
    pipe_rxbufstatus,
    pipe_rxstatus,
    \gt_rxdata_q_reg[15] ,
    pipe_dmonitorout,
    \gt_rxcharisk_q_reg[1] ,
    pipe_rxdisperr,
    pipe_rxnotintable,
    \gt_rx_status_q_reg[2] ,
    gt_cpllpdrefclk,
    \resetovrd_disble.reset_reg[4] ,
    \fsm_reg[2] ,
    \fsm_reg[0] ,
    USER_EYESCANRESET,
    sys_clk,
    rst_gtreset,
    pci_exp_rxn,
    pci_exp_rxp,
    qpllpd_reg,
    qpllpd_reg_0,
    \resetovrd_disble.fsm_reg[1] ,
    gen3_reg,
    USER_RXBUFRESET,
    USER_RXCDRFREQRESET,
    USER_RXCDRRESET,
    gen3_reg_0,
    converge_gen3_reg,
    USER_RXDFELPMRESET,
    SYNC_RXSYNC_DONE,
    \rxsync_fsm_disable.fsm_rx_reg[2] ,
    USER_RXPCSRESET,
    rxsync_donem_reg2_reg,
    GT_RXPMARESET014_out,
    PIPE_RXPOLARITY,
    rst_userrdy,
    pclk_sel_reg,
    PIPE_TXDEEMPH,
    pipe_tx_rcvr_det,
    \txsync_fsm.txdlyen_reg ,
    \txsync_fsm.fsm_tx_reg[2] ,
    PIPE_TXELECIDLE,
    pipe_txinhibit,
    \txsync_fsm.fsm_tx_reg[4] ,
    \txsync_fsm.fsm_tx_reg[4]_0 ,
    GT_TXPMARESET017_out,
    DRPDI,
    PIPE_POWERDOWN,
    RXSYSCLKSEL,
    RXRATE,
    \pipe_stages_1.pipe_tx_margin_q_reg[2] ,
    USER_OOBCLK,
    RXCHBONDO,
    TXPOSTCURSOR,
    TXPRECURSOR,
    PIPE_TXDATA,
    TXMAINCURSOR,
    PIPE_TXCOMPLIANCE,
    PIPE_TXDATAK,
    DRPADDR,
    Q,
    \pl_ltssm_state_q_reg[4] ,
    gt_rxvalid_q_reg,
    rst_cpllpd,
    p_0_in20_in,
    RST_CPLLRESET,
    p_0_in18_in);
  output RATE_CPLLLOCK;
  output [0:0]ext_ch_gt_drprdy;
  output [0:0]pipe_eyescandataerror;
  output [0:0]pci_exp_txn;
  output [0:0]pci_exp_txp;
  output RATE_PHYSTATUS;
  output rxcdrlock_reg1_reg;
  output [0:0]PIPE_RXCHANISALIGNED;
  output [0:0]pipe_rxcommadet;
  output [0:0]pipe_rxdlysresetdone;
  output [0:0]gt_rx_elec_idle_wire_filter;
  output [0:0]pipe_rxoutclk_out;
  output [0:0]pipe_rxphaligndone;
  output [0:0]pipe_rxprbserr;
  output RATE_RXRATEDONE;
  output USER_RXRESETDONE;
  output rxvalid_reg1_reg;
  output [0:0]pipe_txdlysresetdone;
  output [0:0]pipe_txphaligndone;
  output [0:0]pipe_txphinitdone;
  output RATE_TXRATEDONE;
  output USER_TXRESETDONE;
  output [15:0]ext_ch_gt_drpdo;
  output [2:0]pipe_rxbufstatus;
  output [2:0]pipe_rxstatus;
  output [15:0]\gt_rxdata_q_reg[15] ;
  output [7:0]pipe_dmonitorout;
  output [1:0]\gt_rxcharisk_q_reg[1] ;
  output [7:0]pipe_rxdisperr;
  output [7:0]pipe_rxnotintable;
  output [2:0]\gt_rx_status_q_reg[2] ;
  input gt_cpllpdrefclk;
  input \resetovrd_disble.reset_reg[4] ;
  input \fsm_reg[2] ;
  input \fsm_reg[0] ;
  input USER_EYESCANRESET;
  input sys_clk;
  input rst_gtreset;
  input [0:0]pci_exp_rxn;
  input [0:0]pci_exp_rxp;
  input qpllpd_reg;
  input qpllpd_reg_0;
  input \resetovrd_disble.fsm_reg[1] ;
  input gen3_reg;
  input USER_RXBUFRESET;
  input USER_RXCDRFREQRESET;
  input USER_RXCDRRESET;
  input gen3_reg_0;
  input converge_gen3_reg;
  input USER_RXDFELPMRESET;
  input SYNC_RXSYNC_DONE;
  input \rxsync_fsm_disable.fsm_rx_reg[2] ;
  input USER_RXPCSRESET;
  input rxsync_donem_reg2_reg;
  input GT_RXPMARESET014_out;
  input [0:0]PIPE_RXPOLARITY;
  input rst_userrdy;
  input pclk_sel_reg;
  input [0:0]PIPE_TXDEEMPH;
  input pipe_tx_rcvr_det;
  input \txsync_fsm.txdlyen_reg ;
  input \txsync_fsm.fsm_tx_reg[2] ;
  input [0:0]PIPE_TXELECIDLE;
  input [0:0]pipe_txinhibit;
  input \txsync_fsm.fsm_tx_reg[4] ;
  input \txsync_fsm.fsm_tx_reg[4]_0 ;
  input GT_TXPMARESET017_out;
  input [15:0]DRPDI;
  input [1:0]PIPE_POWERDOWN;
  input [1:0]RXSYSCLKSEL;
  input [2:0]RXRATE;
  input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  input USER_OOBCLK;
  input [4:0]RXCHBONDO;
  input [4:0]TXPOSTCURSOR;
  input [4:0]TXPRECURSOR;
  input [15:0]PIPE_TXDATA;
  input [6:0]TXMAINCURSOR;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [1:0]PIPE_TXDATAK;
  input [8:0]DRPADDR;
  input [1:0]Q;
  input \pl_ltssm_state_q_reg[4] ;
  input gt_rxvalid_q_reg;
  input rst_cpllpd;
  input p_0_in20_in;
  input RST_CPLLRESET;
  input p_0_in18_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire GT_RXPMARESET014_out;
  wire GT_TXPMARESET017_out;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXDEEMPH;
  wire [0:0]PIPE_TXELECIDLE;
  wire [1:0]Q;
  wire RATE_CPLLLOCK;
  wire RATE_PHYSTATUS;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RST_CPLLRESET;
  wire [4:0]RXCHBONDO;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_EYESCANRESET;
  wire USER_OOBCLK;
  wire USER_RXBUFRESET;
  wire USER_RXCDRFREQRESET;
  wire USER_RXCDRRESET;
  wire USER_RXDFELPMRESET;
  wire USER_RXPCSRESET;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire converge_gen3_reg;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drprdy;
  wire \fsm_reg[0] ;
  wire \fsm_reg[2] ;
  wire gen3_reg;
  wire gen3_reg_0;
  wire gt_cpllpdrefclk;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxvalid_q_reg;
  wire \gtx_channel.gtxe2_channel_i_n_10 ;
  wire \gtx_channel.gtxe2_channel_i_n_138 ;
  wire \gtx_channel.gtxe2_channel_i_n_139 ;
  wire \gtx_channel.gtxe2_channel_i_n_140 ;
  wire \gtx_channel.gtxe2_channel_i_n_141 ;
  wire \gtx_channel.gtxe2_channel_i_n_142 ;
  wire \gtx_channel.gtxe2_channel_i_n_143 ;
  wire \gtx_channel.gtxe2_channel_i_n_144 ;
  wire \gtx_channel.gtxe2_channel_i_n_145 ;
  wire \gtx_channel.gtxe2_channel_i_n_146 ;
  wire \gtx_channel.gtxe2_channel_i_n_147 ;
  wire \gtx_channel.gtxe2_channel_i_n_148 ;
  wire \gtx_channel.gtxe2_channel_i_n_149 ;
  wire \gtx_channel.gtxe2_channel_i_n_150 ;
  wire \gtx_channel.gtxe2_channel_i_n_151 ;
  wire \gtx_channel.gtxe2_channel_i_n_152 ;
  wire \gtx_channel.gtxe2_channel_i_n_153 ;
  wire \gtx_channel.gtxe2_channel_i_n_189 ;
  wire \gtx_channel.gtxe2_channel_i_n_190 ;
  wire \gtx_channel.gtxe2_channel_i_n_191 ;
  wire \gtx_channel.gtxe2_channel_i_n_192 ;
  wire \gtx_channel.gtxe2_channel_i_n_197 ;
  wire \gtx_channel.gtxe2_channel_i_n_198 ;
  wire \gtx_channel.gtxe2_channel_i_n_37 ;
  wire \gtx_channel.gtxe2_channel_i_n_9 ;
  wire \gtx_channel.gtxe2_channel_i_n_91 ;
  wire \gtx_channel.gtxe2_channel_i_n_92 ;
  wire \gtx_channel.gtxe2_channel_i_n_93 ;
  wire \gtx_channel.gtxe2_channel_i_n_94 ;
  wire \gtx_channel.gtxe2_channel_i_n_95 ;
  wire p_0_in18_in;
  wire p_0_in20_in;
  wire [0:0]pci_exp_rxn;
  wire [0:0]pci_exp_rxp;
  wire [0:0]pci_exp_txn;
  wire [0:0]pci_exp_txp;
  wire pclk_sel_reg;
  wire [7:0]pipe_dmonitorout;
  wire [0:0]pipe_eyescandataerror;
  wire [2:0]pipe_rxbufstatus;
  wire [0:0]pipe_rxcommadet;
  wire [7:0]pipe_rxdisperr;
  wire [0:0]pipe_rxdlysresetdone;
  wire [7:0]pipe_rxnotintable;
  wire [0:0]pipe_rxoutclk_out;
  wire [0:0]pipe_rxphaligndone;
  wire [0:0]pipe_rxprbserr;
  wire [2:0]pipe_rxstatus;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  wire pipe_tx_rcvr_det;
  wire [0:0]pipe_txdlysresetdone;
  wire [0:0]pipe_txinhibit;
  wire [0:0]pipe_txphaligndone;
  wire [0:0]pipe_txphinitdone;
  wire \pl_ltssm_state_q_reg[4] ;
  wire qpllpd_reg;
  wire qpllpd_reg_0;
  wire \resetovrd_disble.fsm_reg[1] ;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_cpllpd;
  wire rst_gtreset;
  wire rst_userrdy;
  wire rxcdrlock_reg1_reg;
  wire rxsync_donem_reg2_reg;
  wire \rxsync_fsm_disable.fsm_rx_reg[2] ;
  wire rxvalid_reg1_reg;
  wire sys_clk;
  wire \txsync_fsm.fsm_tx_reg[2] ;
  wire \txsync_fsm.fsm_tx_reg[4] ;
  wire \txsync_fsm.fsm_tx_reg[4]_0 ;
  wire \txsync_fsm.txdlyen_reg ;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ;
  wire \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ;
  wire [15:0]\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED ;
  wire [7:4]\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED ;
  wire [63:32]\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED ;
  wire [2:0]\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED ;
  wire [6:0]\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED ;
  wire [4:0]\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED ;
  wire [9:0]\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED ;
  wire [1:0]\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED ;

  PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd cpllPDInst
       (.CPLLPD0(CPLLPD0),
        .CPLLRESET0(CPLLRESET0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .p_0_in18_in(p_0_in18_in),
        .p_0_in20_in(p_0_in20_in),
        .rst_cpllpd(rst_cpllpd));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[0]_i_1 
       (.I0(pipe_rxstatus[0]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [0]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[1]_i_1 
       (.I0(pipe_rxstatus[1]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [1]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \gt_rx_status_q[2]_i_1 
       (.I0(pipe_rxstatus[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\pl_ltssm_state_q_reg[4] ),
        .I4(gt_rxvalid_q_reg),
        .O(\gt_rx_status_q_reg[2] [2]));
  (* box_type = "PRIMITIVE" *) 
  GTXE2_CHANNEL #(
    .ALIGN_COMMA_DOUBLE("FALSE"),
    .ALIGN_COMMA_ENABLE(10'b1111111111),
    .ALIGN_COMMA_WORD(1),
    .ALIGN_MCOMMA_DET("TRUE"),
    .ALIGN_MCOMMA_VALUE(10'b1010000011),
    .ALIGN_PCOMMA_DET("TRUE"),
    .ALIGN_PCOMMA_VALUE(10'b0101111100),
    .CBCC_DATA_SOURCE_SEL("DECODED"),
    .CHAN_BOND_KEEP_ALIGN("TRUE"),
    .CHAN_BOND_MAX_SKEW(7),
    .CHAN_BOND_SEQ_1_1(10'b0001001010),
    .CHAN_BOND_SEQ_1_2(10'b0001001010),
    .CHAN_BOND_SEQ_1_3(10'b0001001010),
    .CHAN_BOND_SEQ_1_4(10'b0110111100),
    .CHAN_BOND_SEQ_1_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_1(10'b0001000101),
    .CHAN_BOND_SEQ_2_2(10'b0001000101),
    .CHAN_BOND_SEQ_2_3(10'b0001000101),
    .CHAN_BOND_SEQ_2_4(10'b0110111100),
    .CHAN_BOND_SEQ_2_ENABLE(4'b1111),
    .CHAN_BOND_SEQ_2_USE("TRUE"),
    .CHAN_BOND_SEQ_LEN(4),
    .CLK_CORRECT_USE("TRUE"),
    .CLK_COR_KEEP_IDLE("TRUE"),
    .CLK_COR_MAX_LAT(20),
    .CLK_COR_MIN_LAT(18),
    .CLK_COR_PRECEDENCE("TRUE"),
    .CLK_COR_REPEAT_WAIT(0),
    .CLK_COR_SEQ_1_1(10'b0100011100),
    .CLK_COR_SEQ_1_2(10'b0000000000),
    .CLK_COR_SEQ_1_3(10'b0000000000),
    .CLK_COR_SEQ_1_4(10'b0000000000),
    .CLK_COR_SEQ_1_ENABLE(4'b1111),
    .CLK_COR_SEQ_2_1(10'b0000000000),
    .CLK_COR_SEQ_2_2(10'b0000000000),
    .CLK_COR_SEQ_2_3(10'b0000000000),
    .CLK_COR_SEQ_2_4(10'b0000000000),
    .CLK_COR_SEQ_2_ENABLE(4'b0000),
    .CLK_COR_SEQ_2_USE("FALSE"),
    .CLK_COR_SEQ_LEN(1),
    .CPLL_CFG(24'hA407CC),
    .CPLL_FBDIV(5),
    .CPLL_FBDIV_45(5),
    .CPLL_INIT_CFG(24'h00001E),
    .CPLL_LOCK_CFG(16'h01E8),
    .CPLL_REFCLK_DIV(1),
    .DEC_MCOMMA_DETECT("TRUE"),
    .DEC_PCOMMA_DETECT("TRUE"),
    .DEC_VALID_COMMA_ONLY("FALSE"),
    .DMONITOR_CFG(24'h000B01),
    .ES_CONTROL(6'b000000),
    .ES_ERRDET_EN("FALSE"),
    .ES_EYE_SCAN_EN("FALSE"),
    .ES_HORZ_OFFSET(12'h000),
    .ES_PMA_CFG(10'b0000000000),
    .ES_PRESCALE(5'b00000),
    .ES_QUALIFIER(80'h00000000000000000000),
    .ES_QUAL_MASK(80'h00000000000000000000),
    .ES_SDATA_MASK(80'h00000000000000000000),
    .ES_VERT_OFFSET(9'b000000000),
    .FTS_DESKEW_SEQ_ENABLE(4'b1111),
    .FTS_LANE_DESKEW_CFG(4'b1111),
    .FTS_LANE_DESKEW_EN("TRUE"),
    .GEARBOX_MODE(3'b000),
    .IS_CPLLLOCKDETCLK_INVERTED(1'b0),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_RXUSRCLK2_INVERTED(1'b0),
    .IS_RXUSRCLK_INVERTED(1'b0),
    .IS_TXPHDLYTSTCLK_INVERTED(1'b0),
    .IS_TXUSRCLK2_INVERTED(1'b0),
    .IS_TXUSRCLK_INVERTED(1'b0),
    .OUTREFCLK_SEL_INV(2'b11),
    .PCS_PCIE_EN("TRUE"),
    .PCS_RSVD_ATTR(48'h0000000001CF),
    .PD_TRANS_TIME_FROM_P2(12'h03C),
    .PD_TRANS_TIME_NONE_P2(8'h09),
    .PD_TRANS_TIME_TO_P2(8'h64),
    .PMA_RSV(32'h00018480),
    .PMA_RSV2(16'h2050),
    .PMA_RSV3(2'b00),
    .PMA_RSV4(32'h00000000),
    .RXBUFRESET_TIME(5'b00001),
    .RXBUF_ADDR_MODE("FULL"),
    .RXBUF_EIDLE_HI_CNT(4'b0100),
    .RXBUF_EIDLE_LO_CNT(4'b0000),
    .RXBUF_EN("TRUE"),
    .RXBUF_RESET_ON_CB_CHANGE("TRUE"),
    .RXBUF_RESET_ON_COMMAALIGN("FALSE"),
    .RXBUF_RESET_ON_EIDLE("TRUE"),
    .RXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .RXBUF_THRESH_OVFLW(61),
    .RXBUF_THRESH_OVRD("FALSE"),
    .RXBUF_THRESH_UNDFLW(4),
    .RXCDRFREQRESET_TIME(5'b00001),
    .RXCDRPHRESET_TIME(5'b00001),
    .RXCDR_CFG(72'h03000023FF10200020),
    .RXCDR_FR_RESET_ON_EIDLE(1'b0),
    .RXCDR_HOLD_DURING_EIDLE(1'b1),
    .RXCDR_LOCK_CFG(6'b010101),
    .RXCDR_PH_RESET_ON_EIDLE(1'b0),
    .RXDFELPMRESET_TIME(7'b0001111),
    .RXDLY_CFG(16'h001F),
    .RXDLY_LCFG(9'h030),
    .RXDLY_TAP_CFG(16'h0000),
    .RXGEARBOX_EN("FALSE"),
    .RXISCANRESET_TIME(5'b00001),
    .RXLPM_HF_CFG(14'b00000011110000),
    .RXLPM_LF_CFG(14'b00000011110000),
    .RXOOB_CFG(7'b0000110),
    .RXOUT_DIV(2),
    .RXPCSRESET_TIME(5'b00001),
    .RXPHDLY_CFG(24'h004020),
    .RXPH_CFG(24'h000000),
    .RXPH_MONITOR_SEL(5'b00000),
    .RXPMARESET_TIME(5'b00011),
    .RXPRBS_ERR_LOOPBACK(1'b0),
    .RXSLIDE_AUTO_WAIT(7),
    .RXSLIDE_MODE("PMA"),
    .RX_BIAS_CFG(12'b000000000100),
    .RX_BUFFER_CFG(6'b000000),
    .RX_CLK25_DIV(4),
    .RX_CLKMUX_PD(1'b1),
    .RX_CM_SEL(2'b11),
    .RX_CM_TRIM(3'b010),
    .RX_DATA_WIDTH(20),
    .RX_DDI_SEL(6'b000000),
    .RX_DEBUG_CFG(12'b000000000000),
    .RX_DEFER_RESET_BUF_EN("TRUE"),
    .RX_DFE_GAIN_CFG(23'h020FEA),
    .RX_DFE_H2_CFG(12'b000000000000),
    .RX_DFE_H3_CFG(12'b000001000000),
    .RX_DFE_H4_CFG(11'b00011110000),
    .RX_DFE_H5_CFG(11'b00011100000),
    .RX_DFE_KL_CFG(13'b0000011111110),
    .RX_DFE_KL_CFG2(32'h3290D86C),
    .RX_DFE_LPM_CFG(16'h0954),
    .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b1),
    .RX_DFE_UT_CFG(17'b10001111000000000),
    .RX_DFE_VP_CFG(17'b00011111100000011),
    .RX_DFE_XYD_CFG(13'b0000000000000),
    .RX_DISPERR_SEQ_MATCH("TRUE"),
    .RX_INT_DATAWIDTH(0),
    .RX_OS_CFG(13'b0000010000000),
    .RX_SIG_VALID_DLY(4),
    .RX_XCLK_SEL("RXREC"),
    .SAS_MAX_COM(64),
    .SAS_MIN_COM(36),
    .SATA_BURST_SEQ_LEN(4'b1111),
    .SATA_BURST_VAL(3'b100),
    .SATA_CPLL_CFG("VCO_3000MHZ"),
    .SATA_EIDLE_VAL(3'b100),
    .SATA_MAX_BURST(8),
    .SATA_MAX_INIT(21),
    .SATA_MAX_WAKE(7),
    .SATA_MIN_BURST(4),
    .SATA_MIN_INIT(12),
    .SATA_MIN_WAKE(4),
    .SHOW_REALIGN_COMMA("FALSE"),
    .SIM_CPLLREFCLK_SEL(3'b001),
    .SIM_RECEIVER_DETECT_PASS("TRUE"),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_TX_EIDLE_DRIVE_LEVEL("1"),
    .SIM_VERSION("3.0"),
    .TERM_RCAL_CFG(5'b10000),
    .TERM_RCAL_OVRD(1'b0),
    .TRANS_TIME_RATE(8'h0E),
    .TST_RSV(32'h00000000),
    .TXBUF_EN("FALSE"),
    .TXBUF_RESET_ON_RATE_CHANGE("TRUE"),
    .TXDLY_CFG(16'h001F),
    .TXDLY_LCFG(9'h030),
    .TXDLY_TAP_CFG(16'h0000),
    .TXGEARBOX_EN("FALSE"),
    .TXOUT_DIV(2),
    .TXPCSRESET_TIME(5'b00001),
    .TXPHDLY_CFG(24'h084020),
    .TXPH_CFG(16'h0780),
    .TXPH_MONITOR_SEL(5'b00000),
    .TXPMARESET_TIME(5'b00011),
    .TX_CLK25_DIV(4),
    .TX_CLKMUX_PD(1'b1),
    .TX_DATA_WIDTH(20),
    .TX_DEEMPH0(5'b10100),
    .TX_DEEMPH1(5'b01011),
    .TX_DRIVE_MODE("PIPE"),
    .TX_EIDLE_ASSERT_DELAY(3'b010),
    .TX_EIDLE_DEASSERT_DELAY(3'b100),
    .TX_INT_DATAWIDTH(0),
    .TX_LOOPBACK_DRIVE_HIZ("FALSE"),
    .TX_MAINCURSOR_SEL(1'b0),
    .TX_MARGIN_FULL_0(7'b1001111),
    .TX_MARGIN_FULL_1(7'b1001110),
    .TX_MARGIN_FULL_2(7'b1001101),
    .TX_MARGIN_FULL_3(7'b1001100),
    .TX_MARGIN_FULL_4(7'b1000011),
    .TX_MARGIN_LOW_0(7'b1000101),
    .TX_MARGIN_LOW_1(7'b1000110),
    .TX_MARGIN_LOW_2(7'b1000011),
    .TX_MARGIN_LOW_3(7'b1000010),
    .TX_MARGIN_LOW_4(7'b1000000),
    .TX_PREDRIVER_MODE(1'b0),
    .TX_QPI_STATUS_EN(1'b0),
    .TX_RXDETECT_CFG(14'h0064),
    .TX_RXDETECT_REF(3'b011),
    .TX_XCLK_SEL("TXUSR"),
    .UCODEER_CLR(1'b0)) 
    \gtx_channel.gtxe2_channel_i 
       (.CFGRESET(1'b0),
        .CLKRSVD({1'b0,1'b0,1'b0,USER_OOBCLK}),
        .CPLLFBCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED ),
        .CPLLLOCK(RATE_CPLLLOCK),
        .CPLLLOCKDETCLK(1'b0),
        .CPLLLOCKEN(1'b1),
        .CPLLPD(CPLLPD0),
        .CPLLREFCLKLOST(\NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED ),
        .CPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .CPLLRESET(CPLLRESET0),
        .DMONITOROUT(pipe_dmonitorout),
        .DRPADDR(DRPADDR),
        .DRPCLK(\resetovrd_disble.reset_reg[4] ),
        .DRPDI(DRPDI),
        .DRPDO(ext_ch_gt_drpdo),
        .DRPEN(\fsm_reg[2] ),
        .DRPRDY(ext_ch_gt_drprdy),
        .DRPWE(\fsm_reg[0] ),
        .EYESCANDATAERROR(pipe_eyescandataerror),
        .EYESCANMODE(1'b0),
        .EYESCANRESET(USER_EYESCANRESET),
        .EYESCANTRIGGER(1'b0),
        .GTGREFCLK(1'b0),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTREFCLKMONITOR(\NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED ),
        .GTRESETSEL(1'b0),
        .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GTRXRESET(rst_gtreset),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .GTTXRESET(rst_gtreset),
        .GTXRXN(pci_exp_rxn),
        .GTXRXP(pci_exp_rxp),
        .GTXTXN(pci_exp_txn),
        .GTXTXP(pci_exp_txp),
        .LOOPBACK({1'b0,1'b0,1'b0}),
        .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PCSRSVDOUT(\NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED [15:0]),
        .PHYSTATUS(RATE_PHYSTATUS),
        .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLCLK(qpllpd_reg),
        .QPLLREFCLK(qpllpd_reg_0),
        .RESETOVRD(\resetovrd_disble.fsm_reg[1] ),
        .RX8B10BEN(gen3_reg),
        .RXBUFRESET(USER_RXBUFRESET),
        .RXBUFSTATUS(pipe_rxbufstatus),
        .RXBYTEISALIGNED(\gtx_channel.gtxe2_channel_i_n_9 ),
        .RXBYTEREALIGN(\gtx_channel.gtxe2_channel_i_n_10 ),
        .RXCDRFREQRESET(USER_RXCDRFREQRESET),
        .RXCDRHOLD(1'b0),
        .RXCDRLOCK(rxcdrlock_reg1_reg),
        .RXCDROVRDEN(1'b0),
        .RXCDRRESET(USER_RXCDRRESET),
        .RXCDRRESETRSV(1'b0),
        .RXCHANBONDSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED ),
        .RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
        .RXCHANREALIGN(\NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED ),
        .RXCHARISCOMMA({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_189 ,\gtx_channel.gtxe2_channel_i_n_190 ,\gtx_channel.gtxe2_channel_i_n_191 ,\gtx_channel.gtxe2_channel_i_n_192 }),
        .RXCHARISK({\NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED [7:4],\gtx_channel.gtxe2_channel_i_n_197 ,\gtx_channel.gtxe2_channel_i_n_198 ,\gt_rxcharisk_q_reg[1] }),
        .RXCHBONDEN(gen3_reg),
        .RXCHBONDI(RXCHBONDO),
        .RXCHBONDLEVEL({1'b0,1'b0,1'b0}),
        .RXCHBONDMASTER(1'b0),
        .RXCHBONDO({\gtx_channel.gtxe2_channel_i_n_91 ,\gtx_channel.gtxe2_channel_i_n_92 ,\gtx_channel.gtxe2_channel_i_n_93 ,\gtx_channel.gtxe2_channel_i_n_94 ,\gtx_channel.gtxe2_channel_i_n_95 }),
        .RXCHBONDSLAVE(gen3_reg_0),
        .RXCLKCORCNT(\NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED [1:0]),
        .RXCOMINITDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED ),
        .RXCOMMADET(pipe_rxcommadet),
        .RXCOMMADETEN(1'b1),
        .RXCOMSASDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED ),
        .RXCOMWAKEDET(\NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED ),
        .RXDATA({\NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED [63:32],\gtx_channel.gtxe2_channel_i_n_138 ,\gtx_channel.gtxe2_channel_i_n_139 ,\gtx_channel.gtxe2_channel_i_n_140 ,\gtx_channel.gtxe2_channel_i_n_141 ,\gtx_channel.gtxe2_channel_i_n_142 ,\gtx_channel.gtxe2_channel_i_n_143 ,\gtx_channel.gtxe2_channel_i_n_144 ,\gtx_channel.gtxe2_channel_i_n_145 ,\gtx_channel.gtxe2_channel_i_n_146 ,\gtx_channel.gtxe2_channel_i_n_147 ,\gtx_channel.gtxe2_channel_i_n_148 ,\gtx_channel.gtxe2_channel_i_n_149 ,\gtx_channel.gtxe2_channel_i_n_150 ,\gtx_channel.gtxe2_channel_i_n_151 ,\gtx_channel.gtxe2_channel_i_n_152 ,\gtx_channel.gtxe2_channel_i_n_153 ,\gt_rxdata_q_reg[15] }),
        .RXDATAVALID(\NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED ),
        .RXDDIEN(1'b0),
        .RXDFEAGCHOLD(converge_gen3_reg),
        .RXDFEAGCOVRDEN(1'b0),
        .RXDFECM1EN(1'b0),
        .RXDFELFHOLD(1'b0),
        .RXDFELFOVRDEN(1'b1),
        .RXDFELPMRESET(USER_RXDFELPMRESET),
        .RXDFETAP2HOLD(1'b0),
        .RXDFETAP2OVRDEN(1'b0),
        .RXDFETAP3HOLD(1'b0),
        .RXDFETAP3OVRDEN(1'b0),
        .RXDFETAP4HOLD(1'b0),
        .RXDFETAP4OVRDEN(1'b0),
        .RXDFETAP5HOLD(1'b0),
        .RXDFETAP5OVRDEN(1'b0),
        .RXDFEUTHOLD(1'b0),
        .RXDFEUTOVRDEN(1'b0),
        .RXDFEVPHOLD(1'b0),
        .RXDFEVPOVRDEN(1'b0),
        .RXDFEVSEN(1'b0),
        .RXDFEXYDEN(1'b0),
        .RXDFEXYDHOLD(1'b0),
        .RXDFEXYDOVRDEN(1'b0),
        .RXDISPERR(pipe_rxdisperr),
        .RXDLYBYPASS(1'b1),
        .RXDLYEN(SYNC_RXSYNC_DONE),
        .RXDLYOVRDEN(1'b0),
        .RXDLYSRESET(\rxsync_fsm_disable.fsm_rx_reg[2] ),
        .RXDLYSRESETDONE(pipe_rxdlysresetdone),
        .RXELECIDLE(gt_rx_elec_idle_wire_filter),
        .RXELECIDLEMODE({1'b0,1'b0}),
        .RXGEARBOXSLIP(1'b0),
        .RXHEADER(\NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED [2:0]),
        .RXHEADERVALID(\NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED ),
        .RXLPMEN(gen3_reg_0),
        .RXLPMHFHOLD(1'b0),
        .RXLPMHFOVRDEN(1'b0),
        .RXLPMLFHOLD(1'b0),
        .RXLPMLFKLOVRDEN(1'b0),
        .RXMCOMMAALIGNEN(gen3_reg),
        .RXMONITOROUT(\NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED [6:0]),
        .RXMONITORSEL({1'b0,1'b0}),
        .RXNOTINTABLE(pipe_rxnotintable),
        .RXOOBRESET(1'b0),
        .RXOSHOLD(1'b0),
        .RXOSOVRDEN(1'b0),
        .RXOUTCLK(pipe_rxoutclk_out),
        .RXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED ),
        .RXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED ),
        .RXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .RXPCOMMAALIGNEN(gen3_reg_0),
        .RXPCSRESET(USER_RXPCSRESET),
        .RXPD(PIPE_POWERDOWN),
        .RXPHALIGN(rxsync_donem_reg2_reg),
        .RXPHALIGNDONE(pipe_rxphaligndone),
        .RXPHALIGNEN(1'b0),
        .RXPHDLYPD(1'b0),
        .RXPHDLYRESET(1'b0),
        .RXPHMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED [4:0]),
        .RXPHOVRDEN(1'b0),
        .RXPHSLIPMONITOR(\NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED [4:0]),
        .RXPMARESET(GT_RXPMARESET014_out),
        .RXPOLARITY(PIPE_RXPOLARITY),
        .RXPRBSCNTRESET(1'b0),
        .RXPRBSERR(pipe_rxprbserr),
        .RXPRBSSEL({1'b0,1'b0,1'b0}),
        .RXQPIEN(1'b0),
        .RXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED ),
        .RXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED ),
        .RXRATE(RXRATE),
        .RXRATEDONE(RATE_RXRATEDONE),
        .RXRESETDONE(USER_RXRESETDONE),
        .RXSLIDE(1'b0),
        .RXSTARTOFSEQ(\NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED ),
        .RXSTATUS(pipe_rxstatus),
        .RXSYSCLKSEL(RXSYSCLKSEL),
        .RXUSERRDY(rst_userrdy),
        .RXUSRCLK(pclk_sel_reg),
        .RXUSRCLK2(pclk_sel_reg),
        .RXVALID(rxvalid_reg1_reg),
        .SETERRSTATUS(1'b0),
        .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .TSTOUT(\NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED [9:0]),
        .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX8B10BEN(gen3_reg_0),
        .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}),
        .TXBUFSTATUS(\NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED [1:0]),
        .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXCOMPLIANCE}),
        .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATAK}),
        .TXCOMFINISH(\NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED ),
        .TXCOMINIT(1'b0),
        .TXCOMSAS(1'b0),
        .TXCOMWAKE(1'b0),
        .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PIPE_TXDATA}),
        .TXDEEMPH(PIPE_TXDEEMPH),
        .TXDETECTRX(pipe_tx_rcvr_det),
        .TXDIFFCTRL({1'b1,1'b1,1'b0,1'b0}),
        .TXDIFFPD(1'b0),
        .TXDLYBYPASS(1'b0),
        .TXDLYEN(\txsync_fsm.txdlyen_reg ),
        .TXDLYHOLD(1'b0),
        .TXDLYOVRDEN(1'b0),
        .TXDLYSRESET(\txsync_fsm.fsm_tx_reg[2] ),
        .TXDLYSRESETDONE(pipe_txdlysresetdone),
        .TXDLYUPDOWN(1'b0),
        .TXELECIDLE(PIPE_TXELECIDLE),
        .TXGEARBOXREADY(\NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED ),
        .TXHEADER({1'b0,1'b0,1'b0}),
        .TXINHIBIT(pipe_txinhibit),
        .TXMAINCURSOR(TXMAINCURSOR),
        .TXMARGIN(\pipe_stages_1.pipe_tx_margin_q_reg[2] ),
        .TXOUTCLK(\gtx_channel.gtxe2_channel_i_n_37 ),
        .TXOUTCLKFABRIC(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED ),
        .TXOUTCLKPCS(\NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED ),
        .TXOUTCLKSEL({1'b0,1'b0,1'b0}),
        .TXPCSRESET(1'b0),
        .TXPD(PIPE_POWERDOWN),
        .TXPDELECIDLEMODE(1'b0),
        .TXPHALIGN(\txsync_fsm.fsm_tx_reg[4] ),
        .TXPHALIGNDONE(pipe_txphaligndone),
        .TXPHALIGNEN(1'b1),
        .TXPHDLYPD(1'b0),
        .TXPHDLYRESET(1'b0),
        .TXPHDLYTSTCLK(1'b0),
        .TXPHINIT(\txsync_fsm.fsm_tx_reg[4]_0 ),
        .TXPHINITDONE(pipe_txphinitdone),
        .TXPHOVRDEN(1'b0),
        .TXPISOPD(1'b0),
        .TXPMARESET(GT_TXPMARESET017_out),
        .TXPOLARITY(1'b0),
        .TXPOSTCURSOR(TXPOSTCURSOR),
        .TXPOSTCURSORINV(1'b0),
        .TXPRBSFORCEERR(1'b0),
        .TXPRBSSEL({1'b0,1'b0,1'b0}),
        .TXPRECURSOR(TXPRECURSOR),
        .TXPRECURSORINV(1'b0),
        .TXQPIBIASEN(1'b0),
        .TXQPISENN(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED ),
        .TXQPISENP(\NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED ),
        .TXQPISTRONGPDOWN(1'b0),
        .TXQPIWEAKPUP(1'b0),
        .TXRATE(RXRATE),
        .TXRATEDONE(RATE_TXRATEDONE),
        .TXRESETDONE(USER_TXRESETDONE),
        .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TXSTARTSEQ(1'b0),
        .TXSWING(1'b0),
        .TXSYSCLKSEL(RXSYSCLKSEL),
        .TXUSERRDY(rst_userrdy),
        .TXUSRCLK(pclk_sel_reg),
        .TXUSRCLK2(pclk_sel_reg));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gtx_cpllpd_ovrd" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd
   (CPLLPD0,
    CPLLRESET0,
    gt_cpllpdrefclk,
    rst_cpllpd,
    p_0_in20_in,
    RST_CPLLRESET,
    p_0_in18_in);
  output CPLLPD0;
  output CPLLRESET0;
  input gt_cpllpdrefclk;
  input rst_cpllpd;
  input p_0_in20_in;
  input RST_CPLLRESET;
  input p_0_in18_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire RST_CPLLRESET;
  wire cpllpd;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire p_0_in18_in;
  wire p_0_in20_in;
  wire rst_cpllpd;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;

  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(cpllpd),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllrst),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[7].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_1__6 
       (.I0(cpllpd),
        .I1(rst_cpllpd),
        .I2(p_0_in20_in),
        .O(CPLLPD0));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_2__6 
       (.I0(cpllrst),
        .I1(RST_CPLLRESET),
        .I2(p_0_in18_in),
        .O(CPLLRESET0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gtx_cpllpd_ovrd" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_73
   (CPLLPD0,
    CPLLRESET0,
    gt_cpllpdrefclk,
    rst_cpllpd,
    p_0_in38_in,
    RST_CPLLRESET,
    p_0_in36_in);
  output CPLLPD0;
  output CPLLRESET0;
  input gt_cpllpdrefclk;
  input rst_cpllpd;
  input p_0_in38_in;
  input RST_CPLLRESET;
  input p_0_in36_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire RST_CPLLRESET;
  wire cpllpd;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire p_0_in36_in;
  wire p_0_in38_in;
  wire rst_cpllpd;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;

  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(cpllpd),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllrst),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[6].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_1__5 
       (.I0(cpllpd),
        .I1(rst_cpllpd),
        .I2(p_0_in38_in),
        .O(CPLLPD0));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_2__5 
       (.I0(cpllrst),
        .I1(RST_CPLLRESET),
        .I2(p_0_in36_in),
        .O(CPLLRESET0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gtx_cpllpd_ovrd" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_75
   (CPLLPD0,
    CPLLRESET0,
    gt_cpllpdrefclk,
    rst_cpllpd,
    p_0_in49_in,
    RST_CPLLRESET,
    p_0_in47_in);
  output CPLLPD0;
  output CPLLRESET0;
  input gt_cpllpdrefclk;
  input rst_cpllpd;
  input p_0_in49_in;
  input RST_CPLLRESET;
  input p_0_in47_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire RST_CPLLRESET;
  wire cpllpd;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire p_0_in47_in;
  wire p_0_in49_in;
  wire rst_cpllpd;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;

  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(cpllpd),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllrst),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[5].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_1__4 
       (.I0(cpllpd),
        .I1(rst_cpllpd),
        .I2(p_0_in49_in),
        .O(CPLLPD0));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_2__4 
       (.I0(cpllrst),
        .I1(RST_CPLLRESET),
        .I2(p_0_in47_in),
        .O(CPLLRESET0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gtx_cpllpd_ovrd" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_77
   (CPLLPD0,
    CPLLRESET0,
    gt_cpllpdrefclk,
    rst_cpllpd,
    p_0_in67_in,
    RST_CPLLRESET,
    p_0_in65_in);
  output CPLLPD0;
  output CPLLRESET0;
  input gt_cpllpdrefclk;
  input rst_cpllpd;
  input p_0_in67_in;
  input RST_CPLLRESET;
  input p_0_in65_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire RST_CPLLRESET;
  wire cpllpd;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire p_0_in65_in;
  wire p_0_in67_in;
  wire rst_cpllpd;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;

  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(cpllpd),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllrst),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[4].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_1__3 
       (.I0(cpllpd),
        .I1(rst_cpllpd),
        .I2(p_0_in67_in),
        .O(CPLLPD0));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_2__3 
       (.I0(cpllrst),
        .I1(RST_CPLLRESET),
        .I2(p_0_in65_in),
        .O(CPLLRESET0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gtx_cpllpd_ovrd" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_79
   (CPLLPD0,
    CPLLRESET0,
    gt_cpllpdrefclk,
    rst_cpllpd,
    p_0_in77_in,
    RST_CPLLRESET,
    p_0_in75_in);
  output CPLLPD0;
  output CPLLRESET0;
  input gt_cpllpdrefclk;
  input rst_cpllpd;
  input p_0_in77_in;
  input RST_CPLLRESET;
  input p_0_in75_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire RST_CPLLRESET;
  wire cpllpd;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire p_0_in75_in;
  wire p_0_in77_in;
  wire rst_cpllpd;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;

  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(cpllpd),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllrst),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_1__2 
       (.I0(cpllpd),
        .I1(rst_cpllpd),
        .I2(p_0_in77_in),
        .O(CPLLPD0));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_2__2 
       (.I0(cpllrst),
        .I1(RST_CPLLRESET),
        .I2(p_0_in75_in),
        .O(CPLLRESET0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gtx_cpllpd_ovrd" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_81
   (CPLLPD0,
    CPLLRESET0,
    gt_cpllpdrefclk,
    rst_cpllpd,
    p_0_in123_in,
    RST_CPLLRESET,
    p_0_in121_in);
  output CPLLPD0;
  output CPLLRESET0;
  input gt_cpllpdrefclk;
  input rst_cpllpd;
  input p_0_in123_in;
  input RST_CPLLRESET;
  input p_0_in121_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire RST_CPLLRESET;
  wire cpllpd;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire p_0_in121_in;
  wire p_0_in123_in;
  wire rst_cpllpd;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;

  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(cpllpd),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllrst),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_1__1 
       (.I0(cpllpd),
        .I1(rst_cpllpd),
        .I2(p_0_in123_in),
        .O(CPLLPD0));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_2__1 
       (.I0(cpllrst),
        .I1(RST_CPLLRESET),
        .I2(p_0_in121_in),
        .O(CPLLRESET0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gtx_cpllpd_ovrd" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_83
   (CPLLPD0,
    CPLLRESET0,
    gt_cpllpdrefclk,
    rst_cpllpd,
    p_0_in95_in,
    RST_CPLLRESET,
    p_0_in93_in);
  output CPLLPD0;
  output CPLLRESET0;
  input gt_cpllpdrefclk;
  input rst_cpllpd;
  input p_0_in95_in;
  input RST_CPLLRESET;
  input p_0_in93_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire RST_CPLLRESET;
  wire cpllpd;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire p_0_in93_in;
  wire p_0_in95_in;
  wire rst_cpllpd;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;

  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(cpllpd),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllrst),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_1__0 
       (.I0(cpllpd),
        .I1(rst_cpllpd),
        .I2(p_0_in95_in),
        .O(CPLLPD0));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_2__0 
       (.I0(cpllrst),
        .I1(RST_CPLLRESET),
        .I2(p_0_in93_in),
        .O(CPLLRESET0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_gtx_cpllpd_ovrd" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_gtx_cpllpd_ovrd_87
   (CPLLPD0,
    CPLLRESET0,
    gt_cpllpdrefclk,
    rst_cpllpd,
    p_0_in3_in,
    RST_CPLLRESET,
    p_0_in2_in);
  output CPLLPD0;
  output CPLLRESET0;
  input gt_cpllpdrefclk;
  input rst_cpllpd;
  input p_0_in3_in;
  input RST_CPLLRESET;
  input p_0_in2_in;

  wire CPLLPD0;
  wire CPLLRESET0;
  wire RST_CPLLRESET;
  wire cpllpd;
  wire \cpllpd_wait_reg[31]_srl32_n_1 ;
  wire \cpllpd_wait_reg[63]_srl32_n_1 ;
  wire \cpllpd_wait_reg[94]_srl31_n_0 ;
  wire \cpllreset_wait_reg[126]_srl31_n_0 ;
  wire \cpllreset_wait_reg[31]_srl32_n_1 ;
  wire \cpllreset_wait_reg[63]_srl32_n_1 ;
  wire \cpllreset_wait_reg[95]_srl32_n_1 ;
  wire cpllrst;
  wire gt_cpllpdrefclk;
  wire p_0_in2_in;
  wire p_0_in3_in;
  wire rst_cpllpd;
  wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ;
  wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ;

  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'hFFFFFFFF)) 
    \cpllpd_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllpd_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h7FFFFFFF)) 
    \cpllpd_wait_reg[94]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllpd_wait_reg[63]_srl32_n_1 ),
        .Q(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b1)) 
    \cpllpd_wait_reg[95] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllpd_wait_reg[94]_srl31_n_0 ),
        .Q(cpllpd),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[126]_srl31 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b0}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[95]_srl32_n_1 ),
        .Q(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ));
  (* equivalent_register_removal = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cpllreset_wait_reg[127] 
       (.C(gt_cpllpdrefclk),
        .CE(1'b1),
        .D(\cpllreset_wait_reg[126]_srl31_n_0 ),
        .Q(cpllrst),
        .R(1'b0));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h000000FF)) 
    \cpllreset_wait_reg[31]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(1'b0),
        .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[31]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[63]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[31]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[63]_srl32_n_1 ));
  (* srl_bus_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg " *) 
  (* srl_name = "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \cpllreset_wait_reg[95]_srl32 
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(1'b1),
        .CLK(gt_cpllpdrefclk),
        .D(\cpllreset_wait_reg[63]_srl32_n_1 ),
        .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ),
        .Q31(\cpllreset_wait_reg[95]_srl32_n_1 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_1 
       (.I0(cpllpd),
        .I1(rst_cpllpd),
        .I2(p_0_in3_in),
        .O(CPLLPD0));
  LUT3 #(
    .INIT(8'hFE)) 
    \gtx_channel.gtxe2_channel_i_i_2 
       (.I0(cpllrst),
        .I1(RST_CPLLRESET),
        .I2(p_0_in2_in),
        .O(CPLLRESET0));
endmodule

(* CFG_CTL_IF = "TRUE" *) (* CFG_FC_IF = "TRUE" *) (* CFG_MGMT_IF = "FALSE" *) 
(* CFG_STATUS_IF = "TRUE" *) (* C_DATA_WIDTH = "64" *) (* ERR_REPORTING_IF = "FALSE" *) 
(* EXT_CH_GT_DRP = "FALSE" *) (* EXT_PIPE_INTERFACE = "FALSE" *) (* EXT_STARTUP_PRIMITIVE = "FALSE" *) 
(* KEEP_WIDTH = "8" *) (* LINK_CAP_MAX_LINK_WIDTH = "8" *) (* ORIG_REF_NAME = "PCIeGen1x8If64_pcie2_top" *) 
(* PCIE_ASYNC_EN = "FALSE" *) (* PCIE_EXT_CLK = "FALSE" *) (* PCIE_EXT_GT_COMMON = "FALSE" *) 
(* PIPE_SIM = "FALSE" *) (* PL_INTERFACE = "FALSE" *) (* RCV_MSG_IF = "FALSE" *) 
(* SHARED_LOGIC_IN_CORE = "FALSE" *) (* TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE" *) (* bar_0 = "FFFFFC00" *) 
(* bar_1 = "00000000" *) (* bar_2 = "00000000" *) (* bar_3 = "00000000" *) 
(* bar_4 = "00000000" *) (* bar_5 = "00000000" *) (* bram_lat = "0" *) 
(* c_aer_base_ptr = "000" *) (* c_aer_cap_ecrc_check_capable = "FALSE" *) (* c_aer_cap_ecrc_gen_capable = "FALSE" *) 
(* c_aer_cap_multiheader = "FALSE" *) (* c_aer_cap_nextptr = "000" *) (* c_aer_cap_on = "FALSE" *) 
(* c_aer_cap_optional_err_support = "000000" *) (* c_aer_cap_permit_rooterr_update = "FALSE" *) (* c_buf_opt_bma = "FALSE" *) 
(* c_component_name = "PCIeGen1x8If64" *) (* c_cpl_inf = "TRUE" *) (* c_cpl_infinite = "TRUE" *) 
(* c_cpl_timeout_disable_sup = "FALSE" *) (* c_cpl_timeout_range = "0010" *) (* c_cpl_timeout_ranges_sup = "2" *) 
(* c_d1_support = "FALSE" *) (* c_d2_support = "FALSE" *) (* c_de_emph = "FALSE" *) 
(* c_dev_cap2_ari_forwarding_supported = "FALSE" *) (* c_dev_cap2_atomicop32_completer_supported = "FALSE" *) (* c_dev_cap2_atomicop64_completer_supported = "FALSE" *) 
(* c_dev_cap2_atomicop_routing_supported = "FALSE" *) (* c_dev_cap2_cas128_completer_supported = "FALSE" *) (* c_dev_cap2_tph_completer_supported = "00" *) 
(* c_dev_control_ext_tag_default = "FALSE" *) (* c_dev_port_type = "0" *) (* c_dis_lane_reverse = "TRUE" *) 
(* c_disable_rx_poisoned_resp = "FALSE" *) (* c_disable_scrambling = "FALSE" *) (* c_disable_tx_aspm_l0s = "FALSE" *) 
(* c_dll_lnk_actv_cap = "FALSE" *) (* c_dsi_bool = "FALSE" *) (* c_dsn_base_ptr = "100" *) 
(* c_dsn_cap_enabled = "TRUE" *) (* c_dsn_next_ptr = "000" *) (* c_enable_msg_route = "00000000000" *) 
(* c_ep_l0s_accpt_lat = "0" *) (* c_ep_l1_accpt_lat = "7" *) (* c_ext_pci_cfg_space_addr = "3FF" *) 
(* c_external_clocking = "TRUE" *) (* c_fc_cpld = "850" *) (* c_fc_cplh = "72" *) 
(* c_fc_npd = "8" *) (* c_fc_nph = "4" *) (* c_fc_pd = "64" *) 
(* c_fc_ph = "4" *) (* c_gen1 = "FALSE" *) (* c_header_type = "00" *) 
(* c_hw_auton_spd_disable = "FALSE" *) (* c_int_width = "64" *) (* c_last_cfg_dw = "10C" *) 
(* c_link_cap_aspm_optionality = "FALSE" *) (* c_ll_ack_timeout = "0000" *) (* c_ll_ack_timeout_enable = "FALSE" *) 
(* c_ll_ack_timeout_function = "0" *) (* c_ll_replay_timeout = "0000" *) (* c_ll_replay_timeout_enable = "FALSE" *) 
(* c_ll_replay_timeout_func = "1" *) (* c_lnk_bndwdt_notif = "FALSE" *) (* c_msi = "0" *) 
(* c_msi_64b_addr = "TRUE" *) (* c_msi_cap_on = "TRUE" *) (* c_msi_mult_msg_extn = "0" *) 
(* c_msi_per_vctr_mask_cap = "FALSE" *) (* c_msix_cap_on = "FALSE" *) (* c_msix_next_ptr = "00" *) 
(* c_msix_pba_bir = "0" *) (* c_msix_pba_offset = "0" *) (* c_msix_table_bir = "0" *) 
(* c_msix_table_offset = "0" *) (* c_msix_table_size = "000" *) (* c_pci_cfg_space_addr = "3F" *) 
(* c_pcie_blk_locn = "3" *) (* c_pcie_cap_next_ptr = "00" *) (* c_pcie_cap_slot_implemented = "FALSE" *) 
(* c_pcie_dbg_ports = "TRUE" *) (* c_pcie_fast_config = "0" *) (* c_perf_level_high = "TRUE" *) 
(* c_phantom_functions = "0" *) (* c_pm_cap_next_ptr = "48" *) (* c_pme_support = "0F" *) 
(* c_rbar_base_ptr = "000" *) (* c_rbar_cap_control_encodedbar0 = "00" *) (* c_rbar_cap_control_encodedbar1 = "00" *) 
(* c_rbar_cap_control_encodedbar2 = "00" *) (* c_rbar_cap_control_encodedbar3 = "00" *) (* c_rbar_cap_control_encodedbar4 = "00" *) 
(* c_rbar_cap_control_encodedbar5 = "00" *) (* c_rbar_cap_index0 = "0" *) (* c_rbar_cap_index1 = "0" *) 
(* c_rbar_cap_index2 = "0" *) (* c_rbar_cap_index3 = "0" *) (* c_rbar_cap_index4 = "0" *) 
(* c_rbar_cap_index5 = "0" *) (* c_rbar_cap_nextptr = "000" *) (* c_rbar_cap_on = "FALSE" *) 
(* c_rbar_cap_sup0 = "00001" *) (* c_rbar_cap_sup1 = "00001" *) (* c_rbar_cap_sup2 = "00001" *) 
(* c_rbar_cap_sup3 = "00001" *) (* c_rbar_cap_sup4 = "00001" *) (* c_rbar_cap_sup5 = "00001" *) 
(* c_rbar_num = "0" *) (* c_rcb = "0" *) (* c_recrc_check = "0" *) 
(* c_recrc_check_trim = "FALSE" *) (* c_rev_gt_order = "FALSE" *) (* c_root_cap_crs = "FALSE" *) 
(* c_rx_raddr_lat = "0" *) (* c_rx_ram_limit = "7FF" *) (* c_rx_rdata_lat = "2" *) 
(* c_rx_write_lat = "0" *) (* c_silicon_rev = "2" *) (* c_slot_cap_attn_butn = "FALSE" *) 
(* c_slot_cap_attn_ind = "FALSE" *) (* c_slot_cap_elec_interlock = "FALSE" *) (* c_slot_cap_hotplug_cap = "FALSE" *) 
(* c_slot_cap_hotplug_surprise = "FALSE" *) (* c_slot_cap_mrl = "FALSE" *) (* c_slot_cap_no_cmd_comp_sup = "FALSE" *) 
(* c_slot_cap_physical_slot_num = "0" *) (* c_slot_cap_pwr_ctrl = "FALSE" *) (* c_slot_cap_pwr_ind = "FALSE" *) 
(* c_slot_cap_pwr_limit_scale = "0" *) (* c_slot_cap_pwr_limit_value = "0" *) (* c_surprise_dn_err_cap = "FALSE" *) 
(* c_trgt_lnk_spd = "0" *) (* c_trn_np_fc = "TRUE" *) (* c_tx_last_tlp = "29" *) 
(* c_tx_raddr_lat = "0" *) (* c_tx_rdata_lat = "2" *) (* c_tx_write_lat = "0" *) 
(* c_upconfig_capable = "TRUE" *) (* c_upstream_facing = "TRUE" *) (* c_ur_atomic = "FALSE" *) 
(* c_ur_inv_req = "TRUE" *) (* c_ur_prs_response = "TRUE" *) (* c_vc_base_ptr = "000" *) 
(* c_vc_cap_enabled = "FALSE" *) (* c_vc_cap_reject_snoop = "FALSE" *) (* c_vc_next_ptr = "000" *) 
(* c_vsec_base_ptr = "000" *) (* c_vsec_cap_enabled = "FALSE" *) (* c_vsec_next_ptr = "000" *) 
(* c_xlnx_ref_board = "VC707" *) (* cap_ver = "2" *) (* cardbus_cis_ptr = "00000000" *) 
(* class_code = "058000" *) (* cmps = "2" *) (* con_scl_fctr_d0_state = "0" *) 
(* con_scl_fctr_d1_state = "0" *) (* con_scl_fctr_d2_state = "0" *) (* con_scl_fctr_d3_state = "0" *) 
(* cost_table = "1" *) (* d1_sup = "0" *) (* d2_sup = "0" *) 
(* dev_id = "7018" *) (* dev_port_type = "0000" *) (* dis_scl_fctr_d0_state = "0" *) 
(* dis_scl_fctr_d1_state = "0" *) (* dis_scl_fctr_d2_state = "0" *) (* dis_scl_fctr_d3_state = "0" *) 
(* downgradeipidentifiedwarnings = "yes" *) (* dsi = "0" *) (* ep_l0s_accpt_lat = "000" *) 
(* ep_l1_accpt_lat = "111" *) (* ext_tag_fld_sup = "TRUE" *) (* int_pin = "0" *) 
(* intx = "FALSE" *) (* max_lnk_spd = "1" *) (* max_lnk_wdt = "001000" *) 
(* mps = "010" *) (* no_soft_rst = "TRUE" *) (* pci_exp_int_freq = "3" *) 
(* pci_exp_ref_freq = "0" *) (* phantm_func_sup = "00" *) (* pme_sup = "0F" *) 
(* pwr_con_d0_state = "00" *) (* pwr_con_d1_state = "00" *) (* pwr_con_d2_state = "00" *) 
(* pwr_con_d3_state = "00" *) (* pwr_dis_d0_state = "00" *) (* pwr_dis_d1_state = "00" *) 
(* pwr_dis_d2_state = "00" *) (* pwr_dis_d3_state = "00" *) (* rev_id = "00" *) 
(* slot_clk = "TRUE" *) (* subsys_id = "0007" *) (* subsys_ven_id = "10EE" *) 
(* ven_id = "10EE" *) (* xrom_bar = "00000000" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie2_top
   (pci_exp_txp,
    pci_exp_txn,
    pci_exp_rxp,
    pci_exp_rxn,
    int_pclk_out_slave,
    int_pipe_rxusrclk_out,
    int_rxoutclk_out,
    int_dclk_out,
    int_userclk1_out,
    int_userclk2_out,
    int_oobclk_out,
    int_mmcm_lock_out,
    int_qplllock_out,
    int_qplloutclk_out,
    int_qplloutrefclk_out,
    int_pclk_sel_slave,
    pipe_pclk_in,
    pipe_rxusrclk_in,
    pipe_rxoutclk_in,
    pipe_dclk_in,
    pipe_userclk1_in,
    pipe_userclk2_in,
    pipe_oobclk_in,
    pipe_mmcm_lock_in,
    pipe_txoutclk_out,
    pipe_rxoutclk_out,
    pipe_pclk_sel_out,
    pipe_gen3_out,
    user_clk_out,
    user_reset_out,
    user_lnk_up,
    user_app_rdy,
    tx_buf_av,
    tx_cfg_req,
    tx_err_drop,
    s_axis_tx_tready,
    s_axis_tx_tdata,
    s_axis_tx_tkeep,
    s_axis_tx_tlast,
    s_axis_tx_tvalid,
    s_axis_tx_tuser,
    tx_cfg_gnt,
    m_axis_rx_tdata,
    m_axis_rx_tkeep,
    m_axis_rx_tlast,
    m_axis_rx_tvalid,
    m_axis_rx_tready,
    m_axis_rx_tuser,
    rx_np_ok,
    rx_np_req,
    fc_cpld,
    fc_cplh,
    fc_npd,
    fc_nph,
    fc_pd,
    fc_ph,
    fc_sel,
    cfg_mgmt_do,
    cfg_mgmt_rd_wr_done,
    cfg_status,
    cfg_command,
    cfg_dstatus,
    cfg_dcommand,
    cfg_lstatus,
    cfg_lcommand,
    cfg_dcommand2,
    cfg_pcie_link_state,
    cfg_pmcsr_pme_en,
    cfg_pmcsr_powerstate,
    cfg_pmcsr_pme_status,
    cfg_received_func_lvl_rst,
    cfg_mgmt_di,
    cfg_mgmt_byte_en,
    cfg_mgmt_dwaddr,
    cfg_mgmt_wr_en,
    cfg_mgmt_rd_en,
    cfg_mgmt_wr_readonly,
    cfg_err_ecrc,
    cfg_err_ur,
    cfg_err_cpl_timeout,
    cfg_err_cpl_unexpect,
    cfg_err_cpl_abort,
    cfg_err_posted,
    cfg_err_cor,
    cfg_err_atomic_egress_blocked,
    cfg_err_internal_cor,
    cfg_err_malformed,
    cfg_err_mc_blocked,
    cfg_err_poisoned,
    cfg_err_norecovery,
    cfg_err_tlp_cpl_header,
    cfg_err_cpl_rdy,
    cfg_err_locked,
    cfg_err_acs,
    cfg_err_internal_uncor,
    cfg_trn_pending,
    cfg_pm_halt_aspm_l0s,
    cfg_pm_halt_aspm_l1,
    cfg_pm_force_state_en,
    cfg_pm_force_state,
    cfg_dsn,
    cfg_interrupt,
    cfg_interrupt_rdy,
    cfg_interrupt_assert,
    cfg_interrupt_di,
    cfg_interrupt_do,
    cfg_interrupt_mmenable,
    cfg_interrupt_msienable,
    cfg_interrupt_msixenable,
    cfg_interrupt_msixfm,
    cfg_interrupt_stat,
    cfg_pciecap_interrupt_msgnum,
    cfg_to_turnoff,
    cfg_turnoff_ok,
    cfg_bus_number,
    cfg_device_number,
    cfg_function_number,
    cfg_pm_wake,
    cfg_pm_send_pme_to,
    cfg_ds_bus_number,
    cfg_ds_device_number,
    cfg_ds_function_number,
    cfg_mgmt_wr_rw1c_as_rw,
    cfg_msg_received,
    cfg_msg_data,
    cfg_bridge_serr_en,
    cfg_slot_control_electromech_il_ctl_pulse,
    cfg_root_control_syserr_corr_err_en,
    cfg_root_control_syserr_non_fatal_err_en,
    cfg_root_control_syserr_fatal_err_en,
    cfg_root_control_pme_int_en,
    cfg_aer_rooterr_corr_err_reporting_en,
    cfg_aer_rooterr_non_fatal_err_reporting_en,
    cfg_aer_rooterr_fatal_err_reporting_en,
    cfg_aer_rooterr_corr_err_received,
    cfg_aer_rooterr_non_fatal_err_received,
    cfg_aer_rooterr_fatal_err_received,
    cfg_msg_received_err_cor,
    cfg_msg_received_err_non_fatal,
    cfg_msg_received_err_fatal,
    cfg_msg_received_pm_as_nak,
    cfg_msg_received_pm_pme,
    cfg_msg_received_pme_to_ack,
    cfg_msg_received_assert_int_a,
    cfg_msg_received_assert_int_b,
    cfg_msg_received_assert_int_c,
    cfg_msg_received_assert_int_d,
    cfg_msg_received_deassert_int_a,
    cfg_msg_received_deassert_int_b,
    cfg_msg_received_deassert_int_c,
    cfg_msg_received_deassert_int_d,
    cfg_msg_received_setslotpowerlimit,
    pl_directed_link_change,
    pl_directed_link_width,
    pl_directed_link_speed,
    pl_directed_link_auton,
    pl_upstream_prefer_deemph,
    pl_sel_lnk_rate,
    pl_sel_lnk_width,
    pl_ltssm_state,
    pl_lane_reversal_mode,
    pl_phy_lnk_up,
    pl_tx_pm_state,
    pl_rx_pm_state,
    pl_link_upcfg_cap,
    pl_link_gen2_cap,
    pl_link_partner_gen2_supported,
    pl_initial_link_width,
    pl_directed_change_done,
    pl_received_hot_rst,
    pl_transmit_hot_rst,
    pl_downstream_deemph_source,
    cfg_err_aer_headerlog,
    cfg_aer_interrupt_msgnum,
    cfg_err_aer_headerlog_set,
    cfg_aer_ecrc_check_en,
    cfg_aer_ecrc_gen_en,
    cfg_vc_tcvc_map,
    sys_clk,
    sys_rst_n,
    pipe_mmcm_rst_n,
    common_commands_in,
    pipe_rx_0_sigs,
    pipe_rx_1_sigs,
    pipe_rx_2_sigs,
    pipe_rx_3_sigs,
    pipe_rx_4_sigs,
    pipe_rx_5_sigs,
    pipe_rx_6_sigs,
    pipe_rx_7_sigs,
    common_commands_out,
    pipe_tx_0_sigs,
    pipe_tx_1_sigs,
    pipe_tx_2_sigs,
    pipe_tx_3_sigs,
    pipe_tx_4_sigs,
    pipe_tx_5_sigs,
    pipe_tx_6_sigs,
    pipe_tx_7_sigs,
    startup_eos_in,
    startup_cfgclk,
    startup_cfgmclk,
    startup_eos,
    startup_preq,
    startup_clk,
    startup_gsr,
    startup_gts,
    startup_keyclearb,
    startup_pack,
    startup_usrcclko,
    startup_usrcclkts,
    startup_usrdoneo,
    startup_usrdonets,
    icap_clk,
    icap_csib,
    icap_rdwrb,
    icap_i,
    icap_o,
    qpll_drp_crscode,
    qpll_drp_fsm,
    qpll_drp_done,
    qpll_drp_reset,
    qpll_qplllock,
    qpll_qplloutclk,
    qpll_qplloutrefclk,
    qpll_qplld,
    qpll_qpllreset,
    qpll_drp_clk,
    qpll_drp_rst_n,
    qpll_drp_ovrd,
    qpll_drp_gen3,
    qpll_drp_start,
    pipe_txprbssel,
    pipe_rxprbssel,
    pipe_txprbsforceerr,
    pipe_rxprbscntreset,
    pipe_loopback,
    pipe_rxprbserr,
    pipe_txinhibit,
    pipe_rst_fsm,
    pipe_qrst_fsm,
    pipe_rate_fsm,
    pipe_sync_fsm_tx,
    pipe_sync_fsm_rx,
    pipe_drp_fsm,
    pipe_rst_idle,
    pipe_qrst_idle,
    pipe_rate_idle,
    pipe_eyescandataerror,
    pipe_rxstatus,
    pipe_dmonitorout,
    pipe_cpll_lock,
    pipe_qpll_lock,
    pipe_rxpmaresetdone,
    pipe_rxbufstatus,
    pipe_txphaligndone,
    pipe_txphinitdone,
    pipe_txdlysresetdone,
    pipe_rxphaligndone,
    pipe_rxdlysresetdone,
    pipe_rxsyncdone,
    pipe_rxdisperr,
    pipe_rxnotintable,
    pipe_rxcommadet,
    gt_ch_drp_rdy,
    pipe_debug_0,
    pipe_debug_1,
    pipe_debug_2,
    pipe_debug_3,
    pipe_debug_4,
    pipe_debug_5,
    pipe_debug_6,
    pipe_debug_7,
    pipe_debug_8,
    pipe_debug_9,
    pipe_debug,
    ext_ch_gt_drpclk,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpdi,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdo,
    ext_ch_gt_drprdy,
    pcie_drp_clk,
    pcie_drp_en,
    pcie_drp_we,
    pcie_drp_addr,
    pcie_drp_di,
    pcie_drp_do,
    pcie_drp_rdy);
  output [7:0]pci_exp_txp;
  output [7:0]pci_exp_txn;
  input [7:0]pci_exp_rxp;
  input [7:0]pci_exp_rxn;
  output int_pclk_out_slave;
  output int_pipe_rxusrclk_out;
  output [7:0]int_rxoutclk_out;
  output int_dclk_out;
  output int_userclk1_out;
  output int_userclk2_out;
  output int_oobclk_out;
  output int_mmcm_lock_out;
  output [1:0]int_qplllock_out;
  output [1:0]int_qplloutclk_out;
  output [1:0]int_qplloutrefclk_out;
  input [7:0]int_pclk_sel_slave;
  input pipe_pclk_in;
  input pipe_rxusrclk_in;
  input [7:0]pipe_rxoutclk_in;
  input pipe_dclk_in;
  input pipe_userclk1_in;
  input pipe_userclk2_in;
  input pipe_oobclk_in;
  input pipe_mmcm_lock_in;
  output pipe_txoutclk_out;
  output [7:0]pipe_rxoutclk_out;
  output [7:0]pipe_pclk_sel_out;
  output pipe_gen3_out;
  output user_clk_out;
  output user_reset_out;
  output user_lnk_up;
  output user_app_rdy;
  output [5:0]tx_buf_av;
  output tx_cfg_req;
  output tx_err_drop;
  output s_axis_tx_tready;
  input [63:0]s_axis_tx_tdata;
  input [7:0]s_axis_tx_tkeep;
  input s_axis_tx_tlast;
  input s_axis_tx_tvalid;
  input [3:0]s_axis_tx_tuser;
  input tx_cfg_gnt;
  output [63:0]m_axis_rx_tdata;
  output [7:0]m_axis_rx_tkeep;
  output m_axis_rx_tlast;
  output m_axis_rx_tvalid;
  input m_axis_rx_tready;
  output [21:0]m_axis_rx_tuser;
  input rx_np_ok;
  input rx_np_req;
  output [11:0]fc_cpld;
  output [7:0]fc_cplh;
  output [11:0]fc_npd;
  output [7:0]fc_nph;
  output [11:0]fc_pd;
  output [7:0]fc_ph;
  input [2:0]fc_sel;
  output [31:0]cfg_mgmt_do;
  output cfg_mgmt_rd_wr_done;
  output [15:0]cfg_status;
  output [15:0]cfg_command;
  output [15:0]cfg_dstatus;
  output [15:0]cfg_dcommand;
  output [15:0]cfg_lstatus;
  output [15:0]cfg_lcommand;
  output [15:0]cfg_dcommand2;
  output [2:0]cfg_pcie_link_state;
  output cfg_pmcsr_pme_en;
  output [1:0]cfg_pmcsr_powerstate;
  output cfg_pmcsr_pme_status;
  output cfg_received_func_lvl_rst;
  input [31:0]cfg_mgmt_di;
  input [3:0]cfg_mgmt_byte_en;
  input [9:0]cfg_mgmt_dwaddr;
  input cfg_mgmt_wr_en;
  input cfg_mgmt_rd_en;
  input cfg_mgmt_wr_readonly;
  input cfg_err_ecrc;
  input cfg_err_ur;
  input cfg_err_cpl_timeout;
  input cfg_err_cpl_unexpect;
  input cfg_err_cpl_abort;
  input cfg_err_posted;
  input cfg_err_cor;
  input cfg_err_atomic_egress_blocked;
  input cfg_err_internal_cor;
  input cfg_err_malformed;
  input cfg_err_mc_blocked;
  input cfg_err_poisoned;
  input cfg_err_norecovery;
  input [47:0]cfg_err_tlp_cpl_header;
  output cfg_err_cpl_rdy;
  input cfg_err_locked;
  input cfg_err_acs;
  input cfg_err_internal_uncor;
  input cfg_trn_pending;
  input cfg_pm_halt_aspm_l0s;
  input cfg_pm_halt_aspm_l1;
  input cfg_pm_force_state_en;
  input [1:0]cfg_pm_force_state;
  input [63:0]cfg_dsn;
  input cfg_interrupt;
  output cfg_interrupt_rdy;
  input cfg_interrupt_assert;
  input [7:0]cfg_interrupt_di;
  output [7:0]cfg_interrupt_do;
  output [2:0]cfg_interrupt_mmenable;
  output cfg_interrupt_msienable;
  output cfg_interrupt_msixenable;
  output cfg_interrupt_msixfm;
  input cfg_interrupt_stat;
  input [4:0]cfg_pciecap_interrupt_msgnum;
  output cfg_to_turnoff;
  input cfg_turnoff_ok;
  output [7:0]cfg_bus_number;
  output [4:0]cfg_device_number;
  output [2:0]cfg_function_number;
  input cfg_pm_wake;
  input cfg_pm_send_pme_to;
  input [7:0]cfg_ds_bus_number;
  input [4:0]cfg_ds_device_number;
  input [2:0]cfg_ds_function_number;
  input cfg_mgmt_wr_rw1c_as_rw;
  output cfg_msg_received;
  output [15:0]cfg_msg_data;
  output cfg_bridge_serr_en;
  output cfg_slot_control_electromech_il_ctl_pulse;
  output cfg_root_control_syserr_corr_err_en;
  output cfg_root_control_syserr_non_fatal_err_en;
  output cfg_root_control_syserr_fatal_err_en;
  output cfg_root_control_pme_int_en;
  output cfg_aer_rooterr_corr_err_reporting_en;
  output cfg_aer_rooterr_non_fatal_err_reporting_en;
  output cfg_aer_rooterr_fatal_err_reporting_en;
  output cfg_aer_rooterr_corr_err_received;
  output cfg_aer_rooterr_non_fatal_err_received;
  output cfg_aer_rooterr_fatal_err_received;
  output cfg_msg_received_err_cor;
  output cfg_msg_received_err_non_fatal;
  output cfg_msg_received_err_fatal;
  output cfg_msg_received_pm_as_nak;
  output cfg_msg_received_pm_pme;
  output cfg_msg_received_pme_to_ack;
  output cfg_msg_received_assert_int_a;
  output cfg_msg_received_assert_int_b;
  output cfg_msg_received_assert_int_c;
  output cfg_msg_received_assert_int_d;
  output cfg_msg_received_deassert_int_a;
  output cfg_msg_received_deassert_int_b;
  output cfg_msg_received_deassert_int_c;
  output cfg_msg_received_deassert_int_d;
  output cfg_msg_received_setslotpowerlimit;
  input [1:0]pl_directed_link_change;
  input [1:0]pl_directed_link_width;
  input pl_directed_link_speed;
  input pl_directed_link_auton;
  input pl_upstream_prefer_deemph;
  output pl_sel_lnk_rate;
  output [1:0]pl_sel_lnk_width;
  output [5:0]pl_ltssm_state;
  output [1:0]pl_lane_reversal_mode;
  output pl_phy_lnk_up;
  output [2:0]pl_tx_pm_state;
  output [1:0]pl_rx_pm_state;
  output pl_link_upcfg_cap;
  output pl_link_gen2_cap;
  output pl_link_partner_gen2_supported;
  output [2:0]pl_initial_link_width;
  output pl_directed_change_done;
  output pl_received_hot_rst;
  input pl_transmit_hot_rst;
  input pl_downstream_deemph_source;
  input [127:0]cfg_err_aer_headerlog;
  input [4:0]cfg_aer_interrupt_msgnum;
  output cfg_err_aer_headerlog_set;
  output cfg_aer_ecrc_check_en;
  output cfg_aer_ecrc_gen_en;
  output [6:0]cfg_vc_tcvc_map;
  input sys_clk;
  input sys_rst_n;
  input pipe_mmcm_rst_n;
  input [3:0]common_commands_in;
  input [24:0]pipe_rx_0_sigs;
  input [24:0]pipe_rx_1_sigs;
  input [24:0]pipe_rx_2_sigs;
  input [24:0]pipe_rx_3_sigs;
  input [24:0]pipe_rx_4_sigs;
  input [24:0]pipe_rx_5_sigs;
  input [24:0]pipe_rx_6_sigs;
  input [24:0]pipe_rx_7_sigs;
  output [11:0]common_commands_out;
  output [22:0]pipe_tx_0_sigs;
  output [22:0]pipe_tx_1_sigs;
  output [22:0]pipe_tx_2_sigs;
  output [22:0]pipe_tx_3_sigs;
  output [22:0]pipe_tx_4_sigs;
  output [22:0]pipe_tx_5_sigs;
  output [22:0]pipe_tx_6_sigs;
  output [22:0]pipe_tx_7_sigs;
  input startup_eos_in;
  output startup_cfgclk;
  output startup_cfgmclk;
  output startup_eos;
  output startup_preq;
  input startup_clk;
  input startup_gsr;
  input startup_gts;
  input startup_keyclearb;
  input startup_pack;
  input startup_usrcclko;
  input startup_usrcclkts;
  input startup_usrdoneo;
  input startup_usrdonets;
  input icap_clk;
  input icap_csib;
  input icap_rdwrb;
  input [31:0]icap_i;
  output [31:0]icap_o;
  input [11:0]qpll_drp_crscode;
  input [17:0]qpll_drp_fsm;
  input [1:0]qpll_drp_done;
  input [1:0]qpll_drp_reset;
  input [1:0]qpll_qplllock;
  input [1:0]qpll_qplloutclk;
  input [1:0]qpll_qplloutrefclk;
  output qpll_qplld;
  output [1:0]qpll_qpllreset;
  output qpll_drp_clk;
  output qpll_drp_rst_n;
  output qpll_drp_ovrd;
  output qpll_drp_gen3;
  output qpll_drp_start;
  input [2:0]pipe_txprbssel;
  input [2:0]pipe_rxprbssel;
  input pipe_txprbsforceerr;
  input pipe_rxprbscntreset;
  input [2:0]pipe_loopback;
  output [7:0]pipe_rxprbserr;
  input [7:0]pipe_txinhibit;
  output [4:0]pipe_rst_fsm;
  output [11:0]pipe_qrst_fsm;
  output [39:0]pipe_rate_fsm;
  output [47:0]pipe_sync_fsm_tx;
  output [55:0]pipe_sync_fsm_rx;
  output [55:0]pipe_drp_fsm;
  output pipe_rst_idle;
  output pipe_qrst_idle;
  output pipe_rate_idle;
  output [7:0]pipe_eyescandataerror;
  output [23:0]pipe_rxstatus;
  output [119:0]pipe_dmonitorout;
  output [7:0]pipe_cpll_lock;
  output [1:0]pipe_qpll_lock;
  output [7:0]pipe_rxpmaresetdone;
  output [23:0]pipe_rxbufstatus;
  output [7:0]pipe_txphaligndone;
  output [7:0]pipe_txphinitdone;
  output [7:0]pipe_txdlysresetdone;
  output [7:0]pipe_rxphaligndone;
  output [7:0]pipe_rxdlysresetdone;
  output [7:0]pipe_rxsyncdone;
  output [63:0]pipe_rxdisperr;
  output [63:0]pipe_rxnotintable;
  output [7:0]pipe_rxcommadet;
  output [7:0]gt_ch_drp_rdy;
  output [7:0]pipe_debug_0;
  output [7:0]pipe_debug_1;
  output [7:0]pipe_debug_2;
  output [7:0]pipe_debug_3;
  output [7:0]pipe_debug_4;
  output [7:0]pipe_debug_5;
  output [7:0]pipe_debug_6;
  output [7:0]pipe_debug_7;
  output [7:0]pipe_debug_8;
  output [7:0]pipe_debug_9;
  output [31:0]pipe_debug;
  output ext_ch_gt_drpclk;
  input [71:0]ext_ch_gt_drpaddr;
  input [7:0]ext_ch_gt_drpen;
  input [127:0]ext_ch_gt_drpdi;
  input [7:0]ext_ch_gt_drpwe;
  output [127:0]ext_ch_gt_drpdo;
  output [7:0]ext_ch_gt_drprdy;
  input pcie_drp_clk;
  input pcie_drp_en;
  input pcie_drp_we;
  input [8:0]pcie_drp_addr;
  input [15:0]pcie_drp_di;
  output [15:0]pcie_drp_do;
  output pcie_drp_rdy;

  wire \<const0> ;
  wire \<const1> ;
  wire cfg_aer_ecrc_check_en;
  wire cfg_aer_ecrc_gen_en;
  wire [4:0]cfg_aer_interrupt_msgnum;
  wire cfg_aer_rooterr_corr_err_received;
  wire cfg_aer_rooterr_corr_err_reporting_en;
  wire cfg_aer_rooterr_fatal_err_received;
  wire cfg_aer_rooterr_fatal_err_reporting_en;
  wire cfg_aer_rooterr_non_fatal_err_received;
  wire cfg_aer_rooterr_non_fatal_err_reporting_en;
  wire cfg_bridge_serr_en;
  wire [7:0]cfg_bus_number;
  wire [10:0]\^cfg_command ;
  wire [14:0]\^cfg_dcommand ;
  wire [11:0]\^cfg_dcommand2 ;
  wire [4:0]cfg_device_number;
  wire [7:0]cfg_ds_bus_number;
  wire [4:0]cfg_ds_device_number;
  wire [2:0]cfg_ds_function_number;
  wire [63:0]cfg_dsn;
  wire [3:0]\^cfg_dstatus ;
  wire cfg_err_acs;
  wire [127:0]cfg_err_aer_headerlog;
  wire cfg_err_aer_headerlog_set;
  wire cfg_err_atomic_egress_blocked;
  wire cfg_err_cor;
  wire cfg_err_cpl_abort;
  wire cfg_err_cpl_rdy;
  wire cfg_err_cpl_timeout;
  wire cfg_err_cpl_unexpect;
  wire cfg_err_ecrc;
  wire cfg_err_internal_cor;
  wire cfg_err_internal_uncor;
  wire cfg_err_locked;
  wire cfg_err_malformed;
  wire cfg_err_mc_blocked;
  wire cfg_err_norecovery;
  wire cfg_err_poisoned;
  wire cfg_err_posted;
  wire [47:0]cfg_err_tlp_cpl_header;
  wire cfg_err_ur;
  wire [2:0]cfg_function_number;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire [7:0]cfg_interrupt_di;
  wire [7:0]cfg_interrupt_do;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_msixenable;
  wire cfg_interrupt_msixfm;
  wire cfg_interrupt_rdy;
  wire cfg_interrupt_stat;
  wire [11:0]\^cfg_lcommand ;
  wire [15:0]\^cfg_lstatus ;
  wire [3:0]cfg_mgmt_byte_en;
  wire [31:0]cfg_mgmt_di;
  wire [31:0]cfg_mgmt_do;
  wire [9:0]cfg_mgmt_dwaddr;
  wire cfg_mgmt_rd_en;
  wire cfg_mgmt_rd_wr_done;
  wire cfg_mgmt_wr_en;
  wire cfg_mgmt_wr_readonly;
  wire cfg_mgmt_wr_rw1c_as_rw;
  wire [15:0]cfg_msg_data;
  wire cfg_msg_received;
  wire cfg_msg_received_assert_int_a;
  wire cfg_msg_received_assert_int_b;
  wire cfg_msg_received_assert_int_c;
  wire cfg_msg_received_assert_int_d;
  wire cfg_msg_received_deassert_int_a;
  wire cfg_msg_received_deassert_int_b;
  wire cfg_msg_received_deassert_int_c;
  wire cfg_msg_received_deassert_int_d;
  wire cfg_msg_received_err_cor;
  wire cfg_msg_received_err_fatal;
  wire cfg_msg_received_err_non_fatal;
  wire cfg_msg_received_pm_as_nak;
  wire cfg_msg_received_pm_pme;
  wire cfg_msg_received_pme_to_ack;
  wire cfg_msg_received_setslotpowerlimit;
  wire [2:0]cfg_pcie_link_state;
  wire [4:0]cfg_pciecap_interrupt_msgnum;
  wire [1:0]cfg_pm_force_state;
  wire cfg_pm_force_state_en;
  wire cfg_pm_halt_aspm_l0s;
  wire cfg_pm_halt_aspm_l1;
  wire cfg_pm_send_pme_to;
  wire cfg_pm_wake;
  wire cfg_pmcsr_pme_en;
  wire cfg_pmcsr_pme_status;
  wire [1:0]cfg_pmcsr_powerstate;
  wire cfg_received_func_lvl_rst;
  wire cfg_root_control_pme_int_en;
  wire cfg_root_control_syserr_corr_err_en;
  wire cfg_root_control_syserr_fatal_err_en;
  wire cfg_root_control_syserr_non_fatal_err_en;
  wire cfg_slot_control_electromech_il_ctl_pulse;
  wire cfg_to_turnoff;
  wire cfg_trn_pending;
  wire cfg_turnoff_ok;
  wire [6:0]cfg_vc_tcvc_map;
  wire [3:0]common_commands_in;
  wire [71:0]ext_ch_gt_drpaddr;
  wire ext_ch_gt_drpclk;
  wire [127:0]ext_ch_gt_drpdi;
  wire [127:0]ext_ch_gt_drpdo;
  wire [7:0]ext_ch_gt_drpen;
  wire [7:0]ext_ch_gt_drprdy;
  wire [7:0]ext_ch_gt_drpwe;
  wire [11:0]fc_cpld;
  wire [7:0]fc_cplh;
  wire [11:0]fc_npd;
  wire [7:0]fc_nph;
  wire [11:0]fc_pd;
  wire [7:0]fc_ph;
  wire [2:0]fc_sel;
  wire [7:0]gt_ch_drp_rdy;
  wire icap_clk;
  wire icap_csib;
  wire [31:0]icap_i;
  wire icap_rdwrb;
  wire int_mmcm_lock_out;
  wire [7:0]int_pclk_sel_slave;
  wire int_pipe_rxusrclk_out;
  wire [1:0]int_qplllock_out;
  wire [1:0]int_qplloutclk_out;
  wire [1:0]int_qplloutrefclk_out;
  wire int_userclk2_out;
  wire [63:0]m_axis_rx_tdata;
  wire [7:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [21:0]m_axis_rx_tuser;
  wire m_axis_rx_tvalid;
  wire [7:0]pci_exp_rxn;
  wire [7:0]pci_exp_rxp;
  wire [7:0]pci_exp_txn;
  wire [7:0]pci_exp_txp;
  wire [8:0]pcie_drp_addr;
  wire pcie_drp_clk;
  wire [15:0]pcie_drp_di;
  wire [15:0]pcie_drp_do;
  wire pcie_drp_en;
  wire pcie_drp_rdy;
  wire pcie_drp_we;
  wire [7:0]pipe_cpll_lock;
  wire pipe_dclk_in;
  wire [112:0]\^pipe_dmonitorout ;
  wire [23:0]\^pipe_drp_fsm ;
  wire [7:0]pipe_eyescandataerror;
  wire pipe_gen3_out;
  wire [2:0]pipe_loopback;
  wire pipe_mmcm_lock_in;
  wire pipe_mmcm_rst_n;
  wire pipe_oobclk_in;
  wire pipe_pclk_in;
  wire [7:0]pipe_pclk_sel_out;
  wire [3:0]\^pipe_qrst_fsm ;
  wire pipe_qrst_idle;
  wire [39:0]pipe_rate_fsm;
  wire pipe_rate_idle;
  wire [4:0]pipe_rst_fsm;
  wire pipe_rst_idle;
  wire [24:0]pipe_rx_0_sigs;
  wire [24:0]pipe_rx_1_sigs;
  wire [24:0]pipe_rx_2_sigs;
  wire [24:0]pipe_rx_3_sigs;
  wire [24:0]pipe_rx_4_sigs;
  wire [24:0]pipe_rx_5_sigs;
  wire [24:0]pipe_rx_6_sigs;
  wire [24:0]pipe_rx_7_sigs;
  wire [23:0]pipe_rxbufstatus;
  wire [7:0]pipe_rxcommadet;
  wire [63:0]pipe_rxdisperr;
  wire [7:0]pipe_rxdlysresetdone;
  wire [63:0]pipe_rxnotintable;
  wire [7:0]pipe_rxoutclk_in;
  wire [7:0]pipe_rxoutclk_out;
  wire [7:0]pipe_rxphaligndone;
  wire pipe_rxprbscntreset;
  wire [7:0]pipe_rxprbserr;
  wire [2:0]pipe_rxprbssel;
  wire [23:0]pipe_rxstatus;
  wire pipe_rxusrclk_in;
  wire [55:0]pipe_sync_fsm_rx;
  wire [47:0]pipe_sync_fsm_tx;
  wire [7:0]pipe_txdlysresetdone;
  wire [7:0]pipe_txinhibit;
  wire pipe_txoutclk_out;
  wire [7:0]pipe_txphaligndone;
  wire [7:0]pipe_txphinitdone;
  wire pipe_txprbsforceerr;
  wire [2:0]pipe_txprbssel;
  wire pipe_userclk1_in;
  wire pipe_userclk2_in;
  wire pl_directed_change_done;
  wire pl_directed_link_auton;
  wire [1:0]pl_directed_link_change;
  wire pl_directed_link_speed;
  wire [1:0]pl_directed_link_width;
  wire pl_downstream_deemph_source;
  wire [2:0]pl_initial_link_width;
  wire [1:0]pl_lane_reversal_mode;
  wire pl_link_gen2_cap;
  wire pl_link_partner_gen2_supported;
  wire pl_link_upcfg_cap;
  wire [5:0]pl_ltssm_state;
  wire pl_phy_lnk_up;
  wire pl_received_hot_rst;
  wire [1:0]pl_rx_pm_state;
  wire pl_sel_lnk_rate;
  wire [1:0]pl_sel_lnk_width;
  wire pl_transmit_hot_rst;
  wire [2:0]pl_tx_pm_state;
  wire pl_upstream_prefer_deemph;
  wire [11:0]qpll_drp_crscode;
  wire [1:0]qpll_drp_done;
  wire [17:0]qpll_drp_fsm;
  wire [1:0]qpll_drp_reset;
  wire [1:0]qpll_qplllock;
  wire [1:0]qpll_qplloutclk;
  wire [1:0]qpll_qplloutrefclk;
  wire rx_np_ok;
  wire rx_np_req;
  wire [63:0]s_axis_tx_tdata;
  wire [7:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tready;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire startup_clk;
  wire startup_eos_in;
  wire startup_gsr;
  wire startup_gts;
  wire startup_keyclearb;
  wire startup_pack;
  wire startup_usrcclko;
  wire startup_usrcclkts;
  wire startup_usrdoneo;
  wire startup_usrdonets;
  wire sys_clk;
  wire sys_rst_n;
  wire [5:0]tx_buf_av;
  wire tx_cfg_gnt;
  wire tx_cfg_req;
  wire tx_err_drop;
  wire user_lnk_up;
  wire user_reset_out;

  assign cfg_command[15] = \<const0> ;
  assign cfg_command[14] = \<const0> ;
  assign cfg_command[13] = \<const0> ;
  assign cfg_command[12] = \<const0> ;
  assign cfg_command[11] = \<const0> ;
  assign cfg_command[10] = \^cfg_command [10];
  assign cfg_command[9] = \<const0> ;
  assign cfg_command[8] = \^cfg_command [8];
  assign cfg_command[7] = \<const0> ;
  assign cfg_command[6] = \<const0> ;
  assign cfg_command[5] = \<const0> ;
  assign cfg_command[4] = \<const0> ;
  assign cfg_command[3] = \<const0> ;
  assign cfg_command[2:0] = \^cfg_command [2:0];
  assign cfg_dcommand[15] = \<const0> ;
  assign cfg_dcommand[14:0] = \^cfg_dcommand [14:0];
  assign cfg_dcommand2[15] = \<const0> ;
  assign cfg_dcommand2[14] = \<const0> ;
  assign cfg_dcommand2[13] = \<const0> ;
  assign cfg_dcommand2[12] = \<const0> ;
  assign cfg_dcommand2[11:0] = \^cfg_dcommand2 [11:0];
  assign cfg_dstatus[15] = \<const0> ;
  assign cfg_dstatus[14] = \<const0> ;
  assign cfg_dstatus[13] = \<const0> ;
  assign cfg_dstatus[12] = \<const0> ;
  assign cfg_dstatus[11] = \<const0> ;
  assign cfg_dstatus[10] = \<const0> ;
  assign cfg_dstatus[9] = \<const0> ;
  assign cfg_dstatus[8] = \<const0> ;
  assign cfg_dstatus[7] = \<const0> ;
  assign cfg_dstatus[6] = \<const0> ;
  assign cfg_dstatus[5] = cfg_trn_pending;
  assign cfg_dstatus[4] = \<const0> ;
  assign cfg_dstatus[3:0] = \^cfg_dstatus [3:0];
  assign cfg_lcommand[15] = \<const0> ;
  assign cfg_lcommand[14] = \<const0> ;
  assign cfg_lcommand[13] = \<const0> ;
  assign cfg_lcommand[12] = \<const0> ;
  assign cfg_lcommand[11:3] = \^cfg_lcommand [11:3];
  assign cfg_lcommand[2] = \<const0> ;
  assign cfg_lcommand[1:0] = \^cfg_lcommand [1:0];
  assign cfg_lstatus[15:13] = \^cfg_lstatus [15:13];
  assign cfg_lstatus[12] = \<const1> ;
  assign cfg_lstatus[11] = \^cfg_lstatus [11];
  assign cfg_lstatus[10] = \<const0> ;
  assign cfg_lstatus[9] = \<const0> ;
  assign cfg_lstatus[8] = \<const0> ;
  assign cfg_lstatus[7:4] = \^cfg_lstatus [7:4];
  assign cfg_lstatus[3] = \<const0> ;
  assign cfg_lstatus[2] = \<const0> ;
  assign cfg_lstatus[1:0] = \^cfg_lstatus [1:0];
  assign cfg_status[15] = \<const0> ;
  assign cfg_status[14] = \<const0> ;
  assign cfg_status[13] = \<const0> ;
  assign cfg_status[12] = \<const0> ;
  assign cfg_status[11] = \<const0> ;
  assign cfg_status[10] = \<const0> ;
  assign cfg_status[9] = \<const0> ;
  assign cfg_status[8] = \<const0> ;
  assign cfg_status[7] = \<const0> ;
  assign cfg_status[6] = \<const0> ;
  assign cfg_status[5] = \<const0> ;
  assign cfg_status[4] = \<const0> ;
  assign cfg_status[3] = \<const0> ;
  assign cfg_status[2] = \<const0> ;
  assign cfg_status[1] = \<const0> ;
  assign cfg_status[0] = \<const0> ;
  assign common_commands_out[11] = \<const0> ;
  assign common_commands_out[10] = \<const0> ;
  assign common_commands_out[9] = \<const0> ;
  assign common_commands_out[8] = \<const0> ;
  assign common_commands_out[7] = \<const0> ;
  assign common_commands_out[6] = \<const0> ;
  assign common_commands_out[5] = \<const0> ;
  assign common_commands_out[4] = \<const0> ;
  assign common_commands_out[3] = \<const0> ;
  assign common_commands_out[2] = \<const0> ;
  assign common_commands_out[1] = \<const0> ;
  assign common_commands_out[0] = \<const0> ;
  assign icap_o[31] = \<const0> ;
  assign icap_o[30] = \<const0> ;
  assign icap_o[29] = \<const0> ;
  assign icap_o[28] = \<const0> ;
  assign icap_o[27] = \<const0> ;
  assign icap_o[26] = \<const0> ;
  assign icap_o[25] = \<const0> ;
  assign icap_o[24] = \<const0> ;
  assign icap_o[23] = \<const0> ;
  assign icap_o[22] = \<const0> ;
  assign icap_o[21] = \<const0> ;
  assign icap_o[20] = \<const0> ;
  assign icap_o[19] = \<const0> ;
  assign icap_o[18] = \<const0> ;
  assign icap_o[17] = \<const0> ;
  assign icap_o[16] = \<const0> ;
  assign icap_o[15] = \<const0> ;
  assign icap_o[14] = \<const0> ;
  assign icap_o[13] = \<const0> ;
  assign icap_o[12] = \<const0> ;
  assign icap_o[11] = \<const0> ;
  assign icap_o[10] = \<const0> ;
  assign icap_o[9] = \<const0> ;
  assign icap_o[8] = \<const0> ;
  assign icap_o[7] = \<const0> ;
  assign icap_o[6] = \<const0> ;
  assign icap_o[5] = \<const0> ;
  assign icap_o[4] = \<const0> ;
  assign icap_o[3] = \<const0> ;
  assign icap_o[2] = \<const0> ;
  assign icap_o[1] = \<const0> ;
  assign icap_o[0] = \<const0> ;
  assign int_dclk_out = ext_ch_gt_drpclk;
  assign int_oobclk_out = int_pipe_rxusrclk_out;
  assign int_pclk_out_slave = \<const0> ;
  assign int_rxoutclk_out[7] = \<const0> ;
  assign int_rxoutclk_out[6] = \<const0> ;
  assign int_rxoutclk_out[5] = \<const0> ;
  assign int_rxoutclk_out[4] = \<const0> ;
  assign int_rxoutclk_out[3] = \<const0> ;
  assign int_rxoutclk_out[2] = \<const0> ;
  assign int_rxoutclk_out[1] = \<const0> ;
  assign int_rxoutclk_out[0] = \<const0> ;
  assign int_userclk1_out = int_userclk2_out;
  assign pipe_debug[31] = \<const0> ;
  assign pipe_debug[30] = \<const0> ;
  assign pipe_debug[29] = \<const0> ;
  assign pipe_debug[28] = \<const0> ;
  assign pipe_debug[27] = \<const0> ;
  assign pipe_debug[26] = \<const0> ;
  assign pipe_debug[25] = \<const0> ;
  assign pipe_debug[24] = \<const0> ;
  assign pipe_debug[23] = \<const0> ;
  assign pipe_debug[22] = \<const0> ;
  assign pipe_debug[21] = \<const0> ;
  assign pipe_debug[20] = \<const0> ;
  assign pipe_debug[19] = \<const0> ;
  assign pipe_debug[18] = \<const0> ;
  assign pipe_debug[17] = \<const0> ;
  assign pipe_debug[16] = \<const0> ;
  assign pipe_debug[15] = \<const0> ;
  assign pipe_debug[14] = \<const0> ;
  assign pipe_debug[13] = \<const0> ;
  assign pipe_debug[12] = \<const0> ;
  assign pipe_debug[11] = \<const0> ;
  assign pipe_debug[10] = \<const0> ;
  assign pipe_debug[9] = \<const0> ;
  assign pipe_debug[8] = \<const0> ;
  assign pipe_debug[7] = \<const0> ;
  assign pipe_debug[6] = \<const0> ;
  assign pipe_debug[5] = \<const0> ;
  assign pipe_debug[4] = \<const0> ;
  assign pipe_debug[3] = \<const0> ;
  assign pipe_debug[2] = \<const0> ;
  assign pipe_debug[1] = \<const0> ;
  assign pipe_debug[0] = \<const0> ;
  assign pipe_debug_0[7] = \<const0> ;
  assign pipe_debug_0[6] = \<const0> ;
  assign pipe_debug_0[5] = \<const0> ;
  assign pipe_debug_0[4] = \<const0> ;
  assign pipe_debug_0[3] = \<const0> ;
  assign pipe_debug_0[2] = \<const0> ;
  assign pipe_debug_0[1] = \<const0> ;
  assign pipe_debug_0[0] = \<const0> ;
  assign pipe_debug_1[7] = \<const0> ;
  assign pipe_debug_1[6] = \<const0> ;
  assign pipe_debug_1[5] = \<const0> ;
  assign pipe_debug_1[4] = \<const0> ;
  assign pipe_debug_1[3] = \<const0> ;
  assign pipe_debug_1[2] = \<const0> ;
  assign pipe_debug_1[1] = \<const0> ;
  assign pipe_debug_1[0] = \<const0> ;
  assign pipe_debug_2[7] = \<const0> ;
  assign pipe_debug_2[6] = \<const0> ;
  assign pipe_debug_2[5] = \<const0> ;
  assign pipe_debug_2[4] = \<const0> ;
  assign pipe_debug_2[3] = \<const0> ;
  assign pipe_debug_2[2] = \<const0> ;
  assign pipe_debug_2[1] = \<const0> ;
  assign pipe_debug_2[0] = \<const0> ;
  assign pipe_debug_3[7] = \<const0> ;
  assign pipe_debug_3[6] = \<const0> ;
  assign pipe_debug_3[5] = \<const0> ;
  assign pipe_debug_3[4] = \<const0> ;
  assign pipe_debug_3[3] = \<const0> ;
  assign pipe_debug_3[2] = \<const0> ;
  assign pipe_debug_3[1] = \<const0> ;
  assign pipe_debug_3[0] = \<const0> ;
  assign pipe_debug_4[7] = \<const0> ;
  assign pipe_debug_4[6] = \<const0> ;
  assign pipe_debug_4[5] = \<const0> ;
  assign pipe_debug_4[4] = \<const0> ;
  assign pipe_debug_4[3] = \<const0> ;
  assign pipe_debug_4[2] = \<const0> ;
  assign pipe_debug_4[1] = \<const0> ;
  assign pipe_debug_4[0] = \<const0> ;
  assign pipe_debug_5[7] = \<const0> ;
  assign pipe_debug_5[6] = \<const0> ;
  assign pipe_debug_5[5] = \<const0> ;
  assign pipe_debug_5[4] = \<const0> ;
  assign pipe_debug_5[3] = \<const0> ;
  assign pipe_debug_5[2] = \<const0> ;
  assign pipe_debug_5[1] = \<const0> ;
  assign pipe_debug_5[0] = \<const0> ;
  assign pipe_debug_6[7] = \<const0> ;
  assign pipe_debug_6[6] = \<const0> ;
  assign pipe_debug_6[5] = \<const0> ;
  assign pipe_debug_6[4] = \<const0> ;
  assign pipe_debug_6[3] = \<const0> ;
  assign pipe_debug_6[2] = \<const0> ;
  assign pipe_debug_6[1] = \<const0> ;
  assign pipe_debug_6[0] = \<const0> ;
  assign pipe_debug_7[7] = \<const0> ;
  assign pipe_debug_7[6] = \<const0> ;
  assign pipe_debug_7[5] = \<const0> ;
  assign pipe_debug_7[4] = \<const0> ;
  assign pipe_debug_7[3] = \<const0> ;
  assign pipe_debug_7[2] = \<const0> ;
  assign pipe_debug_7[1] = \<const0> ;
  assign pipe_debug_7[0] = \<const0> ;
  assign pipe_debug_8[7] = \<const0> ;
  assign pipe_debug_8[6] = \<const0> ;
  assign pipe_debug_8[5] = \<const0> ;
  assign pipe_debug_8[4] = \<const0> ;
  assign pipe_debug_8[3] = \<const0> ;
  assign pipe_debug_8[2] = \<const0> ;
  assign pipe_debug_8[1] = \<const0> ;
  assign pipe_debug_8[0] = \<const0> ;
  assign pipe_debug_9[7] = \<const0> ;
  assign pipe_debug_9[6] = \<const0> ;
  assign pipe_debug_9[5] = \<const0> ;
  assign pipe_debug_9[4] = \<const0> ;
  assign pipe_debug_9[3] = \<const0> ;
  assign pipe_debug_9[2] = \<const0> ;
  assign pipe_debug_9[1] = \<const0> ;
  assign pipe_debug_9[0] = \<const0> ;
  assign pipe_dmonitorout[119] = \<const0> ;
  assign pipe_dmonitorout[118] = \<const0> ;
  assign pipe_dmonitorout[117] = \<const0> ;
  assign pipe_dmonitorout[116] = \<const0> ;
  assign pipe_dmonitorout[115] = \<const0> ;
  assign pipe_dmonitorout[114] = \<const0> ;
  assign pipe_dmonitorout[113] = \<const0> ;
  assign pipe_dmonitorout[112:105] = \^pipe_dmonitorout [112:105];
  assign pipe_dmonitorout[104] = \<const0> ;
  assign pipe_dmonitorout[103] = \<const0> ;
  assign pipe_dmonitorout[102] = \<const0> ;
  assign pipe_dmonitorout[101] = \<const0> ;
  assign pipe_dmonitorout[100] = \<const0> ;
  assign pipe_dmonitorout[99] = \<const0> ;
  assign pipe_dmonitorout[98] = \<const0> ;
  assign pipe_dmonitorout[97:90] = \^pipe_dmonitorout [97:90];
  assign pipe_dmonitorout[89] = \<const0> ;
  assign pipe_dmonitorout[88] = \<const0> ;
  assign pipe_dmonitorout[87] = \<const0> ;
  assign pipe_dmonitorout[86] = \<const0> ;
  assign pipe_dmonitorout[85] = \<const0> ;
  assign pipe_dmonitorout[84] = \<const0> ;
  assign pipe_dmonitorout[83] = \<const0> ;
  assign pipe_dmonitorout[82:75] = \^pipe_dmonitorout [82:75];
  assign pipe_dmonitorout[74] = \<const0> ;
  assign pipe_dmonitorout[73] = \<const0> ;
  assign pipe_dmonitorout[72] = \<const0> ;
  assign pipe_dmonitorout[71] = \<const0> ;
  assign pipe_dmonitorout[70] = \<const0> ;
  assign pipe_dmonitorout[69] = \<const0> ;
  assign pipe_dmonitorout[68] = \<const0> ;
  assign pipe_dmonitorout[67:60] = \^pipe_dmonitorout [67:60];
  assign pipe_dmonitorout[59] = \<const0> ;
  assign pipe_dmonitorout[58] = \<const0> ;
  assign pipe_dmonitorout[57] = \<const0> ;
  assign pipe_dmonitorout[56] = \<const0> ;
  assign pipe_dmonitorout[55] = \<const0> ;
  assign pipe_dmonitorout[54] = \<const0> ;
  assign pipe_dmonitorout[53] = \<const0> ;
  assign pipe_dmonitorout[52:45] = \^pipe_dmonitorout [52:45];
  assign pipe_dmonitorout[44] = \<const0> ;
  assign pipe_dmonitorout[43] = \<const0> ;
  assign pipe_dmonitorout[42] = \<const0> ;
  assign pipe_dmonitorout[41] = \<const0> ;
  assign pipe_dmonitorout[40] = \<const0> ;
  assign pipe_dmonitorout[39] = \<const0> ;
  assign pipe_dmonitorout[38] = \<const0> ;
  assign pipe_dmonitorout[37:30] = \^pipe_dmonitorout [37:30];
  assign pipe_dmonitorout[29] = \<const0> ;
  assign pipe_dmonitorout[28] = \<const0> ;
  assign pipe_dmonitorout[27] = \<const0> ;
  assign pipe_dmonitorout[26] = \<const0> ;
  assign pipe_dmonitorout[25] = \<const0> ;
  assign pipe_dmonitorout[24] = \<const0> ;
  assign pipe_dmonitorout[23] = \<const0> ;
  assign pipe_dmonitorout[22:15] = \^pipe_dmonitorout [22:15];
  assign pipe_dmonitorout[14] = \<const0> ;
  assign pipe_dmonitorout[13] = \<const0> ;
  assign pipe_dmonitorout[12] = \<const0> ;
  assign pipe_dmonitorout[11] = \<const0> ;
  assign pipe_dmonitorout[10] = \<const0> ;
  assign pipe_dmonitorout[9] = \<const0> ;
  assign pipe_dmonitorout[8] = \<const0> ;
  assign pipe_dmonitorout[7:0] = \^pipe_dmonitorout [7:0];
  assign pipe_drp_fsm[55] = \<const0> ;
  assign pipe_drp_fsm[54] = \<const0> ;
  assign pipe_drp_fsm[53] = \<const0> ;
  assign pipe_drp_fsm[52] = \<const0> ;
  assign pipe_drp_fsm[51] = \<const0> ;
  assign pipe_drp_fsm[50] = \<const0> ;
  assign pipe_drp_fsm[49] = \<const0> ;
  assign pipe_drp_fsm[48] = \<const0> ;
  assign pipe_drp_fsm[47] = \<const0> ;
  assign pipe_drp_fsm[46] = \<const0> ;
  assign pipe_drp_fsm[45] = \<const0> ;
  assign pipe_drp_fsm[44] = \<const0> ;
  assign pipe_drp_fsm[43] = \<const0> ;
  assign pipe_drp_fsm[42] = \<const0> ;
  assign pipe_drp_fsm[41] = \<const0> ;
  assign pipe_drp_fsm[40] = \<const0> ;
  assign pipe_drp_fsm[39] = \<const0> ;
  assign pipe_drp_fsm[38] = \<const0> ;
  assign pipe_drp_fsm[37] = \<const0> ;
  assign pipe_drp_fsm[36] = \<const0> ;
  assign pipe_drp_fsm[35] = \<const0> ;
  assign pipe_drp_fsm[34] = \<const0> ;
  assign pipe_drp_fsm[33] = \<const0> ;
  assign pipe_drp_fsm[32] = \<const0> ;
  assign pipe_drp_fsm[31] = \<const0> ;
  assign pipe_drp_fsm[30] = \<const0> ;
  assign pipe_drp_fsm[29] = \<const0> ;
  assign pipe_drp_fsm[28] = \<const0> ;
  assign pipe_drp_fsm[27] = \<const0> ;
  assign pipe_drp_fsm[26] = \<const0> ;
  assign pipe_drp_fsm[25] = \<const0> ;
  assign pipe_drp_fsm[24] = \<const0> ;
  assign pipe_drp_fsm[23:0] = \^pipe_drp_fsm [23:0];
  assign pipe_qpll_lock[1:0] = int_qplllock_out;
  assign pipe_qrst_fsm[11] = \<const0> ;
  assign pipe_qrst_fsm[10] = \<const0> ;
  assign pipe_qrst_fsm[9] = \<const0> ;
  assign pipe_qrst_fsm[8] = \<const0> ;
  assign pipe_qrst_fsm[7] = \<const0> ;
  assign pipe_qrst_fsm[6] = \<const0> ;
  assign pipe_qrst_fsm[5] = \<const0> ;
  assign pipe_qrst_fsm[4] = \<const0> ;
  assign pipe_qrst_fsm[3:0] = \^pipe_qrst_fsm [3:0];
  assign pipe_rxpmaresetdone[7] = \<const0> ;
  assign pipe_rxpmaresetdone[6] = \<const0> ;
  assign pipe_rxpmaresetdone[5] = \<const0> ;
  assign pipe_rxpmaresetdone[4] = \<const0> ;
  assign pipe_rxpmaresetdone[3] = \<const0> ;
  assign pipe_rxpmaresetdone[2] = \<const0> ;
  assign pipe_rxpmaresetdone[1] = \<const0> ;
  assign pipe_rxpmaresetdone[0] = \<const0> ;
  assign pipe_rxsyncdone[7] = \<const0> ;
  assign pipe_rxsyncdone[6] = \<const0> ;
  assign pipe_rxsyncdone[5] = \<const0> ;
  assign pipe_rxsyncdone[4] = \<const0> ;
  assign pipe_rxsyncdone[3] = \<const0> ;
  assign pipe_rxsyncdone[2] = \<const0> ;
  assign pipe_rxsyncdone[1] = \<const0> ;
  assign pipe_rxsyncdone[0] = \<const0> ;
  assign pipe_tx_0_sigs[22] = \<const0> ;
  assign pipe_tx_0_sigs[21] = \<const0> ;
  assign pipe_tx_0_sigs[20] = \<const0> ;
  assign pipe_tx_0_sigs[19] = \<const0> ;
  assign pipe_tx_0_sigs[18] = \<const0> ;
  assign pipe_tx_0_sigs[17] = \<const0> ;
  assign pipe_tx_0_sigs[16] = \<const0> ;
  assign pipe_tx_0_sigs[15] = \<const0> ;
  assign pipe_tx_0_sigs[14] = \<const0> ;
  assign pipe_tx_0_sigs[13] = \<const0> ;
  assign pipe_tx_0_sigs[12] = \<const0> ;
  assign pipe_tx_0_sigs[11] = \<const0> ;
  assign pipe_tx_0_sigs[10] = \<const0> ;
  assign pipe_tx_0_sigs[9] = \<const0> ;
  assign pipe_tx_0_sigs[8] = \<const0> ;
  assign pipe_tx_0_sigs[7] = \<const0> ;
  assign pipe_tx_0_sigs[6] = \<const0> ;
  assign pipe_tx_0_sigs[5] = \<const0> ;
  assign pipe_tx_0_sigs[4] = \<const0> ;
  assign pipe_tx_0_sigs[3] = \<const0> ;
  assign pipe_tx_0_sigs[2] = \<const0> ;
  assign pipe_tx_0_sigs[1] = \<const0> ;
  assign pipe_tx_0_sigs[0] = \<const0> ;
  assign pipe_tx_1_sigs[22] = \<const0> ;
  assign pipe_tx_1_sigs[21] = \<const0> ;
  assign pipe_tx_1_sigs[20] = \<const0> ;
  assign pipe_tx_1_sigs[19] = \<const0> ;
  assign pipe_tx_1_sigs[18] = \<const0> ;
  assign pipe_tx_1_sigs[17] = \<const0> ;
  assign pipe_tx_1_sigs[16] = \<const0> ;
  assign pipe_tx_1_sigs[15] = \<const0> ;
  assign pipe_tx_1_sigs[14] = \<const0> ;
  assign pipe_tx_1_sigs[13] = \<const0> ;
  assign pipe_tx_1_sigs[12] = \<const0> ;
  assign pipe_tx_1_sigs[11] = \<const0> ;
  assign pipe_tx_1_sigs[10] = \<const0> ;
  assign pipe_tx_1_sigs[9] = \<const0> ;
  assign pipe_tx_1_sigs[8] = \<const0> ;
  assign pipe_tx_1_sigs[7] = \<const0> ;
  assign pipe_tx_1_sigs[6] = \<const0> ;
  assign pipe_tx_1_sigs[5] = \<const0> ;
  assign pipe_tx_1_sigs[4] = \<const0> ;
  assign pipe_tx_1_sigs[3] = \<const0> ;
  assign pipe_tx_1_sigs[2] = \<const0> ;
  assign pipe_tx_1_sigs[1] = \<const0> ;
  assign pipe_tx_1_sigs[0] = \<const0> ;
  assign pipe_tx_2_sigs[22] = \<const0> ;
  assign pipe_tx_2_sigs[21] = \<const0> ;
  assign pipe_tx_2_sigs[20] = \<const0> ;
  assign pipe_tx_2_sigs[19] = \<const0> ;
  assign pipe_tx_2_sigs[18] = \<const0> ;
  assign pipe_tx_2_sigs[17] = \<const0> ;
  assign pipe_tx_2_sigs[16] = \<const0> ;
  assign pipe_tx_2_sigs[15] = \<const0> ;
  assign pipe_tx_2_sigs[14] = \<const0> ;
  assign pipe_tx_2_sigs[13] = \<const0> ;
  assign pipe_tx_2_sigs[12] = \<const0> ;
  assign pipe_tx_2_sigs[11] = \<const0> ;
  assign pipe_tx_2_sigs[10] = \<const0> ;
  assign pipe_tx_2_sigs[9] = \<const0> ;
  assign pipe_tx_2_sigs[8] = \<const0> ;
  assign pipe_tx_2_sigs[7] = \<const0> ;
  assign pipe_tx_2_sigs[6] = \<const0> ;
  assign pipe_tx_2_sigs[5] = \<const0> ;
  assign pipe_tx_2_sigs[4] = \<const0> ;
  assign pipe_tx_2_sigs[3] = \<const0> ;
  assign pipe_tx_2_sigs[2] = \<const0> ;
  assign pipe_tx_2_sigs[1] = \<const0> ;
  assign pipe_tx_2_sigs[0] = \<const0> ;
  assign pipe_tx_3_sigs[22] = \<const0> ;
  assign pipe_tx_3_sigs[21] = \<const0> ;
  assign pipe_tx_3_sigs[20] = \<const0> ;
  assign pipe_tx_3_sigs[19] = \<const0> ;
  assign pipe_tx_3_sigs[18] = \<const0> ;
  assign pipe_tx_3_sigs[17] = \<const0> ;
  assign pipe_tx_3_sigs[16] = \<const0> ;
  assign pipe_tx_3_sigs[15] = \<const0> ;
  assign pipe_tx_3_sigs[14] = \<const0> ;
  assign pipe_tx_3_sigs[13] = \<const0> ;
  assign pipe_tx_3_sigs[12] = \<const0> ;
  assign pipe_tx_3_sigs[11] = \<const0> ;
  assign pipe_tx_3_sigs[10] = \<const0> ;
  assign pipe_tx_3_sigs[9] = \<const0> ;
  assign pipe_tx_3_sigs[8] = \<const0> ;
  assign pipe_tx_3_sigs[7] = \<const0> ;
  assign pipe_tx_3_sigs[6] = \<const0> ;
  assign pipe_tx_3_sigs[5] = \<const0> ;
  assign pipe_tx_3_sigs[4] = \<const0> ;
  assign pipe_tx_3_sigs[3] = \<const0> ;
  assign pipe_tx_3_sigs[2] = \<const0> ;
  assign pipe_tx_3_sigs[1] = \<const0> ;
  assign pipe_tx_3_sigs[0] = \<const0> ;
  assign pipe_tx_4_sigs[22] = \<const0> ;
  assign pipe_tx_4_sigs[21] = \<const0> ;
  assign pipe_tx_4_sigs[20] = \<const0> ;
  assign pipe_tx_4_sigs[19] = \<const0> ;
  assign pipe_tx_4_sigs[18] = \<const0> ;
  assign pipe_tx_4_sigs[17] = \<const0> ;
  assign pipe_tx_4_sigs[16] = \<const0> ;
  assign pipe_tx_4_sigs[15] = \<const0> ;
  assign pipe_tx_4_sigs[14] = \<const0> ;
  assign pipe_tx_4_sigs[13] = \<const0> ;
  assign pipe_tx_4_sigs[12] = \<const0> ;
  assign pipe_tx_4_sigs[11] = \<const0> ;
  assign pipe_tx_4_sigs[10] = \<const0> ;
  assign pipe_tx_4_sigs[9] = \<const0> ;
  assign pipe_tx_4_sigs[8] = \<const0> ;
  assign pipe_tx_4_sigs[7] = \<const0> ;
  assign pipe_tx_4_sigs[6] = \<const0> ;
  assign pipe_tx_4_sigs[5] = \<const0> ;
  assign pipe_tx_4_sigs[4] = \<const0> ;
  assign pipe_tx_4_sigs[3] = \<const0> ;
  assign pipe_tx_4_sigs[2] = \<const0> ;
  assign pipe_tx_4_sigs[1] = \<const0> ;
  assign pipe_tx_4_sigs[0] = \<const0> ;
  assign pipe_tx_5_sigs[22] = \<const0> ;
  assign pipe_tx_5_sigs[21] = \<const0> ;
  assign pipe_tx_5_sigs[20] = \<const0> ;
  assign pipe_tx_5_sigs[19] = \<const0> ;
  assign pipe_tx_5_sigs[18] = \<const0> ;
  assign pipe_tx_5_sigs[17] = \<const0> ;
  assign pipe_tx_5_sigs[16] = \<const0> ;
  assign pipe_tx_5_sigs[15] = \<const0> ;
  assign pipe_tx_5_sigs[14] = \<const0> ;
  assign pipe_tx_5_sigs[13] = \<const0> ;
  assign pipe_tx_5_sigs[12] = \<const0> ;
  assign pipe_tx_5_sigs[11] = \<const0> ;
  assign pipe_tx_5_sigs[10] = \<const0> ;
  assign pipe_tx_5_sigs[9] = \<const0> ;
  assign pipe_tx_5_sigs[8] = \<const0> ;
  assign pipe_tx_5_sigs[7] = \<const0> ;
  assign pipe_tx_5_sigs[6] = \<const0> ;
  assign pipe_tx_5_sigs[5] = \<const0> ;
  assign pipe_tx_5_sigs[4] = \<const0> ;
  assign pipe_tx_5_sigs[3] = \<const0> ;
  assign pipe_tx_5_sigs[2] = \<const0> ;
  assign pipe_tx_5_sigs[1] = \<const0> ;
  assign pipe_tx_5_sigs[0] = \<const0> ;
  assign pipe_tx_6_sigs[22] = \<const0> ;
  assign pipe_tx_6_sigs[21] = \<const0> ;
  assign pipe_tx_6_sigs[20] = \<const0> ;
  assign pipe_tx_6_sigs[19] = \<const0> ;
  assign pipe_tx_6_sigs[18] = \<const0> ;
  assign pipe_tx_6_sigs[17] = \<const0> ;
  assign pipe_tx_6_sigs[16] = \<const0> ;
  assign pipe_tx_6_sigs[15] = \<const0> ;
  assign pipe_tx_6_sigs[14] = \<const0> ;
  assign pipe_tx_6_sigs[13] = \<const0> ;
  assign pipe_tx_6_sigs[12] = \<const0> ;
  assign pipe_tx_6_sigs[11] = \<const0> ;
  assign pipe_tx_6_sigs[10] = \<const0> ;
  assign pipe_tx_6_sigs[9] = \<const0> ;
  assign pipe_tx_6_sigs[8] = \<const0> ;
  assign pipe_tx_6_sigs[7] = \<const0> ;
  assign pipe_tx_6_sigs[6] = \<const0> ;
  assign pipe_tx_6_sigs[5] = \<const0> ;
  assign pipe_tx_6_sigs[4] = \<const0> ;
  assign pipe_tx_6_sigs[3] = \<const0> ;
  assign pipe_tx_6_sigs[2] = \<const0> ;
  assign pipe_tx_6_sigs[1] = \<const0> ;
  assign pipe_tx_6_sigs[0] = \<const0> ;
  assign pipe_tx_7_sigs[22] = \<const0> ;
  assign pipe_tx_7_sigs[21] = \<const0> ;
  assign pipe_tx_7_sigs[20] = \<const0> ;
  assign pipe_tx_7_sigs[19] = \<const0> ;
  assign pipe_tx_7_sigs[18] = \<const0> ;
  assign pipe_tx_7_sigs[17] = \<const0> ;
  assign pipe_tx_7_sigs[16] = \<const0> ;
  assign pipe_tx_7_sigs[15] = \<const0> ;
  assign pipe_tx_7_sigs[14] = \<const0> ;
  assign pipe_tx_7_sigs[13] = \<const0> ;
  assign pipe_tx_7_sigs[12] = \<const0> ;
  assign pipe_tx_7_sigs[11] = \<const0> ;
  assign pipe_tx_7_sigs[10] = \<const0> ;
  assign pipe_tx_7_sigs[9] = \<const0> ;
  assign pipe_tx_7_sigs[8] = \<const0> ;
  assign pipe_tx_7_sigs[7] = \<const0> ;
  assign pipe_tx_7_sigs[6] = \<const0> ;
  assign pipe_tx_7_sigs[5] = \<const0> ;
  assign pipe_tx_7_sigs[4] = \<const0> ;
  assign pipe_tx_7_sigs[3] = \<const0> ;
  assign pipe_tx_7_sigs[2] = \<const0> ;
  assign pipe_tx_7_sigs[1] = \<const0> ;
  assign pipe_tx_7_sigs[0] = \<const0> ;
  assign qpll_drp_clk = \<const0> ;
  assign qpll_drp_gen3 = \<const0> ;
  assign qpll_drp_ovrd = \<const0> ;
  assign qpll_drp_rst_n = \<const0> ;
  assign qpll_drp_start = \<const0> ;
  assign qpll_qplld = \<const0> ;
  assign qpll_qpllreset[1] = \<const0> ;
  assign qpll_qpllreset[0] = \<const0> ;
  assign startup_cfgclk = \<const0> ;
  assign startup_cfgmclk = \<const0> ;
  assign startup_eos = \<const0> ;
  assign startup_preq = \<const0> ;
  assign user_app_rdy = \<const1> ;
  assign user_clk_out = int_userclk2_out;
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  PCIeGen1x8If64_PCIeGen1x8If64_core_top inst
       (.EQ_GEN3(pipe_gen3_out),
        .INT_OOBCLK_OUT(int_pipe_rxusrclk_out),
        .INT_USERCLK2_OUT(int_userclk2_out),
        .PIPE_DRP_FSM(\^pipe_drp_fsm ),
        .PIPE_RATE_FSM(pipe_rate_fsm),
        .PIPE_SYNC_FSM_TX(pipe_sync_fsm_tx),
        .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en),
        .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en),
        .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
        .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received),
        .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en),
        .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received),
        .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en),
        .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received),
        .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en),
        .cfg_bridge_serr_en(cfg_bridge_serr_en),
        .cfg_bus_number(cfg_bus_number),
        .cfg_command({\^cfg_command [10],\^cfg_command [8],\^cfg_command [2:0]}),
        .cfg_dcommand(\^cfg_dcommand ),
        .cfg_dcommand2(\^cfg_dcommand2 ),
        .cfg_device_number(cfg_device_number),
        .cfg_ds_bus_number(cfg_ds_bus_number),
        .cfg_ds_device_number(cfg_ds_device_number),
        .cfg_ds_function_number(cfg_ds_function_number),
        .cfg_dsn(cfg_dsn),
        .cfg_dstatus(\^cfg_dstatus ),
        .cfg_err_aer_headerlog(cfg_err_aer_headerlog),
        .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set),
        .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked),
        .cfg_err_cor(cfg_err_cor),
        .cfg_err_cpl_abort(cfg_err_cpl_abort),
        .cfg_err_cpl_rdy(cfg_err_cpl_rdy),
        .cfg_err_cpl_timeout(cfg_err_cpl_timeout),
        .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect),
        .cfg_err_ecrc(cfg_err_ecrc),
        .cfg_err_internal_cor(cfg_err_internal_cor),
        .cfg_err_internal_uncor(cfg_err_internal_uncor),
        .cfg_err_locked(cfg_err_locked),
        .cfg_err_malformed(cfg_err_malformed),
        .cfg_err_mc_blocked(cfg_err_mc_blocked),
        .cfg_err_norecovery(cfg_err_norecovery),
        .cfg_err_poisoned(cfg_err_poisoned),
        .cfg_err_posted(cfg_err_posted),
        .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
        .cfg_err_ur(cfg_err_ur),
        .cfg_function_number(cfg_function_number),
        .cfg_interrupt(cfg_interrupt),
        .cfg_interrupt_assert(cfg_interrupt_assert),
        .cfg_interrupt_di(cfg_interrupt_di),
        .cfg_interrupt_do(cfg_interrupt_do),
        .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
        .cfg_interrupt_msienable(cfg_interrupt_msienable),
        .cfg_interrupt_msixenable(cfg_interrupt_msixenable),
        .cfg_interrupt_msixfm(cfg_interrupt_msixfm),
        .cfg_interrupt_rdy(cfg_interrupt_rdy),
        .cfg_interrupt_stat(cfg_interrupt_stat),
        .cfg_lcommand({\^cfg_lcommand [11:3],\^cfg_lcommand [1:0]}),
        .cfg_lstatus({\^cfg_lstatus [15:13],\^cfg_lstatus [11],\^cfg_lstatus [7:4],\^cfg_lstatus [1:0]}),
        .cfg_mgmt_byte_en(cfg_mgmt_byte_en),
        .cfg_mgmt_di(cfg_mgmt_di),
        .cfg_mgmt_do(cfg_mgmt_do),
        .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
        .cfg_mgmt_rd_en(cfg_mgmt_rd_en),
        .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
        .cfg_mgmt_wr_en(cfg_mgmt_wr_en),
        .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
        .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw),
        .cfg_msg_data(cfg_msg_data),
        .cfg_msg_received(cfg_msg_received),
        .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a),
        .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b),
        .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c),
        .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d),
        .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a),
        .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b),
        .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c),
        .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d),
        .cfg_msg_received_err_cor(cfg_msg_received_err_cor),
        .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal),
        .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal),
        .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak),
        .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme),
        .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack),
        .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit),
        .cfg_pcie_link_state(cfg_pcie_link_state),
        .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
        .cfg_pm_force_state(cfg_pm_force_state),
        .cfg_pm_force_state_en(cfg_pm_force_state_en),
        .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s),
        .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1),
        .cfg_pm_wake(cfg_pm_wake),
        .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en),
        .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status),
        .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate),
        .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst),
        .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en),
        .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en),
        .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en),
        .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en),
        .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_trn_pending(cfg_trn_pending),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .cfg_vc_tcvc_map(cfg_vc_tcvc_map),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr),
        .ext_ch_gt_drpclk(ext_ch_gt_drpclk),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo),
        .ext_ch_gt_drpen(ext_ch_gt_drpen),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe),
        .fc_cpld(fc_cpld),
        .fc_cplh(fc_cplh),
        .fc_npd(fc_npd),
        .fc_nph(fc_nph),
        .fc_pd(fc_pd),
        .fc_ph(fc_ph),
        .fc_sel(fc_sel),
        .gt_ch_drp_rdy(gt_ch_drp_rdy),
        .int_mmcm_lock_out(int_mmcm_lock_out),
        .int_pclk_sel_slave(int_pclk_sel_slave),
        .int_qplllock_out(int_qplllock_out),
        .int_qplloutclk_out(int_qplloutclk_out),
        .int_qplloutrefclk_out(int_qplloutrefclk_out),
        .m_axis_rx_tdata(m_axis_rx_tdata),
        .m_axis_rx_tkeep(m_axis_rx_tkeep),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser),
        .m_axis_rx_tvalid(m_axis_rx_tvalid),
        .out({pipe_rst_fsm[4],pipe_rst_idle}),
        .pci_exp_rxn(pci_exp_rxn),
        .pci_exp_rxp(pci_exp_rxp),
        .pci_exp_txn(pci_exp_txn),
        .pci_exp_txp(pci_exp_txp),
        .pcie_drp_addr(pcie_drp_addr),
        .pcie_drp_clk(pcie_drp_clk),
        .pcie_drp_di(pcie_drp_di),
        .pcie_drp_do(pcie_drp_do),
        .pcie_drp_en(pcie_drp_en),
        .pcie_drp_rdy(pcie_drp_rdy),
        .pcie_drp_we(pcie_drp_we),
        .pipe_cpll_lock(pipe_cpll_lock),
        .pipe_dmonitorout({\^pipe_dmonitorout [112:105],\^pipe_dmonitorout [97:90],\^pipe_dmonitorout [82:75],\^pipe_dmonitorout [67:60],\^pipe_dmonitorout [52:45],\^pipe_dmonitorout [37:30],\^pipe_dmonitorout [22:15],\^pipe_dmonitorout [7:0]}),
        .pipe_eyescandataerror(pipe_eyescandataerror),
        .pipe_mmcm_rst_n(pipe_mmcm_rst_n),
        .pipe_pclk_sel_out(pipe_pclk_sel_out),
        .pipe_qrst_fsm(\^pipe_qrst_fsm ),
        .pipe_qrst_idle(pipe_qrst_idle),
        .pipe_rate_idle(pipe_rate_idle),
        .pipe_rst_fsm(pipe_rst_fsm[3:0]),
        .pipe_rxbufstatus(pipe_rxbufstatus),
        .pipe_rxcommadet(pipe_rxcommadet),
        .pipe_rxdisperr(pipe_rxdisperr),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone),
        .pipe_rxnotintable(pipe_rxnotintable),
        .pipe_rxoutclk_out(pipe_rxoutclk_out),
        .pipe_rxphaligndone(pipe_rxphaligndone),
        .pipe_rxprbserr(pipe_rxprbserr),
        .pipe_rxstatus(pipe_rxstatus),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx),
        .pipe_txdlysresetdone(pipe_txdlysresetdone),
        .pipe_txinhibit(pipe_txinhibit),
        .pipe_txoutclk_out(pipe_txoutclk_out),
        .pipe_txphaligndone(pipe_txphaligndone),
        .pipe_txphinitdone(pipe_txphinitdone),
        .pl_directed_change_done(pl_directed_change_done),
        .pl_directed_link_auton(pl_directed_link_auton),
        .pl_directed_link_change(pl_directed_link_change),
        .pl_directed_link_speed(pl_directed_link_speed),
        .pl_directed_link_width(pl_directed_link_width),
        .pl_downstream_deemph_source(pl_downstream_deemph_source),
        .pl_initial_link_width(pl_initial_link_width),
        .pl_lane_reversal_mode(pl_lane_reversal_mode),
        .pl_link_gen2_cap(pl_link_gen2_cap),
        .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported),
        .pl_link_upcfg_cap(pl_link_upcfg_cap),
        .pl_ltssm_state(pl_ltssm_state),
        .pl_phy_lnk_up(pl_phy_lnk_up),
        .pl_received_hot_rst(pl_received_hot_rst),
        .pl_rx_pm_state(pl_rx_pm_state),
        .pl_sel_lnk_rate(pl_sel_lnk_rate),
        .pl_sel_lnk_width(pl_sel_lnk_width),
        .pl_transmit_hot_rst(pl_transmit_hot_rst),
        .pl_tx_pm_state(pl_tx_pm_state),
        .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
        .rx_np_ok(rx_np_ok),
        .rx_np_req(rx_np_req),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep[7]),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tready(s_axis_tx_tready),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .sys_clk(sys_clk),
        .sys_rst_n(sys_rst_n),
        .tx_buf_av(tx_buf_av),
        .tx_cfg_gnt(tx_cfg_gnt),
        .tx_cfg_req(tx_cfg_req),
        .tx_err_drop(tx_err_drop),
        .user_lnk_up(user_lnk_up),
        .user_reset_out(user_reset_out));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_7x
   (user_reset_int_reg,
    trn_rsrc_dsc,
    trn_rsof,
    tbuf_av_gap_thrtl_reg,
    trn_tbuf_av,
    tbuf_av_min_trig,
    tready_thrtl_xhdl1_reg,
    reg_dsc_detect_reg,
    trn_reof,
    tbuf_av_gap_thrtl_reg_0,
    cfg_mgmt_rd_wr_done,
    cfg_err_aer_headerlog_set,
    cfg_err_cpl_rdy,
    cfg_interrupt_rdy,
    E,
    cfg_msg_received,
    cfg_received_func_lvl_rst,
    pl_phy_lnk_up_q_reg,
    trn_in_packet_reg,
    rsrc_rdy_filtered10_out,
    tready_thrtl_xhdl1_reg_0,
    ppm_L1_thrtl_reg,
    cfg_pcie_link_state,
    cfg_aer_ecrc_check_en,
    cfg_aer_ecrc_gen_en,
    cfg_aer_rooterr_corr_err_received,
    cfg_aer_rooterr_corr_err_reporting_en,
    cfg_aer_rooterr_fatal_err_received,
    cfg_aer_rooterr_fatal_err_reporting_en,
    cfg_aer_rooterr_non_fatal_err_received,
    cfg_aer_rooterr_non_fatal_err_reporting_en,
    cfg_bridge_serr_en,
    cfg_command,
    cfg_dcommand2,
    cfg_dcommand,
    cfg_dstatus,
    cfg_interrupt_msienable,
    cfg_interrupt_msixenable,
    cfg_interrupt_msixfm,
    cfg_lcommand,
    cfg_lstatus,
    cfg_msg_received_assert_int_a,
    cfg_msg_received_assert_int_b,
    cfg_msg_received_assert_int_c,
    cfg_msg_received_assert_int_d,
    cfg_msg_received_deassert_int_a,
    cfg_msg_received_deassert_int_b,
    cfg_msg_received_deassert_int_c,
    cfg_msg_received_deassert_int_d,
    cfg_msg_received_err_cor,
    cfg_msg_received_err_fatal,
    cfg_msg_received_err_non_fatal,
    cfg_msg_received_pm_as_nak,
    cfg_to_turnoff,
    cfg_msg_received_pme_to_ack,
    cfg_msg_received_pm_pme,
    cfg_msg_received_setslotpowerlimit,
    cfg_pmcsr_pme_en,
    cfg_pmcsr_pme_status,
    cfg_root_control_pme_int_en,
    cfg_root_control_syserr_corr_err_en,
    cfg_root_control_syserr_fatal_err_en,
    cfg_root_control_syserr_non_fatal_err_en,
    cfg_slot_control_electromech_il_ctl_pulse,
    pcie_drp_rdy,
    pipe_rx0_polarity,
    pipe_rx1_polarity,
    pipe_rx2_polarity,
    pipe_rx3_polarity,
    pipe_rx4_polarity,
    pipe_rx5_polarity,
    pipe_rx6_polarity,
    pipe_rx7_polarity,
    pipe_tx0_compliance,
    pipe_tx0_elec_idle,
    pipe_tx1_compliance,
    pipe_tx1_elec_idle,
    pipe_tx2_compliance,
    pipe_tx2_elec_idle,
    pipe_tx3_compliance,
    pipe_tx3_elec_idle,
    pipe_tx4_compliance,
    pipe_tx4_elec_idle,
    pipe_tx5_compliance,
    pipe_tx5_elec_idle,
    pipe_tx6_compliance,
    pipe_tx6_elec_idle,
    pipe_tx7_compliance,
    pipe_tx7_elec_idle,
    pipe_tx_deemph,
    pipe_tx_rate,
    pipe_tx_rcvr_det,
    pl_directed_change_done,
    pl_link_gen2_cap,
    pl_link_partner_gen2_supported,
    pl_link_upcfg_cap,
    pl_received_hot_rst,
    pl_sel_lnk_rate,
    trn_lnk_up,
    trn_recrc_err,
    trn_rerrfwd,
    trn_tcfg_req,
    tx_err_drop,
    fc_cpld,
    fc_npd,
    fc_pd,
    trn_rd,
    cfg_msg_data,
    pcie_drp_do,
    pipe_tx0_data,
    pipe_tx1_data,
    pipe_tx2_data,
    pipe_tx3_data,
    pipe_tx4_data,
    pipe_tx5_data,
    pipe_tx6_data,
    pipe_tx7_data,
    cfg_pmcsr_powerstate,
    pipe_tx0_char_is_k,
    pipe_tx0_powerdown,
    pipe_tx1_char_is_k,
    pipe_tx1_powerdown,
    pipe_tx2_char_is_k,
    pipe_tx2_powerdown,
    pipe_tx3_char_is_k,
    pipe_tx3_powerdown,
    pipe_tx4_char_is_k,
    pipe_tx4_powerdown,
    pipe_tx5_char_is_k,
    pipe_tx5_powerdown,
    pipe_tx6_char_is_k,
    pipe_tx6_powerdown,
    pipe_tx7_char_is_k,
    pipe_tx7_powerdown,
    pl_lane_reversal_mode,
    pl_rx_pm_state,
    pl_sel_lnk_width,
    trn_rrem,
    cfg_interrupt_mmenable,
    pipe_tx_margin,
    pl_initial_link_width,
    pl_tx_pm_state,
    cfg_mgmt_do,
    trn_tdst_rdy,
    pl_ltssm_state,
    cfg_vc_tcvc_map,
    cfg_interrupt_do,
    fc_cplh,
    fc_nph,
    fc_ph,
    trn_rbar_hit,
    bridge_reset_int,
    pl_phy_lnk_up,
    trn_in_packet_reg_0,
    tready_thrtl_xhdl1_reg_1,
    s_axis_tx_tvalid,
    s_axis_tx_tlast,
    trn_rdst_rdy,
    \tbuf_av_d_reg[4] ,
    cfg_trn_pending,
    cfg_mgmt_wr_rw1c_as_rw,
    cfg_mgmt_wr_readonly,
    cfg_mgmt_wr_en,
    cfg_mgmt_rd_en,
    cfg_err_malformed,
    cfg_err_cor,
    cfg_err_ur,
    cfg_err_ecrc,
    cfg_err_cpl_timeout,
    cfg_err_cpl_abort,
    cfg_err_cpl_unexpect,
    cfg_err_poisoned,
    cfg_err_atomic_egress_blocked,
    cfg_err_mc_blocked,
    cfg_err_internal_uncor,
    cfg_err_internal_cor,
    cfg_err_posted,
    cfg_err_locked,
    cfg_err_norecovery,
    cfg_interrupt,
    cfg_interrupt_assert,
    cfg_interrupt_stat,
    cfg_pm_halt_aspm_l0s,
    cfg_pm_halt_aspm_l1,
    cfg_pm_force_state_en,
    cfg_pm_wake,
    user_reset_out_reg,
    \tcfg_req_cnt_reg[1] ,
    user_clk,
    cfg_pm_turnoff_ok_n,
    pcie_drp_clk,
    pcie_drp_en,
    pcie_drp_we,
    CLK,
    pipe_rx0_chanisaligned,
    pipe_rx0_elec_idle,
    pipe_rx0_phy_status,
    pipe_rx0_valid,
    pipe_rx1_chanisaligned,
    pipe_rx1_elec_idle,
    pipe_rx1_phy_status,
    pipe_rx1_valid,
    pipe_rx2_chanisaligned,
    pipe_rx2_elec_idle,
    pipe_rx2_phy_status,
    pipe_rx2_valid,
    pipe_rx3_chanisaligned,
    pipe_rx3_elec_idle,
    pipe_rx3_phy_status,
    pipe_rx3_valid,
    pipe_rx4_chanisaligned,
    pipe_rx4_elec_idle,
    pipe_rx4_phy_status,
    pipe_rx4_valid,
    pipe_rx5_chanisaligned,
    pipe_rx5_elec_idle,
    pipe_rx5_phy_status,
    pipe_rx5_valid,
    pipe_rx6_chanisaligned,
    pipe_rx6_elec_idle,
    pipe_rx6_phy_status,
    pipe_rx6_valid,
    pipe_rx7_chanisaligned,
    pipe_rx7_elec_idle,
    pipe_rx7_phy_status,
    pipe_rx7_valid,
    pl_directed_link_auton,
    pl_directed_link_speed,
    pl_downstream_deemph_source,
    pl_transmit_hot_rst,
    pl_upstream_prefer_deemph,
    sys_rst_n,
    rx_np_ok,
    rx_np_req,
    trn_tcfg_gnt,
    \xhdl12.reg_tuser_reg[3] ,
    trn_teof,
    trn_tsof,
    trn_tsrc_rdy,
    cfg_err_aer_headerlog,
    trn_td,
    pcie_drp_di,
    Q,
    \pipe_stages_1.pipe_rx_data_q_reg[15] ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_0 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_1 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_2 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_3 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_4 ,
    \pipe_stages_1.pipe_rx_data_q_reg[15]_5 ,
    cfg_pm_force_state,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5 ,
    \pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_6 ,
    pl_directed_link_change,
    pl_directed_link_width,
    trn_trem,
    cfg_ds_function_number,
    \pipe_stages_1.pipe_rx_status_q_reg[2] ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_0 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_1 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_2 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_3 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_4 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_5 ,
    \pipe_stages_1.pipe_rx_status_q_reg[2]_6 ,
    fc_sel,
    cfg_mgmt_di,
    cfg_mgmt_byte_en_n,
    cfg_err_tlp_cpl_header,
    cfg_aer_interrupt_msgnum,
    cfg_ds_device_number,
    cfg_pciecap_interrupt_msgnum,
    cfg_dsn,
    cfg_ds_bus_number,
    cfg_interrupt_di,
    pcie_drp_addr,
    cfg_mgmt_dwaddr);
  output user_reset_int_reg;
  output trn_rsrc_dsc;
  output trn_rsof;
  output tbuf_av_gap_thrtl_reg;
  output [5:0]trn_tbuf_av;
  output tbuf_av_min_trig;
  output tready_thrtl_xhdl1_reg;
  output reg_dsc_detect_reg;
  output trn_reof;
  output tbuf_av_gap_thrtl_reg_0;
  output cfg_mgmt_rd_wr_done;
  output cfg_err_aer_headerlog_set;
  output cfg_err_cpl_rdy;
  output cfg_interrupt_rdy;
  output [0:0]E;
  output cfg_msg_received;
  output cfg_received_func_lvl_rst;
  output pl_phy_lnk_up_q_reg;
  output trn_in_packet_reg;
  output rsrc_rdy_filtered10_out;
  output tready_thrtl_xhdl1_reg_0;
  output ppm_L1_thrtl_reg;
  output [2:0]cfg_pcie_link_state;
  output cfg_aer_ecrc_check_en;
  output cfg_aer_ecrc_gen_en;
  output cfg_aer_rooterr_corr_err_received;
  output cfg_aer_rooterr_corr_err_reporting_en;
  output cfg_aer_rooterr_fatal_err_received;
  output cfg_aer_rooterr_fatal_err_reporting_en;
  output cfg_aer_rooterr_non_fatal_err_received;
  output cfg_aer_rooterr_non_fatal_err_reporting_en;
  output cfg_bridge_serr_en;
  output [4:0]cfg_command;
  output [11:0]cfg_dcommand2;
  output [14:0]cfg_dcommand;
  output [3:0]cfg_dstatus;
  output cfg_interrupt_msienable;
  output cfg_interrupt_msixenable;
  output cfg_interrupt_msixfm;
  output [10:0]cfg_lcommand;
  output [9:0]cfg_lstatus;
  output cfg_msg_received_assert_int_a;
  output cfg_msg_received_assert_int_b;
  output cfg_msg_received_assert_int_c;
  output cfg_msg_received_assert_int_d;
  output cfg_msg_received_deassert_int_a;
  output cfg_msg_received_deassert_int_b;
  output cfg_msg_received_deassert_int_c;
  output cfg_msg_received_deassert_int_d;
  output cfg_msg_received_err_cor;
  output cfg_msg_received_err_fatal;
  output cfg_msg_received_err_non_fatal;
  output cfg_msg_received_pm_as_nak;
  output cfg_to_turnoff;
  output cfg_msg_received_pme_to_ack;
  output cfg_msg_received_pm_pme;
  output cfg_msg_received_setslotpowerlimit;
  output cfg_pmcsr_pme_en;
  output cfg_pmcsr_pme_status;
  output cfg_root_control_pme_int_en;
  output cfg_root_control_syserr_corr_err_en;
  output cfg_root_control_syserr_fatal_err_en;
  output cfg_root_control_syserr_non_fatal_err_en;
  output cfg_slot_control_electromech_il_ctl_pulse;
  output pcie_drp_rdy;
  output pipe_rx0_polarity;
  output pipe_rx1_polarity;
  output pipe_rx2_polarity;
  output pipe_rx3_polarity;
  output pipe_rx4_polarity;
  output pipe_rx5_polarity;
  output pipe_rx6_polarity;
  output pipe_rx7_polarity;
  output pipe_tx0_compliance;
  output pipe_tx0_elec_idle;
  output pipe_tx1_compliance;
  output pipe_tx1_elec_idle;
  output pipe_tx2_compliance;
  output pipe_tx2_elec_idle;
  output pipe_tx3_compliance;
  output pipe_tx3_elec_idle;
  output pipe_tx4_compliance;
  output pipe_tx4_elec_idle;
  output pipe_tx5_compliance;
  output pipe_tx5_elec_idle;
  output pipe_tx6_compliance;
  output pipe_tx6_elec_idle;
  output pipe_tx7_compliance;
  output pipe_tx7_elec_idle;
  output pipe_tx_deemph;
  output pipe_tx_rate;
  output pipe_tx_rcvr_det;
  output pl_directed_change_done;
  output pl_link_gen2_cap;
  output pl_link_partner_gen2_supported;
  output pl_link_upcfg_cap;
  output pl_received_hot_rst;
  output pl_sel_lnk_rate;
  output trn_lnk_up;
  output trn_recrc_err;
  output trn_rerrfwd;
  output trn_tcfg_req;
  output tx_err_drop;
  output [11:0]fc_cpld;
  output [11:0]fc_npd;
  output [11:0]fc_pd;
  output [63:0]trn_rd;
  output [15:0]cfg_msg_data;
  output [15:0]pcie_drp_do;
  output [15:0]pipe_tx0_data;
  output [15:0]pipe_tx1_data;
  output [15:0]pipe_tx2_data;
  output [15:0]pipe_tx3_data;
  output [15:0]pipe_tx4_data;
  output [15:0]pipe_tx5_data;
  output [15:0]pipe_tx6_data;
  output [15:0]pipe_tx7_data;
  output [1:0]cfg_pmcsr_powerstate;
  output [1:0]pipe_tx0_char_is_k;
  output [1:0]pipe_tx0_powerdown;
  output [1:0]pipe_tx1_char_is_k;
  output [1:0]pipe_tx1_powerdown;
  output [1:0]pipe_tx2_char_is_k;
  output [1:0]pipe_tx2_powerdown;
  output [1:0]pipe_tx3_char_is_k;
  output [1:0]pipe_tx3_powerdown;
  output [1:0]pipe_tx4_char_is_k;
  output [1:0]pipe_tx4_powerdown;
  output [1:0]pipe_tx5_char_is_k;
  output [1:0]pipe_tx5_powerdown;
  output [1:0]pipe_tx6_char_is_k;
  output [1:0]pipe_tx6_powerdown;
  output [1:0]pipe_tx7_char_is_k;
  output [1:0]pipe_tx7_powerdown;
  output [1:0]pl_lane_reversal_mode;
  output [1:0]pl_rx_pm_state;
  output [1:0]pl_sel_lnk_width;
  output [0:0]trn_rrem;
  output [2:0]cfg_interrupt_mmenable;
  output [2:0]pipe_tx_margin;
  output [2:0]pl_initial_link_width;
  output [2:0]pl_tx_pm_state;
  output [31:0]cfg_mgmt_do;
  output trn_tdst_rdy;
  output [5:0]pl_ltssm_state;
  output [6:0]cfg_vc_tcvc_map;
  output [7:0]cfg_interrupt_do;
  output [7:0]fc_cplh;
  output [7:0]fc_nph;
  output [7:0]fc_ph;
  output [6:0]trn_rbar_hit;
  input bridge_reset_int;
  input pl_phy_lnk_up;
  input trn_in_packet_reg_0;
  input tready_thrtl_xhdl1_reg_1;
  input s_axis_tx_tvalid;
  input s_axis_tx_tlast;
  input trn_rdst_rdy;
  input \tbuf_av_d_reg[4] ;
  input cfg_trn_pending;
  input cfg_mgmt_wr_rw1c_as_rw;
  input cfg_mgmt_wr_readonly;
  input cfg_mgmt_wr_en;
  input cfg_mgmt_rd_en;
  input cfg_err_malformed;
  input cfg_err_cor;
  input cfg_err_ur;
  input cfg_err_ecrc;
  input cfg_err_cpl_timeout;
  input cfg_err_cpl_abort;
  input cfg_err_cpl_unexpect;
  input cfg_err_poisoned;
  input cfg_err_atomic_egress_blocked;
  input cfg_err_mc_blocked;
  input cfg_err_internal_uncor;
  input cfg_err_internal_cor;
  input cfg_err_posted;
  input cfg_err_locked;
  input cfg_err_norecovery;
  input cfg_interrupt;
  input cfg_interrupt_assert;
  input cfg_interrupt_stat;
  input cfg_pm_halt_aspm_l0s;
  input cfg_pm_halt_aspm_l1;
  input cfg_pm_force_state_en;
  input cfg_pm_wake;
  input user_reset_out_reg;
  input \tcfg_req_cnt_reg[1] ;
  input user_clk;
  input cfg_pm_turnoff_ok_n;
  input pcie_drp_clk;
  input pcie_drp_en;
  input pcie_drp_we;
  input CLK;
  input pipe_rx0_chanisaligned;
  input pipe_rx0_elec_idle;
  input pipe_rx0_phy_status;
  input pipe_rx0_valid;
  input pipe_rx1_chanisaligned;
  input pipe_rx1_elec_idle;
  input pipe_rx1_phy_status;
  input pipe_rx1_valid;
  input pipe_rx2_chanisaligned;
  input pipe_rx2_elec_idle;
  input pipe_rx2_phy_status;
  input pipe_rx2_valid;
  input pipe_rx3_chanisaligned;
  input pipe_rx3_elec_idle;
  input pipe_rx3_phy_status;
  input pipe_rx3_valid;
  input pipe_rx4_chanisaligned;
  input pipe_rx4_elec_idle;
  input pipe_rx4_phy_status;
  input pipe_rx4_valid;
  input pipe_rx5_chanisaligned;
  input pipe_rx5_elec_idle;
  input pipe_rx5_phy_status;
  input pipe_rx5_valid;
  input pipe_rx6_chanisaligned;
  input pipe_rx6_elec_idle;
  input pipe_rx6_phy_status;
  input pipe_rx6_valid;
  input pipe_rx7_chanisaligned;
  input pipe_rx7_elec_idle;
  input pipe_rx7_phy_status;
  input pipe_rx7_valid;
  input pl_directed_link_auton;
  input pl_directed_link_speed;
  input pl_downstream_deemph_source;
  input pl_transmit_hot_rst;
  input pl_upstream_prefer_deemph;
  input sys_rst_n;
  input rx_np_ok;
  input rx_np_req;
  input trn_tcfg_gnt;
  input [3:0]\xhdl12.reg_tuser_reg[3] ;
  input trn_teof;
  input trn_tsof;
  input trn_tsrc_rdy;
  input [127:0]cfg_err_aer_headerlog;
  input [63:0]trn_td;
  input [15:0]pcie_drp_di;
  input [15:0]Q;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_3 ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_4 ;
  input [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_5 ;
  input [1:0]cfg_pm_force_state;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5 ;
  input [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_6 ;
  input [1:0]pl_directed_link_change;
  input [1:0]pl_directed_link_width;
  input [0:0]trn_trem;
  input [2:0]cfg_ds_function_number;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_3 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_4 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_5 ;
  input [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_6 ;
  input [2:0]fc_sel;
  input [31:0]cfg_mgmt_di;
  input [3:0]cfg_mgmt_byte_en_n;
  input [47:0]cfg_err_tlp_cpl_header;
  input [4:0]cfg_aer_interrupt_msgnum;
  input [4:0]cfg_ds_device_number;
  input [4:0]cfg_pciecap_interrupt_msgnum;
  input [63:0]cfg_dsn;
  input [7:0]cfg_ds_bus_number;
  input [7:0]cfg_interrupt_di;
  input [8:0]pcie_drp_addr;
  input [9:0]cfg_mgmt_dwaddr;

  wire CLK;
  wire [0:0]E;
  wire [15:0]Q;
  wire bridge_reset_int;
  wire cfg_aer_ecrc_check_en;
  wire cfg_aer_ecrc_gen_en;
  wire [4:0]cfg_aer_interrupt_msgnum;
  wire cfg_aer_rooterr_corr_err_received;
  wire cfg_aer_rooterr_corr_err_reporting_en;
  wire cfg_aer_rooterr_fatal_err_received;
  wire cfg_aer_rooterr_fatal_err_reporting_en;
  wire cfg_aer_rooterr_non_fatal_err_received;
  wire cfg_aer_rooterr_non_fatal_err_reporting_en;
  wire cfg_bridge_serr_en;
  wire [4:0]cfg_command;
  wire [14:0]cfg_dcommand;
  wire [11:0]cfg_dcommand2;
  wire [7:0]cfg_ds_bus_number;
  wire [4:0]cfg_ds_device_number;
  wire [2:0]cfg_ds_function_number;
  wire [63:0]cfg_dsn;
  wire [3:0]cfg_dstatus;
  wire [127:0]cfg_err_aer_headerlog;
  wire cfg_err_aer_headerlog_set;
  wire cfg_err_aer_headerlog_set_n;
  wire cfg_err_atomic_egress_blocked;
  wire cfg_err_atomic_egress_blocked_n;
  wire cfg_err_cor;
  wire cfg_err_cor_n;
  wire cfg_err_cpl_abort;
  wire cfg_err_cpl_abort_n;
  wire cfg_err_cpl_rdy;
  wire cfg_err_cpl_rdy_n;
  wire cfg_err_cpl_timeout;
  wire cfg_err_cpl_timeout_n;
  wire cfg_err_cpl_unexpect;
  wire cfg_err_cpl_unexpect_n;
  wire cfg_err_ecrc;
  wire cfg_err_ecrc_n;
  wire cfg_err_internal_cor;
  wire cfg_err_internal_cor_n;
  wire cfg_err_internal_uncor;
  wire cfg_err_internal_uncor_n;
  wire cfg_err_locked;
  wire cfg_err_locked_n;
  wire cfg_err_malformed;
  wire cfg_err_malformed_n;
  wire cfg_err_mc_blocked;
  wire cfg_err_mc_blocked_n;
  wire cfg_err_norecovery;
  wire cfg_err_norecovery_n;
  wire cfg_err_poisoned;
  wire cfg_err_poisoned_n;
  wire cfg_err_posted;
  wire cfg_err_posted_n;
  wire [47:0]cfg_err_tlp_cpl_header;
  wire cfg_err_ur;
  wire cfg_err_ur_n;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire cfg_interrupt_assert_n;
  wire [7:0]cfg_interrupt_di;
  wire [7:0]cfg_interrupt_do;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_msixenable;
  wire cfg_interrupt_msixfm;
  wire cfg_interrupt_n;
  wire cfg_interrupt_rdy;
  wire cfg_interrupt_rdy_n;
  wire cfg_interrupt_stat;
  wire cfg_interrupt_stat_n;
  wire [10:0]cfg_lcommand;
  wire [9:0]cfg_lstatus;
  wire [3:0]cfg_mgmt_byte_en_n;
  wire [31:0]cfg_mgmt_di;
  wire [31:0]cfg_mgmt_do;
  wire [9:0]cfg_mgmt_dwaddr;
  wire cfg_mgmt_rd_en;
  wire cfg_mgmt_rd_en_n;
  wire cfg_mgmt_rd_wr_done;
  wire cfg_mgmt_rd_wr_done_n;
  wire cfg_mgmt_wr_en;
  wire cfg_mgmt_wr_en_n;
  wire cfg_mgmt_wr_readonly;
  wire cfg_mgmt_wr_readonly_n;
  wire cfg_mgmt_wr_rw1c_as_rw;
  wire cfg_mgmt_wr_rw1c_as_rw_n;
  wire [15:0]cfg_msg_data;
  wire cfg_msg_received;
  wire cfg_msg_received_assert_int_a;
  wire cfg_msg_received_assert_int_b;
  wire cfg_msg_received_assert_int_c;
  wire cfg_msg_received_assert_int_d;
  wire cfg_msg_received_deassert_int_a;
  wire cfg_msg_received_deassert_int_b;
  wire cfg_msg_received_deassert_int_c;
  wire cfg_msg_received_deassert_int_d;
  wire cfg_msg_received_err_cor;
  wire cfg_msg_received_err_fatal;
  wire cfg_msg_received_err_non_fatal;
  wire cfg_msg_received_pm_as_nak;
  wire cfg_msg_received_pm_pme;
  wire cfg_msg_received_pme_to_ack;
  wire cfg_msg_received_setslotpowerlimit;
  wire [2:0]cfg_pcie_link_state;
  wire [4:0]cfg_pciecap_interrupt_msgnum;
  wire [1:0]cfg_pm_force_state;
  wire cfg_pm_force_state_en;
  wire cfg_pm_force_state_en_n;
  wire cfg_pm_halt_aspm_l0s;
  wire cfg_pm_halt_aspm_l0s_n;
  wire cfg_pm_halt_aspm_l1;
  wire cfg_pm_halt_aspm_l1_n;
  wire cfg_pm_turnoff_ok_n;
  wire cfg_pm_wake;
  wire cfg_pm_wake_n;
  wire cfg_pmcsr_pme_en;
  wire cfg_pmcsr_pme_status;
  wire [1:0]cfg_pmcsr_powerstate;
  wire cfg_received_func_lvl_rst;
  wire cfg_root_control_pme_int_en;
  wire cfg_root_control_syserr_corr_err_en;
  wire cfg_root_control_syserr_fatal_err_en;
  wire cfg_root_control_syserr_non_fatal_err_en;
  wire cfg_slot_control_electromech_il_ctl_pulse;
  wire cfg_to_turnoff;
  wire cfg_trn_pending;
  wire cfg_trn_pending_n;
  wire [6:0]cfg_vc_tcvc_map;
  wire [11:0]fc_cpld;
  wire [7:0]fc_cplh;
  wire [11:0]fc_npd;
  wire [7:0]fc_nph;
  wire [11:0]fc_pd;
  wire [7:0]fc_ph;
  wire [2:0]fc_sel;
  wire [12:0]mim_rx_raddr;
  wire mim_rx_ren;
  wire [12:0]mim_rx_waddr;
  wire [67:0]mim_rx_wdata;
  wire mim_rx_wen;
  wire [12:0]mim_tx_raddr;
  wire mim_tx_ren;
  wire [12:0]mim_tx_waddr;
  wire [68:0]mim_tx_wdata;
  wire mim_tx_wen;
  wire pcie_block_i_n_100;
  wire pcie_block_i_n_101;
  wire pcie_block_i_n_102;
  wire pcie_block_i_n_103;
  wire pcie_block_i_n_104;
  wire pcie_block_i_n_105;
  wire pcie_block_i_n_106;
  wire pcie_block_i_n_107;
  wire pcie_block_i_n_108;
  wire pcie_block_i_n_1097;
  wire pcie_block_i_n_1098;
  wire pcie_block_i_n_1099;
  wire pcie_block_i_n_1100;
  wire pcie_block_i_n_1101;
  wire pcie_block_i_n_1102;
  wire pcie_block_i_n_1103;
  wire pcie_block_i_n_1143;
  wire pcie_block_i_n_140;
  wire pcie_block_i_n_141;
  wire pcie_block_i_n_142;
  wire pcie_block_i_n_143;
  wire pcie_block_i_n_144;
  wire pcie_block_i_n_145;
  wire pcie_block_i_n_146;
  wire pcie_block_i_n_155;
  wire pcie_block_i_n_156;
  wire pcie_block_i_n_157;
  wire pcie_block_i_n_158;
  wire pcie_block_i_n_159;
  wire pcie_block_i_n_160;
  wire pcie_block_i_n_169;
  wire pcie_block_i_n_172;
  wire pcie_block_i_n_173;
  wire pcie_block_i_n_174;
  wire pcie_block_i_n_175;
  wire pcie_block_i_n_176;
  wire pcie_block_i_n_177;
  wire pcie_block_i_n_178;
  wire pcie_block_i_n_179;
  wire pcie_block_i_n_180;
  wire pcie_block_i_n_181;
  wire pcie_block_i_n_182;
  wire pcie_block_i_n_183;
  wire pcie_block_i_n_184;
  wire pcie_block_i_n_185;
  wire pcie_block_i_n_186;
  wire pcie_block_i_n_187;
  wire pcie_block_i_n_188;
  wire pcie_block_i_n_189;
  wire pcie_block_i_n_190;
  wire pcie_block_i_n_191;
  wire pcie_block_i_n_192;
  wire pcie_block_i_n_193;
  wire pcie_block_i_n_194;
  wire pcie_block_i_n_195;
  wire pcie_block_i_n_610;
  wire pcie_block_i_n_611;
  wire pcie_block_i_n_618;
  wire pcie_block_i_n_619;
  wire pcie_block_i_n_687;
  wire pcie_block_i_n_688;
  wire pcie_block_i_n_689;
  wire pcie_block_i_n_690;
  wire pcie_block_i_n_691;
  wire pcie_block_i_n_704;
  wire pcie_block_i_n_705;
  wire pcie_block_i_n_706;
  wire pcie_block_i_n_707;
  wire pcie_block_i_n_708;
  wire pcie_block_i_n_709;
  wire pcie_block_i_n_710;
  wire pcie_block_i_n_711;
  wire pcie_block_i_n_712;
  wire pcie_block_i_n_713;
  wire pcie_block_i_n_714;
  wire pcie_block_i_n_715;
  wire pcie_block_i_n_716;
  wire pcie_block_i_n_717;
  wire pcie_block_i_n_718;
  wire pcie_block_i_n_719;
  wire pcie_block_i_n_72;
  wire pcie_block_i_n_720;
  wire pcie_block_i_n_721;
  wire pcie_block_i_n_722;
  wire pcie_block_i_n_723;
  wire pcie_block_i_n_724;
  wire pcie_block_i_n_725;
  wire pcie_block_i_n_726;
  wire pcie_block_i_n_727;
  wire pcie_block_i_n_728;
  wire pcie_block_i_n_729;
  wire pcie_block_i_n_730;
  wire pcie_block_i_n_731;
  wire pcie_block_i_n_732;
  wire pcie_block_i_n_733;
  wire pcie_block_i_n_734;
  wire pcie_block_i_n_735;
  wire pcie_block_i_n_736;
  wire pcie_block_i_n_737;
  wire pcie_block_i_n_738;
  wire pcie_block_i_n_739;
  wire pcie_block_i_n_740;
  wire pcie_block_i_n_741;
  wire pcie_block_i_n_742;
  wire pcie_block_i_n_743;
  wire pcie_block_i_n_744;
  wire pcie_block_i_n_745;
  wire pcie_block_i_n_746;
  wire pcie_block_i_n_747;
  wire pcie_block_i_n_748;
  wire pcie_block_i_n_749;
  wire pcie_block_i_n_75;
  wire pcie_block_i_n_750;
  wire pcie_block_i_n_751;
  wire pcie_block_i_n_752;
  wire pcie_block_i_n_753;
  wire pcie_block_i_n_754;
  wire pcie_block_i_n_755;
  wire pcie_block_i_n_756;
  wire pcie_block_i_n_757;
  wire pcie_block_i_n_758;
  wire pcie_block_i_n_759;
  wire pcie_block_i_n_76;
  wire pcie_block_i_n_760;
  wire pcie_block_i_n_761;
  wire pcie_block_i_n_762;
  wire pcie_block_i_n_763;
  wire pcie_block_i_n_764;
  wire pcie_block_i_n_765;
  wire pcie_block_i_n_766;
  wire pcie_block_i_n_767;
  wire pcie_block_i_n_768;
  wire pcie_block_i_n_769;
  wire pcie_block_i_n_77;
  wire pcie_block_i_n_770;
  wire pcie_block_i_n_771;
  wire pcie_block_i_n_772;
  wire pcie_block_i_n_773;
  wire pcie_block_i_n_774;
  wire pcie_block_i_n_775;
  wire pcie_block_i_n_776;
  wire pcie_block_i_n_777;
  wire pcie_block_i_n_778;
  wire pcie_block_i_n_779;
  wire pcie_block_i_n_78;
  wire pcie_block_i_n_780;
  wire pcie_block_i_n_781;
  wire pcie_block_i_n_782;
  wire pcie_block_i_n_783;
  wire pcie_block_i_n_784;
  wire pcie_block_i_n_785;
  wire pcie_block_i_n_786;
  wire pcie_block_i_n_787;
  wire pcie_block_i_n_788;
  wire pcie_block_i_n_789;
  wire pcie_block_i_n_790;
  wire pcie_block_i_n_791;
  wire pcie_block_i_n_792;
  wire pcie_block_i_n_793;
  wire pcie_block_i_n_794;
  wire pcie_block_i_n_795;
  wire pcie_block_i_n_796;
  wire pcie_block_i_n_797;
  wire pcie_block_i_n_798;
  wire pcie_block_i_n_799;
  wire pcie_block_i_n_800;
  wire pcie_block_i_n_801;
  wire pcie_block_i_n_802;
  wire pcie_block_i_n_803;
  wire pcie_block_i_n_804;
  wire pcie_block_i_n_805;
  wire pcie_block_i_n_806;
  wire pcie_block_i_n_807;
  wire pcie_block_i_n_808;
  wire pcie_block_i_n_809;
  wire pcie_block_i_n_810;
  wire pcie_block_i_n_811;
  wire pcie_block_i_n_812;
  wire pcie_block_i_n_813;
  wire pcie_block_i_n_814;
  wire pcie_block_i_n_815;
  wire pcie_block_i_n_816;
  wire pcie_block_i_n_817;
  wire pcie_block_i_n_818;
  wire pcie_block_i_n_819;
  wire pcie_block_i_n_820;
  wire pcie_block_i_n_821;
  wire pcie_block_i_n_822;
  wire pcie_block_i_n_823;
  wire pcie_block_i_n_824;
  wire pcie_block_i_n_825;
  wire pcie_block_i_n_826;
  wire pcie_block_i_n_827;
  wire pcie_block_i_n_828;
  wire pcie_block_i_n_829;
  wire pcie_block_i_n_830;
  wire pcie_block_i_n_831;
  wire pcie_block_i_n_832;
  wire pcie_block_i_n_833;
  wire pcie_block_i_n_834;
  wire pcie_block_i_n_835;
  wire pcie_block_i_n_836;
  wire pcie_block_i_n_837;
  wire pcie_block_i_n_838;
  wire pcie_block_i_n_839;
  wire pcie_block_i_n_84;
  wire pcie_block_i_n_840;
  wire pcie_block_i_n_841;
  wire pcie_block_i_n_842;
  wire pcie_block_i_n_843;
  wire pcie_block_i_n_844;
  wire pcie_block_i_n_845;
  wire pcie_block_i_n_846;
  wire pcie_block_i_n_847;
  wire pcie_block_i_n_848;
  wire pcie_block_i_n_849;
  wire pcie_block_i_n_85;
  wire pcie_block_i_n_850;
  wire pcie_block_i_n_851;
  wire pcie_block_i_n_852;
  wire pcie_block_i_n_853;
  wire pcie_block_i_n_854;
  wire pcie_block_i_n_855;
  wire pcie_block_i_n_856;
  wire pcie_block_i_n_857;
  wire pcie_block_i_n_858;
  wire pcie_block_i_n_859;
  wire pcie_block_i_n_86;
  wire pcie_block_i_n_860;
  wire pcie_block_i_n_861;
  wire pcie_block_i_n_862;
  wire pcie_block_i_n_863;
  wire pcie_block_i_n_864;
  wire pcie_block_i_n_865;
  wire pcie_block_i_n_866;
  wire pcie_block_i_n_867;
  wire pcie_block_i_n_868;
  wire pcie_block_i_n_869;
  wire pcie_block_i_n_87;
  wire pcie_block_i_n_870;
  wire pcie_block_i_n_871;
  wire pcie_block_i_n_872;
  wire pcie_block_i_n_873;
  wire pcie_block_i_n_874;
  wire pcie_block_i_n_875;
  wire pcie_block_i_n_876;
  wire pcie_block_i_n_877;
  wire pcie_block_i_n_878;
  wire pcie_block_i_n_879;
  wire pcie_block_i_n_88;
  wire pcie_block_i_n_880;
  wire pcie_block_i_n_881;
  wire pcie_block_i_n_882;
  wire pcie_block_i_n_883;
  wire pcie_block_i_n_884;
  wire pcie_block_i_n_885;
  wire pcie_block_i_n_886;
  wire pcie_block_i_n_887;
  wire pcie_block_i_n_888;
  wire pcie_block_i_n_889;
  wire pcie_block_i_n_89;
  wire pcie_block_i_n_890;
  wire pcie_block_i_n_891;
  wire pcie_block_i_n_892;
  wire pcie_block_i_n_893;
  wire pcie_block_i_n_894;
  wire pcie_block_i_n_895;
  wire pcie_block_i_n_896;
  wire pcie_block_i_n_897;
  wire pcie_block_i_n_898;
  wire pcie_block_i_n_899;
  wire pcie_block_i_n_90;
  wire pcie_block_i_n_900;
  wire pcie_block_i_n_901;
  wire pcie_block_i_n_902;
  wire pcie_block_i_n_903;
  wire pcie_block_i_n_904;
  wire pcie_block_i_n_905;
  wire pcie_block_i_n_906;
  wire pcie_block_i_n_907;
  wire pcie_block_i_n_908;
  wire pcie_block_i_n_909;
  wire pcie_block_i_n_91;
  wire pcie_block_i_n_910;
  wire pcie_block_i_n_911;
  wire pcie_block_i_n_912;
  wire pcie_block_i_n_913;
  wire pcie_block_i_n_914;
  wire pcie_block_i_n_915;
  wire pcie_block_i_n_916;
  wire pcie_block_i_n_917;
  wire pcie_block_i_n_918;
  wire pcie_block_i_n_919;
  wire pcie_block_i_n_92;
  wire pcie_block_i_n_920;
  wire pcie_block_i_n_921;
  wire pcie_block_i_n_922;
  wire pcie_block_i_n_923;
  wire pcie_block_i_n_924;
  wire pcie_block_i_n_925;
  wire pcie_block_i_n_926;
  wire pcie_block_i_n_927;
  wire pcie_block_i_n_928;
  wire pcie_block_i_n_929;
  wire pcie_block_i_n_93;
  wire pcie_block_i_n_930;
  wire pcie_block_i_n_931;
  wire pcie_block_i_n_932;
  wire pcie_block_i_n_933;
  wire pcie_block_i_n_934;
  wire pcie_block_i_n_935;
  wire pcie_block_i_n_936;
  wire pcie_block_i_n_937;
  wire pcie_block_i_n_938;
  wire pcie_block_i_n_939;
  wire pcie_block_i_n_94;
  wire pcie_block_i_n_940;
  wire pcie_block_i_n_941;
  wire pcie_block_i_n_942;
  wire pcie_block_i_n_943;
  wire pcie_block_i_n_944;
  wire pcie_block_i_n_945;
  wire pcie_block_i_n_946;
  wire pcie_block_i_n_947;
  wire pcie_block_i_n_948;
  wire pcie_block_i_n_949;
  wire pcie_block_i_n_95;
  wire pcie_block_i_n_950;
  wire pcie_block_i_n_951;
  wire pcie_block_i_n_952;
  wire pcie_block_i_n_953;
  wire pcie_block_i_n_954;
  wire pcie_block_i_n_955;
  wire pcie_block_i_n_956;
  wire pcie_block_i_n_957;
  wire pcie_block_i_n_958;
  wire pcie_block_i_n_959;
  wire pcie_block_i_n_96;
  wire pcie_block_i_n_98;
  wire pcie_block_i_n_99;
  wire pcie_bram_top_n_0;
  wire pcie_bram_top_n_1;
  wire pcie_bram_top_n_10;
  wire pcie_bram_top_n_100;
  wire pcie_bram_top_n_101;
  wire pcie_bram_top_n_102;
  wire pcie_bram_top_n_103;
  wire pcie_bram_top_n_104;
  wire pcie_bram_top_n_105;
  wire pcie_bram_top_n_106;
  wire pcie_bram_top_n_107;
  wire pcie_bram_top_n_108;
  wire pcie_bram_top_n_109;
  wire pcie_bram_top_n_11;
  wire pcie_bram_top_n_110;
  wire pcie_bram_top_n_111;
  wire pcie_bram_top_n_112;
  wire pcie_bram_top_n_113;
  wire pcie_bram_top_n_114;
  wire pcie_bram_top_n_115;
  wire pcie_bram_top_n_116;
  wire pcie_bram_top_n_117;
  wire pcie_bram_top_n_118;
  wire pcie_bram_top_n_119;
  wire pcie_bram_top_n_12;
  wire pcie_bram_top_n_120;
  wire pcie_bram_top_n_121;
  wire pcie_bram_top_n_122;
  wire pcie_bram_top_n_123;
  wire pcie_bram_top_n_124;
  wire pcie_bram_top_n_125;
  wire pcie_bram_top_n_126;
  wire pcie_bram_top_n_127;
  wire pcie_bram_top_n_128;
  wire pcie_bram_top_n_129;
  wire pcie_bram_top_n_13;
  wire pcie_bram_top_n_130;
  wire pcie_bram_top_n_131;
  wire pcie_bram_top_n_132;
  wire pcie_bram_top_n_133;
  wire pcie_bram_top_n_134;
  wire pcie_bram_top_n_135;
  wire pcie_bram_top_n_136;
  wire pcie_bram_top_n_14;
  wire pcie_bram_top_n_15;
  wire pcie_bram_top_n_16;
  wire pcie_bram_top_n_17;
  wire pcie_bram_top_n_18;
  wire pcie_bram_top_n_19;
  wire pcie_bram_top_n_2;
  wire pcie_bram_top_n_20;
  wire pcie_bram_top_n_21;
  wire pcie_bram_top_n_22;
  wire pcie_bram_top_n_23;
  wire pcie_bram_top_n_24;
  wire pcie_bram_top_n_25;
  wire pcie_bram_top_n_26;
  wire pcie_bram_top_n_27;
  wire pcie_bram_top_n_28;
  wire pcie_bram_top_n_29;
  wire pcie_bram_top_n_3;
  wire pcie_bram_top_n_30;
  wire pcie_bram_top_n_31;
  wire pcie_bram_top_n_32;
  wire pcie_bram_top_n_33;
  wire pcie_bram_top_n_34;
  wire pcie_bram_top_n_35;
  wire pcie_bram_top_n_36;
  wire pcie_bram_top_n_37;
  wire pcie_bram_top_n_38;
  wire pcie_bram_top_n_39;
  wire pcie_bram_top_n_4;
  wire pcie_bram_top_n_40;
  wire pcie_bram_top_n_41;
  wire pcie_bram_top_n_42;
  wire pcie_bram_top_n_43;
  wire pcie_bram_top_n_44;
  wire pcie_bram_top_n_45;
  wire pcie_bram_top_n_46;
  wire pcie_bram_top_n_47;
  wire pcie_bram_top_n_48;
  wire pcie_bram_top_n_49;
  wire pcie_bram_top_n_5;
  wire pcie_bram_top_n_50;
  wire pcie_bram_top_n_51;
  wire pcie_bram_top_n_52;
  wire pcie_bram_top_n_53;
  wire pcie_bram_top_n_54;
  wire pcie_bram_top_n_55;
  wire pcie_bram_top_n_56;
  wire pcie_bram_top_n_57;
  wire pcie_bram_top_n_58;
  wire pcie_bram_top_n_59;
  wire pcie_bram_top_n_6;
  wire pcie_bram_top_n_60;
  wire pcie_bram_top_n_61;
  wire pcie_bram_top_n_62;
  wire pcie_bram_top_n_63;
  wire pcie_bram_top_n_64;
  wire pcie_bram_top_n_65;
  wire pcie_bram_top_n_66;
  wire pcie_bram_top_n_67;
  wire pcie_bram_top_n_68;
  wire pcie_bram_top_n_69;
  wire pcie_bram_top_n_7;
  wire pcie_bram_top_n_70;
  wire pcie_bram_top_n_71;
  wire pcie_bram_top_n_72;
  wire pcie_bram_top_n_73;
  wire pcie_bram_top_n_74;
  wire pcie_bram_top_n_75;
  wire pcie_bram_top_n_76;
  wire pcie_bram_top_n_77;
  wire pcie_bram_top_n_78;
  wire pcie_bram_top_n_79;
  wire pcie_bram_top_n_8;
  wire pcie_bram_top_n_80;
  wire pcie_bram_top_n_81;
  wire pcie_bram_top_n_82;
  wire pcie_bram_top_n_83;
  wire pcie_bram_top_n_84;
  wire pcie_bram_top_n_85;
  wire pcie_bram_top_n_86;
  wire pcie_bram_top_n_87;
  wire pcie_bram_top_n_88;
  wire pcie_bram_top_n_89;
  wire pcie_bram_top_n_9;
  wire pcie_bram_top_n_90;
  wire pcie_bram_top_n_91;
  wire pcie_bram_top_n_92;
  wire pcie_bram_top_n_93;
  wire pcie_bram_top_n_94;
  wire pcie_bram_top_n_95;
  wire pcie_bram_top_n_96;
  wire pcie_bram_top_n_97;
  wire pcie_bram_top_n_98;
  wire pcie_bram_top_n_99;
  wire [8:0]pcie_drp_addr;
  wire pcie_drp_clk;
  wire [15:0]pcie_drp_di;
  wire [15:0]pcie_drp_do;
  wire pcie_drp_en;
  wire pcie_drp_rdy;
  wire pcie_drp_we;
  wire pipe_rx0_chanisaligned;
  wire pipe_rx0_elec_idle;
  wire pipe_rx0_phy_status;
  wire pipe_rx0_polarity;
  wire pipe_rx0_valid;
  wire pipe_rx1_chanisaligned;
  wire pipe_rx1_elec_idle;
  wire pipe_rx1_phy_status;
  wire pipe_rx1_polarity;
  wire pipe_rx1_valid;
  wire pipe_rx2_chanisaligned;
  wire pipe_rx2_elec_idle;
  wire pipe_rx2_phy_status;
  wire pipe_rx2_polarity;
  wire pipe_rx2_valid;
  wire pipe_rx3_chanisaligned;
  wire pipe_rx3_elec_idle;
  wire pipe_rx3_phy_status;
  wire pipe_rx3_polarity;
  wire pipe_rx3_valid;
  wire pipe_rx4_chanisaligned;
  wire pipe_rx4_elec_idle;
  wire pipe_rx4_phy_status;
  wire pipe_rx4_polarity;
  wire pipe_rx4_valid;
  wire pipe_rx5_chanisaligned;
  wire pipe_rx5_elec_idle;
  wire pipe_rx5_phy_status;
  wire pipe_rx5_polarity;
  wire pipe_rx5_valid;
  wire pipe_rx6_chanisaligned;
  wire pipe_rx6_elec_idle;
  wire pipe_rx6_phy_status;
  wire pipe_rx6_polarity;
  wire pipe_rx6_valid;
  wire pipe_rx7_chanisaligned;
  wire pipe_rx7_elec_idle;
  wire pipe_rx7_phy_status;
  wire pipe_rx7_polarity;
  wire pipe_rx7_valid;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5 ;
  wire [1:0]\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_6 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15] ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_3 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_4 ;
  wire [15:0]\pipe_stages_1.pipe_rx_data_q_reg[15]_5 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2] ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_3 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_4 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_5 ;
  wire [2:0]\pipe_stages_1.pipe_rx_status_q_reg[2]_6 ;
  wire [1:0]pipe_tx0_char_is_k;
  wire pipe_tx0_compliance;
  wire [15:0]pipe_tx0_data;
  wire pipe_tx0_elec_idle;
  wire [1:0]pipe_tx0_powerdown;
  wire [1:0]pipe_tx1_char_is_k;
  wire pipe_tx1_compliance;
  wire [15:0]pipe_tx1_data;
  wire pipe_tx1_elec_idle;
  wire [1:0]pipe_tx1_powerdown;
  wire [1:0]pipe_tx2_char_is_k;
  wire pipe_tx2_compliance;
  wire [15:0]pipe_tx2_data;
  wire pipe_tx2_elec_idle;
  wire [1:0]pipe_tx2_powerdown;
  wire [1:0]pipe_tx3_char_is_k;
  wire pipe_tx3_compliance;
  wire [15:0]pipe_tx3_data;
  wire pipe_tx3_elec_idle;
  wire [1:0]pipe_tx3_powerdown;
  wire [1:0]pipe_tx4_char_is_k;
  wire pipe_tx4_compliance;
  wire [15:0]pipe_tx4_data;
  wire pipe_tx4_elec_idle;
  wire [1:0]pipe_tx4_powerdown;
  wire [1:0]pipe_tx5_char_is_k;
  wire pipe_tx5_compliance;
  wire [15:0]pipe_tx5_data;
  wire pipe_tx5_elec_idle;
  wire [1:0]pipe_tx5_powerdown;
  wire [1:0]pipe_tx6_char_is_k;
  wire pipe_tx6_compliance;
  wire [15:0]pipe_tx6_data;
  wire pipe_tx6_elec_idle;
  wire [1:0]pipe_tx6_powerdown;
  wire [1:0]pipe_tx7_char_is_k;
  wire pipe_tx7_compliance;
  wire [15:0]pipe_tx7_data;
  wire pipe_tx7_elec_idle;
  wire [1:0]pipe_tx7_powerdown;
  wire pipe_tx_deemph;
  wire [2:0]pipe_tx_margin;
  wire pipe_tx_rate;
  wire pipe_tx_rcvr_det;
  wire pl_directed_change_done;
  wire pl_directed_link_auton;
  wire [1:0]pl_directed_link_change;
  wire pl_directed_link_speed;
  wire [1:0]pl_directed_link_width;
  wire pl_downstream_deemph_source;
  wire [2:0]pl_initial_link_width;
  wire [1:0]pl_lane_reversal_mode;
  wire pl_link_gen2_cap;
  wire pl_link_partner_gen2_supported;
  wire pl_link_upcfg_cap;
  wire [5:0]pl_ltssm_state;
  wire pl_phy_lnk_up;
  wire pl_phy_lnk_up_n;
  wire pl_phy_lnk_up_q_reg;
  wire pl_received_hot_rst;
  wire [1:0]pl_rx_pm_state;
  wire pl_sel_lnk_rate;
  wire [1:0]pl_sel_lnk_width;
  wire pl_transmit_hot_rst;
  wire [2:0]pl_tx_pm_state;
  wire pl_upstream_prefer_deemph;
  wire ppm_L1_thrtl_reg;
  wire received_func_lvl_rst_n;
  wire reg_dsc_detect_reg;
  wire rsrc_rdy_filtered10_out;
  wire rx_np_ok;
  wire rx_np_req;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tvalid;
  wire sys_rst_n;
  wire \tbuf_av_d_reg[4] ;
  wire tbuf_av_gap_thrtl_i_6_n_0;
  wire tbuf_av_gap_thrtl_i_8_n_0;
  wire tbuf_av_gap_thrtl_reg;
  wire tbuf_av_gap_thrtl_reg_0;
  wire tbuf_av_min_trig;
  wire \tcfg_req_cnt_reg[1] ;
  wire tready_thrtl_xhdl1_reg;
  wire tready_thrtl_xhdl1_reg_0;
  wire tready_thrtl_xhdl1_reg_1;
  wire trn_in_packet_i_2_n_0;
  wire trn_in_packet_i_3__0_n_0;
  wire trn_in_packet_i_4_n_0;
  wire trn_in_packet_reg;
  wire trn_in_packet_reg_0;
  wire trn_lnk_up;
  wire [6:0]trn_rbar_hit;
  wire [63:0]trn_rd;
  wire trn_rdst_rdy;
  wire trn_recrc_err;
  wire trn_reof;
  wire trn_rerrfwd;
  wire [0:0]trn_rrem;
  wire trn_rsof;
  wire trn_rsrc_dsc;
  wire trn_rsrc_rdy;
  wire [5:0]trn_tbuf_av;
  wire trn_tcfg_gnt;
  wire trn_tcfg_req;
  wire [63:0]trn_td;
  wire trn_tdst_rdy;
  wire trn_teof;
  wire [0:0]trn_trem;
  wire trn_tsof;
  wire trn_tsrc_rdy;
  wire tx_err_drop;
  wire user_clk;
  wire user_reset_int_reg;
  wire user_reset_out_reg;
  wire user_rst_n;
  wire [3:0]\xhdl12.reg_tuser_reg[3] ;
  wire [127:64]NLW_pcie_block_i_TRNRD_UNCONNECTED;
  wire [1:1]NLW_pcie_block_i_TRNRREM_UNCONNECTED;
  wire [3:1]NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED;

  LUT1 #(
    .INIT(2'h1)) 
    \cfg_bus_number_d[7]_i_2 
       (.I0(cfg_msg_received),
        .O(E));
  LUT1 #(
    .INIT(2'h1)) 
    cfg_err_aer_headerlog_set_INST_0
       (.I0(cfg_err_aer_headerlog_set_n),
        .O(cfg_err_aer_headerlog_set));
  LUT1 #(
    .INIT(2'h1)) 
    cfg_err_cpl_rdy_INST_0
       (.I0(cfg_err_cpl_rdy_n),
        .O(cfg_err_cpl_rdy));
  LUT1 #(
    .INIT(2'h1)) 
    cfg_interrupt_rdy_INST_0
       (.I0(cfg_interrupt_rdy_n),
        .O(cfg_interrupt_rdy));
  LUT1 #(
    .INIT(2'h1)) 
    cfg_mgmt_rd_wr_done_INST_0
       (.I0(cfg_mgmt_rd_wr_done_n),
        .O(cfg_mgmt_rd_wr_done));
  LUT1 #(
    .INIT(2'h1)) 
    cfg_received_func_lvl_rst_INST_0
       (.I0(received_func_lvl_rst_n),
        .O(cfg_received_func_lvl_rst));
  (* box_type = "PRIMITIVE" *) 
  PCIE_2_1 #(
    .AER_BASE_PTR(12'h000),
    .AER_CAP_ECRC_CHECK_CAPABLE("FALSE"),
    .AER_CAP_ECRC_GEN_CAPABLE("FALSE"),
    .AER_CAP_ID(16'h0001),
    .AER_CAP_MULTIHEADER("FALSE"),
    .AER_CAP_NEXTPTR(12'h000),
    .AER_CAP_ON("FALSE"),
    .AER_CAP_OPTIONAL_ERR_SUPPORT(24'h000000),
    .AER_CAP_PERMIT_ROOTERR_UPDATE("FALSE"),
    .AER_CAP_VERSION(4'h1),
    .ALLOW_X8_GEN2("FALSE"),
    .BAR0(32'hFFFFFC00),
    .BAR1(32'h00000000),
    .BAR2(32'h00000000),
    .BAR3(32'h00000000),
    .BAR4(32'h00000000),
    .BAR5(32'h00000000),
    .CAPABILITIES_PTR(8'h40),
    .CARDBUS_CIS_POINTER(32'h00000000),
    .CFG_ECRC_ERR_CPLSTAT(0),
    .CLASS_CODE(24'h058000),
    .CMD_INTX_IMPLEMENTED("FALSE"),
    .CPL_TIMEOUT_DISABLE_SUPPORTED("FALSE"),
    .CPL_TIMEOUT_RANGES_SUPPORTED(4'h2),
    .CRM_MODULE_RSTS(7'h00),
    .DEV_CAP2_ARI_FORWARDING_SUPPORTED("FALSE"),
    .DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED("FALSE"),
    .DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED("FALSE"),
    .DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED("FALSE"),
    .DEV_CAP2_CAS128_COMPLETER_SUPPORTED("FALSE"),
    .DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED("FALSE"),
    .DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED("FALSE"),
    .DEV_CAP2_LTR_MECHANISM_SUPPORTED("FALSE"),
    .DEV_CAP2_MAX_ENDEND_TLP_PREFIXES(2'h0),
    .DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING("FALSE"),
    .DEV_CAP2_TPH_COMPLETER_SUPPORTED(2'h0),
    .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE("TRUE"),
    .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE("TRUE"),
    .DEV_CAP_ENDPOINT_L0S_LATENCY(0),
    .DEV_CAP_ENDPOINT_L1_LATENCY(7),
    .DEV_CAP_EXT_TAG_SUPPORTED("TRUE"),
    .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE("FALSE"),
    .DEV_CAP_MAX_PAYLOAD_SUPPORTED(2),
    .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT(0),
    .DEV_CAP_ROLE_BASED_ERROR("TRUE"),
    .DEV_CAP_RSVD_14_12(0),
    .DEV_CAP_RSVD_17_16(0),
    .DEV_CAP_RSVD_31_29(0),
    .DEV_CONTROL_AUX_POWER_SUPPORTED("FALSE"),
    .DEV_CONTROL_EXT_TAG_DEFAULT("FALSE"),
    .DISABLE_ASPM_L1_TIMER("FALSE"),
    .DISABLE_BAR_FILTERING("FALSE"),
    .DISABLE_ERR_MSG("FALSE"),
    .DISABLE_ID_CHECK("FALSE"),
    .DISABLE_LANE_REVERSAL("TRUE"),
    .DISABLE_LOCKED_FILTER("FALSE"),
    .DISABLE_PPM_FILTER("FALSE"),
    .DISABLE_RX_POISONED_RESP("FALSE"),
    .DISABLE_RX_TC_FILTER("FALSE"),
    .DISABLE_SCRAMBLING("FALSE"),
    .DNSTREAM_LINK_NUM(8'h00),
    .DSN_BASE_PTR(12'h100),
    .DSN_CAP_ID(16'h0003),
    .DSN_CAP_NEXTPTR(12'h000),
    .DSN_CAP_ON("TRUE"),
    .DSN_CAP_VERSION(4'h1),
    .ENABLE_MSG_ROUTE(11'h000),
    .ENABLE_RX_TD_ECRC_TRIM("FALSE"),
    .ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED("FALSE"),
    .ENTER_RVRY_EI_L0("TRUE"),
    .EXIT_LOOPBACK_ON_EI("TRUE"),
    .EXPANSION_ROM(32'h00000000),
    .EXT_CFG_CAP_PTR(6'h3F),
    .EXT_CFG_XP_CAP_PTR(10'h3FF),
    .HEADER_TYPE(8'h00),
    .INFER_EI(5'h00),
    .INTERRUPT_PIN(8'h00),
    .INTERRUPT_STAT_AUTO("TRUE"),
    .IS_SWITCH("FALSE"),
    .LAST_CONFIG_DWORD(10'h3FF),
    .LINK_CAP_ASPM_OPTIONALITY("FALSE"),
    .LINK_CAP_ASPM_SUPPORT(1),
    .LINK_CAP_CLOCK_POWER_MANAGEMENT("FALSE"),
    .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP("FALSE"),
    .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1(7),
    .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2(7),
    .LINK_CAP_L0S_EXIT_LATENCY_GEN1(7),
    .LINK_CAP_L0S_EXIT_LATENCY_GEN2(7),
    .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1(7),
    .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2(7),
    .LINK_CAP_L1_EXIT_LATENCY_GEN1(7),
    .LINK_CAP_L1_EXIT_LATENCY_GEN2(7),
    .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP("FALSE"),
    .LINK_CAP_MAX_LINK_SPEED(4'h1),
    .LINK_CAP_MAX_LINK_WIDTH(6'h08),
    .LINK_CAP_RSVD_23(0),
    .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE("FALSE"),
    .LINK_CONTROL_RCB(0),
    .LINK_CTRL2_DEEMPHASIS("FALSE"),
    .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE("FALSE"),
    .LINK_CTRL2_TARGET_LINK_SPEED(4'h0),
    .LINK_STATUS_SLOT_CLOCK_CONFIG("TRUE"),
    .LL_ACK_TIMEOUT(15'h0000),
    .LL_ACK_TIMEOUT_EN("FALSE"),
    .LL_ACK_TIMEOUT_FUNC(0),
    .LL_REPLAY_TIMEOUT(15'h0000),
    .LL_REPLAY_TIMEOUT_EN("FALSE"),
    .LL_REPLAY_TIMEOUT_FUNC(1),
    .LTSSM_MAX_LINK_WIDTH(6'h08),
    .MPS_FORCE("FALSE"),
    .MSIX_BASE_PTR(8'h9C),
    .MSIX_CAP_ID(8'h11),
    .MSIX_CAP_NEXTPTR(8'h00),
    .MSIX_CAP_ON("FALSE"),
    .MSIX_CAP_PBA_BIR(0),
    .MSIX_CAP_PBA_OFFSET(29'h00000000),
    .MSIX_CAP_TABLE_BIR(0),
    .MSIX_CAP_TABLE_OFFSET(29'h00000000),
    .MSIX_CAP_TABLE_SIZE(11'h000),
    .MSI_BASE_PTR(8'h48),
    .MSI_CAP_64_BIT_ADDR_CAPABLE("TRUE"),
    .MSI_CAP_ID(8'h05),
    .MSI_CAP_MULTIMSGCAP(0),
    .MSI_CAP_MULTIMSG_EXTENSION(0),
    .MSI_CAP_NEXTPTR(8'h60),
    .MSI_CAP_ON("TRUE"),
    .MSI_CAP_PER_VECTOR_MASKING_CAPABLE("FALSE"),
    .N_FTS_COMCLK_GEN1(255),
    .N_FTS_COMCLK_GEN2(255),
    .N_FTS_GEN1(255),
    .N_FTS_GEN2(255),
    .PCIE_BASE_PTR(8'h60),
    .PCIE_CAP_CAPABILITY_ID(8'h10),
    .PCIE_CAP_CAPABILITY_VERSION(4'h2),
    .PCIE_CAP_DEVICE_PORT_TYPE(4'h0),
    .PCIE_CAP_NEXTPTR(8'h00),
    .PCIE_CAP_ON("TRUE"),
    .PCIE_CAP_RSVD_15_14(0),
    .PCIE_CAP_SLOT_IMPLEMENTED("FALSE"),
    .PCIE_REVISION(2),
    .PL_AUTO_CONFIG(0),
    .PL_FAST_TRAIN("TRUE"),
    .PM_ASPML0S_TIMEOUT(15'h0000),
    .PM_ASPML0S_TIMEOUT_EN("FALSE"),
    .PM_ASPML0S_TIMEOUT_FUNC(0),
    .PM_ASPM_FASTEXIT("FALSE"),
    .PM_BASE_PTR(8'h40),
    .PM_CAP_AUXCURRENT(0),
    .PM_CAP_D1SUPPORT("FALSE"),
    .PM_CAP_D2SUPPORT("FALSE"),
    .PM_CAP_DSI("FALSE"),
    .PM_CAP_ID(8'h01),
    .PM_CAP_NEXTPTR(8'h48),
    .PM_CAP_ON("TRUE"),
    .PM_CAP_PMESUPPORT(5'h0F),
    .PM_CAP_PME_CLOCK("FALSE"),
    .PM_CAP_RSVD_04(0),
    .PM_CAP_VERSION(3),
    .PM_CSR_B2B3("FALSE"),
    .PM_CSR_BPCCEN("FALSE"),
    .PM_CSR_NOSOFTRST("TRUE"),
    .PM_DATA0(8'h00),
    .PM_DATA1(8'h00),
    .PM_DATA2(8'h00),
    .PM_DATA3(8'h00),
    .PM_DATA4(8'h00),
    .PM_DATA5(8'h00),
    .PM_DATA6(8'h00),
    .PM_DATA7(8'h00),
    .PM_DATA_SCALE0(2'h0),
    .PM_DATA_SCALE1(2'h0),
    .PM_DATA_SCALE2(2'h0),
    .PM_DATA_SCALE3(2'h0),
    .PM_DATA_SCALE4(2'h0),
    .PM_DATA_SCALE5(2'h0),
    .PM_DATA_SCALE6(2'h0),
    .PM_DATA_SCALE7(2'h0),
    .PM_MF("FALSE"),
    .RBAR_BASE_PTR(12'h000),
    .RBAR_CAP_CONTROL_ENCODEDBAR0(5'h00),
    .RBAR_CAP_CONTROL_ENCODEDBAR1(5'h00),
    .RBAR_CAP_CONTROL_ENCODEDBAR2(5'h00),
    .RBAR_CAP_CONTROL_ENCODEDBAR3(5'h00),
    .RBAR_CAP_CONTROL_ENCODEDBAR4(5'h00),
    .RBAR_CAP_CONTROL_ENCODEDBAR5(5'h00),
    .RBAR_CAP_ID(16'h0015),
    .RBAR_CAP_INDEX0(3'h0),
    .RBAR_CAP_INDEX1(3'h0),
    .RBAR_CAP_INDEX2(3'h0),
    .RBAR_CAP_INDEX3(3'h0),
    .RBAR_CAP_INDEX4(3'h0),
    .RBAR_CAP_INDEX5(3'h0),
    .RBAR_CAP_NEXTPTR(12'h000),
    .RBAR_CAP_ON("FALSE"),
    .RBAR_CAP_SUP0(32'h00000001),
    .RBAR_CAP_SUP1(32'h00000001),
    .RBAR_CAP_SUP2(32'h00000001),
    .RBAR_CAP_SUP3(32'h00000001),
    .RBAR_CAP_SUP4(32'h00000001),
    .RBAR_CAP_SUP5(32'h00000001),
    .RBAR_CAP_VERSION(4'h1),
    .RBAR_NUM(3'h0),
    .RECRC_CHK(0),
    .RECRC_CHK_TRIM("FALSE"),
    .ROOT_CAP_CRS_SW_VISIBILITY("FALSE"),
    .RP_AUTO_SPD(2'h1),
    .RP_AUTO_SPD_LOOPCNT(5'h1F),
    .SELECT_DLL_IF("FALSE"),
    .SIM_VERSION("1.0"),
    .SLOT_CAP_ATT_BUTTON_PRESENT("FALSE"),
    .SLOT_CAP_ATT_INDICATOR_PRESENT("FALSE"),
    .SLOT_CAP_ELEC_INTERLOCK_PRESENT("FALSE"),
    .SLOT_CAP_HOTPLUG_CAPABLE("FALSE"),
    .SLOT_CAP_HOTPLUG_SURPRISE("FALSE"),
    .SLOT_CAP_MRL_SENSOR_PRESENT("FALSE"),
    .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT("FALSE"),
    .SLOT_CAP_PHYSICAL_SLOT_NUM(13'h0000),
    .SLOT_CAP_POWER_CONTROLLER_PRESENT("FALSE"),
    .SLOT_CAP_POWER_INDICATOR_PRESENT("FALSE"),
    .SLOT_CAP_SLOT_POWER_LIMIT_SCALE(0),
    .SLOT_CAP_SLOT_POWER_LIMIT_VALUE(8'h00),
    .SPARE_BIT0(0),
    .SPARE_BIT1(0),
    .SPARE_BIT2(0),
    .SPARE_BIT3(0),
    .SPARE_BIT4(0),
    .SPARE_BIT5(0),
    .SPARE_BIT6(0),
    .SPARE_BIT7(0),
    .SPARE_BIT8(0),
    .SPARE_BYTE0(8'h00),
    .SPARE_BYTE1(8'h00),
    .SPARE_BYTE2(8'h00),
    .SPARE_BYTE3(8'h00),
    .SPARE_WORD0(32'h00000000),
    .SPARE_WORD1(32'h00000000),
    .SPARE_WORD2(32'h00000000),
    .SPARE_WORD3(32'h00000000),
    .SSL_MESSAGE_AUTO("FALSE"),
    .TECRC_EP_INV("FALSE"),
    .TL_RBYPASS("FALSE"),
    .TL_RX_RAM_RADDR_LATENCY(0),
    .TL_RX_RAM_RDATA_LATENCY(2),
    .TL_RX_RAM_WRITE_LATENCY(0),
    .TL_TFC_DISABLE("FALSE"),
    .TL_TX_CHECKS_DISABLE("FALSE"),
    .TL_TX_RAM_RADDR_LATENCY(0),
    .TL_TX_RAM_RDATA_LATENCY(2),
    .TL_TX_RAM_WRITE_LATENCY(0),
    .TRN_DW("FALSE"),
    .TRN_NP_FC("TRUE"),
    .UPCONFIG_CAPABLE("TRUE"),
    .UPSTREAM_FACING("TRUE"),
    .UR_ATOMIC("FALSE"),
    .UR_CFG1("TRUE"),
    .UR_INV_REQ("TRUE"),
    .UR_PRS_RESPONSE("TRUE"),
    .USER_CLK2_DIV2("FALSE"),
    .USER_CLK_FREQ(3),
    .USE_RID_PINS("FALSE"),
    .VC0_CPL_INFINITE("TRUE"),
    .VC0_RX_RAM_LIMIT(13'h07FF),
    .VC0_TOTAL_CREDITS_CD(850),
    .VC0_TOTAL_CREDITS_CH(72),
    .VC0_TOTAL_CREDITS_NPD(8),
    .VC0_TOTAL_CREDITS_NPH(4),
    .VC0_TOTAL_CREDITS_PD(64),
    .VC0_TOTAL_CREDITS_PH(4),
    .VC0_TX_LASTPACKET(29),
    .VC_BASE_PTR(12'h000),
    .VC_CAP_ID(16'h0002),
    .VC_CAP_NEXTPTR(12'h000),
    .VC_CAP_ON("FALSE"),
    .VC_CAP_REJECT_SNOOP_TRANSACTIONS("FALSE"),
    .VC_CAP_VERSION(4'h1),
    .VSEC_BASE_PTR(12'h000),
    .VSEC_CAP_HDR_ID(16'h1234),
    .VSEC_CAP_HDR_LENGTH(12'h018),
    .VSEC_CAP_HDR_REVISION(4'h1),
    .VSEC_CAP_ID(16'h000B),
    .VSEC_CAP_IS_LINK_VISIBLE("TRUE"),
    .VSEC_CAP_NEXTPTR(12'h000),
    .VSEC_CAP_ON("FALSE"),
    .VSEC_CAP_VERSION(4'h1)) 
    pcie_block_i
       (.CFGAERECRCCHECKEN(cfg_aer_ecrc_check_en),
        .CFGAERECRCGENEN(cfg_aer_ecrc_gen_en),
        .CFGAERINTERRUPTMSGNUM(cfg_aer_interrupt_msgnum),
        .CFGAERROOTERRCORRERRRECEIVED(cfg_aer_rooterr_corr_err_received),
        .CFGAERROOTERRCORRERRREPORTINGEN(cfg_aer_rooterr_corr_err_reporting_en),
        .CFGAERROOTERRFATALERRRECEIVED(cfg_aer_rooterr_fatal_err_received),
        .CFGAERROOTERRFATALERRREPORTINGEN(cfg_aer_rooterr_fatal_err_reporting_en),
        .CFGAERROOTERRNONFATALERRRECEIVED(cfg_aer_rooterr_non_fatal_err_received),
        .CFGAERROOTERRNONFATALERRREPORTINGEN(cfg_aer_rooterr_non_fatal_err_reporting_en),
        .CFGBRIDGESERREN(cfg_bridge_serr_en),
        .CFGCOMMANDBUSMASTERENABLE(cfg_command[2]),
        .CFGCOMMANDINTERRUPTDISABLE(cfg_command[4]),
        .CFGCOMMANDIOENABLE(cfg_command[0]),
        .CFGCOMMANDMEMENABLE(cfg_command[1]),
        .CFGCOMMANDSERREN(cfg_command[3]),
        .CFGDEVCONTROL2ARIFORWARDEN(cfg_dcommand2[5]),
        .CFGDEVCONTROL2ATOMICEGRESSBLOCK(cfg_dcommand2[7]),
        .CFGDEVCONTROL2ATOMICREQUESTEREN(cfg_dcommand2[6]),
        .CFGDEVCONTROL2CPLTIMEOUTDIS(cfg_dcommand2[4]),
        .CFGDEVCONTROL2CPLTIMEOUTVAL(cfg_dcommand2[3:0]),
        .CFGDEVCONTROL2IDOCPLEN(cfg_dcommand2[9]),
        .CFGDEVCONTROL2IDOREQEN(cfg_dcommand2[8]),
        .CFGDEVCONTROL2LTREN(cfg_dcommand2[10]),
        .CFGDEVCONTROL2TLPPREFIXBLOCK(cfg_dcommand2[11]),
        .CFGDEVCONTROLAUXPOWEREN(cfg_dcommand[10]),
        .CFGDEVCONTROLCORRERRREPORTINGEN(cfg_dcommand[0]),
        .CFGDEVCONTROLENABLERO(cfg_dcommand[4]),
        .CFGDEVCONTROLEXTTAGEN(cfg_dcommand[8]),
        .CFGDEVCONTROLFATALERRREPORTINGEN(cfg_dcommand[2]),
        .CFGDEVCONTROLMAXPAYLOAD(cfg_dcommand[7:5]),
        .CFGDEVCONTROLMAXREADREQ(cfg_dcommand[14:12]),
        .CFGDEVCONTROLNONFATALREPORTINGEN(cfg_dcommand[1]),
        .CFGDEVCONTROLNOSNOOPEN(cfg_dcommand[11]),
        .CFGDEVCONTROLPHANTOMEN(cfg_dcommand[9]),
        .CFGDEVCONTROLURERRREPORTINGEN(cfg_dcommand[3]),
        .CFGDEVID({1'b0,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b0,1'b0,1'b0}),
        .CFGDEVSTATUSCORRERRDETECTED(cfg_dstatus[0]),
        .CFGDEVSTATUSFATALERRDETECTED(cfg_dstatus[2]),
        .CFGDEVSTATUSNONFATALERRDETECTED(cfg_dstatus[1]),
        .CFGDEVSTATUSURDETECTED(cfg_dstatus[3]),
        .CFGDSBUSNUMBER(cfg_ds_bus_number),
        .CFGDSDEVICENUMBER(cfg_ds_device_number),
        .CFGDSFUNCTIONNUMBER(cfg_ds_function_number),
        .CFGDSN(cfg_dsn),
        .CFGERRACSN(1'b1),
        .CFGERRAERHEADERLOG(cfg_err_aer_headerlog),
        .CFGERRAERHEADERLOGSETN(cfg_err_aer_headerlog_set_n),
        .CFGERRATOMICEGRESSBLOCKEDN(cfg_err_atomic_egress_blocked_n),
        .CFGERRCORN(cfg_err_cor_n),
        .CFGERRCPLABORTN(cfg_err_cpl_abort_n),
        .CFGERRCPLRDYN(cfg_err_cpl_rdy_n),
        .CFGERRCPLTIMEOUTN(cfg_err_cpl_timeout_n),
        .CFGERRCPLUNEXPECTN(cfg_err_cpl_unexpect_n),
        .CFGERRECRCN(cfg_err_ecrc_n),
        .CFGERRINTERNALCORN(cfg_err_internal_cor_n),
        .CFGERRINTERNALUNCORN(cfg_err_internal_uncor_n),
        .CFGERRLOCKEDN(cfg_err_locked_n),
        .CFGERRMALFORMEDN(cfg_err_malformed_n),
        .CFGERRMCBLOCKEDN(cfg_err_mc_blocked_n),
        .CFGERRNORECOVERYN(cfg_err_norecovery_n),
        .CFGERRPOISONEDN(cfg_err_poisoned_n),
        .CFGERRPOSTEDN(cfg_err_posted_n),
        .CFGERRTLPCPLHEADER(cfg_err_tlp_cpl_header),
        .CFGERRURN(cfg_err_ur_n),
        .CFGFORCECOMMONCLOCKOFF(1'b0),
        .CFGFORCEEXTENDEDSYNCON(1'b0),
        .CFGFORCEMPS({1'b0,1'b0,1'b0}),
        .CFGINTERRUPTASSERTN(cfg_interrupt_assert_n),
        .CFGINTERRUPTDI(cfg_interrupt_di),
        .CFGINTERRUPTDO(cfg_interrupt_do),
        .CFGINTERRUPTMMENABLE(cfg_interrupt_mmenable),
        .CFGINTERRUPTMSIENABLE(cfg_interrupt_msienable),
        .CFGINTERRUPTMSIXENABLE(cfg_interrupt_msixenable),
        .CFGINTERRUPTMSIXFM(cfg_interrupt_msixfm),
        .CFGINTERRUPTN(cfg_interrupt_n),
        .CFGINTERRUPTRDYN(cfg_interrupt_rdy_n),
        .CFGINTERRUPTSTATN(cfg_interrupt_stat_n),
        .CFGLINKCONTROLASPMCONTROL(cfg_lcommand[1:0]),
        .CFGLINKCONTROLAUTOBANDWIDTHINTEN(cfg_lcommand[10]),
        .CFGLINKCONTROLBANDWIDTHINTEN(cfg_lcommand[9]),
        .CFGLINKCONTROLCLOCKPMEN(cfg_lcommand[7]),
        .CFGLINKCONTROLCOMMONCLOCK(cfg_lcommand[5]),
        .CFGLINKCONTROLEXTENDEDSYNC(cfg_lcommand[6]),
        .CFGLINKCONTROLHWAUTOWIDTHDIS(cfg_lcommand[8]),
        .CFGLINKCONTROLLINKDISABLE(cfg_lcommand[3]),
        .CFGLINKCONTROLRCB(cfg_lcommand[2]),
        .CFGLINKCONTROLRETRAINLINK(cfg_lcommand[4]),
        .CFGLINKSTATUSAUTOBANDWIDTHSTATUS(cfg_lstatus[9]),
        .CFGLINKSTATUSBANDWIDTHSTATUS(cfg_lstatus[8]),
        .CFGLINKSTATUSCURRENTSPEED(cfg_lstatus[1:0]),
        .CFGLINKSTATUSDLLACTIVE(cfg_lstatus[7]),
        .CFGLINKSTATUSLINKTRAINING(cfg_lstatus[6]),
        .CFGLINKSTATUSNEGOTIATEDWIDTH(cfg_lstatus[5:2]),
        .CFGMGMTBYTEENN(cfg_mgmt_byte_en_n),
        .CFGMGMTDI(cfg_mgmt_di),
        .CFGMGMTDO(cfg_mgmt_do),
        .CFGMGMTDWADDR(cfg_mgmt_dwaddr),
        .CFGMGMTRDENN(cfg_mgmt_rd_en_n),
        .CFGMGMTRDWRDONEN(cfg_mgmt_rd_wr_done_n),
        .CFGMGMTWRENN(cfg_mgmt_wr_en_n),
        .CFGMGMTWRREADONLYN(cfg_mgmt_wr_readonly_n),
        .CFGMGMTWRRW1CASRWN(cfg_mgmt_wr_rw1c_as_rw_n),
        .CFGMSGDATA(cfg_msg_data),
        .CFGMSGRECEIVED(cfg_msg_received),
        .CFGMSGRECEIVEDASSERTINTA(cfg_msg_received_assert_int_a),
        .CFGMSGRECEIVEDASSERTINTB(cfg_msg_received_assert_int_b),
        .CFGMSGRECEIVEDASSERTINTC(cfg_msg_received_assert_int_c),
        .CFGMSGRECEIVEDASSERTINTD(cfg_msg_received_assert_int_d),
        .CFGMSGRECEIVEDDEASSERTINTA(cfg_msg_received_deassert_int_a),
        .CFGMSGRECEIVEDDEASSERTINTB(cfg_msg_received_deassert_int_b),
        .CFGMSGRECEIVEDDEASSERTINTC(cfg_msg_received_deassert_int_c),
        .CFGMSGRECEIVEDDEASSERTINTD(cfg_msg_received_deassert_int_d),
        .CFGMSGRECEIVEDERRCOR(cfg_msg_received_err_cor),
        .CFGMSGRECEIVEDERRFATAL(cfg_msg_received_err_fatal),
        .CFGMSGRECEIVEDERRNONFATAL(cfg_msg_received_err_non_fatal),
        .CFGMSGRECEIVEDPMASNAK(cfg_msg_received_pm_as_nak),
        .CFGMSGRECEIVEDPMETO(cfg_to_turnoff),
        .CFGMSGRECEIVEDPMETOACK(cfg_msg_received_pme_to_ack),
        .CFGMSGRECEIVEDPMPME(cfg_msg_received_pm_pme),
        .CFGMSGRECEIVEDSETSLOTPOWERLIMIT(cfg_msg_received_setslotpowerlimit),
        .CFGMSGRECEIVEDUNLOCK(pcie_block_i_n_72),
        .CFGPCIECAPINTERRUPTMSGNUM(cfg_pciecap_interrupt_msgnum),
        .CFGPCIELINKSTATE(cfg_pcie_link_state),
        .CFGPMCSRPMEEN(cfg_pmcsr_pme_en),
        .CFGPMCSRPMESTATUS(cfg_pmcsr_pme_status),
        .CFGPMCSRPOWERSTATE(cfg_pmcsr_powerstate),
        .CFGPMFORCESTATE(cfg_pm_force_state),
        .CFGPMFORCESTATEENN(cfg_pm_force_state_en_n),
        .CFGPMHALTASPML0SN(cfg_pm_halt_aspm_l0s_n),
        .CFGPMHALTASPML1N(cfg_pm_halt_aspm_l1_n),
        .CFGPMRCVASREQL1N(pcie_block_i_n_75),
        .CFGPMRCVENTERL1N(pcie_block_i_n_76),
        .CFGPMRCVENTERL23N(pcie_block_i_n_77),
        .CFGPMRCVREQACKN(pcie_block_i_n_78),
        .CFGPMSENDPMETON(1'b1),
        .CFGPMTURNOFFOKN(cfg_pm_turnoff_ok_n),
        .CFGPMWAKEN(cfg_pm_wake_n),
        .CFGPORTNUMBER({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CFGREVID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CFGROOTCONTROLPMEINTEN(cfg_root_control_pme_int_en),
        .CFGROOTCONTROLSYSERRCORRERREN(cfg_root_control_syserr_corr_err_en),
        .CFGROOTCONTROLSYSERRFATALERREN(cfg_root_control_syserr_fatal_err_en),
        .CFGROOTCONTROLSYSERRNONFATALERREN(cfg_root_control_syserr_non_fatal_err_en),
        .CFGSLOTCONTROLELECTROMECHILCTLPULSE(cfg_slot_control_electromech_il_ctl_pulse),
        .CFGSUBSYSID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1}),
        .CFGSUBSYSVENDID({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b1,1'b1,1'b1,1'b0}),
        .CFGTRANSACTION(pcie_block_i_n_84),
        .CFGTRANSACTIONADDR({pcie_block_i_n_1097,pcie_block_i_n_1098,pcie_block_i_n_1099,pcie_block_i_n_1100,pcie_block_i_n_1101,pcie_block_i_n_1102,pcie_block_i_n_1103}),
        .CFGTRANSACTIONTYPE(pcie_block_i_n_85),
        .CFGTRNPENDINGN(cfg_trn_pending_n),
        .CFGVCTCVCMAP(cfg_vc_tcvc_map),
        .CFGVENDID({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0,1'b1,1'b1,1'b1,1'b0}),
        .CMRSTN(1'b1),
        .CMSTICKYRSTN(1'b1),
        .DBGMODE({1'b0,1'b0}),
        .DBGSCLRA(pcie_block_i_n_86),
        .DBGSCLRB(pcie_block_i_n_87),
        .DBGSCLRC(pcie_block_i_n_88),
        .DBGSCLRD(pcie_block_i_n_89),
        .DBGSCLRE(pcie_block_i_n_90),
        .DBGSCLRF(pcie_block_i_n_91),
        .DBGSCLRG(pcie_block_i_n_92),
        .DBGSCLRH(pcie_block_i_n_93),
        .DBGSCLRI(pcie_block_i_n_94),
        .DBGSCLRJ(pcie_block_i_n_95),
        .DBGSCLRK(pcie_block_i_n_96),
        .DBGSUBMODE(1'b0),
        .DBGVECA({pcie_block_i_n_704,pcie_block_i_n_705,pcie_block_i_n_706,pcie_block_i_n_707,pcie_block_i_n_708,pcie_block_i_n_709,pcie_block_i_n_710,pcie_block_i_n_711,pcie_block_i_n_712,pcie_block_i_n_713,pcie_block_i_n_714,pcie_block_i_n_715,pcie_block_i_n_716,pcie_block_i_n_717,pcie_block_i_n_718,pcie_block_i_n_719,pcie_block_i_n_720,pcie_block_i_n_721,pcie_block_i_n_722,pcie_block_i_n_723,pcie_block_i_n_724,pcie_block_i_n_725,pcie_block_i_n_726,pcie_block_i_n_727,pcie_block_i_n_728,pcie_block_i_n_729,pcie_block_i_n_730,pcie_block_i_n_731,pcie_block_i_n_732,pcie_block_i_n_733,pcie_block_i_n_734,pcie_block_i_n_735,pcie_block_i_n_736,pcie_block_i_n_737,pcie_block_i_n_738,pcie_block_i_n_739,pcie_block_i_n_740,pcie_block_i_n_741,pcie_block_i_n_742,pcie_block_i_n_743,pcie_block_i_n_744,pcie_block_i_n_745,pcie_block_i_n_746,pcie_block_i_n_747,pcie_block_i_n_748,pcie_block_i_n_749,pcie_block_i_n_750,pcie_block_i_n_751,pcie_block_i_n_752,pcie_block_i_n_753,pcie_block_i_n_754,pcie_block_i_n_755,pcie_block_i_n_756,pcie_block_i_n_757,pcie_block_i_n_758,pcie_block_i_n_759,pcie_block_i_n_760,pcie_block_i_n_761,pcie_block_i_n_762,pcie_block_i_n_763,pcie_block_i_n_764,pcie_block_i_n_765,pcie_block_i_n_766,pcie_block_i_n_767}),
        .DBGVECB({pcie_block_i_n_768,pcie_block_i_n_769,pcie_block_i_n_770,pcie_block_i_n_771,pcie_block_i_n_772,pcie_block_i_n_773,pcie_block_i_n_774,pcie_block_i_n_775,pcie_block_i_n_776,pcie_block_i_n_777,pcie_block_i_n_778,pcie_block_i_n_779,pcie_block_i_n_780,pcie_block_i_n_781,pcie_block_i_n_782,pcie_block_i_n_783,pcie_block_i_n_784,pcie_block_i_n_785,pcie_block_i_n_786,pcie_block_i_n_787,pcie_block_i_n_788,pcie_block_i_n_789,pcie_block_i_n_790,pcie_block_i_n_791,pcie_block_i_n_792,pcie_block_i_n_793,pcie_block_i_n_794,pcie_block_i_n_795,pcie_block_i_n_796,pcie_block_i_n_797,pcie_block_i_n_798,pcie_block_i_n_799,pcie_block_i_n_800,pcie_block_i_n_801,pcie_block_i_n_802,pcie_block_i_n_803,pcie_block_i_n_804,pcie_block_i_n_805,pcie_block_i_n_806,pcie_block_i_n_807,pcie_block_i_n_808,pcie_block_i_n_809,pcie_block_i_n_810,pcie_block_i_n_811,pcie_block_i_n_812,pcie_block_i_n_813,pcie_block_i_n_814,pcie_block_i_n_815,pcie_block_i_n_816,pcie_block_i_n_817,pcie_block_i_n_818,pcie_block_i_n_819,pcie_block_i_n_820,pcie_block_i_n_821,pcie_block_i_n_822,pcie_block_i_n_823,pcie_block_i_n_824,pcie_block_i_n_825,pcie_block_i_n_826,pcie_block_i_n_827,pcie_block_i_n_828,pcie_block_i_n_829,pcie_block_i_n_830,pcie_block_i_n_831}),
        .DBGVECC({pcie_block_i_n_172,pcie_block_i_n_173,pcie_block_i_n_174,pcie_block_i_n_175,pcie_block_i_n_176,pcie_block_i_n_177,pcie_block_i_n_178,pcie_block_i_n_179,pcie_block_i_n_180,pcie_block_i_n_181,pcie_block_i_n_182,pcie_block_i_n_183}),
        .DLRSTN(1'b1),
        .DRPADDR(pcie_drp_addr),
        .DRPCLK(pcie_drp_clk),
        .DRPDI(pcie_drp_di),
        .DRPDO(pcie_drp_do),
        .DRPEN(pcie_drp_en),
        .DRPRDY(pcie_drp_rdy),
        .DRPWE(pcie_drp_we),
        .FUNCLVLRSTN(1'b1),
        .LL2BADDLLPERR(pcie_block_i_n_98),
        .LL2BADTLPERR(pcie_block_i_n_99),
        .LL2LINKSTATUS({pcie_block_i_n_687,pcie_block_i_n_688,pcie_block_i_n_689,pcie_block_i_n_690,pcie_block_i_n_691}),
        .LL2PROTOCOLERR(pcie_block_i_n_100),
        .LL2RECEIVERERR(pcie_block_i_n_101),
        .LL2REPLAYROERR(pcie_block_i_n_102),
        .LL2REPLAYTOERR(pcie_block_i_n_103),
        .LL2SENDASREQL1(1'b0),
        .LL2SENDENTERL1(1'b0),
        .LL2SENDENTERL23(1'b0),
        .LL2SENDPMACK(1'b0),
        .LL2SUSPENDNOW(1'b0),
        .LL2SUSPENDOK(pcie_block_i_n_104),
        .LL2TFCINIT1SEQ(pcie_block_i_n_105),
        .LL2TFCINIT2SEQ(pcie_block_i_n_106),
        .LL2TLPRCV(1'b0),
        .LL2TXIDLE(pcie_block_i_n_107),
        .LNKCLKEN(pcie_block_i_n_108),
        .MIMRXRADDR(mim_rx_raddr),
        .MIMRXRDATA({pcie_bram_top_n_69,pcie_bram_top_n_70,pcie_bram_top_n_71,pcie_bram_top_n_72,pcie_bram_top_n_73,pcie_bram_top_n_74,pcie_bram_top_n_75,pcie_bram_top_n_76,pcie_bram_top_n_77,pcie_bram_top_n_78,pcie_bram_top_n_79,pcie_bram_top_n_80,pcie_bram_top_n_81,pcie_bram_top_n_82,pcie_bram_top_n_83,pcie_bram_top_n_84,pcie_bram_top_n_85,pcie_bram_top_n_86,pcie_bram_top_n_87,pcie_bram_top_n_88,pcie_bram_top_n_89,pcie_bram_top_n_90,pcie_bram_top_n_91,pcie_bram_top_n_92,pcie_bram_top_n_93,pcie_bram_top_n_94,pcie_bram_top_n_95,pcie_bram_top_n_96,pcie_bram_top_n_97,pcie_bram_top_n_98,pcie_bram_top_n_99,pcie_bram_top_n_100,pcie_bram_top_n_101,pcie_bram_top_n_102,pcie_bram_top_n_103,pcie_bram_top_n_104,pcie_bram_top_n_105,pcie_bram_top_n_106,pcie_bram_top_n_107,pcie_bram_top_n_108,pcie_bram_top_n_109,pcie_bram_top_n_110,pcie_bram_top_n_111,pcie_bram_top_n_112,pcie_bram_top_n_113,pcie_bram_top_n_114,pcie_bram_top_n_115,pcie_bram_top_n_116,pcie_bram_top_n_117,pcie_bram_top_n_118,pcie_bram_top_n_119,pcie_bram_top_n_120,pcie_bram_top_n_121,pcie_bram_top_n_122,pcie_bram_top_n_123,pcie_bram_top_n_124,pcie_bram_top_n_125,pcie_bram_top_n_126,pcie_bram_top_n_127,pcie_bram_top_n_128,pcie_bram_top_n_129,pcie_bram_top_n_130,pcie_bram_top_n_131,pcie_bram_top_n_132,pcie_bram_top_n_133,pcie_bram_top_n_134,pcie_bram_top_n_135,pcie_bram_top_n_136}),
        .MIMRXREN(mim_rx_ren),
        .MIMRXWADDR(mim_rx_waddr),
        .MIMRXWDATA(mim_rx_wdata),
        .MIMRXWEN(mim_rx_wen),
        .MIMTXRADDR(mim_tx_raddr),
        .MIMTXRDATA({pcie_bram_top_n_0,pcie_bram_top_n_1,pcie_bram_top_n_2,pcie_bram_top_n_3,pcie_bram_top_n_4,pcie_bram_top_n_5,pcie_bram_top_n_6,pcie_bram_top_n_7,pcie_bram_top_n_8,pcie_bram_top_n_9,pcie_bram_top_n_10,pcie_bram_top_n_11,pcie_bram_top_n_12,pcie_bram_top_n_13,pcie_bram_top_n_14,pcie_bram_top_n_15,pcie_bram_top_n_16,pcie_bram_top_n_17,pcie_bram_top_n_18,pcie_bram_top_n_19,pcie_bram_top_n_20,pcie_bram_top_n_21,pcie_bram_top_n_22,pcie_bram_top_n_23,pcie_bram_top_n_24,pcie_bram_top_n_25,pcie_bram_top_n_26,pcie_bram_top_n_27,pcie_bram_top_n_28,pcie_bram_top_n_29,pcie_bram_top_n_30,pcie_bram_top_n_31,pcie_bram_top_n_32,pcie_bram_top_n_33,pcie_bram_top_n_34,pcie_bram_top_n_35,pcie_bram_top_n_36,pcie_bram_top_n_37,pcie_bram_top_n_38,pcie_bram_top_n_39,pcie_bram_top_n_40,pcie_bram_top_n_41,pcie_bram_top_n_42,pcie_bram_top_n_43,pcie_bram_top_n_44,pcie_bram_top_n_45,pcie_bram_top_n_46,pcie_bram_top_n_47,pcie_bram_top_n_48,pcie_bram_top_n_49,pcie_bram_top_n_50,pcie_bram_top_n_51,pcie_bram_top_n_52,pcie_bram_top_n_53,pcie_bram_top_n_54,pcie_bram_top_n_55,pcie_bram_top_n_56,pcie_bram_top_n_57,pcie_bram_top_n_58,pcie_bram_top_n_59,pcie_bram_top_n_60,pcie_bram_top_n_61,pcie_bram_top_n_62,pcie_bram_top_n_63,pcie_bram_top_n_64,pcie_bram_top_n_65,pcie_bram_top_n_66,pcie_bram_top_n_67,pcie_bram_top_n_68}),
        .MIMTXREN(mim_tx_ren),
        .MIMTXWADDR(mim_tx_waddr),
        .MIMTXWDATA(mim_tx_wdata),
        .MIMTXWEN(mim_tx_wen),
        .PIPECLK(CLK),
        .PIPERX0CHANISALIGNED(pipe_rx0_chanisaligned),
        .PIPERX0CHARISK(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] ),
        .PIPERX0DATA(Q),
        .PIPERX0ELECIDLE(pipe_rx0_elec_idle),
        .PIPERX0PHYSTATUS(pipe_rx0_phy_status),
        .PIPERX0POLARITY(pipe_rx0_polarity),
        .PIPERX0STATUS(\pipe_stages_1.pipe_rx_status_q_reg[2] ),
        .PIPERX0VALID(pipe_rx0_valid),
        .PIPERX1CHANISALIGNED(pipe_rx1_chanisaligned),
        .PIPERX1CHARISK(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 ),
        .PIPERX1DATA(\pipe_stages_1.pipe_rx_data_q_reg[15] ),
        .PIPERX1ELECIDLE(pipe_rx1_elec_idle),
        .PIPERX1PHYSTATUS(pipe_rx1_phy_status),
        .PIPERX1POLARITY(pipe_rx1_polarity),
        .PIPERX1STATUS(\pipe_stages_1.pipe_rx_status_q_reg[2]_0 ),
        .PIPERX1VALID(pipe_rx1_valid),
        .PIPERX2CHANISALIGNED(pipe_rx2_chanisaligned),
        .PIPERX2CHARISK(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 ),
        .PIPERX2DATA(\pipe_stages_1.pipe_rx_data_q_reg[15]_0 ),
        .PIPERX2ELECIDLE(pipe_rx2_elec_idle),
        .PIPERX2PHYSTATUS(pipe_rx2_phy_status),
        .PIPERX2POLARITY(pipe_rx2_polarity),
        .PIPERX2STATUS(\pipe_stages_1.pipe_rx_status_q_reg[2]_1 ),
        .PIPERX2VALID(pipe_rx2_valid),
        .PIPERX3CHANISALIGNED(pipe_rx3_chanisaligned),
        .PIPERX3CHARISK(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 ),
        .PIPERX3DATA(\pipe_stages_1.pipe_rx_data_q_reg[15]_1 ),
        .PIPERX3ELECIDLE(pipe_rx3_elec_idle),
        .PIPERX3PHYSTATUS(pipe_rx3_phy_status),
        .PIPERX3POLARITY(pipe_rx3_polarity),
        .PIPERX3STATUS(\pipe_stages_1.pipe_rx_status_q_reg[2]_2 ),
        .PIPERX3VALID(pipe_rx3_valid),
        .PIPERX4CHANISALIGNED(pipe_rx4_chanisaligned),
        .PIPERX4CHARISK(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 ),
        .PIPERX4DATA(\pipe_stages_1.pipe_rx_data_q_reg[15]_2 ),
        .PIPERX4ELECIDLE(pipe_rx4_elec_idle),
        .PIPERX4PHYSTATUS(pipe_rx4_phy_status),
        .PIPERX4POLARITY(pipe_rx4_polarity),
        .PIPERX4STATUS(\pipe_stages_1.pipe_rx_status_q_reg[2]_3 ),
        .PIPERX4VALID(pipe_rx4_valid),
        .PIPERX5CHANISALIGNED(pipe_rx5_chanisaligned),
        .PIPERX5CHARISK(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 ),
        .PIPERX5DATA(\pipe_stages_1.pipe_rx_data_q_reg[15]_3 ),
        .PIPERX5ELECIDLE(pipe_rx5_elec_idle),
        .PIPERX5PHYSTATUS(pipe_rx5_phy_status),
        .PIPERX5POLARITY(pipe_rx5_polarity),
        .PIPERX5STATUS(\pipe_stages_1.pipe_rx_status_q_reg[2]_4 ),
        .PIPERX5VALID(pipe_rx5_valid),
        .PIPERX6CHANISALIGNED(pipe_rx6_chanisaligned),
        .PIPERX6CHARISK(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5 ),
        .PIPERX6DATA(\pipe_stages_1.pipe_rx_data_q_reg[15]_4 ),
        .PIPERX6ELECIDLE(pipe_rx6_elec_idle),
        .PIPERX6PHYSTATUS(pipe_rx6_phy_status),
        .PIPERX6POLARITY(pipe_rx6_polarity),
        .PIPERX6STATUS(\pipe_stages_1.pipe_rx_status_q_reg[2]_5 ),
        .PIPERX6VALID(pipe_rx6_valid),
        .PIPERX7CHANISALIGNED(pipe_rx7_chanisaligned),
        .PIPERX7CHARISK(\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_6 ),
        .PIPERX7DATA(\pipe_stages_1.pipe_rx_data_q_reg[15]_5 ),
        .PIPERX7ELECIDLE(pipe_rx7_elec_idle),
        .PIPERX7PHYSTATUS(pipe_rx7_phy_status),
        .PIPERX7POLARITY(pipe_rx7_polarity),
        .PIPERX7STATUS(\pipe_stages_1.pipe_rx_status_q_reg[2]_6 ),
        .PIPERX7VALID(pipe_rx7_valid),
        .PIPETX0CHARISK(pipe_tx0_char_is_k),
        .PIPETX0COMPLIANCE(pipe_tx0_compliance),
        .PIPETX0DATA(pipe_tx0_data),
        .PIPETX0ELECIDLE(pipe_tx0_elec_idle),
        .PIPETX0POWERDOWN(pipe_tx0_powerdown),
        .PIPETX1CHARISK(pipe_tx1_char_is_k),
        .PIPETX1COMPLIANCE(pipe_tx1_compliance),
        .PIPETX1DATA(pipe_tx1_data),
        .PIPETX1ELECIDLE(pipe_tx1_elec_idle),
        .PIPETX1POWERDOWN(pipe_tx1_powerdown),
        .PIPETX2CHARISK(pipe_tx2_char_is_k),
        .PIPETX2COMPLIANCE(pipe_tx2_compliance),
        .PIPETX2DATA(pipe_tx2_data),
        .PIPETX2ELECIDLE(pipe_tx2_elec_idle),
        .PIPETX2POWERDOWN(pipe_tx2_powerdown),
        .PIPETX3CHARISK(pipe_tx3_char_is_k),
        .PIPETX3COMPLIANCE(pipe_tx3_compliance),
        .PIPETX3DATA(pipe_tx3_data),
        .PIPETX3ELECIDLE(pipe_tx3_elec_idle),
        .PIPETX3POWERDOWN(pipe_tx3_powerdown),
        .PIPETX4CHARISK(pipe_tx4_char_is_k),
        .PIPETX4COMPLIANCE(pipe_tx4_compliance),
        .PIPETX4DATA(pipe_tx4_data),
        .PIPETX4ELECIDLE(pipe_tx4_elec_idle),
        .PIPETX4POWERDOWN(pipe_tx4_powerdown),
        .PIPETX5CHARISK(pipe_tx5_char_is_k),
        .PIPETX5COMPLIANCE(pipe_tx5_compliance),
        .PIPETX5DATA(pipe_tx5_data),
        .PIPETX5ELECIDLE(pipe_tx5_elec_idle),
        .PIPETX5POWERDOWN(pipe_tx5_powerdown),
        .PIPETX6CHARISK(pipe_tx6_char_is_k),
        .PIPETX6COMPLIANCE(pipe_tx6_compliance),
        .PIPETX6DATA(pipe_tx6_data),
        .PIPETX6ELECIDLE(pipe_tx6_elec_idle),
        .PIPETX6POWERDOWN(pipe_tx6_powerdown),
        .PIPETX7CHARISK(pipe_tx7_char_is_k),
        .PIPETX7COMPLIANCE(pipe_tx7_compliance),
        .PIPETX7DATA(pipe_tx7_data),
        .PIPETX7ELECIDLE(pipe_tx7_elec_idle),
        .PIPETX7POWERDOWN(pipe_tx7_powerdown),
        .PIPETXDEEMPH(pipe_tx_deemph),
        .PIPETXMARGIN(pipe_tx_margin),
        .PIPETXRATE(pipe_tx_rate),
        .PIPETXRCVRDET(pipe_tx_rcvr_det),
        .PIPETXRESET(pcie_block_i_n_140),
        .PL2DIRECTEDLSTATE({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PL2L0REQ(pcie_block_i_n_141),
        .PL2LINKUP(pcie_block_i_n_142),
        .PL2RECEIVERERR(pcie_block_i_n_143),
        .PL2RECOVERY(pcie_block_i_n_144),
        .PL2RXELECIDLE(pcie_block_i_n_145),
        .PL2RXPMSTATE({pcie_block_i_n_610,pcie_block_i_n_611}),
        .PL2SUSPENDOK(pcie_block_i_n_146),
        .PLDBGMODE({1'b0,1'b0,1'b0}),
        .PLDBGVEC({pcie_block_i_n_184,pcie_block_i_n_185,pcie_block_i_n_186,pcie_block_i_n_187,pcie_block_i_n_188,pcie_block_i_n_189,pcie_block_i_n_190,pcie_block_i_n_191,pcie_block_i_n_192,pcie_block_i_n_193,pcie_block_i_n_194,pcie_block_i_n_195}),
        .PLDIRECTEDCHANGEDONE(pl_directed_change_done),
        .PLDIRECTEDLINKAUTON(pl_directed_link_auton),
        .PLDIRECTEDLINKCHANGE(pl_directed_link_change),
        .PLDIRECTEDLINKSPEED(pl_directed_link_speed),
        .PLDIRECTEDLINKWIDTH(pl_directed_link_width),
        .PLDIRECTEDLTSSMNEW({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .PLDIRECTEDLTSSMNEWVLD(1'b0),
        .PLDIRECTEDLTSSMSTALL(1'b0),
        .PLDOWNSTREAMDEEMPHSOURCE(pl_downstream_deemph_source),
        .PLINITIALLINKWIDTH(pl_initial_link_width),
        .PLLANEREVERSALMODE(pl_lane_reversal_mode),
        .PLLINKGEN2CAP(pl_link_gen2_cap),
        .PLLINKPARTNERGEN2SUPPORTED(pl_link_partner_gen2_supported),
        .PLLINKUPCFGCAP(pl_link_upcfg_cap),
        .PLLTSSMSTATE(pl_ltssm_state),
        .PLPHYLNKUPN(pl_phy_lnk_up_n),
        .PLRECEIVEDHOTRST(pl_received_hot_rst),
        .PLRSTN(1'b1),
        .PLRXPMSTATE(pl_rx_pm_state),
        .PLSELLNKRATE(pl_sel_lnk_rate),
        .PLSELLNKWIDTH(pl_sel_lnk_width),
        .PLTRANSMITHOTRST(pl_transmit_hot_rst),
        .PLTXPMSTATE(pl_tx_pm_state),
        .PLUPSTREAMPREFERDEEMPH(pl_upstream_prefer_deemph),
        .RECEIVEDFUNCLVLRSTN(received_func_lvl_rst_n),
        .SYSRSTN(sys_rst_n),
        .TL2ASPMSUSPENDCREDITCHECK(1'b0),
        .TL2ASPMSUSPENDCREDITCHECKOK(pcie_block_i_n_155),
        .TL2ASPMSUSPENDREQ(pcie_block_i_n_156),
        .TL2ERRFCPE(pcie_block_i_n_157),
        .TL2ERRHDR({pcie_block_i_n_832,pcie_block_i_n_833,pcie_block_i_n_834,pcie_block_i_n_835,pcie_block_i_n_836,pcie_block_i_n_837,pcie_block_i_n_838,pcie_block_i_n_839,pcie_block_i_n_840,pcie_block_i_n_841,pcie_block_i_n_842,pcie_block_i_n_843,pcie_block_i_n_844,pcie_block_i_n_845,pcie_block_i_n_846,pcie_block_i_n_847,pcie_block_i_n_848,pcie_block_i_n_849,pcie_block_i_n_850,pcie_block_i_n_851,pcie_block_i_n_852,pcie_block_i_n_853,pcie_block_i_n_854,pcie_block_i_n_855,pcie_block_i_n_856,pcie_block_i_n_857,pcie_block_i_n_858,pcie_block_i_n_859,pcie_block_i_n_860,pcie_block_i_n_861,pcie_block_i_n_862,pcie_block_i_n_863,pcie_block_i_n_864,pcie_block_i_n_865,pcie_block_i_n_866,pcie_block_i_n_867,pcie_block_i_n_868,pcie_block_i_n_869,pcie_block_i_n_870,pcie_block_i_n_871,pcie_block_i_n_872,pcie_block_i_n_873,pcie_block_i_n_874,pcie_block_i_n_875,pcie_block_i_n_876,pcie_block_i_n_877,pcie_block_i_n_878,pcie_block_i_n_879,pcie_block_i_n_880,pcie_block_i_n_881,pcie_block_i_n_882,pcie_block_i_n_883,pcie_block_i_n_884,pcie_block_i_n_885,pcie_block_i_n_886,pcie_block_i_n_887,pcie_block_i_n_888,pcie_block_i_n_889,pcie_block_i_n_890,pcie_block_i_n_891,pcie_block_i_n_892,pcie_block_i_n_893,pcie_block_i_n_894,pcie_block_i_n_895}),
        .TL2ERRMALFORMED(pcie_block_i_n_158),
        .TL2ERRRXOVERFLOW(pcie_block_i_n_159),
        .TL2PPMSUSPENDOK(pcie_block_i_n_160),
        .TL2PPMSUSPENDREQ(1'b0),
        .TLRSTN(1'b1),
        .TRNFCCPLD(fc_cpld),
        .TRNFCCPLH(fc_cplh),
        .TRNFCNPD(fc_npd),
        .TRNFCNPH(fc_nph),
        .TRNFCPD(fc_pd),
        .TRNFCPH(fc_ph),
        .TRNFCSEL(fc_sel),
        .TRNLNKUP(trn_lnk_up),
        .TRNRBARHIT({pcie_block_i_n_1143,trn_rbar_hit}),
        .TRNRD({NLW_pcie_block_i_TRNRD_UNCONNECTED[127:64],trn_rd}),
        .TRNRDLLPDATA({pcie_block_i_n_896,pcie_block_i_n_897,pcie_block_i_n_898,pcie_block_i_n_899,pcie_block_i_n_900,pcie_block_i_n_901,pcie_block_i_n_902,pcie_block_i_n_903,pcie_block_i_n_904,pcie_block_i_n_905,pcie_block_i_n_906,pcie_block_i_n_907,pcie_block_i_n_908,pcie_block_i_n_909,pcie_block_i_n_910,pcie_block_i_n_911,pcie_block_i_n_912,pcie_block_i_n_913,pcie_block_i_n_914,pcie_block_i_n_915,pcie_block_i_n_916,pcie_block_i_n_917,pcie_block_i_n_918,pcie_block_i_n_919,pcie_block_i_n_920,pcie_block_i_n_921,pcie_block_i_n_922,pcie_block_i_n_923,pcie_block_i_n_924,pcie_block_i_n_925,pcie_block_i_n_926,pcie_block_i_n_927,pcie_block_i_n_928,pcie_block_i_n_929,pcie_block_i_n_930,pcie_block_i_n_931,pcie_block_i_n_932,pcie_block_i_n_933,pcie_block_i_n_934,pcie_block_i_n_935,pcie_block_i_n_936,pcie_block_i_n_937,pcie_block_i_n_938,pcie_block_i_n_939,pcie_block_i_n_940,pcie_block_i_n_941,pcie_block_i_n_942,pcie_block_i_n_943,pcie_block_i_n_944,pcie_block_i_n_945,pcie_block_i_n_946,pcie_block_i_n_947,pcie_block_i_n_948,pcie_block_i_n_949,pcie_block_i_n_950,pcie_block_i_n_951,pcie_block_i_n_952,pcie_block_i_n_953,pcie_block_i_n_954,pcie_block_i_n_955,pcie_block_i_n_956,pcie_block_i_n_957,pcie_block_i_n_958,pcie_block_i_n_959}),
        .TRNRDLLPSRCRDY({pcie_block_i_n_618,pcie_block_i_n_619}),
        .TRNRDSTRDY(trn_rdst_rdy),
        .TRNRECRCERR(trn_recrc_err),
        .TRNREOF(trn_reof),
        .TRNRERRFWD(trn_rerrfwd),
        .TRNRFCPRET(1'b1),
        .TRNRNPOK(rx_np_ok),
        .TRNRNPREQ(rx_np_req),
        .TRNRREM({NLW_pcie_block_i_TRNRREM_UNCONNECTED[1],trn_rrem}),
        .TRNRSOF(trn_rsof),
        .TRNRSRCDSC(trn_rsrc_dsc),
        .TRNRSRCRDY(trn_rsrc_rdy),
        .TRNTBUFAV(trn_tbuf_av),
        .TRNTCFGGNT(trn_tcfg_gnt),
        .TRNTCFGREQ(trn_tcfg_req),
        .TRNTD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,trn_td}),
        .TRNTDLLPDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TRNTDLLPDSTRDY(pcie_block_i_n_169),
        .TRNTDLLPSRCRDY(1'b0),
        .TRNTDSTRDY({NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED[3:1],trn_tdst_rdy}),
        .TRNTECRCGEN(\xhdl12.reg_tuser_reg[3] [0]),
        .TRNTEOF(trn_teof),
        .TRNTERRDROP(tx_err_drop),
        .TRNTERRFWD(\xhdl12.reg_tuser_reg[3] [1]),
        .TRNTREM({1'b0,trn_trem}),
        .TRNTSOF(trn_tsof),
        .TRNTSRCDSC(\xhdl12.reg_tuser_reg[3] [3]),
        .TRNTSRCRDY(trn_tsrc_rdy),
        .TRNTSTR(\xhdl12.reg_tuser_reg[3] [2]),
        .USERCLK(user_clk),
        .USERCLK2(user_clk),
        .USERRSTN(user_rst_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_1
       (.I0(cfg_err_atomic_egress_blocked),
        .O(cfg_err_atomic_egress_blocked_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_10
       (.I0(cfg_err_malformed),
        .O(cfg_err_malformed_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_11
       (.I0(cfg_err_mc_blocked),
        .O(cfg_err_mc_blocked_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_12
       (.I0(cfg_err_norecovery),
        .O(cfg_err_norecovery_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_13
       (.I0(cfg_err_poisoned),
        .O(cfg_err_poisoned_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_14
       (.I0(cfg_err_posted),
        .O(cfg_err_posted_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_15
       (.I0(cfg_err_ur),
        .O(cfg_err_ur_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_16
       (.I0(cfg_interrupt_assert),
        .O(cfg_interrupt_assert_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_17
       (.I0(cfg_interrupt),
        .O(cfg_interrupt_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_18
       (.I0(cfg_interrupt_stat),
        .O(cfg_interrupt_stat_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_19
       (.I0(cfg_mgmt_rd_en),
        .O(cfg_mgmt_rd_en_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_2
       (.I0(cfg_err_cor),
        .O(cfg_err_cor_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_20
       (.I0(cfg_mgmt_wr_en),
        .O(cfg_mgmt_wr_en_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_21
       (.I0(cfg_mgmt_wr_readonly),
        .O(cfg_mgmt_wr_readonly_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_22
       (.I0(cfg_mgmt_wr_rw1c_as_rw),
        .O(cfg_mgmt_wr_rw1c_as_rw_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_23
       (.I0(cfg_pm_force_state_en),
        .O(cfg_pm_force_state_en_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_24
       (.I0(cfg_pm_halt_aspm_l0s),
        .O(cfg_pm_halt_aspm_l0s_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_25
       (.I0(cfg_pm_halt_aspm_l1),
        .O(cfg_pm_halt_aspm_l1_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_27
       (.I0(cfg_pm_wake),
        .O(cfg_pm_wake_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_28
       (.I0(cfg_trn_pending),
        .O(cfg_trn_pending_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_3
       (.I0(cfg_err_cpl_abort),
        .O(cfg_err_cpl_abort_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_4
       (.I0(cfg_err_cpl_timeout),
        .O(cfg_err_cpl_timeout_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_5
       (.I0(cfg_err_cpl_unexpect),
        .O(cfg_err_cpl_unexpect_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_6
       (.I0(cfg_err_ecrc),
        .O(cfg_err_ecrc_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_7
       (.I0(cfg_err_internal_cor),
        .O(cfg_err_internal_cor_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_8
       (.I0(cfg_err_internal_uncor),
        .O(cfg_err_internal_uncor_n));
  LUT1 #(
    .INIT(2'h1)) 
    pcie_block_i_i_9
       (.I0(cfg_err_locked),
        .O(cfg_err_locked_n));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_top_7x pcie_bram_top
       (.MIMRXRADDR(mim_rx_raddr[10:0]),
        .MIMRXWADDR(mim_rx_waddr[10:0]),
        .MIMTXRADDR(mim_tx_raddr[10:0]),
        .MIMTXWADDR(mim_tx_waddr[10:0]),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (mim_rx_wdata),
        .\ramb_bl.ramb36_dp_bl.ram36_bl ({pcie_bram_top_n_69,pcie_bram_top_n_70,pcie_bram_top_n_71,pcie_bram_top_n_72,pcie_bram_top_n_73,pcie_bram_top_n_74,pcie_bram_top_n_75,pcie_bram_top_n_76,pcie_bram_top_n_77,pcie_bram_top_n_78,pcie_bram_top_n_79,pcie_bram_top_n_80,pcie_bram_top_n_81,pcie_bram_top_n_82,pcie_bram_top_n_83,pcie_bram_top_n_84,pcie_bram_top_n_85,pcie_bram_top_n_86,pcie_bram_top_n_87,pcie_bram_top_n_88,pcie_bram_top_n_89,pcie_bram_top_n_90,pcie_bram_top_n_91,pcie_bram_top_n_92,pcie_bram_top_n_93,pcie_bram_top_n_94,pcie_bram_top_n_95,pcie_bram_top_n_96,pcie_bram_top_n_97,pcie_bram_top_n_98,pcie_bram_top_n_99,pcie_bram_top_n_100,pcie_bram_top_n_101,pcie_bram_top_n_102,pcie_bram_top_n_103,pcie_bram_top_n_104,pcie_bram_top_n_105,pcie_bram_top_n_106,pcie_bram_top_n_107,pcie_bram_top_n_108,pcie_bram_top_n_109,pcie_bram_top_n_110,pcie_bram_top_n_111,pcie_bram_top_n_112,pcie_bram_top_n_113,pcie_bram_top_n_114,pcie_bram_top_n_115,pcie_bram_top_n_116,pcie_bram_top_n_117,pcie_bram_top_n_118,pcie_bram_top_n_119,pcie_bram_top_n_120,pcie_bram_top_n_121,pcie_bram_top_n_122,pcie_bram_top_n_123,pcie_bram_top_n_124,pcie_bram_top_n_125,pcie_bram_top_n_126,pcie_bram_top_n_127,pcie_bram_top_n_128,pcie_bram_top_n_129,pcie_bram_top_n_130,pcie_bram_top_n_131,pcie_bram_top_n_132,pcie_bram_top_n_133,pcie_bram_top_n_134,pcie_bram_top_n_135,pcie_bram_top_n_136}),
        .rdata({pcie_bram_top_n_0,pcie_bram_top_n_1,pcie_bram_top_n_2,pcie_bram_top_n_3,pcie_bram_top_n_4,pcie_bram_top_n_5,pcie_bram_top_n_6,pcie_bram_top_n_7,pcie_bram_top_n_8,pcie_bram_top_n_9,pcie_bram_top_n_10,pcie_bram_top_n_11,pcie_bram_top_n_12,pcie_bram_top_n_13,pcie_bram_top_n_14,pcie_bram_top_n_15,pcie_bram_top_n_16,pcie_bram_top_n_17,pcie_bram_top_n_18,pcie_bram_top_n_19,pcie_bram_top_n_20,pcie_bram_top_n_21,pcie_bram_top_n_22,pcie_bram_top_n_23,pcie_bram_top_n_24,pcie_bram_top_n_25,pcie_bram_top_n_26,pcie_bram_top_n_27,pcie_bram_top_n_28,pcie_bram_top_n_29,pcie_bram_top_n_30,pcie_bram_top_n_31,pcie_bram_top_n_32,pcie_bram_top_n_33,pcie_bram_top_n_34,pcie_bram_top_n_35,pcie_bram_top_n_36,pcie_bram_top_n_37,pcie_bram_top_n_38,pcie_bram_top_n_39,pcie_bram_top_n_40,pcie_bram_top_n_41,pcie_bram_top_n_42,pcie_bram_top_n_43,pcie_bram_top_n_44,pcie_bram_top_n_45,pcie_bram_top_n_46,pcie_bram_top_n_47,pcie_bram_top_n_48,pcie_bram_top_n_49,pcie_bram_top_n_50,pcie_bram_top_n_51,pcie_bram_top_n_52,pcie_bram_top_n_53,pcie_bram_top_n_54,pcie_bram_top_n_55,pcie_bram_top_n_56,pcie_bram_top_n_57,pcie_bram_top_n_58,pcie_bram_top_n_59,pcie_bram_top_n_60,pcie_bram_top_n_61,pcie_bram_top_n_62,pcie_bram_top_n_63,pcie_bram_top_n_64,pcie_bram_top_n_65,pcie_bram_top_n_66,pcie_bram_top_n_67,pcie_bram_top_n_68}),
        .user_clk(user_clk),
        .wdata(mim_tx_wdata));
  LUT1 #(
    .INIT(2'h1)) 
    pl_phy_lnk_up_q_i_1
       (.I0(pl_phy_lnk_up_n),
        .O(pl_phy_lnk_up_q_reg));
  LUT4 #(
    .INIT(16'hAAAB)) 
    ppm_L1_thrtl_i_4
       (.I0(user_reset_out_reg),
        .I1(cfg_pcie_link_state[1]),
        .I2(cfg_pcie_link_state[2]),
        .I3(cfg_pcie_link_state[0]),
        .O(ppm_L1_thrtl_reg));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    reg_dsc_detect_i_2
       (.I0(trn_rdst_rdy),
        .I1(trn_reof),
        .I2(trn_rsof),
        .O(reg_dsc_detect_reg));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    tbuf_av_gap_thrtl_i_2
       (.I0(tbuf_av_gap_thrtl_i_6_n_0),
        .I1(trn_tbuf_av[0]),
        .I2(\tbuf_av_d_reg[4] ),
        .I3(trn_tbuf_av[3]),
        .I4(trn_tbuf_av[2]),
        .I5(trn_tbuf_av[4]),
        .O(tbuf_av_gap_thrtl_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF8)) 
    tbuf_av_gap_thrtl_i_5
       (.I0(trn_tbuf_av[0]),
        .I1(trn_tbuf_av[1]),
        .I2(tbuf_av_gap_thrtl_i_8_n_0),
        .I3(trn_tbuf_av[3]),
        .I4(trn_tbuf_av[2]),
        .I5(trn_tbuf_av[4]),
        .O(tbuf_av_gap_thrtl_reg));
  LUT2 #(
    .INIT(4'h2)) 
    tbuf_av_gap_thrtl_i_6
       (.I0(trn_tbuf_av[1]),
        .I1(trn_tbuf_av[5]),
        .O(tbuf_av_gap_thrtl_i_6_n_0));
  LUT4 #(
    .INIT(16'hBFFF)) 
    tbuf_av_gap_thrtl_i_8
       (.I0(trn_tbuf_av[5]),
        .I1(tready_thrtl_xhdl1_reg_1),
        .I2(s_axis_tx_tvalid),
        .I3(s_axis_tx_tlast),
        .O(tbuf_av_gap_thrtl_i_8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    tbuf_av_min_thrtl_i_1
       (.I0(trn_tbuf_av[5]),
        .I1(trn_tbuf_av[4]),
        .I2(trn_tbuf_av[3]),
        .I3(trn_tbuf_av[1]),
        .I4(trn_tbuf_av[2]),
        .O(tbuf_av_min_trig));
  LUT3 #(
    .INIT(8'hEF)) 
    tready_thrtl_xhdl1_i_5
       (.I0(tbuf_av_gap_thrtl_reg_0),
        .I1(\tcfg_req_cnt_reg[1] ),
        .I2(tbuf_av_gap_thrtl_reg),
        .O(tready_thrtl_xhdl1_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    tready_thrtl_xhdl1_i_8
       (.I0(trn_tbuf_av[2]),
        .I1(trn_tbuf_av[1]),
        .I2(trn_tbuf_av[3]),
        .I3(trn_tbuf_av[4]),
        .I4(trn_tbuf_av[5]),
        .O(tready_thrtl_xhdl1_reg));
  LUT6 #(
    .INIT(64'h0010FFDF00100010)) 
    trn_in_packet_i_1
       (.I0(user_reset_out_reg),
        .I1(trn_in_packet_i_2_n_0),
        .I2(trn_rsrc_rdy),
        .I3(trn_in_packet_i_3__0_n_0),
        .I4(trn_in_packet_i_4_n_0),
        .I5(trn_in_packet_reg_0),
        .O(trn_in_packet_reg));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    trn_in_packet_i_2
       (.I0(trn_rsof),
        .I1(trn_reof),
        .I2(trn_rdst_rdy),
        .O(trn_in_packet_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT3 #(
    .INIT(8'h45)) 
    trn_in_packet_i_3__0
       (.I0(trn_in_packet_reg_0),
        .I1(trn_rsrc_dsc),
        .I2(trn_rsof),
        .O(trn_in_packet_i_3__0_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF4000)) 
    trn_in_packet_i_4
       (.I0(trn_rsof),
        .I1(trn_rsrc_rdy),
        .I2(trn_reof),
        .I3(trn_rdst_rdy),
        .I4(trn_rsrc_dsc),
        .I5(user_reset_out_reg),
        .O(trn_in_packet_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT4 #(
    .INIT(16'hAA08)) 
    trn_rsrc_rdy_prev_i_1
       (.I0(trn_rsrc_rdy),
        .I1(trn_rsof),
        .I2(trn_rsrc_dsc),
        .I3(trn_in_packet_reg_0),
        .O(rsrc_rdy_filtered10_out));
  LUT3 #(
    .INIT(8'h2A)) 
    user_reset_int_i_1
       (.I0(bridge_reset_int),
        .I1(pl_phy_lnk_up),
        .I2(user_rst_n),
        .O(user_reset_int_reg));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_bram_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x
   (rdata,
    mim_tx_wen,
    user_clk,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input mim_tx_wen;
  input user_clk;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [17:0]rdata;
  wire user_clk;
  wire [17:0]wdata;

  PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_13 \use_tdp.ramb36 
       (.MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata),
        .user_clk(user_clk),
        .wdata(wdata));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_bram_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_10
   (rdata,
    mim_tx_wen,
    user_clk,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [14:0]rdata;
  input mim_tx_wen;
  input user_clk;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [14:0]wdata;

  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [14:0]rdata;
  wire user_clk;
  wire [14:0]wdata;

  PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO \use_tdp.ramb36 
       (.MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata),
        .user_clk(user_clk),
        .wdata(wdata));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_bram_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_14
   (\ramb_bl.ramb36_dp_bl.ram36_bl ,
    mim_rx_wen,
    user_clk,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg );
  output [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  input mim_rx_wen;
  input user_clk;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;

  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire user_clk;

  PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_21 \use_tdp.ramb36 
       (.MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl ),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_bram_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_15
   (\ramb_bl.ramb36_dp_bl.ram36_bl ,
    mim_rx_wen,
    user_clk,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg );
  output [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  input mim_rx_wen;
  input user_clk;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;

  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire user_clk;

  PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_20 \use_tdp.ramb36 
       (.MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl ),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_bram_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_16
   (\ramb_bl.ramb36_dp_bl.ram36_bl ,
    mim_rx_wen,
    user_clk,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg );
  output [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  input mim_rx_wen;
  input user_clk;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;

  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire user_clk;

  PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_19 \use_tdp.ramb36 
       (.MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl ),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_bram_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_17
   (\ramb_bl.ramb36_dp_bl.ram36_bl ,
    mim_rx_wen,
    user_clk,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg );
  output [13:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  input mim_rx_wen;
  input user_clk;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [13:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;

  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire [13:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [13:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire user_clk;

  PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_18 \use_tdp.ramb36 
       (.MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl ),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_bram_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_8
   (rdata,
    mim_tx_wen,
    user_clk,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input mim_tx_wen;
  input user_clk;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [17:0]rdata;
  wire user_clk;
  wire [17:0]wdata;

  PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_12 \use_tdp.ramb36 
       (.MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata),
        .user_clk(user_clk),
        .wdata(wdata));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_bram_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_9
   (rdata,
    mim_tx_wen,
    user_clk,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input mim_tx_wen;
  input user_clk;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [17:0]rdata;
  wire user_clk;
  wire [17:0]wdata;

  PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_11 \use_tdp.ramb36 
       (.MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata),
        .user_clk(user_clk),
        .wdata(wdata));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_bram_top_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_top_7x
   (rdata,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    mim_tx_wen,
    user_clk,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata,
    mim_rx_wen,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg );
  output [68:0]rdata;
  output [67:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  input mim_tx_wen;
  input user_clk;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [68:0]wdata;
  input mim_rx_wen;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [67:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;

  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [67:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [67:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [68:0]rdata;
  wire user_clk;
  wire [68:0]wdata;

  PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x pcie_brams_rx
       (.MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl ),
        .user_clk(user_clk));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x_7 pcie_brams_tx
       (.MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata),
        .user_clk(user_clk),
        .wdata(wdata));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_brams_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x
   (\ramb_bl.ramb36_dp_bl.ram36_bl ,
    mim_rx_wen,
    user_clk,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg );
  output [67:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  input mim_rx_wen;
  input user_clk;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [67:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;

  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire [67:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [67:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire user_clk;

  PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_14 \brams[0].ram 
       (.MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg [17:0]),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl [17:0]),
        .user_clk(user_clk));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_15 \brams[1].ram 
       (.MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg [35:18]),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl [35:18]),
        .user_clk(user_clk));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_16 \brams[2].ram 
       (.MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg [53:36]),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl [53:36]),
        .user_clk(user_clk));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_17 \brams[3].ram 
       (.MIMRXRADDR(MIMRXRADDR),
        .MIMRXWADDR(MIMRXWADDR),
        .mim_rx_ren(mim_rx_ren),
        .mim_rx_wen(mim_rx_wen),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (\pipe_stages_1.pipe_rx_chanisaligned_q_reg [67:54]),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl [67:54]),
        .user_clk(user_clk));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_brams_7x" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_brams_7x_7
   (rdata,
    mim_tx_wen,
    user_clk,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [68:0]rdata;
  input mim_tx_wen;
  input user_clk;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [68:0]wdata;

  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire [68:0]rdata;
  wire user_clk;
  wire [68:0]wdata;

  PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x \brams[0].ram 
       (.MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata[17:0]),
        .user_clk(user_clk),
        .wdata(wdata[17:0]));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_8 \brams[1].ram 
       (.MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata[35:18]),
        .user_clk(user_clk),
        .wdata(wdata[35:18]));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_9 \brams[2].ram 
       (.MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata[53:36]),
        .user_clk(user_clk),
        .wdata(wdata[53:36]));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_bram_7x_10 \brams[3].ram 
       (.MIMTXRADDR(MIMTXRADDR),
        .MIMTXWADDR(MIMTXWADDR),
        .mim_tx_ren(mim_tx_ren),
        .mim_tx_wen(mim_tx_wen),
        .rdata(rdata[68:54]),
        .user_clk(user_clk),
        .wdata(wdata[68:54]));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_pipe_lane" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane
   (pipe_rx0_valid_o,
    pipe_rx0_chanisaligned_o,
    pipe_rx0_phy_status_o,
    pipe_rx0_elec_idle_o,
    PIPE_RXPOLARITY,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_1 ,
    PIPE_TXDATAK,
    PIPE_TXDATA,
    PIPE_POWERDOWN,
    phy_rdy_n,
    pipe_rx0_valid,
    CLK,
    PIPE_RXCHANISALIGNED,
    gt_rx_phy_status_q,
    gt_rxelecidle_q,
    pipe_rx0_polarity_i,
    pipe_tx0_compliance_i,
    pipe_tx0_elec_idle_i,
    D,
    \gt_rxdata_q_reg[15] ,
    \gt_rx_status_q_reg[2] ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 );
  output pipe_rx0_valid_o;
  output pipe_rx0_chanisaligned_o;
  output pipe_rx0_phy_status_o;
  output pipe_rx0_elec_idle_o;
  output [0:0]PIPE_RXPOLARITY;
  output [0:0]PIPE_TXCOMPLIANCE;
  output [0:0]PIPE_TXELECIDLE;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;
  output [1:0]PIPE_TXDATAK;
  output [15:0]PIPE_TXDATA;
  output [1:0]PIPE_POWERDOWN;
  input phy_rdy_n;
  input pipe_rx0_valid;
  input CLK;
  input [0:0]PIPE_RXCHANISALIGNED;
  input gt_rx_phy_status_q;
  input gt_rxelecidle_q;
  input pipe_rx0_polarity_i;
  input pipe_tx0_compliance_i;
  input pipe_tx0_elec_idle_i;
  input [1:0]D;
  input [15:0]\gt_rxdata_q_reg[15] ;
  input [2:0]\gt_rx_status_q_reg[2] ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;

  wire CLK;
  wire [1:0]D;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXELECIDLE;
  wire gt_rx_phy_status_q;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxelecidle_q;
  wire phy_rdy_n;
  wire pipe_rx0_chanisaligned_o;
  wire pipe_rx0_elec_idle_o;
  wire pipe_rx0_phy_status_o;
  wire pipe_rx0_polarity_i;
  wire pipe_rx0_valid;
  wire pipe_rx0_valid_o;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  wire pipe_tx0_compliance_i;
  wire pipe_tx0_elec_idle_i;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;

  FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(PIPE_RXCHANISALIGNED),
        .Q(pipe_rx0_chanisaligned_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [10]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [11]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [12]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [13]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [14]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [15]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [3]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [4]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [5]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [6]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [7]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [8]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [9]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [9]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rxelecidle_q),
        .Q(pipe_rx0_elec_idle_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_q),
        .Q(pipe_rx0_phy_status_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_polarity_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx0_polarity_i),
        .Q(PIPE_RXPOLARITY),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_valid_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx0_valid),
        .Q(pipe_rx0_valid_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [0]),
        .Q(PIPE_TXDATAK[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [1]),
        .Q(PIPE_TXDATAK[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_compliance_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx0_compliance_i),
        .Q(PIPE_TXCOMPLIANCE),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [0]),
        .Q(PIPE_TXDATA[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [10]),
        .Q(PIPE_TXDATA[10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [11]),
        .Q(PIPE_TXDATA[11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [12]),
        .Q(PIPE_TXDATA[12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [13]),
        .Q(PIPE_TXDATA[13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [14]),
        .Q(PIPE_TXDATA[14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [15]),
        .Q(PIPE_TXDATA[15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [1]),
        .Q(PIPE_TXDATA[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [2]),
        .Q(PIPE_TXDATA[2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [3]),
        .Q(PIPE_TXDATA[3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [4]),
        .Q(PIPE_TXDATA[4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [5]),
        .Q(PIPE_TXDATA[5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [6]),
        .Q(PIPE_TXDATA[6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [7]),
        .Q(PIPE_TXDATA[7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [8]),
        .Q(PIPE_TXDATA[8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [9]),
        .Q(PIPE_TXDATA[9]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx0_elec_idle_i),
        .Q(PIPE_TXELECIDLE),
        .S(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [0]),
        .Q(PIPE_POWERDOWN[0]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [1]),
        .Q(PIPE_POWERDOWN[1]),
        .S(phy_rdy_n));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_pipe_lane" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_0
   (PIPE_RXPOLARITY,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    pipe_rx1_valid_o,
    pipe_rx1_chanisaligned_o,
    pipe_rx1_phy_status_o,
    pipe_rx1_elec_idle_o,
    PIPE_TXDATAK,
    PIPE_TXDATA,
    PIPE_POWERDOWN,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_1 ,
    phy_rdy_n,
    pipe_rx1_polarity_i,
    CLK,
    pipe_tx1_compliance_i,
    pipe_tx1_elec_idle_i,
    pipe_rx1_valid,
    PIPE_RXCHANISALIGNED,
    gt_rx_phy_status_q_reg,
    gt_rxelecidle_q_reg,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ,
    \gt_rxcharisk_q_reg[1] ,
    \gt_rxdata_q_reg[15] ,
    \gt_rx_status_q_reg[2] );
  output [0:0]PIPE_RXPOLARITY;
  output [0:0]PIPE_TXCOMPLIANCE;
  output [0:0]PIPE_TXELECIDLE;
  output pipe_rx1_valid_o;
  output pipe_rx1_chanisaligned_o;
  output pipe_rx1_phy_status_o;
  output pipe_rx1_elec_idle_o;
  output [1:0]PIPE_TXDATAK;
  output [15:0]PIPE_TXDATA;
  output [1:0]PIPE_POWERDOWN;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;
  input phy_rdy_n;
  input pipe_rx1_polarity_i;
  input CLK;
  input pipe_tx1_compliance_i;
  input pipe_tx1_elec_idle_i;
  input pipe_rx1_valid;
  input [0:0]PIPE_RXCHANISALIGNED;
  input gt_rx_phy_status_q_reg;
  input gt_rxelecidle_q_reg;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  input [1:0]\gt_rxcharisk_q_reg[1] ;
  input [15:0]\gt_rxdata_q_reg[15] ;
  input [2:0]\gt_rx_status_q_reg[2] ;

  wire CLK;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXELECIDLE;
  wire gt_rx_phy_status_q_reg;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxelecidle_q_reg;
  wire phy_rdy_n;
  wire pipe_rx1_chanisaligned_o;
  wire pipe_rx1_elec_idle_o;
  wire pipe_rx1_phy_status_o;
  wire pipe_rx1_polarity_i;
  wire pipe_rx1_valid;
  wire pipe_rx1_valid_o;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  wire pipe_tx1_compliance_i;
  wire pipe_tx1_elec_idle_i;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;

  FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(PIPE_RXCHANISALIGNED),
        .Q(pipe_rx1_chanisaligned_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [10]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [11]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [12]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [13]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [14]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [15]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [3]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [4]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [5]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [6]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [7]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [8]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [9]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [9]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rxelecidle_q_reg),
        .Q(pipe_rx1_elec_idle_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_q_reg),
        .Q(pipe_rx1_phy_status_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_polarity_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx1_polarity_i),
        .Q(PIPE_RXPOLARITY),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_valid_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx1_valid),
        .Q(pipe_rx1_valid_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [0]),
        .Q(PIPE_TXDATAK[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [1]),
        .Q(PIPE_TXDATAK[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_compliance_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx1_compliance_i),
        .Q(PIPE_TXCOMPLIANCE),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [0]),
        .Q(PIPE_TXDATA[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [10]),
        .Q(PIPE_TXDATA[10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [11]),
        .Q(PIPE_TXDATA[11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [12]),
        .Q(PIPE_TXDATA[12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [13]),
        .Q(PIPE_TXDATA[13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [14]),
        .Q(PIPE_TXDATA[14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [15]),
        .Q(PIPE_TXDATA[15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [1]),
        .Q(PIPE_TXDATA[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [2]),
        .Q(PIPE_TXDATA[2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [3]),
        .Q(PIPE_TXDATA[3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [4]),
        .Q(PIPE_TXDATA[4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [5]),
        .Q(PIPE_TXDATA[5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [6]),
        .Q(PIPE_TXDATA[6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [7]),
        .Q(PIPE_TXDATA[7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [8]),
        .Q(PIPE_TXDATA[8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [9]),
        .Q(PIPE_TXDATA[9]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx1_elec_idle_i),
        .Q(PIPE_TXELECIDLE),
        .S(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [0]),
        .Q(PIPE_POWERDOWN[0]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [1]),
        .Q(PIPE_POWERDOWN[1]),
        .S(phy_rdy_n));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_pipe_lane" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_1
   (PIPE_RXPOLARITY,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    pipe_rx2_valid_o,
    pipe_rx2_chanisaligned_o,
    pipe_rx2_phy_status_o,
    pipe_rx2_elec_idle_o,
    PIPE_TXDATAK,
    PIPE_TXDATA,
    PIPE_POWERDOWN,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_1 ,
    phy_rdy_n,
    pipe_rx2_polarity_i,
    CLK,
    pipe_tx2_compliance_i,
    pipe_tx2_elec_idle_i,
    pipe_rx2_valid,
    PIPE_RXCHANISALIGNED,
    gt_rx_phy_status_q_reg,
    gt_rxelecidle_q_reg,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ,
    \gt_rxcharisk_q_reg[1] ,
    \gt_rxdata_q_reg[15] ,
    \gt_rx_status_q_reg[2] );
  output [0:0]PIPE_RXPOLARITY;
  output [0:0]PIPE_TXCOMPLIANCE;
  output [0:0]PIPE_TXELECIDLE;
  output pipe_rx2_valid_o;
  output pipe_rx2_chanisaligned_o;
  output pipe_rx2_phy_status_o;
  output pipe_rx2_elec_idle_o;
  output [1:0]PIPE_TXDATAK;
  output [15:0]PIPE_TXDATA;
  output [1:0]PIPE_POWERDOWN;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;
  input phy_rdy_n;
  input pipe_rx2_polarity_i;
  input CLK;
  input pipe_tx2_compliance_i;
  input pipe_tx2_elec_idle_i;
  input pipe_rx2_valid;
  input [0:0]PIPE_RXCHANISALIGNED;
  input gt_rx_phy_status_q_reg;
  input gt_rxelecidle_q_reg;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  input [1:0]\gt_rxcharisk_q_reg[1] ;
  input [15:0]\gt_rxdata_q_reg[15] ;
  input [2:0]\gt_rx_status_q_reg[2] ;

  wire CLK;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXELECIDLE;
  wire gt_rx_phy_status_q_reg;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxelecidle_q_reg;
  wire phy_rdy_n;
  wire pipe_rx2_chanisaligned_o;
  wire pipe_rx2_elec_idle_o;
  wire pipe_rx2_phy_status_o;
  wire pipe_rx2_polarity_i;
  wire pipe_rx2_valid;
  wire pipe_rx2_valid_o;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  wire pipe_tx2_compliance_i;
  wire pipe_tx2_elec_idle_i;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;

  FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(PIPE_RXCHANISALIGNED),
        .Q(pipe_rx2_chanisaligned_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [10]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [11]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [12]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [13]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [14]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [15]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [3]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [4]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [5]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [6]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [7]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [8]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [9]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [9]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rxelecidle_q_reg),
        .Q(pipe_rx2_elec_idle_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_q_reg),
        .Q(pipe_rx2_phy_status_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_polarity_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx2_polarity_i),
        .Q(PIPE_RXPOLARITY),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_valid_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx2_valid),
        .Q(pipe_rx2_valid_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [0]),
        .Q(PIPE_TXDATAK[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [1]),
        .Q(PIPE_TXDATAK[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_compliance_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx2_compliance_i),
        .Q(PIPE_TXCOMPLIANCE),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [0]),
        .Q(PIPE_TXDATA[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [10]),
        .Q(PIPE_TXDATA[10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [11]),
        .Q(PIPE_TXDATA[11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [12]),
        .Q(PIPE_TXDATA[12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [13]),
        .Q(PIPE_TXDATA[13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [14]),
        .Q(PIPE_TXDATA[14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [15]),
        .Q(PIPE_TXDATA[15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [1]),
        .Q(PIPE_TXDATA[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [2]),
        .Q(PIPE_TXDATA[2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [3]),
        .Q(PIPE_TXDATA[3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [4]),
        .Q(PIPE_TXDATA[4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [5]),
        .Q(PIPE_TXDATA[5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [6]),
        .Q(PIPE_TXDATA[6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [7]),
        .Q(PIPE_TXDATA[7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [8]),
        .Q(PIPE_TXDATA[8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [9]),
        .Q(PIPE_TXDATA[9]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx2_elec_idle_i),
        .Q(PIPE_TXELECIDLE),
        .S(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [0]),
        .Q(PIPE_POWERDOWN[0]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [1]),
        .Q(PIPE_POWERDOWN[1]),
        .S(phy_rdy_n));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_pipe_lane" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_2
   (PIPE_RXPOLARITY,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    pipe_rx3_valid_o,
    pipe_rx3_chanisaligned_o,
    pipe_rx3_phy_status_o,
    pipe_rx3_elec_idle_o,
    PIPE_TXDATAK,
    PIPE_TXDATA,
    PIPE_POWERDOWN,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_1 ,
    phy_rdy_n,
    pipe_rx3_polarity_i,
    CLK,
    pipe_tx3_compliance_i,
    pipe_tx3_elec_idle_i,
    pipe_rx3_valid,
    PIPE_RXCHANISALIGNED,
    gt_rx_phy_status_q_reg,
    gt_rxelecidle_q_reg,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ,
    \gt_rxcharisk_q_reg[1] ,
    \gt_rxdata_q_reg[15] ,
    \gt_rx_status_q_reg[2] );
  output [0:0]PIPE_RXPOLARITY;
  output [0:0]PIPE_TXCOMPLIANCE;
  output [0:0]PIPE_TXELECIDLE;
  output pipe_rx3_valid_o;
  output pipe_rx3_chanisaligned_o;
  output pipe_rx3_phy_status_o;
  output pipe_rx3_elec_idle_o;
  output [1:0]PIPE_TXDATAK;
  output [15:0]PIPE_TXDATA;
  output [1:0]PIPE_POWERDOWN;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;
  input phy_rdy_n;
  input pipe_rx3_polarity_i;
  input CLK;
  input pipe_tx3_compliance_i;
  input pipe_tx3_elec_idle_i;
  input pipe_rx3_valid;
  input [0:0]PIPE_RXCHANISALIGNED;
  input gt_rx_phy_status_q_reg;
  input gt_rxelecidle_q_reg;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  input [1:0]\gt_rxcharisk_q_reg[1] ;
  input [15:0]\gt_rxdata_q_reg[15] ;
  input [2:0]\gt_rx_status_q_reg[2] ;

  wire CLK;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXELECIDLE;
  wire gt_rx_phy_status_q_reg;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxelecidle_q_reg;
  wire phy_rdy_n;
  wire pipe_rx3_chanisaligned_o;
  wire pipe_rx3_elec_idle_o;
  wire pipe_rx3_phy_status_o;
  wire pipe_rx3_polarity_i;
  wire pipe_rx3_valid;
  wire pipe_rx3_valid_o;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  wire pipe_tx3_compliance_i;
  wire pipe_tx3_elec_idle_i;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;

  FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(PIPE_RXCHANISALIGNED),
        .Q(pipe_rx3_chanisaligned_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [10]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [11]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [12]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [13]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [14]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [15]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [3]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [4]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [5]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [6]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [7]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [8]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [9]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [9]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rxelecidle_q_reg),
        .Q(pipe_rx3_elec_idle_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_q_reg),
        .Q(pipe_rx3_phy_status_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_polarity_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx3_polarity_i),
        .Q(PIPE_RXPOLARITY),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_valid_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx3_valid),
        .Q(pipe_rx3_valid_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [0]),
        .Q(PIPE_TXDATAK[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [1]),
        .Q(PIPE_TXDATAK[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_compliance_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx3_compliance_i),
        .Q(PIPE_TXCOMPLIANCE),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [0]),
        .Q(PIPE_TXDATA[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [10]),
        .Q(PIPE_TXDATA[10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [11]),
        .Q(PIPE_TXDATA[11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [12]),
        .Q(PIPE_TXDATA[12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [13]),
        .Q(PIPE_TXDATA[13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [14]),
        .Q(PIPE_TXDATA[14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [15]),
        .Q(PIPE_TXDATA[15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [1]),
        .Q(PIPE_TXDATA[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [2]),
        .Q(PIPE_TXDATA[2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [3]),
        .Q(PIPE_TXDATA[3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [4]),
        .Q(PIPE_TXDATA[4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [5]),
        .Q(PIPE_TXDATA[5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [6]),
        .Q(PIPE_TXDATA[6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [7]),
        .Q(PIPE_TXDATA[7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [8]),
        .Q(PIPE_TXDATA[8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [9]),
        .Q(PIPE_TXDATA[9]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx3_elec_idle_i),
        .Q(PIPE_TXELECIDLE),
        .S(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [0]),
        .Q(PIPE_POWERDOWN[0]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [1]),
        .Q(PIPE_POWERDOWN[1]),
        .S(phy_rdy_n));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_pipe_lane" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_3
   (PIPE_RXPOLARITY,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    pipe_rx4_valid_o,
    pipe_rx4_chanisaligned_o,
    pipe_rx4_phy_status_o,
    pipe_rx4_elec_idle_o,
    PIPE_TXDATAK,
    PIPE_TXDATA,
    PIPE_POWERDOWN,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_1 ,
    phy_rdy_n,
    pipe_rx4_polarity_i,
    CLK,
    pipe_tx4_compliance_i,
    pipe_tx4_elec_idle_i,
    pipe_rx4_valid,
    PIPE_RXCHANISALIGNED,
    gt_rx_phy_status_q_reg,
    gt_rxelecidle_q_reg,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ,
    \gt_rxcharisk_q_reg[1] ,
    \gt_rxdata_q_reg[15] ,
    \gt_rx_status_q_reg[2] );
  output [0:0]PIPE_RXPOLARITY;
  output [0:0]PIPE_TXCOMPLIANCE;
  output [0:0]PIPE_TXELECIDLE;
  output pipe_rx4_valid_o;
  output pipe_rx4_chanisaligned_o;
  output pipe_rx4_phy_status_o;
  output pipe_rx4_elec_idle_o;
  output [1:0]PIPE_TXDATAK;
  output [15:0]PIPE_TXDATA;
  output [1:0]PIPE_POWERDOWN;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;
  input phy_rdy_n;
  input pipe_rx4_polarity_i;
  input CLK;
  input pipe_tx4_compliance_i;
  input pipe_tx4_elec_idle_i;
  input pipe_rx4_valid;
  input [0:0]PIPE_RXCHANISALIGNED;
  input gt_rx_phy_status_q_reg;
  input gt_rxelecidle_q_reg;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  input [1:0]\gt_rxcharisk_q_reg[1] ;
  input [15:0]\gt_rxdata_q_reg[15] ;
  input [2:0]\gt_rx_status_q_reg[2] ;

  wire CLK;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXELECIDLE;
  wire gt_rx_phy_status_q_reg;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxelecidle_q_reg;
  wire phy_rdy_n;
  wire pipe_rx4_chanisaligned_o;
  wire pipe_rx4_elec_idle_o;
  wire pipe_rx4_phy_status_o;
  wire pipe_rx4_polarity_i;
  wire pipe_rx4_valid;
  wire pipe_rx4_valid_o;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  wire pipe_tx4_compliance_i;
  wire pipe_tx4_elec_idle_i;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;

  FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(PIPE_RXCHANISALIGNED),
        .Q(pipe_rx4_chanisaligned_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [10]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [11]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [12]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [13]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [14]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [15]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [3]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [4]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [5]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [6]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [7]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [8]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [9]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [9]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rxelecidle_q_reg),
        .Q(pipe_rx4_elec_idle_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_q_reg),
        .Q(pipe_rx4_phy_status_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_polarity_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx4_polarity_i),
        .Q(PIPE_RXPOLARITY),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_valid_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx4_valid),
        .Q(pipe_rx4_valid_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [0]),
        .Q(PIPE_TXDATAK[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [1]),
        .Q(PIPE_TXDATAK[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_compliance_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx4_compliance_i),
        .Q(PIPE_TXCOMPLIANCE),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [0]),
        .Q(PIPE_TXDATA[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [10]),
        .Q(PIPE_TXDATA[10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [11]),
        .Q(PIPE_TXDATA[11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [12]),
        .Q(PIPE_TXDATA[12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [13]),
        .Q(PIPE_TXDATA[13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [14]),
        .Q(PIPE_TXDATA[14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [15]),
        .Q(PIPE_TXDATA[15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [1]),
        .Q(PIPE_TXDATA[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [2]),
        .Q(PIPE_TXDATA[2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [3]),
        .Q(PIPE_TXDATA[3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [4]),
        .Q(PIPE_TXDATA[4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [5]),
        .Q(PIPE_TXDATA[5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [6]),
        .Q(PIPE_TXDATA[6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [7]),
        .Q(PIPE_TXDATA[7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [8]),
        .Q(PIPE_TXDATA[8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [9]),
        .Q(PIPE_TXDATA[9]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx4_elec_idle_i),
        .Q(PIPE_TXELECIDLE),
        .S(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [0]),
        .Q(PIPE_POWERDOWN[0]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [1]),
        .Q(PIPE_POWERDOWN[1]),
        .S(phy_rdy_n));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_pipe_lane" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_4
   (PIPE_RXPOLARITY,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    pipe_rx5_valid_o,
    pipe_rx5_chanisaligned_o,
    pipe_rx5_phy_status_o,
    pipe_rx5_elec_idle_o,
    PIPE_TXDATAK,
    PIPE_TXDATA,
    PIPE_POWERDOWN,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_1 ,
    phy_rdy_n,
    pipe_rx5_polarity_i,
    CLK,
    pipe_tx5_compliance_i,
    pipe_tx5_elec_idle_i,
    pipe_rx5_valid,
    PIPE_RXCHANISALIGNED,
    gt_rx_phy_status_q_reg,
    gt_rxelecidle_q_reg,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ,
    \gt_rxcharisk_q_reg[1] ,
    \gt_rxdata_q_reg[15] ,
    \gt_rx_status_q_reg[2] );
  output [0:0]PIPE_RXPOLARITY;
  output [0:0]PIPE_TXCOMPLIANCE;
  output [0:0]PIPE_TXELECIDLE;
  output pipe_rx5_valid_o;
  output pipe_rx5_chanisaligned_o;
  output pipe_rx5_phy_status_o;
  output pipe_rx5_elec_idle_o;
  output [1:0]PIPE_TXDATAK;
  output [15:0]PIPE_TXDATA;
  output [1:0]PIPE_POWERDOWN;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;
  input phy_rdy_n;
  input pipe_rx5_polarity_i;
  input CLK;
  input pipe_tx5_compliance_i;
  input pipe_tx5_elec_idle_i;
  input pipe_rx5_valid;
  input [0:0]PIPE_RXCHANISALIGNED;
  input gt_rx_phy_status_q_reg;
  input gt_rxelecidle_q_reg;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  input [1:0]\gt_rxcharisk_q_reg[1] ;
  input [15:0]\gt_rxdata_q_reg[15] ;
  input [2:0]\gt_rx_status_q_reg[2] ;

  wire CLK;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXELECIDLE;
  wire gt_rx_phy_status_q_reg;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxelecidle_q_reg;
  wire phy_rdy_n;
  wire pipe_rx5_chanisaligned_o;
  wire pipe_rx5_elec_idle_o;
  wire pipe_rx5_phy_status_o;
  wire pipe_rx5_polarity_i;
  wire pipe_rx5_valid;
  wire pipe_rx5_valid_o;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  wire pipe_tx5_compliance_i;
  wire pipe_tx5_elec_idle_i;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;

  FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(PIPE_RXCHANISALIGNED),
        .Q(pipe_rx5_chanisaligned_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [10]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [11]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [12]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [13]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [14]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [15]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [3]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [4]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [5]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [6]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [7]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [8]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [9]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [9]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rxelecidle_q_reg),
        .Q(pipe_rx5_elec_idle_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_q_reg),
        .Q(pipe_rx5_phy_status_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_polarity_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx5_polarity_i),
        .Q(PIPE_RXPOLARITY),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_valid_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx5_valid),
        .Q(pipe_rx5_valid_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [0]),
        .Q(PIPE_TXDATAK[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [1]),
        .Q(PIPE_TXDATAK[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_compliance_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx5_compliance_i),
        .Q(PIPE_TXCOMPLIANCE),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [0]),
        .Q(PIPE_TXDATA[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [10]),
        .Q(PIPE_TXDATA[10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [11]),
        .Q(PIPE_TXDATA[11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [12]),
        .Q(PIPE_TXDATA[12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [13]),
        .Q(PIPE_TXDATA[13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [14]),
        .Q(PIPE_TXDATA[14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [15]),
        .Q(PIPE_TXDATA[15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [1]),
        .Q(PIPE_TXDATA[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [2]),
        .Q(PIPE_TXDATA[2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [3]),
        .Q(PIPE_TXDATA[3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [4]),
        .Q(PIPE_TXDATA[4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [5]),
        .Q(PIPE_TXDATA[5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [6]),
        .Q(PIPE_TXDATA[6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [7]),
        .Q(PIPE_TXDATA[7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [8]),
        .Q(PIPE_TXDATA[8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [9]),
        .Q(PIPE_TXDATA[9]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx5_elec_idle_i),
        .Q(PIPE_TXELECIDLE),
        .S(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [0]),
        .Q(PIPE_POWERDOWN[0]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [1]),
        .Q(PIPE_POWERDOWN[1]),
        .S(phy_rdy_n));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_pipe_lane" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_5
   (PIPE_RXPOLARITY,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    pipe_rx6_valid_o,
    pipe_rx6_chanisaligned_o,
    pipe_rx6_phy_status_o,
    pipe_rx6_elec_idle_o,
    PIPE_TXDATAK,
    PIPE_TXDATA,
    PIPE_POWERDOWN,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_1 ,
    phy_rdy_n,
    pipe_rx6_polarity_i,
    CLK,
    pipe_tx6_compliance_i,
    pipe_tx6_elec_idle_i,
    pipe_rx6_valid,
    PIPE_RXCHANISALIGNED,
    gt_rx_phy_status_q_reg,
    gt_rxelecidle_q_reg,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ,
    \gt_rxcharisk_q_reg[1] ,
    \gt_rxdata_q_reg[15] ,
    \gt_rx_status_q_reg[2] );
  output [0:0]PIPE_RXPOLARITY;
  output [0:0]PIPE_TXCOMPLIANCE;
  output [0:0]PIPE_TXELECIDLE;
  output pipe_rx6_valid_o;
  output pipe_rx6_chanisaligned_o;
  output pipe_rx6_phy_status_o;
  output pipe_rx6_elec_idle_o;
  output [1:0]PIPE_TXDATAK;
  output [15:0]PIPE_TXDATA;
  output [1:0]PIPE_POWERDOWN;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;
  input phy_rdy_n;
  input pipe_rx6_polarity_i;
  input CLK;
  input pipe_tx6_compliance_i;
  input pipe_tx6_elec_idle_i;
  input pipe_rx6_valid;
  input [0:0]PIPE_RXCHANISALIGNED;
  input gt_rx_phy_status_q_reg;
  input gt_rxelecidle_q_reg;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  input [1:0]\gt_rxcharisk_q_reg[1] ;
  input [15:0]\gt_rxdata_q_reg[15] ;
  input [2:0]\gt_rx_status_q_reg[2] ;

  wire CLK;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXELECIDLE;
  wire gt_rx_phy_status_q_reg;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxelecidle_q_reg;
  wire phy_rdy_n;
  wire pipe_rx6_chanisaligned_o;
  wire pipe_rx6_elec_idle_o;
  wire pipe_rx6_phy_status_o;
  wire pipe_rx6_polarity_i;
  wire pipe_rx6_valid;
  wire pipe_rx6_valid_o;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  wire pipe_tx6_compliance_i;
  wire pipe_tx6_elec_idle_i;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;

  FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(PIPE_RXCHANISALIGNED),
        .Q(pipe_rx6_chanisaligned_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [10]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [11]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [12]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [13]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [14]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [15]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [3]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [4]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [5]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [6]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [7]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [8]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [9]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [9]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rxelecidle_q_reg),
        .Q(pipe_rx6_elec_idle_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_q_reg),
        .Q(pipe_rx6_phy_status_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_polarity_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx6_polarity_i),
        .Q(PIPE_RXPOLARITY),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_valid_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx6_valid),
        .Q(pipe_rx6_valid_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [0]),
        .Q(PIPE_TXDATAK[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [1]),
        .Q(PIPE_TXDATAK[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_compliance_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx6_compliance_i),
        .Q(PIPE_TXCOMPLIANCE),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [0]),
        .Q(PIPE_TXDATA[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [10]),
        .Q(PIPE_TXDATA[10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [11]),
        .Q(PIPE_TXDATA[11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [12]),
        .Q(PIPE_TXDATA[12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [13]),
        .Q(PIPE_TXDATA[13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [14]),
        .Q(PIPE_TXDATA[14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [15]),
        .Q(PIPE_TXDATA[15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [1]),
        .Q(PIPE_TXDATA[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [2]),
        .Q(PIPE_TXDATA[2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [3]),
        .Q(PIPE_TXDATA[3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [4]),
        .Q(PIPE_TXDATA[4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [5]),
        .Q(PIPE_TXDATA[5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [6]),
        .Q(PIPE_TXDATA[6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [7]),
        .Q(PIPE_TXDATA[7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [8]),
        .Q(PIPE_TXDATA[8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [9]),
        .Q(PIPE_TXDATA[9]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx6_elec_idle_i),
        .Q(PIPE_TXELECIDLE),
        .S(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [0]),
        .Q(PIPE_POWERDOWN[0]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [1]),
        .Q(PIPE_POWERDOWN[1]),
        .S(phy_rdy_n));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_pipe_lane" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_6
   (PIPE_RXPOLARITY,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    pipe_rx7_valid_o,
    pipe_rx7_chanisaligned_o,
    pipe_rx7_phy_status_o,
    pipe_rx7_elec_idle_o,
    PIPE_TXDATAK,
    PIPE_TXDATA,
    PIPE_POWERDOWN,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_1 ,
    phy_rdy_n,
    pipe_rx7_polarity_i,
    CLK,
    pipe_tx7_compliance_i,
    pipe_tx7_elec_idle_i,
    pipe_rx7_valid,
    PIPE_RXCHANISALIGNED,
    gt_rx_phy_status_q_reg,
    gt_rxelecidle_q_reg,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ,
    \gt_rxcharisk_q_reg[1] ,
    \gt_rxdata_q_reg[15] ,
    \gt_rx_status_q_reg[2] );
  output [0:0]PIPE_RXPOLARITY;
  output [0:0]PIPE_TXCOMPLIANCE;
  output [0:0]PIPE_TXELECIDLE;
  output pipe_rx7_valid_o;
  output pipe_rx7_chanisaligned_o;
  output pipe_rx7_phy_status_o;
  output pipe_rx7_elec_idle_o;
  output [1:0]PIPE_TXDATAK;
  output [15:0]PIPE_TXDATA;
  output [1:0]PIPE_POWERDOWN;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;
  input phy_rdy_n;
  input pipe_rx7_polarity_i;
  input CLK;
  input pipe_tx7_compliance_i;
  input pipe_tx7_elec_idle_i;
  input pipe_rx7_valid;
  input [0:0]PIPE_RXCHANISALIGNED;
  input gt_rx_phy_status_q_reg;
  input gt_rxelecidle_q_reg;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  input [1:0]\gt_rxcharisk_q_reg[1] ;
  input [15:0]\gt_rxdata_q_reg[15] ;
  input [2:0]\gt_rx_status_q_reg[2] ;

  wire CLK;
  wire [1:0]PIPE_POWERDOWN;
  wire [0:0]PIPE_RXCHANISALIGNED;
  wire [0:0]PIPE_RXPOLARITY;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [15:0]PIPE_TXDATA;
  wire [1:0]PIPE_TXDATAK;
  wire [0:0]PIPE_TXELECIDLE;
  wire gt_rx_phy_status_q_reg;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire gt_rxelecidle_q_reg;
  wire phy_rdy_n;
  wire pipe_rx7_chanisaligned_o;
  wire pipe_rx7_elec_idle_o;
  wire pipe_rx7_phy_status_o;
  wire pipe_rx7_polarity_i;
  wire pipe_rx7_valid;
  wire pipe_rx7_valid_o;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  wire pipe_tx7_compliance_i;
  wire pipe_tx7_elec_idle_i;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;

  FDRE \pipe_stages_1.pipe_rx_chanisaligned_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(PIPE_RXCHANISALIGNED),
        .Q(pipe_rx7_chanisaligned_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxcharisk_q_reg[1] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [10]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [11]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [12]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [13]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [14]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [15]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [3]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [4]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [5]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [6]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [7]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [8]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rxdata_q_reg[15] [9]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_0 [9]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rxelecidle_q_reg),
        .Q(pipe_rx7_elec_idle_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_phy_status_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(gt_rx_phy_status_q_reg),
        .Q(pipe_rx7_phy_status_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_polarity_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx7_polarity_i),
        .Q(PIPE_RXPOLARITY),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [0]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [1]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_status_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gt_rx_status_q_reg[2] [2]),
        .Q(\ramb_bl.ramb36_dp_bl.ram36_bl_1 [2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_rx_valid_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_rx7_valid),
        .Q(pipe_rx7_valid_o),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [0]),
        .Q(PIPE_TXDATAK[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_char_is_k_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 [1]),
        .Q(PIPE_TXDATAK[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_compliance_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx7_compliance_i),
        .Q(PIPE_TXCOMPLIANCE),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [0]),
        .Q(PIPE_TXDATA[0]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [10]),
        .Q(PIPE_TXDATA[10]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [11]),
        .Q(PIPE_TXDATA[11]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [12]),
        .Q(PIPE_TXDATA[12]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [13]),
        .Q(PIPE_TXDATA[13]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [14]),
        .Q(PIPE_TXDATA[14]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [15]),
        .Q(PIPE_TXDATA[15]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [1]),
        .Q(PIPE_TXDATA[1]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [2]),
        .Q(PIPE_TXDATA[2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [3]),
        .Q(PIPE_TXDATA[3]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [4]),
        .Q(PIPE_TXDATA[4]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [5]),
        .Q(PIPE_TXDATA[5]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [6]),
        .Q(PIPE_TXDATA[6]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [7]),
        .Q(PIPE_TXDATA[7]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [8]),
        .Q(PIPE_TXDATA[8]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_data_q_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 [9]),
        .Q(PIPE_TXDATA[9]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_elec_idle_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx7_elec_idle_i),
        .Q(PIPE_TXELECIDLE),
        .S(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_powerdown_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [0]),
        .Q(PIPE_POWERDOWN[0]),
        .R(phy_rdy_n));
  FDSE \pipe_stages_1.pipe_tx_powerdown_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 [1]),
        .Q(PIPE_POWERDOWN[1]),
        .S(phy_rdy_n));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_pipe_misc" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_misc
   (pipe_tx_rcvr_det,
    \rate_reg1_reg[0] ,
    PIPE_TXDEEMPH,
    \cplllock_reg1_reg[3] ,
    \cplllock_reg1_reg[2] ,
    \cplllock_reg1_reg[6] ,
    Q,
    \cplllock_reg1_reg[3]_0 ,
    TXMARGIN,
    PIPE_TXMARGIN,
    phy_rdy_n,
    pipe_tx_rcvr_det_i,
    CLK,
    pipe_tx_rate_i,
    pipe_tx_deemph_i,
    pipe_tx_margin);
  output pipe_tx_rcvr_det;
  output [0:0]\rate_reg1_reg[0] ;
  output [3:0]PIPE_TXDEEMPH;
  output \cplllock_reg1_reg[3] ;
  output \cplllock_reg1_reg[2] ;
  output \cplllock_reg1_reg[6] ;
  output [2:0]Q;
  output [2:0]\cplllock_reg1_reg[3]_0 ;
  output [2:0]TXMARGIN;
  output [2:0]PIPE_TXMARGIN;
  input phy_rdy_n;
  input pipe_tx_rcvr_det_i;
  input CLK;
  input pipe_tx_rate_i;
  input pipe_tx_deemph_i;
  input [2:0]pipe_tx_margin;

  wire CLK;
  wire [3:0]PIPE_TXDEEMPH;
  wire [2:0]PIPE_TXMARGIN;
  wire [2:0]Q;
  wire [2:0]TXMARGIN;
  wire \cplllock_reg1_reg[2] ;
  wire \cplllock_reg1_reg[3] ;
  wire [2:0]\cplllock_reg1_reg[3]_0 ;
  wire \cplllock_reg1_reg[6] ;
  wire phy_rdy_n;
  wire pipe_tx_deemph_i;
  wire [2:0]pipe_tx_margin;
  wire pipe_tx_rate_i;
  wire pipe_tx_rcvr_det;
  wire pipe_tx_rcvr_det_i;
  wire [0:0]\rate_reg1_reg[0] ;

  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_deemph_q_reg" *) 
  FDSE \pipe_stages_1.pipe_tx_deemph_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_deemph_i),
        .Q(PIPE_TXDEEMPH[0]),
        .S(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_deemph_q_reg" *) 
  FDSE \pipe_stages_1.pipe_tx_deemph_q_reg_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_deemph_i),
        .Q(PIPE_TXDEEMPH[1]),
        .S(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_deemph_q_reg" *) 
  FDSE \pipe_stages_1.pipe_tx_deemph_q_reg_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_deemph_i),
        .Q(PIPE_TXDEEMPH[2]),
        .S(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_deemph_q_reg" *) 
  FDSE \pipe_stages_1.pipe_tx_deemph_q_reg_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_deemph_i),
        .Q(PIPE_TXDEEMPH[3]),
        .S(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[0]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[0]),
        .Q(Q[0]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[0]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[0]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[0]),
        .Q(\cplllock_reg1_reg[3]_0 [0]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[0]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[0]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[0]),
        .Q(TXMARGIN[0]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[0]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[0]_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[0]),
        .Q(PIPE_TXMARGIN[0]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[1]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[1]),
        .Q(Q[1]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[1]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[1]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[1]),
        .Q(\cplllock_reg1_reg[3]_0 [1]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[1]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[1]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[1]),
        .Q(TXMARGIN[1]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[1]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[1]_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[1]),
        .Q(PIPE_TXMARGIN[1]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[2]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[2]),
        .Q(Q[2]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[2]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[2]),
        .Q(\cplllock_reg1_reg[3]_0 [2]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[2]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[2]),
        .Q(TXMARGIN[2]),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_margin_q_reg[2]" *) 
  FDRE \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_margin[2]),
        .Q(PIPE_TXMARGIN[2]),
        .R(phy_rdy_n));
  FDRE \pipe_stages_1.pipe_tx_rate_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_rate_i),
        .Q(\rate_reg1_reg[0] ),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_rcvr_det_q_reg" *) 
  FDRE \pipe_stages_1.pipe_tx_rcvr_det_q_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_rcvr_det_i),
        .Q(pipe_tx_rcvr_det),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_rcvr_det_q_reg" *) 
  FDRE \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_rcvr_det_i),
        .Q(\cplllock_reg1_reg[3] ),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_rcvr_det_q_reg" *) 
  FDRE \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_rcvr_det_i),
        .Q(\cplllock_reg1_reg[2] ),
        .R(phy_rdy_n));
  (* ORIG_CELL_NAME = "pipe_stages_1.pipe_tx_rcvr_det_q_reg" *) 
  FDRE \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__1 
       (.C(CLK),
        .CE(1'b1),
        .D(pipe_tx_rcvr_det_i),
        .Q(\cplllock_reg1_reg[6] ),
        .R(phy_rdy_n));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_pipe_pipeline" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_pipeline
   (pipe_tx_rcvr_det,
    \rate_reg1_reg[0] ,
    PIPE_TXDEEMPH,
    pipe_rx0_valid_o,
    pipe_rx0_chanisaligned_o,
    pipe_rx0_phy_status_o,
    pipe_rx0_elec_idle_o,
    PIPE_RXPOLARITY,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    pipe_rx1_valid_o,
    pipe_rx1_chanisaligned_o,
    pipe_rx1_phy_status_o,
    pipe_rx1_elec_idle_o,
    pipe_rx2_valid_o,
    pipe_rx2_chanisaligned_o,
    pipe_rx2_phy_status_o,
    pipe_rx2_elec_idle_o,
    pipe_rx3_valid_o,
    pipe_rx3_chanisaligned_o,
    pipe_rx3_phy_status_o,
    pipe_rx3_elec_idle_o,
    pipe_rx4_valid_o,
    pipe_rx4_chanisaligned_o,
    pipe_rx4_phy_status_o,
    pipe_rx4_elec_idle_o,
    pipe_rx5_valid_o,
    pipe_rx5_chanisaligned_o,
    pipe_rx5_phy_status_o,
    pipe_rx5_elec_idle_o,
    pipe_rx6_valid_o,
    pipe_rx6_chanisaligned_o,
    pipe_rx6_phy_status_o,
    pipe_rx6_elec_idle_o,
    pipe_rx7_valid_o,
    pipe_rx7_chanisaligned_o,
    pipe_rx7_phy_status_o,
    pipe_rx7_elec_idle_o,
    \cplllock_reg1_reg[3] ,
    \cplllock_reg1_reg[2] ,
    \cplllock_reg1_reg[6] ,
    Q,
    \cplllock_reg1_reg[3]_0 ,
    TXMARGIN,
    PIPE_TXMARGIN,
    \ramb_bl.ramb36_dp_bl.ram36_bl ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_1 ,
    PIPE_TXDATAK,
    PIPE_TXDATA,
    PIPE_POWERDOWN,
    \ramb_bl.ramb36_dp_bl.ram36_bl_2 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_3 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_4 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_5 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_6 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_7 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_8 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_9 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_10 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_11 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_12 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_13 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_14 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_15 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_16 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_17 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_18 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_19 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_20 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_21 ,
    \ramb_bl.ramb36_dp_bl.ram36_bl_22 ,
    phy_rdy_n,
    pipe_tx_rcvr_det_i,
    CLK,
    pipe_tx_rate_i,
    pipe_tx_deemph_i,
    pipe_rx0_valid,
    PIPE_RXCHANISALIGNED,
    gt_rx_phy_status_q,
    gt_rxelecidle_q,
    pipe_rx0_polarity_i,
    pipe_rx1_polarity_i,
    pipe_rx2_polarity_i,
    pipe_rx3_polarity_i,
    pipe_rx4_polarity_i,
    pipe_rx5_polarity_i,
    pipe_rx6_polarity_i,
    pipe_rx7_polarity_i,
    pipe_tx0_compliance_i,
    pipe_tx1_compliance_i,
    pipe_tx2_compliance_i,
    pipe_tx3_compliance_i,
    pipe_tx4_compliance_i,
    pipe_tx5_compliance_i,
    pipe_tx6_compliance_i,
    pipe_tx7_compliance_i,
    pipe_tx0_elec_idle_i,
    pipe_tx1_elec_idle_i,
    pipe_tx2_elec_idle_i,
    pipe_tx3_elec_idle_i,
    pipe_tx4_elec_idle_i,
    pipe_tx5_elec_idle_i,
    pipe_tx6_elec_idle_i,
    pipe_tx7_elec_idle_i,
    pipe_rx1_valid,
    gt_rx_phy_status_q_reg,
    gt_rxelecidle_q_reg,
    pipe_rx2_valid,
    gt_rx_phy_status_q_reg_0,
    gt_rxelecidle_q_reg_0,
    pipe_rx3_valid,
    gt_rx_phy_status_q_reg_1,
    gt_rxelecidle_q_reg_1,
    pipe_rx4_valid,
    gt_rx_phy_status_q_reg_2,
    gt_rxelecidle_q_reg_2,
    pipe_rx5_valid,
    gt_rx_phy_status_q_reg_3,
    gt_rxelecidle_q_reg_3,
    pipe_rx6_valid,
    gt_rx_phy_status_q_reg_4,
    gt_rxelecidle_q_reg_4,
    pipe_rx7_valid,
    gt_rx_phy_status_q_reg_5,
    gt_rxelecidle_q_reg_5,
    pipe_tx_margin,
    D,
    \gt_rxdata_q_reg[15] ,
    \gt_rx_status_q_reg[2] ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_3 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_4 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_5 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_6 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_7 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_8 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_9 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_10 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_11 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_12 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_13 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_14 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_15 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_16 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_17 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_18 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_19 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_20 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_21 ,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg_22 ,
    \gt_rxcharisk_q_reg[1] ,
    \gt_rxdata_q_reg[15]_0 ,
    \gt_rx_status_q_reg[2]_0 ,
    \gt_rxcharisk_q_reg[1]_0 ,
    \gt_rxdata_q_reg[15]_1 ,
    \gt_rx_status_q_reg[2]_1 ,
    \gt_rxcharisk_q_reg[1]_1 ,
    \gt_rxdata_q_reg[15]_2 ,
    \gt_rx_status_q_reg[2]_2 ,
    \gt_rxcharisk_q_reg[1]_2 ,
    \gt_rxdata_q_reg[15]_3 ,
    \gt_rx_status_q_reg[2]_3 ,
    \gt_rxcharisk_q_reg[1]_3 ,
    \gt_rxdata_q_reg[15]_4 ,
    \gt_rx_status_q_reg[2]_4 ,
    \gt_rxcharisk_q_reg[1]_4 ,
    \gt_rxdata_q_reg[15]_5 ,
    \gt_rx_status_q_reg[2]_5 ,
    \gt_rxcharisk_q_reg[1]_5 ,
    \gt_rxdata_q_reg[15]_6 ,
    \gt_rx_status_q_reg[2]_6 );
  output pipe_tx_rcvr_det;
  output [0:0]\rate_reg1_reg[0] ;
  output [3:0]PIPE_TXDEEMPH;
  output pipe_rx0_valid_o;
  output pipe_rx0_chanisaligned_o;
  output pipe_rx0_phy_status_o;
  output pipe_rx0_elec_idle_o;
  output [7:0]PIPE_RXPOLARITY;
  output [7:0]PIPE_TXCOMPLIANCE;
  output [7:0]PIPE_TXELECIDLE;
  output pipe_rx1_valid_o;
  output pipe_rx1_chanisaligned_o;
  output pipe_rx1_phy_status_o;
  output pipe_rx1_elec_idle_o;
  output pipe_rx2_valid_o;
  output pipe_rx2_chanisaligned_o;
  output pipe_rx2_phy_status_o;
  output pipe_rx2_elec_idle_o;
  output pipe_rx3_valid_o;
  output pipe_rx3_chanisaligned_o;
  output pipe_rx3_phy_status_o;
  output pipe_rx3_elec_idle_o;
  output pipe_rx4_valid_o;
  output pipe_rx4_chanisaligned_o;
  output pipe_rx4_phy_status_o;
  output pipe_rx4_elec_idle_o;
  output pipe_rx5_valid_o;
  output pipe_rx5_chanisaligned_o;
  output pipe_rx5_phy_status_o;
  output pipe_rx5_elec_idle_o;
  output pipe_rx6_valid_o;
  output pipe_rx6_chanisaligned_o;
  output pipe_rx6_phy_status_o;
  output pipe_rx6_elec_idle_o;
  output pipe_rx7_valid_o;
  output pipe_rx7_chanisaligned_o;
  output pipe_rx7_phy_status_o;
  output pipe_rx7_elec_idle_o;
  output \cplllock_reg1_reg[3] ;
  output \cplllock_reg1_reg[2] ;
  output \cplllock_reg1_reg[6] ;
  output [2:0]Q;
  output [2:0]\cplllock_reg1_reg[3]_0 ;
  output [2:0]TXMARGIN;
  output [2:0]PIPE_TXMARGIN;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;
  output [15:0]PIPE_TXDATAK;
  output [127:0]PIPE_TXDATA;
  output [15:0]PIPE_POWERDOWN;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_2 ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_3 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_4 ;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_5 ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_6 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_7 ;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_8 ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_9 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_10 ;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_11 ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_12 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_13 ;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_14 ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_15 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_16 ;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_17 ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_18 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_19 ;
  output [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_20 ;
  output [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_21 ;
  output [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_22 ;
  input phy_rdy_n;
  input pipe_tx_rcvr_det_i;
  input CLK;
  input pipe_tx_rate_i;
  input pipe_tx_deemph_i;
  input pipe_rx0_valid;
  input [7:0]PIPE_RXCHANISALIGNED;
  input gt_rx_phy_status_q;
  input gt_rxelecidle_q;
  input pipe_rx0_polarity_i;
  input pipe_rx1_polarity_i;
  input pipe_rx2_polarity_i;
  input pipe_rx3_polarity_i;
  input pipe_rx4_polarity_i;
  input pipe_rx5_polarity_i;
  input pipe_rx6_polarity_i;
  input pipe_rx7_polarity_i;
  input pipe_tx0_compliance_i;
  input pipe_tx1_compliance_i;
  input pipe_tx2_compliance_i;
  input pipe_tx3_compliance_i;
  input pipe_tx4_compliance_i;
  input pipe_tx5_compliance_i;
  input pipe_tx6_compliance_i;
  input pipe_tx7_compliance_i;
  input pipe_tx0_elec_idle_i;
  input pipe_tx1_elec_idle_i;
  input pipe_tx2_elec_idle_i;
  input pipe_tx3_elec_idle_i;
  input pipe_tx4_elec_idle_i;
  input pipe_tx5_elec_idle_i;
  input pipe_tx6_elec_idle_i;
  input pipe_tx7_elec_idle_i;
  input pipe_rx1_valid;
  input gt_rx_phy_status_q_reg;
  input gt_rxelecidle_q_reg;
  input pipe_rx2_valid;
  input gt_rx_phy_status_q_reg_0;
  input gt_rxelecidle_q_reg_0;
  input pipe_rx3_valid;
  input gt_rx_phy_status_q_reg_1;
  input gt_rxelecidle_q_reg_1;
  input pipe_rx4_valid;
  input gt_rx_phy_status_q_reg_2;
  input gt_rxelecidle_q_reg_2;
  input pipe_rx5_valid;
  input gt_rx_phy_status_q_reg_3;
  input gt_rxelecidle_q_reg_3;
  input pipe_rx6_valid;
  input gt_rx_phy_status_q_reg_4;
  input gt_rxelecidle_q_reg_4;
  input pipe_rx7_valid;
  input gt_rx_phy_status_q_reg_5;
  input gt_rxelecidle_q_reg_5;
  input [2:0]pipe_tx_margin;
  input [1:0]D;
  input [15:0]\gt_rxdata_q_reg[15] ;
  input [2:0]\gt_rx_status_q_reg[2] ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_3 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_4 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_5 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_6 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_7 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_8 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_9 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_10 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_11 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_12 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_13 ;
  input [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_14 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_15 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_16 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_17 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_18 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_19 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_20 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_21 ;
  input [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_22 ;
  input [1:0]\gt_rxcharisk_q_reg[1] ;
  input [15:0]\gt_rxdata_q_reg[15]_0 ;
  input [2:0]\gt_rx_status_q_reg[2]_0 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  input [15:0]\gt_rxdata_q_reg[15]_1 ;
  input [2:0]\gt_rx_status_q_reg[2]_1 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_1 ;
  input [15:0]\gt_rxdata_q_reg[15]_2 ;
  input [2:0]\gt_rx_status_q_reg[2]_2 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_2 ;
  input [15:0]\gt_rxdata_q_reg[15]_3 ;
  input [2:0]\gt_rx_status_q_reg[2]_3 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_3 ;
  input [15:0]\gt_rxdata_q_reg[15]_4 ;
  input [2:0]\gt_rx_status_q_reg[2]_4 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_4 ;
  input [15:0]\gt_rxdata_q_reg[15]_5 ;
  input [2:0]\gt_rx_status_q_reg[2]_5 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_5 ;
  input [15:0]\gt_rxdata_q_reg[15]_6 ;
  input [2:0]\gt_rx_status_q_reg[2]_6 ;

  wire CLK;
  wire [1:0]D;
  wire [15:0]PIPE_POWERDOWN;
  wire [7:0]PIPE_RXCHANISALIGNED;
  wire [7:0]PIPE_RXPOLARITY;
  wire [7:0]PIPE_TXCOMPLIANCE;
  wire [127:0]PIPE_TXDATA;
  wire [15:0]PIPE_TXDATAK;
  wire [3:0]PIPE_TXDEEMPH;
  wire [7:0]PIPE_TXELECIDLE;
  wire [2:0]PIPE_TXMARGIN;
  wire [2:0]Q;
  wire [2:0]TXMARGIN;
  wire \cplllock_reg1_reg[2] ;
  wire \cplllock_reg1_reg[3] ;
  wire [2:0]\cplllock_reg1_reg[3]_0 ;
  wire \cplllock_reg1_reg[6] ;
  wire gt_rx_phy_status_q;
  wire gt_rx_phy_status_q_reg;
  wire gt_rx_phy_status_q_reg_0;
  wire gt_rx_phy_status_q_reg_1;
  wire gt_rx_phy_status_q_reg_2;
  wire gt_rx_phy_status_q_reg_3;
  wire gt_rx_phy_status_q_reg_4;
  wire gt_rx_phy_status_q_reg_5;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [2:0]\gt_rx_status_q_reg[2]_0 ;
  wire [2:0]\gt_rx_status_q_reg[2]_1 ;
  wire [2:0]\gt_rx_status_q_reg[2]_2 ;
  wire [2:0]\gt_rx_status_q_reg[2]_3 ;
  wire [2:0]\gt_rx_status_q_reg[2]_4 ;
  wire [2:0]\gt_rx_status_q_reg[2]_5 ;
  wire [2:0]\gt_rx_status_q_reg[2]_6 ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_1 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_2 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_3 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_4 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_5 ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire [15:0]\gt_rxdata_q_reg[15]_0 ;
  wire [15:0]\gt_rxdata_q_reg[15]_1 ;
  wire [15:0]\gt_rxdata_q_reg[15]_2 ;
  wire [15:0]\gt_rxdata_q_reg[15]_3 ;
  wire [15:0]\gt_rxdata_q_reg[15]_4 ;
  wire [15:0]\gt_rxdata_q_reg[15]_5 ;
  wire [15:0]\gt_rxdata_q_reg[15]_6 ;
  wire gt_rxelecidle_q;
  wire gt_rxelecidle_q_reg;
  wire gt_rxelecidle_q_reg_0;
  wire gt_rxelecidle_q_reg_1;
  wire gt_rxelecidle_q_reg_2;
  wire gt_rxelecidle_q_reg_3;
  wire gt_rxelecidle_q_reg_4;
  wire gt_rxelecidle_q_reg_5;
  wire phy_rdy_n;
  wire pipe_rx0_chanisaligned_o;
  wire pipe_rx0_elec_idle_o;
  wire pipe_rx0_phy_status_o;
  wire pipe_rx0_polarity_i;
  wire pipe_rx0_valid;
  wire pipe_rx0_valid_o;
  wire pipe_rx1_chanisaligned_o;
  wire pipe_rx1_elec_idle_o;
  wire pipe_rx1_phy_status_o;
  wire pipe_rx1_polarity_i;
  wire pipe_rx1_valid;
  wire pipe_rx1_valid_o;
  wire pipe_rx2_chanisaligned_o;
  wire pipe_rx2_elec_idle_o;
  wire pipe_rx2_phy_status_o;
  wire pipe_rx2_polarity_i;
  wire pipe_rx2_valid;
  wire pipe_rx2_valid_o;
  wire pipe_rx3_chanisaligned_o;
  wire pipe_rx3_elec_idle_o;
  wire pipe_rx3_phy_status_o;
  wire pipe_rx3_polarity_i;
  wire pipe_rx3_valid;
  wire pipe_rx3_valid_o;
  wire pipe_rx4_chanisaligned_o;
  wire pipe_rx4_elec_idle_o;
  wire pipe_rx4_phy_status_o;
  wire pipe_rx4_polarity_i;
  wire pipe_rx4_valid;
  wire pipe_rx4_valid_o;
  wire pipe_rx5_chanisaligned_o;
  wire pipe_rx5_elec_idle_o;
  wire pipe_rx5_phy_status_o;
  wire pipe_rx5_polarity_i;
  wire pipe_rx5_valid;
  wire pipe_rx5_valid_o;
  wire pipe_rx6_chanisaligned_o;
  wire pipe_rx6_elec_idle_o;
  wire pipe_rx6_phy_status_o;
  wire pipe_rx6_polarity_i;
  wire pipe_rx6_valid;
  wire pipe_rx6_valid_o;
  wire pipe_rx7_chanisaligned_o;
  wire pipe_rx7_elec_idle_o;
  wire pipe_rx7_phy_status_o;
  wire pipe_rx7_polarity_i;
  wire pipe_rx7_valid;
  wire pipe_rx7_valid_o;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_10 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_11 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_12 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_13 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_14 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_15 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_16 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_17 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_18 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_19 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_20 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_21 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_22 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_3 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_4 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_5 ;
  wire [1:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_6 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_7 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_8 ;
  wire [15:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg_9 ;
  wire pipe_tx0_compliance_i;
  wire pipe_tx0_elec_idle_i;
  wire pipe_tx1_compliance_i;
  wire pipe_tx1_elec_idle_i;
  wire pipe_tx2_compliance_i;
  wire pipe_tx2_elec_idle_i;
  wire pipe_tx3_compliance_i;
  wire pipe_tx3_elec_idle_i;
  wire pipe_tx4_compliance_i;
  wire pipe_tx4_elec_idle_i;
  wire pipe_tx5_compliance_i;
  wire pipe_tx5_elec_idle_i;
  wire pipe_tx6_compliance_i;
  wire pipe_tx6_elec_idle_i;
  wire pipe_tx7_compliance_i;
  wire pipe_tx7_elec_idle_i;
  wire pipe_tx_deemph_i;
  wire [2:0]pipe_tx_margin;
  wire pipe_tx_rate_i;
  wire pipe_tx_rcvr_det;
  wire pipe_tx_rcvr_det_i;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_1 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_10 ;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_11 ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_12 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_13 ;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_14 ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_15 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_16 ;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_17 ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_18 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_19 ;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_2 ;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_20 ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_21 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_22 ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_3 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_4 ;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_5 ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_6 ;
  wire [2:0]\ramb_bl.ramb36_dp_bl.ram36_bl_7 ;
  wire [1:0]\ramb_bl.ramb36_dp_bl.ram36_bl_8 ;
  wire [15:0]\ramb_bl.ramb36_dp_bl.ram36_bl_9 ;
  wire [0:0]\rate_reg1_reg[0] ;

  PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane pipe_lane_0_i
       (.CLK(CLK),
        .D(D),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[1:0]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[0]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[0]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[0]),
        .PIPE_TXDATA(PIPE_TXDATA[15:0]),
        .PIPE_TXDATAK(PIPE_TXDATAK[1:0]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[0]),
        .gt_rx_phy_status_q(gt_rx_phy_status_q),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2] ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15] ),
        .gt_rxelecidle_q(gt_rxelecidle_q),
        .phy_rdy_n(phy_rdy_n),
        .pipe_rx0_chanisaligned_o(pipe_rx0_chanisaligned_o),
        .pipe_rx0_elec_idle_o(pipe_rx0_elec_idle_o),
        .pipe_rx0_phy_status_o(pipe_rx0_phy_status_o),
        .pipe_rx0_polarity_i(pipe_rx0_polarity_i),
        .pipe_rx0_valid(pipe_rx0_valid),
        .pipe_rx0_valid_o(pipe_rx0_valid_o),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_7 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_15 ),
        .pipe_tx0_compliance_i(pipe_tx0_compliance_i),
        .pipe_tx0_elec_idle_i(pipe_tx0_elec_idle_i),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl_0 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_1 (\ramb_bl.ramb36_dp_bl.ram36_bl_1 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_0 \pipe_lane_2.pipe_lane_1_i 
       (.CLK(CLK),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[3:2]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[1]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[1]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[1]),
        .PIPE_TXDATA(PIPE_TXDATA[31:16]),
        .PIPE_TXDATAK(PIPE_TXDATAK[3:2]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[1]),
        .gt_rx_phy_status_q_reg(gt_rx_phy_status_q_reg),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_0 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1] ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_0 ),
        .gt_rxelecidle_q_reg(gt_rxelecidle_q_reg),
        .phy_rdy_n(phy_rdy_n),
        .pipe_rx1_chanisaligned_o(pipe_rx1_chanisaligned_o),
        .pipe_rx1_elec_idle_o(pipe_rx1_elec_idle_o),
        .pipe_rx1_phy_status_o(pipe_rx1_phy_status_o),
        .pipe_rx1_polarity_i(pipe_rx1_polarity_i),
        .pipe_rx1_valid(pipe_rx1_valid),
        .pipe_rx1_valid_o(pipe_rx1_valid_o),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_8 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_16 ),
        .pipe_tx1_compliance_i(pipe_tx1_compliance_i),
        .pipe_tx1_elec_idle_i(pipe_tx1_elec_idle_i),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl_2 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl_3 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_1 (\ramb_bl.ramb36_dp_bl.ram36_bl_4 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_1 \pipe_lane_4.pipe_lane_2_i 
       (.CLK(CLK),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[5:4]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[2]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[2]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[2]),
        .PIPE_TXDATA(PIPE_TXDATA[47:32]),
        .PIPE_TXDATAK(PIPE_TXDATAK[5:4]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[2]),
        .gt_rx_phy_status_q_reg(gt_rx_phy_status_q_reg_0),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_1 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_0 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_1 ),
        .gt_rxelecidle_q_reg(gt_rxelecidle_q_reg_0),
        .phy_rdy_n(phy_rdy_n),
        .pipe_rx2_chanisaligned_o(pipe_rx2_chanisaligned_o),
        .pipe_rx2_elec_idle_o(pipe_rx2_elec_idle_o),
        .pipe_rx2_phy_status_o(pipe_rx2_phy_status_o),
        .pipe_rx2_polarity_i(pipe_rx2_polarity_i),
        .pipe_rx2_valid(pipe_rx2_valid),
        .pipe_rx2_valid_o(pipe_rx2_valid_o),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_9 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_17 ),
        .pipe_tx2_compliance_i(pipe_tx2_compliance_i),
        .pipe_tx2_elec_idle_i(pipe_tx2_elec_idle_i),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl_5 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl_6 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_1 (\ramb_bl.ramb36_dp_bl.ram36_bl_7 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_2 \pipe_lane_4.pipe_lane_3_i 
       (.CLK(CLK),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[7:6]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[3]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[3]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[3]),
        .PIPE_TXDATA(PIPE_TXDATA[63:48]),
        .PIPE_TXDATAK(PIPE_TXDATAK[7:6]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[3]),
        .gt_rx_phy_status_q_reg(gt_rx_phy_status_q_reg_1),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_2 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_1 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_2 ),
        .gt_rxelecidle_q_reg(gt_rxelecidle_q_reg_1),
        .phy_rdy_n(phy_rdy_n),
        .pipe_rx3_chanisaligned_o(pipe_rx3_chanisaligned_o),
        .pipe_rx3_elec_idle_o(pipe_rx3_elec_idle_o),
        .pipe_rx3_phy_status_o(pipe_rx3_phy_status_o),
        .pipe_rx3_polarity_i(pipe_rx3_polarity_i),
        .pipe_rx3_valid(pipe_rx3_valid),
        .pipe_rx3_valid_o(pipe_rx3_valid_o),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_10 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_18 ),
        .pipe_tx3_compliance_i(pipe_tx3_compliance_i),
        .pipe_tx3_elec_idle_i(pipe_tx3_elec_idle_i),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl_8 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl_9 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_1 (\ramb_bl.ramb36_dp_bl.ram36_bl_10 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_3 \pipe_lane_8.pipe_lane_4_i 
       (.CLK(CLK),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[9:8]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[4]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[4]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[4]),
        .PIPE_TXDATA(PIPE_TXDATA[79:64]),
        .PIPE_TXDATAK(PIPE_TXDATAK[9:8]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[4]),
        .gt_rx_phy_status_q_reg(gt_rx_phy_status_q_reg_2),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_3 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_2 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_3 ),
        .gt_rxelecidle_q_reg(gt_rxelecidle_q_reg_2),
        .phy_rdy_n(phy_rdy_n),
        .pipe_rx4_chanisaligned_o(pipe_rx4_chanisaligned_o),
        .pipe_rx4_elec_idle_o(pipe_rx4_elec_idle_o),
        .pipe_rx4_phy_status_o(pipe_rx4_phy_status_o),
        .pipe_rx4_polarity_i(pipe_rx4_polarity_i),
        .pipe_rx4_valid(pipe_rx4_valid),
        .pipe_rx4_valid_o(pipe_rx4_valid_o),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_3 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_11 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_19 ),
        .pipe_tx4_compliance_i(pipe_tx4_compliance_i),
        .pipe_tx4_elec_idle_i(pipe_tx4_elec_idle_i),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl_11 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl_12 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_1 (\ramb_bl.ramb36_dp_bl.ram36_bl_13 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_4 \pipe_lane_8.pipe_lane_5_i 
       (.CLK(CLK),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[11:10]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[5]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[5]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[5]),
        .PIPE_TXDATA(PIPE_TXDATA[95:80]),
        .PIPE_TXDATAK(PIPE_TXDATAK[11:10]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[5]),
        .gt_rx_phy_status_q_reg(gt_rx_phy_status_q_reg_3),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_4 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_3 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_4 ),
        .gt_rxelecidle_q_reg(gt_rxelecidle_q_reg_3),
        .phy_rdy_n(phy_rdy_n),
        .pipe_rx5_chanisaligned_o(pipe_rx5_chanisaligned_o),
        .pipe_rx5_elec_idle_o(pipe_rx5_elec_idle_o),
        .pipe_rx5_phy_status_o(pipe_rx5_phy_status_o),
        .pipe_rx5_polarity_i(pipe_rx5_polarity_i),
        .pipe_rx5_valid(pipe_rx5_valid),
        .pipe_rx5_valid_o(pipe_rx5_valid_o),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_4 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_12 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_20 ),
        .pipe_tx5_compliance_i(pipe_tx5_compliance_i),
        .pipe_tx5_elec_idle_i(pipe_tx5_elec_idle_i),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl_14 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl_15 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_1 (\ramb_bl.ramb36_dp_bl.ram36_bl_16 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_5 \pipe_lane_8.pipe_lane_6_i 
       (.CLK(CLK),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[13:12]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[6]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[6]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[6]),
        .PIPE_TXDATA(PIPE_TXDATA[111:96]),
        .PIPE_TXDATAK(PIPE_TXDATAK[13:12]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[6]),
        .gt_rx_phy_status_q_reg(gt_rx_phy_status_q_reg_4),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_5 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_4 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_5 ),
        .gt_rxelecidle_q_reg(gt_rxelecidle_q_reg_4),
        .phy_rdy_n(phy_rdy_n),
        .pipe_rx6_chanisaligned_o(pipe_rx6_chanisaligned_o),
        .pipe_rx6_elec_idle_o(pipe_rx6_elec_idle_o),
        .pipe_rx6_phy_status_o(pipe_rx6_phy_status_o),
        .pipe_rx6_polarity_i(pipe_rx6_polarity_i),
        .pipe_rx6_valid(pipe_rx6_valid),
        .pipe_rx6_valid_o(pipe_rx6_valid_o),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_5 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_13 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_21 ),
        .pipe_tx6_compliance_i(pipe_tx6_compliance_i),
        .pipe_tx6_elec_idle_i(pipe_tx6_elec_idle_i),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl_17 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl_18 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_1 (\ramb_bl.ramb36_dp_bl.ram36_bl_19 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_lane_6 \pipe_lane_8.pipe_lane_7_i 
       (.CLK(CLK),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[15:14]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[7]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[7]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[7]),
        .PIPE_TXDATA(PIPE_TXDATA[127:112]),
        .PIPE_TXDATAK(PIPE_TXDATAK[15:14]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[7]),
        .gt_rx_phy_status_q_reg(gt_rx_phy_status_q_reg_5),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_6 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_5 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_6 ),
        .gt_rxelecidle_q_reg(gt_rxelecidle_q_reg_5),
        .phy_rdy_n(phy_rdy_n),
        .pipe_rx7_chanisaligned_o(pipe_rx7_chanisaligned_o),
        .pipe_rx7_elec_idle_o(pipe_rx7_elec_idle_o),
        .pipe_rx7_phy_status_o(pipe_rx7_phy_status_o),
        .pipe_rx7_polarity_i(pipe_rx7_polarity_i),
        .pipe_rx7_valid(pipe_rx7_valid),
        .pipe_rx7_valid_o(pipe_rx7_valid_o),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_6 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_14 ),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 (\pipe_stages_1.pipe_rx_chanisaligned_q_reg_22 ),
        .pipe_tx7_compliance_i(pipe_tx7_compliance_i),
        .pipe_tx7_elec_idle_i(pipe_tx7_elec_idle_i),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (\ramb_bl.ramb36_dp_bl.ram36_bl_20 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (\ramb_bl.ramb36_dp_bl.ram36_bl_21 ),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_1 (\ramb_bl.ramb36_dp_bl.ram36_bl_22 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_misc pipe_misc_i
       (.CLK(CLK),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH),
        .PIPE_TXMARGIN(PIPE_TXMARGIN),
        .Q(Q),
        .TXMARGIN(TXMARGIN),
        .\cplllock_reg1_reg[2] (\cplllock_reg1_reg[2] ),
        .\cplllock_reg1_reg[3] (\cplllock_reg1_reg[3] ),
        .\cplllock_reg1_reg[3]_0 (\cplllock_reg1_reg[3]_0 ),
        .\cplllock_reg1_reg[6] (\cplllock_reg1_reg[6] ),
        .phy_rdy_n(phy_rdy_n),
        .pipe_tx_deemph_i(pipe_tx_deemph_i),
        .pipe_tx_margin(pipe_tx_margin),
        .pipe_tx_rate_i(pipe_tx_rate_i),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det),
        .pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
        .\rate_reg1_reg[0] (\rate_reg1_reg[0] ));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pcie_top" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pcie_top
   (m_axis_rx_tvalid,
    m_axis_rx_tlast,
    trn_tcfg_req,
    s_axis_tx_tready,
    pipe_tx_rcvr_det,
    \rate_reg1_reg[0] ,
    PIPE_TXDEEMPH,
    PIPE_RXPOLARITY,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    \cplllock_reg1_reg[3] ,
    \cplllock_reg1_reg[2] ,
    \cplllock_reg1_reg[6] ,
    user_reset_int_reg,
    trn_tbuf_av,
    cfg_pcie_link_state,
    cfg_mgmt_rd_wr_done,
    cfg_err_aer_headerlog_set,
    cfg_err_cpl_rdy,
    cfg_interrupt_rdy,
    cfg_msg_received,
    cfg_received_func_lvl_rst,
    pl_phy_lnk_up_q_reg,
    m_axis_rx_tdata,
    m_axis_rx_tkeep,
    m_axis_rx_tuser,
    cfg_to_turnoff,
    cfg_bus_number,
    cfg_msg_data,
    cfg_device_number,
    cfg_function_number,
    Q,
    \cplllock_reg1_reg[3]_0 ,
    TXMARGIN,
    PIPE_TXMARGIN,
    PIPE_TXDATAK,
    PIPE_TXDATA,
    PIPE_POWERDOWN,
    cfg_aer_ecrc_check_en,
    cfg_aer_ecrc_gen_en,
    cfg_aer_rooterr_corr_err_received,
    cfg_aer_rooterr_corr_err_reporting_en,
    cfg_aer_rooterr_fatal_err_received,
    cfg_aer_rooterr_fatal_err_reporting_en,
    cfg_aer_rooterr_non_fatal_err_received,
    cfg_aer_rooterr_non_fatal_err_reporting_en,
    cfg_bridge_serr_en,
    cfg_command,
    cfg_dcommand2,
    cfg_dcommand,
    cfg_dstatus,
    cfg_interrupt_msienable,
    cfg_interrupt_msixenable,
    cfg_interrupt_msixfm,
    cfg_lcommand,
    cfg_lstatus,
    cfg_msg_received_assert_int_a,
    cfg_msg_received_assert_int_b,
    cfg_msg_received_assert_int_c,
    cfg_msg_received_assert_int_d,
    cfg_msg_received_deassert_int_a,
    cfg_msg_received_deassert_int_b,
    cfg_msg_received_deassert_int_c,
    cfg_msg_received_deassert_int_d,
    cfg_msg_received_err_cor,
    cfg_msg_received_err_fatal,
    cfg_msg_received_err_non_fatal,
    cfg_msg_received_pm_as_nak,
    cfg_msg_received_pme_to_ack,
    cfg_msg_received_pm_pme,
    cfg_msg_received_setslotpowerlimit,
    cfg_pmcsr_pme_en,
    cfg_pmcsr_pme_status,
    cfg_root_control_pme_int_en,
    cfg_root_control_syserr_corr_err_en,
    cfg_root_control_syserr_fatal_err_en,
    cfg_root_control_syserr_non_fatal_err_en,
    cfg_slot_control_electromech_il_ctl_pulse,
    pcie_drp_rdy,
    pl_directed_change_done,
    pl_link_gen2_cap,
    pl_link_partner_gen2_supported,
    pl_link_upcfg_cap,
    pl_received_hot_rst,
    pl_sel_lnk_rate,
    trn_lnk_up,
    tx_err_drop,
    fc_cpld,
    fc_npd,
    fc_pd,
    pcie_drp_do,
    cfg_pmcsr_powerstate,
    pl_lane_reversal_mode,
    pl_rx_pm_state,
    pl_sel_lnk_width,
    cfg_interrupt_mmenable,
    pl_initial_link_width,
    pl_tx_pm_state,
    cfg_mgmt_do,
    pl_ltssm_state,
    cfg_vc_tcvc_map,
    cfg_interrupt_do,
    fc_cplh,
    fc_nph,
    fc_ph,
    user_reset_out_reg,
    user_clk,
    s_axis_tx_tlast,
    s_axis_tx_tvalid,
    s_axis_tx_tkeep,
    tx_cfg_gnt,
    cfg_turnoff_ok,
    phy_rdy_n,
    CLK,
    pipe_rx0_valid,
    PIPE_RXCHANISALIGNED,
    gt_rx_phy_status_q,
    gt_rxelecidle_q,
    pipe_rx1_valid,
    gt_rx_phy_status_q_reg,
    gt_rxelecidle_q_reg,
    pipe_rx2_valid,
    gt_rx_phy_status_q_reg_0,
    gt_rxelecidle_q_reg_0,
    pipe_rx3_valid,
    gt_rx_phy_status_q_reg_1,
    gt_rxelecidle_q_reg_1,
    pipe_rx4_valid,
    gt_rx_phy_status_q_reg_2,
    gt_rxelecidle_q_reg_2,
    pipe_rx5_valid,
    gt_rx_phy_status_q_reg_3,
    gt_rxelecidle_q_reg_3,
    pipe_rx6_valid,
    gt_rx_phy_status_q_reg_4,
    gt_rxelecidle_q_reg_4,
    pipe_rx7_valid,
    gt_rx_phy_status_q_reg_5,
    gt_rxelecidle_q_reg_5,
    bridge_reset_int,
    pl_phy_lnk_up,
    m_axis_rx_tready,
    s_axis_tx_tuser,
    s_axis_tx_tdata,
    user_lnk_up_int_reg,
    cfg_trn_pending,
    cfg_mgmt_wr_rw1c_as_rw,
    cfg_mgmt_wr_readonly,
    cfg_mgmt_wr_en,
    cfg_mgmt_rd_en,
    cfg_err_malformed,
    cfg_err_cor,
    cfg_err_ur,
    cfg_err_ecrc,
    cfg_err_cpl_timeout,
    cfg_err_cpl_abort,
    cfg_err_cpl_unexpect,
    cfg_err_poisoned,
    cfg_err_atomic_egress_blocked,
    cfg_err_mc_blocked,
    cfg_err_internal_uncor,
    cfg_err_internal_cor,
    cfg_err_posted,
    cfg_err_locked,
    cfg_err_norecovery,
    cfg_interrupt,
    cfg_interrupt_assert,
    cfg_interrupt_stat,
    cfg_pm_halt_aspm_l0s,
    cfg_pm_halt_aspm_l1,
    cfg_pm_force_state_en,
    cfg_pm_wake,
    D,
    \gt_rxdata_q_reg[15] ,
    \gt_rx_status_q_reg[2] ,
    \gt_rxcharisk_q_reg[1] ,
    \gt_rxdata_q_reg[15]_0 ,
    \gt_rx_status_q_reg[2]_0 ,
    \gt_rxcharisk_q_reg[1]_0 ,
    \gt_rxdata_q_reg[15]_1 ,
    \gt_rx_status_q_reg[2]_1 ,
    \gt_rxcharisk_q_reg[1]_1 ,
    \gt_rxdata_q_reg[15]_2 ,
    \gt_rx_status_q_reg[2]_2 ,
    \gt_rxcharisk_q_reg[1]_2 ,
    \gt_rxdata_q_reg[15]_3 ,
    \gt_rx_status_q_reg[2]_3 ,
    \gt_rxcharisk_q_reg[1]_3 ,
    \gt_rxdata_q_reg[15]_4 ,
    \gt_rx_status_q_reg[2]_4 ,
    \gt_rxcharisk_q_reg[1]_4 ,
    \gt_rxdata_q_reg[15]_5 ,
    \gt_rx_status_q_reg[2]_5 ,
    \gt_rxcharisk_q_reg[1]_5 ,
    \gt_rxdata_q_reg[15]_6 ,
    \gt_rx_status_q_reg[2]_6 ,
    pcie_drp_clk,
    pcie_drp_en,
    pcie_drp_we,
    pl_directed_link_auton,
    pl_directed_link_speed,
    pl_downstream_deemph_source,
    pl_transmit_hot_rst,
    pl_upstream_prefer_deemph,
    sys_rst_n,
    rx_np_ok,
    rx_np_req,
    cfg_err_aer_headerlog,
    pcie_drp_di,
    cfg_pm_force_state,
    pl_directed_link_change,
    pl_directed_link_width,
    cfg_ds_function_number,
    fc_sel,
    cfg_mgmt_di,
    cfg_mgmt_byte_en_n,
    cfg_err_tlp_cpl_header,
    cfg_aer_interrupt_msgnum,
    cfg_ds_device_number,
    cfg_pciecap_interrupt_msgnum,
    cfg_dsn,
    cfg_ds_bus_number,
    cfg_interrupt_di,
    pcie_drp_addr,
    cfg_mgmt_dwaddr);
  output m_axis_rx_tvalid;
  output m_axis_rx_tlast;
  output trn_tcfg_req;
  output s_axis_tx_tready;
  output pipe_tx_rcvr_det;
  output [0:0]\rate_reg1_reg[0] ;
  output [3:0]PIPE_TXDEEMPH;
  output [7:0]PIPE_RXPOLARITY;
  output [7:0]PIPE_TXCOMPLIANCE;
  output [7:0]PIPE_TXELECIDLE;
  output \cplllock_reg1_reg[3] ;
  output \cplllock_reg1_reg[2] ;
  output \cplllock_reg1_reg[6] ;
  output user_reset_int_reg;
  output [5:0]trn_tbuf_av;
  output [2:0]cfg_pcie_link_state;
  output cfg_mgmt_rd_wr_done;
  output cfg_err_aer_headerlog_set;
  output cfg_err_cpl_rdy;
  output cfg_interrupt_rdy;
  output cfg_msg_received;
  output cfg_received_func_lvl_rst;
  output pl_phy_lnk_up_q_reg;
  output [63:0]m_axis_rx_tdata;
  output [7:0]m_axis_rx_tkeep;
  output [21:0]m_axis_rx_tuser;
  output cfg_to_turnoff;
  output [7:0]cfg_bus_number;
  output [15:0]cfg_msg_data;
  output [4:0]cfg_device_number;
  output [2:0]cfg_function_number;
  output [2:0]Q;
  output [2:0]\cplllock_reg1_reg[3]_0 ;
  output [2:0]TXMARGIN;
  output [2:0]PIPE_TXMARGIN;
  output [15:0]PIPE_TXDATAK;
  output [127:0]PIPE_TXDATA;
  output [15:0]PIPE_POWERDOWN;
  output cfg_aer_ecrc_check_en;
  output cfg_aer_ecrc_gen_en;
  output cfg_aer_rooterr_corr_err_received;
  output cfg_aer_rooterr_corr_err_reporting_en;
  output cfg_aer_rooterr_fatal_err_received;
  output cfg_aer_rooterr_fatal_err_reporting_en;
  output cfg_aer_rooterr_non_fatal_err_received;
  output cfg_aer_rooterr_non_fatal_err_reporting_en;
  output cfg_bridge_serr_en;
  output [4:0]cfg_command;
  output [11:0]cfg_dcommand2;
  output [14:0]cfg_dcommand;
  output [3:0]cfg_dstatus;
  output cfg_interrupt_msienable;
  output cfg_interrupt_msixenable;
  output cfg_interrupt_msixfm;
  output [10:0]cfg_lcommand;
  output [9:0]cfg_lstatus;
  output cfg_msg_received_assert_int_a;
  output cfg_msg_received_assert_int_b;
  output cfg_msg_received_assert_int_c;
  output cfg_msg_received_assert_int_d;
  output cfg_msg_received_deassert_int_a;
  output cfg_msg_received_deassert_int_b;
  output cfg_msg_received_deassert_int_c;
  output cfg_msg_received_deassert_int_d;
  output cfg_msg_received_err_cor;
  output cfg_msg_received_err_fatal;
  output cfg_msg_received_err_non_fatal;
  output cfg_msg_received_pm_as_nak;
  output cfg_msg_received_pme_to_ack;
  output cfg_msg_received_pm_pme;
  output cfg_msg_received_setslotpowerlimit;
  output cfg_pmcsr_pme_en;
  output cfg_pmcsr_pme_status;
  output cfg_root_control_pme_int_en;
  output cfg_root_control_syserr_corr_err_en;
  output cfg_root_control_syserr_fatal_err_en;
  output cfg_root_control_syserr_non_fatal_err_en;
  output cfg_slot_control_electromech_il_ctl_pulse;
  output pcie_drp_rdy;
  output pl_directed_change_done;
  output pl_link_gen2_cap;
  output pl_link_partner_gen2_supported;
  output pl_link_upcfg_cap;
  output pl_received_hot_rst;
  output pl_sel_lnk_rate;
  output trn_lnk_up;
  output tx_err_drop;
  output [11:0]fc_cpld;
  output [11:0]fc_npd;
  output [11:0]fc_pd;
  output [15:0]pcie_drp_do;
  output [1:0]cfg_pmcsr_powerstate;
  output [1:0]pl_lane_reversal_mode;
  output [1:0]pl_rx_pm_state;
  output [1:0]pl_sel_lnk_width;
  output [2:0]cfg_interrupt_mmenable;
  output [2:0]pl_initial_link_width;
  output [2:0]pl_tx_pm_state;
  output [31:0]cfg_mgmt_do;
  output [5:0]pl_ltssm_state;
  output [6:0]cfg_vc_tcvc_map;
  output [7:0]cfg_interrupt_do;
  output [7:0]fc_cplh;
  output [7:0]fc_nph;
  output [7:0]fc_ph;
  input user_reset_out_reg;
  input user_clk;
  input s_axis_tx_tlast;
  input s_axis_tx_tvalid;
  input [0:0]s_axis_tx_tkeep;
  input tx_cfg_gnt;
  input cfg_turnoff_ok;
  input phy_rdy_n;
  input CLK;
  input pipe_rx0_valid;
  input [7:0]PIPE_RXCHANISALIGNED;
  input gt_rx_phy_status_q;
  input gt_rxelecidle_q;
  input pipe_rx1_valid;
  input gt_rx_phy_status_q_reg;
  input gt_rxelecidle_q_reg;
  input pipe_rx2_valid;
  input gt_rx_phy_status_q_reg_0;
  input gt_rxelecidle_q_reg_0;
  input pipe_rx3_valid;
  input gt_rx_phy_status_q_reg_1;
  input gt_rxelecidle_q_reg_1;
  input pipe_rx4_valid;
  input gt_rx_phy_status_q_reg_2;
  input gt_rxelecidle_q_reg_2;
  input pipe_rx5_valid;
  input gt_rx_phy_status_q_reg_3;
  input gt_rxelecidle_q_reg_3;
  input pipe_rx6_valid;
  input gt_rx_phy_status_q_reg_4;
  input gt_rxelecidle_q_reg_4;
  input pipe_rx7_valid;
  input gt_rx_phy_status_q_reg_5;
  input gt_rxelecidle_q_reg_5;
  input bridge_reset_int;
  input pl_phy_lnk_up;
  input m_axis_rx_tready;
  input [3:0]s_axis_tx_tuser;
  input [63:0]s_axis_tx_tdata;
  input user_lnk_up_int_reg;
  input cfg_trn_pending;
  input cfg_mgmt_wr_rw1c_as_rw;
  input cfg_mgmt_wr_readonly;
  input cfg_mgmt_wr_en;
  input cfg_mgmt_rd_en;
  input cfg_err_malformed;
  input cfg_err_cor;
  input cfg_err_ur;
  input cfg_err_ecrc;
  input cfg_err_cpl_timeout;
  input cfg_err_cpl_abort;
  input cfg_err_cpl_unexpect;
  input cfg_err_poisoned;
  input cfg_err_atomic_egress_blocked;
  input cfg_err_mc_blocked;
  input cfg_err_internal_uncor;
  input cfg_err_internal_cor;
  input cfg_err_posted;
  input cfg_err_locked;
  input cfg_err_norecovery;
  input cfg_interrupt;
  input cfg_interrupt_assert;
  input cfg_interrupt_stat;
  input cfg_pm_halt_aspm_l0s;
  input cfg_pm_halt_aspm_l1;
  input cfg_pm_force_state_en;
  input cfg_pm_wake;
  input [1:0]D;
  input [15:0]\gt_rxdata_q_reg[15] ;
  input [2:0]\gt_rx_status_q_reg[2] ;
  input [1:0]\gt_rxcharisk_q_reg[1] ;
  input [15:0]\gt_rxdata_q_reg[15]_0 ;
  input [2:0]\gt_rx_status_q_reg[2]_0 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  input [15:0]\gt_rxdata_q_reg[15]_1 ;
  input [2:0]\gt_rx_status_q_reg[2]_1 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_1 ;
  input [15:0]\gt_rxdata_q_reg[15]_2 ;
  input [2:0]\gt_rx_status_q_reg[2]_2 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_2 ;
  input [15:0]\gt_rxdata_q_reg[15]_3 ;
  input [2:0]\gt_rx_status_q_reg[2]_3 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_3 ;
  input [15:0]\gt_rxdata_q_reg[15]_4 ;
  input [2:0]\gt_rx_status_q_reg[2]_4 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_4 ;
  input [15:0]\gt_rxdata_q_reg[15]_5 ;
  input [2:0]\gt_rx_status_q_reg[2]_5 ;
  input [1:0]\gt_rxcharisk_q_reg[1]_5 ;
  input [15:0]\gt_rxdata_q_reg[15]_6 ;
  input [2:0]\gt_rx_status_q_reg[2]_6 ;
  input pcie_drp_clk;
  input pcie_drp_en;
  input pcie_drp_we;
  input pl_directed_link_auton;
  input pl_directed_link_speed;
  input pl_downstream_deemph_source;
  input pl_transmit_hot_rst;
  input pl_upstream_prefer_deemph;
  input sys_rst_n;
  input rx_np_ok;
  input rx_np_req;
  input [127:0]cfg_err_aer_headerlog;
  input [15:0]pcie_drp_di;
  input [1:0]cfg_pm_force_state;
  input [1:0]pl_directed_link_change;
  input [1:0]pl_directed_link_width;
  input [2:0]cfg_ds_function_number;
  input [2:0]fc_sel;
  input [31:0]cfg_mgmt_di;
  input [3:0]cfg_mgmt_byte_en_n;
  input [47:0]cfg_err_tlp_cpl_header;
  input [4:0]cfg_aer_interrupt_msgnum;
  input [4:0]cfg_ds_device_number;
  input [4:0]cfg_pciecap_interrupt_msgnum;
  input [63:0]cfg_dsn;
  input [7:0]cfg_ds_bus_number;
  input [7:0]cfg_interrupt_di;
  input [8:0]pcie_drp_addr;
  input [9:0]cfg_mgmt_dwaddr;

  wire CLK;
  wire [1:0]D;
  wire [15:0]PIPE_POWERDOWN;
  wire [7:0]PIPE_RXCHANISALIGNED;
  wire [7:0]PIPE_RXPOLARITY;
  wire [7:0]PIPE_TXCOMPLIANCE;
  wire [127:0]PIPE_TXDATA;
  wire [15:0]PIPE_TXDATAK;
  wire [3:0]PIPE_TXDEEMPH;
  wire [7:0]PIPE_TXELECIDLE;
  wire [2:0]PIPE_TXMARGIN;
  wire [2:0]Q;
  wire [2:0]TXMARGIN;
  wire axi_basic_top_i_n_7;
  wire axi_basic_top_i_n_8;
  wire axi_basic_top_i_n_9;
  wire bridge_reset_int;
  wire cfg_aer_ecrc_check_en;
  wire cfg_aer_ecrc_gen_en;
  wire [4:0]cfg_aer_interrupt_msgnum;
  wire cfg_aer_rooterr_corr_err_received;
  wire cfg_aer_rooterr_corr_err_reporting_en;
  wire cfg_aer_rooterr_fatal_err_received;
  wire cfg_aer_rooterr_fatal_err_reporting_en;
  wire cfg_aer_rooterr_non_fatal_err_received;
  wire cfg_aer_rooterr_non_fatal_err_reporting_en;
  wire cfg_bridge_serr_en;
  wire [7:0]cfg_bus_number;
  wire [4:0]cfg_command;
  wire [14:0]cfg_dcommand;
  wire [11:0]cfg_dcommand2;
  wire [4:0]cfg_device_number;
  wire [7:0]cfg_ds_bus_number;
  wire [4:0]cfg_ds_device_number;
  wire [2:0]cfg_ds_function_number;
  wire [63:0]cfg_dsn;
  wire [3:0]cfg_dstatus;
  wire [127:0]cfg_err_aer_headerlog;
  wire cfg_err_aer_headerlog_set;
  wire cfg_err_atomic_egress_blocked;
  wire cfg_err_cor;
  wire cfg_err_cpl_abort;
  wire cfg_err_cpl_rdy;
  wire cfg_err_cpl_timeout;
  wire cfg_err_cpl_unexpect;
  wire cfg_err_ecrc;
  wire cfg_err_internal_cor;
  wire cfg_err_internal_uncor;
  wire cfg_err_locked;
  wire cfg_err_malformed;
  wire cfg_err_mc_blocked;
  wire cfg_err_norecovery;
  wire cfg_err_poisoned;
  wire cfg_err_posted;
  wire [47:0]cfg_err_tlp_cpl_header;
  wire cfg_err_ur;
  wire [2:0]cfg_function_number;
  wire cfg_interrupt;
  wire cfg_interrupt_assert;
  wire [7:0]cfg_interrupt_di;
  wire [7:0]cfg_interrupt_do;
  wire [2:0]cfg_interrupt_mmenable;
  wire cfg_interrupt_msienable;
  wire cfg_interrupt_msixenable;
  wire cfg_interrupt_msixfm;
  wire cfg_interrupt_rdy;
  wire cfg_interrupt_stat;
  wire [10:0]cfg_lcommand;
  wire [9:0]cfg_lstatus;
  wire [3:0]cfg_mgmt_byte_en_n;
  wire [31:0]cfg_mgmt_di;
  wire [31:0]cfg_mgmt_do;
  wire [9:0]cfg_mgmt_dwaddr;
  wire cfg_mgmt_rd_en;
  wire cfg_mgmt_rd_wr_done;
  wire cfg_mgmt_wr_en;
  wire cfg_mgmt_wr_readonly;
  wire cfg_mgmt_wr_rw1c_as_rw;
  wire [15:0]cfg_msg_data;
  wire cfg_msg_received;
  wire cfg_msg_received_assert_int_a;
  wire cfg_msg_received_assert_int_b;
  wire cfg_msg_received_assert_int_c;
  wire cfg_msg_received_assert_int_d;
  wire cfg_msg_received_deassert_int_a;
  wire cfg_msg_received_deassert_int_b;
  wire cfg_msg_received_deassert_int_c;
  wire cfg_msg_received_deassert_int_d;
  wire cfg_msg_received_err_cor;
  wire cfg_msg_received_err_fatal;
  wire cfg_msg_received_err_non_fatal;
  wire cfg_msg_received_pm_as_nak;
  wire cfg_msg_received_pm_pme;
  wire cfg_msg_received_pme_to_ack;
  wire cfg_msg_received_setslotpowerlimit;
  wire [2:0]cfg_pcie_link_state;
  wire [4:0]cfg_pciecap_interrupt_msgnum;
  wire [1:0]cfg_pm_force_state;
  wire cfg_pm_force_state_en;
  wire cfg_pm_halt_aspm_l0s;
  wire cfg_pm_halt_aspm_l1;
  wire cfg_pm_turnoff_ok_n;
  wire cfg_pm_wake;
  wire cfg_pmcsr_pme_en;
  wire cfg_pmcsr_pme_status;
  wire [1:0]cfg_pmcsr_powerstate;
  wire cfg_received_func_lvl_rst;
  wire cfg_root_control_pme_int_en;
  wire cfg_root_control_syserr_corr_err_en;
  wire cfg_root_control_syserr_fatal_err_en;
  wire cfg_root_control_syserr_non_fatal_err_en;
  wire cfg_slot_control_electromech_il_ctl_pulse;
  wire cfg_to_turnoff;
  wire cfg_trn_pending;
  wire cfg_turnoff_ok;
  wire [6:0]cfg_vc_tcvc_map;
  wire \cplllock_reg1_reg[2] ;
  wire \cplllock_reg1_reg[3] ;
  wire [2:0]\cplllock_reg1_reg[3]_0 ;
  wire \cplllock_reg1_reg[6] ;
  wire [11:0]fc_cpld;
  wire [7:0]fc_cplh;
  wire [11:0]fc_npd;
  wire [7:0]fc_nph;
  wire [11:0]fc_pd;
  wire [7:0]fc_ph;
  wire [2:0]fc_sel;
  wire gt_rx_phy_status_q;
  wire gt_rx_phy_status_q_reg;
  wire gt_rx_phy_status_q_reg_0;
  wire gt_rx_phy_status_q_reg_1;
  wire gt_rx_phy_status_q_reg_2;
  wire gt_rx_phy_status_q_reg_3;
  wire gt_rx_phy_status_q_reg_4;
  wire gt_rx_phy_status_q_reg_5;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [2:0]\gt_rx_status_q_reg[2]_0 ;
  wire [2:0]\gt_rx_status_q_reg[2]_1 ;
  wire [2:0]\gt_rx_status_q_reg[2]_2 ;
  wire [2:0]\gt_rx_status_q_reg[2]_3 ;
  wire [2:0]\gt_rx_status_q_reg[2]_4 ;
  wire [2:0]\gt_rx_status_q_reg[2]_5 ;
  wire [2:0]\gt_rx_status_q_reg[2]_6 ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_1 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_2 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_3 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_4 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_5 ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire [15:0]\gt_rxdata_q_reg[15]_0 ;
  wire [15:0]\gt_rxdata_q_reg[15]_1 ;
  wire [15:0]\gt_rxdata_q_reg[15]_2 ;
  wire [15:0]\gt_rxdata_q_reg[15]_3 ;
  wire [15:0]\gt_rxdata_q_reg[15]_4 ;
  wire [15:0]\gt_rxdata_q_reg[15]_5 ;
  wire [15:0]\gt_rxdata_q_reg[15]_6 ;
  wire gt_rxelecidle_q;
  wire gt_rxelecidle_q_reg;
  wire gt_rxelecidle_q_reg_0;
  wire gt_rxelecidle_q_reg_1;
  wire gt_rxelecidle_q_reg_2;
  wire gt_rxelecidle_q_reg_3;
  wire gt_rxelecidle_q_reg_4;
  wire gt_rxelecidle_q_reg_5;
  wire [63:0]m_axis_rx_tdata;
  wire [7:0]m_axis_rx_tkeep;
  wire m_axis_rx_tlast;
  wire m_axis_rx_tready;
  wire [21:0]m_axis_rx_tuser;
  wire m_axis_rx_tvalid;
  wire pcie_7x_i_n_11;
  wire pcie_7x_i_n_12;
  wire pcie_7x_i_n_14;
  wire pcie_7x_i_n_19;
  wire pcie_7x_i_n_23;
  wire pcie_7x_i_n_25;
  wire pcie_7x_i_n_26;
  wire pcie_7x_i_n_3;
  wire [8:0]pcie_drp_addr;
  wire pcie_drp_clk;
  wire [15:0]pcie_drp_di;
  wire [15:0]pcie_drp_do;
  wire pcie_drp_en;
  wire pcie_drp_rdy;
  wire pcie_drp_we;
  wire phy_rdy_n;
  wire pipe_rx0_chanisaligned_o;
  wire [1:0]pipe_rx0_char_is_k_o;
  wire [15:0]pipe_rx0_data_o;
  wire pipe_rx0_elec_idle_o;
  wire pipe_rx0_phy_status_o;
  wire pipe_rx0_polarity_i;
  wire [2:0]pipe_rx0_status_o;
  wire pipe_rx0_valid;
  wire pipe_rx0_valid_o;
  wire pipe_rx1_chanisaligned_o;
  wire [1:0]pipe_rx1_char_is_k_o;
  wire [15:0]pipe_rx1_data_o;
  wire pipe_rx1_elec_idle_o;
  wire pipe_rx1_phy_status_o;
  wire pipe_rx1_polarity_i;
  wire [2:0]pipe_rx1_status_o;
  wire pipe_rx1_valid;
  wire pipe_rx1_valid_o;
  wire pipe_rx2_chanisaligned_o;
  wire [1:0]pipe_rx2_char_is_k_o;
  wire [15:0]pipe_rx2_data_o;
  wire pipe_rx2_elec_idle_o;
  wire pipe_rx2_phy_status_o;
  wire pipe_rx2_polarity_i;
  wire [2:0]pipe_rx2_status_o;
  wire pipe_rx2_valid;
  wire pipe_rx2_valid_o;
  wire pipe_rx3_chanisaligned_o;
  wire [1:0]pipe_rx3_char_is_k_o;
  wire [15:0]pipe_rx3_data_o;
  wire pipe_rx3_elec_idle_o;
  wire pipe_rx3_phy_status_o;
  wire pipe_rx3_polarity_i;
  wire [2:0]pipe_rx3_status_o;
  wire pipe_rx3_valid;
  wire pipe_rx3_valid_o;
  wire pipe_rx4_chanisaligned_o;
  wire [1:0]pipe_rx4_char_is_k_o;
  wire [15:0]pipe_rx4_data_o;
  wire pipe_rx4_elec_idle_o;
  wire pipe_rx4_phy_status_o;
  wire pipe_rx4_polarity_i;
  wire [2:0]pipe_rx4_status_o;
  wire pipe_rx4_valid;
  wire pipe_rx4_valid_o;
  wire pipe_rx5_chanisaligned_o;
  wire [1:0]pipe_rx5_char_is_k_o;
  wire [15:0]pipe_rx5_data_o;
  wire pipe_rx5_elec_idle_o;
  wire pipe_rx5_phy_status_o;
  wire pipe_rx5_polarity_i;
  wire [2:0]pipe_rx5_status_o;
  wire pipe_rx5_valid;
  wire pipe_rx5_valid_o;
  wire pipe_rx6_chanisaligned_o;
  wire [1:0]pipe_rx6_char_is_k_o;
  wire [15:0]pipe_rx6_data_o;
  wire pipe_rx6_elec_idle_o;
  wire pipe_rx6_phy_status_o;
  wire pipe_rx6_polarity_i;
  wire [2:0]pipe_rx6_status_o;
  wire pipe_rx6_valid;
  wire pipe_rx6_valid_o;
  wire pipe_rx7_chanisaligned_o;
  wire [1:0]pipe_rx7_char_is_k_o;
  wire [15:0]pipe_rx7_data_o;
  wire pipe_rx7_elec_idle_o;
  wire pipe_rx7_phy_status_o;
  wire pipe_rx7_polarity_i;
  wire [2:0]pipe_rx7_status_o;
  wire pipe_rx7_valid;
  wire pipe_rx7_valid_o;
  wire [1:0]pipe_tx0_char_is_k_i;
  wire pipe_tx0_compliance_i;
  wire [15:0]pipe_tx0_data_i;
  wire pipe_tx0_elec_idle_i;
  wire [1:0]pipe_tx0_powerdown_i;
  wire [1:0]pipe_tx1_char_is_k_i;
  wire pipe_tx1_compliance_i;
  wire [15:0]pipe_tx1_data_i;
  wire pipe_tx1_elec_idle_i;
  wire [1:0]pipe_tx1_powerdown_i;
  wire [1:0]pipe_tx2_char_is_k_i;
  wire pipe_tx2_compliance_i;
  wire [15:0]pipe_tx2_data_i;
  wire pipe_tx2_elec_idle_i;
  wire [1:0]pipe_tx2_powerdown_i;
  wire [1:0]pipe_tx3_char_is_k_i;
  wire pipe_tx3_compliance_i;
  wire [15:0]pipe_tx3_data_i;
  wire pipe_tx3_elec_idle_i;
  wire [1:0]pipe_tx3_powerdown_i;
  wire [1:0]pipe_tx4_char_is_k_i;
  wire pipe_tx4_compliance_i;
  wire [15:0]pipe_tx4_data_i;
  wire pipe_tx4_elec_idle_i;
  wire [1:0]pipe_tx4_powerdown_i;
  wire [1:0]pipe_tx5_char_is_k_i;
  wire pipe_tx5_compliance_i;
  wire [15:0]pipe_tx5_data_i;
  wire pipe_tx5_elec_idle_i;
  wire [1:0]pipe_tx5_powerdown_i;
  wire [1:0]pipe_tx6_char_is_k_i;
  wire pipe_tx6_compliance_i;
  wire [15:0]pipe_tx6_data_i;
  wire pipe_tx6_elec_idle_i;
  wire [1:0]pipe_tx6_powerdown_i;
  wire [1:0]pipe_tx7_char_is_k_i;
  wire pipe_tx7_compliance_i;
  wire [15:0]pipe_tx7_data_i;
  wire pipe_tx7_elec_idle_i;
  wire [1:0]pipe_tx7_powerdown_i;
  wire pipe_tx_deemph_i;
  wire [2:0]pipe_tx_margin_i;
  wire pipe_tx_rate_i;
  wire pipe_tx_rcvr_det;
  wire pipe_tx_rcvr_det_i;
  wire pl_directed_change_done;
  wire pl_directed_link_auton;
  wire [1:0]pl_directed_link_change;
  wire pl_directed_link_speed;
  wire [1:0]pl_directed_link_width;
  wire pl_downstream_deemph_source;
  wire [2:0]pl_initial_link_width;
  wire [1:0]pl_lane_reversal_mode;
  wire pl_link_gen2_cap;
  wire pl_link_partner_gen2_supported;
  wire pl_link_upcfg_cap;
  wire [5:0]pl_ltssm_state;
  wire pl_phy_lnk_up;
  wire pl_phy_lnk_up_q_reg;
  wire pl_received_hot_rst;
  wire [1:0]pl_rx_pm_state;
  wire pl_sel_lnk_rate;
  wire [1:0]pl_sel_lnk_width;
  wire pl_transmit_hot_rst;
  wire [2:0]pl_tx_pm_state;
  wire pl_upstream_prefer_deemph;
  wire [0:0]\rate_reg1_reg[0] ;
  wire \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered10_out ;
  wire rx_np_ok;
  wire rx_np_req;
  wire [63:0]s_axis_tx_tdata;
  wire [0:0]s_axis_tx_tkeep;
  wire s_axis_tx_tlast;
  wire s_axis_tx_tready;
  wire [3:0]s_axis_tx_tuser;
  wire s_axis_tx_tvalid;
  wire sys_rst_n;
  wire trn_lnk_up;
  wire [6:0]trn_rbar_hit;
  wire [63:0]trn_rd;
  wire trn_rdst_rdy;
  wire trn_recrc_err;
  wire trn_reof;
  wire trn_rerrfwd;
  wire trn_rrem;
  wire trn_rsof;
  wire trn_rsrc_dsc;
  wire [5:0]trn_tbuf_av;
  wire trn_tcfg_gnt;
  wire trn_tcfg_req;
  wire [63:0]trn_td;
  wire trn_tdst_rdy;
  wire trn_tecrc_gen;
  wire trn_teof;
  wire trn_terrfwd;
  wire trn_trem;
  wire trn_tsof;
  wire trn_tsrc_dsc;
  wire trn_tsrc_rdy;
  wire trn_tstr;
  wire tx_cfg_gnt;
  wire tx_err_drop;
  wire \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ;
  wire \tx_inst/xhdl12.tx_thrl_ctl_inst/tbuf_av_min_trig ;
  wire user_clk;
  wire user_lnk_up_int_reg;
  wire user_reset_int_reg;
  wire user_reset_out_reg;

  PCIeGen1x8If64_PCIeGen1x8If64_axi_basic_top axi_basic_top_i
       (.Q({trn_td[31:0],trn_td[63:32]}),
        .cfg_pcie_link_state(cfg_pcie_link_state),
        .cfg_pm_turnoff_ok_n(cfg_pm_turnoff_ok_n),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_turnoff_ok(cfg_turnoff_ok),
        .m_axis_rx_tdata(m_axis_rx_tdata),
        .m_axis_rx_tkeep(m_axis_rx_tkeep),
        .m_axis_rx_tlast(m_axis_rx_tlast),
        .m_axis_rx_tready(m_axis_rx_tready),
        .m_axis_rx_tuser(m_axis_rx_tuser),
        .m_axis_rx_tvalid(m_axis_rx_tvalid),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (pcie_7x_i_n_11),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (pcie_7x_i_n_14),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (pcie_7x_i_n_3),
        .\ramb_bl.ramb36_dp_bl.ram36_bl ({trn_tsrc_dsc,trn_tstr,trn_terrfwd,trn_tecrc_gen}),
        .rsrc_rdy_filtered10_out(\rx_inst/rx_pipeline_inst/rsrc_rdy_filtered10_out ),
        .s_axis_tx_tdata(s_axis_tx_tdata),
        .s_axis_tx_tkeep(s_axis_tx_tkeep),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tready(s_axis_tx_tready),
        .s_axis_tx_tuser(s_axis_tx_tuser),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .tbuf_av_gap_thrtl_reg(axi_basic_top_i_n_8),
        .tbuf_av_gap_thrtl_reg_0(axi_basic_top_i_n_9),
        .tbuf_av_min_trig(\tx_inst/xhdl12.tx_thrl_ctl_inst/tbuf_av_min_trig ),
        .\tcfg_req_cnt_reg[1] (pcie_7x_i_n_25),
        .trn_in_packet_reg(axi_basic_top_i_n_7),
        .trn_rbar_hit(trn_rbar_hit),
        .trn_rd(trn_rd),
        .trn_rdst_rdy(trn_rdst_rdy),
        .trn_rdst_rdy_xhdl4_reg(pcie_7x_i_n_12),
        .trn_recrc_err(trn_recrc_err),
        .trn_reof(trn_reof),
        .trn_rerrfwd(trn_rerrfwd),
        .trn_rrem(trn_rrem),
        .trn_rsof(trn_rsof),
        .trn_rsrc_dsc(trn_rsrc_dsc),
        .trn_tbuf_av(trn_tbuf_av),
        .trn_tcfg_gnt(trn_tcfg_gnt),
        .trn_tcfg_req(trn_tcfg_req),
        .trn_tdst_rdy(trn_tdst_rdy),
        .trn_teof(trn_teof),
        .trn_trem(trn_trem),
        .trn_tsof(trn_tsof),
        .trn_tsrc_rdy(trn_tsrc_rdy),
        .tx_cfg_gnt(tx_cfg_gnt),
        .user_clk(user_clk),
        .user_lnk_up_int_reg(user_lnk_up_int_reg),
        .user_reset_out_reg(user_reset_out_reg),
        .user_reset_out_reg_0(pcie_7x_i_n_23),
        .user_reset_out_reg_1(pcie_7x_i_n_26));
  LUT1 #(
    .INIT(2'h1)) 
    \cfg_bus_number_d[7]_i_1 
       (.I0(user_lnk_up_int_reg),
        .O(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_bus_number_d_reg[0] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[8]),
        .Q(cfg_bus_number[0]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_bus_number_d_reg[1] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[9]),
        .Q(cfg_bus_number[1]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_bus_number_d_reg[2] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[10]),
        .Q(cfg_bus_number[2]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_bus_number_d_reg[3] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[11]),
        .Q(cfg_bus_number[3]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_bus_number_d_reg[4] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[12]),
        .Q(cfg_bus_number[4]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_bus_number_d_reg[5] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[13]),
        .Q(cfg_bus_number[5]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_bus_number_d_reg[6] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[14]),
        .Q(cfg_bus_number[6]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_bus_number_d_reg[7] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[15]),
        .Q(cfg_bus_number[7]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_device_number_d_reg[0] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[3]),
        .Q(cfg_device_number[0]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_device_number_d_reg[1] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[4]),
        .Q(cfg_device_number[1]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_device_number_d_reg[2] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[5]),
        .Q(cfg_device_number[2]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_device_number_d_reg[3] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[6]),
        .Q(cfg_device_number[3]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_device_number_d_reg[4] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[7]),
        .Q(cfg_device_number[4]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_function_number_d_reg[0] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[0]),
        .Q(cfg_function_number[0]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_function_number_d_reg[1] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[1]),
        .Q(cfg_function_number[1]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  FDRE \cfg_function_number_d_reg[2] 
       (.C(user_clk),
        .CE(pcie_7x_i_n_19),
        .D(cfg_msg_data[2]),
        .Q(cfg_function_number[2]),
        .R(\tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig ));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_7x pcie_7x_i
       (.CLK(CLK),
        .E(pcie_7x_i_n_19),
        .Q(pipe_rx0_data_o),
        .bridge_reset_int(bridge_reset_int),
        .cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en),
        .cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en),
        .cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
        .cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received),
        .cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en),
        .cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received),
        .cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en),
        .cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received),
        .cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en),
        .cfg_bridge_serr_en(cfg_bridge_serr_en),
        .cfg_command(cfg_command),
        .cfg_dcommand(cfg_dcommand),
        .cfg_dcommand2(cfg_dcommand2),
        .cfg_ds_bus_number(cfg_ds_bus_number),
        .cfg_ds_device_number(cfg_ds_device_number),
        .cfg_ds_function_number(cfg_ds_function_number),
        .cfg_dsn(cfg_dsn),
        .cfg_dstatus(cfg_dstatus),
        .cfg_err_aer_headerlog(cfg_err_aer_headerlog),
        .cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set),
        .cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked),
        .cfg_err_cor(cfg_err_cor),
        .cfg_err_cpl_abort(cfg_err_cpl_abort),
        .cfg_err_cpl_rdy(cfg_err_cpl_rdy),
        .cfg_err_cpl_timeout(cfg_err_cpl_timeout),
        .cfg_err_cpl_unexpect(cfg_err_cpl_unexpect),
        .cfg_err_ecrc(cfg_err_ecrc),
        .cfg_err_internal_cor(cfg_err_internal_cor),
        .cfg_err_internal_uncor(cfg_err_internal_uncor),
        .cfg_err_locked(cfg_err_locked),
        .cfg_err_malformed(cfg_err_malformed),
        .cfg_err_mc_blocked(cfg_err_mc_blocked),
        .cfg_err_norecovery(cfg_err_norecovery),
        .cfg_err_poisoned(cfg_err_poisoned),
        .cfg_err_posted(cfg_err_posted),
        .cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
        .cfg_err_ur(cfg_err_ur),
        .cfg_interrupt(cfg_interrupt),
        .cfg_interrupt_assert(cfg_interrupt_assert),
        .cfg_interrupt_di(cfg_interrupt_di),
        .cfg_interrupt_do(cfg_interrupt_do),
        .cfg_interrupt_mmenable(cfg_interrupt_mmenable),
        .cfg_interrupt_msienable(cfg_interrupt_msienable),
        .cfg_interrupt_msixenable(cfg_interrupt_msixenable),
        .cfg_interrupt_msixfm(cfg_interrupt_msixfm),
        .cfg_interrupt_rdy(cfg_interrupt_rdy),
        .cfg_interrupt_stat(cfg_interrupt_stat),
        .cfg_lcommand(cfg_lcommand),
        .cfg_lstatus(cfg_lstatus),
        .cfg_mgmt_byte_en_n(cfg_mgmt_byte_en_n),
        .cfg_mgmt_di(cfg_mgmt_di),
        .cfg_mgmt_do(cfg_mgmt_do),
        .cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
        .cfg_mgmt_rd_en(cfg_mgmt_rd_en),
        .cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
        .cfg_mgmt_wr_en(cfg_mgmt_wr_en),
        .cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
        .cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw),
        .cfg_msg_data(cfg_msg_data),
        .cfg_msg_received(cfg_msg_received),
        .cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a),
        .cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b),
        .cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c),
        .cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d),
        .cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a),
        .cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b),
        .cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c),
        .cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d),
        .cfg_msg_received_err_cor(cfg_msg_received_err_cor),
        .cfg_msg_received_err_fatal(cfg_msg_received_err_fatal),
        .cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal),
        .cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak),
        .cfg_msg_received_pm_pme(cfg_msg_received_pm_pme),
        .cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack),
        .cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit),
        .cfg_pcie_link_state(cfg_pcie_link_state),
        .cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
        .cfg_pm_force_state(cfg_pm_force_state),
        .cfg_pm_force_state_en(cfg_pm_force_state_en),
        .cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s),
        .cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1),
        .cfg_pm_turnoff_ok_n(cfg_pm_turnoff_ok_n),
        .cfg_pm_wake(cfg_pm_wake),
        .cfg_pmcsr_pme_en(cfg_pmcsr_pme_en),
        .cfg_pmcsr_pme_status(cfg_pmcsr_pme_status),
        .cfg_pmcsr_powerstate(cfg_pmcsr_powerstate),
        .cfg_received_func_lvl_rst(cfg_received_func_lvl_rst),
        .cfg_root_control_pme_int_en(cfg_root_control_pme_int_en),
        .cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en),
        .cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en),
        .cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en),
        .cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse),
        .cfg_to_turnoff(cfg_to_turnoff),
        .cfg_trn_pending(cfg_trn_pending),
        .cfg_vc_tcvc_map(cfg_vc_tcvc_map),
        .fc_cpld(fc_cpld),
        .fc_cplh(fc_cplh),
        .fc_npd(fc_npd),
        .fc_nph(fc_nph),
        .fc_pd(fc_pd),
        .fc_ph(fc_ph),
        .fc_sel(fc_sel),
        .pcie_drp_addr(pcie_drp_addr),
        .pcie_drp_clk(pcie_drp_clk),
        .pcie_drp_di(pcie_drp_di),
        .pcie_drp_do(pcie_drp_do),
        .pcie_drp_en(pcie_drp_en),
        .pcie_drp_rdy(pcie_drp_rdy),
        .pcie_drp_we(pcie_drp_we),
        .pipe_rx0_chanisaligned(pipe_rx0_chanisaligned_o),
        .pipe_rx0_elec_idle(pipe_rx0_elec_idle_o),
        .pipe_rx0_phy_status(pipe_rx0_phy_status_o),
        .pipe_rx0_polarity(pipe_rx0_polarity_i),
        .pipe_rx0_valid(pipe_rx0_valid_o),
        .pipe_rx1_chanisaligned(pipe_rx1_chanisaligned_o),
        .pipe_rx1_elec_idle(pipe_rx1_elec_idle_o),
        .pipe_rx1_phy_status(pipe_rx1_phy_status_o),
        .pipe_rx1_polarity(pipe_rx1_polarity_i),
        .pipe_rx1_valid(pipe_rx1_valid_o),
        .pipe_rx2_chanisaligned(pipe_rx2_chanisaligned_o),
        .pipe_rx2_elec_idle(pipe_rx2_elec_idle_o),
        .pipe_rx2_phy_status(pipe_rx2_phy_status_o),
        .pipe_rx2_polarity(pipe_rx2_polarity_i),
        .pipe_rx2_valid(pipe_rx2_valid_o),
        .pipe_rx3_chanisaligned(pipe_rx3_chanisaligned_o),
        .pipe_rx3_elec_idle(pipe_rx3_elec_idle_o),
        .pipe_rx3_phy_status(pipe_rx3_phy_status_o),
        .pipe_rx3_polarity(pipe_rx3_polarity_i),
        .pipe_rx3_valid(pipe_rx3_valid_o),
        .pipe_rx4_chanisaligned(pipe_rx4_chanisaligned_o),
        .pipe_rx4_elec_idle(pipe_rx4_elec_idle_o),
        .pipe_rx4_phy_status(pipe_rx4_phy_status_o),
        .pipe_rx4_polarity(pipe_rx4_polarity_i),
        .pipe_rx4_valid(pipe_rx4_valid_o),
        .pipe_rx5_chanisaligned(pipe_rx5_chanisaligned_o),
        .pipe_rx5_elec_idle(pipe_rx5_elec_idle_o),
        .pipe_rx5_phy_status(pipe_rx5_phy_status_o),
        .pipe_rx5_polarity(pipe_rx5_polarity_i),
        .pipe_rx5_valid(pipe_rx5_valid_o),
        .pipe_rx6_chanisaligned(pipe_rx6_chanisaligned_o),
        .pipe_rx6_elec_idle(pipe_rx6_elec_idle_o),
        .pipe_rx6_phy_status(pipe_rx6_phy_status_o),
        .pipe_rx6_polarity(pipe_rx6_polarity_i),
        .pipe_rx6_valid(pipe_rx6_valid_o),
        .pipe_rx7_chanisaligned(pipe_rx7_chanisaligned_o),
        .pipe_rx7_elec_idle(pipe_rx7_elec_idle_o),
        .pipe_rx7_phy_status(pipe_rx7_phy_status_o),
        .pipe_rx7_polarity(pipe_rx7_polarity_i),
        .pipe_rx7_valid(pipe_rx7_valid_o),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1] (pipe_rx0_char_is_k_o),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_0 (pipe_rx1_char_is_k_o),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_1 (pipe_rx2_char_is_k_o),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_2 (pipe_rx3_char_is_k_o),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_3 (pipe_rx4_char_is_k_o),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_4 (pipe_rx5_char_is_k_o),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_5 (pipe_rx6_char_is_k_o),
        .\pipe_stages_1.pipe_rx_char_is_k_q_reg[1]_6 (pipe_rx7_char_is_k_o),
        .\pipe_stages_1.pipe_rx_data_q_reg[15] (pipe_rx1_data_o),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_0 (pipe_rx2_data_o),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_1 (pipe_rx3_data_o),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_2 (pipe_rx4_data_o),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_3 (pipe_rx5_data_o),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_4 (pipe_rx6_data_o),
        .\pipe_stages_1.pipe_rx_data_q_reg[15]_5 (pipe_rx7_data_o),
        .\pipe_stages_1.pipe_rx_status_q_reg[2] (pipe_rx0_status_o),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_0 (pipe_rx1_status_o),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_1 (pipe_rx2_status_o),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_2 (pipe_rx3_status_o),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_3 (pipe_rx4_status_o),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_4 (pipe_rx5_status_o),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_5 (pipe_rx6_status_o),
        .\pipe_stages_1.pipe_rx_status_q_reg[2]_6 (pipe_rx7_status_o),
        .pipe_tx0_char_is_k(pipe_tx0_char_is_k_i),
        .pipe_tx0_compliance(pipe_tx0_compliance_i),
        .pipe_tx0_data(pipe_tx0_data_i),
        .pipe_tx0_elec_idle(pipe_tx0_elec_idle_i),
        .pipe_tx0_powerdown(pipe_tx0_powerdown_i),
        .pipe_tx1_char_is_k(pipe_tx1_char_is_k_i),
        .pipe_tx1_compliance(pipe_tx1_compliance_i),
        .pipe_tx1_data(pipe_tx1_data_i),
        .pipe_tx1_elec_idle(pipe_tx1_elec_idle_i),
        .pipe_tx1_powerdown(pipe_tx1_powerdown_i),
        .pipe_tx2_char_is_k(pipe_tx2_char_is_k_i),
        .pipe_tx2_compliance(pipe_tx2_compliance_i),
        .pipe_tx2_data(pipe_tx2_data_i),
        .pipe_tx2_elec_idle(pipe_tx2_elec_idle_i),
        .pipe_tx2_powerdown(pipe_tx2_powerdown_i),
        .pipe_tx3_char_is_k(pipe_tx3_char_is_k_i),
        .pipe_tx3_compliance(pipe_tx3_compliance_i),
        .pipe_tx3_data(pipe_tx3_data_i),
        .pipe_tx3_elec_idle(pipe_tx3_elec_idle_i),
        .pipe_tx3_powerdown(pipe_tx3_powerdown_i),
        .pipe_tx4_char_is_k(pipe_tx4_char_is_k_i),
        .pipe_tx4_compliance(pipe_tx4_compliance_i),
        .pipe_tx4_data(pipe_tx4_data_i),
        .pipe_tx4_elec_idle(pipe_tx4_elec_idle_i),
        .pipe_tx4_powerdown(pipe_tx4_powerdown_i),
        .pipe_tx5_char_is_k(pipe_tx5_char_is_k_i),
        .pipe_tx5_compliance(pipe_tx5_compliance_i),
        .pipe_tx5_data(pipe_tx5_data_i),
        .pipe_tx5_elec_idle(pipe_tx5_elec_idle_i),
        .pipe_tx5_powerdown(pipe_tx5_powerdown_i),
        .pipe_tx6_char_is_k(pipe_tx6_char_is_k_i),
        .pipe_tx6_compliance(pipe_tx6_compliance_i),
        .pipe_tx6_data(pipe_tx6_data_i),
        .pipe_tx6_elec_idle(pipe_tx6_elec_idle_i),
        .pipe_tx6_powerdown(pipe_tx6_powerdown_i),
        .pipe_tx7_char_is_k(pipe_tx7_char_is_k_i),
        .pipe_tx7_compliance(pipe_tx7_compliance_i),
        .pipe_tx7_data(pipe_tx7_data_i),
        .pipe_tx7_elec_idle(pipe_tx7_elec_idle_i),
        .pipe_tx7_powerdown(pipe_tx7_powerdown_i),
        .pipe_tx_deemph(pipe_tx_deemph_i),
        .pipe_tx_margin(pipe_tx_margin_i),
        .pipe_tx_rate(pipe_tx_rate_i),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det_i),
        .pl_directed_change_done(pl_directed_change_done),
        .pl_directed_link_auton(pl_directed_link_auton),
        .pl_directed_link_change(pl_directed_link_change),
        .pl_directed_link_speed(pl_directed_link_speed),
        .pl_directed_link_width(pl_directed_link_width),
        .pl_downstream_deemph_source(pl_downstream_deemph_source),
        .pl_initial_link_width(pl_initial_link_width),
        .pl_lane_reversal_mode(pl_lane_reversal_mode),
        .pl_link_gen2_cap(pl_link_gen2_cap),
        .pl_link_partner_gen2_supported(pl_link_partner_gen2_supported),
        .pl_link_upcfg_cap(pl_link_upcfg_cap),
        .pl_ltssm_state(pl_ltssm_state),
        .pl_phy_lnk_up(pl_phy_lnk_up),
        .pl_phy_lnk_up_q_reg(pl_phy_lnk_up_q_reg),
        .pl_received_hot_rst(pl_received_hot_rst),
        .pl_rx_pm_state(pl_rx_pm_state),
        .pl_sel_lnk_rate(pl_sel_lnk_rate),
        .pl_sel_lnk_width(pl_sel_lnk_width),
        .pl_transmit_hot_rst(pl_transmit_hot_rst),
        .pl_tx_pm_state(pl_tx_pm_state),
        .pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
        .ppm_L1_thrtl_reg(pcie_7x_i_n_26),
        .reg_dsc_detect_reg(pcie_7x_i_n_12),
        .rsrc_rdy_filtered10_out(\rx_inst/rx_pipeline_inst/rsrc_rdy_filtered10_out ),
        .rx_np_ok(rx_np_ok),
        .rx_np_req(rx_np_req),
        .s_axis_tx_tlast(s_axis_tx_tlast),
        .s_axis_tx_tvalid(s_axis_tx_tvalid),
        .sys_rst_n(sys_rst_n),
        .\tbuf_av_d_reg[4] (axi_basic_top_i_n_9),
        .tbuf_av_gap_thrtl_reg(pcie_7x_i_n_3),
        .tbuf_av_gap_thrtl_reg_0(pcie_7x_i_n_14),
        .tbuf_av_min_trig(\tx_inst/xhdl12.tx_thrl_ctl_inst/tbuf_av_min_trig ),
        .\tcfg_req_cnt_reg[1] (axi_basic_top_i_n_8),
        .tready_thrtl_xhdl1_reg(pcie_7x_i_n_11),
        .tready_thrtl_xhdl1_reg_0(pcie_7x_i_n_25),
        .tready_thrtl_xhdl1_reg_1(s_axis_tx_tready),
        .trn_in_packet_reg(pcie_7x_i_n_23),
        .trn_in_packet_reg_0(axi_basic_top_i_n_7),
        .trn_lnk_up(trn_lnk_up),
        .trn_rbar_hit(trn_rbar_hit),
        .trn_rd(trn_rd),
        .trn_rdst_rdy(trn_rdst_rdy),
        .trn_recrc_err(trn_recrc_err),
        .trn_reof(trn_reof),
        .trn_rerrfwd(trn_rerrfwd),
        .trn_rrem(trn_rrem),
        .trn_rsof(trn_rsof),
        .trn_rsrc_dsc(trn_rsrc_dsc),
        .trn_tbuf_av(trn_tbuf_av),
        .trn_tcfg_gnt(trn_tcfg_gnt),
        .trn_tcfg_req(trn_tcfg_req),
        .trn_td(trn_td),
        .trn_tdst_rdy(trn_tdst_rdy),
        .trn_teof(trn_teof),
        .trn_trem(trn_trem),
        .trn_tsof(trn_tsof),
        .trn_tsrc_rdy(trn_tsrc_rdy),
        .tx_err_drop(tx_err_drop),
        .user_clk(user_clk),
        .user_reset_int_reg(user_reset_int_reg),
        .user_reset_out_reg(user_reset_out_reg),
        .\xhdl12.reg_tuser_reg[3] ({trn_tsrc_dsc,trn_tstr,trn_terrfwd,trn_tecrc_gen}));
  PCIeGen1x8If64_PCIeGen1x8If64_pcie_pipe_pipeline pcie_pipe_pipeline_i
       (.CLK(CLK),
        .D(D),
        .PIPE_POWERDOWN(PIPE_POWERDOWN),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE),
        .PIPE_TXDATA(PIPE_TXDATA),
        .PIPE_TXDATAK(PIPE_TXDATAK),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE),
        .PIPE_TXMARGIN(PIPE_TXMARGIN),
        .Q(Q),
        .TXMARGIN(TXMARGIN),
        .\cplllock_reg1_reg[2] (\cplllock_reg1_reg[2] ),
        .\cplllock_reg1_reg[3] (\cplllock_reg1_reg[3] ),
        .\cplllock_reg1_reg[3]_0 (\cplllock_reg1_reg[3]_0 ),
        .\cplllock_reg1_reg[6] (\cplllock_reg1_reg[6] ),
        .gt_rx_phy_status_q(gt_rx_phy_status_q),
        .gt_rx_phy_status_q_reg(gt_rx_phy_status_q_reg),
        .gt_rx_phy_status_q_reg_0(gt_rx_phy_status_q_reg_0),
        .gt_rx_phy_status_q_reg_1(gt_rx_phy_status_q_reg_1),
        .gt_rx_phy_status_q_reg_2(gt_rx_phy_status_q_reg_2),
        .gt_rx_phy_status_q_reg_3(gt_rx_phy_status_q_reg_3),
        .gt_rx_phy_status_q_reg_4(gt_rx_phy_status_q_reg_4),
        .gt_rx_phy_status_q_reg_5(gt_rx_phy_status_q_reg_5),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2] ),
        .\gt_rx_status_q_reg[2]_0 (\gt_rx_status_q_reg[2]_0 ),
        .\gt_rx_status_q_reg[2]_1 (\gt_rx_status_q_reg[2]_1 ),
        .\gt_rx_status_q_reg[2]_2 (\gt_rx_status_q_reg[2]_2 ),
        .\gt_rx_status_q_reg[2]_3 (\gt_rx_status_q_reg[2]_3 ),
        .\gt_rx_status_q_reg[2]_4 (\gt_rx_status_q_reg[2]_4 ),
        .\gt_rx_status_q_reg[2]_5 (\gt_rx_status_q_reg[2]_5 ),
        .\gt_rx_status_q_reg[2]_6 (\gt_rx_status_q_reg[2]_6 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1] ),
        .\gt_rxcharisk_q_reg[1]_0 (\gt_rxcharisk_q_reg[1]_0 ),
        .\gt_rxcharisk_q_reg[1]_1 (\gt_rxcharisk_q_reg[1]_1 ),
        .\gt_rxcharisk_q_reg[1]_2 (\gt_rxcharisk_q_reg[1]_2 ),
        .\gt_rxcharisk_q_reg[1]_3 (\gt_rxcharisk_q_reg[1]_3 ),
        .\gt_rxcharisk_q_reg[1]_4 (\gt_rxcharisk_q_reg[1]_4 ),
        .\gt_rxcharisk_q_reg[1]_5 (\gt_rxcharisk_q_reg[1]_5 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15] ),
        .\gt_rxdata_q_reg[15]_0 (\gt_rxdata_q_reg[15]_0 ),
        .\gt_rxdata_q_reg[15]_1 (\gt_rxdata_q_reg[15]_1 ),
        .\gt_rxdata_q_reg[15]_2 (\gt_rxdata_q_reg[15]_2 ),
        .\gt_rxdata_q_reg[15]_3 (\gt_rxdata_q_reg[15]_3 ),
        .\gt_rxdata_q_reg[15]_4 (\gt_rxdata_q_reg[15]_4 ),
        .\gt_rxdata_q_reg[15]_5 (\gt_rxdata_q_reg[15]_5 ),
        .\gt_rxdata_q_reg[15]_6 (\gt_rxdata_q_reg[15]_6 ),
        .gt_rxelecidle_q(gt_rxelecidle_q),
        .gt_rxelecidle_q_reg(gt_rxelecidle_q_reg),
        .gt_rxelecidle_q_reg_0(gt_rxelecidle_q_reg_0),
        .gt_rxelecidle_q_reg_1(gt_rxelecidle_q_reg_1),
        .gt_rxelecidle_q_reg_2(gt_rxelecidle_q_reg_2),
        .gt_rxelecidle_q_reg_3(gt_rxelecidle_q_reg_3),
        .gt_rxelecidle_q_reg_4(gt_rxelecidle_q_reg_4),
        .gt_rxelecidle_q_reg_5(gt_rxelecidle_q_reg_5),
        .phy_rdy_n(phy_rdy_n),
        .pipe_rx0_chanisaligned_o(pipe_rx0_chanisaligned_o),
        .pipe_rx0_elec_idle_o(pipe_rx0_elec_idle_o),
        .pipe_rx0_phy_status_o(pipe_rx0_phy_status_o),
        .pipe_rx0_polarity_i(pipe_rx0_polarity_i),
        .pipe_rx0_valid(pipe_rx0_valid),
        .pipe_rx0_valid_o(pipe_rx0_valid_o),
        .pipe_rx1_chanisaligned_o(pipe_rx1_chanisaligned_o),
        .pipe_rx1_elec_idle_o(pipe_rx1_elec_idle_o),
        .pipe_rx1_phy_status_o(pipe_rx1_phy_status_o),
        .pipe_rx1_polarity_i(pipe_rx1_polarity_i),
        .pipe_rx1_valid(pipe_rx1_valid),
        .pipe_rx1_valid_o(pipe_rx1_valid_o),
        .pipe_rx2_chanisaligned_o(pipe_rx2_chanisaligned_o),
        .pipe_rx2_elec_idle_o(pipe_rx2_elec_idle_o),
        .pipe_rx2_phy_status_o(pipe_rx2_phy_status_o),
        .pipe_rx2_polarity_i(pipe_rx2_polarity_i),
        .pipe_rx2_valid(pipe_rx2_valid),
        .pipe_rx2_valid_o(pipe_rx2_valid_o),
        .pipe_rx3_chanisaligned_o(pipe_rx3_chanisaligned_o),
        .pipe_rx3_elec_idle_o(pipe_rx3_elec_idle_o),
        .pipe_rx3_phy_status_o(pipe_rx3_phy_status_o),
        .pipe_rx3_polarity_i(pipe_rx3_polarity_i),
        .pipe_rx3_valid(pipe_rx3_valid),
        .pipe_rx3_valid_o(pipe_rx3_valid_o),
        .pipe_rx4_chanisaligned_o(pipe_rx4_chanisaligned_o),
        .pipe_rx4_elec_idle_o(pipe_rx4_elec_idle_o),
        .pipe_rx4_phy_status_o(pipe_rx4_phy_status_o),
        .pipe_rx4_polarity_i(pipe_rx4_polarity_i),
        .pipe_rx4_valid(pipe_rx4_valid),
        .pipe_rx4_valid_o(pipe_rx4_valid_o),
        .pipe_rx5_chanisaligned_o(pipe_rx5_chanisaligned_o),
        .pipe_rx5_elec_idle_o(pipe_rx5_elec_idle_o),
        .pipe_rx5_phy_status_o(pipe_rx5_phy_status_o),
        .pipe_rx5_polarity_i(pipe_rx5_polarity_i),
        .pipe_rx5_valid(pipe_rx5_valid),
        .pipe_rx5_valid_o(pipe_rx5_valid_o),
        .pipe_rx6_chanisaligned_o(pipe_rx6_chanisaligned_o),
        .pipe_rx6_elec_idle_o(pipe_rx6_elec_idle_o),
        .pipe_rx6_phy_status_o(pipe_rx6_phy_status_o),
        .pipe_rx6_polarity_i(pipe_rx6_polarity_i),
        .pipe_rx6_valid(pipe_rx6_valid),
        .pipe_rx6_valid_o(pipe_rx6_valid_o),
        .pipe_rx7_chanisaligned_o(pipe_rx7_chanisaligned_o),
        .pipe_rx7_elec_idle_o(pipe_rx7_elec_idle_o),
        .pipe_rx7_phy_status_o(pipe_rx7_phy_status_o),
        .pipe_rx7_polarity_i(pipe_rx7_polarity_i),
        .pipe_rx7_valid(pipe_rx7_valid),
        .pipe_rx7_valid_o(pipe_rx7_valid_o),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg (pipe_tx0_char_is_k_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_0 (pipe_tx1_char_is_k_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_1 (pipe_tx2_char_is_k_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_10 (pipe_tx3_data_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_11 (pipe_tx4_data_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_12 (pipe_tx5_data_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_13 (pipe_tx6_data_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_14 (pipe_tx7_data_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_15 (pipe_tx0_powerdown_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_16 (pipe_tx1_powerdown_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_17 (pipe_tx2_powerdown_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_18 (pipe_tx3_powerdown_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_19 (pipe_tx4_powerdown_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_2 (pipe_tx3_char_is_k_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_20 (pipe_tx5_powerdown_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_21 (pipe_tx6_powerdown_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_22 (pipe_tx7_powerdown_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_3 (pipe_tx4_char_is_k_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_4 (pipe_tx5_char_is_k_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_5 (pipe_tx6_char_is_k_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_6 (pipe_tx7_char_is_k_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_7 (pipe_tx0_data_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_8 (pipe_tx1_data_i),
        .\pipe_stages_1.pipe_rx_chanisaligned_q_reg_9 (pipe_tx2_data_i),
        .pipe_tx0_compliance_i(pipe_tx0_compliance_i),
        .pipe_tx0_elec_idle_i(pipe_tx0_elec_idle_i),
        .pipe_tx1_compliance_i(pipe_tx1_compliance_i),
        .pipe_tx1_elec_idle_i(pipe_tx1_elec_idle_i),
        .pipe_tx2_compliance_i(pipe_tx2_compliance_i),
        .pipe_tx2_elec_idle_i(pipe_tx2_elec_idle_i),
        .pipe_tx3_compliance_i(pipe_tx3_compliance_i),
        .pipe_tx3_elec_idle_i(pipe_tx3_elec_idle_i),
        .pipe_tx4_compliance_i(pipe_tx4_compliance_i),
        .pipe_tx4_elec_idle_i(pipe_tx4_elec_idle_i),
        .pipe_tx5_compliance_i(pipe_tx5_compliance_i),
        .pipe_tx5_elec_idle_i(pipe_tx5_elec_idle_i),
        .pipe_tx6_compliance_i(pipe_tx6_compliance_i),
        .pipe_tx6_elec_idle_i(pipe_tx6_elec_idle_i),
        .pipe_tx7_compliance_i(pipe_tx7_compliance_i),
        .pipe_tx7_elec_idle_i(pipe_tx7_elec_idle_i),
        .pipe_tx_deemph_i(pipe_tx_deemph_i),
        .pipe_tx_margin(pipe_tx_margin_i),
        .pipe_tx_rate_i(pipe_tx_rate_i),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det),
        .pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
        .\ramb_bl.ramb36_dp_bl.ram36_bl (pipe_rx0_char_is_k_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_0 (pipe_rx0_data_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_1 (pipe_rx0_status_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_10 (pipe_rx3_status_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_11 (pipe_rx4_char_is_k_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_12 (pipe_rx4_data_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_13 (pipe_rx4_status_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_14 (pipe_rx5_char_is_k_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_15 (pipe_rx5_data_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_16 (pipe_rx5_status_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_17 (pipe_rx6_char_is_k_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_18 (pipe_rx6_data_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_19 (pipe_rx6_status_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_2 (pipe_rx1_char_is_k_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_20 (pipe_rx7_char_is_k_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_21 (pipe_rx7_data_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_22 (pipe_rx7_status_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_3 (pipe_rx1_data_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_4 (pipe_rx1_status_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_5 (pipe_rx2_char_is_k_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_6 (pipe_rx2_data_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_7 (pipe_rx2_status_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_8 (pipe_rx3_char_is_k_o),
        .\ramb_bl.ramb36_dp_bl.ram36_bl_9 (pipe_rx3_data_o),
        .\rate_reg1_reg[0] (\rate_reg1_reg[0] ));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_clock" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_clock
   (CLK_MMCM_LOCK,
    CLK_PCLK,
    CLK_DCLK,
    CLK_USERCLK1,
    pipe_txoutclk_out,
    D,
    int_pclk_sel_slave,
    rate_gen3,
    pipe_mmcm_rst_n);
  output CLK_MMCM_LOCK;
  output CLK_PCLK;
  output CLK_DCLK;
  output CLK_USERCLK1;
  input pipe_txoutclk_out;
  input [7:0]D;
  input [7:0]int_pclk_sel_slave;
  input [0:0]rate_gen3;
  input pipe_mmcm_rst_n;

  wire CLK_DCLK;
  wire CLK_MMCM_LOCK;
  wire CLK_PCLK;
  wire CLK_USERCLK1;
  wire [7:0]D;
  wire clk_125mhz;
  wire clk_250mhz;
  wire gen3_reg1;
  wire gen3_reg2;
  wire [7:0]int_pclk_sel_slave;
  wire mmcm_fb;
  wire p_0_in__0;
  wire \pclk_i1_bufgctrl.pclk_i1_i_1_n_0 ;
  (* DONT_TOUCH *) wire pclk_sel;
  wire pclk_sel0_out;
  wire pclk_sel_i_2__7_n_0;
  wire pclk_sel_i_3_n_0;
  wire [7:0]pclk_sel_reg1;
  wire [7:0]pclk_sel_reg2;
  wire [7:0]pclk_sel_slave_reg1;
  wire [7:0]pclk_sel_slave_reg2;
  wire pipe_mmcm_rst_n;
  wire pipe_txoutclk_out;
  wire [0:0]rate_gen3;
  wire refclk;
  wire userclk1;
  wire NLW_mmcm_i_CLKFBOUTB_UNCONNECTED;
  wire NLW_mmcm_i_CLKFBSTOPPED_UNCONNECTED;
  wire NLW_mmcm_i_CLKINSTOPPED_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT0B_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT1B_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT2B_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT3_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT3B_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT4_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT5_UNCONNECTED;
  wire NLW_mmcm_i_CLKOUT6_UNCONNECTED;
  wire NLW_mmcm_i_DRDY_UNCONNECTED;
  wire NLW_mmcm_i_PSDONE_UNCONNECTED;
  wire [15:0]NLW_mmcm_i_DO_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  BUFG \dclk_i_bufg.dclk_i 
       (.I(clk_125mhz),
        .O(CLK_DCLK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg1_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(gen3_reg1),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg2_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(p_0_in__0));
  (* box_type = "PRIMITIVE" *) 
  MMCME2_ADV #(
    .BANDWIDTH("OPTIMIZED"),
    .CLKFBOUT_MULT_F(10.000000),
    .CLKFBOUT_PHASE(0.000000),
    .CLKFBOUT_USE_FINE_PS("FALSE"),
    .CLKIN1_PERIOD(10.000000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE_F(8.000000),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT0_USE_FINE_PS("FALSE"),
    .CLKOUT1_DIVIDE(4),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT1_USE_FINE_PS("FALSE"),
    .CLKOUT2_DIVIDE(4),
    .CLKOUT2_DUTY_CYCLE(0.500000),
    .CLKOUT2_PHASE(0.000000),
    .CLKOUT2_USE_FINE_PS("FALSE"),
    .CLKOUT3_DIVIDE(4),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT3_USE_FINE_PS("FALSE"),
    .CLKOUT4_CASCADE("FALSE"),
    .CLKOUT4_DIVIDE(20),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(0.000000),
    .CLKOUT4_USE_FINE_PS("FALSE"),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .CLKOUT5_USE_FINE_PS("FALSE"),
    .CLKOUT6_DIVIDE(1),
    .CLKOUT6_DUTY_CYCLE(0.500000),
    .CLKOUT6_PHASE(0.000000),
    .CLKOUT6_USE_FINE_PS("FALSE"),
    .COMPENSATION("INTERNAL"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKINSEL_INVERTED(1'b0),
    .IS_PSEN_INVERTED(1'b0),
    .IS_PSINCDEC_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER1(0.010000),
    .REF_JITTER2(0.010000),
    .SS_EN("FALSE"),
    .SS_MODE("CENTER_HIGH"),
    .SS_MOD_PERIOD(10000),
    .STARTUP_WAIT("FALSE")) 
    mmcm_i
       (.CLKFBIN(mmcm_fb),
        .CLKFBOUT(mmcm_fb),
        .CLKFBOUTB(NLW_mmcm_i_CLKFBOUTB_UNCONNECTED),
        .CLKFBSTOPPED(NLW_mmcm_i_CLKFBSTOPPED_UNCONNECTED),
        .CLKIN1(refclk),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKINSTOPPED(NLW_mmcm_i_CLKINSTOPPED_UNCONNECTED),
        .CLKOUT0(clk_125mhz),
        .CLKOUT0B(NLW_mmcm_i_CLKOUT0B_UNCONNECTED),
        .CLKOUT1(clk_250mhz),
        .CLKOUT1B(NLW_mmcm_i_CLKOUT1B_UNCONNECTED),
        .CLKOUT2(userclk1),
        .CLKOUT2B(NLW_mmcm_i_CLKOUT2B_UNCONNECTED),
        .CLKOUT3(NLW_mmcm_i_CLKOUT3_UNCONNECTED),
        .CLKOUT3B(NLW_mmcm_i_CLKOUT3B_UNCONNECTED),
        .CLKOUT4(NLW_mmcm_i_CLKOUT4_UNCONNECTED),
        .CLKOUT5(NLW_mmcm_i_CLKOUT5_UNCONNECTED),
        .CLKOUT6(NLW_mmcm_i_CLKOUT6_UNCONNECTED),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(NLW_mmcm_i_DO_UNCONNECTED[15:0]),
        .DRDY(NLW_mmcm_i_DRDY_UNCONNECTED),
        .DWE(1'b0),
        .LOCKED(CLK_MMCM_LOCK),
        .PSCLK(1'b0),
        .PSDONE(NLW_mmcm_i_PSDONE_UNCONNECTED),
        .PSEN(1'b0),
        .PSINCDEC(1'b0),
        .PWRDWN(1'b0),
        .RST(p_0_in__0));
  LUT1 #(
    .INIT(2'h1)) 
    mmcm_i_i_1
       (.I0(pipe_mmcm_rst_n),
        .O(p_0_in__0));
  (* box_type = "PRIMITIVE" *) 
  BUFGCTRL #(
    .INIT_OUT(0),
    .IS_CE0_INVERTED(1'b0),
    .IS_CE1_INVERTED(1'b0),
    .IS_I0_INVERTED(1'b0),
    .IS_I1_INVERTED(1'b0),
    .IS_IGNORE0_INVERTED(1'b0),
    .IS_IGNORE1_INVERTED(1'b0),
    .IS_S0_INVERTED(1'b0),
    .IS_S1_INVERTED(1'b0),
    .PRESELECT_I0("FALSE"),
    .PRESELECT_I1("FALSE")) 
    \pclk_i1_bufgctrl.pclk_i1 
       (.CE0(1'b1),
        .CE1(1'b1),
        .I0(clk_125mhz),
        .I1(clk_250mhz),
        .IGNORE0(1'b0),
        .IGNORE1(1'b0),
        .O(CLK_PCLK),
        .S0(\pclk_i1_bufgctrl.pclk_i1_i_1_n_0 ),
        .S1(pclk_sel));
  LUT1 #(
    .INIT(2'h1)) 
    \pclk_i1_bufgctrl.pclk_i1_i_1 
       (.I0(pclk_sel),
        .O(\pclk_i1_bufgctrl.pclk_i1_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF80FC8000000000)) 
    pclk_sel_i_1
       (.I0(pclk_sel_i_2__7_n_0),
        .I1(pclk_sel_reg2[3]),
        .I2(pclk_sel_reg2[2]),
        .I3(pclk_sel),
        .I4(pclk_sel_i_3_n_0),
        .I5(pipe_mmcm_rst_n),
        .O(pclk_sel0_out));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    pclk_sel_i_2__7
       (.I0(pclk_sel_reg2[5]),
        .I1(pclk_sel_reg2[4]),
        .I2(pclk_sel_reg2[6]),
        .I3(pclk_sel_reg2[7]),
        .I4(pclk_sel_reg2[0]),
        .I5(pclk_sel_reg2[1]),
        .O(pclk_sel_i_2__7_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    pclk_sel_i_3
       (.I0(pclk_sel_reg2[5]),
        .I1(pclk_sel_reg2[4]),
        .I2(pclk_sel_reg2[6]),
        .I3(pclk_sel_reg2[7]),
        .I4(pclk_sel_reg2[0]),
        .I5(pclk_sel_reg2[1]),
        .O(pclk_sel_i_3_n_0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel0_out),
        .Q(pclk_sel),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg1_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(pclk_sel_reg1[0]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg1_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(pclk_sel_reg1[1]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg1_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(pclk_sel_reg1[2]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg1_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(pclk_sel_reg1[3]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg1_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[4]),
        .Q(pclk_sel_reg1[4]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg1_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[5]),
        .Q(pclk_sel_reg1[5]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg1_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[6]),
        .Q(pclk_sel_reg1[6]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg1_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(D[7]),
        .Q(pclk_sel_reg1[7]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg2_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_reg1[0]),
        .Q(pclk_sel_reg2[0]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg2_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_reg1[1]),
        .Q(pclk_sel_reg2[1]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg2_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_reg1[2]),
        .Q(pclk_sel_reg2[2]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg2_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_reg1[3]),
        .Q(pclk_sel_reg2[3]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg2_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_reg1[4]),
        .Q(pclk_sel_reg2[4]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg2_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_reg1[5]),
        .Q(pclk_sel_reg2[5]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg2_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_reg1[6]),
        .Q(pclk_sel_reg2[6]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_reg2_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_reg1[7]),
        .Q(pclk_sel_reg2[7]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg1_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(int_pclk_sel_slave[0]),
        .Q(pclk_sel_slave_reg1[0]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg1_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(int_pclk_sel_slave[1]),
        .Q(pclk_sel_slave_reg1[1]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg1_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(int_pclk_sel_slave[2]),
        .Q(pclk_sel_slave_reg1[2]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg1_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(int_pclk_sel_slave[3]),
        .Q(pclk_sel_slave_reg1[3]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg1_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(int_pclk_sel_slave[4]),
        .Q(pclk_sel_slave_reg1[4]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg1_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(int_pclk_sel_slave[5]),
        .Q(pclk_sel_slave_reg1[5]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg1_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(int_pclk_sel_slave[6]),
        .Q(pclk_sel_slave_reg1[6]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg1_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(int_pclk_sel_slave[7]),
        .Q(pclk_sel_slave_reg1[7]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg2_reg[0] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_slave_reg1[0]),
        .Q(pclk_sel_slave_reg2[0]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg2_reg[1] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_slave_reg1[1]),
        .Q(pclk_sel_slave_reg2[1]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg2_reg[2] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_slave_reg1[2]),
        .Q(pclk_sel_slave_reg2[2]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg2_reg[3] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_slave_reg1[3]),
        .Q(pclk_sel_slave_reg2[3]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg2_reg[4] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_slave_reg1[4]),
        .Q(pclk_sel_slave_reg2[4]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg2_reg[5] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_slave_reg1[5]),
        .Q(pclk_sel_slave_reg2[5]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg2_reg[6] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_slave_reg1[6]),
        .Q(pclk_sel_slave_reg2[6]),
        .R(p_0_in__0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \pclk_sel_slave_reg2_reg[7] 
       (.C(CLK_PCLK),
        .CE(1'b1),
        .D(pclk_sel_slave_reg1[7]),
        .Q(pclk_sel_slave_reg2[7]),
        .R(p_0_in__0));
  (* box_type = "PRIMITIVE" *) 
  BUFG \txoutclk_i.txoutclk_i 
       (.I(pipe_txoutclk_out),
        .O(refclk));
  (* box_type = "PRIMITIVE" *) 
  BUFG \userclk1_i1.usrclk1_i1 
       (.I(userclk1),
        .O(CLK_USERCLK1));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_drp" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp
   (Q,
    DRPADDR,
    \cplllock_reg1_reg[0] ,
    \cplllock_reg1_reg[0]_0 ,
    gt_ch_drp_rdy,
    DRPDI,
    DRP_DONE,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi,
    RST_DCLK_RESET,
    DRP_X16X20_MODE,
    \resetovrd_disble.reset_reg[4] ,
    DRP_START,
    ext_ch_gt_drprdy,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    DRP_X16,
    ext_ch_gt_drpdo,
    DRP_GTXRESET);
  output [2:0]Q;
  output [8:0]DRPADDR;
  output \cplllock_reg1_reg[0] ;
  output \cplllock_reg1_reg[0]_0 ;
  output [0:0]gt_ch_drp_rdy;
  output [15:0]DRPDI;
  output DRP_DONE;
  input [8:0]ext_ch_gt_drpaddr;
  input [0:0]ext_ch_gt_drpen;
  input [0:0]ext_ch_gt_drpwe;
  input [15:0]ext_ch_gt_drpdi;
  input RST_DCLK_RESET;
  input DRP_X16X20_MODE;
  input \resetovrd_disble.reset_reg[4] ;
  input DRP_START;
  input [0:0]ext_ch_gt_drprdy;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input DRP_X16;
  input [15:0]ext_ch_gt_drpdo;
  input DRP_GTXRESET;

  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_DONE;
  wire DRP_GTXRESET;
  wire DRP_START;
  wire DRP_X16;
  wire DRP_X16X20_MODE;
  wire [2:0]Q;
  wire RST_DCLK_RESET;
  wire \addr_reg[0]_i_1_n_0 ;
  wire \addr_reg[1]_i_1_n_0 ;
  wire \addr_reg[2]_i_1_n_0 ;
  wire \addr_reg[3]_i_1_n_0 ;
  wire \addr_reg[4]_i_1_n_0 ;
  wire \addr_reg[4]_i_2_n_0 ;
  wire \addr_reg[5]_i_1_n_0 ;
  wire \addr_reg[6]_i_1_n_0 ;
  wire \addr_reg[7]_i_1_n_0 ;
  wire \addr_reg[7]_i_2_n_0 ;
  wire \addr_reg_reg_n_0_[0] ;
  wire \addr_reg_reg_n_0_[1] ;
  wire \addr_reg_reg_n_0_[2] ;
  wire \addr_reg_reg_n_0_[3] ;
  wire \addr_reg_reg_n_0_[4] ;
  wire \addr_reg_reg_n_0_[5] ;
  wire \addr_reg_reg_n_0_[6] ;
  wire \addr_reg_reg_n_0_[7] ;
  wire \cplllock_reg1_reg[0] ;
  wire \cplllock_reg1_reg[0]_0 ;
  wire [7:7]data15;
  wire data4;
  wire [15:0]di_reg;
  wire \di_reg[0]_i_2_n_0 ;
  wire \di_reg[0]_i_3_n_0 ;
  wire \di_reg[0]_i_4_n_0 ;
  wire \di_reg[0]_i_5_n_0 ;
  wire \di_reg[0]_i_6_n_0 ;
  wire \di_reg[10]_i_2_n_0 ;
  wire \di_reg[11]_i_2_n_0 ;
  wire \di_reg[11]_i_3_n_0 ;
  wire \di_reg[11]_i_4_n_0 ;
  wire \di_reg[11]_i_5_n_0 ;
  wire \di_reg[12]_i_2_n_0 ;
  wire \di_reg[12]_i_3_n_0 ;
  wire \di_reg[12]_i_4_n_0 ;
  wire \di_reg[13]_i_2_n_0 ;
  wire \di_reg[13]_i_3_n_0 ;
  wire \di_reg[13]_i_4_n_0 ;
  wire \di_reg[14]_i_2_n_0 ;
  wire \di_reg[14]_i_3_n_0 ;
  wire \di_reg[14]_i_4_n_0 ;
  wire \di_reg[14]_i_6_n_0 ;
  wire \di_reg[14]_i_7_n_0 ;
  wire \di_reg[15]_i_2_n_0 ;
  wire \di_reg[1]_i_2_n_0 ;
  wire \di_reg[1]_i_3_n_0 ;
  wire \di_reg[1]_i_4_n_0 ;
  wire \di_reg[1]_i_5_n_0 ;
  wire \di_reg[1]_i_6_n_0 ;
  wire \di_reg[2]_i_2_n_0 ;
  wire \di_reg[2]_i_3_n_0 ;
  wire \di_reg[2]_i_4_n_0 ;
  wire \di_reg[2]_i_5_n_0 ;
  wire \di_reg[3]_i_2_n_0 ;
  wire \di_reg[3]_i_3_n_0 ;
  wire \di_reg[3]_i_4_n_0 ;
  wire \di_reg[4]_i_2_n_0 ;
  wire \di_reg[4]_i_3_n_0 ;
  wire \di_reg[4]_i_4_n_0 ;
  wire \di_reg[4]_i_5_n_0 ;
  wire \di_reg[4]_i_6_n_0 ;
  wire \di_reg[4]_i_7_n_0 ;
  wire \di_reg[4]_i_8_n_0 ;
  wire \di_reg[5]_i_2_n_0 ;
  wire \di_reg[5]_i_3_n_0 ;
  wire \di_reg[5]_i_4_n_0 ;
  wire \di_reg[6]_i_2_n_0 ;
  wire \di_reg[6]_i_3_n_0 ;
  wire \di_reg[7]_i_2_n_0 ;
  wire \di_reg[7]_i_3_n_0 ;
  wire \di_reg_reg_n_0_[0] ;
  wire \di_reg_reg_n_0_[10] ;
  wire \di_reg_reg_n_0_[11] ;
  wire \di_reg_reg_n_0_[12] ;
  wire \di_reg_reg_n_0_[13] ;
  wire \di_reg_reg_n_0_[14] ;
  wire \di_reg_reg_n_0_[15] ;
  wire \di_reg_reg_n_0_[1] ;
  wire \di_reg_reg_n_0_[2] ;
  wire \di_reg_reg_n_0_[3] ;
  wire \di_reg_reg_n_0_[4] ;
  wire \di_reg_reg_n_0_[5] ;
  wire \di_reg_reg_n_0_[6] ;
  wire \di_reg_reg_n_0_[7] ;
  wire \di_reg_reg_n_0_[8] ;
  wire \di_reg_reg_n_0_[9] ;
  wire [15:0]do_reg1;
  wire [15:0]do_reg2;
  wire done_i_1_n_0;
  wire [8:0]ext_ch_gt_drpaddr;
  wire [15:0]ext_ch_gt_drpdi;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drpen;
  wire [0:0]ext_ch_gt_drprdy;
  wire [0:0]ext_ch_gt_drpwe;
  wire [2:0]fsm;
  wire \fsm[0]_i_3__0_n_0 ;
  wire [0:0]gt_ch_drp_rdy;
  wire gtxreset_reg1;
  wire gtxreset_reg2;
  wire [4:0]index;
  wire \index[0]_i_1__1_n_0 ;
  wire \index[1]_i_1__1_n_0 ;
  wire \index[2]_i_1__1_n_0 ;
  wire \index[3]_i_1_n_0 ;
  wire \index[3]_i_2_n_0 ;
  wire \index[4]_i_1_n_0 ;
  wire \index[4]_i_2_n_0 ;
  wire \index[4]_i_3_n_0 ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1_n_0 ;
  wire mode;
  wire mode_i_1_n_0;
  wire mode_i_2_n_0;
  wire mode_i_3__1_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire [1:0]rate_reg1;
  wire [1:0]rate_reg2;
  wire rdy_reg1;
  wire rdy_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire start_reg1;
  wire start_reg2;
  wire x16_reg1;
  wire x16_reg2;
  wire x16x20_mode_reg1;
  wire x16x20_mode_reg2;

  LUT6 #(
    .INIT(64'h1471357514713564)) 
    \addr_reg[0]_i_1 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2_n_0 ),
        .O(\addr_reg[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h404050500F0F0500)) 
    \addr_reg[1]_i_1 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h051005105A055A00)) 
    \addr_reg[2]_i_1 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(index[2]),
        .I4(mode),
        .I5(index[1]),
        .O(\addr_reg[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5767576753275326)) 
    \addr_reg[3]_i_1 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(\addr_reg[4]_i_2_n_0 ),
        .I5(index[0]),
        .O(\addr_reg[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FCCFFF01)) 
    \addr_reg[4]_i_1 
       (.I0(\addr_reg[4]_i_2_n_0 ),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[3]),
        .I5(index[4]),
        .O(\addr_reg[4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \addr_reg[4]_i_2 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .O(\addr_reg[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00001A1A0F0F0F0A)) 
    \addr_reg[5]_i_1 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000011545554)) 
    \addr_reg[6]_i_1 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(mode),
        .I3(index[3]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\addr_reg[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5422262254222633)) 
    \addr_reg[7]_i_1 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2_n_0 ),
        .O(\addr_reg[7]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hCE)) 
    \addr_reg[7]_i_2 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .I2(index[0]),
        .O(\addr_reg[7]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[0]_i_1_n_0 ),
        .Q(\addr_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[1]_i_1_n_0 ),
        .Q(\addr_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[2]_i_1_n_0 ),
        .Q(\addr_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[3]_i_1_n_0 ),
        .Q(\addr_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[4]_i_1_n_0 ),
        .Q(\addr_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[5]_i_1_n_0 ),
        .Q(\addr_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[6]_i_1_n_0 ),
        .Q(\addr_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[7]_i_1_n_0 ),
        .Q(\addr_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'hB8B8B8BBB8B8B888)) 
    \di_reg[0]_i_2 
       (.I0(\di_reg[0]_i_4_n_0 ),
        .I1(index[3]),
        .I2(do_reg2[0]),
        .I3(\di_reg[0]_i_5_n_0 ),
        .I4(\di_reg[0]_i_6_n_0 ),
        .I5(\di_reg[4]_i_8_n_0 ),
        .O(\di_reg[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00003414)) 
    \di_reg[0]_i_3 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[0]),
        .I4(index[3]),
        .O(\di_reg[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hB0BFFFFFB0B00000)) 
    \di_reg[0]_i_4 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(do_reg2[0]),
        .O(\di_reg[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \di_reg[0]_i_5 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .O(\di_reg[0]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \di_reg[0]_i_6 
       (.I0(index[1]),
        .I1(mode),
        .I2(index[0]),
        .O(\di_reg[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[10]_i_1 
       (.I0(index[4]),
        .I1(do_reg2[10]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[10]_i_2_n_0 ),
        .O(di_reg[10]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[10]_i_2 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[11]_i_1 
       (.I0(index[3]),
        .I1(\di_reg[11]_i_2_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[11]_i_3_n_0 ),
        .I4(\di_reg[11]_i_4_n_0 ),
        .I5(\di_reg[11]_i_5_n_0 ),
        .O(di_reg[11]));
  LUT6 #(
    .INIT(64'h0808080808380808)) 
    \di_reg[11]_i_2 
       (.I0(do_reg2[11]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[0]),
        .I4(rate_reg2[1]),
        .I5(index[0]),
        .O(\di_reg[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCC0CCC0C0C0C880C)) 
    \di_reg[11]_i_3 
       (.I0(data15),
        .I1(index[3]),
        .I2(do_reg2[11]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAAAAAABAAABA)) 
    \di_reg[11]_i_4 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAA00AAAAAAA3)) 
    \di_reg[11]_i_5 
       (.I0(do_reg2[11]),
        .I1(x16_reg2),
        .I2(\addr_reg[4]_i_2_n_0 ),
        .I3(index[0]),
        .I4(index[1]),
        .I5(index[2]),
        .O(\di_reg[11]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \di_reg[12]_i_1 
       (.I0(\di_reg[12]_i_2_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[12]_i_3_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[12]_i_4_n_0 ),
        .O(di_reg[12]));
  LUT5 #(
    .INIT(32'h00003202)) 
    \di_reg[12]_i_2 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[12]),
        .I4(index[3]),
        .O(\di_reg[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[12]_i_3 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[12]),
        .O(\di_reg[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAA8AAABAAABA)) 
    \di_reg[12]_i_4 
       (.I0(do_reg2[12]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[12]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \di_reg[13]_i_1 
       (.I0(\di_reg[13]_i_2_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[13]_i_3_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[13]_i_4_n_0 ),
        .O(di_reg[13]));
  LUT6 #(
    .INIT(64'h0808080838380838)) 
    \di_reg[13]_i_2 
       (.I0(do_reg2[13]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[13]_i_3 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[13]),
        .O(\di_reg[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAA8AAA8AAABAAA8A)) 
    \di_reg[13]_i_4 
       (.I0(do_reg2[13]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[1]),
        .I5(rate_reg2[0]),
        .O(\di_reg[13]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h080008FF08000800)) 
    \di_reg[14]_i_1 
       (.I0(do_reg2[14]),
        .I1(\di_reg[14]_i_2_n_0 ),
        .I2(index[3]),
        .I3(index[4]),
        .I4(\di_reg[14]_i_3_n_0 ),
        .I5(\di_reg[14]_i_4_n_0 ),
        .O(di_reg[14]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_2 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0033303310130033)) 
    \di_reg[14]_i_3 
       (.I0(data15),
        .I1(index[3]),
        .I2(index[2]),
        .I3(do_reg2[14]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000DF10)) 
    \di_reg[14]_i_4 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(do_reg2[14]),
        .I4(index[2]),
        .I5(\di_reg[14]_i_6_n_0 ),
        .O(\di_reg[14]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_5 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .O(data15));
  LUT6 #(
    .INIT(64'hBBBB3BBBBBBB3FBB)) 
    \di_reg[14]_i_6 
       (.I0(\di_reg[14]_i_7_n_0 ),
        .I1(index[3]),
        .I2(index[0]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(\di_reg[5]_i_4_n_0 ),
        .O(\di_reg[14]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h4440)) 
    \di_reg[14]_i_7 
       (.I0(index[1]),
        .I1(index[2]),
        .I2(do_reg2[14]),
        .I3(index[0]),
        .O(\di_reg[14]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[15]_i_1 
       (.I0(index[4]),
        .I1(do_reg2[15]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[15]_i_2_n_0 ),
        .O(di_reg[15]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[15]_i_2 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[15]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hABAA)) 
    \di_reg[1]_i_1 
       (.I0(\di_reg[1]_i_2_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[1]_i_3_n_0 ),
        .I3(\di_reg[1]_i_4_n_0 ),
        .O(di_reg[1]));
  LUT6 #(
    .INIT(64'h0000000034140000)) 
    \di_reg[1]_i_2 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[1]),
        .I4(index[4]),
        .I5(index[3]),
        .O(\di_reg[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FB330000)) 
    \di_reg[1]_i_3 
       (.I0(index[2]),
        .I1(do_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[3]),
        .I5(\di_reg[1]_i_5_n_0 ),
        .O(\di_reg[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFCCC5555)) 
    \di_reg[1]_i_4 
       (.I0(\di_reg[1]_i_6_n_0 ),
        .I1(do_reg2[1]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\di_reg[1]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \di_reg[1]_i_5 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .I3(index[1]),
        .O(\di_reg[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h002F0F20F02FFF2F)) 
    \di_reg[1]_i_6 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(mode),
        .I5(do_reg2[1]),
        .O(\di_reg[1]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[2]_i_1 
       (.I0(\di_reg[2]_i_2_n_0 ),
        .I1(\di_reg[2]_i_3_n_0 ),
        .O(di_reg[2]));
  LUT6 #(
    .INIT(64'h00400500FFFFFFFF)) 
    \di_reg[2]_i_2 
       (.I0(index[3]),
        .I1(do_reg2[2]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\di_reg[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF470047)) 
    \di_reg[2]_i_3 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(\di_reg[2]_i_4_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[2]_i_5_n_0 ),
        .I5(index[4]),
        .O(\di_reg[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hF4F40404F00FF000)) 
    \di_reg[2]_i_4 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(mode),
        .I4(do_reg2[2]),
        .I5(index[1]),
        .O(\di_reg[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hF5D535D5F5D5F5D5)) 
    \di_reg[2]_i_5 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hBAAA1000AAFF0000)) 
    \di_reg[3]_i_2 
       (.I0(\di_reg[3]_i_4_n_0 ),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(do_reg2[3]),
        .I5(index[0]),
        .O(\di_reg[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000033E200)) 
    \di_reg[3]_i_3 
       (.I0(data15),
        .I1(index[0]),
        .I2(do_reg2[3]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\di_reg[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[3]_i_4 
       (.I0(index[3]),
        .I1(index[1]),
        .O(\di_reg[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[4]_i_1 
       (.I0(index[3]),
        .I1(\di_reg[4]_i_2_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[4]_i_3_n_0 ),
        .I4(\di_reg[4]_i_4_n_0 ),
        .I5(\di_reg[4]_i_5_n_0 ),
        .O(di_reg[4]));
  LUT6 #(
    .INIT(64'h08080B0830303030)) 
    \di_reg[4]_i_2 
       (.I0(do_reg2[4]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DFFFFFFF)) 
    \di_reg[4]_i_3 
       (.I0(index[0]),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\di_reg[4]_i_6_n_0 ),
        .O(\di_reg[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FFFFE00000000)) 
    \di_reg[4]_i_4 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(do_reg2[4]),
        .O(\di_reg[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010C00)) 
    \di_reg[4]_i_5 
       (.I0(\di_reg[4]_i_7_n_0 ),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(\di_reg[4]_i_8_n_0 ),
        .I5(index[3]),
        .O(\di_reg[4]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h1F0FFF0F)) 
    \di_reg[4]_i_6 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(do_reg2[4]),
        .I4(index[1]),
        .O(\di_reg[4]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \di_reg[4]_i_7 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .O(\di_reg[4]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \di_reg[4]_i_8 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .O(\di_reg[4]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h33000000B888B888)) 
    \di_reg[5]_i_1 
       (.I0(\di_reg[5]_i_2_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[5]_i_3_n_0 ),
        .I3(do_reg2[5]),
        .I4(\di_reg[5]_i_4_n_0 ),
        .I5(index[3]),
        .O(di_reg[5]));
  LUT6 #(
    .INIT(64'h0B0B080B33333033)) 
    \di_reg[5]_i_2 
       (.I0(do_reg2[5]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \di_reg[5]_i_3 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(x16x20_mode_reg2),
        .I4(mode),
        .O(\di_reg[5]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[5]_i_4 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h67FF000067000000)) 
    \di_reg[6]_i_2 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[6]),
        .I5(\di_reg[5]_i_3_n_0 ),
        .O(\di_reg[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00002404)) 
    \di_reg[6]_i_3 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[6]),
        .I4(index[3]),
        .O(\di_reg[6]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF0900)) 
    \di_reg[7]_i_2 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[7]),
        .O(\di_reg[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000C320032)) 
    \di_reg[7]_i_3 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(do_reg2[7]),
        .I5(index[3]),
        .O(\di_reg[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[8]_i_1 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[8]),
        .O(di_reg[8]));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[9]_i_1 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[9]),
        .O(di_reg[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[0]),
        .Q(\di_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[0]_i_1 
       (.I0(\di_reg[0]_i_2_n_0 ),
        .I1(\di_reg[0]_i_3_n_0 ),
        .O(di_reg[0]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[10]),
        .Q(\di_reg_reg_n_0_[10] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[11]),
        .Q(\di_reg_reg_n_0_[11] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[12]),
        .Q(\di_reg_reg_n_0_[12] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[13]),
        .Q(\di_reg_reg_n_0_[13] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[14]),
        .Q(\di_reg_reg_n_0_[14] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[15]),
        .Q(\di_reg_reg_n_0_[15] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[1]),
        .Q(\di_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[2]),
        .Q(\di_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[3]),
        .Q(\di_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[3]_i_1 
       (.I0(\di_reg[3]_i_2_n_0 ),
        .I1(\di_reg[3]_i_3_n_0 ),
        .O(di_reg[3]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[4]),
        .Q(\di_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[5]),
        .Q(\di_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[6]),
        .Q(\di_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[6]_i_1 
       (.I0(\di_reg[6]_i_2_n_0 ),
        .I1(\di_reg[6]_i_3_n_0 ),
        .O(di_reg[6]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[7]),
        .Q(\di_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[7]_i_1 
       (.I0(\di_reg[7]_i_2_n_0 ),
        .I1(\di_reg[7]_i_3_n_0 ),
        .O(di_reg[7]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[8]),
        .Q(\di_reg_reg_n_0_[8] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[9]),
        .Q(\di_reg_reg_n_0_[9] ),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[0]),
        .Q(do_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[10]),
        .Q(do_reg1[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[11]),
        .Q(do_reg1[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[12]),
        .Q(do_reg1[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[13]),
        .Q(do_reg1[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[14]),
        .Q(do_reg1[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[15]),
        .Q(do_reg1[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[1]),
        .Q(do_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[2]),
        .Q(do_reg1[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[3]),
        .Q(do_reg1[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[4]),
        .Q(do_reg1[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[5]),
        .Q(do_reg1[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[6]),
        .Q(do_reg1[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[7]),
        .Q(do_reg1[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[8]),
        .Q(do_reg1[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[9]),
        .Q(do_reg1[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(RST_DCLK_RESET));
  LUT4 #(
    .INIT(16'h0001)) 
    done_i_1
       (.I0(start_reg2),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(done_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(done_i_1_n_0),
        .Q(DRP_DONE),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0B3BFFFF0B3B0000)) 
    \fsm[0]_i_1__0 
       (.I0(data4),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(rdy_reg2),
        .I4(Q[2]),
        .I5(\fsm[0]_i_3__0_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT5 #(
    .INIT(32'hEFFEFFFF)) 
    \fsm[0]_i_2 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[4]),
        .I3(index[2]),
        .I4(mode_i_2_n_0),
        .O(data4));
  LUT6 #(
    .INIT(64'h7477FFFF7477CCCC)) 
    \fsm[0]_i_3__0 
       (.I0(rdy_reg2),
        .I1(Q[1]),
        .I2(load_cnt[1]),
        .I3(load_cnt[0]),
        .I4(Q[0]),
        .I5(start_reg2),
        .O(\fsm[0]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h185018501D501850)) 
    \fsm[1]_i_1 
       (.I0(Q[2]),
        .I1(rdy_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(load_cnt[0]),
        .I5(load_cnt[1]),
        .O(fsm[1]));
  LUT4 #(
    .INIT(16'h6222)) 
    \fsm[2]_i_1__0 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(rdy_reg2),
        .I3(Q[0]),
        .O(fsm[2]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \gt_ch_drp_rdy[0]_INST_0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(gt_ch_drp_rdy));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_14__3 
       (.I0(ext_ch_gt_drpdi[15]),
        .I1(\di_reg_reg_n_0_[15] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[15]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_15 
       (.I0(ext_ch_gt_drpdi[14]),
        .I1(\di_reg_reg_n_0_[14] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[14]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_16 
       (.I0(ext_ch_gt_drpdi[13]),
        .I1(\di_reg_reg_n_0_[13] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[13]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_17 
       (.I0(ext_ch_gt_drpdi[12]),
        .I1(\di_reg_reg_n_0_[12] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[12]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_18 
       (.I0(ext_ch_gt_drpdi[11]),
        .I1(\di_reg_reg_n_0_[11] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[11]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_19 
       (.I0(ext_ch_gt_drpdi[10]),
        .I1(\di_reg_reg_n_0_[10] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[10]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_20 
       (.I0(ext_ch_gt_drpdi[9]),
        .I1(\di_reg_reg_n_0_[9] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[9]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_21 
       (.I0(ext_ch_gt_drpdi[8]),
        .I1(\di_reg_reg_n_0_[8] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_22 
       (.I0(ext_ch_gt_drpdi[7]),
        .I1(\di_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_23 
       (.I0(ext_ch_gt_drpdi[6]),
        .I1(\di_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[6]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_24 
       (.I0(ext_ch_gt_drpdi[5]),
        .I1(\di_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_25 
       (.I0(ext_ch_gt_drpdi[4]),
        .I1(\di_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_26 
       (.I0(ext_ch_gt_drpdi[3]),
        .I1(\di_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_27 
       (.I0(ext_ch_gt_drpdi[2]),
        .I1(\di_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_28 
       (.I0(ext_ch_gt_drpdi[1]),
        .I1(\di_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_29 
       (.I0(ext_ch_gt_drpdi[0]),
        .I1(\di_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[0]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT4 #(
    .INIT(16'h003E)) 
    \gtx_channel.gtxe2_channel_i_i_3 
       (.I0(ext_ch_gt_drpen),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\cplllock_reg1_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT4 #(
    .INIT(16'h0032)) 
    \gtx_channel.gtxe2_channel_i_i_4 
       (.I0(ext_ch_gt_drpwe),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(\cplllock_reg1_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_47__3 
       (.I0(ext_ch_gt_drpaddr[8]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(DRPADDR[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_48 
       (.I0(ext_ch_gt_drpaddr[7]),
        .I1(\addr_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_49 
       (.I0(ext_ch_gt_drpaddr[6]),
        .I1(\addr_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[6]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_50 
       (.I0(ext_ch_gt_drpaddr[5]),
        .I1(\addr_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_51 
       (.I0(ext_ch_gt_drpaddr[4]),
        .I1(\addr_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_52 
       (.I0(ext_ch_gt_drpaddr[3]),
        .I1(\addr_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_53 
       (.I0(ext_ch_gt_drpaddr[2]),
        .I1(\addr_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_54 
       (.I0(ext_ch_gt_drpaddr[1]),
        .I1(\addr_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_55 
       (.I0(ext_ch_gt_drpaddr[0]),
        .I1(\addr_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[0]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_GTXRESET),
        .Q(gtxreset_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(gtxreset_reg1),
        .Q(gtxreset_reg2),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \index[0]_i_1__1 
       (.I0(index[0]),
        .I1(Q[2]),
        .I2(\index[3]_i_2_n_0 ),
        .O(\index[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT4 #(
    .INIT(16'h0220)) 
    \index[1]_i_1__1 
       (.I0(Q[2]),
        .I1(\index[3]_i_2_n_0 ),
        .I2(index[1]),
        .I3(index[0]),
        .O(\index[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT5 #(
    .INIT(32'h02222000)) 
    \index[2]_i_1__1 
       (.I0(Q[2]),
        .I1(\index[3]_i_2_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .O(\index[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0222222220000000)) 
    \index[3]_i_1 
       (.I0(Q[2]),
        .I1(\index[3]_i_2_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\index[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAE)) 
    \index[3]_i_2 
       (.I0(Q[0]),
        .I1(mode_i_2_n_0),
        .I2(index[2]),
        .I3(index[4]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\index[3]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h89)) 
    \index[4]_i_1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\index[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \index[4]_i_2 
       (.I0(index[0]),
        .I1(index[2]),
        .I2(index[3]),
        .I3(index[1]),
        .I4(index[4]),
        .I5(\index[4]_i_3_n_0 ),
        .O(\index[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \index[4]_i_3 
       (.I0(\index[3]_i_2_n_0 ),
        .I1(Q[2]),
        .O(\index[4]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1_n_0 ),
        .D(\index[0]_i_1__1_n_0 ),
        .Q(index[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1_n_0 ),
        .D(\index[1]_i_1__1_n_0 ),
        .Q(index[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1_n_0 ),
        .D(\index[2]_i_1__1_n_0 ),
        .Q(index[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1_n_0 ),
        .D(\index[3]_i_1_n_0 ),
        .Q(index[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1_n_0 ),
        .D(\index[4]_i_2_n_0 ),
        .Q(index[4]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \load_cnt[0]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(load_cnt[1]),
        .I3(Q[2]),
        .O(\load_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1_n_0 ),
        .Q(load_cnt[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(load_cnt[1]),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h00AAA2AAAAAAAA00)) 
    mode_i_1
       (.I0(mode),
        .I1(mode_i_2_n_0),
        .I2(mode_i_3__1_n_0),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(mode_i_1_n_0));
  LUT4 #(
    .INIT(16'hCCB8)) 
    mode_i_2
       (.I0(mode),
        .I1(index[0]),
        .I2(x16x20_mode_reg2),
        .I3(index[2]),
        .O(mode_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    mode_i_3__1
       (.I0(index[2]),
        .I1(index[4]),
        .I2(index[1]),
        .I3(index[3]),
        .O(mode_i_3__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mode_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(mode_i_1_n_0),
        .Q(mode),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[0]),
        .Q(rate_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[1]),
        .Q(rate_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drprdy),
        .Q(rdy_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_START),
        .Q(start_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16),
        .Q(x16_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16_reg1),
        .Q(x16_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16X20_MODE),
        .Q(x16x20_mode_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16x20_mode_reg1),
        .Q(x16x20_mode_reg2),
        .R(RST_DCLK_RESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_drp" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_30
   (Q,
    DRPADDR,
    \cplllock_reg1_reg[1] ,
    \cplllock_reg1_reg[1]_0 ,
    gt_ch_drp_rdy,
    DRPDI,
    DRP_DONE,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi,
    RST_DCLK_RESET,
    DRP_X16X20_MODE,
    \resetovrd_disble.reset_reg[4] ,
    DRP_START,
    ext_ch_gt_drprdy,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    DRP_X16,
    ext_ch_gt_drpdo,
    rst_gtreset);
  output [2:0]Q;
  output [8:0]DRPADDR;
  output \cplllock_reg1_reg[1] ;
  output \cplllock_reg1_reg[1]_0 ;
  output [0:0]gt_ch_drp_rdy;
  output [15:0]DRPDI;
  output DRP_DONE;
  input [8:0]ext_ch_gt_drpaddr;
  input [0:0]ext_ch_gt_drpen;
  input [0:0]ext_ch_gt_drpwe;
  input [15:0]ext_ch_gt_drpdi;
  input RST_DCLK_RESET;
  input DRP_X16X20_MODE;
  input \resetovrd_disble.reset_reg[4] ;
  input DRP_START;
  input [0:0]ext_ch_gt_drprdy;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input DRP_X16;
  input [15:0]ext_ch_gt_drpdo;
  input rst_gtreset;

  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_DONE;
  wire DRP_START;
  wire DRP_X16;
  wire DRP_X16X20_MODE;
  wire [2:0]Q;
  wire RST_DCLK_RESET;
  wire \addr_reg[0]_i_1__0_n_0 ;
  wire \addr_reg[1]_i_1__0_n_0 ;
  wire \addr_reg[2]_i_1__0_n_0 ;
  wire \addr_reg[3]_i_1__0_n_0 ;
  wire \addr_reg[4]_i_1__0_n_0 ;
  wire \addr_reg[4]_i_2__0_n_0 ;
  wire \addr_reg[5]_i_1__0_n_0 ;
  wire \addr_reg[6]_i_1__0_n_0 ;
  wire \addr_reg[7]_i_1__0_n_0 ;
  wire \addr_reg[7]_i_2__0_n_0 ;
  wire \addr_reg_reg_n_0_[0] ;
  wire \addr_reg_reg_n_0_[1] ;
  wire \addr_reg_reg_n_0_[2] ;
  wire \addr_reg_reg_n_0_[3] ;
  wire \addr_reg_reg_n_0_[4] ;
  wire \addr_reg_reg_n_0_[5] ;
  wire \addr_reg_reg_n_0_[6] ;
  wire \addr_reg_reg_n_0_[7] ;
  wire \cplllock_reg1_reg[1] ;
  wire \cplllock_reg1_reg[1]_0 ;
  wire [7:7]data15;
  wire data4;
  wire [15:0]di_reg;
  wire \di_reg[0]_i_2__0_n_0 ;
  wire \di_reg[0]_i_3__0_n_0 ;
  wire \di_reg[0]_i_4__0_n_0 ;
  wire \di_reg[0]_i_5__0_n_0 ;
  wire \di_reg[0]_i_6__0_n_0 ;
  wire \di_reg[10]_i_2__0_n_0 ;
  wire \di_reg[11]_i_2__0_n_0 ;
  wire \di_reg[11]_i_3__0_n_0 ;
  wire \di_reg[11]_i_4__0_n_0 ;
  wire \di_reg[11]_i_5__0_n_0 ;
  wire \di_reg[12]_i_2__0_n_0 ;
  wire \di_reg[12]_i_3__0_n_0 ;
  wire \di_reg[12]_i_4__0_n_0 ;
  wire \di_reg[13]_i_2__0_n_0 ;
  wire \di_reg[13]_i_3__0_n_0 ;
  wire \di_reg[13]_i_4__0_n_0 ;
  wire \di_reg[14]_i_2__0_n_0 ;
  wire \di_reg[14]_i_3__0_n_0 ;
  wire \di_reg[14]_i_4__0_n_0 ;
  wire \di_reg[14]_i_6__0_n_0 ;
  wire \di_reg[14]_i_7__0_n_0 ;
  wire \di_reg[15]_i_2__0_n_0 ;
  wire \di_reg[1]_i_2__0_n_0 ;
  wire \di_reg[1]_i_3__0_n_0 ;
  wire \di_reg[1]_i_4__0_n_0 ;
  wire \di_reg[1]_i_5__0_n_0 ;
  wire \di_reg[1]_i_6__0_n_0 ;
  wire \di_reg[2]_i_2__0_n_0 ;
  wire \di_reg[2]_i_3__0_n_0 ;
  wire \di_reg[2]_i_4__0_n_0 ;
  wire \di_reg[2]_i_5__0_n_0 ;
  wire \di_reg[3]_i_2__0_n_0 ;
  wire \di_reg[3]_i_3__0_n_0 ;
  wire \di_reg[3]_i_4__0_n_0 ;
  wire \di_reg[4]_i_2__0_n_0 ;
  wire \di_reg[4]_i_3__0_n_0 ;
  wire \di_reg[4]_i_4__0_n_0 ;
  wire \di_reg[4]_i_5__0_n_0 ;
  wire \di_reg[4]_i_6__0_n_0 ;
  wire \di_reg[4]_i_7__0_n_0 ;
  wire \di_reg[4]_i_8__0_n_0 ;
  wire \di_reg[5]_i_2__0_n_0 ;
  wire \di_reg[5]_i_3__0_n_0 ;
  wire \di_reg[5]_i_4__0_n_0 ;
  wire \di_reg[6]_i_2__0_n_0 ;
  wire \di_reg[6]_i_3__0_n_0 ;
  wire \di_reg[7]_i_2__0_n_0 ;
  wire \di_reg[7]_i_3__0_n_0 ;
  wire \di_reg_reg_n_0_[0] ;
  wire \di_reg_reg_n_0_[10] ;
  wire \di_reg_reg_n_0_[11] ;
  wire \di_reg_reg_n_0_[12] ;
  wire \di_reg_reg_n_0_[13] ;
  wire \di_reg_reg_n_0_[14] ;
  wire \di_reg_reg_n_0_[15] ;
  wire \di_reg_reg_n_0_[1] ;
  wire \di_reg_reg_n_0_[2] ;
  wire \di_reg_reg_n_0_[3] ;
  wire \di_reg_reg_n_0_[4] ;
  wire \di_reg_reg_n_0_[5] ;
  wire \di_reg_reg_n_0_[6] ;
  wire \di_reg_reg_n_0_[7] ;
  wire \di_reg_reg_n_0_[8] ;
  wire \di_reg_reg_n_0_[9] ;
  wire [15:0]do_reg1;
  wire [15:0]do_reg2;
  wire done_i_1__0_n_0;
  wire [8:0]ext_ch_gt_drpaddr;
  wire [15:0]ext_ch_gt_drpdi;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drpen;
  wire [0:0]ext_ch_gt_drprdy;
  wire [0:0]ext_ch_gt_drpwe;
  wire [2:0]fsm;
  wire \fsm[0]_i_3__2_n_0 ;
  wire [0:0]gt_ch_drp_rdy;
  wire gtxreset_reg1;
  wire gtxreset_reg2;
  wire [4:0]index;
  wire \index[0]_i_1__2_n_0 ;
  wire \index[1]_i_1__2_n_0 ;
  wire \index[2]_i_1__2_n_0 ;
  wire \index[3]_i_1__0_n_0 ;
  wire \index[3]_i_2__0_n_0 ;
  wire \index[4]_i_1__0_n_0 ;
  wire \index[4]_i_2__0_n_0 ;
  wire \index[4]_i_3__0_n_0 ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1__1_n_0 ;
  wire mode;
  wire mode_i_1__0_n_0;
  wire mode_i_2__0_n_0;
  wire mode_i_3__2_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire [1:0]rate_reg1;
  wire [1:0]rate_reg2;
  wire rdy_reg1;
  wire rdy_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_gtreset;
  wire start_reg1;
  wire start_reg2;
  wire x16_reg1;
  wire x16_reg2;
  wire x16x20_mode_reg1;
  wire x16x20_mode_reg2;

  LUT6 #(
    .INIT(64'h1471357514713564)) 
    \addr_reg[0]_i_1__0 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__0_n_0 ),
        .O(\addr_reg[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h404050500F0F0500)) 
    \addr_reg[1]_i_1__0 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h051005105A055A00)) 
    \addr_reg[2]_i_1__0 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(index[2]),
        .I4(mode),
        .I5(index[1]),
        .O(\addr_reg[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h5767576753275326)) 
    \addr_reg[3]_i_1__0 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(\addr_reg[4]_i_2__0_n_0 ),
        .I5(index[0]),
        .O(\addr_reg[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FCCFFF01)) 
    \addr_reg[4]_i_1__0 
       (.I0(\addr_reg[4]_i_2__0_n_0 ),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[3]),
        .I5(index[4]),
        .O(\addr_reg[4]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \addr_reg[4]_i_2__0 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .O(\addr_reg[4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00001A1A0F0F0F0A)) 
    \addr_reg[5]_i_1__0 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000011545554)) 
    \addr_reg[6]_i_1__0 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(mode),
        .I3(index[3]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\addr_reg[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h5422262254222633)) 
    \addr_reg[7]_i_1__0 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__0_n_0 ),
        .O(\addr_reg[7]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hCE)) 
    \addr_reg[7]_i_2__0 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .I2(index[0]),
        .O(\addr_reg[7]_i_2__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[0]_i_1__0_n_0 ),
        .Q(\addr_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[1]_i_1__0_n_0 ),
        .Q(\addr_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[2]_i_1__0_n_0 ),
        .Q(\addr_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[3]_i_1__0_n_0 ),
        .Q(\addr_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[4]_i_1__0_n_0 ),
        .Q(\addr_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[5]_i_1__0_n_0 ),
        .Q(\addr_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[6]_i_1__0_n_0 ),
        .Q(\addr_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[7]_i_1__0_n_0 ),
        .Q(\addr_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'hB8B8B8BBB8B8B888)) 
    \di_reg[0]_i_2__0 
       (.I0(\di_reg[0]_i_4__0_n_0 ),
        .I1(index[3]),
        .I2(do_reg2[0]),
        .I3(\di_reg[0]_i_5__0_n_0 ),
        .I4(\di_reg[0]_i_6__0_n_0 ),
        .I5(\di_reg[4]_i_8__0_n_0 ),
        .O(\di_reg[0]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00003414)) 
    \di_reg[0]_i_3__0 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[0]),
        .I4(index[3]),
        .O(\di_reg[0]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hB0BFFFFFB0B00000)) 
    \di_reg[0]_i_4__0 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(do_reg2[0]),
        .O(\di_reg[0]_i_4__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \di_reg[0]_i_5__0 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .O(\di_reg[0]_i_5__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \di_reg[0]_i_6__0 
       (.I0(index[1]),
        .I1(mode),
        .I2(index[0]),
        .O(\di_reg[0]_i_6__0_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[10]_i_1__0 
       (.I0(index[4]),
        .I1(do_reg2[10]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[10]_i_2__0_n_0 ),
        .O(di_reg[10]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[10]_i_2__0 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[10]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[11]_i_1__0 
       (.I0(index[3]),
        .I1(\di_reg[11]_i_2__0_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[11]_i_3__0_n_0 ),
        .I4(\di_reg[11]_i_4__0_n_0 ),
        .I5(\di_reg[11]_i_5__0_n_0 ),
        .O(di_reg[11]));
  LUT6 #(
    .INIT(64'h0808080808380808)) 
    \di_reg[11]_i_2__0 
       (.I0(do_reg2[11]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[0]),
        .I4(rate_reg2[1]),
        .I5(index[0]),
        .O(\di_reg[11]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hCC0CCC0C0C0C880C)) 
    \di_reg[11]_i_3__0 
       (.I0(data15),
        .I1(index[3]),
        .I2(do_reg2[11]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[11]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAAAAAABAAABA)) 
    \di_reg[11]_i_4__0 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[11]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAA00AAAAAAA3)) 
    \di_reg[11]_i_5__0 
       (.I0(do_reg2[11]),
        .I1(x16_reg2),
        .I2(\addr_reg[4]_i_2__0_n_0 ),
        .I3(index[0]),
        .I4(index[1]),
        .I5(index[2]),
        .O(\di_reg[11]_i_5__0_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \di_reg[12]_i_1__0 
       (.I0(\di_reg[12]_i_2__0_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[12]_i_3__0_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[12]_i_4__0_n_0 ),
        .O(di_reg[12]));
  LUT5 #(
    .INIT(32'h00003202)) 
    \di_reg[12]_i_2__0 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[12]),
        .I4(index[3]),
        .O(\di_reg[12]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[12]_i_3__0 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[12]),
        .O(\di_reg[12]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAA8AAABAAABA)) 
    \di_reg[12]_i_4__0 
       (.I0(do_reg2[12]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[12]_i_4__0_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \di_reg[13]_i_1__0 
       (.I0(\di_reg[13]_i_2__0_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[13]_i_3__0_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[13]_i_4__0_n_0 ),
        .O(di_reg[13]));
  LUT6 #(
    .INIT(64'h0808080838380838)) 
    \di_reg[13]_i_2__0 
       (.I0(do_reg2[13]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[13]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[13]_i_3__0 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[13]),
        .O(\di_reg[13]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hAA8AAA8AAABAAA8A)) 
    \di_reg[13]_i_4__0 
       (.I0(do_reg2[13]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[1]),
        .I5(rate_reg2[0]),
        .O(\di_reg[13]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h080008FF08000800)) 
    \di_reg[14]_i_1__0 
       (.I0(do_reg2[14]),
        .I1(\di_reg[14]_i_2__0_n_0 ),
        .I2(index[3]),
        .I3(index[4]),
        .I4(\di_reg[14]_i_3__0_n_0 ),
        .I5(\di_reg[14]_i_4__0_n_0 ),
        .O(di_reg[14]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_2__0 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[14]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0033303310130033)) 
    \di_reg[14]_i_3__0 
       (.I0(data15),
        .I1(index[3]),
        .I2(index[2]),
        .I3(do_reg2[14]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[14]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000DF10)) 
    \di_reg[14]_i_4__0 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(do_reg2[14]),
        .I4(index[2]),
        .I5(\di_reg[14]_i_6__0_n_0 ),
        .O(\di_reg[14]_i_4__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_5__0 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .O(data15));
  LUT6 #(
    .INIT(64'hBBBB3BBBBBBB3FBB)) 
    \di_reg[14]_i_6__0 
       (.I0(\di_reg[14]_i_7__0_n_0 ),
        .I1(index[3]),
        .I2(index[0]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(\di_reg[5]_i_4__0_n_0 ),
        .O(\di_reg[14]_i_6__0_n_0 ));
  LUT4 #(
    .INIT(16'h4440)) 
    \di_reg[14]_i_7__0 
       (.I0(index[1]),
        .I1(index[2]),
        .I2(do_reg2[14]),
        .I3(index[0]),
        .O(\di_reg[14]_i_7__0_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[15]_i_1__0 
       (.I0(index[4]),
        .I1(do_reg2[15]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[15]_i_2__0_n_0 ),
        .O(di_reg[15]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[15]_i_2__0 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[15]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'hABAA)) 
    \di_reg[1]_i_1__0 
       (.I0(\di_reg[1]_i_2__0_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[1]_i_3__0_n_0 ),
        .I3(\di_reg[1]_i_4__0_n_0 ),
        .O(di_reg[1]));
  LUT6 #(
    .INIT(64'h0000000034140000)) 
    \di_reg[1]_i_2__0 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[1]),
        .I4(index[4]),
        .I5(index[3]),
        .O(\di_reg[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FB330000)) 
    \di_reg[1]_i_3__0 
       (.I0(index[2]),
        .I1(do_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[3]),
        .I5(\di_reg[1]_i_5__0_n_0 ),
        .O(\di_reg[1]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFCCC5555)) 
    \di_reg[1]_i_4__0 
       (.I0(\di_reg[1]_i_6__0_n_0 ),
        .I1(do_reg2[1]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\di_reg[1]_i_4__0_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \di_reg[1]_i_5__0 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .I3(index[1]),
        .O(\di_reg[1]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'h002F0F20F02FFF2F)) 
    \di_reg[1]_i_6__0 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(mode),
        .I5(do_reg2[1]),
        .O(\di_reg[1]_i_6__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[2]_i_1__0 
       (.I0(\di_reg[2]_i_2__0_n_0 ),
        .I1(\di_reg[2]_i_3__0_n_0 ),
        .O(di_reg[2]));
  LUT6 #(
    .INIT(64'h00400500FFFFFFFF)) 
    \di_reg[2]_i_2__0 
       (.I0(index[3]),
        .I1(do_reg2[2]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\di_reg[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF470047)) 
    \di_reg[2]_i_3__0 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(\di_reg[2]_i_4__0_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[2]_i_5__0_n_0 ),
        .I5(index[4]),
        .O(\di_reg[2]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hF4F40404F00FF000)) 
    \di_reg[2]_i_4__0 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(mode),
        .I4(do_reg2[2]),
        .I5(index[1]),
        .O(\di_reg[2]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'hF5D535D5F5D5F5D5)) 
    \di_reg[2]_i_5__0 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[2]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'hBAAA1000AAFF0000)) 
    \di_reg[3]_i_2__0 
       (.I0(\di_reg[3]_i_4__0_n_0 ),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(do_reg2[3]),
        .I5(index[0]),
        .O(\di_reg[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h000000000033E200)) 
    \di_reg[3]_i_3__0 
       (.I0(data15),
        .I1(index[0]),
        .I2(do_reg2[3]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\di_reg[3]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[3]_i_4__0 
       (.I0(index[3]),
        .I1(index[1]),
        .O(\di_reg[3]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[4]_i_1__0 
       (.I0(index[3]),
        .I1(\di_reg[4]_i_2__0_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[4]_i_3__0_n_0 ),
        .I4(\di_reg[4]_i_4__0_n_0 ),
        .I5(\di_reg[4]_i_5__0_n_0 ),
        .O(di_reg[4]));
  LUT6 #(
    .INIT(64'h08080B0830303030)) 
    \di_reg[4]_i_2__0 
       (.I0(do_reg2[4]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DFFFFFFF)) 
    \di_reg[4]_i_3__0 
       (.I0(index[0]),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\di_reg[4]_i_6__0_n_0 ),
        .O(\di_reg[4]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FFFFE00000000)) 
    \di_reg[4]_i_4__0 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(do_reg2[4]),
        .O(\di_reg[4]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010C00)) 
    \di_reg[4]_i_5__0 
       (.I0(\di_reg[4]_i_7__0_n_0 ),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(\di_reg[4]_i_8__0_n_0 ),
        .I5(index[3]),
        .O(\di_reg[4]_i_5__0_n_0 ));
  LUT5 #(
    .INIT(32'h1F0FFF0F)) 
    \di_reg[4]_i_6__0 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(do_reg2[4]),
        .I4(index[1]),
        .O(\di_reg[4]_i_6__0_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \di_reg[4]_i_7__0 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .O(\di_reg[4]_i_7__0_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \di_reg[4]_i_8__0 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .O(\di_reg[4]_i_8__0_n_0 ));
  LUT6 #(
    .INIT(64'h33000000B888B888)) 
    \di_reg[5]_i_1__0 
       (.I0(\di_reg[5]_i_2__0_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[5]_i_3__0_n_0 ),
        .I3(do_reg2[5]),
        .I4(\di_reg[5]_i_4__0_n_0 ),
        .I5(index[3]),
        .O(di_reg[5]));
  LUT6 #(
    .INIT(64'h0B0B080B33333033)) 
    \di_reg[5]_i_2__0 
       (.I0(do_reg2[5]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[5]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \di_reg[5]_i_3__0 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(x16x20_mode_reg2),
        .I4(mode),
        .O(\di_reg[5]_i_3__0_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[5]_i_4__0 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[5]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h67FF000067000000)) 
    \di_reg[6]_i_2__0 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[6]),
        .I5(\di_reg[5]_i_3__0_n_0 ),
        .O(\di_reg[6]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00002404)) 
    \di_reg[6]_i_3__0 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[6]),
        .I4(index[3]),
        .O(\di_reg[6]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF0900)) 
    \di_reg[7]_i_2__0 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[7]),
        .O(\di_reg[7]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h000000000C320032)) 
    \di_reg[7]_i_3__0 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(do_reg2[7]),
        .I5(index[3]),
        .O(\di_reg[7]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[8]_i_1__0 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[8]),
        .O(di_reg[8]));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[9]_i_1__0 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[9]),
        .O(di_reg[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[0]),
        .Q(\di_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[0]_i_1__0 
       (.I0(\di_reg[0]_i_2__0_n_0 ),
        .I1(\di_reg[0]_i_3__0_n_0 ),
        .O(di_reg[0]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[10]),
        .Q(\di_reg_reg_n_0_[10] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[11]),
        .Q(\di_reg_reg_n_0_[11] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[12]),
        .Q(\di_reg_reg_n_0_[12] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[13]),
        .Q(\di_reg_reg_n_0_[13] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[14]),
        .Q(\di_reg_reg_n_0_[14] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[15]),
        .Q(\di_reg_reg_n_0_[15] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[1]),
        .Q(\di_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[2]),
        .Q(\di_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[3]),
        .Q(\di_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[3]_i_1__0 
       (.I0(\di_reg[3]_i_2__0_n_0 ),
        .I1(\di_reg[3]_i_3__0_n_0 ),
        .O(di_reg[3]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[4]),
        .Q(\di_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[5]),
        .Q(\di_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[6]),
        .Q(\di_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[6]_i_1__0 
       (.I0(\di_reg[6]_i_2__0_n_0 ),
        .I1(\di_reg[6]_i_3__0_n_0 ),
        .O(di_reg[6]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[7]),
        .Q(\di_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[7]_i_1__0 
       (.I0(\di_reg[7]_i_2__0_n_0 ),
        .I1(\di_reg[7]_i_3__0_n_0 ),
        .O(di_reg[7]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[8]),
        .Q(\di_reg_reg_n_0_[8] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[9]),
        .Q(\di_reg_reg_n_0_[9] ),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[0]),
        .Q(do_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[10]),
        .Q(do_reg1[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[11]),
        .Q(do_reg1[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[12]),
        .Q(do_reg1[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[13]),
        .Q(do_reg1[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[14]),
        .Q(do_reg1[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[15]),
        .Q(do_reg1[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[1]),
        .Q(do_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[2]),
        .Q(do_reg1[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[3]),
        .Q(do_reg1[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[4]),
        .Q(do_reg1[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[5]),
        .Q(do_reg1[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[6]),
        .Q(do_reg1[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[7]),
        .Q(do_reg1[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[8]),
        .Q(do_reg1[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[9]),
        .Q(do_reg1[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(RST_DCLK_RESET));
  LUT4 #(
    .INIT(16'h0001)) 
    done_i_1__0
       (.I0(start_reg2),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(done_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(done_i_1__0_n_0),
        .Q(DRP_DONE),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0B3BFFFF0B3B0000)) 
    \fsm[0]_i_1__2 
       (.I0(data4),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(rdy_reg2),
        .I4(Q[2]),
        .I5(\fsm[0]_i_3__2_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT5 #(
    .INIT(32'hEFFEFFFF)) 
    \fsm[0]_i_2__0 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[4]),
        .I3(index[2]),
        .I4(mode_i_2__0_n_0),
        .O(data4));
  LUT6 #(
    .INIT(64'h7477FFFF7477CCCC)) 
    \fsm[0]_i_3__2 
       (.I0(rdy_reg2),
        .I1(Q[1]),
        .I2(load_cnt[1]),
        .I3(load_cnt[0]),
        .I4(Q[0]),
        .I5(start_reg2),
        .O(\fsm[0]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'h185018501D501850)) 
    \fsm[1]_i_1__0 
       (.I0(Q[2]),
        .I1(rdy_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(load_cnt[0]),
        .I5(load_cnt[1]),
        .O(fsm[1]));
  LUT4 #(
    .INIT(16'h6222)) 
    \fsm[2]_i_1__2 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(rdy_reg2),
        .I3(Q[0]),
        .O(fsm[2]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \gt_ch_drp_rdy[1]_INST_0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(gt_ch_drp_rdy));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_14__4 
       (.I0(ext_ch_gt_drpdi[15]),
        .I1(\di_reg_reg_n_0_[15] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[15]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_15__0 
       (.I0(ext_ch_gt_drpdi[14]),
        .I1(\di_reg_reg_n_0_[14] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[14]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_16__0 
       (.I0(ext_ch_gt_drpdi[13]),
        .I1(\di_reg_reg_n_0_[13] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[13]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_17__0 
       (.I0(ext_ch_gt_drpdi[12]),
        .I1(\di_reg_reg_n_0_[12] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[12]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_18__0 
       (.I0(ext_ch_gt_drpdi[11]),
        .I1(\di_reg_reg_n_0_[11] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[11]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_19__0 
       (.I0(ext_ch_gt_drpdi[10]),
        .I1(\di_reg_reg_n_0_[10] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[10]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_20__0 
       (.I0(ext_ch_gt_drpdi[9]),
        .I1(\di_reg_reg_n_0_[9] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[9]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_21__0 
       (.I0(ext_ch_gt_drpdi[8]),
        .I1(\di_reg_reg_n_0_[8] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_22__0 
       (.I0(ext_ch_gt_drpdi[7]),
        .I1(\di_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_23__0 
       (.I0(ext_ch_gt_drpdi[6]),
        .I1(\di_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[6]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_24__0 
       (.I0(ext_ch_gt_drpdi[5]),
        .I1(\di_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_25__0 
       (.I0(ext_ch_gt_drpdi[4]),
        .I1(\di_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_26__0 
       (.I0(ext_ch_gt_drpdi[3]),
        .I1(\di_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_27__0 
       (.I0(ext_ch_gt_drpdi[2]),
        .I1(\di_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_28__0 
       (.I0(ext_ch_gt_drpdi[1]),
        .I1(\di_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_29__0 
       (.I0(ext_ch_gt_drpdi[0]),
        .I1(\di_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[0]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT4 #(
    .INIT(16'h003E)) 
    \gtx_channel.gtxe2_channel_i_i_3__0 
       (.I0(ext_ch_gt_drpen),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\cplllock_reg1_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_47__4 
       (.I0(ext_ch_gt_drpaddr[8]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(DRPADDR[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_48__0 
       (.I0(ext_ch_gt_drpaddr[7]),
        .I1(\addr_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_49__0 
       (.I0(ext_ch_gt_drpaddr[6]),
        .I1(\addr_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[6]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'h0032)) 
    \gtx_channel.gtxe2_channel_i_i_4__0 
       (.I0(ext_ch_gt_drpwe),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(\cplllock_reg1_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_50__0 
       (.I0(ext_ch_gt_drpaddr[5]),
        .I1(\addr_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_51__0 
       (.I0(ext_ch_gt_drpaddr[4]),
        .I1(\addr_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_52__0 
       (.I0(ext_ch_gt_drpaddr[3]),
        .I1(\addr_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_53__0 
       (.I0(ext_ch_gt_drpaddr[2]),
        .I1(\addr_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_54__0 
       (.I0(ext_ch_gt_drpaddr[1]),
        .I1(\addr_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_55__0 
       (.I0(ext_ch_gt_drpaddr[0]),
        .I1(\addr_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[0]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rst_gtreset),
        .Q(gtxreset_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(gtxreset_reg1),
        .Q(gtxreset_reg2),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \index[0]_i_1__2 
       (.I0(index[0]),
        .I1(Q[2]),
        .I2(\index[3]_i_2__0_n_0 ),
        .O(\index[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'h0220)) 
    \index[1]_i_1__2 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__0_n_0 ),
        .I2(index[1]),
        .I3(index[0]),
        .O(\index[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT5 #(
    .INIT(32'h02222000)) 
    \index[2]_i_1__2 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__0_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .O(\index[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0222222220000000)) 
    \index[3]_i_1__0 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__0_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\index[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAE)) 
    \index[3]_i_2__0 
       (.I0(Q[0]),
        .I1(mode_i_2__0_n_0),
        .I2(index[2]),
        .I3(index[4]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\index[3]_i_2__0_n_0 ));
  LUT3 #(
    .INIT(8'h89)) 
    \index[4]_i_1__0 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\index[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \index[4]_i_2__0 
       (.I0(index[0]),
        .I1(index[2]),
        .I2(index[3]),
        .I3(index[1]),
        .I4(index[4]),
        .I5(\index[4]_i_3__0_n_0 ),
        .O(\index[4]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \index[4]_i_3__0 
       (.I0(\index[3]_i_2__0_n_0 ),
        .I1(Q[2]),
        .O(\index[4]_i_3__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__0_n_0 ),
        .D(\index[0]_i_1__2_n_0 ),
        .Q(index[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__0_n_0 ),
        .D(\index[1]_i_1__2_n_0 ),
        .Q(index[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__0_n_0 ),
        .D(\index[2]_i_1__2_n_0 ),
        .Q(index[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__0_n_0 ),
        .D(\index[3]_i_1__0_n_0 ),
        .Q(index[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__0_n_0 ),
        .D(\index[4]_i_2__0_n_0 ),
        .Q(index[4]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \load_cnt[0]_i_1__1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(load_cnt[1]),
        .I3(Q[2]),
        .O(\load_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__1_n_0 ),
        .Q(load_cnt[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(load_cnt[1]),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h00AAA2AAAAAAAA00)) 
    mode_i_1__0
       (.I0(mode),
        .I1(mode_i_2__0_n_0),
        .I2(mode_i_3__2_n_0),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(mode_i_1__0_n_0));
  LUT4 #(
    .INIT(16'hCCB8)) 
    mode_i_2__0
       (.I0(mode),
        .I1(index[0]),
        .I2(x16x20_mode_reg2),
        .I3(index[2]),
        .O(mode_i_2__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    mode_i_3__2
       (.I0(index[2]),
        .I1(index[4]),
        .I2(index[1]),
        .I3(index[3]),
        .O(mode_i_3__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mode_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(mode_i_1__0_n_0),
        .Q(mode),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[0]),
        .Q(rate_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[1]),
        .Q(rate_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drprdy),
        .Q(rdy_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_START),
        .Q(start_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16),
        .Q(x16_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16_reg1),
        .Q(x16_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16X20_MODE),
        .Q(x16x20_mode_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16x20_mode_reg1),
        .Q(x16x20_mode_reg2),
        .R(RST_DCLK_RESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_drp" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_36
   (Q,
    DRPADDR,
    \cplllock_reg1_reg[2] ,
    \cplllock_reg1_reg[2]_0 ,
    gt_ch_drp_rdy,
    DRPDI,
    DRP_DONE,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi,
    RST_DCLK_RESET,
    DRP_X16X20_MODE,
    \resetovrd_disble.reset_reg[4] ,
    DRP_START,
    ext_ch_gt_drprdy,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    DRP_X16,
    ext_ch_gt_drpdo,
    rst_gtreset);
  output [2:0]Q;
  output [8:0]DRPADDR;
  output \cplllock_reg1_reg[2] ;
  output \cplllock_reg1_reg[2]_0 ;
  output [0:0]gt_ch_drp_rdy;
  output [15:0]DRPDI;
  output DRP_DONE;
  input [8:0]ext_ch_gt_drpaddr;
  input [0:0]ext_ch_gt_drpen;
  input [0:0]ext_ch_gt_drpwe;
  input [15:0]ext_ch_gt_drpdi;
  input RST_DCLK_RESET;
  input DRP_X16X20_MODE;
  input \resetovrd_disble.reset_reg[4] ;
  input DRP_START;
  input [0:0]ext_ch_gt_drprdy;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input DRP_X16;
  input [15:0]ext_ch_gt_drpdo;
  input rst_gtreset;

  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_DONE;
  wire DRP_START;
  wire DRP_X16;
  wire DRP_X16X20_MODE;
  wire [2:0]Q;
  wire RST_DCLK_RESET;
  wire \addr_reg[0]_i_1__1_n_0 ;
  wire \addr_reg[1]_i_1__1_n_0 ;
  wire \addr_reg[2]_i_1__1_n_0 ;
  wire \addr_reg[3]_i_1__1_n_0 ;
  wire \addr_reg[4]_i_1__1_n_0 ;
  wire \addr_reg[4]_i_2__1_n_0 ;
  wire \addr_reg[5]_i_1__1_n_0 ;
  wire \addr_reg[6]_i_1__1_n_0 ;
  wire \addr_reg[7]_i_1__1_n_0 ;
  wire \addr_reg[7]_i_2__1_n_0 ;
  wire \addr_reg_reg_n_0_[0] ;
  wire \addr_reg_reg_n_0_[1] ;
  wire \addr_reg_reg_n_0_[2] ;
  wire \addr_reg_reg_n_0_[3] ;
  wire \addr_reg_reg_n_0_[4] ;
  wire \addr_reg_reg_n_0_[5] ;
  wire \addr_reg_reg_n_0_[6] ;
  wire \addr_reg_reg_n_0_[7] ;
  wire \cplllock_reg1_reg[2] ;
  wire \cplllock_reg1_reg[2]_0 ;
  wire [7:7]data15;
  wire data4;
  wire [15:0]di_reg;
  wire \di_reg[0]_i_2__1_n_0 ;
  wire \di_reg[0]_i_3__1_n_0 ;
  wire \di_reg[0]_i_4__1_n_0 ;
  wire \di_reg[0]_i_5__1_n_0 ;
  wire \di_reg[0]_i_6__1_n_0 ;
  wire \di_reg[10]_i_2__1_n_0 ;
  wire \di_reg[11]_i_2__1_n_0 ;
  wire \di_reg[11]_i_3__1_n_0 ;
  wire \di_reg[11]_i_4__1_n_0 ;
  wire \di_reg[11]_i_5__1_n_0 ;
  wire \di_reg[12]_i_2__1_n_0 ;
  wire \di_reg[12]_i_3__1_n_0 ;
  wire \di_reg[12]_i_4__1_n_0 ;
  wire \di_reg[13]_i_2__1_n_0 ;
  wire \di_reg[13]_i_3__1_n_0 ;
  wire \di_reg[13]_i_4__1_n_0 ;
  wire \di_reg[14]_i_2__1_n_0 ;
  wire \di_reg[14]_i_3__1_n_0 ;
  wire \di_reg[14]_i_4__1_n_0 ;
  wire \di_reg[14]_i_6__1_n_0 ;
  wire \di_reg[14]_i_7__1_n_0 ;
  wire \di_reg[15]_i_2__1_n_0 ;
  wire \di_reg[1]_i_2__1_n_0 ;
  wire \di_reg[1]_i_3__1_n_0 ;
  wire \di_reg[1]_i_4__1_n_0 ;
  wire \di_reg[1]_i_5__1_n_0 ;
  wire \di_reg[1]_i_6__1_n_0 ;
  wire \di_reg[2]_i_2__1_n_0 ;
  wire \di_reg[2]_i_3__1_n_0 ;
  wire \di_reg[2]_i_4__1_n_0 ;
  wire \di_reg[2]_i_5__1_n_0 ;
  wire \di_reg[3]_i_2__1_n_0 ;
  wire \di_reg[3]_i_3__1_n_0 ;
  wire \di_reg[3]_i_4__1_n_0 ;
  wire \di_reg[4]_i_2__1_n_0 ;
  wire \di_reg[4]_i_3__1_n_0 ;
  wire \di_reg[4]_i_4__1_n_0 ;
  wire \di_reg[4]_i_5__1_n_0 ;
  wire \di_reg[4]_i_6__1_n_0 ;
  wire \di_reg[4]_i_7__1_n_0 ;
  wire \di_reg[4]_i_8__1_n_0 ;
  wire \di_reg[5]_i_2__1_n_0 ;
  wire \di_reg[5]_i_3__1_n_0 ;
  wire \di_reg[5]_i_4__1_n_0 ;
  wire \di_reg[6]_i_2__1_n_0 ;
  wire \di_reg[6]_i_3__1_n_0 ;
  wire \di_reg[7]_i_2__1_n_0 ;
  wire \di_reg[7]_i_3__1_n_0 ;
  wire \di_reg_reg_n_0_[0] ;
  wire \di_reg_reg_n_0_[10] ;
  wire \di_reg_reg_n_0_[11] ;
  wire \di_reg_reg_n_0_[12] ;
  wire \di_reg_reg_n_0_[13] ;
  wire \di_reg_reg_n_0_[14] ;
  wire \di_reg_reg_n_0_[15] ;
  wire \di_reg_reg_n_0_[1] ;
  wire \di_reg_reg_n_0_[2] ;
  wire \di_reg_reg_n_0_[3] ;
  wire \di_reg_reg_n_0_[4] ;
  wire \di_reg_reg_n_0_[5] ;
  wire \di_reg_reg_n_0_[6] ;
  wire \di_reg_reg_n_0_[7] ;
  wire \di_reg_reg_n_0_[8] ;
  wire \di_reg_reg_n_0_[9] ;
  wire [15:0]do_reg1;
  wire [15:0]do_reg2;
  wire done_i_1__1_n_0;
  wire [8:0]ext_ch_gt_drpaddr;
  wire [15:0]ext_ch_gt_drpdi;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drpen;
  wire [0:0]ext_ch_gt_drprdy;
  wire [0:0]ext_ch_gt_drpwe;
  wire [2:0]fsm;
  wire \fsm[0]_i_3__4_n_0 ;
  wire [0:0]gt_ch_drp_rdy;
  wire gtxreset_reg1;
  wire gtxreset_reg2;
  wire [4:0]index;
  wire \index[0]_i_1__3_n_0 ;
  wire \index[1]_i_1__3_n_0 ;
  wire \index[2]_i_1__3_n_0 ;
  wire \index[3]_i_1__1_n_0 ;
  wire \index[3]_i_2__1_n_0 ;
  wire \index[4]_i_1__1_n_0 ;
  wire \index[4]_i_2__1_n_0 ;
  wire \index[4]_i_3__1_n_0 ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1__2_n_0 ;
  wire mode;
  wire mode_i_1__1_n_0;
  wire mode_i_2__1_n_0;
  wire mode_i_3__3_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire [1:0]rate_reg1;
  wire [1:0]rate_reg2;
  wire rdy_reg1;
  wire rdy_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_gtreset;
  wire start_reg1;
  wire start_reg2;
  wire x16_reg1;
  wire x16_reg2;
  wire x16x20_mode_reg1;
  wire x16x20_mode_reg2;

  LUT6 #(
    .INIT(64'h1471357514713564)) 
    \addr_reg[0]_i_1__1 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__1_n_0 ),
        .O(\addr_reg[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h404050500F0F0500)) 
    \addr_reg[1]_i_1__1 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h051005105A055A00)) 
    \addr_reg[2]_i_1__1 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(index[2]),
        .I4(mode),
        .I5(index[1]),
        .O(\addr_reg[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h5767576753275326)) 
    \addr_reg[3]_i_1__1 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(\addr_reg[4]_i_2__1_n_0 ),
        .I5(index[0]),
        .O(\addr_reg[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FCCFFF01)) 
    \addr_reg[4]_i_1__1 
       (.I0(\addr_reg[4]_i_2__1_n_0 ),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[3]),
        .I5(index[4]),
        .O(\addr_reg[4]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \addr_reg[4]_i_2__1 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .O(\addr_reg[4]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h00001A1A0F0F0F0A)) 
    \addr_reg[5]_i_1__1 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[5]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000011545554)) 
    \addr_reg[6]_i_1__1 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(mode),
        .I3(index[3]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\addr_reg[6]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h5422262254222633)) 
    \addr_reg[7]_i_1__1 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__1_n_0 ),
        .O(\addr_reg[7]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hCE)) 
    \addr_reg[7]_i_2__1 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .I2(index[0]),
        .O(\addr_reg[7]_i_2__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[0]_i_1__1_n_0 ),
        .Q(\addr_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[1]_i_1__1_n_0 ),
        .Q(\addr_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[2]_i_1__1_n_0 ),
        .Q(\addr_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[3]_i_1__1_n_0 ),
        .Q(\addr_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[4]_i_1__1_n_0 ),
        .Q(\addr_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[5]_i_1__1_n_0 ),
        .Q(\addr_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[6]_i_1__1_n_0 ),
        .Q(\addr_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[7]_i_1__1_n_0 ),
        .Q(\addr_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'hB8B8B8BBB8B8B888)) 
    \di_reg[0]_i_2__1 
       (.I0(\di_reg[0]_i_4__1_n_0 ),
        .I1(index[3]),
        .I2(do_reg2[0]),
        .I3(\di_reg[0]_i_5__1_n_0 ),
        .I4(\di_reg[0]_i_6__1_n_0 ),
        .I5(\di_reg[4]_i_8__1_n_0 ),
        .O(\di_reg[0]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00003414)) 
    \di_reg[0]_i_3__1 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[0]),
        .I4(index[3]),
        .O(\di_reg[0]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hB0BFFFFFB0B00000)) 
    \di_reg[0]_i_4__1 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(do_reg2[0]),
        .O(\di_reg[0]_i_4__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \di_reg[0]_i_5__1 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .O(\di_reg[0]_i_5__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \di_reg[0]_i_6__1 
       (.I0(index[1]),
        .I1(mode),
        .I2(index[0]),
        .O(\di_reg[0]_i_6__1_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[10]_i_1__1 
       (.I0(index[4]),
        .I1(do_reg2[10]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[10]_i_2__1_n_0 ),
        .O(di_reg[10]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[10]_i_2__1 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[10]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[11]_i_1__1 
       (.I0(index[3]),
        .I1(\di_reg[11]_i_2__1_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[11]_i_3__1_n_0 ),
        .I4(\di_reg[11]_i_4__1_n_0 ),
        .I5(\di_reg[11]_i_5__1_n_0 ),
        .O(di_reg[11]));
  LUT6 #(
    .INIT(64'h0808080808380808)) 
    \di_reg[11]_i_2__1 
       (.I0(do_reg2[11]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[0]),
        .I4(rate_reg2[1]),
        .I5(index[0]),
        .O(\di_reg[11]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hCC0CCC0C0C0C880C)) 
    \di_reg[11]_i_3__1 
       (.I0(data15),
        .I1(index[3]),
        .I2(do_reg2[11]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[11]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAAAAAABAAABA)) 
    \di_reg[11]_i_4__1 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[11]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAA00AAAAAAA3)) 
    \di_reg[11]_i_5__1 
       (.I0(do_reg2[11]),
        .I1(x16_reg2),
        .I2(\addr_reg[4]_i_2__1_n_0 ),
        .I3(index[0]),
        .I4(index[1]),
        .I5(index[2]),
        .O(\di_reg[11]_i_5__1_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \di_reg[12]_i_1__1 
       (.I0(\di_reg[12]_i_2__1_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[12]_i_3__1_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[12]_i_4__1_n_0 ),
        .O(di_reg[12]));
  LUT5 #(
    .INIT(32'h00003202)) 
    \di_reg[12]_i_2__1 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[12]),
        .I4(index[3]),
        .O(\di_reg[12]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[12]_i_3__1 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[12]),
        .O(\di_reg[12]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAA8AAABAAABA)) 
    \di_reg[12]_i_4__1 
       (.I0(do_reg2[12]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[12]_i_4__1_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \di_reg[13]_i_1__1 
       (.I0(\di_reg[13]_i_2__1_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[13]_i_3__1_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[13]_i_4__1_n_0 ),
        .O(di_reg[13]));
  LUT6 #(
    .INIT(64'h0808080838380838)) 
    \di_reg[13]_i_2__1 
       (.I0(do_reg2[13]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[13]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[13]_i_3__1 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[13]),
        .O(\di_reg[13]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hAA8AAA8AAABAAA8A)) 
    \di_reg[13]_i_4__1 
       (.I0(do_reg2[13]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[1]),
        .I5(rate_reg2[0]),
        .O(\di_reg[13]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'h080008FF08000800)) 
    \di_reg[14]_i_1__1 
       (.I0(do_reg2[14]),
        .I1(\di_reg[14]_i_2__1_n_0 ),
        .I2(index[3]),
        .I3(index[4]),
        .I4(\di_reg[14]_i_3__1_n_0 ),
        .I5(\di_reg[14]_i_4__1_n_0 ),
        .O(di_reg[14]));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_2__1 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[14]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h0033303310130033)) 
    \di_reg[14]_i_3__1 
       (.I0(data15),
        .I1(index[3]),
        .I2(index[2]),
        .I3(do_reg2[14]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[14]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000DF10)) 
    \di_reg[14]_i_4__1 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(do_reg2[14]),
        .I4(index[2]),
        .I5(\di_reg[14]_i_6__1_n_0 ),
        .O(\di_reg[14]_i_4__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_5__1 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .O(data15));
  LUT6 #(
    .INIT(64'hBBBB3BBBBBBB3FBB)) 
    \di_reg[14]_i_6__1 
       (.I0(\di_reg[14]_i_7__1_n_0 ),
        .I1(index[3]),
        .I2(index[0]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(\di_reg[5]_i_4__1_n_0 ),
        .O(\di_reg[14]_i_6__1_n_0 ));
  LUT4 #(
    .INIT(16'h4440)) 
    \di_reg[14]_i_7__1 
       (.I0(index[1]),
        .I1(index[2]),
        .I2(do_reg2[14]),
        .I3(index[0]),
        .O(\di_reg[14]_i_7__1_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[15]_i_1__1 
       (.I0(index[4]),
        .I1(do_reg2[15]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[15]_i_2__1_n_0 ),
        .O(di_reg[15]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[15]_i_2__1 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[15]_i_2__1_n_0 ));
  LUT4 #(
    .INIT(16'hABAA)) 
    \di_reg[1]_i_1__1 
       (.I0(\di_reg[1]_i_2__1_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[1]_i_3__1_n_0 ),
        .I3(\di_reg[1]_i_4__1_n_0 ),
        .O(di_reg[1]));
  LUT6 #(
    .INIT(64'h0000000034140000)) 
    \di_reg[1]_i_2__1 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[1]),
        .I4(index[4]),
        .I5(index[3]),
        .O(\di_reg[1]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FB330000)) 
    \di_reg[1]_i_3__1 
       (.I0(index[2]),
        .I1(do_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[3]),
        .I5(\di_reg[1]_i_5__1_n_0 ),
        .O(\di_reg[1]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFCCC5555)) 
    \di_reg[1]_i_4__1 
       (.I0(\di_reg[1]_i_6__1_n_0 ),
        .I1(do_reg2[1]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\di_reg[1]_i_4__1_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \di_reg[1]_i_5__1 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .I3(index[1]),
        .O(\di_reg[1]_i_5__1_n_0 ));
  LUT6 #(
    .INIT(64'h002F0F20F02FFF2F)) 
    \di_reg[1]_i_6__1 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(mode),
        .I5(do_reg2[1]),
        .O(\di_reg[1]_i_6__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[2]_i_1__1 
       (.I0(\di_reg[2]_i_2__1_n_0 ),
        .I1(\di_reg[2]_i_3__1_n_0 ),
        .O(di_reg[2]));
  LUT6 #(
    .INIT(64'h00400500FFFFFFFF)) 
    \di_reg[2]_i_2__1 
       (.I0(index[3]),
        .I1(do_reg2[2]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\di_reg[2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF470047)) 
    \di_reg[2]_i_3__1 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(\di_reg[2]_i_4__1_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[2]_i_5__1_n_0 ),
        .I5(index[4]),
        .O(\di_reg[2]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hF4F40404F00FF000)) 
    \di_reg[2]_i_4__1 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(mode),
        .I4(do_reg2[2]),
        .I5(index[1]),
        .O(\di_reg[2]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'hF5D535D5F5D5F5D5)) 
    \di_reg[2]_i_5__1 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[2]_i_5__1_n_0 ));
  LUT6 #(
    .INIT(64'hBAAA1000AAFF0000)) 
    \di_reg[3]_i_2__1 
       (.I0(\di_reg[3]_i_4__1_n_0 ),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(do_reg2[3]),
        .I5(index[0]),
        .O(\di_reg[3]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000033E200)) 
    \di_reg[3]_i_3__1 
       (.I0(data15),
        .I1(index[0]),
        .I2(do_reg2[3]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\di_reg[3]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[3]_i_4__1 
       (.I0(index[3]),
        .I1(index[1]),
        .O(\di_reg[3]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[4]_i_1__1 
       (.I0(index[3]),
        .I1(\di_reg[4]_i_2__1_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[4]_i_3__1_n_0 ),
        .I4(\di_reg[4]_i_4__1_n_0 ),
        .I5(\di_reg[4]_i_5__1_n_0 ),
        .O(di_reg[4]));
  LUT6 #(
    .INIT(64'h08080B0830303030)) 
    \di_reg[4]_i_2__1 
       (.I0(do_reg2[4]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[4]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DFFFFFFF)) 
    \di_reg[4]_i_3__1 
       (.I0(index[0]),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\di_reg[4]_i_6__1_n_0 ),
        .O(\di_reg[4]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FFFFE00000000)) 
    \di_reg[4]_i_4__1 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(do_reg2[4]),
        .O(\di_reg[4]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010C00)) 
    \di_reg[4]_i_5__1 
       (.I0(\di_reg[4]_i_7__1_n_0 ),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(\di_reg[4]_i_8__1_n_0 ),
        .I5(index[3]),
        .O(\di_reg[4]_i_5__1_n_0 ));
  LUT5 #(
    .INIT(32'h1F0FFF0F)) 
    \di_reg[4]_i_6__1 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(do_reg2[4]),
        .I4(index[1]),
        .O(\di_reg[4]_i_6__1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \di_reg[4]_i_7__1 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .O(\di_reg[4]_i_7__1_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \di_reg[4]_i_8__1 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .O(\di_reg[4]_i_8__1_n_0 ));
  LUT6 #(
    .INIT(64'h33000000B888B888)) 
    \di_reg[5]_i_1__1 
       (.I0(\di_reg[5]_i_2__1_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[5]_i_3__1_n_0 ),
        .I3(do_reg2[5]),
        .I4(\di_reg[5]_i_4__1_n_0 ),
        .I5(index[3]),
        .O(di_reg[5]));
  LUT6 #(
    .INIT(64'h0B0B080B33333033)) 
    \di_reg[5]_i_2__1 
       (.I0(do_reg2[5]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[5]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \di_reg[5]_i_3__1 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(x16x20_mode_reg2),
        .I4(mode),
        .O(\di_reg[5]_i_3__1_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[5]_i_4__1 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[5]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'h67FF000067000000)) 
    \di_reg[6]_i_2__1 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[6]),
        .I5(\di_reg[5]_i_3__1_n_0 ),
        .O(\di_reg[6]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00002404)) 
    \di_reg[6]_i_3__1 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[6]),
        .I4(index[3]),
        .O(\di_reg[6]_i_3__1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF0900)) 
    \di_reg[7]_i_2__1 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[7]),
        .O(\di_reg[7]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000C320032)) 
    \di_reg[7]_i_3__1 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(do_reg2[7]),
        .I5(index[3]),
        .O(\di_reg[7]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[8]_i_1__1 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[8]),
        .O(di_reg[8]));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[9]_i_1__1 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[9]),
        .O(di_reg[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[0]),
        .Q(\di_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[0]_i_1__1 
       (.I0(\di_reg[0]_i_2__1_n_0 ),
        .I1(\di_reg[0]_i_3__1_n_0 ),
        .O(di_reg[0]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[10]),
        .Q(\di_reg_reg_n_0_[10] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[11]),
        .Q(\di_reg_reg_n_0_[11] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[12]),
        .Q(\di_reg_reg_n_0_[12] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[13]),
        .Q(\di_reg_reg_n_0_[13] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[14]),
        .Q(\di_reg_reg_n_0_[14] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[15]),
        .Q(\di_reg_reg_n_0_[15] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[1]),
        .Q(\di_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[2]),
        .Q(\di_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[3]),
        .Q(\di_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[3]_i_1__1 
       (.I0(\di_reg[3]_i_2__1_n_0 ),
        .I1(\di_reg[3]_i_3__1_n_0 ),
        .O(di_reg[3]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[4]),
        .Q(\di_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[5]),
        .Q(\di_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[6]),
        .Q(\di_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[6]_i_1__1 
       (.I0(\di_reg[6]_i_2__1_n_0 ),
        .I1(\di_reg[6]_i_3__1_n_0 ),
        .O(di_reg[6]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[7]),
        .Q(\di_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[7]_i_1__1 
       (.I0(\di_reg[7]_i_2__1_n_0 ),
        .I1(\di_reg[7]_i_3__1_n_0 ),
        .O(di_reg[7]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[8]),
        .Q(\di_reg_reg_n_0_[8] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[9]),
        .Q(\di_reg_reg_n_0_[9] ),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[0]),
        .Q(do_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[10]),
        .Q(do_reg1[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[11]),
        .Q(do_reg1[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[12]),
        .Q(do_reg1[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[13]),
        .Q(do_reg1[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[14]),
        .Q(do_reg1[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[15]),
        .Q(do_reg1[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[1]),
        .Q(do_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[2]),
        .Q(do_reg1[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[3]),
        .Q(do_reg1[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[4]),
        .Q(do_reg1[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[5]),
        .Q(do_reg1[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[6]),
        .Q(do_reg1[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[7]),
        .Q(do_reg1[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[8]),
        .Q(do_reg1[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[9]),
        .Q(do_reg1[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(RST_DCLK_RESET));
  LUT4 #(
    .INIT(16'h0001)) 
    done_i_1__1
       (.I0(start_reg2),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(done_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(done_i_1__1_n_0),
        .Q(DRP_DONE),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0B3BFFFF0B3B0000)) 
    \fsm[0]_i_1__4 
       (.I0(data4),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(rdy_reg2),
        .I4(Q[2]),
        .I5(\fsm[0]_i_3__4_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT5 #(
    .INIT(32'hEFFEFFFF)) 
    \fsm[0]_i_2__1 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[4]),
        .I3(index[2]),
        .I4(mode_i_2__1_n_0),
        .O(data4));
  LUT6 #(
    .INIT(64'h7477FFFF7477CCCC)) 
    \fsm[0]_i_3__4 
       (.I0(rdy_reg2),
        .I1(Q[1]),
        .I2(load_cnt[1]),
        .I3(load_cnt[0]),
        .I4(Q[0]),
        .I5(start_reg2),
        .O(\fsm[0]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'h185018501D501850)) 
    \fsm[1]_i_1__1 
       (.I0(Q[2]),
        .I1(rdy_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(load_cnt[0]),
        .I5(load_cnt[1]),
        .O(fsm[1]));
  LUT4 #(
    .INIT(16'h6222)) 
    \fsm[2]_i_1__4 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(rdy_reg2),
        .I3(Q[0]),
        .O(fsm[2]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \gt_ch_drp_rdy[2]_INST_0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(gt_ch_drp_rdy));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_15__1 
       (.I0(ext_ch_gt_drpdi[15]),
        .I1(\di_reg_reg_n_0_[15] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[15]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_16__1 
       (.I0(ext_ch_gt_drpdi[14]),
        .I1(\di_reg_reg_n_0_[14] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[14]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_17__1 
       (.I0(ext_ch_gt_drpdi[13]),
        .I1(\di_reg_reg_n_0_[13] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[13]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_18__1 
       (.I0(ext_ch_gt_drpdi[12]),
        .I1(\di_reg_reg_n_0_[12] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[12]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_19__1 
       (.I0(ext_ch_gt_drpdi[11]),
        .I1(\di_reg_reg_n_0_[11] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[11]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_20__1 
       (.I0(ext_ch_gt_drpdi[10]),
        .I1(\di_reg_reg_n_0_[10] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[10]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_21__1 
       (.I0(ext_ch_gt_drpdi[9]),
        .I1(\di_reg_reg_n_0_[9] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[9]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_22__1 
       (.I0(ext_ch_gt_drpdi[8]),
        .I1(\di_reg_reg_n_0_[8] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_23__1 
       (.I0(ext_ch_gt_drpdi[7]),
        .I1(\di_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_24__1 
       (.I0(ext_ch_gt_drpdi[6]),
        .I1(\di_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[6]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_25__1 
       (.I0(ext_ch_gt_drpdi[5]),
        .I1(\di_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_26__1 
       (.I0(ext_ch_gt_drpdi[4]),
        .I1(\di_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_27__1 
       (.I0(ext_ch_gt_drpdi[3]),
        .I1(\di_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_28__1 
       (.I0(ext_ch_gt_drpdi[2]),
        .I1(\di_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_29__1 
       (.I0(ext_ch_gt_drpdi[1]),
        .I1(\di_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_30__3 
       (.I0(ext_ch_gt_drpdi[0]),
        .I1(\di_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[0]));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT4 #(
    .INIT(16'h003E)) 
    \gtx_channel.gtxe2_channel_i_i_3__1 
       (.I0(ext_ch_gt_drpen),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\cplllock_reg1_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_48__3 
       (.I0(ext_ch_gt_drpaddr[8]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(DRPADDR[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_49__1 
       (.I0(ext_ch_gt_drpaddr[7]),
        .I1(\addr_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[7]));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT4 #(
    .INIT(16'h0032)) 
    \gtx_channel.gtxe2_channel_i_i_4__1 
       (.I0(ext_ch_gt_drpwe),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(\cplllock_reg1_reg[2]_0 ));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_50__1 
       (.I0(ext_ch_gt_drpaddr[6]),
        .I1(\addr_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[6]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_51__1 
       (.I0(ext_ch_gt_drpaddr[5]),
        .I1(\addr_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_52__1 
       (.I0(ext_ch_gt_drpaddr[4]),
        .I1(\addr_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_53__1 
       (.I0(ext_ch_gt_drpaddr[3]),
        .I1(\addr_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_54__1 
       (.I0(ext_ch_gt_drpaddr[2]),
        .I1(\addr_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_55__1 
       (.I0(ext_ch_gt_drpaddr[1]),
        .I1(\addr_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_56__3 
       (.I0(ext_ch_gt_drpaddr[0]),
        .I1(\addr_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[0]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rst_gtreset),
        .Q(gtxreset_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(gtxreset_reg1),
        .Q(gtxreset_reg2),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \index[0]_i_1__3 
       (.I0(index[0]),
        .I1(Q[2]),
        .I2(\index[3]_i_2__1_n_0 ),
        .O(\index[0]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT4 #(
    .INIT(16'h0220)) 
    \index[1]_i_1__3 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__1_n_0 ),
        .I2(index[1]),
        .I3(index[0]),
        .O(\index[1]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT5 #(
    .INIT(32'h02222000)) 
    \index[2]_i_1__3 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__1_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .O(\index[2]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h0222222220000000)) 
    \index[3]_i_1__1 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__1_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\index[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAE)) 
    \index[3]_i_2__1 
       (.I0(Q[0]),
        .I1(mode_i_2__1_n_0),
        .I2(index[2]),
        .I3(index[4]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\index[3]_i_2__1_n_0 ));
  LUT3 #(
    .INIT(8'h89)) 
    \index[4]_i_1__1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\index[4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \index[4]_i_2__1 
       (.I0(index[0]),
        .I1(index[2]),
        .I2(index[3]),
        .I3(index[1]),
        .I4(index[4]),
        .I5(\index[4]_i_3__1_n_0 ),
        .O(\index[4]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \index[4]_i_3__1 
       (.I0(\index[3]_i_2__1_n_0 ),
        .I1(Q[2]),
        .O(\index[4]_i_3__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__1_n_0 ),
        .D(\index[0]_i_1__3_n_0 ),
        .Q(index[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__1_n_0 ),
        .D(\index[1]_i_1__3_n_0 ),
        .Q(index[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__1_n_0 ),
        .D(\index[2]_i_1__3_n_0 ),
        .Q(index[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__1_n_0 ),
        .D(\index[3]_i_1__1_n_0 ),
        .Q(index[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__1_n_0 ),
        .D(\index[4]_i_2__1_n_0 ),
        .Q(index[4]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \load_cnt[0]_i_1__2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(load_cnt[1]),
        .I3(Q[2]),
        .O(\load_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__2_n_0 ),
        .Q(load_cnt[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(load_cnt[1]),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h00AAA2AAAAAAAA00)) 
    mode_i_1__1
       (.I0(mode),
        .I1(mode_i_2__1_n_0),
        .I2(mode_i_3__3_n_0),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(mode_i_1__1_n_0));
  LUT4 #(
    .INIT(16'hCCB8)) 
    mode_i_2__1
       (.I0(mode),
        .I1(index[0]),
        .I2(x16x20_mode_reg2),
        .I3(index[2]),
        .O(mode_i_2__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    mode_i_3__3
       (.I0(index[2]),
        .I1(index[4]),
        .I2(index[1]),
        .I3(index[3]),
        .O(mode_i_3__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mode_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(mode_i_1__1_n_0),
        .Q(mode),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[0]),
        .Q(rate_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[1]),
        .Q(rate_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drprdy),
        .Q(rdy_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_START),
        .Q(start_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16),
        .Q(x16_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16_reg1),
        .Q(x16_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16X20_MODE),
        .Q(x16x20_mode_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16x20_mode_reg1),
        .Q(x16x20_mode_reg2),
        .R(RST_DCLK_RESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_drp" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_42
   (Q,
    DRPADDR,
    \cplllock_reg1_reg[3] ,
    \cplllock_reg1_reg[3]_0 ,
    gt_ch_drp_rdy,
    DRPDI,
    DRP_DONE,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi,
    RST_DCLK_RESET,
    DRP_X16X20_MODE,
    \resetovrd_disble.reset_reg[4] ,
    DRP_START,
    ext_ch_gt_drprdy,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    DRP_X16,
    ext_ch_gt_drpdo,
    rst_gtreset);
  output [2:0]Q;
  output [8:0]DRPADDR;
  output \cplllock_reg1_reg[3] ;
  output \cplllock_reg1_reg[3]_0 ;
  output [0:0]gt_ch_drp_rdy;
  output [15:0]DRPDI;
  output DRP_DONE;
  input [8:0]ext_ch_gt_drpaddr;
  input [0:0]ext_ch_gt_drpen;
  input [0:0]ext_ch_gt_drpwe;
  input [15:0]ext_ch_gt_drpdi;
  input RST_DCLK_RESET;
  input DRP_X16X20_MODE;
  input \resetovrd_disble.reset_reg[4] ;
  input DRP_START;
  input [0:0]ext_ch_gt_drprdy;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input DRP_X16;
  input [15:0]ext_ch_gt_drpdo;
  input rst_gtreset;

  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_DONE;
  wire DRP_START;
  wire DRP_X16;
  wire DRP_X16X20_MODE;
  wire [2:0]Q;
  wire RST_DCLK_RESET;
  wire \addr_reg[0]_i_1__2_n_0 ;
  wire \addr_reg[1]_i_1__2_n_0 ;
  wire \addr_reg[2]_i_1__2_n_0 ;
  wire \addr_reg[3]_i_1__2_n_0 ;
  wire \addr_reg[4]_i_1__2_n_0 ;
  wire \addr_reg[4]_i_2__2_n_0 ;
  wire \addr_reg[5]_i_1__2_n_0 ;
  wire \addr_reg[6]_i_1__2_n_0 ;
  wire \addr_reg[7]_i_1__2_n_0 ;
  wire \addr_reg[7]_i_2__2_n_0 ;
  wire \addr_reg_reg_n_0_[0] ;
  wire \addr_reg_reg_n_0_[1] ;
  wire \addr_reg_reg_n_0_[2] ;
  wire \addr_reg_reg_n_0_[3] ;
  wire \addr_reg_reg_n_0_[4] ;
  wire \addr_reg_reg_n_0_[5] ;
  wire \addr_reg_reg_n_0_[6] ;
  wire \addr_reg_reg_n_0_[7] ;
  wire \cplllock_reg1_reg[3] ;
  wire \cplllock_reg1_reg[3]_0 ;
  wire [7:7]data15;
  wire data4;
  wire [15:0]di_reg;
  wire \di_reg[0]_i_2__2_n_0 ;
  wire \di_reg[0]_i_3__2_n_0 ;
  wire \di_reg[0]_i_4__2_n_0 ;
  wire \di_reg[0]_i_5__2_n_0 ;
  wire \di_reg[0]_i_6__2_n_0 ;
  wire \di_reg[10]_i_2__2_n_0 ;
  wire \di_reg[11]_i_2__2_n_0 ;
  wire \di_reg[11]_i_3__2_n_0 ;
  wire \di_reg[11]_i_4__2_n_0 ;
  wire \di_reg[11]_i_5__2_n_0 ;
  wire \di_reg[12]_i_2__2_n_0 ;
  wire \di_reg[12]_i_3__2_n_0 ;
  wire \di_reg[12]_i_4__2_n_0 ;
  wire \di_reg[13]_i_2__2_n_0 ;
  wire \di_reg[13]_i_3__2_n_0 ;
  wire \di_reg[13]_i_4__2_n_0 ;
  wire \di_reg[14]_i_2__2_n_0 ;
  wire \di_reg[14]_i_3__2_n_0 ;
  wire \di_reg[14]_i_4__2_n_0 ;
  wire \di_reg[14]_i_6__2_n_0 ;
  wire \di_reg[14]_i_7__2_n_0 ;
  wire \di_reg[15]_i_2__2_n_0 ;
  wire \di_reg[1]_i_2__2_n_0 ;
  wire \di_reg[1]_i_3__2_n_0 ;
  wire \di_reg[1]_i_4__2_n_0 ;
  wire \di_reg[1]_i_5__2_n_0 ;
  wire \di_reg[1]_i_6__2_n_0 ;
  wire \di_reg[2]_i_2__2_n_0 ;
  wire \di_reg[2]_i_3__2_n_0 ;
  wire \di_reg[2]_i_4__2_n_0 ;
  wire \di_reg[2]_i_5__2_n_0 ;
  wire \di_reg[3]_i_2__2_n_0 ;
  wire \di_reg[3]_i_3__2_n_0 ;
  wire \di_reg[3]_i_4__2_n_0 ;
  wire \di_reg[4]_i_2__2_n_0 ;
  wire \di_reg[4]_i_3__2_n_0 ;
  wire \di_reg[4]_i_4__2_n_0 ;
  wire \di_reg[4]_i_5__2_n_0 ;
  wire \di_reg[4]_i_6__2_n_0 ;
  wire \di_reg[4]_i_7__2_n_0 ;
  wire \di_reg[4]_i_8__2_n_0 ;
  wire \di_reg[5]_i_2__2_n_0 ;
  wire \di_reg[5]_i_3__2_n_0 ;
  wire \di_reg[5]_i_4__2_n_0 ;
  wire \di_reg[6]_i_2__2_n_0 ;
  wire \di_reg[6]_i_3__2_n_0 ;
  wire \di_reg[7]_i_2__2_n_0 ;
  wire \di_reg[7]_i_3__2_n_0 ;
  wire \di_reg_reg_n_0_[0] ;
  wire \di_reg_reg_n_0_[10] ;
  wire \di_reg_reg_n_0_[11] ;
  wire \di_reg_reg_n_0_[12] ;
  wire \di_reg_reg_n_0_[13] ;
  wire \di_reg_reg_n_0_[14] ;
  wire \di_reg_reg_n_0_[15] ;
  wire \di_reg_reg_n_0_[1] ;
  wire \di_reg_reg_n_0_[2] ;
  wire \di_reg_reg_n_0_[3] ;
  wire \di_reg_reg_n_0_[4] ;
  wire \di_reg_reg_n_0_[5] ;
  wire \di_reg_reg_n_0_[6] ;
  wire \di_reg_reg_n_0_[7] ;
  wire \di_reg_reg_n_0_[8] ;
  wire \di_reg_reg_n_0_[9] ;
  wire [15:0]do_reg1;
  wire [15:0]do_reg2;
  wire done_i_1__2_n_0;
  wire [8:0]ext_ch_gt_drpaddr;
  wire [15:0]ext_ch_gt_drpdi;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drpen;
  wire [0:0]ext_ch_gt_drprdy;
  wire [0:0]ext_ch_gt_drpwe;
  wire [2:0]fsm;
  wire \fsm[0]_i_3__6_n_0 ;
  wire [0:0]gt_ch_drp_rdy;
  wire gtxreset_reg1;
  wire gtxreset_reg2;
  wire [4:0]index;
  wire \index[0]_i_1__4_n_0 ;
  wire \index[1]_i_1__4_n_0 ;
  wire \index[2]_i_1__4_n_0 ;
  wire \index[3]_i_1__2_n_0 ;
  wire \index[3]_i_2__2_n_0 ;
  wire \index[4]_i_1__2_n_0 ;
  wire \index[4]_i_2__2_n_0 ;
  wire \index[4]_i_3__2_n_0 ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1__3_n_0 ;
  wire mode;
  wire mode_i_1__2_n_0;
  wire mode_i_2__2_n_0;
  wire mode_i_3__4_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire [1:0]rate_reg1;
  wire [1:0]rate_reg2;
  wire rdy_reg1;
  wire rdy_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_gtreset;
  wire start_reg1;
  wire start_reg2;
  wire x16_reg1;
  wire x16_reg2;
  wire x16x20_mode_reg1;
  wire x16x20_mode_reg2;

  LUT6 #(
    .INIT(64'h1471357514713564)) 
    \addr_reg[0]_i_1__2 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__2_n_0 ),
        .O(\addr_reg[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h404050500F0F0500)) 
    \addr_reg[1]_i_1__2 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h051005105A055A00)) 
    \addr_reg[2]_i_1__2 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(index[2]),
        .I4(mode),
        .I5(index[1]),
        .O(\addr_reg[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h5767576753275326)) 
    \addr_reg[3]_i_1__2 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(\addr_reg[4]_i_2__2_n_0 ),
        .I5(index[0]),
        .O(\addr_reg[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FCCFFF01)) 
    \addr_reg[4]_i_1__2 
       (.I0(\addr_reg[4]_i_2__2_n_0 ),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[3]),
        .I5(index[4]),
        .O(\addr_reg[4]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \addr_reg[4]_i_2__2 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .O(\addr_reg[4]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h00001A1A0F0F0F0A)) 
    \addr_reg[5]_i_1__2 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[5]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000011545554)) 
    \addr_reg[6]_i_1__2 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(mode),
        .I3(index[3]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\addr_reg[6]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h5422262254222633)) 
    \addr_reg[7]_i_1__2 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__2_n_0 ),
        .O(\addr_reg[7]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hCE)) 
    \addr_reg[7]_i_2__2 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .I2(index[0]),
        .O(\addr_reg[7]_i_2__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[0]_i_1__2_n_0 ),
        .Q(\addr_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[1]_i_1__2_n_0 ),
        .Q(\addr_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[2]_i_1__2_n_0 ),
        .Q(\addr_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[3]_i_1__2_n_0 ),
        .Q(\addr_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[4]_i_1__2_n_0 ),
        .Q(\addr_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[5]_i_1__2_n_0 ),
        .Q(\addr_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[6]_i_1__2_n_0 ),
        .Q(\addr_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[7]_i_1__2_n_0 ),
        .Q(\addr_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'hB8B8B8BBB8B8B888)) 
    \di_reg[0]_i_2__2 
       (.I0(\di_reg[0]_i_4__2_n_0 ),
        .I1(index[3]),
        .I2(do_reg2[0]),
        .I3(\di_reg[0]_i_5__2_n_0 ),
        .I4(\di_reg[0]_i_6__2_n_0 ),
        .I5(\di_reg[4]_i_8__2_n_0 ),
        .O(\di_reg[0]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'h00003414)) 
    \di_reg[0]_i_3__2 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[0]),
        .I4(index[3]),
        .O(\di_reg[0]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hB0BFFFFFB0B00000)) 
    \di_reg[0]_i_4__2 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(do_reg2[0]),
        .O(\di_reg[0]_i_4__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \di_reg[0]_i_5__2 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .O(\di_reg[0]_i_5__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \di_reg[0]_i_6__2 
       (.I0(index[1]),
        .I1(mode),
        .I2(index[0]),
        .O(\di_reg[0]_i_6__2_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[10]_i_1__2 
       (.I0(index[4]),
        .I1(do_reg2[10]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[10]_i_2__2_n_0 ),
        .O(di_reg[10]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[10]_i_2__2 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[10]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[11]_i_1__2 
       (.I0(index[3]),
        .I1(\di_reg[11]_i_2__2_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[11]_i_3__2_n_0 ),
        .I4(\di_reg[11]_i_4__2_n_0 ),
        .I5(\di_reg[11]_i_5__2_n_0 ),
        .O(di_reg[11]));
  LUT6 #(
    .INIT(64'h0808080808380808)) 
    \di_reg[11]_i_2__2 
       (.I0(do_reg2[11]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[0]),
        .I4(rate_reg2[1]),
        .I5(index[0]),
        .O(\di_reg[11]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hCC0CCC0C0C0C880C)) 
    \di_reg[11]_i_3__2 
       (.I0(data15),
        .I1(index[3]),
        .I2(do_reg2[11]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[11]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAAAAAABAAABA)) 
    \di_reg[11]_i_4__2 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[11]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAA00AAAAAAA3)) 
    \di_reg[11]_i_5__2 
       (.I0(do_reg2[11]),
        .I1(x16_reg2),
        .I2(\addr_reg[4]_i_2__2_n_0 ),
        .I3(index[0]),
        .I4(index[1]),
        .I5(index[2]),
        .O(\di_reg[11]_i_5__2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \di_reg[12]_i_1__2 
       (.I0(\di_reg[12]_i_2__2_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[12]_i_3__2_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[12]_i_4__2_n_0 ),
        .O(di_reg[12]));
  LUT5 #(
    .INIT(32'h00003202)) 
    \di_reg[12]_i_2__2 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[12]),
        .I4(index[3]),
        .O(\di_reg[12]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[12]_i_3__2 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[12]),
        .O(\di_reg[12]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAA8AAABAAABA)) 
    \di_reg[12]_i_4__2 
       (.I0(do_reg2[12]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[12]_i_4__2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \di_reg[13]_i_1__2 
       (.I0(\di_reg[13]_i_2__2_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[13]_i_3__2_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[13]_i_4__2_n_0 ),
        .O(di_reg[13]));
  LUT6 #(
    .INIT(64'h0808080838380838)) 
    \di_reg[13]_i_2__2 
       (.I0(do_reg2[13]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[13]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[13]_i_3__2 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[13]),
        .O(\di_reg[13]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hAA8AAA8AAABAAA8A)) 
    \di_reg[13]_i_4__2 
       (.I0(do_reg2[13]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[1]),
        .I5(rate_reg2[0]),
        .O(\di_reg[13]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'h080008FF08000800)) 
    \di_reg[14]_i_1__2 
       (.I0(do_reg2[14]),
        .I1(\di_reg[14]_i_2__2_n_0 ),
        .I2(index[3]),
        .I3(index[4]),
        .I4(\di_reg[14]_i_3__2_n_0 ),
        .I5(\di_reg[14]_i_4__2_n_0 ),
        .O(di_reg[14]));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_2__2 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[14]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h0033303310130033)) 
    \di_reg[14]_i_3__2 
       (.I0(data15),
        .I1(index[3]),
        .I2(index[2]),
        .I3(do_reg2[14]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[14]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000DF10)) 
    \di_reg[14]_i_4__2 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(do_reg2[14]),
        .I4(index[2]),
        .I5(\di_reg[14]_i_6__2_n_0 ),
        .O(\di_reg[14]_i_4__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_5__2 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .O(data15));
  LUT6 #(
    .INIT(64'hBBBB3BBBBBBB3FBB)) 
    \di_reg[14]_i_6__2 
       (.I0(\di_reg[14]_i_7__2_n_0 ),
        .I1(index[3]),
        .I2(index[0]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(\di_reg[5]_i_4__2_n_0 ),
        .O(\di_reg[14]_i_6__2_n_0 ));
  LUT4 #(
    .INIT(16'h4440)) 
    \di_reg[14]_i_7__2 
       (.I0(index[1]),
        .I1(index[2]),
        .I2(do_reg2[14]),
        .I3(index[0]),
        .O(\di_reg[14]_i_7__2_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[15]_i_1__2 
       (.I0(index[4]),
        .I1(do_reg2[15]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[15]_i_2__2_n_0 ),
        .O(di_reg[15]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[15]_i_2__2 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[15]_i_2__2_n_0 ));
  LUT4 #(
    .INIT(16'hABAA)) 
    \di_reg[1]_i_1__2 
       (.I0(\di_reg[1]_i_2__2_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[1]_i_3__2_n_0 ),
        .I3(\di_reg[1]_i_4__2_n_0 ),
        .O(di_reg[1]));
  LUT6 #(
    .INIT(64'h0000000034140000)) 
    \di_reg[1]_i_2__2 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[1]),
        .I4(index[4]),
        .I5(index[3]),
        .O(\di_reg[1]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FB330000)) 
    \di_reg[1]_i_3__2 
       (.I0(index[2]),
        .I1(do_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[3]),
        .I5(\di_reg[1]_i_5__2_n_0 ),
        .O(\di_reg[1]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFCCC5555)) 
    \di_reg[1]_i_4__2 
       (.I0(\di_reg[1]_i_6__2_n_0 ),
        .I1(do_reg2[1]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\di_reg[1]_i_4__2_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \di_reg[1]_i_5__2 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .I3(index[1]),
        .O(\di_reg[1]_i_5__2_n_0 ));
  LUT6 #(
    .INIT(64'h002F0F20F02FFF2F)) 
    \di_reg[1]_i_6__2 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(mode),
        .I5(do_reg2[1]),
        .O(\di_reg[1]_i_6__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[2]_i_1__2 
       (.I0(\di_reg[2]_i_2__2_n_0 ),
        .I1(\di_reg[2]_i_3__2_n_0 ),
        .O(di_reg[2]));
  LUT6 #(
    .INIT(64'h00400500FFFFFFFF)) 
    \di_reg[2]_i_2__2 
       (.I0(index[3]),
        .I1(do_reg2[2]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\di_reg[2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF470047)) 
    \di_reg[2]_i_3__2 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(\di_reg[2]_i_4__2_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[2]_i_5__2_n_0 ),
        .I5(index[4]),
        .O(\di_reg[2]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hF4F40404F00FF000)) 
    \di_reg[2]_i_4__2 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(mode),
        .I4(do_reg2[2]),
        .I5(index[1]),
        .O(\di_reg[2]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'hF5D535D5F5D5F5D5)) 
    \di_reg[2]_i_5__2 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[2]_i_5__2_n_0 ));
  LUT6 #(
    .INIT(64'hBAAA1000AAFF0000)) 
    \di_reg[3]_i_2__2 
       (.I0(\di_reg[3]_i_4__2_n_0 ),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(do_reg2[3]),
        .I5(index[0]),
        .O(\di_reg[3]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000033E200)) 
    \di_reg[3]_i_3__2 
       (.I0(data15),
        .I1(index[0]),
        .I2(do_reg2[3]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\di_reg[3]_i_3__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[3]_i_4__2 
       (.I0(index[3]),
        .I1(index[1]),
        .O(\di_reg[3]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[4]_i_1__2 
       (.I0(index[3]),
        .I1(\di_reg[4]_i_2__2_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[4]_i_3__2_n_0 ),
        .I4(\di_reg[4]_i_4__2_n_0 ),
        .I5(\di_reg[4]_i_5__2_n_0 ),
        .O(di_reg[4]));
  LUT6 #(
    .INIT(64'h08080B0830303030)) 
    \di_reg[4]_i_2__2 
       (.I0(do_reg2[4]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[4]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DFFFFFFF)) 
    \di_reg[4]_i_3__2 
       (.I0(index[0]),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\di_reg[4]_i_6__2_n_0 ),
        .O(\di_reg[4]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FFFFE00000000)) 
    \di_reg[4]_i_4__2 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(do_reg2[4]),
        .O(\di_reg[4]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010C00)) 
    \di_reg[4]_i_5__2 
       (.I0(\di_reg[4]_i_7__2_n_0 ),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(\di_reg[4]_i_8__2_n_0 ),
        .I5(index[3]),
        .O(\di_reg[4]_i_5__2_n_0 ));
  LUT5 #(
    .INIT(32'h1F0FFF0F)) 
    \di_reg[4]_i_6__2 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(do_reg2[4]),
        .I4(index[1]),
        .O(\di_reg[4]_i_6__2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \di_reg[4]_i_7__2 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .O(\di_reg[4]_i_7__2_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \di_reg[4]_i_8__2 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .O(\di_reg[4]_i_8__2_n_0 ));
  LUT6 #(
    .INIT(64'h33000000B888B888)) 
    \di_reg[5]_i_1__2 
       (.I0(\di_reg[5]_i_2__2_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[5]_i_3__2_n_0 ),
        .I3(do_reg2[5]),
        .I4(\di_reg[5]_i_4__2_n_0 ),
        .I5(index[3]),
        .O(di_reg[5]));
  LUT6 #(
    .INIT(64'h0B0B080B33333033)) 
    \di_reg[5]_i_2__2 
       (.I0(do_reg2[5]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[5]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \di_reg[5]_i_3__2 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(x16x20_mode_reg2),
        .I4(mode),
        .O(\di_reg[5]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[5]_i_4__2 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[5]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'h67FF000067000000)) 
    \di_reg[6]_i_2__2 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[6]),
        .I5(\di_reg[5]_i_3__2_n_0 ),
        .O(\di_reg[6]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'h00002404)) 
    \di_reg[6]_i_3__2 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[6]),
        .I4(index[3]),
        .O(\di_reg[6]_i_3__2_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF0900)) 
    \di_reg[7]_i_2__2 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[7]),
        .O(\di_reg[7]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000C320032)) 
    \di_reg[7]_i_3__2 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(do_reg2[7]),
        .I5(index[3]),
        .O(\di_reg[7]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[8]_i_1__2 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[8]),
        .O(di_reg[8]));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[9]_i_1__2 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[9]),
        .O(di_reg[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[0]),
        .Q(\di_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[0]_i_1__2 
       (.I0(\di_reg[0]_i_2__2_n_0 ),
        .I1(\di_reg[0]_i_3__2_n_0 ),
        .O(di_reg[0]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[10]),
        .Q(\di_reg_reg_n_0_[10] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[11]),
        .Q(\di_reg_reg_n_0_[11] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[12]),
        .Q(\di_reg_reg_n_0_[12] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[13]),
        .Q(\di_reg_reg_n_0_[13] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[14]),
        .Q(\di_reg_reg_n_0_[14] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[15]),
        .Q(\di_reg_reg_n_0_[15] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[1]),
        .Q(\di_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[2]),
        .Q(\di_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[3]),
        .Q(\di_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[3]_i_1__2 
       (.I0(\di_reg[3]_i_2__2_n_0 ),
        .I1(\di_reg[3]_i_3__2_n_0 ),
        .O(di_reg[3]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[4]),
        .Q(\di_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[5]),
        .Q(\di_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[6]),
        .Q(\di_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[6]_i_1__2 
       (.I0(\di_reg[6]_i_2__2_n_0 ),
        .I1(\di_reg[6]_i_3__2_n_0 ),
        .O(di_reg[6]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[7]),
        .Q(\di_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[7]_i_1__2 
       (.I0(\di_reg[7]_i_2__2_n_0 ),
        .I1(\di_reg[7]_i_3__2_n_0 ),
        .O(di_reg[7]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[8]),
        .Q(\di_reg_reg_n_0_[8] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[9]),
        .Q(\di_reg_reg_n_0_[9] ),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[0]),
        .Q(do_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[10]),
        .Q(do_reg1[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[11]),
        .Q(do_reg1[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[12]),
        .Q(do_reg1[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[13]),
        .Q(do_reg1[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[14]),
        .Q(do_reg1[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[15]),
        .Q(do_reg1[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[1]),
        .Q(do_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[2]),
        .Q(do_reg1[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[3]),
        .Q(do_reg1[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[4]),
        .Q(do_reg1[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[5]),
        .Q(do_reg1[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[6]),
        .Q(do_reg1[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[7]),
        .Q(do_reg1[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[8]),
        .Q(do_reg1[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[9]),
        .Q(do_reg1[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(RST_DCLK_RESET));
  LUT4 #(
    .INIT(16'h0001)) 
    done_i_1__2
       (.I0(start_reg2),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(done_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(done_i_1__2_n_0),
        .Q(DRP_DONE),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0B3BFFFF0B3B0000)) 
    \fsm[0]_i_1__6 
       (.I0(data4),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(rdy_reg2),
        .I4(Q[2]),
        .I5(\fsm[0]_i_3__6_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT5 #(
    .INIT(32'hEFFEFFFF)) 
    \fsm[0]_i_2__2 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[4]),
        .I3(index[2]),
        .I4(mode_i_2__2_n_0),
        .O(data4));
  LUT6 #(
    .INIT(64'h7477FFFF7477CCCC)) 
    \fsm[0]_i_3__6 
       (.I0(rdy_reg2),
        .I1(Q[1]),
        .I2(load_cnt[1]),
        .I3(load_cnt[0]),
        .I4(Q[0]),
        .I5(start_reg2),
        .O(\fsm[0]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'h185018501D501850)) 
    \fsm[1]_i_1__2 
       (.I0(Q[2]),
        .I1(rdy_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(load_cnt[0]),
        .I5(load_cnt[1]),
        .O(fsm[1]));
  LUT4 #(
    .INIT(16'h6222)) 
    \fsm[2]_i_1__6 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(rdy_reg2),
        .I3(Q[0]),
        .O(fsm[2]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \gt_ch_drp_rdy[3]_INST_0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(gt_ch_drp_rdy));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_15__2 
       (.I0(ext_ch_gt_drpdi[15]),
        .I1(\di_reg_reg_n_0_[15] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[15]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_16__2 
       (.I0(ext_ch_gt_drpdi[14]),
        .I1(\di_reg_reg_n_0_[14] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[14]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_17__2 
       (.I0(ext_ch_gt_drpdi[13]),
        .I1(\di_reg_reg_n_0_[13] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[13]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_18__2 
       (.I0(ext_ch_gt_drpdi[12]),
        .I1(\di_reg_reg_n_0_[12] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[12]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_19__2 
       (.I0(ext_ch_gt_drpdi[11]),
        .I1(\di_reg_reg_n_0_[11] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[11]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_20__2 
       (.I0(ext_ch_gt_drpdi[10]),
        .I1(\di_reg_reg_n_0_[10] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[10]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_21__2 
       (.I0(ext_ch_gt_drpdi[9]),
        .I1(\di_reg_reg_n_0_[9] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[9]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_22__2 
       (.I0(ext_ch_gt_drpdi[8]),
        .I1(\di_reg_reg_n_0_[8] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_23__2 
       (.I0(ext_ch_gt_drpdi[7]),
        .I1(\di_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_24__2 
       (.I0(ext_ch_gt_drpdi[6]),
        .I1(\di_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[6]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_25__2 
       (.I0(ext_ch_gt_drpdi[5]),
        .I1(\di_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_26__2 
       (.I0(ext_ch_gt_drpdi[4]),
        .I1(\di_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_27__2 
       (.I0(ext_ch_gt_drpdi[3]),
        .I1(\di_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_28__2 
       (.I0(ext_ch_gt_drpdi[2]),
        .I1(\di_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_29__2 
       (.I0(ext_ch_gt_drpdi[1]),
        .I1(\di_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_30__4 
       (.I0(ext_ch_gt_drpdi[0]),
        .I1(\di_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[0]));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT4 #(
    .INIT(16'h003E)) 
    \gtx_channel.gtxe2_channel_i_i_3__2 
       (.I0(ext_ch_gt_drpen),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\cplllock_reg1_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_48__4 
       (.I0(ext_ch_gt_drpaddr[8]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(DRPADDR[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_49__2 
       (.I0(ext_ch_gt_drpaddr[7]),
        .I1(\addr_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[7]));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT4 #(
    .INIT(16'h0032)) 
    \gtx_channel.gtxe2_channel_i_i_4__2 
       (.I0(ext_ch_gt_drpwe),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(\cplllock_reg1_reg[3]_0 ));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_50__2 
       (.I0(ext_ch_gt_drpaddr[6]),
        .I1(\addr_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[6]));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_51__2 
       (.I0(ext_ch_gt_drpaddr[5]),
        .I1(\addr_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_52__2 
       (.I0(ext_ch_gt_drpaddr[4]),
        .I1(\addr_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_53__2 
       (.I0(ext_ch_gt_drpaddr[3]),
        .I1(\addr_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_54__2 
       (.I0(ext_ch_gt_drpaddr[2]),
        .I1(\addr_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_55__2 
       (.I0(ext_ch_gt_drpaddr[1]),
        .I1(\addr_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_56__4 
       (.I0(ext_ch_gt_drpaddr[0]),
        .I1(\addr_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[0]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rst_gtreset),
        .Q(gtxreset_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(gtxreset_reg1),
        .Q(gtxreset_reg2),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \index[0]_i_1__4 
       (.I0(index[0]),
        .I1(Q[2]),
        .I2(\index[3]_i_2__2_n_0 ),
        .O(\index[0]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT4 #(
    .INIT(16'h0220)) 
    \index[1]_i_1__4 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__2_n_0 ),
        .I2(index[1]),
        .I3(index[0]),
        .O(\index[1]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT5 #(
    .INIT(32'h02222000)) 
    \index[2]_i_1__4 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__2_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .O(\index[2]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h0222222220000000)) 
    \index[3]_i_1__2 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__2_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\index[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAE)) 
    \index[3]_i_2__2 
       (.I0(Q[0]),
        .I1(mode_i_2__2_n_0),
        .I2(index[2]),
        .I3(index[4]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\index[3]_i_2__2_n_0 ));
  LUT3 #(
    .INIT(8'h89)) 
    \index[4]_i_1__2 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\index[4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \index[4]_i_2__2 
       (.I0(index[0]),
        .I1(index[2]),
        .I2(index[3]),
        .I3(index[1]),
        .I4(index[4]),
        .I5(\index[4]_i_3__2_n_0 ),
        .O(\index[4]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \index[4]_i_3__2 
       (.I0(\index[3]_i_2__2_n_0 ),
        .I1(Q[2]),
        .O(\index[4]_i_3__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__2_n_0 ),
        .D(\index[0]_i_1__4_n_0 ),
        .Q(index[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__2_n_0 ),
        .D(\index[1]_i_1__4_n_0 ),
        .Q(index[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__2_n_0 ),
        .D(\index[2]_i_1__4_n_0 ),
        .Q(index[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__2_n_0 ),
        .D(\index[3]_i_1__2_n_0 ),
        .Q(index[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__2_n_0 ),
        .D(\index[4]_i_2__2_n_0 ),
        .Q(index[4]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \load_cnt[0]_i_1__3 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(load_cnt[1]),
        .I3(Q[2]),
        .O(\load_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__3_n_0 ),
        .Q(load_cnt[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(load_cnt[1]),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h00AAA2AAAAAAAA00)) 
    mode_i_1__2
       (.I0(mode),
        .I1(mode_i_2__2_n_0),
        .I2(mode_i_3__4_n_0),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(mode_i_1__2_n_0));
  LUT4 #(
    .INIT(16'hCCB8)) 
    mode_i_2__2
       (.I0(mode),
        .I1(index[0]),
        .I2(x16x20_mode_reg2),
        .I3(index[2]),
        .O(mode_i_2__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    mode_i_3__4
       (.I0(index[2]),
        .I1(index[4]),
        .I2(index[1]),
        .I3(index[3]),
        .O(mode_i_3__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mode_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(mode_i_1__2_n_0),
        .Q(mode),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[0]),
        .Q(rate_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[1]),
        .Q(rate_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drprdy),
        .Q(rdy_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_START),
        .Q(start_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16),
        .Q(x16_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16_reg1),
        .Q(x16_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16X20_MODE),
        .Q(x16x20_mode_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16x20_mode_reg1),
        .Q(x16x20_mode_reg2),
        .R(RST_DCLK_RESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_drp" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_48
   (Q,
    DRPADDR,
    \cplllock_reg1_reg[4] ,
    \cplllock_reg1_reg[4]_0 ,
    gt_ch_drp_rdy,
    DRPDI,
    DRP_DONE,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi,
    RST_DCLK_RESET,
    DRP_X16X20_MODE,
    \resetovrd_disble.reset_reg[4] ,
    DRP_START,
    ext_ch_gt_drprdy,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    DRP_X16,
    ext_ch_gt_drpdo,
    rst_gtreset);
  output [2:0]Q;
  output [8:0]DRPADDR;
  output \cplllock_reg1_reg[4] ;
  output \cplllock_reg1_reg[4]_0 ;
  output [0:0]gt_ch_drp_rdy;
  output [15:0]DRPDI;
  output DRP_DONE;
  input [8:0]ext_ch_gt_drpaddr;
  input [0:0]ext_ch_gt_drpen;
  input [0:0]ext_ch_gt_drpwe;
  input [15:0]ext_ch_gt_drpdi;
  input RST_DCLK_RESET;
  input DRP_X16X20_MODE;
  input \resetovrd_disble.reset_reg[4] ;
  input DRP_START;
  input [0:0]ext_ch_gt_drprdy;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input DRP_X16;
  input [15:0]ext_ch_gt_drpdo;
  input rst_gtreset;

  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_DONE;
  wire DRP_START;
  wire DRP_X16;
  wire DRP_X16X20_MODE;
  wire [2:0]Q;
  wire RST_DCLK_RESET;
  wire \addr_reg[0]_i_1__3_n_0 ;
  wire \addr_reg[1]_i_1__3_n_0 ;
  wire \addr_reg[2]_i_1__3_n_0 ;
  wire \addr_reg[3]_i_1__3_n_0 ;
  wire \addr_reg[4]_i_1__3_n_0 ;
  wire \addr_reg[4]_i_2__3_n_0 ;
  wire \addr_reg[5]_i_1__3_n_0 ;
  wire \addr_reg[6]_i_1__3_n_0 ;
  wire \addr_reg[7]_i_1__3_n_0 ;
  wire \addr_reg[7]_i_2__3_n_0 ;
  wire \addr_reg_reg_n_0_[0] ;
  wire \addr_reg_reg_n_0_[1] ;
  wire \addr_reg_reg_n_0_[2] ;
  wire \addr_reg_reg_n_0_[3] ;
  wire \addr_reg_reg_n_0_[4] ;
  wire \addr_reg_reg_n_0_[5] ;
  wire \addr_reg_reg_n_0_[6] ;
  wire \addr_reg_reg_n_0_[7] ;
  wire \cplllock_reg1_reg[4] ;
  wire \cplllock_reg1_reg[4]_0 ;
  wire [7:7]data15;
  wire data4;
  wire [15:0]di_reg;
  wire \di_reg[0]_i_2__3_n_0 ;
  wire \di_reg[0]_i_3__3_n_0 ;
  wire \di_reg[0]_i_4__3_n_0 ;
  wire \di_reg[0]_i_5__3_n_0 ;
  wire \di_reg[0]_i_6__3_n_0 ;
  wire \di_reg[10]_i_2__3_n_0 ;
  wire \di_reg[11]_i_2__3_n_0 ;
  wire \di_reg[11]_i_3__3_n_0 ;
  wire \di_reg[11]_i_4__3_n_0 ;
  wire \di_reg[11]_i_5__3_n_0 ;
  wire \di_reg[12]_i_2__3_n_0 ;
  wire \di_reg[12]_i_3__3_n_0 ;
  wire \di_reg[12]_i_4__3_n_0 ;
  wire \di_reg[13]_i_2__3_n_0 ;
  wire \di_reg[13]_i_3__3_n_0 ;
  wire \di_reg[13]_i_4__3_n_0 ;
  wire \di_reg[14]_i_2__3_n_0 ;
  wire \di_reg[14]_i_3__3_n_0 ;
  wire \di_reg[14]_i_4__3_n_0 ;
  wire \di_reg[14]_i_6__3_n_0 ;
  wire \di_reg[14]_i_7__3_n_0 ;
  wire \di_reg[15]_i_2__3_n_0 ;
  wire \di_reg[1]_i_2__3_n_0 ;
  wire \di_reg[1]_i_3__3_n_0 ;
  wire \di_reg[1]_i_4__3_n_0 ;
  wire \di_reg[1]_i_5__3_n_0 ;
  wire \di_reg[1]_i_6__3_n_0 ;
  wire \di_reg[2]_i_2__3_n_0 ;
  wire \di_reg[2]_i_3__3_n_0 ;
  wire \di_reg[2]_i_4__3_n_0 ;
  wire \di_reg[2]_i_5__3_n_0 ;
  wire \di_reg[3]_i_2__3_n_0 ;
  wire \di_reg[3]_i_3__3_n_0 ;
  wire \di_reg[3]_i_4__3_n_0 ;
  wire \di_reg[4]_i_2__3_n_0 ;
  wire \di_reg[4]_i_3__3_n_0 ;
  wire \di_reg[4]_i_4__3_n_0 ;
  wire \di_reg[4]_i_5__3_n_0 ;
  wire \di_reg[4]_i_6__3_n_0 ;
  wire \di_reg[4]_i_7__3_n_0 ;
  wire \di_reg[4]_i_8__3_n_0 ;
  wire \di_reg[5]_i_2__3_n_0 ;
  wire \di_reg[5]_i_3__3_n_0 ;
  wire \di_reg[5]_i_4__3_n_0 ;
  wire \di_reg[6]_i_2__3_n_0 ;
  wire \di_reg[6]_i_3__3_n_0 ;
  wire \di_reg[7]_i_2__3_n_0 ;
  wire \di_reg[7]_i_3__3_n_0 ;
  wire \di_reg_reg_n_0_[0] ;
  wire \di_reg_reg_n_0_[10] ;
  wire \di_reg_reg_n_0_[11] ;
  wire \di_reg_reg_n_0_[12] ;
  wire \di_reg_reg_n_0_[13] ;
  wire \di_reg_reg_n_0_[14] ;
  wire \di_reg_reg_n_0_[15] ;
  wire \di_reg_reg_n_0_[1] ;
  wire \di_reg_reg_n_0_[2] ;
  wire \di_reg_reg_n_0_[3] ;
  wire \di_reg_reg_n_0_[4] ;
  wire \di_reg_reg_n_0_[5] ;
  wire \di_reg_reg_n_0_[6] ;
  wire \di_reg_reg_n_0_[7] ;
  wire \di_reg_reg_n_0_[8] ;
  wire \di_reg_reg_n_0_[9] ;
  wire [15:0]do_reg1;
  wire [15:0]do_reg2;
  wire done_i_1__3_n_0;
  wire [8:0]ext_ch_gt_drpaddr;
  wire [15:0]ext_ch_gt_drpdi;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drpen;
  wire [0:0]ext_ch_gt_drprdy;
  wire [0:0]ext_ch_gt_drpwe;
  wire [2:0]fsm;
  wire \fsm[0]_i_3__8_n_0 ;
  wire [0:0]gt_ch_drp_rdy;
  wire gtxreset_reg1;
  wire gtxreset_reg2;
  wire [4:0]index;
  wire \index[0]_i_1__5_n_0 ;
  wire \index[1]_i_1__5_n_0 ;
  wire \index[2]_i_1__5_n_0 ;
  wire \index[3]_i_1__3_n_0 ;
  wire \index[3]_i_2__3_n_0 ;
  wire \index[4]_i_1__3_n_0 ;
  wire \index[4]_i_2__3_n_0 ;
  wire \index[4]_i_3__3_n_0 ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1__4_n_0 ;
  wire mode;
  wire mode_i_1__3_n_0;
  wire mode_i_2__3_n_0;
  wire mode_i_3__5_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire [1:0]rate_reg1;
  wire [1:0]rate_reg2;
  wire rdy_reg1;
  wire rdy_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_gtreset;
  wire start_reg1;
  wire start_reg2;
  wire x16_reg1;
  wire x16_reg2;
  wire x16x20_mode_reg1;
  wire x16x20_mode_reg2;

  LUT6 #(
    .INIT(64'h1471357514713564)) 
    \addr_reg[0]_i_1__3 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__3_n_0 ),
        .O(\addr_reg[0]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h404050500F0F0500)) 
    \addr_reg[1]_i_1__3 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[1]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h051005105A055A00)) 
    \addr_reg[2]_i_1__3 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(index[2]),
        .I4(mode),
        .I5(index[1]),
        .O(\addr_reg[2]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h5767576753275326)) 
    \addr_reg[3]_i_1__3 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(\addr_reg[4]_i_2__3_n_0 ),
        .I5(index[0]),
        .O(\addr_reg[3]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FCCFFF01)) 
    \addr_reg[4]_i_1__3 
       (.I0(\addr_reg[4]_i_2__3_n_0 ),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[3]),
        .I5(index[4]),
        .O(\addr_reg[4]_i_1__3_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \addr_reg[4]_i_2__3 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .O(\addr_reg[4]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h00001A1A0F0F0F0A)) 
    \addr_reg[5]_i_1__3 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[5]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000011545554)) 
    \addr_reg[6]_i_1__3 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(mode),
        .I3(index[3]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\addr_reg[6]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h5422262254222633)) 
    \addr_reg[7]_i_1__3 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__3_n_0 ),
        .O(\addr_reg[7]_i_1__3_n_0 ));
  LUT3 #(
    .INIT(8'hCE)) 
    \addr_reg[7]_i_2__3 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .I2(index[0]),
        .O(\addr_reg[7]_i_2__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[0]_i_1__3_n_0 ),
        .Q(\addr_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[1]_i_1__3_n_0 ),
        .Q(\addr_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[2]_i_1__3_n_0 ),
        .Q(\addr_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[3]_i_1__3_n_0 ),
        .Q(\addr_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[4]_i_1__3_n_0 ),
        .Q(\addr_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[5]_i_1__3_n_0 ),
        .Q(\addr_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[6]_i_1__3_n_0 ),
        .Q(\addr_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[7]_i_1__3_n_0 ),
        .Q(\addr_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'hB8B8B8BBB8B8B888)) 
    \di_reg[0]_i_2__3 
       (.I0(\di_reg[0]_i_4__3_n_0 ),
        .I1(index[3]),
        .I2(do_reg2[0]),
        .I3(\di_reg[0]_i_5__3_n_0 ),
        .I4(\di_reg[0]_i_6__3_n_0 ),
        .I5(\di_reg[4]_i_8__3_n_0 ),
        .O(\di_reg[0]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h00003414)) 
    \di_reg[0]_i_3__3 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[0]),
        .I4(index[3]),
        .O(\di_reg[0]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hB0BFFFFFB0B00000)) 
    \di_reg[0]_i_4__3 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(do_reg2[0]),
        .O(\di_reg[0]_i_4__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \di_reg[0]_i_5__3 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .O(\di_reg[0]_i_5__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \di_reg[0]_i_6__3 
       (.I0(index[1]),
        .I1(mode),
        .I2(index[0]),
        .O(\di_reg[0]_i_6__3_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[10]_i_1__3 
       (.I0(index[4]),
        .I1(do_reg2[10]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[10]_i_2__3_n_0 ),
        .O(di_reg[10]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[10]_i_2__3 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[10]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[11]_i_1__3 
       (.I0(index[3]),
        .I1(\di_reg[11]_i_2__3_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[11]_i_3__3_n_0 ),
        .I4(\di_reg[11]_i_4__3_n_0 ),
        .I5(\di_reg[11]_i_5__3_n_0 ),
        .O(di_reg[11]));
  LUT6 #(
    .INIT(64'h0808080808380808)) 
    \di_reg[11]_i_2__3 
       (.I0(do_reg2[11]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[0]),
        .I4(rate_reg2[1]),
        .I5(index[0]),
        .O(\di_reg[11]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'hCC0CCC0C0C0C880C)) 
    \di_reg[11]_i_3__3 
       (.I0(data15),
        .I1(index[3]),
        .I2(do_reg2[11]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[11]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAAAAAABAAABA)) 
    \di_reg[11]_i_4__3 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[11]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAA00AAAAAAA3)) 
    \di_reg[11]_i_5__3 
       (.I0(do_reg2[11]),
        .I1(x16_reg2),
        .I2(\addr_reg[4]_i_2__3_n_0 ),
        .I3(index[0]),
        .I4(index[1]),
        .I5(index[2]),
        .O(\di_reg[11]_i_5__3_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \di_reg[12]_i_1__3 
       (.I0(\di_reg[12]_i_2__3_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[12]_i_3__3_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[12]_i_4__3_n_0 ),
        .O(di_reg[12]));
  LUT5 #(
    .INIT(32'h00003202)) 
    \di_reg[12]_i_2__3 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[12]),
        .I4(index[3]),
        .O(\di_reg[12]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[12]_i_3__3 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[12]),
        .O(\di_reg[12]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAA8AAABAAABA)) 
    \di_reg[12]_i_4__3 
       (.I0(do_reg2[12]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[12]_i_4__3_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \di_reg[13]_i_1__3 
       (.I0(\di_reg[13]_i_2__3_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[13]_i_3__3_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[13]_i_4__3_n_0 ),
        .O(di_reg[13]));
  LUT6 #(
    .INIT(64'h0808080838380838)) 
    \di_reg[13]_i_2__3 
       (.I0(do_reg2[13]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[13]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[13]_i_3__3 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[13]),
        .O(\di_reg[13]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hAA8AAA8AAABAAA8A)) 
    \di_reg[13]_i_4__3 
       (.I0(do_reg2[13]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[1]),
        .I5(rate_reg2[0]),
        .O(\di_reg[13]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'h080008FF08000800)) 
    \di_reg[14]_i_1__3 
       (.I0(do_reg2[14]),
        .I1(\di_reg[14]_i_2__3_n_0 ),
        .I2(index[3]),
        .I3(index[4]),
        .I4(\di_reg[14]_i_3__3_n_0 ),
        .I5(\di_reg[14]_i_4__3_n_0 ),
        .O(di_reg[14]));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_2__3 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[14]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h0033303310130033)) 
    \di_reg[14]_i_3__3 
       (.I0(data15),
        .I1(index[3]),
        .I2(index[2]),
        .I3(do_reg2[14]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[14]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000DF10)) 
    \di_reg[14]_i_4__3 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(do_reg2[14]),
        .I4(index[2]),
        .I5(\di_reg[14]_i_6__3_n_0 ),
        .O(\di_reg[14]_i_4__3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_5__3 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .O(data15));
  LUT6 #(
    .INIT(64'hBBBB3BBBBBBB3FBB)) 
    \di_reg[14]_i_6__3 
       (.I0(\di_reg[14]_i_7__3_n_0 ),
        .I1(index[3]),
        .I2(index[0]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(\di_reg[5]_i_4__3_n_0 ),
        .O(\di_reg[14]_i_6__3_n_0 ));
  LUT4 #(
    .INIT(16'h4440)) 
    \di_reg[14]_i_7__3 
       (.I0(index[1]),
        .I1(index[2]),
        .I2(do_reg2[14]),
        .I3(index[0]),
        .O(\di_reg[14]_i_7__3_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[15]_i_1__3 
       (.I0(index[4]),
        .I1(do_reg2[15]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[15]_i_2__3_n_0 ),
        .O(di_reg[15]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[15]_i_2__3 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[15]_i_2__3_n_0 ));
  LUT4 #(
    .INIT(16'hABAA)) 
    \di_reg[1]_i_1__3 
       (.I0(\di_reg[1]_i_2__3_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[1]_i_3__3_n_0 ),
        .I3(\di_reg[1]_i_4__3_n_0 ),
        .O(di_reg[1]));
  LUT6 #(
    .INIT(64'h0000000034140000)) 
    \di_reg[1]_i_2__3 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[1]),
        .I4(index[4]),
        .I5(index[3]),
        .O(\di_reg[1]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FB330000)) 
    \di_reg[1]_i_3__3 
       (.I0(index[2]),
        .I1(do_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[3]),
        .I5(\di_reg[1]_i_5__3_n_0 ),
        .O(\di_reg[1]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFCCC5555)) 
    \di_reg[1]_i_4__3 
       (.I0(\di_reg[1]_i_6__3_n_0 ),
        .I1(do_reg2[1]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\di_reg[1]_i_4__3_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \di_reg[1]_i_5__3 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .I3(index[1]),
        .O(\di_reg[1]_i_5__3_n_0 ));
  LUT6 #(
    .INIT(64'h002F0F20F02FFF2F)) 
    \di_reg[1]_i_6__3 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(mode),
        .I5(do_reg2[1]),
        .O(\di_reg[1]_i_6__3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[2]_i_1__3 
       (.I0(\di_reg[2]_i_2__3_n_0 ),
        .I1(\di_reg[2]_i_3__3_n_0 ),
        .O(di_reg[2]));
  LUT6 #(
    .INIT(64'h00400500FFFFFFFF)) 
    \di_reg[2]_i_2__3 
       (.I0(index[3]),
        .I1(do_reg2[2]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\di_reg[2]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF470047)) 
    \di_reg[2]_i_3__3 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(\di_reg[2]_i_4__3_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[2]_i_5__3_n_0 ),
        .I5(index[4]),
        .O(\di_reg[2]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hF4F40404F00FF000)) 
    \di_reg[2]_i_4__3 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(mode),
        .I4(do_reg2[2]),
        .I5(index[1]),
        .O(\di_reg[2]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'hF5D535D5F5D5F5D5)) 
    \di_reg[2]_i_5__3 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[2]_i_5__3_n_0 ));
  LUT6 #(
    .INIT(64'hBAAA1000AAFF0000)) 
    \di_reg[3]_i_2__3 
       (.I0(\di_reg[3]_i_4__3_n_0 ),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(do_reg2[3]),
        .I5(index[0]),
        .O(\di_reg[3]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000033E200)) 
    \di_reg[3]_i_3__3 
       (.I0(data15),
        .I1(index[0]),
        .I2(do_reg2[3]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\di_reg[3]_i_3__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[3]_i_4__3 
       (.I0(index[3]),
        .I1(index[1]),
        .O(\di_reg[3]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[4]_i_1__3 
       (.I0(index[3]),
        .I1(\di_reg[4]_i_2__3_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[4]_i_3__3_n_0 ),
        .I4(\di_reg[4]_i_4__3_n_0 ),
        .I5(\di_reg[4]_i_5__3_n_0 ),
        .O(di_reg[4]));
  LUT6 #(
    .INIT(64'h08080B0830303030)) 
    \di_reg[4]_i_2__3 
       (.I0(do_reg2[4]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[4]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DFFFFFFF)) 
    \di_reg[4]_i_3__3 
       (.I0(index[0]),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\di_reg[4]_i_6__3_n_0 ),
        .O(\di_reg[4]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FFFFE00000000)) 
    \di_reg[4]_i_4__3 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(do_reg2[4]),
        .O(\di_reg[4]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010C00)) 
    \di_reg[4]_i_5__3 
       (.I0(\di_reg[4]_i_7__3_n_0 ),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(\di_reg[4]_i_8__3_n_0 ),
        .I5(index[3]),
        .O(\di_reg[4]_i_5__3_n_0 ));
  LUT5 #(
    .INIT(32'h1F0FFF0F)) 
    \di_reg[4]_i_6__3 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(do_reg2[4]),
        .I4(index[1]),
        .O(\di_reg[4]_i_6__3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \di_reg[4]_i_7__3 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .O(\di_reg[4]_i_7__3_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \di_reg[4]_i_8__3 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .O(\di_reg[4]_i_8__3_n_0 ));
  LUT6 #(
    .INIT(64'h33000000B888B888)) 
    \di_reg[5]_i_1__3 
       (.I0(\di_reg[5]_i_2__3_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[5]_i_3__3_n_0 ),
        .I3(do_reg2[5]),
        .I4(\di_reg[5]_i_4__3_n_0 ),
        .I5(index[3]),
        .O(di_reg[5]));
  LUT6 #(
    .INIT(64'h0B0B080B33333033)) 
    \di_reg[5]_i_2__3 
       (.I0(do_reg2[5]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[5]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \di_reg[5]_i_3__3 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(x16x20_mode_reg2),
        .I4(mode),
        .O(\di_reg[5]_i_3__3_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[5]_i_4__3 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[5]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'h67FF000067000000)) 
    \di_reg[6]_i_2__3 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[6]),
        .I5(\di_reg[5]_i_3__3_n_0 ),
        .O(\di_reg[6]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h00002404)) 
    \di_reg[6]_i_3__3 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[6]),
        .I4(index[3]),
        .O(\di_reg[6]_i_3__3_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF0900)) 
    \di_reg[7]_i_2__3 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[7]),
        .O(\di_reg[7]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000C320032)) 
    \di_reg[7]_i_3__3 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(do_reg2[7]),
        .I5(index[3]),
        .O(\di_reg[7]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[8]_i_1__3 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[8]),
        .O(di_reg[8]));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[9]_i_1__3 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[9]),
        .O(di_reg[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[0]),
        .Q(\di_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[0]_i_1__3 
       (.I0(\di_reg[0]_i_2__3_n_0 ),
        .I1(\di_reg[0]_i_3__3_n_0 ),
        .O(di_reg[0]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[10]),
        .Q(\di_reg_reg_n_0_[10] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[11]),
        .Q(\di_reg_reg_n_0_[11] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[12]),
        .Q(\di_reg_reg_n_0_[12] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[13]),
        .Q(\di_reg_reg_n_0_[13] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[14]),
        .Q(\di_reg_reg_n_0_[14] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[15]),
        .Q(\di_reg_reg_n_0_[15] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[1]),
        .Q(\di_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[2]),
        .Q(\di_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[3]),
        .Q(\di_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[3]_i_1__3 
       (.I0(\di_reg[3]_i_2__3_n_0 ),
        .I1(\di_reg[3]_i_3__3_n_0 ),
        .O(di_reg[3]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[4]),
        .Q(\di_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[5]),
        .Q(\di_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[6]),
        .Q(\di_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[6]_i_1__3 
       (.I0(\di_reg[6]_i_2__3_n_0 ),
        .I1(\di_reg[6]_i_3__3_n_0 ),
        .O(di_reg[6]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[7]),
        .Q(\di_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[7]_i_1__3 
       (.I0(\di_reg[7]_i_2__3_n_0 ),
        .I1(\di_reg[7]_i_3__3_n_0 ),
        .O(di_reg[7]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[8]),
        .Q(\di_reg_reg_n_0_[8] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[9]),
        .Q(\di_reg_reg_n_0_[9] ),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[0]),
        .Q(do_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[10]),
        .Q(do_reg1[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[11]),
        .Q(do_reg1[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[12]),
        .Q(do_reg1[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[13]),
        .Q(do_reg1[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[14]),
        .Q(do_reg1[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[15]),
        .Q(do_reg1[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[1]),
        .Q(do_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[2]),
        .Q(do_reg1[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[3]),
        .Q(do_reg1[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[4]),
        .Q(do_reg1[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[5]),
        .Q(do_reg1[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[6]),
        .Q(do_reg1[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[7]),
        .Q(do_reg1[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[8]),
        .Q(do_reg1[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[9]),
        .Q(do_reg1[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(RST_DCLK_RESET));
  LUT4 #(
    .INIT(16'h0001)) 
    done_i_1__3
       (.I0(start_reg2),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(done_i_1__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(done_i_1__3_n_0),
        .Q(DRP_DONE),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0B3BFFFF0B3B0000)) 
    \fsm[0]_i_1__8 
       (.I0(data4),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(rdy_reg2),
        .I4(Q[2]),
        .I5(\fsm[0]_i_3__8_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT5 #(
    .INIT(32'hEFFEFFFF)) 
    \fsm[0]_i_2__3 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[4]),
        .I3(index[2]),
        .I4(mode_i_2__3_n_0),
        .O(data4));
  LUT6 #(
    .INIT(64'h7477FFFF7477CCCC)) 
    \fsm[0]_i_3__8 
       (.I0(rdy_reg2),
        .I1(Q[1]),
        .I2(load_cnt[1]),
        .I3(load_cnt[0]),
        .I4(Q[0]),
        .I5(start_reg2),
        .O(\fsm[0]_i_3__8_n_0 ));
  LUT6 #(
    .INIT(64'h185018501D501850)) 
    \fsm[1]_i_1__3 
       (.I0(Q[2]),
        .I1(rdy_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(load_cnt[0]),
        .I5(load_cnt[1]),
        .O(fsm[1]));
  LUT4 #(
    .INIT(16'h6222)) 
    \fsm[2]_i_1__8 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(rdy_reg2),
        .I3(Q[0]),
        .O(fsm[2]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \gt_ch_drp_rdy[4]_INST_0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(gt_ch_drp_rdy));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_14__5 
       (.I0(ext_ch_gt_drpdi[15]),
        .I1(\di_reg_reg_n_0_[15] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[15]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_15__3 
       (.I0(ext_ch_gt_drpdi[14]),
        .I1(\di_reg_reg_n_0_[14] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[14]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_16__3 
       (.I0(ext_ch_gt_drpdi[13]),
        .I1(\di_reg_reg_n_0_[13] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[13]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_17__3 
       (.I0(ext_ch_gt_drpdi[12]),
        .I1(\di_reg_reg_n_0_[12] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[12]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_18__3 
       (.I0(ext_ch_gt_drpdi[11]),
        .I1(\di_reg_reg_n_0_[11] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[11]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_19__3 
       (.I0(ext_ch_gt_drpdi[10]),
        .I1(\di_reg_reg_n_0_[10] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[10]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_20__3 
       (.I0(ext_ch_gt_drpdi[9]),
        .I1(\di_reg_reg_n_0_[9] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[9]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_21__3 
       (.I0(ext_ch_gt_drpdi[8]),
        .I1(\di_reg_reg_n_0_[8] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_22__3 
       (.I0(ext_ch_gt_drpdi[7]),
        .I1(\di_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_23__3 
       (.I0(ext_ch_gt_drpdi[6]),
        .I1(\di_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[6]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_24__3 
       (.I0(ext_ch_gt_drpdi[5]),
        .I1(\di_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_25__3 
       (.I0(ext_ch_gt_drpdi[4]),
        .I1(\di_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_26__3 
       (.I0(ext_ch_gt_drpdi[3]),
        .I1(\di_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_27__3 
       (.I0(ext_ch_gt_drpdi[2]),
        .I1(\di_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_28__3 
       (.I0(ext_ch_gt_drpdi[1]),
        .I1(\di_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_29__3 
       (.I0(ext_ch_gt_drpdi[0]),
        .I1(\di_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[0]));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT4 #(
    .INIT(16'h003E)) 
    \gtx_channel.gtxe2_channel_i_i_3__3 
       (.I0(ext_ch_gt_drpen),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\cplllock_reg1_reg[4] ));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_47__5 
       (.I0(ext_ch_gt_drpaddr[8]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(DRPADDR[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_48__1 
       (.I0(ext_ch_gt_drpaddr[7]),
        .I1(\addr_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_49__3 
       (.I0(ext_ch_gt_drpaddr[6]),
        .I1(\addr_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[6]));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT4 #(
    .INIT(16'h0032)) 
    \gtx_channel.gtxe2_channel_i_i_4__3 
       (.I0(ext_ch_gt_drpwe),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(\cplllock_reg1_reg[4]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_50__3 
       (.I0(ext_ch_gt_drpaddr[5]),
        .I1(\addr_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_51__3 
       (.I0(ext_ch_gt_drpaddr[4]),
        .I1(\addr_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_52__3 
       (.I0(ext_ch_gt_drpaddr[3]),
        .I1(\addr_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_53__3 
       (.I0(ext_ch_gt_drpaddr[2]),
        .I1(\addr_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_54__3 
       (.I0(ext_ch_gt_drpaddr[1]),
        .I1(\addr_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_55__3 
       (.I0(ext_ch_gt_drpaddr[0]),
        .I1(\addr_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[0]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rst_gtreset),
        .Q(gtxreset_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(gtxreset_reg1),
        .Q(gtxreset_reg2),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \index[0]_i_1__5 
       (.I0(index[0]),
        .I1(Q[2]),
        .I2(\index[3]_i_2__3_n_0 ),
        .O(\index[0]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT4 #(
    .INIT(16'h0220)) 
    \index[1]_i_1__5 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__3_n_0 ),
        .I2(index[1]),
        .I3(index[0]),
        .O(\index[1]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT5 #(
    .INIT(32'h02222000)) 
    \index[2]_i_1__5 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__3_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .O(\index[2]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h0222222220000000)) 
    \index[3]_i_1__3 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__3_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\index[3]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAE)) 
    \index[3]_i_2__3 
       (.I0(Q[0]),
        .I1(mode_i_2__3_n_0),
        .I2(index[2]),
        .I3(index[4]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\index[3]_i_2__3_n_0 ));
  LUT3 #(
    .INIT(8'h89)) 
    \index[4]_i_1__3 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\index[4]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \index[4]_i_2__3 
       (.I0(index[0]),
        .I1(index[2]),
        .I2(index[3]),
        .I3(index[1]),
        .I4(index[4]),
        .I5(\index[4]_i_3__3_n_0 ),
        .O(\index[4]_i_2__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \index[4]_i_3__3 
       (.I0(\index[3]_i_2__3_n_0 ),
        .I1(Q[2]),
        .O(\index[4]_i_3__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__3_n_0 ),
        .D(\index[0]_i_1__5_n_0 ),
        .Q(index[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__3_n_0 ),
        .D(\index[1]_i_1__5_n_0 ),
        .Q(index[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__3_n_0 ),
        .D(\index[2]_i_1__5_n_0 ),
        .Q(index[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__3_n_0 ),
        .D(\index[3]_i_1__3_n_0 ),
        .Q(index[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__3_n_0 ),
        .D(\index[4]_i_2__3_n_0 ),
        .Q(index[4]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \load_cnt[0]_i_1__4 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(load_cnt[1]),
        .I3(Q[2]),
        .O(\load_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__4_n_0 ),
        .Q(load_cnt[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(load_cnt[1]),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h00AAA2AAAAAAAA00)) 
    mode_i_1__3
       (.I0(mode),
        .I1(mode_i_2__3_n_0),
        .I2(mode_i_3__5_n_0),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(mode_i_1__3_n_0));
  LUT4 #(
    .INIT(16'hCCB8)) 
    mode_i_2__3
       (.I0(mode),
        .I1(index[0]),
        .I2(x16x20_mode_reg2),
        .I3(index[2]),
        .O(mode_i_2__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    mode_i_3__5
       (.I0(index[2]),
        .I1(index[4]),
        .I2(index[1]),
        .I3(index[3]),
        .O(mode_i_3__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mode_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(mode_i_1__3_n_0),
        .Q(mode),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[0]),
        .Q(rate_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[1]),
        .Q(rate_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drprdy),
        .Q(rdy_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_START),
        .Q(start_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16),
        .Q(x16_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16_reg1),
        .Q(x16_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16X20_MODE),
        .Q(x16x20_mode_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16x20_mode_reg1),
        .Q(x16x20_mode_reg2),
        .R(RST_DCLK_RESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_drp" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_55
   (Q,
    DRPADDR,
    \cplllock_reg1_reg[5] ,
    \cplllock_reg1_reg[5]_0 ,
    gt_ch_drp_rdy,
    DRPDI,
    DRP_DONE,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi,
    RST_DCLK_RESET,
    DRP_X16X20_MODE,
    \resetovrd_disble.reset_reg[4] ,
    DRP_START,
    ext_ch_gt_drprdy,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    DRP_X16,
    ext_ch_gt_drpdo,
    rst_gtreset);
  output [2:0]Q;
  output [8:0]DRPADDR;
  output \cplllock_reg1_reg[5] ;
  output \cplllock_reg1_reg[5]_0 ;
  output [0:0]gt_ch_drp_rdy;
  output [15:0]DRPDI;
  output DRP_DONE;
  input [8:0]ext_ch_gt_drpaddr;
  input [0:0]ext_ch_gt_drpen;
  input [0:0]ext_ch_gt_drpwe;
  input [15:0]ext_ch_gt_drpdi;
  input RST_DCLK_RESET;
  input DRP_X16X20_MODE;
  input \resetovrd_disble.reset_reg[4] ;
  input DRP_START;
  input [0:0]ext_ch_gt_drprdy;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input DRP_X16;
  input [15:0]ext_ch_gt_drpdo;
  input rst_gtreset;

  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_DONE;
  wire DRP_START;
  wire DRP_X16;
  wire DRP_X16X20_MODE;
  wire [2:0]Q;
  wire RST_DCLK_RESET;
  wire \addr_reg[0]_i_1__4_n_0 ;
  wire \addr_reg[1]_i_1__4_n_0 ;
  wire \addr_reg[2]_i_1__4_n_0 ;
  wire \addr_reg[3]_i_1__4_n_0 ;
  wire \addr_reg[4]_i_1__4_n_0 ;
  wire \addr_reg[4]_i_2__4_n_0 ;
  wire \addr_reg[5]_i_1__4_n_0 ;
  wire \addr_reg[6]_i_1__4_n_0 ;
  wire \addr_reg[7]_i_1__4_n_0 ;
  wire \addr_reg[7]_i_2__4_n_0 ;
  wire \addr_reg_reg_n_0_[0] ;
  wire \addr_reg_reg_n_0_[1] ;
  wire \addr_reg_reg_n_0_[2] ;
  wire \addr_reg_reg_n_0_[3] ;
  wire \addr_reg_reg_n_0_[4] ;
  wire \addr_reg_reg_n_0_[5] ;
  wire \addr_reg_reg_n_0_[6] ;
  wire \addr_reg_reg_n_0_[7] ;
  wire \cplllock_reg1_reg[5] ;
  wire \cplllock_reg1_reg[5]_0 ;
  wire [7:7]data15;
  wire data4;
  wire [15:0]di_reg;
  wire \di_reg[0]_i_2__4_n_0 ;
  wire \di_reg[0]_i_3__4_n_0 ;
  wire \di_reg[0]_i_4__4_n_0 ;
  wire \di_reg[0]_i_5__4_n_0 ;
  wire \di_reg[0]_i_6__4_n_0 ;
  wire \di_reg[10]_i_2__4_n_0 ;
  wire \di_reg[11]_i_2__4_n_0 ;
  wire \di_reg[11]_i_3__4_n_0 ;
  wire \di_reg[11]_i_4__4_n_0 ;
  wire \di_reg[11]_i_5__4_n_0 ;
  wire \di_reg[12]_i_2__4_n_0 ;
  wire \di_reg[12]_i_3__4_n_0 ;
  wire \di_reg[12]_i_4__4_n_0 ;
  wire \di_reg[13]_i_2__4_n_0 ;
  wire \di_reg[13]_i_3__4_n_0 ;
  wire \di_reg[13]_i_4__4_n_0 ;
  wire \di_reg[14]_i_2__4_n_0 ;
  wire \di_reg[14]_i_3__4_n_0 ;
  wire \di_reg[14]_i_4__4_n_0 ;
  wire \di_reg[14]_i_6__4_n_0 ;
  wire \di_reg[14]_i_7__4_n_0 ;
  wire \di_reg[15]_i_2__4_n_0 ;
  wire \di_reg[1]_i_2__4_n_0 ;
  wire \di_reg[1]_i_3__4_n_0 ;
  wire \di_reg[1]_i_4__4_n_0 ;
  wire \di_reg[1]_i_5__4_n_0 ;
  wire \di_reg[1]_i_6__4_n_0 ;
  wire \di_reg[2]_i_2__4_n_0 ;
  wire \di_reg[2]_i_3__4_n_0 ;
  wire \di_reg[2]_i_4__4_n_0 ;
  wire \di_reg[2]_i_5__4_n_0 ;
  wire \di_reg[3]_i_2__4_n_0 ;
  wire \di_reg[3]_i_3__4_n_0 ;
  wire \di_reg[3]_i_4__4_n_0 ;
  wire \di_reg[4]_i_2__4_n_0 ;
  wire \di_reg[4]_i_3__4_n_0 ;
  wire \di_reg[4]_i_4__4_n_0 ;
  wire \di_reg[4]_i_5__4_n_0 ;
  wire \di_reg[4]_i_6__4_n_0 ;
  wire \di_reg[4]_i_7__4_n_0 ;
  wire \di_reg[4]_i_8__4_n_0 ;
  wire \di_reg[5]_i_2__4_n_0 ;
  wire \di_reg[5]_i_3__4_n_0 ;
  wire \di_reg[5]_i_4__4_n_0 ;
  wire \di_reg[6]_i_2__4_n_0 ;
  wire \di_reg[6]_i_3__4_n_0 ;
  wire \di_reg[7]_i_2__4_n_0 ;
  wire \di_reg[7]_i_3__4_n_0 ;
  wire \di_reg_reg_n_0_[0] ;
  wire \di_reg_reg_n_0_[10] ;
  wire \di_reg_reg_n_0_[11] ;
  wire \di_reg_reg_n_0_[12] ;
  wire \di_reg_reg_n_0_[13] ;
  wire \di_reg_reg_n_0_[14] ;
  wire \di_reg_reg_n_0_[15] ;
  wire \di_reg_reg_n_0_[1] ;
  wire \di_reg_reg_n_0_[2] ;
  wire \di_reg_reg_n_0_[3] ;
  wire \di_reg_reg_n_0_[4] ;
  wire \di_reg_reg_n_0_[5] ;
  wire \di_reg_reg_n_0_[6] ;
  wire \di_reg_reg_n_0_[7] ;
  wire \di_reg_reg_n_0_[8] ;
  wire \di_reg_reg_n_0_[9] ;
  wire [15:0]do_reg1;
  wire [15:0]do_reg2;
  wire done_i_1__4_n_0;
  wire [8:0]ext_ch_gt_drpaddr;
  wire [15:0]ext_ch_gt_drpdi;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drpen;
  wire [0:0]ext_ch_gt_drprdy;
  wire [0:0]ext_ch_gt_drpwe;
  wire [2:0]fsm;
  wire \fsm[0]_i_3__10_n_0 ;
  wire [0:0]gt_ch_drp_rdy;
  wire gtxreset_reg1;
  wire gtxreset_reg2;
  wire [4:0]index;
  wire \index[0]_i_1__6_n_0 ;
  wire \index[1]_i_1__6_n_0 ;
  wire \index[2]_i_1__6_n_0 ;
  wire \index[3]_i_1__4_n_0 ;
  wire \index[3]_i_2__4_n_0 ;
  wire \index[4]_i_1__4_n_0 ;
  wire \index[4]_i_2__4_n_0 ;
  wire \index[4]_i_3__4_n_0 ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1__6_n_0 ;
  wire mode;
  wire mode_i_1__4_n_0;
  wire mode_i_2__4_n_0;
  wire mode_i_3__6_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire [1:0]rate_reg1;
  wire [1:0]rate_reg2;
  wire rdy_reg1;
  wire rdy_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_gtreset;
  wire start_reg1;
  wire start_reg2;
  wire x16_reg1;
  wire x16_reg2;
  wire x16x20_mode_reg1;
  wire x16x20_mode_reg2;

  LUT6 #(
    .INIT(64'h1471357514713564)) 
    \addr_reg[0]_i_1__4 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__4_n_0 ),
        .O(\addr_reg[0]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h404050500F0F0500)) 
    \addr_reg[1]_i_1__4 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[1]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h051005105A055A00)) 
    \addr_reg[2]_i_1__4 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(index[2]),
        .I4(mode),
        .I5(index[1]),
        .O(\addr_reg[2]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h5767576753275326)) 
    \addr_reg[3]_i_1__4 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(\addr_reg[4]_i_2__4_n_0 ),
        .I5(index[0]),
        .O(\addr_reg[3]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FCCFFF01)) 
    \addr_reg[4]_i_1__4 
       (.I0(\addr_reg[4]_i_2__4_n_0 ),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[3]),
        .I5(index[4]),
        .O(\addr_reg[4]_i_1__4_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \addr_reg[4]_i_2__4 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .O(\addr_reg[4]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h00001A1A0F0F0F0A)) 
    \addr_reg[5]_i_1__4 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[5]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000011545554)) 
    \addr_reg[6]_i_1__4 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(mode),
        .I3(index[3]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\addr_reg[6]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h5422262254222633)) 
    \addr_reg[7]_i_1__4 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__4_n_0 ),
        .O(\addr_reg[7]_i_1__4_n_0 ));
  LUT3 #(
    .INIT(8'hCE)) 
    \addr_reg[7]_i_2__4 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .I2(index[0]),
        .O(\addr_reg[7]_i_2__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[0]_i_1__4_n_0 ),
        .Q(\addr_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[1]_i_1__4_n_0 ),
        .Q(\addr_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[2]_i_1__4_n_0 ),
        .Q(\addr_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[3]_i_1__4_n_0 ),
        .Q(\addr_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[4]_i_1__4_n_0 ),
        .Q(\addr_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[5]_i_1__4_n_0 ),
        .Q(\addr_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[6]_i_1__4_n_0 ),
        .Q(\addr_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[7]_i_1__4_n_0 ),
        .Q(\addr_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'hB8B8B8BBB8B8B888)) 
    \di_reg[0]_i_2__4 
       (.I0(\di_reg[0]_i_4__4_n_0 ),
        .I1(index[3]),
        .I2(do_reg2[0]),
        .I3(\di_reg[0]_i_5__4_n_0 ),
        .I4(\di_reg[0]_i_6__4_n_0 ),
        .I5(\di_reg[4]_i_8__4_n_0 ),
        .O(\di_reg[0]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'h00003414)) 
    \di_reg[0]_i_3__4 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[0]),
        .I4(index[3]),
        .O(\di_reg[0]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hB0BFFFFFB0B00000)) 
    \di_reg[0]_i_4__4 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(do_reg2[0]),
        .O(\di_reg[0]_i_4__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \di_reg[0]_i_5__4 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .O(\di_reg[0]_i_5__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \di_reg[0]_i_6__4 
       (.I0(index[1]),
        .I1(mode),
        .I2(index[0]),
        .O(\di_reg[0]_i_6__4_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[10]_i_1__4 
       (.I0(index[4]),
        .I1(do_reg2[10]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[10]_i_2__4_n_0 ),
        .O(di_reg[10]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[10]_i_2__4 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[10]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[11]_i_1__4 
       (.I0(index[3]),
        .I1(\di_reg[11]_i_2__4_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[11]_i_3__4_n_0 ),
        .I4(\di_reg[11]_i_4__4_n_0 ),
        .I5(\di_reg[11]_i_5__4_n_0 ),
        .O(di_reg[11]));
  LUT6 #(
    .INIT(64'h0808080808380808)) 
    \di_reg[11]_i_2__4 
       (.I0(do_reg2[11]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[0]),
        .I4(rate_reg2[1]),
        .I5(index[0]),
        .O(\di_reg[11]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'hCC0CCC0C0C0C880C)) 
    \di_reg[11]_i_3__4 
       (.I0(data15),
        .I1(index[3]),
        .I2(do_reg2[11]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[11]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAAAAAABAAABA)) 
    \di_reg[11]_i_4__4 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[11]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAA00AAAAAAA3)) 
    \di_reg[11]_i_5__4 
       (.I0(do_reg2[11]),
        .I1(x16_reg2),
        .I2(\addr_reg[4]_i_2__4_n_0 ),
        .I3(index[0]),
        .I4(index[1]),
        .I5(index[2]),
        .O(\di_reg[11]_i_5__4_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \di_reg[12]_i_1__4 
       (.I0(\di_reg[12]_i_2__4_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[12]_i_3__4_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[12]_i_4__4_n_0 ),
        .O(di_reg[12]));
  LUT5 #(
    .INIT(32'h00003202)) 
    \di_reg[12]_i_2__4 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[12]),
        .I4(index[3]),
        .O(\di_reg[12]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[12]_i_3__4 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[12]),
        .O(\di_reg[12]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAA8AAABAAABA)) 
    \di_reg[12]_i_4__4 
       (.I0(do_reg2[12]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[12]_i_4__4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \di_reg[13]_i_1__4 
       (.I0(\di_reg[13]_i_2__4_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[13]_i_3__4_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[13]_i_4__4_n_0 ),
        .O(di_reg[13]));
  LUT6 #(
    .INIT(64'h0808080838380838)) 
    \di_reg[13]_i_2__4 
       (.I0(do_reg2[13]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[13]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[13]_i_3__4 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[13]),
        .O(\di_reg[13]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hAA8AAA8AAABAAA8A)) 
    \di_reg[13]_i_4__4 
       (.I0(do_reg2[13]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[1]),
        .I5(rate_reg2[0]),
        .O(\di_reg[13]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'h080008FF08000800)) 
    \di_reg[14]_i_1__4 
       (.I0(do_reg2[14]),
        .I1(\di_reg[14]_i_2__4_n_0 ),
        .I2(index[3]),
        .I3(index[4]),
        .I4(\di_reg[14]_i_3__4_n_0 ),
        .I5(\di_reg[14]_i_4__4_n_0 ),
        .O(di_reg[14]));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_2__4 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[14]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h0033303310130033)) 
    \di_reg[14]_i_3__4 
       (.I0(data15),
        .I1(index[3]),
        .I2(index[2]),
        .I3(do_reg2[14]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[14]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000DF10)) 
    \di_reg[14]_i_4__4 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(do_reg2[14]),
        .I4(index[2]),
        .I5(\di_reg[14]_i_6__4_n_0 ),
        .O(\di_reg[14]_i_4__4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_5__4 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .O(data15));
  LUT6 #(
    .INIT(64'hBBBB3BBBBBBB3FBB)) 
    \di_reg[14]_i_6__4 
       (.I0(\di_reg[14]_i_7__4_n_0 ),
        .I1(index[3]),
        .I2(index[0]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(\di_reg[5]_i_4__4_n_0 ),
        .O(\di_reg[14]_i_6__4_n_0 ));
  LUT4 #(
    .INIT(16'h4440)) 
    \di_reg[14]_i_7__4 
       (.I0(index[1]),
        .I1(index[2]),
        .I2(do_reg2[14]),
        .I3(index[0]),
        .O(\di_reg[14]_i_7__4_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[15]_i_1__4 
       (.I0(index[4]),
        .I1(do_reg2[15]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[15]_i_2__4_n_0 ),
        .O(di_reg[15]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[15]_i_2__4 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[15]_i_2__4_n_0 ));
  LUT4 #(
    .INIT(16'hABAA)) 
    \di_reg[1]_i_1__4 
       (.I0(\di_reg[1]_i_2__4_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[1]_i_3__4_n_0 ),
        .I3(\di_reg[1]_i_4__4_n_0 ),
        .O(di_reg[1]));
  LUT6 #(
    .INIT(64'h0000000034140000)) 
    \di_reg[1]_i_2__4 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[1]),
        .I4(index[4]),
        .I5(index[3]),
        .O(\di_reg[1]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FB330000)) 
    \di_reg[1]_i_3__4 
       (.I0(index[2]),
        .I1(do_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[3]),
        .I5(\di_reg[1]_i_5__4_n_0 ),
        .O(\di_reg[1]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFCCC5555)) 
    \di_reg[1]_i_4__4 
       (.I0(\di_reg[1]_i_6__4_n_0 ),
        .I1(do_reg2[1]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\di_reg[1]_i_4__4_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \di_reg[1]_i_5__4 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .I3(index[1]),
        .O(\di_reg[1]_i_5__4_n_0 ));
  LUT6 #(
    .INIT(64'h002F0F20F02FFF2F)) 
    \di_reg[1]_i_6__4 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(mode),
        .I5(do_reg2[1]),
        .O(\di_reg[1]_i_6__4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[2]_i_1__4 
       (.I0(\di_reg[2]_i_2__4_n_0 ),
        .I1(\di_reg[2]_i_3__4_n_0 ),
        .O(di_reg[2]));
  LUT6 #(
    .INIT(64'h00400500FFFFFFFF)) 
    \di_reg[2]_i_2__4 
       (.I0(index[3]),
        .I1(do_reg2[2]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\di_reg[2]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF470047)) 
    \di_reg[2]_i_3__4 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(\di_reg[2]_i_4__4_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[2]_i_5__4_n_0 ),
        .I5(index[4]),
        .O(\di_reg[2]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hF4F40404F00FF000)) 
    \di_reg[2]_i_4__4 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(mode),
        .I4(do_reg2[2]),
        .I5(index[1]),
        .O(\di_reg[2]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'hF5D535D5F5D5F5D5)) 
    \di_reg[2]_i_5__4 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[2]_i_5__4_n_0 ));
  LUT6 #(
    .INIT(64'hBAAA1000AAFF0000)) 
    \di_reg[3]_i_2__4 
       (.I0(\di_reg[3]_i_4__4_n_0 ),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(do_reg2[3]),
        .I5(index[0]),
        .O(\di_reg[3]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000033E200)) 
    \di_reg[3]_i_3__4 
       (.I0(data15),
        .I1(index[0]),
        .I2(do_reg2[3]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\di_reg[3]_i_3__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[3]_i_4__4 
       (.I0(index[3]),
        .I1(index[1]),
        .O(\di_reg[3]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[4]_i_1__4 
       (.I0(index[3]),
        .I1(\di_reg[4]_i_2__4_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[4]_i_3__4_n_0 ),
        .I4(\di_reg[4]_i_4__4_n_0 ),
        .I5(\di_reg[4]_i_5__4_n_0 ),
        .O(di_reg[4]));
  LUT6 #(
    .INIT(64'h08080B0830303030)) 
    \di_reg[4]_i_2__4 
       (.I0(do_reg2[4]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[4]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DFFFFFFF)) 
    \di_reg[4]_i_3__4 
       (.I0(index[0]),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\di_reg[4]_i_6__4_n_0 ),
        .O(\di_reg[4]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FFFFE00000000)) 
    \di_reg[4]_i_4__4 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(do_reg2[4]),
        .O(\di_reg[4]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010C00)) 
    \di_reg[4]_i_5__4 
       (.I0(\di_reg[4]_i_7__4_n_0 ),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(\di_reg[4]_i_8__4_n_0 ),
        .I5(index[3]),
        .O(\di_reg[4]_i_5__4_n_0 ));
  LUT5 #(
    .INIT(32'h1F0FFF0F)) 
    \di_reg[4]_i_6__4 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(do_reg2[4]),
        .I4(index[1]),
        .O(\di_reg[4]_i_6__4_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \di_reg[4]_i_7__4 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .O(\di_reg[4]_i_7__4_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \di_reg[4]_i_8__4 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .O(\di_reg[4]_i_8__4_n_0 ));
  LUT6 #(
    .INIT(64'h33000000B888B888)) 
    \di_reg[5]_i_1__4 
       (.I0(\di_reg[5]_i_2__4_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[5]_i_3__4_n_0 ),
        .I3(do_reg2[5]),
        .I4(\di_reg[5]_i_4__4_n_0 ),
        .I5(index[3]),
        .O(di_reg[5]));
  LUT6 #(
    .INIT(64'h0B0B080B33333033)) 
    \di_reg[5]_i_2__4 
       (.I0(do_reg2[5]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[5]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \di_reg[5]_i_3__4 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(x16x20_mode_reg2),
        .I4(mode),
        .O(\di_reg[5]_i_3__4_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[5]_i_4__4 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[5]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'h67FF000067000000)) 
    \di_reg[6]_i_2__4 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[6]),
        .I5(\di_reg[5]_i_3__4_n_0 ),
        .O(\di_reg[6]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'h00002404)) 
    \di_reg[6]_i_3__4 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[6]),
        .I4(index[3]),
        .O(\di_reg[6]_i_3__4_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF0900)) 
    \di_reg[7]_i_2__4 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[7]),
        .O(\di_reg[7]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000C320032)) 
    \di_reg[7]_i_3__4 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(do_reg2[7]),
        .I5(index[3]),
        .O(\di_reg[7]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[8]_i_1__4 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[8]),
        .O(di_reg[8]));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[9]_i_1__4 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[9]),
        .O(di_reg[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[0]),
        .Q(\di_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[0]_i_1__4 
       (.I0(\di_reg[0]_i_2__4_n_0 ),
        .I1(\di_reg[0]_i_3__4_n_0 ),
        .O(di_reg[0]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[10]),
        .Q(\di_reg_reg_n_0_[10] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[11]),
        .Q(\di_reg_reg_n_0_[11] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[12]),
        .Q(\di_reg_reg_n_0_[12] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[13]),
        .Q(\di_reg_reg_n_0_[13] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[14]),
        .Q(\di_reg_reg_n_0_[14] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[15]),
        .Q(\di_reg_reg_n_0_[15] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[1]),
        .Q(\di_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[2]),
        .Q(\di_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[3]),
        .Q(\di_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[3]_i_1__4 
       (.I0(\di_reg[3]_i_2__4_n_0 ),
        .I1(\di_reg[3]_i_3__4_n_0 ),
        .O(di_reg[3]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[4]),
        .Q(\di_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[5]),
        .Q(\di_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[6]),
        .Q(\di_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[6]_i_1__4 
       (.I0(\di_reg[6]_i_2__4_n_0 ),
        .I1(\di_reg[6]_i_3__4_n_0 ),
        .O(di_reg[6]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[7]),
        .Q(\di_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[7]_i_1__4 
       (.I0(\di_reg[7]_i_2__4_n_0 ),
        .I1(\di_reg[7]_i_3__4_n_0 ),
        .O(di_reg[7]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[8]),
        .Q(\di_reg_reg_n_0_[8] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[9]),
        .Q(\di_reg_reg_n_0_[9] ),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[0]),
        .Q(do_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[10]),
        .Q(do_reg1[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[11]),
        .Q(do_reg1[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[12]),
        .Q(do_reg1[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[13]),
        .Q(do_reg1[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[14]),
        .Q(do_reg1[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[15]),
        .Q(do_reg1[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[1]),
        .Q(do_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[2]),
        .Q(do_reg1[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[3]),
        .Q(do_reg1[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[4]),
        .Q(do_reg1[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[5]),
        .Q(do_reg1[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[6]),
        .Q(do_reg1[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[7]),
        .Q(do_reg1[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[8]),
        .Q(do_reg1[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[9]),
        .Q(do_reg1[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(RST_DCLK_RESET));
  LUT4 #(
    .INIT(16'h0001)) 
    done_i_1__4
       (.I0(start_reg2),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(done_i_1__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(done_i_1__4_n_0),
        .Q(DRP_DONE),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0B3BFFFF0B3B0000)) 
    \fsm[0]_i_1__10 
       (.I0(data4),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(rdy_reg2),
        .I4(Q[2]),
        .I5(\fsm[0]_i_3__10_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT5 #(
    .INIT(32'hEFFEFFFF)) 
    \fsm[0]_i_2__4 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[4]),
        .I3(index[2]),
        .I4(mode_i_2__4_n_0),
        .O(data4));
  LUT6 #(
    .INIT(64'h7477FFFF7477CCCC)) 
    \fsm[0]_i_3__10 
       (.I0(rdy_reg2),
        .I1(Q[1]),
        .I2(load_cnt[1]),
        .I3(load_cnt[0]),
        .I4(Q[0]),
        .I5(start_reg2),
        .O(\fsm[0]_i_3__10_n_0 ));
  LUT6 #(
    .INIT(64'h185018501D501850)) 
    \fsm[1]_i_1__4 
       (.I0(Q[2]),
        .I1(rdy_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(load_cnt[0]),
        .I5(load_cnt[1]),
        .O(fsm[1]));
  LUT4 #(
    .INIT(16'h6222)) 
    \fsm[2]_i_1__10 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(rdy_reg2),
        .I3(Q[0]),
        .O(fsm[2]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \gt_ch_drp_rdy[5]_INST_0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(gt_ch_drp_rdy));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_14__6 
       (.I0(ext_ch_gt_drpdi[15]),
        .I1(\di_reg_reg_n_0_[15] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[15]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_15__4 
       (.I0(ext_ch_gt_drpdi[14]),
        .I1(\di_reg_reg_n_0_[14] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[14]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_16__4 
       (.I0(ext_ch_gt_drpdi[13]),
        .I1(\di_reg_reg_n_0_[13] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[13]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_17__4 
       (.I0(ext_ch_gt_drpdi[12]),
        .I1(\di_reg_reg_n_0_[12] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[12]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_18__4 
       (.I0(ext_ch_gt_drpdi[11]),
        .I1(\di_reg_reg_n_0_[11] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[11]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_19__4 
       (.I0(ext_ch_gt_drpdi[10]),
        .I1(\di_reg_reg_n_0_[10] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[10]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_20__4 
       (.I0(ext_ch_gt_drpdi[9]),
        .I1(\di_reg_reg_n_0_[9] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[9]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_21__4 
       (.I0(ext_ch_gt_drpdi[8]),
        .I1(\di_reg_reg_n_0_[8] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_22__4 
       (.I0(ext_ch_gt_drpdi[7]),
        .I1(\di_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_23__4 
       (.I0(ext_ch_gt_drpdi[6]),
        .I1(\di_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[6]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_24__4 
       (.I0(ext_ch_gt_drpdi[5]),
        .I1(\di_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_25__4 
       (.I0(ext_ch_gt_drpdi[4]),
        .I1(\di_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_26__4 
       (.I0(ext_ch_gt_drpdi[3]),
        .I1(\di_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_27__4 
       (.I0(ext_ch_gt_drpdi[2]),
        .I1(\di_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_28__4 
       (.I0(ext_ch_gt_drpdi[1]),
        .I1(\di_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_29__4 
       (.I0(ext_ch_gt_drpdi[0]),
        .I1(\di_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[0]));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT4 #(
    .INIT(16'h003E)) 
    \gtx_channel.gtxe2_channel_i_i_3__4 
       (.I0(ext_ch_gt_drpen),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\cplllock_reg1_reg[5] ));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_47__6 
       (.I0(ext_ch_gt_drpaddr[8]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(DRPADDR[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_48__2 
       (.I0(ext_ch_gt_drpaddr[7]),
        .I1(\addr_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_49__4 
       (.I0(ext_ch_gt_drpaddr[6]),
        .I1(\addr_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[6]));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT4 #(
    .INIT(16'h0032)) 
    \gtx_channel.gtxe2_channel_i_i_4__4 
       (.I0(ext_ch_gt_drpwe),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(\cplllock_reg1_reg[5]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_50__4 
       (.I0(ext_ch_gt_drpaddr[5]),
        .I1(\addr_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_51__4 
       (.I0(ext_ch_gt_drpaddr[4]),
        .I1(\addr_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_52__4 
       (.I0(ext_ch_gt_drpaddr[3]),
        .I1(\addr_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_53__4 
       (.I0(ext_ch_gt_drpaddr[2]),
        .I1(\addr_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_54__4 
       (.I0(ext_ch_gt_drpaddr[1]),
        .I1(\addr_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_55__4 
       (.I0(ext_ch_gt_drpaddr[0]),
        .I1(\addr_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[0]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rst_gtreset),
        .Q(gtxreset_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(gtxreset_reg1),
        .Q(gtxreset_reg2),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \index[0]_i_1__6 
       (.I0(index[0]),
        .I1(Q[2]),
        .I2(\index[3]_i_2__4_n_0 ),
        .O(\index[0]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT4 #(
    .INIT(16'h0220)) 
    \index[1]_i_1__6 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__4_n_0 ),
        .I2(index[1]),
        .I3(index[0]),
        .O(\index[1]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT5 #(
    .INIT(32'h02222000)) 
    \index[2]_i_1__6 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__4_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .O(\index[2]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h0222222220000000)) 
    \index[3]_i_1__4 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__4_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\index[3]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAE)) 
    \index[3]_i_2__4 
       (.I0(Q[0]),
        .I1(mode_i_2__4_n_0),
        .I2(index[2]),
        .I3(index[4]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\index[3]_i_2__4_n_0 ));
  LUT3 #(
    .INIT(8'h89)) 
    \index[4]_i_1__4 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\index[4]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \index[4]_i_2__4 
       (.I0(index[0]),
        .I1(index[2]),
        .I2(index[3]),
        .I3(index[1]),
        .I4(index[4]),
        .I5(\index[4]_i_3__4_n_0 ),
        .O(\index[4]_i_2__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \index[4]_i_3__4 
       (.I0(\index[3]_i_2__4_n_0 ),
        .I1(Q[2]),
        .O(\index[4]_i_3__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__4_n_0 ),
        .D(\index[0]_i_1__6_n_0 ),
        .Q(index[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__4_n_0 ),
        .D(\index[1]_i_1__6_n_0 ),
        .Q(index[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__4_n_0 ),
        .D(\index[2]_i_1__6_n_0 ),
        .Q(index[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__4_n_0 ),
        .D(\index[3]_i_1__4_n_0 ),
        .Q(index[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__4_n_0 ),
        .D(\index[4]_i_2__4_n_0 ),
        .Q(index[4]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \load_cnt[0]_i_1__6 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(load_cnt[1]),
        .I3(Q[2]),
        .O(\load_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__6_n_0 ),
        .Q(load_cnt[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(load_cnt[1]),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h00AAA2AAAAAAAA00)) 
    mode_i_1__4
       (.I0(mode),
        .I1(mode_i_2__4_n_0),
        .I2(mode_i_3__6_n_0),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(mode_i_1__4_n_0));
  LUT4 #(
    .INIT(16'hCCB8)) 
    mode_i_2__4
       (.I0(mode),
        .I1(index[0]),
        .I2(x16x20_mode_reg2),
        .I3(index[2]),
        .O(mode_i_2__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    mode_i_3__6
       (.I0(index[2]),
        .I1(index[4]),
        .I2(index[1]),
        .I3(index[3]),
        .O(mode_i_3__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mode_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(mode_i_1__4_n_0),
        .Q(mode),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[0]),
        .Q(rate_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[1]),
        .Q(rate_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drprdy),
        .Q(rdy_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_START),
        .Q(start_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16),
        .Q(x16_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16_reg1),
        .Q(x16_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16X20_MODE),
        .Q(x16x20_mode_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16x20_mode_reg1),
        .Q(x16x20_mode_reg2),
        .R(RST_DCLK_RESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_drp" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_61
   (Q,
    DRPADDR,
    \cplllock_reg1_reg[6] ,
    \cplllock_reg1_reg[6]_0 ,
    gt_ch_drp_rdy,
    DRPDI,
    DRP_DONE,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi,
    RST_DCLK_RESET,
    DRP_X16X20_MODE,
    \resetovrd_disble.reset_reg[4] ,
    DRP_START,
    ext_ch_gt_drprdy,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    DRP_X16,
    ext_ch_gt_drpdo,
    rst_gtreset);
  output [2:0]Q;
  output [8:0]DRPADDR;
  output \cplllock_reg1_reg[6] ;
  output \cplllock_reg1_reg[6]_0 ;
  output [0:0]gt_ch_drp_rdy;
  output [15:0]DRPDI;
  output DRP_DONE;
  input [8:0]ext_ch_gt_drpaddr;
  input [0:0]ext_ch_gt_drpen;
  input [0:0]ext_ch_gt_drpwe;
  input [15:0]ext_ch_gt_drpdi;
  input RST_DCLK_RESET;
  input DRP_X16X20_MODE;
  input \resetovrd_disble.reset_reg[4] ;
  input DRP_START;
  input [0:0]ext_ch_gt_drprdy;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input DRP_X16;
  input [15:0]ext_ch_gt_drpdo;
  input rst_gtreset;

  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_DONE;
  wire DRP_START;
  wire DRP_X16;
  wire DRP_X16X20_MODE;
  wire [2:0]Q;
  wire RST_DCLK_RESET;
  wire \addr_reg[0]_i_1__5_n_0 ;
  wire \addr_reg[1]_i_1__5_n_0 ;
  wire \addr_reg[2]_i_1__5_n_0 ;
  wire \addr_reg[3]_i_1__5_n_0 ;
  wire \addr_reg[4]_i_1__5_n_0 ;
  wire \addr_reg[4]_i_2__5_n_0 ;
  wire \addr_reg[5]_i_1__5_n_0 ;
  wire \addr_reg[6]_i_1__5_n_0 ;
  wire \addr_reg[7]_i_1__5_n_0 ;
  wire \addr_reg[7]_i_2__5_n_0 ;
  wire \addr_reg_reg_n_0_[0] ;
  wire \addr_reg_reg_n_0_[1] ;
  wire \addr_reg_reg_n_0_[2] ;
  wire \addr_reg_reg_n_0_[3] ;
  wire \addr_reg_reg_n_0_[4] ;
  wire \addr_reg_reg_n_0_[5] ;
  wire \addr_reg_reg_n_0_[6] ;
  wire \addr_reg_reg_n_0_[7] ;
  wire \cplllock_reg1_reg[6] ;
  wire \cplllock_reg1_reg[6]_0 ;
  wire [7:7]data15;
  wire data4;
  wire [15:0]di_reg;
  wire \di_reg[0]_i_2__5_n_0 ;
  wire \di_reg[0]_i_3__5_n_0 ;
  wire \di_reg[0]_i_4__5_n_0 ;
  wire \di_reg[0]_i_5__5_n_0 ;
  wire \di_reg[0]_i_6__5_n_0 ;
  wire \di_reg[10]_i_2__5_n_0 ;
  wire \di_reg[11]_i_2__5_n_0 ;
  wire \di_reg[11]_i_3__5_n_0 ;
  wire \di_reg[11]_i_4__5_n_0 ;
  wire \di_reg[11]_i_5__5_n_0 ;
  wire \di_reg[12]_i_2__5_n_0 ;
  wire \di_reg[12]_i_3__5_n_0 ;
  wire \di_reg[12]_i_4__5_n_0 ;
  wire \di_reg[13]_i_2__5_n_0 ;
  wire \di_reg[13]_i_3__5_n_0 ;
  wire \di_reg[13]_i_4__5_n_0 ;
  wire \di_reg[14]_i_2__5_n_0 ;
  wire \di_reg[14]_i_3__5_n_0 ;
  wire \di_reg[14]_i_4__5_n_0 ;
  wire \di_reg[14]_i_6__5_n_0 ;
  wire \di_reg[14]_i_7__5_n_0 ;
  wire \di_reg[15]_i_2__5_n_0 ;
  wire \di_reg[1]_i_2__5_n_0 ;
  wire \di_reg[1]_i_3__5_n_0 ;
  wire \di_reg[1]_i_4__5_n_0 ;
  wire \di_reg[1]_i_5__5_n_0 ;
  wire \di_reg[1]_i_6__5_n_0 ;
  wire \di_reg[2]_i_2__5_n_0 ;
  wire \di_reg[2]_i_3__5_n_0 ;
  wire \di_reg[2]_i_4__5_n_0 ;
  wire \di_reg[2]_i_5__5_n_0 ;
  wire \di_reg[3]_i_2__5_n_0 ;
  wire \di_reg[3]_i_3__5_n_0 ;
  wire \di_reg[3]_i_4__5_n_0 ;
  wire \di_reg[4]_i_2__5_n_0 ;
  wire \di_reg[4]_i_3__5_n_0 ;
  wire \di_reg[4]_i_4__5_n_0 ;
  wire \di_reg[4]_i_5__5_n_0 ;
  wire \di_reg[4]_i_6__5_n_0 ;
  wire \di_reg[4]_i_7__5_n_0 ;
  wire \di_reg[4]_i_8__5_n_0 ;
  wire \di_reg[5]_i_2__5_n_0 ;
  wire \di_reg[5]_i_3__5_n_0 ;
  wire \di_reg[5]_i_4__5_n_0 ;
  wire \di_reg[6]_i_2__5_n_0 ;
  wire \di_reg[6]_i_3__5_n_0 ;
  wire \di_reg[7]_i_2__5_n_0 ;
  wire \di_reg[7]_i_3__5_n_0 ;
  wire \di_reg_reg_n_0_[0] ;
  wire \di_reg_reg_n_0_[10] ;
  wire \di_reg_reg_n_0_[11] ;
  wire \di_reg_reg_n_0_[12] ;
  wire \di_reg_reg_n_0_[13] ;
  wire \di_reg_reg_n_0_[14] ;
  wire \di_reg_reg_n_0_[15] ;
  wire \di_reg_reg_n_0_[1] ;
  wire \di_reg_reg_n_0_[2] ;
  wire \di_reg_reg_n_0_[3] ;
  wire \di_reg_reg_n_0_[4] ;
  wire \di_reg_reg_n_0_[5] ;
  wire \di_reg_reg_n_0_[6] ;
  wire \di_reg_reg_n_0_[7] ;
  wire \di_reg_reg_n_0_[8] ;
  wire \di_reg_reg_n_0_[9] ;
  wire [15:0]do_reg1;
  wire [15:0]do_reg2;
  wire done_i_1__5_n_0;
  wire [8:0]ext_ch_gt_drpaddr;
  wire [15:0]ext_ch_gt_drpdi;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drpen;
  wire [0:0]ext_ch_gt_drprdy;
  wire [0:0]ext_ch_gt_drpwe;
  wire [2:0]fsm;
  wire \fsm[0]_i_3__12_n_0 ;
  wire [0:0]gt_ch_drp_rdy;
  wire gtxreset_reg1;
  wire gtxreset_reg2;
  wire [4:0]index;
  wire \index[0]_i_1__7_n_0 ;
  wire \index[1]_i_1__7_n_0 ;
  wire \index[2]_i_1__7_n_0 ;
  wire \index[3]_i_1__5_n_0 ;
  wire \index[3]_i_2__5_n_0 ;
  wire \index[4]_i_1__5_n_0 ;
  wire \index[4]_i_2__5_n_0 ;
  wire \index[4]_i_3__5_n_0 ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1__7_n_0 ;
  wire mode;
  wire mode_i_1__5_n_0;
  wire mode_i_2__5_n_0;
  wire mode_i_3__7_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire [1:0]rate_reg1;
  wire [1:0]rate_reg2;
  wire rdy_reg1;
  wire rdy_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_gtreset;
  wire start_reg1;
  wire start_reg2;
  wire x16_reg1;
  wire x16_reg2;
  wire x16x20_mode_reg1;
  wire x16x20_mode_reg2;

  LUT6 #(
    .INIT(64'h1471357514713564)) 
    \addr_reg[0]_i_1__5 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__5_n_0 ),
        .O(\addr_reg[0]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h404050500F0F0500)) 
    \addr_reg[1]_i_1__5 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[1]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h051005105A055A00)) 
    \addr_reg[2]_i_1__5 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(index[2]),
        .I4(mode),
        .I5(index[1]),
        .O(\addr_reg[2]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h5767576753275326)) 
    \addr_reg[3]_i_1__5 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(\addr_reg[4]_i_2__5_n_0 ),
        .I5(index[0]),
        .O(\addr_reg[3]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FCCFFF01)) 
    \addr_reg[4]_i_1__5 
       (.I0(\addr_reg[4]_i_2__5_n_0 ),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[3]),
        .I5(index[4]),
        .O(\addr_reg[4]_i_1__5_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \addr_reg[4]_i_2__5 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .O(\addr_reg[4]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h00001A1A0F0F0F0A)) 
    \addr_reg[5]_i_1__5 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[5]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000011545554)) 
    \addr_reg[6]_i_1__5 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(mode),
        .I3(index[3]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\addr_reg[6]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h5422262254222633)) 
    \addr_reg[7]_i_1__5 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__5_n_0 ),
        .O(\addr_reg[7]_i_1__5_n_0 ));
  LUT3 #(
    .INIT(8'hCE)) 
    \addr_reg[7]_i_2__5 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .I2(index[0]),
        .O(\addr_reg[7]_i_2__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[0]_i_1__5_n_0 ),
        .Q(\addr_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[1]_i_1__5_n_0 ),
        .Q(\addr_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[2]_i_1__5_n_0 ),
        .Q(\addr_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[3]_i_1__5_n_0 ),
        .Q(\addr_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[4]_i_1__5_n_0 ),
        .Q(\addr_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[5]_i_1__5_n_0 ),
        .Q(\addr_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[6]_i_1__5_n_0 ),
        .Q(\addr_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[7]_i_1__5_n_0 ),
        .Q(\addr_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'hB8B8B8BBB8B8B888)) 
    \di_reg[0]_i_2__5 
       (.I0(\di_reg[0]_i_4__5_n_0 ),
        .I1(index[3]),
        .I2(do_reg2[0]),
        .I3(\di_reg[0]_i_5__5_n_0 ),
        .I4(\di_reg[0]_i_6__5_n_0 ),
        .I5(\di_reg[4]_i_8__5_n_0 ),
        .O(\di_reg[0]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h00003414)) 
    \di_reg[0]_i_3__5 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[0]),
        .I4(index[3]),
        .O(\di_reg[0]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hB0BFFFFFB0B00000)) 
    \di_reg[0]_i_4__5 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(do_reg2[0]),
        .O(\di_reg[0]_i_4__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \di_reg[0]_i_5__5 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .O(\di_reg[0]_i_5__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \di_reg[0]_i_6__5 
       (.I0(index[1]),
        .I1(mode),
        .I2(index[0]),
        .O(\di_reg[0]_i_6__5_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[10]_i_1__5 
       (.I0(index[4]),
        .I1(do_reg2[10]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[10]_i_2__5_n_0 ),
        .O(di_reg[10]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[10]_i_2__5 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[10]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[11]_i_1__5 
       (.I0(index[3]),
        .I1(\di_reg[11]_i_2__5_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[11]_i_3__5_n_0 ),
        .I4(\di_reg[11]_i_4__5_n_0 ),
        .I5(\di_reg[11]_i_5__5_n_0 ),
        .O(di_reg[11]));
  LUT6 #(
    .INIT(64'h0808080808380808)) 
    \di_reg[11]_i_2__5 
       (.I0(do_reg2[11]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[0]),
        .I4(rate_reg2[1]),
        .I5(index[0]),
        .O(\di_reg[11]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'hCC0CCC0C0C0C880C)) 
    \di_reg[11]_i_3__5 
       (.I0(data15),
        .I1(index[3]),
        .I2(do_reg2[11]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[11]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAAAAAABAAABA)) 
    \di_reg[11]_i_4__5 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[11]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAA00AAAAAAA3)) 
    \di_reg[11]_i_5__5 
       (.I0(do_reg2[11]),
        .I1(x16_reg2),
        .I2(\addr_reg[4]_i_2__5_n_0 ),
        .I3(index[0]),
        .I4(index[1]),
        .I5(index[2]),
        .O(\di_reg[11]_i_5__5_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \di_reg[12]_i_1__5 
       (.I0(\di_reg[12]_i_2__5_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[12]_i_3__5_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[12]_i_4__5_n_0 ),
        .O(di_reg[12]));
  LUT5 #(
    .INIT(32'h00003202)) 
    \di_reg[12]_i_2__5 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[12]),
        .I4(index[3]),
        .O(\di_reg[12]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[12]_i_3__5 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[12]),
        .O(\di_reg[12]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAA8AAABAAABA)) 
    \di_reg[12]_i_4__5 
       (.I0(do_reg2[12]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[12]_i_4__5_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \di_reg[13]_i_1__5 
       (.I0(\di_reg[13]_i_2__5_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[13]_i_3__5_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[13]_i_4__5_n_0 ),
        .O(di_reg[13]));
  LUT6 #(
    .INIT(64'h0808080838380838)) 
    \di_reg[13]_i_2__5 
       (.I0(do_reg2[13]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[13]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[13]_i_3__5 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[13]),
        .O(\di_reg[13]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hAA8AAA8AAABAAA8A)) 
    \di_reg[13]_i_4__5 
       (.I0(do_reg2[13]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[1]),
        .I5(rate_reg2[0]),
        .O(\di_reg[13]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'h080008FF08000800)) 
    \di_reg[14]_i_1__5 
       (.I0(do_reg2[14]),
        .I1(\di_reg[14]_i_2__5_n_0 ),
        .I2(index[3]),
        .I3(index[4]),
        .I4(\di_reg[14]_i_3__5_n_0 ),
        .I5(\di_reg[14]_i_4__5_n_0 ),
        .O(di_reg[14]));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_2__5 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[14]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h0033303310130033)) 
    \di_reg[14]_i_3__5 
       (.I0(data15),
        .I1(index[3]),
        .I2(index[2]),
        .I3(do_reg2[14]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[14]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000DF10)) 
    \di_reg[14]_i_4__5 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(do_reg2[14]),
        .I4(index[2]),
        .I5(\di_reg[14]_i_6__5_n_0 ),
        .O(\di_reg[14]_i_4__5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_5__5 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .O(data15));
  LUT6 #(
    .INIT(64'hBBBB3BBBBBBB3FBB)) 
    \di_reg[14]_i_6__5 
       (.I0(\di_reg[14]_i_7__5_n_0 ),
        .I1(index[3]),
        .I2(index[0]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(\di_reg[5]_i_4__5_n_0 ),
        .O(\di_reg[14]_i_6__5_n_0 ));
  LUT4 #(
    .INIT(16'h4440)) 
    \di_reg[14]_i_7__5 
       (.I0(index[1]),
        .I1(index[2]),
        .I2(do_reg2[14]),
        .I3(index[0]),
        .O(\di_reg[14]_i_7__5_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[15]_i_1__5 
       (.I0(index[4]),
        .I1(do_reg2[15]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[15]_i_2__5_n_0 ),
        .O(di_reg[15]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[15]_i_2__5 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[15]_i_2__5_n_0 ));
  LUT4 #(
    .INIT(16'hABAA)) 
    \di_reg[1]_i_1__5 
       (.I0(\di_reg[1]_i_2__5_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[1]_i_3__5_n_0 ),
        .I3(\di_reg[1]_i_4__5_n_0 ),
        .O(di_reg[1]));
  LUT6 #(
    .INIT(64'h0000000034140000)) 
    \di_reg[1]_i_2__5 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[1]),
        .I4(index[4]),
        .I5(index[3]),
        .O(\di_reg[1]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FB330000)) 
    \di_reg[1]_i_3__5 
       (.I0(index[2]),
        .I1(do_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[3]),
        .I5(\di_reg[1]_i_5__5_n_0 ),
        .O(\di_reg[1]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFCCC5555)) 
    \di_reg[1]_i_4__5 
       (.I0(\di_reg[1]_i_6__5_n_0 ),
        .I1(do_reg2[1]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\di_reg[1]_i_4__5_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \di_reg[1]_i_5__5 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .I3(index[1]),
        .O(\di_reg[1]_i_5__5_n_0 ));
  LUT6 #(
    .INIT(64'h002F0F20F02FFF2F)) 
    \di_reg[1]_i_6__5 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(mode),
        .I5(do_reg2[1]),
        .O(\di_reg[1]_i_6__5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[2]_i_1__5 
       (.I0(\di_reg[2]_i_2__5_n_0 ),
        .I1(\di_reg[2]_i_3__5_n_0 ),
        .O(di_reg[2]));
  LUT6 #(
    .INIT(64'h00400500FFFFFFFF)) 
    \di_reg[2]_i_2__5 
       (.I0(index[3]),
        .I1(do_reg2[2]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\di_reg[2]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF470047)) 
    \di_reg[2]_i_3__5 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(\di_reg[2]_i_4__5_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[2]_i_5__5_n_0 ),
        .I5(index[4]),
        .O(\di_reg[2]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hF4F40404F00FF000)) 
    \di_reg[2]_i_4__5 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(mode),
        .I4(do_reg2[2]),
        .I5(index[1]),
        .O(\di_reg[2]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'hF5D535D5F5D5F5D5)) 
    \di_reg[2]_i_5__5 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[2]_i_5__5_n_0 ));
  LUT6 #(
    .INIT(64'hBAAA1000AAFF0000)) 
    \di_reg[3]_i_2__5 
       (.I0(\di_reg[3]_i_4__5_n_0 ),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(do_reg2[3]),
        .I5(index[0]),
        .O(\di_reg[3]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h000000000033E200)) 
    \di_reg[3]_i_3__5 
       (.I0(data15),
        .I1(index[0]),
        .I2(do_reg2[3]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\di_reg[3]_i_3__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[3]_i_4__5 
       (.I0(index[3]),
        .I1(index[1]),
        .O(\di_reg[3]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[4]_i_1__5 
       (.I0(index[3]),
        .I1(\di_reg[4]_i_2__5_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[4]_i_3__5_n_0 ),
        .I4(\di_reg[4]_i_4__5_n_0 ),
        .I5(\di_reg[4]_i_5__5_n_0 ),
        .O(di_reg[4]));
  LUT6 #(
    .INIT(64'h08080B0830303030)) 
    \di_reg[4]_i_2__5 
       (.I0(do_reg2[4]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[4]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DFFFFFFF)) 
    \di_reg[4]_i_3__5 
       (.I0(index[0]),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\di_reg[4]_i_6__5_n_0 ),
        .O(\di_reg[4]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FFFFE00000000)) 
    \di_reg[4]_i_4__5 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(do_reg2[4]),
        .O(\di_reg[4]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010C00)) 
    \di_reg[4]_i_5__5 
       (.I0(\di_reg[4]_i_7__5_n_0 ),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(\di_reg[4]_i_8__5_n_0 ),
        .I5(index[3]),
        .O(\di_reg[4]_i_5__5_n_0 ));
  LUT5 #(
    .INIT(32'h1F0FFF0F)) 
    \di_reg[4]_i_6__5 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(do_reg2[4]),
        .I4(index[1]),
        .O(\di_reg[4]_i_6__5_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \di_reg[4]_i_7__5 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .O(\di_reg[4]_i_7__5_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \di_reg[4]_i_8__5 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .O(\di_reg[4]_i_8__5_n_0 ));
  LUT6 #(
    .INIT(64'h33000000B888B888)) 
    \di_reg[5]_i_1__5 
       (.I0(\di_reg[5]_i_2__5_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[5]_i_3__5_n_0 ),
        .I3(do_reg2[5]),
        .I4(\di_reg[5]_i_4__5_n_0 ),
        .I5(index[3]),
        .O(di_reg[5]));
  LUT6 #(
    .INIT(64'h0B0B080B33333033)) 
    \di_reg[5]_i_2__5 
       (.I0(do_reg2[5]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[5]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \di_reg[5]_i_3__5 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(x16x20_mode_reg2),
        .I4(mode),
        .O(\di_reg[5]_i_3__5_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[5]_i_4__5 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[5]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'h67FF000067000000)) 
    \di_reg[6]_i_2__5 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[6]),
        .I5(\di_reg[5]_i_3__5_n_0 ),
        .O(\di_reg[6]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h00002404)) 
    \di_reg[6]_i_3__5 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[6]),
        .I4(index[3]),
        .O(\di_reg[6]_i_3__5_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF0900)) 
    \di_reg[7]_i_2__5 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[7]),
        .O(\di_reg[7]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h000000000C320032)) 
    \di_reg[7]_i_3__5 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(do_reg2[7]),
        .I5(index[3]),
        .O(\di_reg[7]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[8]_i_1__5 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[8]),
        .O(di_reg[8]));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[9]_i_1__5 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[9]),
        .O(di_reg[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[0]),
        .Q(\di_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[0]_i_1__5 
       (.I0(\di_reg[0]_i_2__5_n_0 ),
        .I1(\di_reg[0]_i_3__5_n_0 ),
        .O(di_reg[0]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[10]),
        .Q(\di_reg_reg_n_0_[10] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[11]),
        .Q(\di_reg_reg_n_0_[11] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[12]),
        .Q(\di_reg_reg_n_0_[12] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[13]),
        .Q(\di_reg_reg_n_0_[13] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[14]),
        .Q(\di_reg_reg_n_0_[14] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[15]),
        .Q(\di_reg_reg_n_0_[15] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[1]),
        .Q(\di_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[2]),
        .Q(\di_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[3]),
        .Q(\di_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[3]_i_1__5 
       (.I0(\di_reg[3]_i_2__5_n_0 ),
        .I1(\di_reg[3]_i_3__5_n_0 ),
        .O(di_reg[3]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[4]),
        .Q(\di_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[5]),
        .Q(\di_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[6]),
        .Q(\di_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[6]_i_1__5 
       (.I0(\di_reg[6]_i_2__5_n_0 ),
        .I1(\di_reg[6]_i_3__5_n_0 ),
        .O(di_reg[6]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[7]),
        .Q(\di_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[7]_i_1__5 
       (.I0(\di_reg[7]_i_2__5_n_0 ),
        .I1(\di_reg[7]_i_3__5_n_0 ),
        .O(di_reg[7]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[8]),
        .Q(\di_reg_reg_n_0_[8] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[9]),
        .Q(\di_reg_reg_n_0_[9] ),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[0]),
        .Q(do_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[10]),
        .Q(do_reg1[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[11]),
        .Q(do_reg1[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[12]),
        .Q(do_reg1[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[13]),
        .Q(do_reg1[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[14]),
        .Q(do_reg1[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[15]),
        .Q(do_reg1[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[1]),
        .Q(do_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[2]),
        .Q(do_reg1[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[3]),
        .Q(do_reg1[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[4]),
        .Q(do_reg1[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[5]),
        .Q(do_reg1[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[6]),
        .Q(do_reg1[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[7]),
        .Q(do_reg1[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[8]),
        .Q(do_reg1[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[9]),
        .Q(do_reg1[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(RST_DCLK_RESET));
  LUT4 #(
    .INIT(16'h0001)) 
    done_i_1__5
       (.I0(start_reg2),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(done_i_1__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(done_i_1__5_n_0),
        .Q(DRP_DONE),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0B3BFFFF0B3B0000)) 
    \fsm[0]_i_1__12 
       (.I0(data4),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(rdy_reg2),
        .I4(Q[2]),
        .I5(\fsm[0]_i_3__12_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT5 #(
    .INIT(32'hEFFEFFFF)) 
    \fsm[0]_i_2__5 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[4]),
        .I3(index[2]),
        .I4(mode_i_2__5_n_0),
        .O(data4));
  LUT6 #(
    .INIT(64'h7477FFFF7477CCCC)) 
    \fsm[0]_i_3__12 
       (.I0(rdy_reg2),
        .I1(Q[1]),
        .I2(load_cnt[1]),
        .I3(load_cnt[0]),
        .I4(Q[0]),
        .I5(start_reg2),
        .O(\fsm[0]_i_3__12_n_0 ));
  LUT6 #(
    .INIT(64'h185018501D501850)) 
    \fsm[1]_i_1__5 
       (.I0(Q[2]),
        .I1(rdy_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(load_cnt[0]),
        .I5(load_cnt[1]),
        .O(fsm[1]));
  LUT4 #(
    .INIT(16'h6222)) 
    \fsm[2]_i_1__12 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(rdy_reg2),
        .I3(Q[0]),
        .O(fsm[2]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \gt_ch_drp_rdy[6]_INST_0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(gt_ch_drp_rdy));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_15__5 
       (.I0(ext_ch_gt_drpdi[15]),
        .I1(\di_reg_reg_n_0_[15] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[15]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_16__5 
       (.I0(ext_ch_gt_drpdi[14]),
        .I1(\di_reg_reg_n_0_[14] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[14]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_17__5 
       (.I0(ext_ch_gt_drpdi[13]),
        .I1(\di_reg_reg_n_0_[13] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[13]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_18__5 
       (.I0(ext_ch_gt_drpdi[12]),
        .I1(\di_reg_reg_n_0_[12] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[12]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_19__5 
       (.I0(ext_ch_gt_drpdi[11]),
        .I1(\di_reg_reg_n_0_[11] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[11]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_20__5 
       (.I0(ext_ch_gt_drpdi[10]),
        .I1(\di_reg_reg_n_0_[10] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[10]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_21__5 
       (.I0(ext_ch_gt_drpdi[9]),
        .I1(\di_reg_reg_n_0_[9] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[9]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_22__5 
       (.I0(ext_ch_gt_drpdi[8]),
        .I1(\di_reg_reg_n_0_[8] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_23__5 
       (.I0(ext_ch_gt_drpdi[7]),
        .I1(\di_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_24__5 
       (.I0(ext_ch_gt_drpdi[6]),
        .I1(\di_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[6]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_25__5 
       (.I0(ext_ch_gt_drpdi[5]),
        .I1(\di_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_26__5 
       (.I0(ext_ch_gt_drpdi[4]),
        .I1(\di_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_27__5 
       (.I0(ext_ch_gt_drpdi[3]),
        .I1(\di_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_28__5 
       (.I0(ext_ch_gt_drpdi[2]),
        .I1(\di_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_29__5 
       (.I0(ext_ch_gt_drpdi[1]),
        .I1(\di_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_30__5 
       (.I0(ext_ch_gt_drpdi[0]),
        .I1(\di_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[0]));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT4 #(
    .INIT(16'h003E)) 
    \gtx_channel.gtxe2_channel_i_i_3__5 
       (.I0(ext_ch_gt_drpen),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\cplllock_reg1_reg[6] ));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_48__5 
       (.I0(ext_ch_gt_drpaddr[8]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(DRPADDR[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_49__5 
       (.I0(ext_ch_gt_drpaddr[7]),
        .I1(\addr_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[7]));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT4 #(
    .INIT(16'h0032)) 
    \gtx_channel.gtxe2_channel_i_i_4__5 
       (.I0(ext_ch_gt_drpwe),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(\cplllock_reg1_reg[6]_0 ));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_50__5 
       (.I0(ext_ch_gt_drpaddr[6]),
        .I1(\addr_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[6]));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_51__5 
       (.I0(ext_ch_gt_drpaddr[5]),
        .I1(\addr_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_52__5 
       (.I0(ext_ch_gt_drpaddr[4]),
        .I1(\addr_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_53__5 
       (.I0(ext_ch_gt_drpaddr[3]),
        .I1(\addr_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_54__5 
       (.I0(ext_ch_gt_drpaddr[2]),
        .I1(\addr_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_55__5 
       (.I0(ext_ch_gt_drpaddr[1]),
        .I1(\addr_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_56__5 
       (.I0(ext_ch_gt_drpaddr[0]),
        .I1(\addr_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[0]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rst_gtreset),
        .Q(gtxreset_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(gtxreset_reg1),
        .Q(gtxreset_reg2),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \index[0]_i_1__7 
       (.I0(index[0]),
        .I1(Q[2]),
        .I2(\index[3]_i_2__5_n_0 ),
        .O(\index[0]_i_1__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT4 #(
    .INIT(16'h0220)) 
    \index[1]_i_1__7 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__5_n_0 ),
        .I2(index[1]),
        .I3(index[0]),
        .O(\index[1]_i_1__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT5 #(
    .INIT(32'h02222000)) 
    \index[2]_i_1__7 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__5_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .O(\index[2]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'h0222222220000000)) 
    \index[3]_i_1__5 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__5_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\index[3]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAE)) 
    \index[3]_i_2__5 
       (.I0(Q[0]),
        .I1(mode_i_2__5_n_0),
        .I2(index[2]),
        .I3(index[4]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\index[3]_i_2__5_n_0 ));
  LUT3 #(
    .INIT(8'h89)) 
    \index[4]_i_1__5 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\index[4]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \index[4]_i_2__5 
       (.I0(index[0]),
        .I1(index[2]),
        .I2(index[3]),
        .I3(index[1]),
        .I4(index[4]),
        .I5(\index[4]_i_3__5_n_0 ),
        .O(\index[4]_i_2__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \index[4]_i_3__5 
       (.I0(\index[3]_i_2__5_n_0 ),
        .I1(Q[2]),
        .O(\index[4]_i_3__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__5_n_0 ),
        .D(\index[0]_i_1__7_n_0 ),
        .Q(index[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__5_n_0 ),
        .D(\index[1]_i_1__7_n_0 ),
        .Q(index[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__5_n_0 ),
        .D(\index[2]_i_1__7_n_0 ),
        .Q(index[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__5_n_0 ),
        .D(\index[3]_i_1__5_n_0 ),
        .Q(index[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__5_n_0 ),
        .D(\index[4]_i_2__5_n_0 ),
        .Q(index[4]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \load_cnt[0]_i_1__7 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(load_cnt[1]),
        .I3(Q[2]),
        .O(\load_cnt[0]_i_1__7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__7_n_0 ),
        .Q(load_cnt[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(load_cnt[1]),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h00AAA2AAAAAAAA00)) 
    mode_i_1__5
       (.I0(mode),
        .I1(mode_i_2__5_n_0),
        .I2(mode_i_3__7_n_0),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(mode_i_1__5_n_0));
  LUT4 #(
    .INIT(16'hCCB8)) 
    mode_i_2__5
       (.I0(mode),
        .I1(index[0]),
        .I2(x16x20_mode_reg2),
        .I3(index[2]),
        .O(mode_i_2__5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    mode_i_3__7
       (.I0(index[2]),
        .I1(index[4]),
        .I2(index[1]),
        .I3(index[3]),
        .O(mode_i_3__7_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mode_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(mode_i_1__5_n_0),
        .Q(mode),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[0]),
        .Q(rate_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[1]),
        .Q(rate_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drprdy),
        .Q(rdy_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_START),
        .Q(start_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16),
        .Q(x16_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16_reg1),
        .Q(x16_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16X20_MODE),
        .Q(x16x20_mode_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16x20_mode_reg1),
        .Q(x16x20_mode_reg2),
        .R(RST_DCLK_RESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_drp" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_67
   (Q,
    DRPADDR,
    \cplllock_reg1_reg[7] ,
    \cplllock_reg1_reg[7]_0 ,
    gt_ch_drp_rdy,
    DRPDI,
    DRP_DONE,
    ext_ch_gt_drpaddr,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi,
    RST_DCLK_RESET,
    DRP_X16X20_MODE,
    \resetovrd_disble.reset_reg[4] ,
    DRP_START,
    ext_ch_gt_drprdy,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    DRP_X16,
    ext_ch_gt_drpdo,
    rst_gtreset);
  output [2:0]Q;
  output [8:0]DRPADDR;
  output \cplllock_reg1_reg[7] ;
  output \cplllock_reg1_reg[7]_0 ;
  output [0:0]gt_ch_drp_rdy;
  output [15:0]DRPDI;
  output DRP_DONE;
  input [8:0]ext_ch_gt_drpaddr;
  input [0:0]ext_ch_gt_drpen;
  input [0:0]ext_ch_gt_drpwe;
  input [15:0]ext_ch_gt_drpdi;
  input RST_DCLK_RESET;
  input DRP_X16X20_MODE;
  input \resetovrd_disble.reset_reg[4] ;
  input DRP_START;
  input [0:0]ext_ch_gt_drprdy;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input DRP_X16;
  input [15:0]ext_ch_gt_drpdo;
  input rst_gtreset;

  wire [8:0]DRPADDR;
  wire [15:0]DRPDI;
  wire DRP_DONE;
  wire DRP_START;
  wire DRP_X16;
  wire DRP_X16X20_MODE;
  wire [2:0]Q;
  wire RST_DCLK_RESET;
  wire \addr_reg[0]_i_1__6_n_0 ;
  wire \addr_reg[1]_i_1__6_n_0 ;
  wire \addr_reg[2]_i_1__6_n_0 ;
  wire \addr_reg[3]_i_1__6_n_0 ;
  wire \addr_reg[4]_i_1__6_n_0 ;
  wire \addr_reg[4]_i_2__6_n_0 ;
  wire \addr_reg[5]_i_1__6_n_0 ;
  wire \addr_reg[6]_i_1__6_n_0 ;
  wire \addr_reg[7]_i_1__6_n_0 ;
  wire \addr_reg[7]_i_2__6_n_0 ;
  wire \addr_reg_reg_n_0_[0] ;
  wire \addr_reg_reg_n_0_[1] ;
  wire \addr_reg_reg_n_0_[2] ;
  wire \addr_reg_reg_n_0_[3] ;
  wire \addr_reg_reg_n_0_[4] ;
  wire \addr_reg_reg_n_0_[5] ;
  wire \addr_reg_reg_n_0_[6] ;
  wire \addr_reg_reg_n_0_[7] ;
  wire \cplllock_reg1_reg[7] ;
  wire \cplllock_reg1_reg[7]_0 ;
  wire [7:7]data15;
  wire data4;
  wire [15:0]di_reg;
  wire \di_reg[0]_i_2__6_n_0 ;
  wire \di_reg[0]_i_3__6_n_0 ;
  wire \di_reg[0]_i_4__6_n_0 ;
  wire \di_reg[0]_i_5__6_n_0 ;
  wire \di_reg[0]_i_6__6_n_0 ;
  wire \di_reg[10]_i_2__6_n_0 ;
  wire \di_reg[11]_i_2__6_n_0 ;
  wire \di_reg[11]_i_3__6_n_0 ;
  wire \di_reg[11]_i_4__6_n_0 ;
  wire \di_reg[11]_i_5__6_n_0 ;
  wire \di_reg[12]_i_2__6_n_0 ;
  wire \di_reg[12]_i_3__6_n_0 ;
  wire \di_reg[12]_i_4__6_n_0 ;
  wire \di_reg[13]_i_2__6_n_0 ;
  wire \di_reg[13]_i_3__6_n_0 ;
  wire \di_reg[13]_i_4__6_n_0 ;
  wire \di_reg[14]_i_2__6_n_0 ;
  wire \di_reg[14]_i_3__6_n_0 ;
  wire \di_reg[14]_i_4__6_n_0 ;
  wire \di_reg[14]_i_6__6_n_0 ;
  wire \di_reg[14]_i_7__6_n_0 ;
  wire \di_reg[15]_i_2__6_n_0 ;
  wire \di_reg[1]_i_2__6_n_0 ;
  wire \di_reg[1]_i_3__6_n_0 ;
  wire \di_reg[1]_i_4__6_n_0 ;
  wire \di_reg[1]_i_5__6_n_0 ;
  wire \di_reg[1]_i_6__6_n_0 ;
  wire \di_reg[2]_i_2__6_n_0 ;
  wire \di_reg[2]_i_3__6_n_0 ;
  wire \di_reg[2]_i_4__6_n_0 ;
  wire \di_reg[2]_i_5__6_n_0 ;
  wire \di_reg[3]_i_2__6_n_0 ;
  wire \di_reg[3]_i_3__6_n_0 ;
  wire \di_reg[3]_i_4__6_n_0 ;
  wire \di_reg[4]_i_2__6_n_0 ;
  wire \di_reg[4]_i_3__6_n_0 ;
  wire \di_reg[4]_i_4__6_n_0 ;
  wire \di_reg[4]_i_5__6_n_0 ;
  wire \di_reg[4]_i_6__6_n_0 ;
  wire \di_reg[4]_i_7__6_n_0 ;
  wire \di_reg[4]_i_8__6_n_0 ;
  wire \di_reg[5]_i_2__6_n_0 ;
  wire \di_reg[5]_i_3__6_n_0 ;
  wire \di_reg[5]_i_4__6_n_0 ;
  wire \di_reg[6]_i_2__6_n_0 ;
  wire \di_reg[6]_i_3__6_n_0 ;
  wire \di_reg[7]_i_2__6_n_0 ;
  wire \di_reg[7]_i_3__6_n_0 ;
  wire \di_reg_reg_n_0_[0] ;
  wire \di_reg_reg_n_0_[10] ;
  wire \di_reg_reg_n_0_[11] ;
  wire \di_reg_reg_n_0_[12] ;
  wire \di_reg_reg_n_0_[13] ;
  wire \di_reg_reg_n_0_[14] ;
  wire \di_reg_reg_n_0_[15] ;
  wire \di_reg_reg_n_0_[1] ;
  wire \di_reg_reg_n_0_[2] ;
  wire \di_reg_reg_n_0_[3] ;
  wire \di_reg_reg_n_0_[4] ;
  wire \di_reg_reg_n_0_[5] ;
  wire \di_reg_reg_n_0_[6] ;
  wire \di_reg_reg_n_0_[7] ;
  wire \di_reg_reg_n_0_[8] ;
  wire \di_reg_reg_n_0_[9] ;
  wire [15:0]do_reg1;
  wire [15:0]do_reg2;
  wire done_i_1__6_n_0;
  wire [8:0]ext_ch_gt_drpaddr;
  wire [15:0]ext_ch_gt_drpdi;
  wire [15:0]ext_ch_gt_drpdo;
  wire [0:0]ext_ch_gt_drpen;
  wire [0:0]ext_ch_gt_drprdy;
  wire [0:0]ext_ch_gt_drpwe;
  wire [2:0]fsm;
  wire \fsm[0]_i_3__14_n_0 ;
  wire [0:0]gt_ch_drp_rdy;
  wire gtxreset_reg1;
  wire gtxreset_reg2;
  wire [4:0]index;
  wire \index[0]_i_1__8_n_0 ;
  wire \index[1]_i_1__8_n_0 ;
  wire \index[2]_i_1__8_n_0 ;
  wire \index[3]_i_1__6_n_0 ;
  wire \index[3]_i_2__6_n_0 ;
  wire \index[4]_i_1__6_n_0 ;
  wire \index[4]_i_2__6_n_0 ;
  wire \index[4]_i_3__6_n_0 ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1__8_n_0 ;
  wire mode;
  wire mode_i_1__6_n_0;
  wire mode_i_2__6_n_0;
  wire mode_i_3__8_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire [1:0]rate_reg1;
  wire [1:0]rate_reg2;
  wire rdy_reg1;
  wire rdy_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rst_gtreset;
  wire start_reg1;
  wire start_reg2;
  wire x16_reg1;
  wire x16_reg2;
  wire x16x20_mode_reg1;
  wire x16x20_mode_reg2;

  LUT6 #(
    .INIT(64'h1471357514713564)) 
    \addr_reg[0]_i_1__6 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__6_n_0 ),
        .O(\addr_reg[0]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h404050500F0F0500)) 
    \addr_reg[1]_i_1__6 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[1]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h051005105A055A00)) 
    \addr_reg[2]_i_1__6 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(index[2]),
        .I4(mode),
        .I5(index[1]),
        .O(\addr_reg[2]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h5767576753275326)) 
    \addr_reg[3]_i_1__6 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(\addr_reg[4]_i_2__6_n_0 ),
        .I5(index[0]),
        .O(\addr_reg[3]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FCCFFF01)) 
    \addr_reg[4]_i_1__6 
       (.I0(\addr_reg[4]_i_2__6_n_0 ),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[3]),
        .I5(index[4]),
        .O(\addr_reg[4]_i_1__6_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \addr_reg[4]_i_2__6 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .O(\addr_reg[4]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h00001A1A0F0F0F0A)) 
    \addr_reg[5]_i_1__6 
       (.I0(index[4]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(mode),
        .I4(index[1]),
        .I5(index[2]),
        .O(\addr_reg[5]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000011545554)) 
    \addr_reg[6]_i_1__6 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(mode),
        .I3(index[3]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\addr_reg[6]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h5422262254222633)) 
    \addr_reg[7]_i_1__6 
       (.I0(index[4]),
        .I1(index[3]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\addr_reg[7]_i_2__6_n_0 ),
        .O(\addr_reg[7]_i_1__6_n_0 ));
  LUT3 #(
    .INIT(8'hCE)) 
    \addr_reg[7]_i_2__6 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .I2(index[0]),
        .O(\addr_reg[7]_i_2__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[0]_i_1__6_n_0 ),
        .Q(\addr_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[1]_i_1__6_n_0 ),
        .Q(\addr_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[2]_i_1__6_n_0 ),
        .Q(\addr_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[3]_i_1__6_n_0 ),
        .Q(\addr_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[4]_i_1__6_n_0 ),
        .Q(\addr_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[5]_i_1__6_n_0 ),
        .Q(\addr_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[6]_i_1__6_n_0 ),
        .Q(\addr_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\addr_reg[7]_i_1__6_n_0 ),
        .Q(\addr_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'hB8B8B8BBB8B8B888)) 
    \di_reg[0]_i_2__6 
       (.I0(\di_reg[0]_i_4__6_n_0 ),
        .I1(index[3]),
        .I2(do_reg2[0]),
        .I3(\di_reg[0]_i_5__6_n_0 ),
        .I4(\di_reg[0]_i_6__6_n_0 ),
        .I5(\di_reg[4]_i_8__6_n_0 ),
        .O(\di_reg[0]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h00003414)) 
    \di_reg[0]_i_3__6 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[0]),
        .I4(index[3]),
        .O(\di_reg[0]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hB0BFFFFFB0B00000)) 
    \di_reg[0]_i_4__6 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(do_reg2[0]),
        .O(\di_reg[0]_i_4__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \di_reg[0]_i_5__6 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .O(\di_reg[0]_i_5__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \di_reg[0]_i_6__6 
       (.I0(index[1]),
        .I1(mode),
        .I2(index[0]),
        .O(\di_reg[0]_i_6__6_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[10]_i_1__6 
       (.I0(index[4]),
        .I1(do_reg2[10]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[10]_i_2__6_n_0 ),
        .O(di_reg[10]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[10]_i_2__6 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[10]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[11]_i_1__6 
       (.I0(index[3]),
        .I1(\di_reg[11]_i_2__6_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[11]_i_3__6_n_0 ),
        .I4(\di_reg[11]_i_4__6_n_0 ),
        .I5(\di_reg[11]_i_5__6_n_0 ),
        .O(di_reg[11]));
  LUT6 #(
    .INIT(64'h0808080808380808)) 
    \di_reg[11]_i_2__6 
       (.I0(do_reg2[11]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[0]),
        .I4(rate_reg2[1]),
        .I5(index[0]),
        .O(\di_reg[11]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'hCC0CCC0C0C0C880C)) 
    \di_reg[11]_i_3__6 
       (.I0(data15),
        .I1(index[3]),
        .I2(do_reg2[11]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[11]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAAAAAABAAABA)) 
    \di_reg[11]_i_4__6 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[11]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAA00AAAAAAA3)) 
    \di_reg[11]_i_5__6 
       (.I0(do_reg2[11]),
        .I1(x16_reg2),
        .I2(\addr_reg[4]_i_2__6_n_0 ),
        .I3(index[0]),
        .I4(index[1]),
        .I5(index[2]),
        .O(\di_reg[11]_i_5__6_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \di_reg[12]_i_1__6 
       (.I0(\di_reg[12]_i_2__6_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[12]_i_3__6_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[12]_i_4__6_n_0 ),
        .O(di_reg[12]));
  LUT5 #(
    .INIT(32'h00003202)) 
    \di_reg[12]_i_2__6 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[12]),
        .I4(index[3]),
        .O(\di_reg[12]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[12]_i_3__6 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[12]),
        .O(\di_reg[12]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hAABAAA8AAABAAABA)) 
    \di_reg[12]_i_4__6 
       (.I0(do_reg2[12]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[12]_i_4__6_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \di_reg[13]_i_1__6 
       (.I0(\di_reg[13]_i_2__6_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[13]_i_3__6_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[13]_i_4__6_n_0 ),
        .O(di_reg[13]));
  LUT6 #(
    .INIT(64'h0808080838380838)) 
    \di_reg[13]_i_2__6 
       (.I0(do_reg2[13]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[13]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h04FFFFFF04000000)) 
    \di_reg[13]_i_3__6 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(do_reg2[13]),
        .O(\di_reg[13]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hAA8AAA8AAABAAA8A)) 
    \di_reg[13]_i_4__6 
       (.I0(do_reg2[13]),
        .I1(index[0]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(rate_reg2[1]),
        .I5(rate_reg2[0]),
        .O(\di_reg[13]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'h080008FF08000800)) 
    \di_reg[14]_i_1__6 
       (.I0(do_reg2[14]),
        .I1(\di_reg[14]_i_2__6_n_0 ),
        .I2(index[3]),
        .I3(index[4]),
        .I4(\di_reg[14]_i_3__6_n_0 ),
        .I5(\di_reg[14]_i_4__6_n_0 ),
        .O(di_reg[14]));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_2__6 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[14]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h0033303310130033)) 
    \di_reg[14]_i_3__6 
       (.I0(data15),
        .I1(index[3]),
        .I2(index[2]),
        .I3(do_reg2[14]),
        .I4(index[0]),
        .I5(index[1]),
        .O(\di_reg[14]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000DF10)) 
    \di_reg[14]_i_4__6 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(do_reg2[14]),
        .I4(index[2]),
        .I5(\di_reg[14]_i_6__6_n_0 ),
        .O(\di_reg[14]_i_4__6_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[14]_i_5__6 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .O(data15));
  LUT6 #(
    .INIT(64'hBBBB3BBBBBBB3FBB)) 
    \di_reg[14]_i_6__6 
       (.I0(\di_reg[14]_i_7__6_n_0 ),
        .I1(index[3]),
        .I2(index[0]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(\di_reg[5]_i_4__6_n_0 ),
        .O(\di_reg[14]_i_6__6_n_0 ));
  LUT4 #(
    .INIT(16'h4440)) 
    \di_reg[14]_i_7__6 
       (.I0(index[1]),
        .I1(index[2]),
        .I2(do_reg2[14]),
        .I3(index[0]),
        .O(\di_reg[14]_i_7__6_n_0 ));
  LUT6 #(
    .INIT(64'h544C4444044C4444)) 
    \di_reg[15]_i_1__6 
       (.I0(index[4]),
        .I1(do_reg2[15]),
        .I2(index[1]),
        .I3(index[3]),
        .I4(index[2]),
        .I5(\di_reg[15]_i_2__6_n_0 ),
        .O(di_reg[15]));
  LUT3 #(
    .INIT(8'h0D)) 
    \di_reg[15]_i_2__6 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .O(\di_reg[15]_i_2__6_n_0 ));
  LUT4 #(
    .INIT(16'hABAA)) 
    \di_reg[1]_i_1__6 
       (.I0(\di_reg[1]_i_2__6_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[1]_i_3__6_n_0 ),
        .I3(\di_reg[1]_i_4__6_n_0 ),
        .O(di_reg[1]));
  LUT6 #(
    .INIT(64'h0000000034140000)) 
    \di_reg[1]_i_2__6 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[1]),
        .I4(index[4]),
        .I5(index[3]),
        .O(\di_reg[1]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FB330000)) 
    \di_reg[1]_i_3__6 
       (.I0(index[2]),
        .I1(do_reg2[1]),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[3]),
        .I5(\di_reg[1]_i_5__6_n_0 ),
        .O(\di_reg[1]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFCCC5555)) 
    \di_reg[1]_i_4__6 
       (.I0(\di_reg[1]_i_6__6_n_0 ),
        .I1(do_reg2[1]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\di_reg[1]_i_4__6_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \di_reg[1]_i_5__6 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[0]),
        .I3(index[1]),
        .O(\di_reg[1]_i_5__6_n_0 ));
  LUT6 #(
    .INIT(64'h002F0F20F02FFF2F)) 
    \di_reg[1]_i_6__6 
       (.I0(rate_reg2[1]),
        .I1(rate_reg2[0]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(mode),
        .I5(do_reg2[1]),
        .O(\di_reg[1]_i_6__6_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \di_reg[2]_i_1__6 
       (.I0(\di_reg[2]_i_2__6_n_0 ),
        .I1(\di_reg[2]_i_3__6_n_0 ),
        .O(di_reg[2]));
  LUT6 #(
    .INIT(64'h00400500FFFFFFFF)) 
    \di_reg[2]_i_2__6 
       (.I0(index[3]),
        .I1(do_reg2[2]),
        .I2(index[2]),
        .I3(index[1]),
        .I4(index[0]),
        .I5(index[4]),
        .O(\di_reg[2]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF470047)) 
    \di_reg[2]_i_3__6 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(\di_reg[2]_i_4__6_n_0 ),
        .I3(index[3]),
        .I4(\di_reg[2]_i_5__6_n_0 ),
        .I5(index[4]),
        .O(\di_reg[2]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hF4F40404F00FF000)) 
    \di_reg[2]_i_4__6 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .I2(index[0]),
        .I3(mode),
        .I4(do_reg2[2]),
        .I5(index[1]),
        .O(\di_reg[2]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'hF5D535D5F5D5F5D5)) 
    \di_reg[2]_i_5__6 
       (.I0(do_reg2[2]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(index[0]),
        .I4(rate_reg2[0]),
        .I5(rate_reg2[1]),
        .O(\di_reg[2]_i_5__6_n_0 ));
  LUT6 #(
    .INIT(64'hBAAA1000AAFF0000)) 
    \di_reg[3]_i_2__6 
       (.I0(\di_reg[3]_i_4__6_n_0 ),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(do_reg2[3]),
        .I5(index[0]),
        .O(\di_reg[3]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h000000000033E200)) 
    \di_reg[3]_i_3__6 
       (.I0(data15),
        .I1(index[0]),
        .I2(do_reg2[3]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\di_reg[3]_i_3__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[3]_i_4__6 
       (.I0(index[3]),
        .I1(index[1]),
        .O(\di_reg[3]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'h404F404F404F4040)) 
    \di_reg[4]_i_1__6 
       (.I0(index[3]),
        .I1(\di_reg[4]_i_2__6_n_0 ),
        .I2(index[4]),
        .I3(\di_reg[4]_i_3__6_n_0 ),
        .I4(\di_reg[4]_i_4__6_n_0 ),
        .I5(\di_reg[4]_i_5__6_n_0 ),
        .O(di_reg[4]));
  LUT6 #(
    .INIT(64'h08080B0830303030)) 
    \di_reg[4]_i_2__6 
       (.I0(do_reg2[4]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[4]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DFFFFFFF)) 
    \di_reg[4]_i_3__6 
       (.I0(index[0]),
        .I1(rate_reg2[0]),
        .I2(rate_reg2[1]),
        .I3(index[2]),
        .I4(index[1]),
        .I5(\di_reg[4]_i_6__6_n_0 ),
        .O(\di_reg[4]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FFFFE00000000)) 
    \di_reg[4]_i_4__6 
       (.I0(mode),
        .I1(x16x20_mode_reg2),
        .I2(index[1]),
        .I3(index[2]),
        .I4(index[0]),
        .I5(do_reg2[4]),
        .O(\di_reg[4]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010C00)) 
    \di_reg[4]_i_5__6 
       (.I0(\di_reg[4]_i_7__6_n_0 ),
        .I1(index[1]),
        .I2(index[2]),
        .I3(index[0]),
        .I4(\di_reg[4]_i_8__6_n_0 ),
        .I5(index[3]),
        .O(\di_reg[4]_i_5__6_n_0 ));
  LUT5 #(
    .INIT(32'h1F0FFF0F)) 
    \di_reg[4]_i_6__6 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[3]),
        .I3(do_reg2[4]),
        .I4(index[1]),
        .O(\di_reg[4]_i_6__6_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \di_reg[4]_i_7__6 
       (.I0(x16x20_mode_reg2),
        .I1(mode),
        .O(\di_reg[4]_i_7__6_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \di_reg[4]_i_8__6 
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .O(\di_reg[4]_i_8__6_n_0 ));
  LUT6 #(
    .INIT(64'h33000000B888B888)) 
    \di_reg[5]_i_1__6 
       (.I0(\di_reg[5]_i_2__6_n_0 ),
        .I1(index[4]),
        .I2(\di_reg[5]_i_3__6_n_0 ),
        .I3(do_reg2[5]),
        .I4(\di_reg[5]_i_4__6_n_0 ),
        .I5(index[3]),
        .O(di_reg[5]));
  LUT6 #(
    .INIT(64'h0B0B080B33333033)) 
    \di_reg[5]_i_2__6 
       (.I0(do_reg2[5]),
        .I1(index[2]),
        .I2(index[1]),
        .I3(rate_reg2[1]),
        .I4(rate_reg2[0]),
        .I5(index[0]),
        .O(\di_reg[5]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \di_reg[5]_i_3__6 
       (.I0(index[2]),
        .I1(index[0]),
        .I2(index[1]),
        .I3(x16x20_mode_reg2),
        .I4(mode),
        .O(\di_reg[5]_i_3__6_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \di_reg[5]_i_4__6 
       (.I0(index[2]),
        .I1(index[1]),
        .O(\di_reg[5]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'h67FF000067000000)) 
    \di_reg[6]_i_2__6 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[6]),
        .I5(\di_reg[5]_i_3__6_n_0 ),
        .O(\di_reg[6]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h00002404)) 
    \di_reg[6]_i_3__6 
       (.I0(index[0]),
        .I1(index[1]),
        .I2(index[2]),
        .I3(do_reg2[6]),
        .I4(index[3]),
        .O(\di_reg[6]_i_3__6_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF0900)) 
    \di_reg[7]_i_2__6 
       (.I0(index[2]),
        .I1(index[1]),
        .I2(index[0]),
        .I3(index[3]),
        .I4(do_reg2[7]),
        .O(\di_reg[7]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h000000000C320032)) 
    \di_reg[7]_i_3__6 
       (.I0(data15),
        .I1(index[0]),
        .I2(index[1]),
        .I3(index[2]),
        .I4(do_reg2[7]),
        .I5(index[3]),
        .O(\di_reg[7]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[8]_i_1__6 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[8]),
        .O(di_reg[8]));
  LUT6 #(
    .INIT(64'h033733F300040000)) 
    \di_reg[9]_i_1__6 
       (.I0(index[0]),
        .I1(index[4]),
        .I2(index[2]),
        .I3(index[3]),
        .I4(index[1]),
        .I5(do_reg2[9]),
        .O(di_reg[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[0]),
        .Q(\di_reg_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[0]_i_1__6 
       (.I0(\di_reg[0]_i_2__6_n_0 ),
        .I1(\di_reg[0]_i_3__6_n_0 ),
        .O(di_reg[0]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[10]),
        .Q(\di_reg_reg_n_0_[10] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[11]),
        .Q(\di_reg_reg_n_0_[11] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[12]),
        .Q(\di_reg_reg_n_0_[12] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[13]),
        .Q(\di_reg_reg_n_0_[13] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[14]),
        .Q(\di_reg_reg_n_0_[14] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[15]),
        .Q(\di_reg_reg_n_0_[15] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[1]),
        .Q(\di_reg_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[2]),
        .Q(\di_reg_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[3]),
        .Q(\di_reg_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[3]_i_1__6 
       (.I0(\di_reg[3]_i_2__6_n_0 ),
        .I1(\di_reg[3]_i_3__6_n_0 ),
        .O(di_reg[3]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[4]),
        .Q(\di_reg_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[5]),
        .Q(\di_reg_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[6]),
        .Q(\di_reg_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[6]_i_1__6 
       (.I0(\di_reg[6]_i_2__6_n_0 ),
        .I1(\di_reg[6]_i_3__6_n_0 ),
        .O(di_reg[6]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[7]),
        .Q(\di_reg_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  MUXF7 \di_reg_reg[7]_i_1__6 
       (.I0(\di_reg[7]_i_2__6_n_0 ),
        .I1(\di_reg[7]_i_3__6_n_0 ),
        .O(di_reg[7]),
        .S(index[4]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[8]),
        .Q(\di_reg_reg_n_0_[8] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di_reg[9]),
        .Q(\di_reg_reg_n_0_[9] ),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[0]),
        .Q(do_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[10]),
        .Q(do_reg1[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[11]),
        .Q(do_reg1[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[12]),
        .Q(do_reg1[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[13]),
        .Q(do_reg1[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[14]),
        .Q(do_reg1[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[15]),
        .Q(do_reg1[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[1]),
        .Q(do_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[2]),
        .Q(do_reg1[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[3]),
        .Q(do_reg1[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[4]),
        .Q(do_reg1[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[5]),
        .Q(do_reg1[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[6]),
        .Q(do_reg1[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[7]),
        .Q(do_reg1[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[8]),
        .Q(do_reg1[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drpdo[9]),
        .Q(do_reg1[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(RST_DCLK_RESET));
  LUT4 #(
    .INIT(16'h0001)) 
    done_i_1__6
       (.I0(start_reg2),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(done_i_1__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(done_i_1__6_n_0),
        .Q(DRP_DONE),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0B3BFFFF0B3B0000)) 
    \fsm[0]_i_1__14 
       (.I0(data4),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(rdy_reg2),
        .I4(Q[2]),
        .I5(\fsm[0]_i_3__14_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT5 #(
    .INIT(32'hEFFEFFFF)) 
    \fsm[0]_i_2__6 
       (.I0(index[3]),
        .I1(index[1]),
        .I2(index[4]),
        .I3(index[2]),
        .I4(mode_i_2__6_n_0),
        .O(data4));
  LUT6 #(
    .INIT(64'h7477FFFF7477CCCC)) 
    \fsm[0]_i_3__14 
       (.I0(rdy_reg2),
        .I1(Q[1]),
        .I2(load_cnt[1]),
        .I3(load_cnt[0]),
        .I4(Q[0]),
        .I5(start_reg2),
        .O(\fsm[0]_i_3__14_n_0 ));
  LUT6 #(
    .INIT(64'h185018501D501850)) 
    \fsm[1]_i_1__6 
       (.I0(Q[2]),
        .I1(rdy_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(load_cnt[0]),
        .I5(load_cnt[1]),
        .O(fsm[1]));
  LUT4 #(
    .INIT(16'h6222)) 
    \fsm[2]_i_1__14 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(rdy_reg2),
        .I3(Q[0]),
        .O(fsm[2]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \gt_ch_drp_rdy[7]_INST_0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(gt_ch_drp_rdy));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_15__6 
       (.I0(ext_ch_gt_drpdi[15]),
        .I1(\di_reg_reg_n_0_[15] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[15]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_16__6 
       (.I0(ext_ch_gt_drpdi[14]),
        .I1(\di_reg_reg_n_0_[14] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[14]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_17__6 
       (.I0(ext_ch_gt_drpdi[13]),
        .I1(\di_reg_reg_n_0_[13] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[13]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_18__6 
       (.I0(ext_ch_gt_drpdi[12]),
        .I1(\di_reg_reg_n_0_[12] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[12]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_19__6 
       (.I0(ext_ch_gt_drpdi[11]),
        .I1(\di_reg_reg_n_0_[11] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[11]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_20__6 
       (.I0(ext_ch_gt_drpdi[10]),
        .I1(\di_reg_reg_n_0_[10] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[10]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_21__6 
       (.I0(ext_ch_gt_drpdi[9]),
        .I1(\di_reg_reg_n_0_[9] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[9]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_22__6 
       (.I0(ext_ch_gt_drpdi[8]),
        .I1(\di_reg_reg_n_0_[8] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_23__6 
       (.I0(ext_ch_gt_drpdi[7]),
        .I1(\di_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[7]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_24__6 
       (.I0(ext_ch_gt_drpdi[6]),
        .I1(\di_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[6]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_25__6 
       (.I0(ext_ch_gt_drpdi[5]),
        .I1(\di_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_26__6 
       (.I0(ext_ch_gt_drpdi[4]),
        .I1(\di_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_27__6 
       (.I0(ext_ch_gt_drpdi[3]),
        .I1(\di_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_28__6 
       (.I0(ext_ch_gt_drpdi[2]),
        .I1(\di_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_29__6 
       (.I0(ext_ch_gt_drpdi[1]),
        .I1(\di_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_30__6 
       (.I0(ext_ch_gt_drpdi[0]),
        .I1(\di_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPDI[0]));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT4 #(
    .INIT(16'h003E)) 
    \gtx_channel.gtxe2_channel_i_i_3__6 
       (.I0(ext_ch_gt_drpen),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\cplllock_reg1_reg[7] ));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_48__6 
       (.I0(ext_ch_gt_drpaddr[8]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(DRPADDR[8]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_49__6 
       (.I0(ext_ch_gt_drpaddr[7]),
        .I1(\addr_reg_reg_n_0_[7] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[7]));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT4 #(
    .INIT(16'h0032)) 
    \gtx_channel.gtxe2_channel_i_i_4__6 
       (.I0(ext_ch_gt_drpwe),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(\cplllock_reg1_reg[7]_0 ));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_50__6 
       (.I0(ext_ch_gt_drpaddr[6]),
        .I1(\addr_reg_reg_n_0_[6] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[6]));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_51__6 
       (.I0(ext_ch_gt_drpaddr[5]),
        .I1(\addr_reg_reg_n_0_[5] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[5]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_52__6 
       (.I0(ext_ch_gt_drpaddr[4]),
        .I1(\addr_reg_reg_n_0_[4] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[4]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_53__6 
       (.I0(ext_ch_gt_drpaddr[3]),
        .I1(\addr_reg_reg_n_0_[3] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[3]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_54__6 
       (.I0(ext_ch_gt_drpaddr[2]),
        .I1(\addr_reg_reg_n_0_[2] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[2]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_55__6 
       (.I0(ext_ch_gt_drpaddr[1]),
        .I1(\addr_reg_reg_n_0_[1] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[1]));
  LUT5 #(
    .INIT(32'hCCCCCCCA)) 
    \gtx_channel.gtxe2_channel_i_i_56__6 
       (.I0(ext_ch_gt_drpaddr[0]),
        .I1(\addr_reg_reg_n_0_[0] ),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(DRPADDR[0]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rst_gtreset),
        .Q(gtxreset_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gtxreset_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(gtxreset_reg1),
        .Q(gtxreset_reg2),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \index[0]_i_1__8 
       (.I0(index[0]),
        .I1(Q[2]),
        .I2(\index[3]_i_2__6_n_0 ),
        .O(\index[0]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT4 #(
    .INIT(16'h0220)) 
    \index[1]_i_1__8 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__6_n_0 ),
        .I2(index[1]),
        .I3(index[0]),
        .O(\index[1]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT5 #(
    .INIT(32'h02222000)) 
    \index[2]_i_1__8 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__6_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .O(\index[2]_i_1__8_n_0 ));
  LUT6 #(
    .INIT(64'h0222222220000000)) 
    \index[3]_i_1__6 
       (.I0(Q[2]),
        .I1(\index[3]_i_2__6_n_0 ),
        .I2(index[0]),
        .I3(index[1]),
        .I4(index[2]),
        .I5(index[3]),
        .O(\index[3]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAE)) 
    \index[3]_i_2__6 
       (.I0(Q[0]),
        .I1(mode_i_2__6_n_0),
        .I2(index[2]),
        .I3(index[4]),
        .I4(index[1]),
        .I5(index[3]),
        .O(\index[3]_i_2__6_n_0 ));
  LUT3 #(
    .INIT(8'h89)) 
    \index[4]_i_1__6 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\index[4]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \index[4]_i_2__6 
       (.I0(index[0]),
        .I1(index[2]),
        .I2(index[3]),
        .I3(index[1]),
        .I4(index[4]),
        .I5(\index[4]_i_3__6_n_0 ),
        .O(\index[4]_i_2__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \index[4]_i_3__6 
       (.I0(\index[3]_i_2__6_n_0 ),
        .I1(Q[2]),
        .O(\index[4]_i_3__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__6_n_0 ),
        .D(\index[0]_i_1__8_n_0 ),
        .Q(index[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__6_n_0 ),
        .D(\index[1]_i_1__8_n_0 ),
        .Q(index[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__6_n_0 ),
        .D(\index[2]_i_1__8_n_0 ),
        .Q(index[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__6_n_0 ),
        .D(\index[3]_i_1__6_n_0 ),
        .Q(index[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\index[4]_i_1__6_n_0 ),
        .D(\index[4]_i_2__6_n_0 ),
        .Q(index[4]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \load_cnt[0]_i_1__8 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(load_cnt[1]),
        .I3(Q[2]),
        .O(\load_cnt[0]_i_1__8_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__8_n_0 ),
        .Q(load_cnt[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(load_cnt[1]),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h00AAA2AAAAAAAA00)) 
    mode_i_1__6
       (.I0(mode),
        .I1(mode_i_2__6_n_0),
        .I2(mode_i_3__8_n_0),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(mode_i_1__6_n_0));
  LUT4 #(
    .INIT(16'hCCB8)) 
    mode_i_2__6
       (.I0(mode),
        .I1(index[0]),
        .I2(x16x20_mode_reg2),
        .I3(index[2]),
        .O(mode_i_2__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    mode_i_3__8
       (.I0(index[2]),
        .I1(index[4]),
        .I2(index[1]),
        .I3(index[3]),
        .O(mode_i_3__8_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mode_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(mode_i_1__6_n_0),
        .Q(mode),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[0]),
        .Q(rate_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rate_reg1[1]),
        .Q(rate_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ext_ch_gt_drprdy),
        .Q(rdy_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_START),
        .Q(start_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16),
        .Q(x16_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16_reg1),
        .Q(x16_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_X16X20_MODE),
        .Q(x16x20_mode_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE x16x20_mode_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(x16x20_mode_reg1),
        .Q(x16x20_mode_reg2),
        .R(RST_DCLK_RESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_eq" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq
   (TXPRECURSOR,
    TXMAINCURSOR,
    TXPOSTCURSOR,
    USER_RXEQ_ADAPT_DONE,
    RST_CPLLRESET,
    CLK,
    rate_gen3);
  output [4:0]TXPRECURSOR;
  output [6:0]TXMAINCURSOR;
  output [4:0]TXPOSTCURSOR;
  output USER_RXEQ_ADAPT_DONE;
  input RST_CPLLRESET;
  input CLK;
  input [0:0]rate_gen3;

  wire CLK;
  wire \FSM_onehot_fsm_tx[1]_i_1_n_0 ;
  wire \FSM_onehot_fsm_tx[1]_i_2_n_0 ;
  wire \FSM_onehot_fsm_tx[2]_i_1_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_1_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_2_n_0 ;
  wire \FSM_onehot_fsm_tx[4]_i_1_n_0 ;
  wire \FSM_onehot_fsm_tx[5]_i_1_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_1_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_2_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_3_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[4] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[5] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[6] ;
  wire \FSM_sequential_fsm_rx[0]_i_2_n_0 ;
  wire \FSM_sequential_fsm_rx[0]_i_3_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_2_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_3_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[2] ;
  wire RST_CPLLRESET;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_RXEQ_ADAPT_DONE;
  wire gen3_reg1;
  wire gen3_reg2;
  wire [0:0]rate_gen3;
  wire rxeq_adapt_done_reg_reg_n_0;
  wire [2:0]rxeq_cnt;
  wire \rxeq_cnt_reg_n_0_[0] ;
  wire \rxeq_cnt_reg_n_0_[1] ;
  wire \rxeq_cnt_reg_n_0_[2] ;
  wire [1:0]rxeq_control_reg1;
  wire [1:0]rxeq_control_reg2;
  wire [5:0]rxeq_fs;
  wire \rxeq_fs[5]_i_1_n_0 ;
  wire [5:0]rxeq_fs__0;
  wire [5:0]rxeq_lf;
  wire \rxeq_lf[5]_i_1_n_0 ;
  wire [5:0]rxeq_lf__0;
  wire [5:0]rxeq_lffs_reg1;
  wire [5:0]rxeq_lffs_reg2;
  wire rxeq_new_txcoeff_req_reg_n_0;
  wire \rxeq_preset[0]_i_1_n_0 ;
  wire \rxeq_preset[1]_i_1_n_0 ;
  wire \rxeq_preset[2]_i_1_n_0 ;
  wire \rxeq_preset[2]_i_2_n_0 ;
  wire [2:0]rxeq_preset__0;
  wire [2:0]rxeq_preset_reg1;
  wire [2:0]rxeq_preset_reg2;
  wire rxeq_preset_valid;
  wire rxeq_preset_valid_reg_n_0;
  wire rxeq_scan_i_n_0;
  wire rxeq_scan_i_n_1;
  wire rxeq_scan_i_n_2;
  wire rxeq_scan_i_n_3;
  wire rxeq_scan_i_n_4;
  wire rxeq_scan_i_n_5;
  wire [17:0]rxeq_txcoeff;
  wire [5:0]rxeq_txcoeff__0;
  wire \rxeq_txcoeff_reg_n_0_[10] ;
  wire \rxeq_txcoeff_reg_n_0_[11] ;
  wire \rxeq_txcoeff_reg_n_0_[12] ;
  wire \rxeq_txcoeff_reg_n_0_[13] ;
  wire \rxeq_txcoeff_reg_n_0_[14] ;
  wire \rxeq_txcoeff_reg_n_0_[15] ;
  wire \rxeq_txcoeff_reg_n_0_[16] ;
  wire \rxeq_txcoeff_reg_n_0_[17] ;
  wire \rxeq_txcoeff_reg_n_0_[6] ;
  wire \rxeq_txcoeff_reg_n_0_[7] ;
  wire \rxeq_txcoeff_reg_n_0_[8] ;
  wire \rxeq_txcoeff_reg_n_0_[9] ;
  wire [3:0]rxeq_txpreset;
  wire \rxeq_txpreset[3]_i_1_n_0 ;
  wire [3:0]rxeq_txpreset__0;
  wire [3:0]rxeq_txpreset_reg1;
  wire [3:0]rxeq_txpreset_reg2;
  wire rxeq_user_en_reg1;
  wire rxeq_user_en_reg2;
  wire rxeq_user_mode_reg1;
  wire rxeq_user_mode_reg2;
  wire [17:0]rxeq_user_txcoeff_reg1;
  wire [17:0]rxeq_user_txcoeff_reg2;
  wire [1:0]txeq_control_reg1;
  wire [1:0]txeq_control_reg2;
  wire [5:0]txeq_deemph_reg1;
  wire [5:0]txeq_deemph_reg2;
  wire \txeq_preset[0]_i_1_n_0 ;
  wire \txeq_preset[10]_i_1_n_0 ;
  wire \txeq_preset[11]_i_1_n_0 ;
  wire \txeq_preset[12]_i_1_n_0 ;
  wire \txeq_preset[13]_i_1_n_0 ;
  wire \txeq_preset[14]_i_1_n_0 ;
  wire \txeq_preset[15]_i_1_n_0 ;
  wire \txeq_preset[16]_i_1_n_0 ;
  wire \txeq_preset[17]_i_1__6_n_0 ;
  wire \txeq_preset[17]_i_2_n_0 ;
  wire \txeq_preset[1]_i_1_n_0 ;
  wire \txeq_preset[2]_i_1_n_0 ;
  wire \txeq_preset[3]_i_1_n_0 ;
  wire \txeq_preset[7]_i_1_n_0 ;
  wire \txeq_preset[8]_i_1_n_0 ;
  wire \txeq_preset[9]_i_1_n_0 ;
  wire txeq_preset_done;
  wire [3:0]txeq_preset_reg1;
  wire [3:0]txeq_preset_reg2;
  wire \txeq_preset_reg_n_0_[0] ;
  wire \txeq_preset_reg_n_0_[10] ;
  wire \txeq_preset_reg_n_0_[11] ;
  wire \txeq_preset_reg_n_0_[12] ;
  wire \txeq_preset_reg_n_0_[13] ;
  wire \txeq_preset_reg_n_0_[14] ;
  wire \txeq_preset_reg_n_0_[15] ;
  wire \txeq_preset_reg_n_0_[16] ;
  wire \txeq_preset_reg_n_0_[17] ;
  wire \txeq_preset_reg_n_0_[1] ;
  wire \txeq_preset_reg_n_0_[2] ;
  wire \txeq_preset_reg_n_0_[3] ;
  wire \txeq_preset_reg_n_0_[4] ;
  wire \txeq_preset_reg_n_0_[5] ;
  wire \txeq_preset_reg_n_0_[6] ;
  wire \txeq_preset_reg_n_0_[7] ;
  wire \txeq_preset_reg_n_0_[8] ;
  wire \txeq_preset_reg_n_0_[9] ;
  wire \txeq_txcoeff[0]_i_1_n_0 ;
  wire \txeq_txcoeff[0]_i_2_n_0 ;
  wire \txeq_txcoeff[10]_i_1_n_0 ;
  wire \txeq_txcoeff[10]_i_2_n_0 ;
  wire \txeq_txcoeff[11]_i_1_n_0 ;
  wire \txeq_txcoeff[11]_i_2_n_0 ;
  wire \txeq_txcoeff[12]_i_1_n_0 ;
  wire \txeq_txcoeff[12]_i_2_n_0 ;
  wire \txeq_txcoeff[13]_i_1_n_0 ;
  wire \txeq_txcoeff[13]_i_2_n_0 ;
  wire \txeq_txcoeff[14]_i_1_n_0 ;
  wire \txeq_txcoeff[14]_i_2_n_0 ;
  wire \txeq_txcoeff[15]_i_1_n_0 ;
  wire \txeq_txcoeff[15]_i_2_n_0 ;
  wire \txeq_txcoeff[16]_i_1_n_0 ;
  wire \txeq_txcoeff[16]_i_2_n_0 ;
  wire \txeq_txcoeff[17]_i_1_n_0 ;
  wire \txeq_txcoeff[17]_i_2_n_0 ;
  wire \txeq_txcoeff[18]_i_1_n_0 ;
  wire \txeq_txcoeff[18]_i_2_n_0 ;
  wire \txeq_txcoeff[18]_i_3_n_0 ;
  wire \txeq_txcoeff[1]_i_1_n_0 ;
  wire \txeq_txcoeff[1]_i_2_n_0 ;
  wire \txeq_txcoeff[2]_i_1_n_0 ;
  wire \txeq_txcoeff[2]_i_2_n_0 ;
  wire \txeq_txcoeff[3]_i_1_n_0 ;
  wire \txeq_txcoeff[3]_i_2_n_0 ;
  wire \txeq_txcoeff[4]_i_1_n_0 ;
  wire \txeq_txcoeff[4]_i_2_n_0 ;
  wire \txeq_txcoeff[5]_i_1_n_0 ;
  wire \txeq_txcoeff[5]_i_2_n_0 ;
  wire \txeq_txcoeff[6]_i_1_n_0 ;
  wire \txeq_txcoeff[6]_i_2_n_0 ;
  wire \txeq_txcoeff[7]_i_1_n_0 ;
  wire \txeq_txcoeff[7]_i_2_n_0 ;
  wire \txeq_txcoeff[8]_i_1_n_0 ;
  wire \txeq_txcoeff[8]_i_2_n_0 ;
  wire \txeq_txcoeff[9]_i_1_n_0 ;
  wire \txeq_txcoeff[9]_i_2_n_0 ;
  wire [1:0]txeq_txcoeff_cnt;
  wire \txeq_txcoeff_cnt_reg_n_0_[0] ;
  wire \txeq_txcoeff_cnt_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[0] ;
  wire \txeq_txcoeff_reg_n_0_[10] ;
  wire \txeq_txcoeff_reg_n_0_[11] ;
  wire \txeq_txcoeff_reg_n_0_[12] ;
  wire \txeq_txcoeff_reg_n_0_[13] ;
  wire \txeq_txcoeff_reg_n_0_[14] ;
  wire \txeq_txcoeff_reg_n_0_[15] ;
  wire \txeq_txcoeff_reg_n_0_[16] ;
  wire \txeq_txcoeff_reg_n_0_[17] ;
  wire \txeq_txcoeff_reg_n_0_[18] ;
  wire \txeq_txcoeff_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[2] ;
  wire \txeq_txcoeff_reg_n_0_[3] ;
  wire \txeq_txcoeff_reg_n_0_[4] ;
  wire \txeq_txcoeff_reg_n_0_[5] ;
  wire \txeq_txcoeff_reg_n_0_[6] ;
  wire \txeq_txcoeff_reg_n_0_[7] ;
  wire \txeq_txcoeff_reg_n_0_[8] ;
  wire \txeq_txcoeff_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'h000000FF10101050)) 
    \FSM_onehot_fsm_tx[1]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx[1]_i_2_n_0 ),
        .I3(txeq_control_reg2[0]),
        .I4(txeq_control_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_onehot_fsm_tx[1]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h20202F20)) 
    \FSM_onehot_fsm_tx[2]_i_1 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I4(txeq_preset_done),
        .O(\FSM_onehot_fsm_tx[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h45454545FF454545)) 
    \FSM_onehot_fsm_tx[3]_i_1 
       (.I0(\FSM_onehot_fsm_tx[3]_i_2_n_0 ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(\FSM_onehot_fsm_tx[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_onehot_fsm_tx[3]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm_tx[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \FSM_onehot_fsm_tx[4]_i_1 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm_tx[5]_i_1 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \FSM_onehot_fsm_tx[6]_i_1 
       (.I0(\FSM_onehot_fsm_tx[6]_i_2_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_tx[6]_i_3_n_0 ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBBBBBB8)) 
    \FSM_onehot_fsm_tx[6]_i_2 
       (.I0(txeq_preset_done),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[6]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_fsm_tx[6]_i_3 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .O(\FSM_onehot_fsm_tx[6]_i_3_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_tx_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[1]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[2]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[3]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[4]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[5]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[6]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h838183C3)) 
    \FSM_sequential_fsm_rx[0]_i_2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(rxeq_control_reg2[0]),
        .O(\FSM_sequential_fsm_rx[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFD000080)) 
    \FSM_sequential_fsm_rx[0]_i_3 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm_rx[0]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_fsm_rx[2]_i_2 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fsm_rx[2]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_fsm_rx[2]_i_3 
       (.I0(rxeq_control_reg2[0]),
        .I1(rxeq_control_reg2[1]),
        .O(\FSM_sequential_fsm_rx[2]_i_3_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_scan_i_n_2),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_scan_i_n_1),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_scan_i_n_0),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_30 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .O(TXPOSTCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_31 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[16] ),
        .O(TXPOSTCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_32 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .O(TXPOSTCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_33 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .O(TXPOSTCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_34 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[13] ),
        .O(TXPOSTCURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_35 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[4] ),
        .O(TXPRECURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_36 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[3] ),
        .O(TXPRECURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_37 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[2] ),
        .O(TXPRECURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_38 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[1] ),
        .O(TXPRECURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_39 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[0] ),
        .O(TXPRECURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_40 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .O(TXMAINCURSOR[6]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_41 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .O(TXMAINCURSOR[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_42 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .O(TXMAINCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_43 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[9] ),
        .O(TXMAINCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_44 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[8] ),
        .O(TXMAINCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_45 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[7] ),
        .O(TXMAINCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_46 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[6] ),
        .O(TXMAINCURSOR[0]));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_scan_i_n_4),
        .Q(USER_RXEQ_ADAPT_DONE),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_scan_i_n_5),
        .Q(rxeq_adapt_done_reg_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04041C10)) 
    \rxeq_cnt[0]_i_1 
       (.I0(\rxeq_cnt_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_cnt[0]));
  LUT5 #(
    .INIT(32'h00424200)) 
    \rxeq_cnt[1]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[1] ),
        .I4(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[1]));
  LUT6 #(
    .INIT(64'h0042420042004200)) 
    \rxeq_cnt[2]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[2] ),
        .I4(\rxeq_cnt_reg_n_0_[1] ),
        .I5(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[2]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_cnt[0]),
        .Q(\rxeq_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_cnt[1]),
        .Q(\rxeq_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_cnt[2]),
        .Q(\rxeq_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_control_reg1[0]),
        .Q(rxeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_control_reg1[1]),
        .Q(rxeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[0]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_fs[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[1]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_fs[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[2]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_fs[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[3]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_fs[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[4]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_fs[4]));
  LUT4 #(
    .INIT(16'hC203)) 
    \rxeq_fs[5]_i_1 
       (.I0(rxeq_control_reg2[1]),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_fs[5]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[5]_i_2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_fs[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[0] 
       (.C(CLK),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[0]),
        .Q(rxeq_fs__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[1] 
       (.C(CLK),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[1]),
        .Q(rxeq_fs__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[2] 
       (.C(CLK),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[2]),
        .Q(rxeq_fs__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[3] 
       (.C(CLK),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[3]),
        .Q(rxeq_fs__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[4] 
       (.C(CLK),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[4]),
        .Q(rxeq_fs__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[5] 
       (.C(CLK),
        .CE(\rxeq_fs[5]_i_1_n_0 ),
        .D(rxeq_fs[5]),
        .Q(rxeq_fs__0[5]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[0]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_lf[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[1]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_lf[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[2]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_lf[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[3]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_lf[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[4]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_lf[4]));
  LUT6 #(
    .INIT(64'hFF000000000080FF)) 
    \rxeq_lf[5]_i_1 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\rxeq_cnt_reg_n_0_[2] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I5(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_lf[5]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[5]_i_2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_lf[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[0] 
       (.C(CLK),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[0]),
        .Q(rxeq_lf__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[1] 
       (.C(CLK),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[1]),
        .Q(rxeq_lf__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[2] 
       (.C(CLK),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[2]),
        .Q(rxeq_lf__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[3] 
       (.C(CLK),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[3]),
        .Q(rxeq_lf__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[4] 
       (.C(CLK),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[4]),
        .Q(rxeq_lf__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[5] 
       (.C(CLK),
        .CE(\rxeq_lf[5]_i_1_n_0 ),
        .D(rxeq_lf[5]),
        .Q(rxeq_lf__0[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[0]),
        .Q(rxeq_lffs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[1]),
        .Q(rxeq_lffs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[2]),
        .Q(rxeq_lffs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[3]),
        .Q(rxeq_lffs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[4]),
        .Q(rxeq_lffs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[5]),
        .Q(rxeq_lffs_reg2[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_new_txcoeff_req_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_scan_i_n_3),
        .Q(rxeq_new_txcoeff_req_reg_n_0),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[0]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[0]),
        .I4(\rxeq_preset[2]_i_2_n_0 ),
        .I5(rxeq_preset__0[0]),
        .O(\rxeq_preset[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[1]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[1]),
        .I4(\rxeq_preset[2]_i_2_n_0 ),
        .I5(rxeq_preset__0[1]),
        .O(\rxeq_preset[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[2]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[2]),
        .I4(\rxeq_preset[2]_i_2_n_0 ),
        .I5(rxeq_preset__0[2]),
        .O(\rxeq_preset[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF00400FF)) 
    \rxeq_preset[2]_i_2 
       (.I0(rxeq_control_reg2[1]),
        .I1(rxeq_control_reg2[0]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_preset[2]_i_2_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_preset_reg1[0]),
        .Q(rxeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_preset_reg1[1]),
        .Q(rxeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_preset_reg1[2]),
        .Q(rxeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_preset[0]_i_1_n_0 ),
        .Q(rxeq_preset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_preset[1]_i_1_n_0 ),
        .Q(rxeq_preset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_preset[2]_i_1_n_0 ),
        .Q(rxeq_preset__0[2]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h04)) 
    rxeq_preset_valid_i_1
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(rxeq_preset_valid));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_preset_valid_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_preset_valid),
        .Q(rxeq_preset_valid_reg_n_0),
        .R(RST_CPLLRESET));
  PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_86 rxeq_scan_i
       (.CLK(CLK),
        .D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}),
        .\FSM_sequential_fsm_rx_reg[0] (\FSM_sequential_fsm_rx[0]_i_2_n_0 ),
        .\FSM_sequential_fsm_rx_reg[2] ({\FSM_sequential_fsm_rx_reg_n_0_[2] ,\FSM_sequential_fsm_rx_reg_n_0_[1] ,\FSM_sequential_fsm_rx_reg_n_0_[0] }),
        .Q(rxeq_txpreset__0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE),
        .out(rxeq_control_reg2),
        .rxeq_adapt_done_reg(rxeq_scan_i_n_4),
        .rxeq_adapt_done_reg_reg(rxeq_scan_i_n_5),
        .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_reg_n_0),
        .\rxeq_cnt_reg[1] (\FSM_sequential_fsm_rx[0]_i_3_n_0 ),
        .\rxeq_cnt_reg[1]_0 (\FSM_sequential_fsm_rx[2]_i_2_n_0 ),
        .\rxeq_control_reg2_reg[0] (\FSM_sequential_fsm_rx[2]_i_3_n_0 ),
        .\rxeq_fs_reg[5] (rxeq_fs__0),
        .\rxeq_lf_reg[5] (rxeq_lf__0),
        .rxeq_new_txcoeff_req_reg(rxeq_scan_i_n_3),
        .rxeq_new_txcoeff_req_reg_0(rxeq_new_txcoeff_req_reg_n_0),
        .\rxeq_preset_reg[2] (rxeq_preset__0),
        .rxeq_preset_valid_reg(rxeq_preset_valid_reg_n_0),
        .\rxeq_txcoeff_reg[17] ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,rxeq_txcoeff__0}));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[0]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[6] ),
        .O(rxeq_txcoeff[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[10]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[16] ),
        .O(rxeq_txcoeff[10]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[11]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[17] ),
        .O(rxeq_txcoeff[11]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[12]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[0]),
        .O(rxeq_txcoeff[12]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[13]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[1]),
        .O(rxeq_txcoeff[13]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[14]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[2]),
        .O(rxeq_txcoeff[14]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[15]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[3]),
        .O(rxeq_txcoeff[15]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[16]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[4]),
        .O(rxeq_txcoeff[16]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[17]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[5]),
        .O(rxeq_txcoeff[17]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[1]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[7] ),
        .O(rxeq_txcoeff[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[2]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[8] ),
        .O(rxeq_txcoeff[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[3]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[9] ),
        .O(rxeq_txcoeff[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[4]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[10] ),
        .O(rxeq_txcoeff[4]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[5]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[11] ),
        .O(rxeq_txcoeff[5]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[6]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[12] ),
        .O(rxeq_txcoeff[6]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[7]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[13] ),
        .O(rxeq_txcoeff[7]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[8]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[14] ),
        .O(rxeq_txcoeff[8]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[9]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[15] ),
        .O(rxeq_txcoeff[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[0] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[0]),
        .Q(rxeq_txcoeff__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[10] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[10]),
        .Q(\rxeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[11] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[11]),
        .Q(\rxeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[12] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[12]),
        .Q(\rxeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[13] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[13]),
        .Q(\rxeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[14] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[14]),
        .Q(\rxeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[15] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[15]),
        .Q(\rxeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[16] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[16]),
        .Q(\rxeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[17] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[17]),
        .Q(\rxeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[1] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[1]),
        .Q(rxeq_txcoeff__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[2] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[2]),
        .Q(rxeq_txcoeff__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[3] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[3]),
        .Q(rxeq_txcoeff__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[4] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[4]),
        .Q(rxeq_txcoeff__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[5] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[5]),
        .Q(rxeq_txcoeff__0[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[6] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[6]),
        .Q(\rxeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[7] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[7]),
        .Q(\rxeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[8] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[8]),
        .Q(\rxeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[9] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txcoeff[9]),
        .Q(\rxeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[0]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[0]),
        .O(rxeq_txpreset[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[1]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[1]),
        .O(rxeq_txpreset[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[2]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[2]),
        .O(rxeq_txpreset[2]));
  LUT4 #(
    .INIT(16'hF405)) 
    \rxeq_txpreset[3]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_txpreset[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[3]_i_2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[3]),
        .O(rxeq_txpreset[3]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[0]),
        .Q(rxeq_txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[1]),
        .Q(rxeq_txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[2]),
        .Q(rxeq_txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[3]),
        .Q(rxeq_txpreset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[0] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txpreset[0]),
        .Q(rxeq_txpreset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[1] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txpreset[1]),
        .Q(rxeq_txpreset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[2] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txpreset[2]),
        .Q(rxeq_txpreset__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[3] 
       (.C(CLK),
        .CE(\rxeq_txpreset[3]_i_1_n_0 ),
        .D(rxeq_txpreset[3]),
        .Q(rxeq_txpreset__0[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_en_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_en_reg1),
        .Q(rxeq_user_en_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_mode_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_mode_reg1),
        .Q(rxeq_user_mode_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[0]),
        .Q(rxeq_user_txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[10]),
        .Q(rxeq_user_txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[11]),
        .Q(rxeq_user_txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[12]),
        .Q(rxeq_user_txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[13]),
        .Q(rxeq_user_txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[14]),
        .Q(rxeq_user_txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[15]),
        .Q(rxeq_user_txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[16]),
        .Q(rxeq_user_txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[17]),
        .Q(rxeq_user_txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[1]),
        .Q(rxeq_user_txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[2]),
        .Q(rxeq_user_txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[3]),
        .Q(rxeq_user_txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[4]),
        .Q(rxeq_user_txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[5]),
        .Q(rxeq_user_txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[6]),
        .Q(rxeq_user_txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[7]),
        .Q(rxeq_user_txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[8]),
        .Q(rxeq_user_txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[9]),
        .Q(rxeq_user_txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_control_reg1[0]),
        .Q(txeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_control_reg1[1]),
        .Q(txeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_deemph_reg1[0]),
        .Q(txeq_deemph_reg2[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_deemph_reg1[1]),
        .Q(txeq_deemph_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_deemph_reg1[2]),
        .Q(txeq_deemph_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_deemph_reg1[3]),
        .Q(txeq_deemph_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_deemph_reg1[4]),
        .Q(txeq_deemph_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_deemph_reg1[5]),
        .Q(txeq_deemph_reg2[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00001000)) 
    \txeq_preset[0]_i_1 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAEABBABB)) 
    \txeq_preset[10]_i_1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[10]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAEAABABB)) 
    \txeq_preset[11]_i_1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[11]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00001574)) 
    \txeq_preset[12]_i_1 
       (.I0(txeq_preset_reg2[3]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[12]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[13]_i_1 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[13]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000410)) 
    \txeq_preset[14]_i_1 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[14]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hAAAB)) 
    \txeq_preset[15]_i_1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .O(\txeq_preset[15]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0014)) 
    \txeq_preset[16]_i_1 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[16]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \txeq_preset[17]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(RST_CPLLRESET),
        .O(\txeq_preset[17]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hAAEABABB)) 
    \txeq_preset[17]_i_2 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[17]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[1]_i_1 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h00C8)) 
    \txeq_preset[2]_i_1 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00003424)) 
    \txeq_preset[3]_i_1 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000408)) 
    \txeq_preset[7]_i_1 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAEBBFB)) 
    \txeq_preset[8]_i_1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[8]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAEAEBABB)) 
    \txeq_preset[9]_i_1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    txeq_preset_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .Q(txeq_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_preset_reg1[0]),
        .Q(txeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_preset_reg1[1]),
        .Q(txeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_preset_reg1[2]),
        .Q(txeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_preset_reg1[3]),
        .Q(txeq_preset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[0] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[0]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[10] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[10]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[11] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[11]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[12] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[12]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[13] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[13]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[14] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[14]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[15] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[15]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[16] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[16]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[17] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[17]_i_2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[1] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[1]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[2] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[2]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[3] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[3]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[4] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[5] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[6] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[7] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[7]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[8] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[8]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[9] 
       (.C(CLK),
        .CE(\txeq_preset[17]_i_1__6_n_0 ),
        .D(\txeq_preset[9]_i_1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[0]_i_1 
       (.I0(\txeq_txcoeff_reg_n_0_[6] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\txeq_preset_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[0]_i_2_n_0 ),
        .O(\txeq_txcoeff[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAA208A00)) 
    \txeq_txcoeff[0]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .O(\txeq_txcoeff[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[10]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[10] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[9] ),
        .I4(\txeq_txcoeff[10]_i_2_n_0 ),
        .O(\txeq_txcoeff[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[10]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[16] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[10]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[11]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[11] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[10] ),
        .I4(\txeq_txcoeff[11]_i_2_n_0 ),
        .O(\txeq_txcoeff[11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[11]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[18] ),
        .I2(\txeq_txcoeff_reg_n_0_[17] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[11]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[12]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[11] ),
        .I4(\txeq_txcoeff[12]_i_2_n_0 ),
        .O(\txeq_txcoeff[12]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[12]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[0]),
        .I2(\txeq_txcoeff_reg_n_0_[18] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[12]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[13]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[13] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[12] ),
        .I4(\txeq_txcoeff[13]_i_2_n_0 ),
        .O(\txeq_txcoeff[13]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[13]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[1]),
        .I2(txeq_deemph_reg2[0]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[13]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[14]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[14] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[13] ),
        .I4(\txeq_txcoeff[14]_i_2_n_0 ),
        .O(\txeq_txcoeff[14]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[14]_i_2 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[14]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[15]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[15] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[14] ),
        .I4(\txeq_txcoeff[15]_i_2_n_0 ),
        .O(\txeq_txcoeff[15]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[15]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[3]),
        .I2(txeq_deemph_reg2[2]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[15]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[16]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[16] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[15] ),
        .I4(\txeq_txcoeff[16]_i_2_n_0 ),
        .O(\txeq_txcoeff[16]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[16]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[4]),
        .I2(txeq_deemph_reg2[3]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[16]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[17]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[17] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[16] ),
        .I4(\txeq_txcoeff[17]_i_2_n_0 ),
        .O(\txeq_txcoeff[17]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[17]_i_2 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[4]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[17]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5557FF5755575557)) 
    \txeq_txcoeff[18]_i_1 
       (.I0(\FSM_onehot_fsm_tx[1]_i_2_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[0]),
        .I5(txeq_control_reg2[1]),
        .O(\txeq_txcoeff[18]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \txeq_txcoeff[18]_i_2 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\txeq_txcoeff[18]_i_3_n_0 ),
        .O(\txeq_txcoeff[18]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF888F8F888888888)) 
    \txeq_txcoeff[18]_i_3 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(txeq_deemph_reg2[5]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[18]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[1]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[1]_i_2_n_0 ),
        .O(\txeq_txcoeff[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[1]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[2]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[1] ),
        .I4(\txeq_txcoeff[2]_i_2_n_0 ),
        .O(\txeq_txcoeff[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[2]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[8] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[3]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[2] ),
        .I4(\txeq_txcoeff[3]_i_2_n_0 ),
        .O(\txeq_txcoeff[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[3]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .I2(\txeq_txcoeff_reg_n_0_[9] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[4]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[3] ),
        .I4(\txeq_txcoeff[4]_i_2_n_0 ),
        .O(\txeq_txcoeff[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[4]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .I2(\txeq_txcoeff_reg_n_0_[10] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[5]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[5] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[4] ),
        .I4(\txeq_txcoeff[5]_i_2_n_0 ),
        .O(\txeq_txcoeff[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[5]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .I2(\txeq_txcoeff_reg_n_0_[11] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[6]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[5] ),
        .I4(\txeq_txcoeff[6]_i_2_n_0 ),
        .O(\txeq_txcoeff[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[6]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[12] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[7]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[7] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff[7]_i_2_n_0 ),
        .O(\txeq_txcoeff[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[7]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .I2(\txeq_txcoeff_reg_n_0_[13] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[8]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[8] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[7] ),
        .I4(\txeq_txcoeff[8]_i_2_n_0 ),
        .O(\txeq_txcoeff[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[8]_i_2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .I2(\txeq_txcoeff_reg_n_0_[14] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[9]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[9] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[8] ),
        .I4(\txeq_txcoeff[9]_i_2_n_0 ),
        .O(\txeq_txcoeff[9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[9]_i_2 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[15] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[9]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h4444F444)) 
    \txeq_txcoeff_cnt[0]_i_1 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(txeq_control_reg2[1]),
        .I4(txeq_control_reg2[0]),
        .O(txeq_txcoeff_cnt[0]));
  LUT3 #(
    .INIT(8'h28)) 
    \txeq_txcoeff_cnt[1]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(txeq_txcoeff_cnt[1]));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[0]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[1]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[0] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[0]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[10] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[10]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[11] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[11]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[12] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[12]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[13] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[13]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[14] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[14]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[15] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[15]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[16] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[16]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[17] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[17]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[18] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[18]_i_2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[1] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[1]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[2] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[2]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[3] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[3]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[4] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[4]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[5] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[5]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[6] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[6]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[7] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[7]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[8] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[8]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[9] 
       (.C(CLK),
        .CE(\txeq_txcoeff[18]_i_1_n_0 ),
        .D(\txeq_txcoeff[9]_i_1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_eq" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_31
   (TXPRECURSOR,
    TXMAINCURSOR,
    TXPOSTCURSOR,
    USER_RXEQ_ADAPT_DONE,
    RST_CPLLRESET,
    pclk_sel_reg,
    rate_gen3);
  output [4:0]TXPRECURSOR;
  output [6:0]TXMAINCURSOR;
  output [4:0]TXPOSTCURSOR;
  output USER_RXEQ_ADAPT_DONE;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]rate_gen3;

  wire \FSM_onehot_fsm_tx[1]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm_tx[1]_i_2__0_n_0 ;
  wire \FSM_onehot_fsm_tx[2]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_2__0_n_0 ;
  wire \FSM_onehot_fsm_tx[4]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm_tx[5]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_2__0_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_3__0_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[4] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[5] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[6] ;
  wire \FSM_sequential_fsm_rx[0]_i_2__0_n_0 ;
  wire \FSM_sequential_fsm_rx[0]_i_3__0_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_2__0_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_3__0_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[2] ;
  wire RST_CPLLRESET;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_RXEQ_ADAPT_DONE;
  wire gen3_reg1;
  wire gen3_reg2;
  wire pclk_sel_reg;
  wire [0:0]rate_gen3;
  wire rxeq_adapt_done_reg_reg_n_0;
  wire [2:0]rxeq_cnt;
  wire \rxeq_cnt_reg_n_0_[0] ;
  wire \rxeq_cnt_reg_n_0_[1] ;
  wire \rxeq_cnt_reg_n_0_[2] ;
  wire [1:0]rxeq_control_reg1;
  wire [1:0]rxeq_control_reg2;
  wire [5:0]rxeq_fs;
  wire \rxeq_fs[5]_i_1__0_n_0 ;
  wire [5:0]rxeq_fs__0;
  wire [5:0]rxeq_lf;
  wire \rxeq_lf[5]_i_1__0_n_0 ;
  wire [5:0]rxeq_lf__0;
  wire [5:0]rxeq_lffs_reg1;
  wire [5:0]rxeq_lffs_reg2;
  wire rxeq_new_txcoeff_req_reg_n_0;
  wire \rxeq_preset[0]_i_1__0_n_0 ;
  wire \rxeq_preset[1]_i_1__0_n_0 ;
  wire \rxeq_preset[2]_i_1__0_n_0 ;
  wire \rxeq_preset[2]_i_2__0_n_0 ;
  wire [2:0]rxeq_preset__0;
  wire [2:0]rxeq_preset_reg1;
  wire [2:0]rxeq_preset_reg2;
  wire rxeq_preset_valid;
  wire rxeq_preset_valid_reg_n_0;
  wire rxeq_scan_i_n_0;
  wire rxeq_scan_i_n_1;
  wire rxeq_scan_i_n_2;
  wire rxeq_scan_i_n_3;
  wire rxeq_scan_i_n_4;
  wire rxeq_scan_i_n_5;
  wire [17:0]rxeq_txcoeff;
  wire [5:0]rxeq_txcoeff__0;
  wire \rxeq_txcoeff_reg_n_0_[10] ;
  wire \rxeq_txcoeff_reg_n_0_[11] ;
  wire \rxeq_txcoeff_reg_n_0_[12] ;
  wire \rxeq_txcoeff_reg_n_0_[13] ;
  wire \rxeq_txcoeff_reg_n_0_[14] ;
  wire \rxeq_txcoeff_reg_n_0_[15] ;
  wire \rxeq_txcoeff_reg_n_0_[16] ;
  wire \rxeq_txcoeff_reg_n_0_[17] ;
  wire \rxeq_txcoeff_reg_n_0_[6] ;
  wire \rxeq_txcoeff_reg_n_0_[7] ;
  wire \rxeq_txcoeff_reg_n_0_[8] ;
  wire \rxeq_txcoeff_reg_n_0_[9] ;
  wire [3:0]rxeq_txpreset;
  wire \rxeq_txpreset[3]_i_1__0_n_0 ;
  wire [3:0]rxeq_txpreset__0;
  wire [3:0]rxeq_txpreset_reg1;
  wire [3:0]rxeq_txpreset_reg2;
  wire rxeq_user_en_reg1;
  wire rxeq_user_en_reg2;
  wire rxeq_user_mode_reg1;
  wire rxeq_user_mode_reg2;
  wire [17:0]rxeq_user_txcoeff_reg1;
  wire [17:0]rxeq_user_txcoeff_reg2;
  wire [1:0]txeq_control_reg1;
  wire [1:0]txeq_control_reg2;
  wire [5:0]txeq_deemph_reg1;
  wire [5:0]txeq_deemph_reg2;
  wire \txeq_preset[0]_i_1__0_n_0 ;
  wire \txeq_preset[10]_i_1__0_n_0 ;
  wire \txeq_preset[11]_i_1__0_n_0 ;
  wire \txeq_preset[12]_i_1__0_n_0 ;
  wire \txeq_preset[13]_i_1__0_n_0 ;
  wire \txeq_preset[14]_i_1__0_n_0 ;
  wire \txeq_preset[15]_i_1__0_n_0 ;
  wire \txeq_preset[16]_i_1__0_n_0 ;
  wire \txeq_preset[17]_i_1__5_n_0 ;
  wire \txeq_preset[17]_i_2__0_n_0 ;
  wire \txeq_preset[1]_i_1__0_n_0 ;
  wire \txeq_preset[2]_i_1__0_n_0 ;
  wire \txeq_preset[3]_i_1__0_n_0 ;
  wire \txeq_preset[7]_i_1__0_n_0 ;
  wire \txeq_preset[8]_i_1__0_n_0 ;
  wire \txeq_preset[9]_i_1__0_n_0 ;
  wire txeq_preset_done;
  wire [3:0]txeq_preset_reg1;
  wire [3:0]txeq_preset_reg2;
  wire \txeq_preset_reg_n_0_[0] ;
  wire \txeq_preset_reg_n_0_[10] ;
  wire \txeq_preset_reg_n_0_[11] ;
  wire \txeq_preset_reg_n_0_[12] ;
  wire \txeq_preset_reg_n_0_[13] ;
  wire \txeq_preset_reg_n_0_[14] ;
  wire \txeq_preset_reg_n_0_[15] ;
  wire \txeq_preset_reg_n_0_[16] ;
  wire \txeq_preset_reg_n_0_[17] ;
  wire \txeq_preset_reg_n_0_[1] ;
  wire \txeq_preset_reg_n_0_[2] ;
  wire \txeq_preset_reg_n_0_[3] ;
  wire \txeq_preset_reg_n_0_[4] ;
  wire \txeq_preset_reg_n_0_[5] ;
  wire \txeq_preset_reg_n_0_[6] ;
  wire \txeq_preset_reg_n_0_[7] ;
  wire \txeq_preset_reg_n_0_[8] ;
  wire \txeq_preset_reg_n_0_[9] ;
  wire \txeq_txcoeff[0]_i_1__0_n_0 ;
  wire \txeq_txcoeff[0]_i_2__0_n_0 ;
  wire \txeq_txcoeff[10]_i_1__0_n_0 ;
  wire \txeq_txcoeff[10]_i_2__0_n_0 ;
  wire \txeq_txcoeff[11]_i_1__0_n_0 ;
  wire \txeq_txcoeff[11]_i_2__0_n_0 ;
  wire \txeq_txcoeff[12]_i_1__0_n_0 ;
  wire \txeq_txcoeff[12]_i_2__0_n_0 ;
  wire \txeq_txcoeff[13]_i_1__0_n_0 ;
  wire \txeq_txcoeff[13]_i_2__0_n_0 ;
  wire \txeq_txcoeff[14]_i_1__0_n_0 ;
  wire \txeq_txcoeff[14]_i_2__0_n_0 ;
  wire \txeq_txcoeff[15]_i_1__0_n_0 ;
  wire \txeq_txcoeff[15]_i_2__0_n_0 ;
  wire \txeq_txcoeff[16]_i_1__0_n_0 ;
  wire \txeq_txcoeff[16]_i_2__0_n_0 ;
  wire \txeq_txcoeff[17]_i_1__0_n_0 ;
  wire \txeq_txcoeff[17]_i_2__0_n_0 ;
  wire \txeq_txcoeff[18]_i_1__0_n_0 ;
  wire \txeq_txcoeff[18]_i_2__0_n_0 ;
  wire \txeq_txcoeff[18]_i_3__0_n_0 ;
  wire \txeq_txcoeff[1]_i_1__0_n_0 ;
  wire \txeq_txcoeff[1]_i_2__0_n_0 ;
  wire \txeq_txcoeff[2]_i_1__0_n_0 ;
  wire \txeq_txcoeff[2]_i_2__0_n_0 ;
  wire \txeq_txcoeff[3]_i_1__0_n_0 ;
  wire \txeq_txcoeff[3]_i_2__0_n_0 ;
  wire \txeq_txcoeff[4]_i_1__0_n_0 ;
  wire \txeq_txcoeff[4]_i_2__0_n_0 ;
  wire \txeq_txcoeff[5]_i_1__0_n_0 ;
  wire \txeq_txcoeff[5]_i_2__0_n_0 ;
  wire \txeq_txcoeff[6]_i_1__0_n_0 ;
  wire \txeq_txcoeff[6]_i_2__0_n_0 ;
  wire \txeq_txcoeff[7]_i_1__0_n_0 ;
  wire \txeq_txcoeff[7]_i_2__0_n_0 ;
  wire \txeq_txcoeff[8]_i_1__0_n_0 ;
  wire \txeq_txcoeff[8]_i_2__0_n_0 ;
  wire \txeq_txcoeff[9]_i_1__0_n_0 ;
  wire \txeq_txcoeff[9]_i_2__0_n_0 ;
  wire [1:0]txeq_txcoeff_cnt;
  wire \txeq_txcoeff_cnt_reg_n_0_[0] ;
  wire \txeq_txcoeff_cnt_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[0] ;
  wire \txeq_txcoeff_reg_n_0_[10] ;
  wire \txeq_txcoeff_reg_n_0_[11] ;
  wire \txeq_txcoeff_reg_n_0_[12] ;
  wire \txeq_txcoeff_reg_n_0_[13] ;
  wire \txeq_txcoeff_reg_n_0_[14] ;
  wire \txeq_txcoeff_reg_n_0_[15] ;
  wire \txeq_txcoeff_reg_n_0_[16] ;
  wire \txeq_txcoeff_reg_n_0_[17] ;
  wire \txeq_txcoeff_reg_n_0_[18] ;
  wire \txeq_txcoeff_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[2] ;
  wire \txeq_txcoeff_reg_n_0_[3] ;
  wire \txeq_txcoeff_reg_n_0_[4] ;
  wire \txeq_txcoeff_reg_n_0_[5] ;
  wire \txeq_txcoeff_reg_n_0_[6] ;
  wire \txeq_txcoeff_reg_n_0_[7] ;
  wire \txeq_txcoeff_reg_n_0_[8] ;
  wire \txeq_txcoeff_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'h000000FF10101050)) 
    \FSM_onehot_fsm_tx[1]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx[1]_i_2__0_n_0 ),
        .I3(txeq_control_reg2[0]),
        .I4(txeq_control_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[1]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_onehot_fsm_tx[1]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[1]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h20202F20)) 
    \FSM_onehot_fsm_tx[2]_i_1__0 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I4(txeq_preset_done),
        .O(\FSM_onehot_fsm_tx[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h45454545FF454545)) 
    \FSM_onehot_fsm_tx[3]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx[3]_i_2__0_n_0 ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(\FSM_onehot_fsm_tx[3]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_onehot_fsm_tx[3]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm_tx[3]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \FSM_onehot_fsm_tx[4]_i_1__0 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[4]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm_tx[5]_i_1__0 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \FSM_onehot_fsm_tx[6]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx[6]_i_2__0_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_tx[6]_i_3__0_n_0 ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBBBBBB8)) 
    \FSM_onehot_fsm_tx[6]_i_2__0 
       (.I0(txeq_preset_done),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[6]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_fsm_tx[6]_i_3__0 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .O(\FSM_onehot_fsm_tx[6]_i_3__0_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[1]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[2]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[3]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[4]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[5]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[6]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h838183C3)) 
    \FSM_sequential_fsm_rx[0]_i_2__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(rxeq_control_reg2[0]),
        .O(\FSM_sequential_fsm_rx[0]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFD000080)) 
    \FSM_sequential_fsm_rx[0]_i_3__0 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm_rx[0]_i_3__0_n_0 ));
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_fsm_rx[2]_i_2__0 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fsm_rx[2]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_fsm_rx[2]_i_3__0 
       (.I0(rxeq_control_reg2[0]),
        .I1(rxeq_control_reg2[1]),
        .O(\FSM_sequential_fsm_rx[2]_i_3__0_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_2),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_1),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_0),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_30__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .O(TXPOSTCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_31__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[16] ),
        .O(TXPOSTCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_32__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .O(TXPOSTCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_33__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .O(TXPOSTCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_34__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[13] ),
        .O(TXPOSTCURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_35__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[4] ),
        .O(TXPRECURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_36__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[3] ),
        .O(TXPRECURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_37__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[2] ),
        .O(TXPRECURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_38__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[1] ),
        .O(TXPRECURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_39__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[0] ),
        .O(TXPRECURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_40__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .O(TXMAINCURSOR[6]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_41__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .O(TXMAINCURSOR[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_42__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .O(TXMAINCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_43__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[9] ),
        .O(TXMAINCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_44__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[8] ),
        .O(TXMAINCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_45__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[7] ),
        .O(TXMAINCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_46__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[6] ),
        .O(TXMAINCURSOR[0]));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_4),
        .Q(USER_RXEQ_ADAPT_DONE),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_5),
        .Q(rxeq_adapt_done_reg_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04041C10)) 
    \rxeq_cnt[0]_i_1__0 
       (.I0(\rxeq_cnt_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_cnt[0]));
  LUT5 #(
    .INIT(32'h00424200)) 
    \rxeq_cnt[1]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[1] ),
        .I4(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[1]));
  LUT6 #(
    .INIT(64'h0042420042004200)) 
    \rxeq_cnt[2]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[2] ),
        .I4(\rxeq_cnt_reg_n_0_[1] ),
        .I5(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[2]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[0]),
        .Q(\rxeq_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[1]),
        .Q(\rxeq_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[2]),
        .Q(\rxeq_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[0]),
        .Q(rxeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[1]),
        .Q(rxeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[0]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_fs[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[1]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_fs[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[2]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_fs[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[3]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_fs[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[4]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_fs[4]));
  LUT4 #(
    .INIT(16'hC203)) 
    \rxeq_fs[5]_i_1__0 
       (.I0(rxeq_control_reg2[1]),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_fs[5]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[5]_i_2__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_fs[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[0]),
        .Q(rxeq_fs__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[1]),
        .Q(rxeq_fs__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[2]),
        .Q(rxeq_fs__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[3]),
        .Q(rxeq_fs__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[4]),
        .Q(rxeq_fs__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__0_n_0 ),
        .D(rxeq_fs[5]),
        .Q(rxeq_fs__0[5]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[0]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_lf[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[1]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_lf[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[2]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_lf[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[3]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_lf[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[4]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_lf[4]));
  LUT6 #(
    .INIT(64'hFF000000000080FF)) 
    \rxeq_lf[5]_i_1__0 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\rxeq_cnt_reg_n_0_[2] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I5(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_lf[5]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[5]_i_2__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_lf[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[0]),
        .Q(rxeq_lf__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[1]),
        .Q(rxeq_lf__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[2]),
        .Q(rxeq_lf__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[3]),
        .Q(rxeq_lf__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[4]),
        .Q(rxeq_lf__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__0_n_0 ),
        .D(rxeq_lf[5]),
        .Q(rxeq_lf__0[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[0]),
        .Q(rxeq_lffs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[1]),
        .Q(rxeq_lffs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[2]),
        .Q(rxeq_lffs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[3]),
        .Q(rxeq_lffs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[4]),
        .Q(rxeq_lffs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[5]),
        .Q(rxeq_lffs_reg2[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_new_txcoeff_req_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_3),
        .Q(rxeq_new_txcoeff_req_reg_n_0),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[0]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[0]),
        .I4(\rxeq_preset[2]_i_2__0_n_0 ),
        .I5(rxeq_preset__0[0]),
        .O(\rxeq_preset[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[1]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[1]),
        .I4(\rxeq_preset[2]_i_2__0_n_0 ),
        .I5(rxeq_preset__0[1]),
        .O(\rxeq_preset[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[2]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[2]),
        .I4(\rxeq_preset[2]_i_2__0_n_0 ),
        .I5(rxeq_preset__0[2]),
        .O(\rxeq_preset[2]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hF00400FF)) 
    \rxeq_preset[2]_i_2__0 
       (.I0(rxeq_control_reg2[1]),
        .I1(rxeq_control_reg2[0]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_preset[2]_i_2__0_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[0]),
        .Q(rxeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[1]),
        .Q(rxeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[2]),
        .Q(rxeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[0]_i_1__0_n_0 ),
        .Q(rxeq_preset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[1]_i_1__0_n_0 ),
        .Q(rxeq_preset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[2]_i_1__0_n_0 ),
        .Q(rxeq_preset__0[2]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h04)) 
    rxeq_preset_valid_i_1__0
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(rxeq_preset_valid));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_preset_valid_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid),
        .Q(rxeq_preset_valid_reg_n_0),
        .R(RST_CPLLRESET));
  PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_82 rxeq_scan_i
       (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}),
        .\FSM_sequential_fsm_rx_reg[0] (\FSM_sequential_fsm_rx[0]_i_2__0_n_0 ),
        .\FSM_sequential_fsm_rx_reg[2] ({\FSM_sequential_fsm_rx_reg_n_0_[2] ,\FSM_sequential_fsm_rx_reg_n_0_[1] ,\FSM_sequential_fsm_rx_reg_n_0_[0] }),
        .Q(rxeq_txpreset__0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE),
        .out(rxeq_control_reg2),
        .pclk_sel_reg(pclk_sel_reg),
        .rxeq_adapt_done_reg(rxeq_scan_i_n_4),
        .rxeq_adapt_done_reg_reg(rxeq_scan_i_n_5),
        .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_reg_n_0),
        .\rxeq_cnt_reg[1] (\FSM_sequential_fsm_rx[0]_i_3__0_n_0 ),
        .\rxeq_cnt_reg[1]_0 (\FSM_sequential_fsm_rx[2]_i_2__0_n_0 ),
        .\rxeq_control_reg2_reg[0] (\FSM_sequential_fsm_rx[2]_i_3__0_n_0 ),
        .\rxeq_fs_reg[5] (rxeq_fs__0),
        .\rxeq_lf_reg[5] (rxeq_lf__0),
        .rxeq_new_txcoeff_req_reg(rxeq_scan_i_n_3),
        .rxeq_new_txcoeff_req_reg_0(rxeq_new_txcoeff_req_reg_n_0),
        .\rxeq_preset_reg[2] (rxeq_preset__0),
        .rxeq_preset_valid_reg(rxeq_preset_valid_reg_n_0),
        .\rxeq_txcoeff_reg[17] ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,rxeq_txcoeff__0}));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[0]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[6] ),
        .O(rxeq_txcoeff[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[10]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[16] ),
        .O(rxeq_txcoeff[10]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[11]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[17] ),
        .O(rxeq_txcoeff[11]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[12]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[0]),
        .O(rxeq_txcoeff[12]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[13]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[1]),
        .O(rxeq_txcoeff[13]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[14]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[2]),
        .O(rxeq_txcoeff[14]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[15]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[3]),
        .O(rxeq_txcoeff[15]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[16]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[4]),
        .O(rxeq_txcoeff[16]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[17]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[5]),
        .O(rxeq_txcoeff[17]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[1]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[7] ),
        .O(rxeq_txcoeff[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[2]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[8] ),
        .O(rxeq_txcoeff[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[3]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[9] ),
        .O(rxeq_txcoeff[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[4]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[10] ),
        .O(rxeq_txcoeff[4]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[5]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[11] ),
        .O(rxeq_txcoeff[5]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[6]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[12] ),
        .O(rxeq_txcoeff[6]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[7]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[13] ),
        .O(rxeq_txcoeff[7]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[8]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[14] ),
        .O(rxeq_txcoeff[8]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[9]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[15] ),
        .O(rxeq_txcoeff[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[0]),
        .Q(rxeq_txcoeff__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[10]),
        .Q(\rxeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[11]),
        .Q(\rxeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[12]),
        .Q(\rxeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[13]),
        .Q(\rxeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[14]),
        .Q(\rxeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[15]),
        .Q(\rxeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[16]),
        .Q(\rxeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[17]),
        .Q(\rxeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[1]),
        .Q(rxeq_txcoeff__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[2]),
        .Q(rxeq_txcoeff__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[3]),
        .Q(rxeq_txcoeff__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[4]),
        .Q(rxeq_txcoeff__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[5]),
        .Q(rxeq_txcoeff__0[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[6]),
        .Q(\rxeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[7]),
        .Q(\rxeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[8]),
        .Q(\rxeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txcoeff[9]),
        .Q(\rxeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[0]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[0]),
        .O(rxeq_txpreset[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[1]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[1]),
        .O(rxeq_txpreset[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[2]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[2]),
        .O(rxeq_txpreset[2]));
  LUT4 #(
    .INIT(16'hF405)) 
    \rxeq_txpreset[3]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_txpreset[3]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[3]_i_2__0 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[3]),
        .O(rxeq_txpreset[3]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[0]),
        .Q(rxeq_txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[1]),
        .Q(rxeq_txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[2]),
        .Q(rxeq_txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[3]),
        .Q(rxeq_txpreset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txpreset[0]),
        .Q(rxeq_txpreset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txpreset[1]),
        .Q(rxeq_txpreset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txpreset[2]),
        .Q(rxeq_txpreset__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__0_n_0 ),
        .D(rxeq_txpreset[3]),
        .Q(rxeq_txpreset__0[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_en_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_en_reg1),
        .Q(rxeq_user_en_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_mode_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_mode_reg1),
        .Q(rxeq_user_mode_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[0]),
        .Q(rxeq_user_txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[10]),
        .Q(rxeq_user_txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[11]),
        .Q(rxeq_user_txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[12]),
        .Q(rxeq_user_txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[13]),
        .Q(rxeq_user_txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[14]),
        .Q(rxeq_user_txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[15]),
        .Q(rxeq_user_txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[16]),
        .Q(rxeq_user_txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[17]),
        .Q(rxeq_user_txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[1]),
        .Q(rxeq_user_txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[2]),
        .Q(rxeq_user_txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[3]),
        .Q(rxeq_user_txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[4]),
        .Q(rxeq_user_txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[5]),
        .Q(rxeq_user_txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[6]),
        .Q(rxeq_user_txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[7]),
        .Q(rxeq_user_txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[8]),
        .Q(rxeq_user_txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[9]),
        .Q(rxeq_user_txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[0]),
        .Q(txeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[1]),
        .Q(txeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[0]),
        .Q(txeq_deemph_reg2[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[1]),
        .Q(txeq_deemph_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[2]),
        .Q(txeq_deemph_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[3]),
        .Q(txeq_deemph_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[4]),
        .Q(txeq_deemph_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[5]),
        .Q(txeq_deemph_reg2[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00001000)) 
    \txeq_preset[0]_i_1__0 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hAEABBABB)) 
    \txeq_preset[10]_i_1__0 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[10]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hAEAABABB)) 
    \txeq_preset[11]_i_1__0 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[11]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00001574)) 
    \txeq_preset[12]_i_1__0 
       (.I0(txeq_preset_reg2[3]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[12]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[13]_i_1__0 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[13]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000410)) 
    \txeq_preset[14]_i_1__0 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[14]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hAAAB)) 
    \txeq_preset[15]_i_1__0 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .O(\txeq_preset[15]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h0014)) 
    \txeq_preset[16]_i_1__0 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[16]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \txeq_preset[17]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(RST_CPLLRESET),
        .O(\txeq_preset[17]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hAAEABABB)) 
    \txeq_preset[17]_i_2__0 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[17]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[1]_i_1__0 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00C8)) 
    \txeq_preset[2]_i_1__0 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[2]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00003424)) 
    \txeq_preset[3]_i_1__0 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[3]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000408)) 
    \txeq_preset[7]_i_1__0 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[7]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hAAAEBBFB)) 
    \txeq_preset[8]_i_1__0 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[8]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hAEAEBABB)) 
    \txeq_preset[9]_i_1__0 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[9]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    txeq_preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .Q(txeq_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[0]),
        .Q(txeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[1]),
        .Q(txeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[2]),
        .Q(txeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[3]),
        .Q(txeq_preset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[0]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[10]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[11]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[12]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[13]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[14]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[15]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[16]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[17]_i_2__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[1]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[2]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[3]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[7]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[8]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__5_n_0 ),
        .D(\txeq_preset[9]_i_1__0_n_0 ),
        .Q(\txeq_preset_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[0]_i_1__0 
       (.I0(\txeq_txcoeff_reg_n_0_[6] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\txeq_preset_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[0]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hAA208A00)) 
    \txeq_txcoeff[0]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .O(\txeq_txcoeff[0]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[10]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[10] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[9] ),
        .I4(\txeq_txcoeff[10]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[10]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[10]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[16] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[10]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[11]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[11] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[10] ),
        .I4(\txeq_txcoeff[11]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[11]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[11]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[18] ),
        .I2(\txeq_txcoeff_reg_n_0_[17] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[11]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[12]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[11] ),
        .I4(\txeq_txcoeff[12]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[12]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[12]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[0]),
        .I2(\txeq_txcoeff_reg_n_0_[18] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[12]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[13]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[13] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[12] ),
        .I4(\txeq_txcoeff[13]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[13]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[13]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[1]),
        .I2(txeq_deemph_reg2[0]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[13]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[14]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[14] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[13] ),
        .I4(\txeq_txcoeff[14]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[14]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[14]_i_2__0 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[14]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[15]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[15] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[14] ),
        .I4(\txeq_txcoeff[15]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[15]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[15]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[3]),
        .I2(txeq_deemph_reg2[2]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[15]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[16]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[16] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[15] ),
        .I4(\txeq_txcoeff[16]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[16]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[16]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[4]),
        .I2(txeq_deemph_reg2[3]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[16]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[17]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[17] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[16] ),
        .I4(\txeq_txcoeff[17]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[17]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[17]_i_2__0 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[4]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[17]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h5557FF5755575557)) 
    \txeq_txcoeff[18]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx[1]_i_2__0_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[0]),
        .I5(txeq_control_reg2[1]),
        .O(\txeq_txcoeff[18]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \txeq_txcoeff[18]_i_2__0 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\txeq_txcoeff[18]_i_3__0_n_0 ),
        .O(\txeq_txcoeff[18]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hF888F8F888888888)) 
    \txeq_txcoeff[18]_i_3__0 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(txeq_deemph_reg2[5]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[18]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[1]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[1]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[1]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[1]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[2]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[1] ),
        .I4(\txeq_txcoeff[2]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[2]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[8] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[2]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[3]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[2] ),
        .I4(\txeq_txcoeff[3]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[3]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .I2(\txeq_txcoeff_reg_n_0_[9] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[3]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[4]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[3] ),
        .I4(\txeq_txcoeff[4]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[4]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .I2(\txeq_txcoeff_reg_n_0_[10] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[4]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[5]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[5] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[4] ),
        .I4(\txeq_txcoeff[5]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[5]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .I2(\txeq_txcoeff_reg_n_0_[11] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[5]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[6]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[5] ),
        .I4(\txeq_txcoeff[6]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[6]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[12] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[6]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[7]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[7] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff[7]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[7]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[7]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .I2(\txeq_txcoeff_reg_n_0_[13] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[7]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[8]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[8] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[7] ),
        .I4(\txeq_txcoeff[8]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[8]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[8]_i_2__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .I2(\txeq_txcoeff_reg_n_0_[14] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[8]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[9]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[9] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[8] ),
        .I4(\txeq_txcoeff[9]_i_2__0_n_0 ),
        .O(\txeq_txcoeff[9]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[9]_i_2__0 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[15] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[9]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h4444F444)) 
    \txeq_txcoeff_cnt[0]_i_1__0 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(txeq_control_reg2[1]),
        .I4(txeq_control_reg2[0]),
        .O(txeq_txcoeff_cnt[0]));
  LUT3 #(
    .INIT(8'h28)) 
    \txeq_txcoeff_cnt[1]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(txeq_txcoeff_cnt[1]));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[0]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[1]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[0]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[10]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[11]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[12]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[13]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[14]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[15]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[16]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[17]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[18] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[18]_i_2__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[1]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[2]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[3]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[4]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[5]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[6]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[7]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[8]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__0_n_0 ),
        .D(\txeq_txcoeff[9]_i_1__0_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_eq" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_37
   (TXPRECURSOR,
    TXMAINCURSOR,
    TXPOSTCURSOR,
    USER_RXEQ_ADAPT_DONE,
    RST_CPLLRESET,
    pclk_sel_reg,
    rate_gen3);
  output [4:0]TXPRECURSOR;
  output [6:0]TXMAINCURSOR;
  output [4:0]TXPOSTCURSOR;
  output USER_RXEQ_ADAPT_DONE;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]rate_gen3;

  wire \FSM_onehot_fsm_tx[1]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm_tx[1]_i_2__1_n_0 ;
  wire \FSM_onehot_fsm_tx[2]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_2__1_n_0 ;
  wire \FSM_onehot_fsm_tx[4]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm_tx[5]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_2__1_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_3__1_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[4] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[5] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[6] ;
  wire \FSM_sequential_fsm_rx[0]_i_2__1_n_0 ;
  wire \FSM_sequential_fsm_rx[0]_i_3__1_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_2__1_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_3__1_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[2] ;
  wire RST_CPLLRESET;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_RXEQ_ADAPT_DONE;
  wire gen3_reg1;
  wire gen3_reg2;
  wire pclk_sel_reg;
  wire [0:0]rate_gen3;
  wire rxeq_adapt_done_reg_reg_n_0;
  wire [2:0]rxeq_cnt;
  wire \rxeq_cnt_reg_n_0_[0] ;
  wire \rxeq_cnt_reg_n_0_[1] ;
  wire \rxeq_cnt_reg_n_0_[2] ;
  wire [1:0]rxeq_control_reg1;
  wire [1:0]rxeq_control_reg2;
  wire [5:0]rxeq_fs;
  wire \rxeq_fs[5]_i_1__1_n_0 ;
  wire [5:0]rxeq_fs__0;
  wire [5:0]rxeq_lf;
  wire \rxeq_lf[5]_i_1__1_n_0 ;
  wire [5:0]rxeq_lf__0;
  wire [5:0]rxeq_lffs_reg1;
  wire [5:0]rxeq_lffs_reg2;
  wire rxeq_new_txcoeff_req_reg_n_0;
  wire \rxeq_preset[0]_i_1__1_n_0 ;
  wire \rxeq_preset[1]_i_1__1_n_0 ;
  wire \rxeq_preset[2]_i_1__1_n_0 ;
  wire \rxeq_preset[2]_i_2__1_n_0 ;
  wire [2:0]rxeq_preset__0;
  wire [2:0]rxeq_preset_reg1;
  wire [2:0]rxeq_preset_reg2;
  wire rxeq_preset_valid;
  wire rxeq_preset_valid_reg_n_0;
  wire rxeq_scan_i_n_0;
  wire rxeq_scan_i_n_1;
  wire rxeq_scan_i_n_2;
  wire rxeq_scan_i_n_3;
  wire rxeq_scan_i_n_4;
  wire rxeq_scan_i_n_5;
  wire [17:0]rxeq_txcoeff;
  wire [5:0]rxeq_txcoeff__0;
  wire \rxeq_txcoeff_reg_n_0_[10] ;
  wire \rxeq_txcoeff_reg_n_0_[11] ;
  wire \rxeq_txcoeff_reg_n_0_[12] ;
  wire \rxeq_txcoeff_reg_n_0_[13] ;
  wire \rxeq_txcoeff_reg_n_0_[14] ;
  wire \rxeq_txcoeff_reg_n_0_[15] ;
  wire \rxeq_txcoeff_reg_n_0_[16] ;
  wire \rxeq_txcoeff_reg_n_0_[17] ;
  wire \rxeq_txcoeff_reg_n_0_[6] ;
  wire \rxeq_txcoeff_reg_n_0_[7] ;
  wire \rxeq_txcoeff_reg_n_0_[8] ;
  wire \rxeq_txcoeff_reg_n_0_[9] ;
  wire [3:0]rxeq_txpreset;
  wire \rxeq_txpreset[3]_i_1__1_n_0 ;
  wire [3:0]rxeq_txpreset__0;
  wire [3:0]rxeq_txpreset_reg1;
  wire [3:0]rxeq_txpreset_reg2;
  wire rxeq_user_en_reg1;
  wire rxeq_user_en_reg2;
  wire rxeq_user_mode_reg1;
  wire rxeq_user_mode_reg2;
  wire [17:0]rxeq_user_txcoeff_reg1;
  wire [17:0]rxeq_user_txcoeff_reg2;
  wire [1:0]txeq_control_reg1;
  wire [1:0]txeq_control_reg2;
  wire [5:0]txeq_deemph_reg1;
  wire [5:0]txeq_deemph_reg2;
  wire \txeq_preset[0]_i_1__1_n_0 ;
  wire \txeq_preset[10]_i_1__1_n_0 ;
  wire \txeq_preset[11]_i_1__1_n_0 ;
  wire \txeq_preset[12]_i_1__1_n_0 ;
  wire \txeq_preset[13]_i_1__1_n_0 ;
  wire \txeq_preset[14]_i_1__1_n_0 ;
  wire \txeq_preset[15]_i_1__1_n_0 ;
  wire \txeq_preset[16]_i_1__1_n_0 ;
  wire \txeq_preset[17]_i_1__4_n_0 ;
  wire \txeq_preset[17]_i_2__1_n_0 ;
  wire \txeq_preset[1]_i_1__1_n_0 ;
  wire \txeq_preset[2]_i_1__1_n_0 ;
  wire \txeq_preset[3]_i_1__1_n_0 ;
  wire \txeq_preset[7]_i_1__1_n_0 ;
  wire \txeq_preset[8]_i_1__1_n_0 ;
  wire \txeq_preset[9]_i_1__1_n_0 ;
  wire txeq_preset_done;
  wire [3:0]txeq_preset_reg1;
  wire [3:0]txeq_preset_reg2;
  wire \txeq_preset_reg_n_0_[0] ;
  wire \txeq_preset_reg_n_0_[10] ;
  wire \txeq_preset_reg_n_0_[11] ;
  wire \txeq_preset_reg_n_0_[12] ;
  wire \txeq_preset_reg_n_0_[13] ;
  wire \txeq_preset_reg_n_0_[14] ;
  wire \txeq_preset_reg_n_0_[15] ;
  wire \txeq_preset_reg_n_0_[16] ;
  wire \txeq_preset_reg_n_0_[17] ;
  wire \txeq_preset_reg_n_0_[1] ;
  wire \txeq_preset_reg_n_0_[2] ;
  wire \txeq_preset_reg_n_0_[3] ;
  wire \txeq_preset_reg_n_0_[4] ;
  wire \txeq_preset_reg_n_0_[5] ;
  wire \txeq_preset_reg_n_0_[6] ;
  wire \txeq_preset_reg_n_0_[7] ;
  wire \txeq_preset_reg_n_0_[8] ;
  wire \txeq_preset_reg_n_0_[9] ;
  wire \txeq_txcoeff[0]_i_1__1_n_0 ;
  wire \txeq_txcoeff[0]_i_2__1_n_0 ;
  wire \txeq_txcoeff[10]_i_1__1_n_0 ;
  wire \txeq_txcoeff[10]_i_2__1_n_0 ;
  wire \txeq_txcoeff[11]_i_1__1_n_0 ;
  wire \txeq_txcoeff[11]_i_2__1_n_0 ;
  wire \txeq_txcoeff[12]_i_1__1_n_0 ;
  wire \txeq_txcoeff[12]_i_2__1_n_0 ;
  wire \txeq_txcoeff[13]_i_1__1_n_0 ;
  wire \txeq_txcoeff[13]_i_2__1_n_0 ;
  wire \txeq_txcoeff[14]_i_1__1_n_0 ;
  wire \txeq_txcoeff[14]_i_2__1_n_0 ;
  wire \txeq_txcoeff[15]_i_1__1_n_0 ;
  wire \txeq_txcoeff[15]_i_2__1_n_0 ;
  wire \txeq_txcoeff[16]_i_1__1_n_0 ;
  wire \txeq_txcoeff[16]_i_2__1_n_0 ;
  wire \txeq_txcoeff[17]_i_1__1_n_0 ;
  wire \txeq_txcoeff[17]_i_2__1_n_0 ;
  wire \txeq_txcoeff[18]_i_1__1_n_0 ;
  wire \txeq_txcoeff[18]_i_2__1_n_0 ;
  wire \txeq_txcoeff[18]_i_3__1_n_0 ;
  wire \txeq_txcoeff[1]_i_1__1_n_0 ;
  wire \txeq_txcoeff[1]_i_2__1_n_0 ;
  wire \txeq_txcoeff[2]_i_1__1_n_0 ;
  wire \txeq_txcoeff[2]_i_2__1_n_0 ;
  wire \txeq_txcoeff[3]_i_1__1_n_0 ;
  wire \txeq_txcoeff[3]_i_2__1_n_0 ;
  wire \txeq_txcoeff[4]_i_1__1_n_0 ;
  wire \txeq_txcoeff[4]_i_2__1_n_0 ;
  wire \txeq_txcoeff[5]_i_1__1_n_0 ;
  wire \txeq_txcoeff[5]_i_2__1_n_0 ;
  wire \txeq_txcoeff[6]_i_1__1_n_0 ;
  wire \txeq_txcoeff[6]_i_2__1_n_0 ;
  wire \txeq_txcoeff[7]_i_1__1_n_0 ;
  wire \txeq_txcoeff[7]_i_2__1_n_0 ;
  wire \txeq_txcoeff[8]_i_1__1_n_0 ;
  wire \txeq_txcoeff[8]_i_2__1_n_0 ;
  wire \txeq_txcoeff[9]_i_1__1_n_0 ;
  wire \txeq_txcoeff[9]_i_2__1_n_0 ;
  wire [1:0]txeq_txcoeff_cnt;
  wire \txeq_txcoeff_cnt_reg_n_0_[0] ;
  wire \txeq_txcoeff_cnt_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[0] ;
  wire \txeq_txcoeff_reg_n_0_[10] ;
  wire \txeq_txcoeff_reg_n_0_[11] ;
  wire \txeq_txcoeff_reg_n_0_[12] ;
  wire \txeq_txcoeff_reg_n_0_[13] ;
  wire \txeq_txcoeff_reg_n_0_[14] ;
  wire \txeq_txcoeff_reg_n_0_[15] ;
  wire \txeq_txcoeff_reg_n_0_[16] ;
  wire \txeq_txcoeff_reg_n_0_[17] ;
  wire \txeq_txcoeff_reg_n_0_[18] ;
  wire \txeq_txcoeff_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[2] ;
  wire \txeq_txcoeff_reg_n_0_[3] ;
  wire \txeq_txcoeff_reg_n_0_[4] ;
  wire \txeq_txcoeff_reg_n_0_[5] ;
  wire \txeq_txcoeff_reg_n_0_[6] ;
  wire \txeq_txcoeff_reg_n_0_[7] ;
  wire \txeq_txcoeff_reg_n_0_[8] ;
  wire \txeq_txcoeff_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'h000000FF10101050)) 
    \FSM_onehot_fsm_tx[1]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx[1]_i_2__1_n_0 ),
        .I3(txeq_control_reg2[0]),
        .I4(txeq_control_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[1]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_onehot_fsm_tx[1]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[1]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h20202F20)) 
    \FSM_onehot_fsm_tx[2]_i_1__1 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I4(txeq_preset_done),
        .O(\FSM_onehot_fsm_tx[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h45454545FF454545)) 
    \FSM_onehot_fsm_tx[3]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx[3]_i_2__1_n_0 ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(\FSM_onehot_fsm_tx[3]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_onehot_fsm_tx[3]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm_tx[3]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \FSM_onehot_fsm_tx[4]_i_1__1 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[4]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm_tx[5]_i_1__1 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[5]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \FSM_onehot_fsm_tx[6]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx[6]_i_2__1_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_tx[6]_i_3__1_n_0 ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[6]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBBBBBB8)) 
    \FSM_onehot_fsm_tx[6]_i_2__1 
       (.I0(txeq_preset_done),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[6]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_fsm_tx[6]_i_3__1 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .O(\FSM_onehot_fsm_tx[6]_i_3__1_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[1]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[2]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[3]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[4]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[5]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[6]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h838183C3)) 
    \FSM_sequential_fsm_rx[0]_i_2__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(rxeq_control_reg2[0]),
        .O(\FSM_sequential_fsm_rx[0]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFD000080)) 
    \FSM_sequential_fsm_rx[0]_i_3__1 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm_rx[0]_i_3__1_n_0 ));
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_fsm_rx[2]_i_2__1 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fsm_rx[2]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_fsm_rx[2]_i_3__1 
       (.I0(rxeq_control_reg2[0]),
        .I1(rxeq_control_reg2[1]),
        .O(\FSM_sequential_fsm_rx[2]_i_3__1_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_2),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_1),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_0),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_31__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .O(TXPOSTCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_32__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[16] ),
        .O(TXPOSTCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_33__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .O(TXPOSTCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_34__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .O(TXPOSTCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_35__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[13] ),
        .O(TXPOSTCURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_36__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[4] ),
        .O(TXPRECURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_37__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[3] ),
        .O(TXPRECURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_38__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[2] ),
        .O(TXPRECURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_39__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[1] ),
        .O(TXPRECURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_40__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[0] ),
        .O(TXPRECURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_41__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .O(TXMAINCURSOR[6]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_42__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .O(TXMAINCURSOR[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_43__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .O(TXMAINCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_44__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[9] ),
        .O(TXMAINCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_45__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[8] ),
        .O(TXMAINCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_46__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[7] ),
        .O(TXMAINCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_47 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[6] ),
        .O(TXMAINCURSOR[0]));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_4),
        .Q(USER_RXEQ_ADAPT_DONE),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_5),
        .Q(rxeq_adapt_done_reg_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04041C10)) 
    \rxeq_cnt[0]_i_1__1 
       (.I0(\rxeq_cnt_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_cnt[0]));
  LUT5 #(
    .INIT(32'h00424200)) 
    \rxeq_cnt[1]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[1] ),
        .I4(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[1]));
  LUT6 #(
    .INIT(64'h0042420042004200)) 
    \rxeq_cnt[2]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[2] ),
        .I4(\rxeq_cnt_reg_n_0_[1] ),
        .I5(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[2]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[0]),
        .Q(\rxeq_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[1]),
        .Q(\rxeq_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[2]),
        .Q(\rxeq_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[0]),
        .Q(rxeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[1]),
        .Q(rxeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[0]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_fs[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[1]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_fs[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[2]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_fs[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[3]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_fs[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[4]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_fs[4]));
  LUT4 #(
    .INIT(16'hC203)) 
    \rxeq_fs[5]_i_1__1 
       (.I0(rxeq_control_reg2[1]),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_fs[5]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[5]_i_2__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_fs[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__1_n_0 ),
        .D(rxeq_fs[0]),
        .Q(rxeq_fs__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__1_n_0 ),
        .D(rxeq_fs[1]),
        .Q(rxeq_fs__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__1_n_0 ),
        .D(rxeq_fs[2]),
        .Q(rxeq_fs__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__1_n_0 ),
        .D(rxeq_fs[3]),
        .Q(rxeq_fs__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__1_n_0 ),
        .D(rxeq_fs[4]),
        .Q(rxeq_fs__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__1_n_0 ),
        .D(rxeq_fs[5]),
        .Q(rxeq_fs__0[5]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[0]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_lf[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[1]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_lf[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[2]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_lf[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[3]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_lf[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[4]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_lf[4]));
  LUT6 #(
    .INIT(64'hFF000000000080FF)) 
    \rxeq_lf[5]_i_1__1 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\rxeq_cnt_reg_n_0_[2] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I5(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_lf[5]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[5]_i_2__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_lf[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__1_n_0 ),
        .D(rxeq_lf[0]),
        .Q(rxeq_lf__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__1_n_0 ),
        .D(rxeq_lf[1]),
        .Q(rxeq_lf__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__1_n_0 ),
        .D(rxeq_lf[2]),
        .Q(rxeq_lf__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__1_n_0 ),
        .D(rxeq_lf[3]),
        .Q(rxeq_lf__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__1_n_0 ),
        .D(rxeq_lf[4]),
        .Q(rxeq_lf__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__1_n_0 ),
        .D(rxeq_lf[5]),
        .Q(rxeq_lf__0[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[0]),
        .Q(rxeq_lffs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[1]),
        .Q(rxeq_lffs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[2]),
        .Q(rxeq_lffs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[3]),
        .Q(rxeq_lffs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[4]),
        .Q(rxeq_lffs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[5]),
        .Q(rxeq_lffs_reg2[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_new_txcoeff_req_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_3),
        .Q(rxeq_new_txcoeff_req_reg_n_0),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[0]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[0]),
        .I4(\rxeq_preset[2]_i_2__1_n_0 ),
        .I5(rxeq_preset__0[0]),
        .O(\rxeq_preset[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[1]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[1]),
        .I4(\rxeq_preset[2]_i_2__1_n_0 ),
        .I5(rxeq_preset__0[1]),
        .O(\rxeq_preset[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[2]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[2]),
        .I4(\rxeq_preset[2]_i_2__1_n_0 ),
        .I5(rxeq_preset__0[2]),
        .O(\rxeq_preset[2]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hF00400FF)) 
    \rxeq_preset[2]_i_2__1 
       (.I0(rxeq_control_reg2[1]),
        .I1(rxeq_control_reg2[0]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_preset[2]_i_2__1_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[0]),
        .Q(rxeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[1]),
        .Q(rxeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[2]),
        .Q(rxeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[0]_i_1__1_n_0 ),
        .Q(rxeq_preset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[1]_i_1__1_n_0 ),
        .Q(rxeq_preset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[2]_i_1__1_n_0 ),
        .Q(rxeq_preset__0[2]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h04)) 
    rxeq_preset_valid_i_1__1
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(rxeq_preset_valid));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_preset_valid_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid),
        .Q(rxeq_preset_valid_reg_n_0),
        .R(RST_CPLLRESET));
  PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_80 rxeq_scan_i
       (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}),
        .\FSM_sequential_fsm_rx_reg[0] (\FSM_sequential_fsm_rx[0]_i_2__1_n_0 ),
        .\FSM_sequential_fsm_rx_reg[2] ({\FSM_sequential_fsm_rx_reg_n_0_[2] ,\FSM_sequential_fsm_rx_reg_n_0_[1] ,\FSM_sequential_fsm_rx_reg_n_0_[0] }),
        .Q(rxeq_txpreset__0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE),
        .out(rxeq_control_reg2),
        .pclk_sel_reg(pclk_sel_reg),
        .rxeq_adapt_done_reg(rxeq_scan_i_n_4),
        .rxeq_adapt_done_reg_reg(rxeq_scan_i_n_5),
        .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_reg_n_0),
        .\rxeq_cnt_reg[1] (\FSM_sequential_fsm_rx[0]_i_3__1_n_0 ),
        .\rxeq_cnt_reg[1]_0 (\FSM_sequential_fsm_rx[2]_i_2__1_n_0 ),
        .\rxeq_control_reg2_reg[0] (\FSM_sequential_fsm_rx[2]_i_3__1_n_0 ),
        .\rxeq_fs_reg[5] (rxeq_fs__0),
        .\rxeq_lf_reg[5] (rxeq_lf__0),
        .rxeq_new_txcoeff_req_reg(rxeq_scan_i_n_3),
        .rxeq_new_txcoeff_req_reg_0(rxeq_new_txcoeff_req_reg_n_0),
        .\rxeq_preset_reg[2] (rxeq_preset__0),
        .rxeq_preset_valid_reg(rxeq_preset_valid_reg_n_0),
        .\rxeq_txcoeff_reg[17] ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,rxeq_txcoeff__0}));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[0]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[6] ),
        .O(rxeq_txcoeff[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[10]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[16] ),
        .O(rxeq_txcoeff[10]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[11]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[17] ),
        .O(rxeq_txcoeff[11]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[12]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[0]),
        .O(rxeq_txcoeff[12]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[13]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[1]),
        .O(rxeq_txcoeff[13]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[14]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[2]),
        .O(rxeq_txcoeff[14]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[15]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[3]),
        .O(rxeq_txcoeff[15]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[16]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[4]),
        .O(rxeq_txcoeff[16]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[17]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[5]),
        .O(rxeq_txcoeff[17]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[1]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[7] ),
        .O(rxeq_txcoeff[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[2]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[8] ),
        .O(rxeq_txcoeff[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[3]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[9] ),
        .O(rxeq_txcoeff[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[4]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[10] ),
        .O(rxeq_txcoeff[4]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[5]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[11] ),
        .O(rxeq_txcoeff[5]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[6]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[12] ),
        .O(rxeq_txcoeff[6]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[7]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[13] ),
        .O(rxeq_txcoeff[7]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[8]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[14] ),
        .O(rxeq_txcoeff[8]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[9]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[15] ),
        .O(rxeq_txcoeff[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[0]),
        .Q(rxeq_txcoeff__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[10]),
        .Q(\rxeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[11]),
        .Q(\rxeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[12]),
        .Q(\rxeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[13]),
        .Q(\rxeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[14]),
        .Q(\rxeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[15]),
        .Q(\rxeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[16]),
        .Q(\rxeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[17]),
        .Q(\rxeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[1]),
        .Q(rxeq_txcoeff__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[2]),
        .Q(rxeq_txcoeff__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[3]),
        .Q(rxeq_txcoeff__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[4]),
        .Q(rxeq_txcoeff__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[5]),
        .Q(rxeq_txcoeff__0[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[6]),
        .Q(\rxeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[7]),
        .Q(\rxeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[8]),
        .Q(\rxeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txcoeff[9]),
        .Q(\rxeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[0]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[0]),
        .O(rxeq_txpreset[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[1]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[1]),
        .O(rxeq_txpreset[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[2]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[2]),
        .O(rxeq_txpreset[2]));
  LUT4 #(
    .INIT(16'hF405)) 
    \rxeq_txpreset[3]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_txpreset[3]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[3]_i_2__1 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[3]),
        .O(rxeq_txpreset[3]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[0]),
        .Q(rxeq_txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[1]),
        .Q(rxeq_txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[2]),
        .Q(rxeq_txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[3]),
        .Q(rxeq_txpreset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txpreset[0]),
        .Q(rxeq_txpreset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txpreset[1]),
        .Q(rxeq_txpreset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txpreset[2]),
        .Q(rxeq_txpreset__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__1_n_0 ),
        .D(rxeq_txpreset[3]),
        .Q(rxeq_txpreset__0[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_en_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_en_reg1),
        .Q(rxeq_user_en_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_mode_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_mode_reg1),
        .Q(rxeq_user_mode_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[0]),
        .Q(rxeq_user_txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[10]),
        .Q(rxeq_user_txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[11]),
        .Q(rxeq_user_txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[12]),
        .Q(rxeq_user_txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[13]),
        .Q(rxeq_user_txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[14]),
        .Q(rxeq_user_txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[15]),
        .Q(rxeq_user_txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[16]),
        .Q(rxeq_user_txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[17]),
        .Q(rxeq_user_txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[1]),
        .Q(rxeq_user_txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[2]),
        .Q(rxeq_user_txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[3]),
        .Q(rxeq_user_txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[4]),
        .Q(rxeq_user_txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[5]),
        .Q(rxeq_user_txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[6]),
        .Q(rxeq_user_txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[7]),
        .Q(rxeq_user_txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[8]),
        .Q(rxeq_user_txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[9]),
        .Q(rxeq_user_txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[0]),
        .Q(txeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[1]),
        .Q(txeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[0]),
        .Q(txeq_deemph_reg2[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[1]),
        .Q(txeq_deemph_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[2]),
        .Q(txeq_deemph_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[3]),
        .Q(txeq_deemph_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[4]),
        .Q(txeq_deemph_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[5]),
        .Q(txeq_deemph_reg2[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00001000)) 
    \txeq_preset[0]_i_1__1 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hAEABBABB)) 
    \txeq_preset[10]_i_1__1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[10]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hAEAABABB)) 
    \txeq_preset[11]_i_1__1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[11]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00001574)) 
    \txeq_preset[12]_i_1__1 
       (.I0(txeq_preset_reg2[3]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[12]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[13]_i_1__1 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[13]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00000410)) 
    \txeq_preset[14]_i_1__1 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[14]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hAAAB)) 
    \txeq_preset[15]_i_1__1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .O(\txeq_preset[15]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0014)) 
    \txeq_preset[16]_i_1__1 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[16]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \txeq_preset[17]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(RST_CPLLRESET),
        .O(\txeq_preset[17]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hAAEABABB)) 
    \txeq_preset[17]_i_2__1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[17]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[1]_i_1__1 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h00C8)) 
    \txeq_preset[2]_i_1__1 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[2]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00003424)) 
    \txeq_preset[3]_i_1__1 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[3]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00000408)) 
    \txeq_preset[7]_i_1__1 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[7]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAEBBFB)) 
    \txeq_preset[8]_i_1__1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[8]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hAEAEBABB)) 
    \txeq_preset[9]_i_1__1 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[9]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    txeq_preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .Q(txeq_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[0]),
        .Q(txeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[1]),
        .Q(txeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[2]),
        .Q(txeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[3]),
        .Q(txeq_preset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[0]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[10]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[11]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[12]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[13]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[14]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[15]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[16]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[17]_i_2__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[1]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[2]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[3]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[7]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[8]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__4_n_0 ),
        .D(\txeq_preset[9]_i_1__1_n_0 ),
        .Q(\txeq_preset_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[0]_i_1__1 
       (.I0(\txeq_txcoeff_reg_n_0_[6] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\txeq_preset_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[0]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hAA208A00)) 
    \txeq_txcoeff[0]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .O(\txeq_txcoeff[0]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[10]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[10] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[9] ),
        .I4(\txeq_txcoeff[10]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[10]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[10]_i_2__1 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[16] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[10]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[11]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[11] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[10] ),
        .I4(\txeq_txcoeff[11]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[11]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[11]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[18] ),
        .I2(\txeq_txcoeff_reg_n_0_[17] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[11]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[12]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[11] ),
        .I4(\txeq_txcoeff[12]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[12]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[12]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[0]),
        .I2(\txeq_txcoeff_reg_n_0_[18] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[12]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[13]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[13] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[12] ),
        .I4(\txeq_txcoeff[13]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[13]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[13]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[1]),
        .I2(txeq_deemph_reg2[0]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[13]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[14]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[14] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[13] ),
        .I4(\txeq_txcoeff[14]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[14]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[14]_i_2__1 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[14]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[15]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[15] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[14] ),
        .I4(\txeq_txcoeff[15]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[15]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[15]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[3]),
        .I2(txeq_deemph_reg2[2]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[15]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[16]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[16] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[15] ),
        .I4(\txeq_txcoeff[16]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[16]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[16]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[4]),
        .I2(txeq_deemph_reg2[3]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[16]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[17]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[17] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[16] ),
        .I4(\txeq_txcoeff[17]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[17]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[17]_i_2__1 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[4]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[17]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h5557FF5755575557)) 
    \txeq_txcoeff[18]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx[1]_i_2__1_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[0]),
        .I5(txeq_control_reg2[1]),
        .O(\txeq_txcoeff[18]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \txeq_txcoeff[18]_i_2__1 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\txeq_txcoeff[18]_i_3__1_n_0 ),
        .O(\txeq_txcoeff[18]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hF888F8F888888888)) 
    \txeq_txcoeff[18]_i_3__1 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(txeq_deemph_reg2[5]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[18]_i_3__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[1]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[1]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[1]_i_2__1 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[1]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[2]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[1] ),
        .I4(\txeq_txcoeff[2]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[2]_i_2__1 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[8] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[2]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[3]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[2] ),
        .I4(\txeq_txcoeff[3]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[3]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .I2(\txeq_txcoeff_reg_n_0_[9] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[3]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[4]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[3] ),
        .I4(\txeq_txcoeff[4]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[4]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .I2(\txeq_txcoeff_reg_n_0_[10] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[4]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[5]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[5] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[4] ),
        .I4(\txeq_txcoeff[5]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[5]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[5]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .I2(\txeq_txcoeff_reg_n_0_[11] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[5]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[6]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[5] ),
        .I4(\txeq_txcoeff[6]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[6]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[6]_i_2__1 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[12] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[6]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[7]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[7] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff[7]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[7]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[7]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .I2(\txeq_txcoeff_reg_n_0_[13] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[7]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[8]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[8] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[7] ),
        .I4(\txeq_txcoeff[8]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[8]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[8]_i_2__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .I2(\txeq_txcoeff_reg_n_0_[14] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[8]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[9]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[9] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[8] ),
        .I4(\txeq_txcoeff[9]_i_2__1_n_0 ),
        .O(\txeq_txcoeff[9]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[9]_i_2__1 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[15] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[9]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h4444F444)) 
    \txeq_txcoeff_cnt[0]_i_1__1 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(txeq_control_reg2[1]),
        .I4(txeq_control_reg2[0]),
        .O(txeq_txcoeff_cnt[0]));
  LUT3 #(
    .INIT(8'h28)) 
    \txeq_txcoeff_cnt[1]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(txeq_txcoeff_cnt[1]));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[0]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[1]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[0]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[10]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[11]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[12]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[13]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[14]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[15]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[16]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[17]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[18] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[18]_i_2__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[1]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[2]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[3]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[4]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[5]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[6]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[7]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[8]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__1_n_0 ),
        .D(\txeq_txcoeff[9]_i_1__1_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_eq" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_43
   (TXPRECURSOR,
    TXMAINCURSOR,
    TXPOSTCURSOR,
    USER_RXEQ_ADAPT_DONE,
    RST_CPLLRESET,
    pclk_sel_reg,
    rate_gen3);
  output [4:0]TXPRECURSOR;
  output [6:0]TXMAINCURSOR;
  output [4:0]TXPOSTCURSOR;
  output USER_RXEQ_ADAPT_DONE;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]rate_gen3;

  wire \FSM_onehot_fsm_tx[1]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm_tx[1]_i_2__2_n_0 ;
  wire \FSM_onehot_fsm_tx[2]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_2__2_n_0 ;
  wire \FSM_onehot_fsm_tx[4]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm_tx[5]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_2__2_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_3__2_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[4] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[5] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[6] ;
  wire \FSM_sequential_fsm_rx[0]_i_2__2_n_0 ;
  wire \FSM_sequential_fsm_rx[0]_i_3__2_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_2__2_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_3__2_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[2] ;
  wire RST_CPLLRESET;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_RXEQ_ADAPT_DONE;
  wire gen3_reg1;
  wire gen3_reg2;
  wire pclk_sel_reg;
  wire [0:0]rate_gen3;
  wire rxeq_adapt_done_reg_reg_n_0;
  wire [2:0]rxeq_cnt;
  wire \rxeq_cnt_reg_n_0_[0] ;
  wire \rxeq_cnt_reg_n_0_[1] ;
  wire \rxeq_cnt_reg_n_0_[2] ;
  wire [1:0]rxeq_control_reg1;
  wire [1:0]rxeq_control_reg2;
  wire [5:0]rxeq_fs;
  wire \rxeq_fs[5]_i_1__2_n_0 ;
  wire [5:0]rxeq_fs__0;
  wire [5:0]rxeq_lf;
  wire \rxeq_lf[5]_i_1__2_n_0 ;
  wire [5:0]rxeq_lf__0;
  wire [5:0]rxeq_lffs_reg1;
  wire [5:0]rxeq_lffs_reg2;
  wire rxeq_new_txcoeff_req_reg_n_0;
  wire \rxeq_preset[0]_i_1__2_n_0 ;
  wire \rxeq_preset[1]_i_1__2_n_0 ;
  wire \rxeq_preset[2]_i_1__2_n_0 ;
  wire \rxeq_preset[2]_i_2__2_n_0 ;
  wire [2:0]rxeq_preset__0;
  wire [2:0]rxeq_preset_reg1;
  wire [2:0]rxeq_preset_reg2;
  wire rxeq_preset_valid;
  wire rxeq_preset_valid_reg_n_0;
  wire rxeq_scan_i_n_0;
  wire rxeq_scan_i_n_1;
  wire rxeq_scan_i_n_2;
  wire rxeq_scan_i_n_3;
  wire rxeq_scan_i_n_4;
  wire rxeq_scan_i_n_5;
  wire [17:0]rxeq_txcoeff;
  wire [5:0]rxeq_txcoeff__0;
  wire \rxeq_txcoeff_reg_n_0_[10] ;
  wire \rxeq_txcoeff_reg_n_0_[11] ;
  wire \rxeq_txcoeff_reg_n_0_[12] ;
  wire \rxeq_txcoeff_reg_n_0_[13] ;
  wire \rxeq_txcoeff_reg_n_0_[14] ;
  wire \rxeq_txcoeff_reg_n_0_[15] ;
  wire \rxeq_txcoeff_reg_n_0_[16] ;
  wire \rxeq_txcoeff_reg_n_0_[17] ;
  wire \rxeq_txcoeff_reg_n_0_[6] ;
  wire \rxeq_txcoeff_reg_n_0_[7] ;
  wire \rxeq_txcoeff_reg_n_0_[8] ;
  wire \rxeq_txcoeff_reg_n_0_[9] ;
  wire [3:0]rxeq_txpreset;
  wire \rxeq_txpreset[3]_i_1__2_n_0 ;
  wire [3:0]rxeq_txpreset__0;
  wire [3:0]rxeq_txpreset_reg1;
  wire [3:0]rxeq_txpreset_reg2;
  wire rxeq_user_en_reg1;
  wire rxeq_user_en_reg2;
  wire rxeq_user_mode_reg1;
  wire rxeq_user_mode_reg2;
  wire [17:0]rxeq_user_txcoeff_reg1;
  wire [17:0]rxeq_user_txcoeff_reg2;
  wire [1:0]txeq_control_reg1;
  wire [1:0]txeq_control_reg2;
  wire [5:0]txeq_deemph_reg1;
  wire [5:0]txeq_deemph_reg2;
  wire \txeq_preset[0]_i_1__2_n_0 ;
  wire \txeq_preset[10]_i_1__2_n_0 ;
  wire \txeq_preset[11]_i_1__2_n_0 ;
  wire \txeq_preset[12]_i_1__2_n_0 ;
  wire \txeq_preset[13]_i_1__2_n_0 ;
  wire \txeq_preset[14]_i_1__2_n_0 ;
  wire \txeq_preset[15]_i_1__2_n_0 ;
  wire \txeq_preset[16]_i_1__2_n_0 ;
  wire \txeq_preset[17]_i_1__3_n_0 ;
  wire \txeq_preset[17]_i_2__2_n_0 ;
  wire \txeq_preset[1]_i_1__2_n_0 ;
  wire \txeq_preset[2]_i_1__2_n_0 ;
  wire \txeq_preset[3]_i_1__2_n_0 ;
  wire \txeq_preset[7]_i_1__2_n_0 ;
  wire \txeq_preset[8]_i_1__2_n_0 ;
  wire \txeq_preset[9]_i_1__2_n_0 ;
  wire txeq_preset_done;
  wire [3:0]txeq_preset_reg1;
  wire [3:0]txeq_preset_reg2;
  wire \txeq_preset_reg_n_0_[0] ;
  wire \txeq_preset_reg_n_0_[10] ;
  wire \txeq_preset_reg_n_0_[11] ;
  wire \txeq_preset_reg_n_0_[12] ;
  wire \txeq_preset_reg_n_0_[13] ;
  wire \txeq_preset_reg_n_0_[14] ;
  wire \txeq_preset_reg_n_0_[15] ;
  wire \txeq_preset_reg_n_0_[16] ;
  wire \txeq_preset_reg_n_0_[17] ;
  wire \txeq_preset_reg_n_0_[1] ;
  wire \txeq_preset_reg_n_0_[2] ;
  wire \txeq_preset_reg_n_0_[3] ;
  wire \txeq_preset_reg_n_0_[4] ;
  wire \txeq_preset_reg_n_0_[5] ;
  wire \txeq_preset_reg_n_0_[6] ;
  wire \txeq_preset_reg_n_0_[7] ;
  wire \txeq_preset_reg_n_0_[8] ;
  wire \txeq_preset_reg_n_0_[9] ;
  wire \txeq_txcoeff[0]_i_1__2_n_0 ;
  wire \txeq_txcoeff[0]_i_2__2_n_0 ;
  wire \txeq_txcoeff[10]_i_1__2_n_0 ;
  wire \txeq_txcoeff[10]_i_2__2_n_0 ;
  wire \txeq_txcoeff[11]_i_1__2_n_0 ;
  wire \txeq_txcoeff[11]_i_2__2_n_0 ;
  wire \txeq_txcoeff[12]_i_1__2_n_0 ;
  wire \txeq_txcoeff[12]_i_2__2_n_0 ;
  wire \txeq_txcoeff[13]_i_1__2_n_0 ;
  wire \txeq_txcoeff[13]_i_2__2_n_0 ;
  wire \txeq_txcoeff[14]_i_1__2_n_0 ;
  wire \txeq_txcoeff[14]_i_2__2_n_0 ;
  wire \txeq_txcoeff[15]_i_1__2_n_0 ;
  wire \txeq_txcoeff[15]_i_2__2_n_0 ;
  wire \txeq_txcoeff[16]_i_1__2_n_0 ;
  wire \txeq_txcoeff[16]_i_2__2_n_0 ;
  wire \txeq_txcoeff[17]_i_1__2_n_0 ;
  wire \txeq_txcoeff[17]_i_2__2_n_0 ;
  wire \txeq_txcoeff[18]_i_1__2_n_0 ;
  wire \txeq_txcoeff[18]_i_2__2_n_0 ;
  wire \txeq_txcoeff[18]_i_3__2_n_0 ;
  wire \txeq_txcoeff[1]_i_1__2_n_0 ;
  wire \txeq_txcoeff[1]_i_2__2_n_0 ;
  wire \txeq_txcoeff[2]_i_1__2_n_0 ;
  wire \txeq_txcoeff[2]_i_2__2_n_0 ;
  wire \txeq_txcoeff[3]_i_1__2_n_0 ;
  wire \txeq_txcoeff[3]_i_2__2_n_0 ;
  wire \txeq_txcoeff[4]_i_1__2_n_0 ;
  wire \txeq_txcoeff[4]_i_2__2_n_0 ;
  wire \txeq_txcoeff[5]_i_1__2_n_0 ;
  wire \txeq_txcoeff[5]_i_2__2_n_0 ;
  wire \txeq_txcoeff[6]_i_1__2_n_0 ;
  wire \txeq_txcoeff[6]_i_2__2_n_0 ;
  wire \txeq_txcoeff[7]_i_1__2_n_0 ;
  wire \txeq_txcoeff[7]_i_2__2_n_0 ;
  wire \txeq_txcoeff[8]_i_1__2_n_0 ;
  wire \txeq_txcoeff[8]_i_2__2_n_0 ;
  wire \txeq_txcoeff[9]_i_1__2_n_0 ;
  wire \txeq_txcoeff[9]_i_2__2_n_0 ;
  wire [1:0]txeq_txcoeff_cnt;
  wire \txeq_txcoeff_cnt_reg_n_0_[0] ;
  wire \txeq_txcoeff_cnt_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[0] ;
  wire \txeq_txcoeff_reg_n_0_[10] ;
  wire \txeq_txcoeff_reg_n_0_[11] ;
  wire \txeq_txcoeff_reg_n_0_[12] ;
  wire \txeq_txcoeff_reg_n_0_[13] ;
  wire \txeq_txcoeff_reg_n_0_[14] ;
  wire \txeq_txcoeff_reg_n_0_[15] ;
  wire \txeq_txcoeff_reg_n_0_[16] ;
  wire \txeq_txcoeff_reg_n_0_[17] ;
  wire \txeq_txcoeff_reg_n_0_[18] ;
  wire \txeq_txcoeff_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[2] ;
  wire \txeq_txcoeff_reg_n_0_[3] ;
  wire \txeq_txcoeff_reg_n_0_[4] ;
  wire \txeq_txcoeff_reg_n_0_[5] ;
  wire \txeq_txcoeff_reg_n_0_[6] ;
  wire \txeq_txcoeff_reg_n_0_[7] ;
  wire \txeq_txcoeff_reg_n_0_[8] ;
  wire \txeq_txcoeff_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'h000000FF10101050)) 
    \FSM_onehot_fsm_tx[1]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx[1]_i_2__2_n_0 ),
        .I3(txeq_control_reg2[0]),
        .I4(txeq_control_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[1]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_onehot_fsm_tx[1]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[1]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'h20202F20)) 
    \FSM_onehot_fsm_tx[2]_i_1__2 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I4(txeq_preset_done),
        .O(\FSM_onehot_fsm_tx[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h45454545FF454545)) 
    \FSM_onehot_fsm_tx[3]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx[3]_i_2__2_n_0 ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(\FSM_onehot_fsm_tx[3]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_onehot_fsm_tx[3]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm_tx[3]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \FSM_onehot_fsm_tx[4]_i_1__2 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[4]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm_tx[5]_i_1__2 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[5]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \FSM_onehot_fsm_tx[6]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx[6]_i_2__2_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_tx[6]_i_3__2_n_0 ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[6]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBBBBBB8)) 
    \FSM_onehot_fsm_tx[6]_i_2__2 
       (.I0(txeq_preset_done),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[6]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_fsm_tx[6]_i_3__2 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .O(\FSM_onehot_fsm_tx[6]_i_3__2_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[1]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[2]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[3]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[4]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[5]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[6]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h838183C3)) 
    \FSM_sequential_fsm_rx[0]_i_2__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(rxeq_control_reg2[0]),
        .O(\FSM_sequential_fsm_rx[0]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFD000080)) 
    \FSM_sequential_fsm_rx[0]_i_3__2 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm_rx[0]_i_3__2_n_0 ));
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_fsm_rx[2]_i_2__2 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fsm_rx[2]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_fsm_rx[2]_i_3__2 
       (.I0(rxeq_control_reg2[0]),
        .I1(rxeq_control_reg2[1]),
        .O(\FSM_sequential_fsm_rx[2]_i_3__2_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_2),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_1),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_0),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_31__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .O(TXPOSTCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_32__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[16] ),
        .O(TXPOSTCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_33__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .O(TXPOSTCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_34__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .O(TXPOSTCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_35__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[13] ),
        .O(TXPOSTCURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_36__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[4] ),
        .O(TXPRECURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_37__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[3] ),
        .O(TXPRECURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_38__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[2] ),
        .O(TXPRECURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_39__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[1] ),
        .O(TXPRECURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_40__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[0] ),
        .O(TXPRECURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_41__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .O(TXMAINCURSOR[6]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_42__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .O(TXMAINCURSOR[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_43__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .O(TXMAINCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_44__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[9] ),
        .O(TXMAINCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_45__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[8] ),
        .O(TXMAINCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_46__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[7] ),
        .O(TXMAINCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_47__0 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[6] ),
        .O(TXMAINCURSOR[0]));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_4),
        .Q(USER_RXEQ_ADAPT_DONE),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_5),
        .Q(rxeq_adapt_done_reg_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04041C10)) 
    \rxeq_cnt[0]_i_1__2 
       (.I0(\rxeq_cnt_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_cnt[0]));
  LUT5 #(
    .INIT(32'h00424200)) 
    \rxeq_cnt[1]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[1] ),
        .I4(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[1]));
  LUT6 #(
    .INIT(64'h0042420042004200)) 
    \rxeq_cnt[2]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[2] ),
        .I4(\rxeq_cnt_reg_n_0_[1] ),
        .I5(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[2]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[0]),
        .Q(\rxeq_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[1]),
        .Q(\rxeq_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[2]),
        .Q(\rxeq_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[0]),
        .Q(rxeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[1]),
        .Q(rxeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[0]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_fs[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[1]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_fs[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[2]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_fs[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[3]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_fs[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[4]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_fs[4]));
  LUT4 #(
    .INIT(16'hC203)) 
    \rxeq_fs[5]_i_1__2 
       (.I0(rxeq_control_reg2[1]),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_fs[5]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[5]_i_2__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_fs[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__2_n_0 ),
        .D(rxeq_fs[0]),
        .Q(rxeq_fs__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__2_n_0 ),
        .D(rxeq_fs[1]),
        .Q(rxeq_fs__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__2_n_0 ),
        .D(rxeq_fs[2]),
        .Q(rxeq_fs__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__2_n_0 ),
        .D(rxeq_fs[3]),
        .Q(rxeq_fs__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__2_n_0 ),
        .D(rxeq_fs[4]),
        .Q(rxeq_fs__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__2_n_0 ),
        .D(rxeq_fs[5]),
        .Q(rxeq_fs__0[5]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[0]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_lf[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[1]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_lf[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[2]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_lf[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[3]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_lf[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[4]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_lf[4]));
  LUT6 #(
    .INIT(64'hFF000000000080FF)) 
    \rxeq_lf[5]_i_1__2 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\rxeq_cnt_reg_n_0_[2] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I5(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_lf[5]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[5]_i_2__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_lf[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__2_n_0 ),
        .D(rxeq_lf[0]),
        .Q(rxeq_lf__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__2_n_0 ),
        .D(rxeq_lf[1]),
        .Q(rxeq_lf__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__2_n_0 ),
        .D(rxeq_lf[2]),
        .Q(rxeq_lf__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__2_n_0 ),
        .D(rxeq_lf[3]),
        .Q(rxeq_lf__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__2_n_0 ),
        .D(rxeq_lf[4]),
        .Q(rxeq_lf__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__2_n_0 ),
        .D(rxeq_lf[5]),
        .Q(rxeq_lf__0[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[0]),
        .Q(rxeq_lffs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[1]),
        .Q(rxeq_lffs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[2]),
        .Q(rxeq_lffs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[3]),
        .Q(rxeq_lffs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[4]),
        .Q(rxeq_lffs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[5]),
        .Q(rxeq_lffs_reg2[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_new_txcoeff_req_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_3),
        .Q(rxeq_new_txcoeff_req_reg_n_0),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[0]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[0]),
        .I4(\rxeq_preset[2]_i_2__2_n_0 ),
        .I5(rxeq_preset__0[0]),
        .O(\rxeq_preset[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[1]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[1]),
        .I4(\rxeq_preset[2]_i_2__2_n_0 ),
        .I5(rxeq_preset__0[1]),
        .O(\rxeq_preset[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[2]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[2]),
        .I4(\rxeq_preset[2]_i_2__2_n_0 ),
        .I5(rxeq_preset__0[2]),
        .O(\rxeq_preset[2]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hF00400FF)) 
    \rxeq_preset[2]_i_2__2 
       (.I0(rxeq_control_reg2[1]),
        .I1(rxeq_control_reg2[0]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_preset[2]_i_2__2_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[0]),
        .Q(rxeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[1]),
        .Q(rxeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[2]),
        .Q(rxeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[0]_i_1__2_n_0 ),
        .Q(rxeq_preset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[1]_i_1__2_n_0 ),
        .Q(rxeq_preset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[2]_i_1__2_n_0 ),
        .Q(rxeq_preset__0[2]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h04)) 
    rxeq_preset_valid_i_1__2
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(rxeq_preset_valid));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_preset_valid_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid),
        .Q(rxeq_preset_valid_reg_n_0),
        .R(RST_CPLLRESET));
  PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_78 rxeq_scan_i
       (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}),
        .\FSM_sequential_fsm_rx_reg[0] (\FSM_sequential_fsm_rx[0]_i_2__2_n_0 ),
        .\FSM_sequential_fsm_rx_reg[2] ({\FSM_sequential_fsm_rx_reg_n_0_[2] ,\FSM_sequential_fsm_rx_reg_n_0_[1] ,\FSM_sequential_fsm_rx_reg_n_0_[0] }),
        .Q(rxeq_txpreset__0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE),
        .out(rxeq_control_reg2),
        .pclk_sel_reg(pclk_sel_reg),
        .rxeq_adapt_done_reg(rxeq_scan_i_n_4),
        .rxeq_adapt_done_reg_reg(rxeq_scan_i_n_5),
        .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_reg_n_0),
        .\rxeq_cnt_reg[1] (\FSM_sequential_fsm_rx[0]_i_3__2_n_0 ),
        .\rxeq_cnt_reg[1]_0 (\FSM_sequential_fsm_rx[2]_i_2__2_n_0 ),
        .\rxeq_control_reg2_reg[0] (\FSM_sequential_fsm_rx[2]_i_3__2_n_0 ),
        .\rxeq_fs_reg[5] (rxeq_fs__0),
        .\rxeq_lf_reg[5] (rxeq_lf__0),
        .rxeq_new_txcoeff_req_reg(rxeq_scan_i_n_3),
        .rxeq_new_txcoeff_req_reg_0(rxeq_new_txcoeff_req_reg_n_0),
        .\rxeq_preset_reg[2] (rxeq_preset__0),
        .rxeq_preset_valid_reg(rxeq_preset_valid_reg_n_0),
        .\rxeq_txcoeff_reg[17] ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,rxeq_txcoeff__0}));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[0]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[6] ),
        .O(rxeq_txcoeff[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[10]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[16] ),
        .O(rxeq_txcoeff[10]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[11]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[17] ),
        .O(rxeq_txcoeff[11]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[12]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[0]),
        .O(rxeq_txcoeff[12]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[13]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[1]),
        .O(rxeq_txcoeff[13]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[14]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[2]),
        .O(rxeq_txcoeff[14]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[15]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[3]),
        .O(rxeq_txcoeff[15]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[16]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[4]),
        .O(rxeq_txcoeff[16]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[17]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[5]),
        .O(rxeq_txcoeff[17]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[1]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[7] ),
        .O(rxeq_txcoeff[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[2]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[8] ),
        .O(rxeq_txcoeff[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[3]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[9] ),
        .O(rxeq_txcoeff[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[4]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[10] ),
        .O(rxeq_txcoeff[4]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[5]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[11] ),
        .O(rxeq_txcoeff[5]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[6]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[12] ),
        .O(rxeq_txcoeff[6]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[7]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[13] ),
        .O(rxeq_txcoeff[7]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[8]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[14] ),
        .O(rxeq_txcoeff[8]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[9]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[15] ),
        .O(rxeq_txcoeff[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[0]),
        .Q(rxeq_txcoeff__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[10]),
        .Q(\rxeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[11]),
        .Q(\rxeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[12]),
        .Q(\rxeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[13]),
        .Q(\rxeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[14]),
        .Q(\rxeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[15]),
        .Q(\rxeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[16]),
        .Q(\rxeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[17]),
        .Q(\rxeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[1]),
        .Q(rxeq_txcoeff__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[2]),
        .Q(rxeq_txcoeff__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[3]),
        .Q(rxeq_txcoeff__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[4]),
        .Q(rxeq_txcoeff__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[5]),
        .Q(rxeq_txcoeff__0[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[6]),
        .Q(\rxeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[7]),
        .Q(\rxeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[8]),
        .Q(\rxeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txcoeff[9]),
        .Q(\rxeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[0]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[0]),
        .O(rxeq_txpreset[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[1]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[1]),
        .O(rxeq_txpreset[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[2]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[2]),
        .O(rxeq_txpreset[2]));
  LUT4 #(
    .INIT(16'hF405)) 
    \rxeq_txpreset[3]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_txpreset[3]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[3]_i_2__2 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[3]),
        .O(rxeq_txpreset[3]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[0]),
        .Q(rxeq_txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[1]),
        .Q(rxeq_txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[2]),
        .Q(rxeq_txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[3]),
        .Q(rxeq_txpreset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txpreset[0]),
        .Q(rxeq_txpreset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txpreset[1]),
        .Q(rxeq_txpreset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txpreset[2]),
        .Q(rxeq_txpreset__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__2_n_0 ),
        .D(rxeq_txpreset[3]),
        .Q(rxeq_txpreset__0[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_en_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_en_reg1),
        .Q(rxeq_user_en_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_mode_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_mode_reg1),
        .Q(rxeq_user_mode_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[0]),
        .Q(rxeq_user_txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[10]),
        .Q(rxeq_user_txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[11]),
        .Q(rxeq_user_txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[12]),
        .Q(rxeq_user_txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[13]),
        .Q(rxeq_user_txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[14]),
        .Q(rxeq_user_txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[15]),
        .Q(rxeq_user_txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[16]),
        .Q(rxeq_user_txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[17]),
        .Q(rxeq_user_txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[1]),
        .Q(rxeq_user_txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[2]),
        .Q(rxeq_user_txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[3]),
        .Q(rxeq_user_txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[4]),
        .Q(rxeq_user_txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[5]),
        .Q(rxeq_user_txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[6]),
        .Q(rxeq_user_txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[7]),
        .Q(rxeq_user_txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[8]),
        .Q(rxeq_user_txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[9]),
        .Q(rxeq_user_txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[0]),
        .Q(txeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[1]),
        .Q(txeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[0]),
        .Q(txeq_deemph_reg2[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[1]),
        .Q(txeq_deemph_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[2]),
        .Q(txeq_deemph_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[3]),
        .Q(txeq_deemph_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[4]),
        .Q(txeq_deemph_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[5]),
        .Q(txeq_deemph_reg2[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00001000)) 
    \txeq_preset[0]_i_1__2 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hAEABBABB)) 
    \txeq_preset[10]_i_1__2 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[10]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hAEAABABB)) 
    \txeq_preset[11]_i_1__2 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[11]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00001574)) 
    \txeq_preset[12]_i_1__2 
       (.I0(txeq_preset_reg2[3]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[12]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[13]_i_1__2 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[13]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00000410)) 
    \txeq_preset[14]_i_1__2 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[14]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'hAAAB)) 
    \txeq_preset[15]_i_1__2 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .O(\txeq_preset[15]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0014)) 
    \txeq_preset[16]_i_1__2 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[16]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \txeq_preset[17]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(RST_CPLLRESET),
        .O(\txeq_preset[17]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hAAEABABB)) 
    \txeq_preset[17]_i_2__2 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[17]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[1]_i_1__2 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[1]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h00C8)) 
    \txeq_preset[2]_i_1__2 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[2]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00003424)) 
    \txeq_preset[3]_i_1__2 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[3]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00000408)) 
    \txeq_preset[7]_i_1__2 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[7]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hAAAEBBFB)) 
    \txeq_preset[8]_i_1__2 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[8]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hAEAEBABB)) 
    \txeq_preset[9]_i_1__2 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[9]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    txeq_preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .Q(txeq_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[0]),
        .Q(txeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[1]),
        .Q(txeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[2]),
        .Q(txeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[3]),
        .Q(txeq_preset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[0]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[10]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[11]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[12]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[13]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[14]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[15]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[16]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[17]_i_2__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[1]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[2]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[3]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[7]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[8]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__3_n_0 ),
        .D(\txeq_preset[9]_i_1__2_n_0 ),
        .Q(\txeq_preset_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[0]_i_1__2 
       (.I0(\txeq_txcoeff_reg_n_0_[6] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\txeq_preset_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[0]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hAA208A00)) 
    \txeq_txcoeff[0]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .O(\txeq_txcoeff[0]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[10]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[10] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[9] ),
        .I4(\txeq_txcoeff[10]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[10]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[10]_i_2__2 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[16] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[10]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[11]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[11] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[10] ),
        .I4(\txeq_txcoeff[11]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[11]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[11]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[18] ),
        .I2(\txeq_txcoeff_reg_n_0_[17] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[11]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[12]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[11] ),
        .I4(\txeq_txcoeff[12]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[12]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[12]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[0]),
        .I2(\txeq_txcoeff_reg_n_0_[18] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[12]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[13]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[13] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[12] ),
        .I4(\txeq_txcoeff[13]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[13]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[13]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[1]),
        .I2(txeq_deemph_reg2[0]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[13]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[14]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[14] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[13] ),
        .I4(\txeq_txcoeff[14]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[14]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[14]_i_2__2 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[14]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[15]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[15] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[14] ),
        .I4(\txeq_txcoeff[15]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[15]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[15]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[3]),
        .I2(txeq_deemph_reg2[2]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[15]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[16]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[16] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[15] ),
        .I4(\txeq_txcoeff[16]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[16]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[16]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[4]),
        .I2(txeq_deemph_reg2[3]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[16]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[17]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[17] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[16] ),
        .I4(\txeq_txcoeff[17]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[17]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[17]_i_2__2 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[4]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[17]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h5557FF5755575557)) 
    \txeq_txcoeff[18]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx[1]_i_2__2_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[0]),
        .I5(txeq_control_reg2[1]),
        .O(\txeq_txcoeff[18]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \txeq_txcoeff[18]_i_2__2 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\txeq_txcoeff[18]_i_3__2_n_0 ),
        .O(\txeq_txcoeff[18]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hF888F8F888888888)) 
    \txeq_txcoeff[18]_i_3__2 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(txeq_deemph_reg2[5]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[18]_i_3__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[1]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[1]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[1]_i_2__2 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[1]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[2]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[1] ),
        .I4(\txeq_txcoeff[2]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[2]_i_2__2 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[8] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[2]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[3]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[2] ),
        .I4(\txeq_txcoeff[3]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[3]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .I2(\txeq_txcoeff_reg_n_0_[9] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[3]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[4]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[3] ),
        .I4(\txeq_txcoeff[4]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[4]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .I2(\txeq_txcoeff_reg_n_0_[10] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[4]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[5]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[5] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[4] ),
        .I4(\txeq_txcoeff[5]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[5]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[5]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .I2(\txeq_txcoeff_reg_n_0_[11] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[5]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[6]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[5] ),
        .I4(\txeq_txcoeff[6]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[6]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[6]_i_2__2 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[12] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[6]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[7]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[7] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff[7]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[7]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[7]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .I2(\txeq_txcoeff_reg_n_0_[13] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[7]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[8]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[8] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[7] ),
        .I4(\txeq_txcoeff[8]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[8]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[8]_i_2__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .I2(\txeq_txcoeff_reg_n_0_[14] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[8]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[9]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[9] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[8] ),
        .I4(\txeq_txcoeff[9]_i_2__2_n_0 ),
        .O(\txeq_txcoeff[9]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[9]_i_2__2 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[15] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[9]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'h4444F444)) 
    \txeq_txcoeff_cnt[0]_i_1__2 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(txeq_control_reg2[1]),
        .I4(txeq_control_reg2[0]),
        .O(txeq_txcoeff_cnt[0]));
  LUT3 #(
    .INIT(8'h28)) 
    \txeq_txcoeff_cnt[1]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(txeq_txcoeff_cnt[1]));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[0]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[1]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[0]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[10]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[11]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[12]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[13]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[14]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[15]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[16]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[17]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[18] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[18]_i_2__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[1]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[2]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[3]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[4]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[5]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[6]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[7]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[8]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__2_n_0 ),
        .D(\txeq_txcoeff[9]_i_1__2_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_eq" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_49
   (TXPRECURSOR,
    TXMAINCURSOR,
    TXPOSTCURSOR,
    USER_RXEQ_ADAPT_DONE,
    RST_CPLLRESET,
    pclk_sel_reg,
    rate_gen3);
  output [4:0]TXPRECURSOR;
  output [6:0]TXMAINCURSOR;
  output [4:0]TXPOSTCURSOR;
  output USER_RXEQ_ADAPT_DONE;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]rate_gen3;

  wire \FSM_onehot_fsm_tx[1]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm_tx[1]_i_2__3_n_0 ;
  wire \FSM_onehot_fsm_tx[2]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_2__3_n_0 ;
  wire \FSM_onehot_fsm_tx[4]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm_tx[5]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_2__3_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_3__3_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[4] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[5] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[6] ;
  wire \FSM_sequential_fsm_rx[0]_i_2__3_n_0 ;
  wire \FSM_sequential_fsm_rx[0]_i_3__3_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_2__3_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_3__3_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[2] ;
  wire RST_CPLLRESET;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_RXEQ_ADAPT_DONE;
  wire gen3_reg1;
  wire gen3_reg2;
  wire pclk_sel_reg;
  wire [0:0]rate_gen3;
  wire rxeq_adapt_done_reg_reg_n_0;
  wire [2:0]rxeq_cnt;
  wire \rxeq_cnt_reg_n_0_[0] ;
  wire \rxeq_cnt_reg_n_0_[1] ;
  wire \rxeq_cnt_reg_n_0_[2] ;
  wire [1:0]rxeq_control_reg1;
  wire [1:0]rxeq_control_reg2;
  wire [5:0]rxeq_fs;
  wire \rxeq_fs[5]_i_1__3_n_0 ;
  wire [5:0]rxeq_fs__0;
  wire [5:0]rxeq_lf;
  wire \rxeq_lf[5]_i_1__3_n_0 ;
  wire [5:0]rxeq_lf__0;
  wire [5:0]rxeq_lffs_reg1;
  wire [5:0]rxeq_lffs_reg2;
  wire rxeq_new_txcoeff_req_reg_n_0;
  wire \rxeq_preset[0]_i_1__3_n_0 ;
  wire \rxeq_preset[1]_i_1__3_n_0 ;
  wire \rxeq_preset[2]_i_1__3_n_0 ;
  wire \rxeq_preset[2]_i_2__3_n_0 ;
  wire [2:0]rxeq_preset__0;
  wire [2:0]rxeq_preset_reg1;
  wire [2:0]rxeq_preset_reg2;
  wire rxeq_preset_valid;
  wire rxeq_preset_valid_reg_n_0;
  wire rxeq_scan_i_n_0;
  wire rxeq_scan_i_n_1;
  wire rxeq_scan_i_n_2;
  wire rxeq_scan_i_n_3;
  wire rxeq_scan_i_n_4;
  wire rxeq_scan_i_n_5;
  wire [17:0]rxeq_txcoeff;
  wire [5:0]rxeq_txcoeff__0;
  wire \rxeq_txcoeff_reg_n_0_[10] ;
  wire \rxeq_txcoeff_reg_n_0_[11] ;
  wire \rxeq_txcoeff_reg_n_0_[12] ;
  wire \rxeq_txcoeff_reg_n_0_[13] ;
  wire \rxeq_txcoeff_reg_n_0_[14] ;
  wire \rxeq_txcoeff_reg_n_0_[15] ;
  wire \rxeq_txcoeff_reg_n_0_[16] ;
  wire \rxeq_txcoeff_reg_n_0_[17] ;
  wire \rxeq_txcoeff_reg_n_0_[6] ;
  wire \rxeq_txcoeff_reg_n_0_[7] ;
  wire \rxeq_txcoeff_reg_n_0_[8] ;
  wire \rxeq_txcoeff_reg_n_0_[9] ;
  wire [3:0]rxeq_txpreset;
  wire \rxeq_txpreset[3]_i_1__3_n_0 ;
  wire [3:0]rxeq_txpreset__0;
  wire [3:0]rxeq_txpreset_reg1;
  wire [3:0]rxeq_txpreset_reg2;
  wire rxeq_user_en_reg1;
  wire rxeq_user_en_reg2;
  wire rxeq_user_mode_reg1;
  wire rxeq_user_mode_reg2;
  wire [17:0]rxeq_user_txcoeff_reg1;
  wire [17:0]rxeq_user_txcoeff_reg2;
  wire [1:0]txeq_control_reg1;
  wire [1:0]txeq_control_reg2;
  wire [5:0]txeq_deemph_reg1;
  wire [5:0]txeq_deemph_reg2;
  wire \txeq_preset[0]_i_1__3_n_0 ;
  wire \txeq_preset[10]_i_1__3_n_0 ;
  wire \txeq_preset[11]_i_1__3_n_0 ;
  wire \txeq_preset[12]_i_1__3_n_0 ;
  wire \txeq_preset[13]_i_1__3_n_0 ;
  wire \txeq_preset[14]_i_1__3_n_0 ;
  wire \txeq_preset[15]_i_1__3_n_0 ;
  wire \txeq_preset[16]_i_1__3_n_0 ;
  wire \txeq_preset[17]_i_1__2_n_0 ;
  wire \txeq_preset[17]_i_2__3_n_0 ;
  wire \txeq_preset[1]_i_1__3_n_0 ;
  wire \txeq_preset[2]_i_1__3_n_0 ;
  wire \txeq_preset[3]_i_1__3_n_0 ;
  wire \txeq_preset[7]_i_1__3_n_0 ;
  wire \txeq_preset[8]_i_1__3_n_0 ;
  wire \txeq_preset[9]_i_1__3_n_0 ;
  wire txeq_preset_done;
  wire [3:0]txeq_preset_reg1;
  wire [3:0]txeq_preset_reg2;
  wire \txeq_preset_reg_n_0_[0] ;
  wire \txeq_preset_reg_n_0_[10] ;
  wire \txeq_preset_reg_n_0_[11] ;
  wire \txeq_preset_reg_n_0_[12] ;
  wire \txeq_preset_reg_n_0_[13] ;
  wire \txeq_preset_reg_n_0_[14] ;
  wire \txeq_preset_reg_n_0_[15] ;
  wire \txeq_preset_reg_n_0_[16] ;
  wire \txeq_preset_reg_n_0_[17] ;
  wire \txeq_preset_reg_n_0_[1] ;
  wire \txeq_preset_reg_n_0_[2] ;
  wire \txeq_preset_reg_n_0_[3] ;
  wire \txeq_preset_reg_n_0_[4] ;
  wire \txeq_preset_reg_n_0_[5] ;
  wire \txeq_preset_reg_n_0_[6] ;
  wire \txeq_preset_reg_n_0_[7] ;
  wire \txeq_preset_reg_n_0_[8] ;
  wire \txeq_preset_reg_n_0_[9] ;
  wire \txeq_txcoeff[0]_i_1__3_n_0 ;
  wire \txeq_txcoeff[0]_i_2__3_n_0 ;
  wire \txeq_txcoeff[10]_i_1__3_n_0 ;
  wire \txeq_txcoeff[10]_i_2__3_n_0 ;
  wire \txeq_txcoeff[11]_i_1__3_n_0 ;
  wire \txeq_txcoeff[11]_i_2__3_n_0 ;
  wire \txeq_txcoeff[12]_i_1__3_n_0 ;
  wire \txeq_txcoeff[12]_i_2__3_n_0 ;
  wire \txeq_txcoeff[13]_i_1__3_n_0 ;
  wire \txeq_txcoeff[13]_i_2__3_n_0 ;
  wire \txeq_txcoeff[14]_i_1__3_n_0 ;
  wire \txeq_txcoeff[14]_i_2__3_n_0 ;
  wire \txeq_txcoeff[15]_i_1__3_n_0 ;
  wire \txeq_txcoeff[15]_i_2__3_n_0 ;
  wire \txeq_txcoeff[16]_i_1__3_n_0 ;
  wire \txeq_txcoeff[16]_i_2__3_n_0 ;
  wire \txeq_txcoeff[17]_i_1__3_n_0 ;
  wire \txeq_txcoeff[17]_i_2__3_n_0 ;
  wire \txeq_txcoeff[18]_i_1__3_n_0 ;
  wire \txeq_txcoeff[18]_i_2__3_n_0 ;
  wire \txeq_txcoeff[18]_i_3__3_n_0 ;
  wire \txeq_txcoeff[1]_i_1__3_n_0 ;
  wire \txeq_txcoeff[1]_i_2__3_n_0 ;
  wire \txeq_txcoeff[2]_i_1__3_n_0 ;
  wire \txeq_txcoeff[2]_i_2__3_n_0 ;
  wire \txeq_txcoeff[3]_i_1__3_n_0 ;
  wire \txeq_txcoeff[3]_i_2__3_n_0 ;
  wire \txeq_txcoeff[4]_i_1__3_n_0 ;
  wire \txeq_txcoeff[4]_i_2__3_n_0 ;
  wire \txeq_txcoeff[5]_i_1__3_n_0 ;
  wire \txeq_txcoeff[5]_i_2__3_n_0 ;
  wire \txeq_txcoeff[6]_i_1__3_n_0 ;
  wire \txeq_txcoeff[6]_i_2__3_n_0 ;
  wire \txeq_txcoeff[7]_i_1__3_n_0 ;
  wire \txeq_txcoeff[7]_i_2__3_n_0 ;
  wire \txeq_txcoeff[8]_i_1__3_n_0 ;
  wire \txeq_txcoeff[8]_i_2__3_n_0 ;
  wire \txeq_txcoeff[9]_i_1__3_n_0 ;
  wire \txeq_txcoeff[9]_i_2__3_n_0 ;
  wire [1:0]txeq_txcoeff_cnt;
  wire \txeq_txcoeff_cnt_reg_n_0_[0] ;
  wire \txeq_txcoeff_cnt_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[0] ;
  wire \txeq_txcoeff_reg_n_0_[10] ;
  wire \txeq_txcoeff_reg_n_0_[11] ;
  wire \txeq_txcoeff_reg_n_0_[12] ;
  wire \txeq_txcoeff_reg_n_0_[13] ;
  wire \txeq_txcoeff_reg_n_0_[14] ;
  wire \txeq_txcoeff_reg_n_0_[15] ;
  wire \txeq_txcoeff_reg_n_0_[16] ;
  wire \txeq_txcoeff_reg_n_0_[17] ;
  wire \txeq_txcoeff_reg_n_0_[18] ;
  wire \txeq_txcoeff_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[2] ;
  wire \txeq_txcoeff_reg_n_0_[3] ;
  wire \txeq_txcoeff_reg_n_0_[4] ;
  wire \txeq_txcoeff_reg_n_0_[5] ;
  wire \txeq_txcoeff_reg_n_0_[6] ;
  wire \txeq_txcoeff_reg_n_0_[7] ;
  wire \txeq_txcoeff_reg_n_0_[8] ;
  wire \txeq_txcoeff_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'h000000FF10101050)) 
    \FSM_onehot_fsm_tx[1]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx[1]_i_2__3_n_0 ),
        .I3(txeq_control_reg2[0]),
        .I4(txeq_control_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[1]_i_1__3_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_onehot_fsm_tx[1]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[1]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h20202F20)) 
    \FSM_onehot_fsm_tx[2]_i_1__3 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I4(txeq_preset_done),
        .O(\FSM_onehot_fsm_tx[2]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h45454545FF454545)) 
    \FSM_onehot_fsm_tx[3]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx[3]_i_2__3_n_0 ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(\FSM_onehot_fsm_tx[3]_i_1__3_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_onehot_fsm_tx[3]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm_tx[3]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \FSM_onehot_fsm_tx[4]_i_1__3 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[4]_i_1__3_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm_tx[5]_i_1__3 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[5]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \FSM_onehot_fsm_tx[6]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx[6]_i_2__3_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_tx[6]_i_3__3_n_0 ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[6]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBBBBBB8)) 
    \FSM_onehot_fsm_tx[6]_i_2__3 
       (.I0(txeq_preset_done),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[6]_i_2__3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_fsm_tx[6]_i_3__3 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .O(\FSM_onehot_fsm_tx[6]_i_3__3_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[1]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[2]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[3]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[4]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[5]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[6]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h838183C3)) 
    \FSM_sequential_fsm_rx[0]_i_2__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(rxeq_control_reg2[0]),
        .O(\FSM_sequential_fsm_rx[0]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFD000080)) 
    \FSM_sequential_fsm_rx[0]_i_3__3 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm_rx[0]_i_3__3_n_0 ));
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_fsm_rx[2]_i_2__3 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fsm_rx[2]_i_2__3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_fsm_rx[2]_i_3__3 
       (.I0(rxeq_control_reg2[0]),
        .I1(rxeq_control_reg2[1]),
        .O(\FSM_sequential_fsm_rx[2]_i_3__3_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_2),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_1),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_0),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_30__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .O(TXPOSTCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_31__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[16] ),
        .O(TXPOSTCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_32__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .O(TXPOSTCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_33__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .O(TXPOSTCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_34__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[13] ),
        .O(TXPOSTCURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_35__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[4] ),
        .O(TXPRECURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_36__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[3] ),
        .O(TXPRECURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_37__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[2] ),
        .O(TXPRECURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_38__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[1] ),
        .O(TXPRECURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_39__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[0] ),
        .O(TXPRECURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_40__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .O(TXMAINCURSOR[6]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_41__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .O(TXMAINCURSOR[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_42__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .O(TXMAINCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_43__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[9] ),
        .O(TXMAINCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_44__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[8] ),
        .O(TXMAINCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_45__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[7] ),
        .O(TXMAINCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_46__3 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[6] ),
        .O(TXMAINCURSOR[0]));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_4),
        .Q(USER_RXEQ_ADAPT_DONE),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_5),
        .Q(rxeq_adapt_done_reg_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04041C10)) 
    \rxeq_cnt[0]_i_1__3 
       (.I0(\rxeq_cnt_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_cnt[0]));
  LUT5 #(
    .INIT(32'h00424200)) 
    \rxeq_cnt[1]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[1] ),
        .I4(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[1]));
  LUT6 #(
    .INIT(64'h0042420042004200)) 
    \rxeq_cnt[2]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[2] ),
        .I4(\rxeq_cnt_reg_n_0_[1] ),
        .I5(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[2]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[0]),
        .Q(\rxeq_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[1]),
        .Q(\rxeq_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[2]),
        .Q(\rxeq_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[0]),
        .Q(rxeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[1]),
        .Q(rxeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[0]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_fs[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[1]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_fs[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[2]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_fs[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[3]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_fs[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[4]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_fs[4]));
  LUT4 #(
    .INIT(16'hC203)) 
    \rxeq_fs[5]_i_1__3 
       (.I0(rxeq_control_reg2[1]),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_fs[5]_i_1__3_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[5]_i_2__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_fs[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__3_n_0 ),
        .D(rxeq_fs[0]),
        .Q(rxeq_fs__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__3_n_0 ),
        .D(rxeq_fs[1]),
        .Q(rxeq_fs__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__3_n_0 ),
        .D(rxeq_fs[2]),
        .Q(rxeq_fs__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__3_n_0 ),
        .D(rxeq_fs[3]),
        .Q(rxeq_fs__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__3_n_0 ),
        .D(rxeq_fs[4]),
        .Q(rxeq_fs__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__3_n_0 ),
        .D(rxeq_fs[5]),
        .Q(rxeq_fs__0[5]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[0]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_lf[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[1]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_lf[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[2]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_lf[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[3]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_lf[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[4]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_lf[4]));
  LUT6 #(
    .INIT(64'hFF000000000080FF)) 
    \rxeq_lf[5]_i_1__3 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\rxeq_cnt_reg_n_0_[2] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I5(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_lf[5]_i_1__3_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[5]_i_2__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_lf[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__3_n_0 ),
        .D(rxeq_lf[0]),
        .Q(rxeq_lf__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__3_n_0 ),
        .D(rxeq_lf[1]),
        .Q(rxeq_lf__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__3_n_0 ),
        .D(rxeq_lf[2]),
        .Q(rxeq_lf__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__3_n_0 ),
        .D(rxeq_lf[3]),
        .Q(rxeq_lf__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__3_n_0 ),
        .D(rxeq_lf[4]),
        .Q(rxeq_lf__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__3_n_0 ),
        .D(rxeq_lf[5]),
        .Q(rxeq_lf__0[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[0]),
        .Q(rxeq_lffs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[1]),
        .Q(rxeq_lffs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[2]),
        .Q(rxeq_lffs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[3]),
        .Q(rxeq_lffs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[4]),
        .Q(rxeq_lffs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[5]),
        .Q(rxeq_lffs_reg2[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_new_txcoeff_req_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_3),
        .Q(rxeq_new_txcoeff_req_reg_n_0),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[0]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[0]),
        .I4(\rxeq_preset[2]_i_2__3_n_0 ),
        .I5(rxeq_preset__0[0]),
        .O(\rxeq_preset[0]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[1]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[1]),
        .I4(\rxeq_preset[2]_i_2__3_n_0 ),
        .I5(rxeq_preset__0[1]),
        .O(\rxeq_preset[1]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[2]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[2]),
        .I4(\rxeq_preset[2]_i_2__3_n_0 ),
        .I5(rxeq_preset__0[2]),
        .O(\rxeq_preset[2]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hF00400FF)) 
    \rxeq_preset[2]_i_2__3 
       (.I0(rxeq_control_reg2[1]),
        .I1(rxeq_control_reg2[0]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_preset[2]_i_2__3_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[0]),
        .Q(rxeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[1]),
        .Q(rxeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[2]),
        .Q(rxeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[0]_i_1__3_n_0 ),
        .Q(rxeq_preset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[1]_i_1__3_n_0 ),
        .Q(rxeq_preset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[2]_i_1__3_n_0 ),
        .Q(rxeq_preset__0[2]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h04)) 
    rxeq_preset_valid_i_1__3
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(rxeq_preset_valid));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_preset_valid_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid),
        .Q(rxeq_preset_valid_reg_n_0),
        .R(RST_CPLLRESET));
  PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_76 rxeq_scan_i
       (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}),
        .\FSM_sequential_fsm_rx_reg[0] (\FSM_sequential_fsm_rx[0]_i_2__3_n_0 ),
        .\FSM_sequential_fsm_rx_reg[2] ({\FSM_sequential_fsm_rx_reg_n_0_[2] ,\FSM_sequential_fsm_rx_reg_n_0_[1] ,\FSM_sequential_fsm_rx_reg_n_0_[0] }),
        .Q(rxeq_txpreset__0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE),
        .out(rxeq_control_reg2),
        .pclk_sel_reg(pclk_sel_reg),
        .rxeq_adapt_done_reg(rxeq_scan_i_n_4),
        .rxeq_adapt_done_reg_reg(rxeq_scan_i_n_5),
        .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_reg_n_0),
        .\rxeq_cnt_reg[1] (\FSM_sequential_fsm_rx[0]_i_3__3_n_0 ),
        .\rxeq_cnt_reg[1]_0 (\FSM_sequential_fsm_rx[2]_i_2__3_n_0 ),
        .\rxeq_control_reg2_reg[0] (\FSM_sequential_fsm_rx[2]_i_3__3_n_0 ),
        .\rxeq_fs_reg[5] (rxeq_fs__0),
        .\rxeq_lf_reg[5] (rxeq_lf__0),
        .rxeq_new_txcoeff_req_reg(rxeq_scan_i_n_3),
        .rxeq_new_txcoeff_req_reg_0(rxeq_new_txcoeff_req_reg_n_0),
        .\rxeq_preset_reg[2] (rxeq_preset__0),
        .rxeq_preset_valid_reg(rxeq_preset_valid_reg_n_0),
        .\rxeq_txcoeff_reg[17] ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,rxeq_txcoeff__0}));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[0]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[6] ),
        .O(rxeq_txcoeff[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[10]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[16] ),
        .O(rxeq_txcoeff[10]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[11]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[17] ),
        .O(rxeq_txcoeff[11]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[12]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[0]),
        .O(rxeq_txcoeff[12]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[13]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[1]),
        .O(rxeq_txcoeff[13]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[14]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[2]),
        .O(rxeq_txcoeff[14]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[15]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[3]),
        .O(rxeq_txcoeff[15]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[16]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[4]),
        .O(rxeq_txcoeff[16]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[17]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[5]),
        .O(rxeq_txcoeff[17]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[1]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[7] ),
        .O(rxeq_txcoeff[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[2]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[8] ),
        .O(rxeq_txcoeff[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[3]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[9] ),
        .O(rxeq_txcoeff[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[4]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[10] ),
        .O(rxeq_txcoeff[4]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[5]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[11] ),
        .O(rxeq_txcoeff[5]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[6]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[12] ),
        .O(rxeq_txcoeff[6]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[7]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[13] ),
        .O(rxeq_txcoeff[7]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[8]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[14] ),
        .O(rxeq_txcoeff[8]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[9]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[15] ),
        .O(rxeq_txcoeff[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[0]),
        .Q(rxeq_txcoeff__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[10]),
        .Q(\rxeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[11]),
        .Q(\rxeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[12]),
        .Q(\rxeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[13]),
        .Q(\rxeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[14]),
        .Q(\rxeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[15]),
        .Q(\rxeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[16]),
        .Q(\rxeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[17]),
        .Q(\rxeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[1]),
        .Q(rxeq_txcoeff__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[2]),
        .Q(rxeq_txcoeff__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[3]),
        .Q(rxeq_txcoeff__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[4]),
        .Q(rxeq_txcoeff__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[5]),
        .Q(rxeq_txcoeff__0[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[6]),
        .Q(\rxeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[7]),
        .Q(\rxeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[8]),
        .Q(\rxeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txcoeff[9]),
        .Q(\rxeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[0]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[0]),
        .O(rxeq_txpreset[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[1]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[1]),
        .O(rxeq_txpreset[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[2]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[2]),
        .O(rxeq_txpreset[2]));
  LUT4 #(
    .INIT(16'hF405)) 
    \rxeq_txpreset[3]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_txpreset[3]_i_1__3_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[3]_i_2__3 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[3]),
        .O(rxeq_txpreset[3]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[0]),
        .Q(rxeq_txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[1]),
        .Q(rxeq_txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[2]),
        .Q(rxeq_txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[3]),
        .Q(rxeq_txpreset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txpreset[0]),
        .Q(rxeq_txpreset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txpreset[1]),
        .Q(rxeq_txpreset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txpreset[2]),
        .Q(rxeq_txpreset__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__3_n_0 ),
        .D(rxeq_txpreset[3]),
        .Q(rxeq_txpreset__0[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_en_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_en_reg1),
        .Q(rxeq_user_en_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_mode_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_mode_reg1),
        .Q(rxeq_user_mode_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[0]),
        .Q(rxeq_user_txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[10]),
        .Q(rxeq_user_txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[11]),
        .Q(rxeq_user_txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[12]),
        .Q(rxeq_user_txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[13]),
        .Q(rxeq_user_txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[14]),
        .Q(rxeq_user_txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[15]),
        .Q(rxeq_user_txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[16]),
        .Q(rxeq_user_txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[17]),
        .Q(rxeq_user_txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[1]),
        .Q(rxeq_user_txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[2]),
        .Q(rxeq_user_txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[3]),
        .Q(rxeq_user_txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[4]),
        .Q(rxeq_user_txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[5]),
        .Q(rxeq_user_txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[6]),
        .Q(rxeq_user_txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[7]),
        .Q(rxeq_user_txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[8]),
        .Q(rxeq_user_txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[9]),
        .Q(rxeq_user_txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[0]),
        .Q(txeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[1]),
        .Q(txeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[0]),
        .Q(txeq_deemph_reg2[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[1]),
        .Q(txeq_deemph_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[2]),
        .Q(txeq_deemph_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[3]),
        .Q(txeq_deemph_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[4]),
        .Q(txeq_deemph_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[5]),
        .Q(txeq_deemph_reg2[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00001000)) 
    \txeq_preset[0]_i_1__3 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[0]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hAEABBABB)) 
    \txeq_preset[10]_i_1__3 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[10]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hAEAABABB)) 
    \txeq_preset[11]_i_1__3 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[11]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h00001574)) 
    \txeq_preset[12]_i_1__3 
       (.I0(txeq_preset_reg2[3]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[12]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[13]_i_1__3 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[13]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h00000410)) 
    \txeq_preset[14]_i_1__3 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[14]_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'hAAAB)) 
    \txeq_preset[15]_i_1__3 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .O(\txeq_preset[15]_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'h0014)) 
    \txeq_preset[16]_i_1__3 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[16]_i_1__3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \txeq_preset[17]_i_1__2 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(RST_CPLLRESET),
        .O(\txeq_preset[17]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hAAEABABB)) 
    \txeq_preset[17]_i_2__3 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[17]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[1]_i_1__3 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[1]_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'h00C8)) 
    \txeq_preset[2]_i_1__3 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[2]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h00003424)) 
    \txeq_preset[3]_i_1__3 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[3]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h00000408)) 
    \txeq_preset[7]_i_1__3 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[7]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hAAAEBBFB)) 
    \txeq_preset[8]_i_1__3 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[8]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hAEAEBABB)) 
    \txeq_preset[9]_i_1__3 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[9]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    txeq_preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .Q(txeq_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[0]),
        .Q(txeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[1]),
        .Q(txeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[2]),
        .Q(txeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[3]),
        .Q(txeq_preset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[0]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[10]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[11]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[12]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[13]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[14]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[15]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[16]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[17]_i_2__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[1]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[2]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[3]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[7]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[8]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__2_n_0 ),
        .D(\txeq_preset[9]_i_1__3_n_0 ),
        .Q(\txeq_preset_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[0]_i_1__3 
       (.I0(\txeq_txcoeff_reg_n_0_[6] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\txeq_preset_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[0]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[0]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hAA208A00)) 
    \txeq_txcoeff[0]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .O(\txeq_txcoeff[0]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[10]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[10] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[9] ),
        .I4(\txeq_txcoeff[10]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[10]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[10]_i_2__3 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[16] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[10]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[11]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[11] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[10] ),
        .I4(\txeq_txcoeff[11]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[11]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[11]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[18] ),
        .I2(\txeq_txcoeff_reg_n_0_[17] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[11]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[12]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[11] ),
        .I4(\txeq_txcoeff[12]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[12]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[12]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[0]),
        .I2(\txeq_txcoeff_reg_n_0_[18] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[12]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[13]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[13] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[12] ),
        .I4(\txeq_txcoeff[13]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[13]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[13]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[1]),
        .I2(txeq_deemph_reg2[0]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[13]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[14]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[14] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[13] ),
        .I4(\txeq_txcoeff[14]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[14]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[14]_i_2__3 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[14]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[15]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[15] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[14] ),
        .I4(\txeq_txcoeff[15]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[15]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[15]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[3]),
        .I2(txeq_deemph_reg2[2]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[15]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[16]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[16] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[15] ),
        .I4(\txeq_txcoeff[16]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[16]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[16]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[4]),
        .I2(txeq_deemph_reg2[3]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[16]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[17]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[17] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[16] ),
        .I4(\txeq_txcoeff[17]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[17]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[17]_i_2__3 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[4]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[17]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h5557FF5755575557)) 
    \txeq_txcoeff[18]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx[1]_i_2__3_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[0]),
        .I5(txeq_control_reg2[1]),
        .O(\txeq_txcoeff[18]_i_1__3_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \txeq_txcoeff[18]_i_2__3 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\txeq_txcoeff[18]_i_3__3_n_0 ),
        .O(\txeq_txcoeff[18]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'hF888F8F888888888)) 
    \txeq_txcoeff[18]_i_3__3 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(txeq_deemph_reg2[5]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[18]_i_3__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[1]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[1]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[1]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[1]_i_2__3 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[1]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[2]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[1] ),
        .I4(\txeq_txcoeff[2]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[2]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[2]_i_2__3 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[8] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[2]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[3]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[2] ),
        .I4(\txeq_txcoeff[3]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[3]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[3]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .I2(\txeq_txcoeff_reg_n_0_[9] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[3]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[4]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[3] ),
        .I4(\txeq_txcoeff[4]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[4]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[4]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .I2(\txeq_txcoeff_reg_n_0_[10] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[4]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[5]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[5] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[4] ),
        .I4(\txeq_txcoeff[5]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[5]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[5]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .I2(\txeq_txcoeff_reg_n_0_[11] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[5]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[6]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[5] ),
        .I4(\txeq_txcoeff[6]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[6]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[6]_i_2__3 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[12] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[6]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[7]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[7] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff[7]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[7]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[7]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .I2(\txeq_txcoeff_reg_n_0_[13] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[7]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[8]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[8] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[7] ),
        .I4(\txeq_txcoeff[8]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[8]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[8]_i_2__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .I2(\txeq_txcoeff_reg_n_0_[14] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[8]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[9]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[9] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[8] ),
        .I4(\txeq_txcoeff[9]_i_2__3_n_0 ),
        .O(\txeq_txcoeff[9]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[9]_i_2__3 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[15] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[9]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h4444F444)) 
    \txeq_txcoeff_cnt[0]_i_1__3 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(txeq_control_reg2[1]),
        .I4(txeq_control_reg2[0]),
        .O(txeq_txcoeff_cnt[0]));
  LUT3 #(
    .INIT(8'h28)) 
    \txeq_txcoeff_cnt[1]_i_1__3 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(txeq_txcoeff_cnt[1]));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[0]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[1]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[0]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[10]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[11]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[12]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[13]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[14]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[15]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[16]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[17]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[18] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[18]_i_2__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[1]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[2]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[3]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[4]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[5]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[6]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[7]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[8]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__3_n_0 ),
        .D(\txeq_txcoeff[9]_i_1__3_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_eq" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_56
   (TXPRECURSOR,
    TXMAINCURSOR,
    TXPOSTCURSOR,
    USER_RXEQ_ADAPT_DONE,
    RST_CPLLRESET,
    pclk_sel_reg,
    rate_gen3);
  output [4:0]TXPRECURSOR;
  output [6:0]TXMAINCURSOR;
  output [4:0]TXPOSTCURSOR;
  output USER_RXEQ_ADAPT_DONE;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]rate_gen3;

  wire \FSM_onehot_fsm_tx[1]_i_1__4_n_0 ;
  wire \FSM_onehot_fsm_tx[1]_i_2__4_n_0 ;
  wire \FSM_onehot_fsm_tx[2]_i_1__4_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_1__4_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_2__4_n_0 ;
  wire \FSM_onehot_fsm_tx[4]_i_1__4_n_0 ;
  wire \FSM_onehot_fsm_tx[5]_i_1__4_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_1__4_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_2__4_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_3__4_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[4] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[5] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[6] ;
  wire \FSM_sequential_fsm_rx[0]_i_2__4_n_0 ;
  wire \FSM_sequential_fsm_rx[0]_i_3__4_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_2__4_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_3__4_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[2] ;
  wire RST_CPLLRESET;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_RXEQ_ADAPT_DONE;
  wire gen3_reg1;
  wire gen3_reg2;
  wire pclk_sel_reg;
  wire [0:0]rate_gen3;
  wire rxeq_adapt_done_reg_reg_n_0;
  wire [2:0]rxeq_cnt;
  wire \rxeq_cnt_reg_n_0_[0] ;
  wire \rxeq_cnt_reg_n_0_[1] ;
  wire \rxeq_cnt_reg_n_0_[2] ;
  wire [1:0]rxeq_control_reg1;
  wire [1:0]rxeq_control_reg2;
  wire [5:0]rxeq_fs;
  wire \rxeq_fs[5]_i_1__4_n_0 ;
  wire [5:0]rxeq_fs__0;
  wire [5:0]rxeq_lf;
  wire \rxeq_lf[5]_i_1__4_n_0 ;
  wire [5:0]rxeq_lf__0;
  wire [5:0]rxeq_lffs_reg1;
  wire [5:0]rxeq_lffs_reg2;
  wire rxeq_new_txcoeff_req_reg_n_0;
  wire \rxeq_preset[0]_i_1__4_n_0 ;
  wire \rxeq_preset[1]_i_1__4_n_0 ;
  wire \rxeq_preset[2]_i_1__4_n_0 ;
  wire \rxeq_preset[2]_i_2__4_n_0 ;
  wire [2:0]rxeq_preset__0;
  wire [2:0]rxeq_preset_reg1;
  wire [2:0]rxeq_preset_reg2;
  wire rxeq_preset_valid;
  wire rxeq_preset_valid_reg_n_0;
  wire rxeq_scan_i_n_0;
  wire rxeq_scan_i_n_1;
  wire rxeq_scan_i_n_2;
  wire rxeq_scan_i_n_3;
  wire rxeq_scan_i_n_4;
  wire rxeq_scan_i_n_5;
  wire [17:0]rxeq_txcoeff;
  wire [5:0]rxeq_txcoeff__0;
  wire \rxeq_txcoeff_reg_n_0_[10] ;
  wire \rxeq_txcoeff_reg_n_0_[11] ;
  wire \rxeq_txcoeff_reg_n_0_[12] ;
  wire \rxeq_txcoeff_reg_n_0_[13] ;
  wire \rxeq_txcoeff_reg_n_0_[14] ;
  wire \rxeq_txcoeff_reg_n_0_[15] ;
  wire \rxeq_txcoeff_reg_n_0_[16] ;
  wire \rxeq_txcoeff_reg_n_0_[17] ;
  wire \rxeq_txcoeff_reg_n_0_[6] ;
  wire \rxeq_txcoeff_reg_n_0_[7] ;
  wire \rxeq_txcoeff_reg_n_0_[8] ;
  wire \rxeq_txcoeff_reg_n_0_[9] ;
  wire [3:0]rxeq_txpreset;
  wire \rxeq_txpreset[3]_i_1__4_n_0 ;
  wire [3:0]rxeq_txpreset__0;
  wire [3:0]rxeq_txpreset_reg1;
  wire [3:0]rxeq_txpreset_reg2;
  wire rxeq_user_en_reg1;
  wire rxeq_user_en_reg2;
  wire rxeq_user_mode_reg1;
  wire rxeq_user_mode_reg2;
  wire [17:0]rxeq_user_txcoeff_reg1;
  wire [17:0]rxeq_user_txcoeff_reg2;
  wire [1:0]txeq_control_reg1;
  wire [1:0]txeq_control_reg2;
  wire [5:0]txeq_deemph_reg1;
  wire [5:0]txeq_deemph_reg2;
  wire \txeq_preset[0]_i_1__4_n_0 ;
  wire \txeq_preset[10]_i_1__4_n_0 ;
  wire \txeq_preset[11]_i_1__4_n_0 ;
  wire \txeq_preset[12]_i_1__4_n_0 ;
  wire \txeq_preset[13]_i_1__4_n_0 ;
  wire \txeq_preset[14]_i_1__4_n_0 ;
  wire \txeq_preset[15]_i_1__4_n_0 ;
  wire \txeq_preset[16]_i_1__4_n_0 ;
  wire \txeq_preset[17]_i_1__1_n_0 ;
  wire \txeq_preset[17]_i_2__4_n_0 ;
  wire \txeq_preset[1]_i_1__4_n_0 ;
  wire \txeq_preset[2]_i_1__4_n_0 ;
  wire \txeq_preset[3]_i_1__4_n_0 ;
  wire \txeq_preset[7]_i_1__4_n_0 ;
  wire \txeq_preset[8]_i_1__4_n_0 ;
  wire \txeq_preset[9]_i_1__4_n_0 ;
  wire txeq_preset_done;
  wire [3:0]txeq_preset_reg1;
  wire [3:0]txeq_preset_reg2;
  wire \txeq_preset_reg_n_0_[0] ;
  wire \txeq_preset_reg_n_0_[10] ;
  wire \txeq_preset_reg_n_0_[11] ;
  wire \txeq_preset_reg_n_0_[12] ;
  wire \txeq_preset_reg_n_0_[13] ;
  wire \txeq_preset_reg_n_0_[14] ;
  wire \txeq_preset_reg_n_0_[15] ;
  wire \txeq_preset_reg_n_0_[16] ;
  wire \txeq_preset_reg_n_0_[17] ;
  wire \txeq_preset_reg_n_0_[1] ;
  wire \txeq_preset_reg_n_0_[2] ;
  wire \txeq_preset_reg_n_0_[3] ;
  wire \txeq_preset_reg_n_0_[4] ;
  wire \txeq_preset_reg_n_0_[5] ;
  wire \txeq_preset_reg_n_0_[6] ;
  wire \txeq_preset_reg_n_0_[7] ;
  wire \txeq_preset_reg_n_0_[8] ;
  wire \txeq_preset_reg_n_0_[9] ;
  wire \txeq_txcoeff[0]_i_1__4_n_0 ;
  wire \txeq_txcoeff[0]_i_2__4_n_0 ;
  wire \txeq_txcoeff[10]_i_1__4_n_0 ;
  wire \txeq_txcoeff[10]_i_2__4_n_0 ;
  wire \txeq_txcoeff[11]_i_1__4_n_0 ;
  wire \txeq_txcoeff[11]_i_2__4_n_0 ;
  wire \txeq_txcoeff[12]_i_1__4_n_0 ;
  wire \txeq_txcoeff[12]_i_2__4_n_0 ;
  wire \txeq_txcoeff[13]_i_1__4_n_0 ;
  wire \txeq_txcoeff[13]_i_2__4_n_0 ;
  wire \txeq_txcoeff[14]_i_1__4_n_0 ;
  wire \txeq_txcoeff[14]_i_2__4_n_0 ;
  wire \txeq_txcoeff[15]_i_1__4_n_0 ;
  wire \txeq_txcoeff[15]_i_2__4_n_0 ;
  wire \txeq_txcoeff[16]_i_1__4_n_0 ;
  wire \txeq_txcoeff[16]_i_2__4_n_0 ;
  wire \txeq_txcoeff[17]_i_1__4_n_0 ;
  wire \txeq_txcoeff[17]_i_2__4_n_0 ;
  wire \txeq_txcoeff[18]_i_1__4_n_0 ;
  wire \txeq_txcoeff[18]_i_2__4_n_0 ;
  wire \txeq_txcoeff[18]_i_3__4_n_0 ;
  wire \txeq_txcoeff[1]_i_1__4_n_0 ;
  wire \txeq_txcoeff[1]_i_2__4_n_0 ;
  wire \txeq_txcoeff[2]_i_1__4_n_0 ;
  wire \txeq_txcoeff[2]_i_2__4_n_0 ;
  wire \txeq_txcoeff[3]_i_1__4_n_0 ;
  wire \txeq_txcoeff[3]_i_2__4_n_0 ;
  wire \txeq_txcoeff[4]_i_1__4_n_0 ;
  wire \txeq_txcoeff[4]_i_2__4_n_0 ;
  wire \txeq_txcoeff[5]_i_1__4_n_0 ;
  wire \txeq_txcoeff[5]_i_2__4_n_0 ;
  wire \txeq_txcoeff[6]_i_1__4_n_0 ;
  wire \txeq_txcoeff[6]_i_2__4_n_0 ;
  wire \txeq_txcoeff[7]_i_1__4_n_0 ;
  wire \txeq_txcoeff[7]_i_2__4_n_0 ;
  wire \txeq_txcoeff[8]_i_1__4_n_0 ;
  wire \txeq_txcoeff[8]_i_2__4_n_0 ;
  wire \txeq_txcoeff[9]_i_1__4_n_0 ;
  wire \txeq_txcoeff[9]_i_2__4_n_0 ;
  wire [1:0]txeq_txcoeff_cnt;
  wire \txeq_txcoeff_cnt_reg_n_0_[0] ;
  wire \txeq_txcoeff_cnt_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[0] ;
  wire \txeq_txcoeff_reg_n_0_[10] ;
  wire \txeq_txcoeff_reg_n_0_[11] ;
  wire \txeq_txcoeff_reg_n_0_[12] ;
  wire \txeq_txcoeff_reg_n_0_[13] ;
  wire \txeq_txcoeff_reg_n_0_[14] ;
  wire \txeq_txcoeff_reg_n_0_[15] ;
  wire \txeq_txcoeff_reg_n_0_[16] ;
  wire \txeq_txcoeff_reg_n_0_[17] ;
  wire \txeq_txcoeff_reg_n_0_[18] ;
  wire \txeq_txcoeff_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[2] ;
  wire \txeq_txcoeff_reg_n_0_[3] ;
  wire \txeq_txcoeff_reg_n_0_[4] ;
  wire \txeq_txcoeff_reg_n_0_[5] ;
  wire \txeq_txcoeff_reg_n_0_[6] ;
  wire \txeq_txcoeff_reg_n_0_[7] ;
  wire \txeq_txcoeff_reg_n_0_[8] ;
  wire \txeq_txcoeff_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'h000000FF10101050)) 
    \FSM_onehot_fsm_tx[1]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx[1]_i_2__4_n_0 ),
        .I3(txeq_control_reg2[0]),
        .I4(txeq_control_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[1]_i_1__4_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_onehot_fsm_tx[1]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[1]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'h20202F20)) 
    \FSM_onehot_fsm_tx[2]_i_1__4 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I4(txeq_preset_done),
        .O(\FSM_onehot_fsm_tx[2]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h45454545FF454545)) 
    \FSM_onehot_fsm_tx[3]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx[3]_i_2__4_n_0 ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(\FSM_onehot_fsm_tx[3]_i_1__4_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_onehot_fsm_tx[3]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm_tx[3]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \FSM_onehot_fsm_tx[4]_i_1__4 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[4]_i_1__4_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm_tx[5]_i_1__4 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[5]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \FSM_onehot_fsm_tx[6]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx[6]_i_2__4_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_tx[6]_i_3__4_n_0 ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[6]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBBBBBB8)) 
    \FSM_onehot_fsm_tx[6]_i_2__4 
       (.I0(txeq_preset_done),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[6]_i_2__4_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_fsm_tx[6]_i_3__4 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .O(\FSM_onehot_fsm_tx[6]_i_3__4_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[1]_i_1__4_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[2]_i_1__4_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[3]_i_1__4_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[4]_i_1__4_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[5]_i_1__4_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[6]_i_1__4_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h838183C3)) 
    \FSM_sequential_fsm_rx[0]_i_2__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(rxeq_control_reg2[0]),
        .O(\FSM_sequential_fsm_rx[0]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFD000080)) 
    \FSM_sequential_fsm_rx[0]_i_3__4 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm_rx[0]_i_3__4_n_0 ));
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_fsm_rx[2]_i_2__4 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fsm_rx[2]_i_2__4_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_fsm_rx[2]_i_3__4 
       (.I0(rxeq_control_reg2[0]),
        .I1(rxeq_control_reg2[1]),
        .O(\FSM_sequential_fsm_rx[2]_i_3__4_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_2),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_1),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_0),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_30__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .O(TXPOSTCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_31__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[16] ),
        .O(TXPOSTCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_32__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .O(TXPOSTCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_33__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .O(TXPOSTCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_34__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[13] ),
        .O(TXPOSTCURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_35__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[4] ),
        .O(TXPRECURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_36__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[3] ),
        .O(TXPRECURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_37__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[2] ),
        .O(TXPRECURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_38__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[1] ),
        .O(TXPRECURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_39__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[0] ),
        .O(TXPRECURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_40__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .O(TXMAINCURSOR[6]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_41__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .O(TXMAINCURSOR[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_42__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .O(TXMAINCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_43__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[9] ),
        .O(TXMAINCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_44__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[8] ),
        .O(TXMAINCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_45__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[7] ),
        .O(TXMAINCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_46__4 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[6] ),
        .O(TXMAINCURSOR[0]));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_4),
        .Q(USER_RXEQ_ADAPT_DONE),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_5),
        .Q(rxeq_adapt_done_reg_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04041C10)) 
    \rxeq_cnt[0]_i_1__4 
       (.I0(\rxeq_cnt_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_cnt[0]));
  LUT5 #(
    .INIT(32'h00424200)) 
    \rxeq_cnt[1]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[1] ),
        .I4(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[1]));
  LUT6 #(
    .INIT(64'h0042420042004200)) 
    \rxeq_cnt[2]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[2] ),
        .I4(\rxeq_cnt_reg_n_0_[1] ),
        .I5(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[2]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[0]),
        .Q(\rxeq_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[1]),
        .Q(\rxeq_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[2]),
        .Q(\rxeq_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[0]),
        .Q(rxeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[1]),
        .Q(rxeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[0]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_fs[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[1]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_fs[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[2]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_fs[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[3]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_fs[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[4]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_fs[4]));
  LUT4 #(
    .INIT(16'hC203)) 
    \rxeq_fs[5]_i_1__4 
       (.I0(rxeq_control_reg2[1]),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_fs[5]_i_1__4_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[5]_i_2__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_fs[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__4_n_0 ),
        .D(rxeq_fs[0]),
        .Q(rxeq_fs__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__4_n_0 ),
        .D(rxeq_fs[1]),
        .Q(rxeq_fs__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__4_n_0 ),
        .D(rxeq_fs[2]),
        .Q(rxeq_fs__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__4_n_0 ),
        .D(rxeq_fs[3]),
        .Q(rxeq_fs__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__4_n_0 ),
        .D(rxeq_fs[4]),
        .Q(rxeq_fs__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__4_n_0 ),
        .D(rxeq_fs[5]),
        .Q(rxeq_fs__0[5]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[0]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_lf[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[1]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_lf[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[2]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_lf[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[3]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_lf[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[4]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_lf[4]));
  LUT6 #(
    .INIT(64'hFF000000000080FF)) 
    \rxeq_lf[5]_i_1__4 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\rxeq_cnt_reg_n_0_[2] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I5(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_lf[5]_i_1__4_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[5]_i_2__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_lf[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__4_n_0 ),
        .D(rxeq_lf[0]),
        .Q(rxeq_lf__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__4_n_0 ),
        .D(rxeq_lf[1]),
        .Q(rxeq_lf__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__4_n_0 ),
        .D(rxeq_lf[2]),
        .Q(rxeq_lf__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__4_n_0 ),
        .D(rxeq_lf[3]),
        .Q(rxeq_lf__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__4_n_0 ),
        .D(rxeq_lf[4]),
        .Q(rxeq_lf__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__4_n_0 ),
        .D(rxeq_lf[5]),
        .Q(rxeq_lf__0[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[0]),
        .Q(rxeq_lffs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[1]),
        .Q(rxeq_lffs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[2]),
        .Q(rxeq_lffs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[3]),
        .Q(rxeq_lffs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[4]),
        .Q(rxeq_lffs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[5]),
        .Q(rxeq_lffs_reg2[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_new_txcoeff_req_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_3),
        .Q(rxeq_new_txcoeff_req_reg_n_0),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[0]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[0]),
        .I4(\rxeq_preset[2]_i_2__4_n_0 ),
        .I5(rxeq_preset__0[0]),
        .O(\rxeq_preset[0]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[1]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[1]),
        .I4(\rxeq_preset[2]_i_2__4_n_0 ),
        .I5(rxeq_preset__0[1]),
        .O(\rxeq_preset[1]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[2]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[2]),
        .I4(\rxeq_preset[2]_i_2__4_n_0 ),
        .I5(rxeq_preset__0[2]),
        .O(\rxeq_preset[2]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hF00400FF)) 
    \rxeq_preset[2]_i_2__4 
       (.I0(rxeq_control_reg2[1]),
        .I1(rxeq_control_reg2[0]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_preset[2]_i_2__4_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[0]),
        .Q(rxeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[1]),
        .Q(rxeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[2]),
        .Q(rxeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[0]_i_1__4_n_0 ),
        .Q(rxeq_preset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[1]_i_1__4_n_0 ),
        .Q(rxeq_preset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[2]_i_1__4_n_0 ),
        .Q(rxeq_preset__0[2]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h04)) 
    rxeq_preset_valid_i_1__4
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(rxeq_preset_valid));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_preset_valid_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid),
        .Q(rxeq_preset_valid_reg_n_0),
        .R(RST_CPLLRESET));
  PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_74 rxeq_scan_i
       (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}),
        .\FSM_sequential_fsm_rx_reg[0] (\FSM_sequential_fsm_rx[0]_i_2__4_n_0 ),
        .\FSM_sequential_fsm_rx_reg[2] ({\FSM_sequential_fsm_rx_reg_n_0_[2] ,\FSM_sequential_fsm_rx_reg_n_0_[1] ,\FSM_sequential_fsm_rx_reg_n_0_[0] }),
        .Q(rxeq_txpreset__0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE),
        .out(rxeq_control_reg2),
        .pclk_sel_reg(pclk_sel_reg),
        .rxeq_adapt_done_reg(rxeq_scan_i_n_4),
        .rxeq_adapt_done_reg_reg(rxeq_scan_i_n_5),
        .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_reg_n_0),
        .\rxeq_cnt_reg[1] (\FSM_sequential_fsm_rx[0]_i_3__4_n_0 ),
        .\rxeq_cnt_reg[1]_0 (\FSM_sequential_fsm_rx[2]_i_2__4_n_0 ),
        .\rxeq_control_reg2_reg[0] (\FSM_sequential_fsm_rx[2]_i_3__4_n_0 ),
        .\rxeq_fs_reg[5] (rxeq_fs__0),
        .\rxeq_lf_reg[5] (rxeq_lf__0),
        .rxeq_new_txcoeff_req_reg(rxeq_scan_i_n_3),
        .rxeq_new_txcoeff_req_reg_0(rxeq_new_txcoeff_req_reg_n_0),
        .\rxeq_preset_reg[2] (rxeq_preset__0),
        .rxeq_preset_valid_reg(rxeq_preset_valid_reg_n_0),
        .\rxeq_txcoeff_reg[17] ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,rxeq_txcoeff__0}));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[0]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[6] ),
        .O(rxeq_txcoeff[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[10]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[16] ),
        .O(rxeq_txcoeff[10]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[11]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[17] ),
        .O(rxeq_txcoeff[11]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[12]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[0]),
        .O(rxeq_txcoeff[12]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[13]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[1]),
        .O(rxeq_txcoeff[13]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[14]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[2]),
        .O(rxeq_txcoeff[14]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[15]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[3]),
        .O(rxeq_txcoeff[15]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[16]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[4]),
        .O(rxeq_txcoeff[16]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[17]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[5]),
        .O(rxeq_txcoeff[17]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[1]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[7] ),
        .O(rxeq_txcoeff[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[2]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[8] ),
        .O(rxeq_txcoeff[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[3]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[9] ),
        .O(rxeq_txcoeff[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[4]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[10] ),
        .O(rxeq_txcoeff[4]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[5]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[11] ),
        .O(rxeq_txcoeff[5]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[6]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[12] ),
        .O(rxeq_txcoeff[6]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[7]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[13] ),
        .O(rxeq_txcoeff[7]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[8]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[14] ),
        .O(rxeq_txcoeff[8]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[9]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[15] ),
        .O(rxeq_txcoeff[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[0]),
        .Q(rxeq_txcoeff__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[10]),
        .Q(\rxeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[11]),
        .Q(\rxeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[12]),
        .Q(\rxeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[13]),
        .Q(\rxeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[14]),
        .Q(\rxeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[15]),
        .Q(\rxeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[16]),
        .Q(\rxeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[17]),
        .Q(\rxeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[1]),
        .Q(rxeq_txcoeff__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[2]),
        .Q(rxeq_txcoeff__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[3]),
        .Q(rxeq_txcoeff__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[4]),
        .Q(rxeq_txcoeff__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[5]),
        .Q(rxeq_txcoeff__0[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[6]),
        .Q(\rxeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[7]),
        .Q(\rxeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[8]),
        .Q(\rxeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txcoeff[9]),
        .Q(\rxeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[0]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[0]),
        .O(rxeq_txpreset[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[1]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[1]),
        .O(rxeq_txpreset[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[2]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[2]),
        .O(rxeq_txpreset[2]));
  LUT4 #(
    .INIT(16'hF405)) 
    \rxeq_txpreset[3]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_txpreset[3]_i_1__4_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[3]_i_2__4 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[3]),
        .O(rxeq_txpreset[3]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[0]),
        .Q(rxeq_txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[1]),
        .Q(rxeq_txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[2]),
        .Q(rxeq_txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[3]),
        .Q(rxeq_txpreset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txpreset[0]),
        .Q(rxeq_txpreset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txpreset[1]),
        .Q(rxeq_txpreset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txpreset[2]),
        .Q(rxeq_txpreset__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__4_n_0 ),
        .D(rxeq_txpreset[3]),
        .Q(rxeq_txpreset__0[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_en_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_en_reg1),
        .Q(rxeq_user_en_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_mode_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_mode_reg1),
        .Q(rxeq_user_mode_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[0]),
        .Q(rxeq_user_txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[10]),
        .Q(rxeq_user_txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[11]),
        .Q(rxeq_user_txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[12]),
        .Q(rxeq_user_txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[13]),
        .Q(rxeq_user_txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[14]),
        .Q(rxeq_user_txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[15]),
        .Q(rxeq_user_txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[16]),
        .Q(rxeq_user_txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[17]),
        .Q(rxeq_user_txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[1]),
        .Q(rxeq_user_txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[2]),
        .Q(rxeq_user_txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[3]),
        .Q(rxeq_user_txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[4]),
        .Q(rxeq_user_txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[5]),
        .Q(rxeq_user_txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[6]),
        .Q(rxeq_user_txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[7]),
        .Q(rxeq_user_txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[8]),
        .Q(rxeq_user_txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[9]),
        .Q(rxeq_user_txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[0]),
        .Q(txeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[1]),
        .Q(txeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[0]),
        .Q(txeq_deemph_reg2[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[1]),
        .Q(txeq_deemph_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[2]),
        .Q(txeq_deemph_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[3]),
        .Q(txeq_deemph_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[4]),
        .Q(txeq_deemph_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[5]),
        .Q(txeq_deemph_reg2[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00001000)) 
    \txeq_preset[0]_i_1__4 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[0]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hAEABBABB)) 
    \txeq_preset[10]_i_1__4 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[10]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hAEAABABB)) 
    \txeq_preset[11]_i_1__4 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[11]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h00001574)) 
    \txeq_preset[12]_i_1__4 
       (.I0(txeq_preset_reg2[3]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[12]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[13]_i_1__4 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[13]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h00000410)) 
    \txeq_preset[14]_i_1__4 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[14]_i_1__4_n_0 ));
  LUT4 #(
    .INIT(16'hAAAB)) 
    \txeq_preset[15]_i_1__4 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .O(\txeq_preset[15]_i_1__4_n_0 ));
  LUT4 #(
    .INIT(16'h0014)) 
    \txeq_preset[16]_i_1__4 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[16]_i_1__4_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \txeq_preset[17]_i_1__1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(RST_CPLLRESET),
        .O(\txeq_preset[17]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hAAEABABB)) 
    \txeq_preset[17]_i_2__4 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[17]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[1]_i_1__4 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[1]_i_1__4_n_0 ));
  LUT4 #(
    .INIT(16'h00C8)) 
    \txeq_preset[2]_i_1__4 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[2]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h00003424)) 
    \txeq_preset[3]_i_1__4 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[3]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h00000408)) 
    \txeq_preset[7]_i_1__4 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[7]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hAAAEBBFB)) 
    \txeq_preset[8]_i_1__4 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[8]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hAEAEBABB)) 
    \txeq_preset[9]_i_1__4 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[9]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    txeq_preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .Q(txeq_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[0]),
        .Q(txeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[1]),
        .Q(txeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[2]),
        .Q(txeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[3]),
        .Q(txeq_preset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[0]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[10]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[11]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[12]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[13]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[14]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[15]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[16]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[17]_i_2__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[1]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[2]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[3]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[7]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[8]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__1_n_0 ),
        .D(\txeq_preset[9]_i_1__4_n_0 ),
        .Q(\txeq_preset_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[0]_i_1__4 
       (.I0(\txeq_txcoeff_reg_n_0_[6] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\txeq_preset_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[0]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[0]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hAA208A00)) 
    \txeq_txcoeff[0]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .O(\txeq_txcoeff[0]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[10]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[10] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[9] ),
        .I4(\txeq_txcoeff[10]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[10]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[10]_i_2__4 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[16] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[10]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[11]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[11] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[10] ),
        .I4(\txeq_txcoeff[11]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[11]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[11]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[18] ),
        .I2(\txeq_txcoeff_reg_n_0_[17] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[11]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[12]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[11] ),
        .I4(\txeq_txcoeff[12]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[12]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[12]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[0]),
        .I2(\txeq_txcoeff_reg_n_0_[18] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[12]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[13]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[13] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[12] ),
        .I4(\txeq_txcoeff[13]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[13]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[13]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[1]),
        .I2(txeq_deemph_reg2[0]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[13]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[14]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[14] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[13] ),
        .I4(\txeq_txcoeff[14]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[14]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[14]_i_2__4 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[14]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[15]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[15] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[14] ),
        .I4(\txeq_txcoeff[15]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[15]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[15]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[3]),
        .I2(txeq_deemph_reg2[2]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[15]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[16]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[16] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[15] ),
        .I4(\txeq_txcoeff[16]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[16]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[16]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[4]),
        .I2(txeq_deemph_reg2[3]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[16]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[17]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[17] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[16] ),
        .I4(\txeq_txcoeff[17]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[17]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[17]_i_2__4 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[4]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[17]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h5557FF5755575557)) 
    \txeq_txcoeff[18]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx[1]_i_2__4_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[0]),
        .I5(txeq_control_reg2[1]),
        .O(\txeq_txcoeff[18]_i_1__4_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \txeq_txcoeff[18]_i_2__4 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\txeq_txcoeff[18]_i_3__4_n_0 ),
        .O(\txeq_txcoeff[18]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'hF888F8F888888888)) 
    \txeq_txcoeff[18]_i_3__4 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(txeq_deemph_reg2[5]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[18]_i_3__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[1]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[1]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[1]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[1]_i_2__4 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[1]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[2]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[1] ),
        .I4(\txeq_txcoeff[2]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[2]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[2]_i_2__4 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[8] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[2]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[3]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[2] ),
        .I4(\txeq_txcoeff[3]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[3]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[3]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .I2(\txeq_txcoeff_reg_n_0_[9] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[3]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[4]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[3] ),
        .I4(\txeq_txcoeff[4]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[4]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[4]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .I2(\txeq_txcoeff_reg_n_0_[10] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[4]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[5]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[5] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[4] ),
        .I4(\txeq_txcoeff[5]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[5]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[5]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .I2(\txeq_txcoeff_reg_n_0_[11] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[5]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[6]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[5] ),
        .I4(\txeq_txcoeff[6]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[6]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[6]_i_2__4 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[12] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[6]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[7]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[7] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff[7]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[7]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[7]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .I2(\txeq_txcoeff_reg_n_0_[13] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[7]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[8]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[8] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[7] ),
        .I4(\txeq_txcoeff[8]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[8]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[8]_i_2__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .I2(\txeq_txcoeff_reg_n_0_[14] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[8]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[9]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[9] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[8] ),
        .I4(\txeq_txcoeff[9]_i_2__4_n_0 ),
        .O(\txeq_txcoeff[9]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[9]_i_2__4 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[15] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[9]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'h4444F444)) 
    \txeq_txcoeff_cnt[0]_i_1__4 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(txeq_control_reg2[1]),
        .I4(txeq_control_reg2[0]),
        .O(txeq_txcoeff_cnt[0]));
  LUT3 #(
    .INIT(8'h28)) 
    \txeq_txcoeff_cnt[1]_i_1__4 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(txeq_txcoeff_cnt[1]));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[0]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[1]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[0]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[10]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[11]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[12]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[13]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[14]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[15]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[16]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[17]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[18] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[18]_i_2__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[1]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[2]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[3]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[4]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[5]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[6]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[7]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[8]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__4_n_0 ),
        .D(\txeq_txcoeff[9]_i_1__4_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_eq" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_62
   (TXPRECURSOR,
    TXMAINCURSOR,
    TXPOSTCURSOR,
    USER_RXEQ_ADAPT_DONE,
    RST_CPLLRESET,
    pclk_sel_reg,
    rate_gen3);
  output [4:0]TXPRECURSOR;
  output [6:0]TXMAINCURSOR;
  output [4:0]TXPOSTCURSOR;
  output USER_RXEQ_ADAPT_DONE;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]rate_gen3;

  wire \FSM_onehot_fsm_tx[1]_i_1__5_n_0 ;
  wire \FSM_onehot_fsm_tx[1]_i_2__5_n_0 ;
  wire \FSM_onehot_fsm_tx[2]_i_1__5_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_1__5_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_2__5_n_0 ;
  wire \FSM_onehot_fsm_tx[4]_i_1__5_n_0 ;
  wire \FSM_onehot_fsm_tx[5]_i_1__5_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_1__5_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_2__5_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_3__5_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[4] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[5] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[6] ;
  wire \FSM_sequential_fsm_rx[0]_i_2__5_n_0 ;
  wire \FSM_sequential_fsm_rx[0]_i_3__5_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_2__5_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_3__5_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[2] ;
  wire RST_CPLLRESET;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_RXEQ_ADAPT_DONE;
  wire gen3_reg1;
  wire gen3_reg2;
  wire pclk_sel_reg;
  wire [0:0]rate_gen3;
  wire rxeq_adapt_done_reg_reg_n_0;
  wire [2:0]rxeq_cnt;
  wire \rxeq_cnt_reg_n_0_[0] ;
  wire \rxeq_cnt_reg_n_0_[1] ;
  wire \rxeq_cnt_reg_n_0_[2] ;
  wire [1:0]rxeq_control_reg1;
  wire [1:0]rxeq_control_reg2;
  wire [5:0]rxeq_fs;
  wire \rxeq_fs[5]_i_1__5_n_0 ;
  wire [5:0]rxeq_fs__0;
  wire [5:0]rxeq_lf;
  wire \rxeq_lf[5]_i_1__5_n_0 ;
  wire [5:0]rxeq_lf__0;
  wire [5:0]rxeq_lffs_reg1;
  wire [5:0]rxeq_lffs_reg2;
  wire rxeq_new_txcoeff_req_reg_n_0;
  wire \rxeq_preset[0]_i_1__5_n_0 ;
  wire \rxeq_preset[1]_i_1__5_n_0 ;
  wire \rxeq_preset[2]_i_1__5_n_0 ;
  wire \rxeq_preset[2]_i_2__5_n_0 ;
  wire [2:0]rxeq_preset__0;
  wire [2:0]rxeq_preset_reg1;
  wire [2:0]rxeq_preset_reg2;
  wire rxeq_preset_valid;
  wire rxeq_preset_valid_reg_n_0;
  wire rxeq_scan_i_n_0;
  wire rxeq_scan_i_n_1;
  wire rxeq_scan_i_n_2;
  wire rxeq_scan_i_n_3;
  wire rxeq_scan_i_n_4;
  wire rxeq_scan_i_n_5;
  wire [17:0]rxeq_txcoeff;
  wire [5:0]rxeq_txcoeff__0;
  wire \rxeq_txcoeff_reg_n_0_[10] ;
  wire \rxeq_txcoeff_reg_n_0_[11] ;
  wire \rxeq_txcoeff_reg_n_0_[12] ;
  wire \rxeq_txcoeff_reg_n_0_[13] ;
  wire \rxeq_txcoeff_reg_n_0_[14] ;
  wire \rxeq_txcoeff_reg_n_0_[15] ;
  wire \rxeq_txcoeff_reg_n_0_[16] ;
  wire \rxeq_txcoeff_reg_n_0_[17] ;
  wire \rxeq_txcoeff_reg_n_0_[6] ;
  wire \rxeq_txcoeff_reg_n_0_[7] ;
  wire \rxeq_txcoeff_reg_n_0_[8] ;
  wire \rxeq_txcoeff_reg_n_0_[9] ;
  wire [3:0]rxeq_txpreset;
  wire \rxeq_txpreset[3]_i_1__5_n_0 ;
  wire [3:0]rxeq_txpreset__0;
  wire [3:0]rxeq_txpreset_reg1;
  wire [3:0]rxeq_txpreset_reg2;
  wire rxeq_user_en_reg1;
  wire rxeq_user_en_reg2;
  wire rxeq_user_mode_reg1;
  wire rxeq_user_mode_reg2;
  wire [17:0]rxeq_user_txcoeff_reg1;
  wire [17:0]rxeq_user_txcoeff_reg2;
  wire [1:0]txeq_control_reg1;
  wire [1:0]txeq_control_reg2;
  wire [5:0]txeq_deemph_reg1;
  wire [5:0]txeq_deemph_reg2;
  wire \txeq_preset[0]_i_1__5_n_0 ;
  wire \txeq_preset[10]_i_1__5_n_0 ;
  wire \txeq_preset[11]_i_1__5_n_0 ;
  wire \txeq_preset[12]_i_1__5_n_0 ;
  wire \txeq_preset[13]_i_1__5_n_0 ;
  wire \txeq_preset[14]_i_1__5_n_0 ;
  wire \txeq_preset[15]_i_1__5_n_0 ;
  wire \txeq_preset[16]_i_1__5_n_0 ;
  wire \txeq_preset[17]_i_1__0_n_0 ;
  wire \txeq_preset[17]_i_2__5_n_0 ;
  wire \txeq_preset[1]_i_1__5_n_0 ;
  wire \txeq_preset[2]_i_1__5_n_0 ;
  wire \txeq_preset[3]_i_1__5_n_0 ;
  wire \txeq_preset[7]_i_1__5_n_0 ;
  wire \txeq_preset[8]_i_1__5_n_0 ;
  wire \txeq_preset[9]_i_1__5_n_0 ;
  wire txeq_preset_done;
  wire [3:0]txeq_preset_reg1;
  wire [3:0]txeq_preset_reg2;
  wire \txeq_preset_reg_n_0_[0] ;
  wire \txeq_preset_reg_n_0_[10] ;
  wire \txeq_preset_reg_n_0_[11] ;
  wire \txeq_preset_reg_n_0_[12] ;
  wire \txeq_preset_reg_n_0_[13] ;
  wire \txeq_preset_reg_n_0_[14] ;
  wire \txeq_preset_reg_n_0_[15] ;
  wire \txeq_preset_reg_n_0_[16] ;
  wire \txeq_preset_reg_n_0_[17] ;
  wire \txeq_preset_reg_n_0_[1] ;
  wire \txeq_preset_reg_n_0_[2] ;
  wire \txeq_preset_reg_n_0_[3] ;
  wire \txeq_preset_reg_n_0_[4] ;
  wire \txeq_preset_reg_n_0_[5] ;
  wire \txeq_preset_reg_n_0_[6] ;
  wire \txeq_preset_reg_n_0_[7] ;
  wire \txeq_preset_reg_n_0_[8] ;
  wire \txeq_preset_reg_n_0_[9] ;
  wire \txeq_txcoeff[0]_i_1__5_n_0 ;
  wire \txeq_txcoeff[0]_i_2__5_n_0 ;
  wire \txeq_txcoeff[10]_i_1__5_n_0 ;
  wire \txeq_txcoeff[10]_i_2__5_n_0 ;
  wire \txeq_txcoeff[11]_i_1__5_n_0 ;
  wire \txeq_txcoeff[11]_i_2__5_n_0 ;
  wire \txeq_txcoeff[12]_i_1__5_n_0 ;
  wire \txeq_txcoeff[12]_i_2__5_n_0 ;
  wire \txeq_txcoeff[13]_i_1__5_n_0 ;
  wire \txeq_txcoeff[13]_i_2__5_n_0 ;
  wire \txeq_txcoeff[14]_i_1__5_n_0 ;
  wire \txeq_txcoeff[14]_i_2__5_n_0 ;
  wire \txeq_txcoeff[15]_i_1__5_n_0 ;
  wire \txeq_txcoeff[15]_i_2__5_n_0 ;
  wire \txeq_txcoeff[16]_i_1__5_n_0 ;
  wire \txeq_txcoeff[16]_i_2__5_n_0 ;
  wire \txeq_txcoeff[17]_i_1__5_n_0 ;
  wire \txeq_txcoeff[17]_i_2__5_n_0 ;
  wire \txeq_txcoeff[18]_i_1__5_n_0 ;
  wire \txeq_txcoeff[18]_i_2__5_n_0 ;
  wire \txeq_txcoeff[18]_i_3__5_n_0 ;
  wire \txeq_txcoeff[1]_i_1__5_n_0 ;
  wire \txeq_txcoeff[1]_i_2__5_n_0 ;
  wire \txeq_txcoeff[2]_i_1__5_n_0 ;
  wire \txeq_txcoeff[2]_i_2__5_n_0 ;
  wire \txeq_txcoeff[3]_i_1__5_n_0 ;
  wire \txeq_txcoeff[3]_i_2__5_n_0 ;
  wire \txeq_txcoeff[4]_i_1__5_n_0 ;
  wire \txeq_txcoeff[4]_i_2__5_n_0 ;
  wire \txeq_txcoeff[5]_i_1__5_n_0 ;
  wire \txeq_txcoeff[5]_i_2__5_n_0 ;
  wire \txeq_txcoeff[6]_i_1__5_n_0 ;
  wire \txeq_txcoeff[6]_i_2__5_n_0 ;
  wire \txeq_txcoeff[7]_i_1__5_n_0 ;
  wire \txeq_txcoeff[7]_i_2__5_n_0 ;
  wire \txeq_txcoeff[8]_i_1__5_n_0 ;
  wire \txeq_txcoeff[8]_i_2__5_n_0 ;
  wire \txeq_txcoeff[9]_i_1__5_n_0 ;
  wire \txeq_txcoeff[9]_i_2__5_n_0 ;
  wire [1:0]txeq_txcoeff_cnt;
  wire \txeq_txcoeff_cnt_reg_n_0_[0] ;
  wire \txeq_txcoeff_cnt_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[0] ;
  wire \txeq_txcoeff_reg_n_0_[10] ;
  wire \txeq_txcoeff_reg_n_0_[11] ;
  wire \txeq_txcoeff_reg_n_0_[12] ;
  wire \txeq_txcoeff_reg_n_0_[13] ;
  wire \txeq_txcoeff_reg_n_0_[14] ;
  wire \txeq_txcoeff_reg_n_0_[15] ;
  wire \txeq_txcoeff_reg_n_0_[16] ;
  wire \txeq_txcoeff_reg_n_0_[17] ;
  wire \txeq_txcoeff_reg_n_0_[18] ;
  wire \txeq_txcoeff_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[2] ;
  wire \txeq_txcoeff_reg_n_0_[3] ;
  wire \txeq_txcoeff_reg_n_0_[4] ;
  wire \txeq_txcoeff_reg_n_0_[5] ;
  wire \txeq_txcoeff_reg_n_0_[6] ;
  wire \txeq_txcoeff_reg_n_0_[7] ;
  wire \txeq_txcoeff_reg_n_0_[8] ;
  wire \txeq_txcoeff_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'h000000FF10101050)) 
    \FSM_onehot_fsm_tx[1]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx[1]_i_2__5_n_0 ),
        .I3(txeq_control_reg2[0]),
        .I4(txeq_control_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[1]_i_1__5_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_onehot_fsm_tx[1]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[1]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h20202F20)) 
    \FSM_onehot_fsm_tx[2]_i_1__5 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I4(txeq_preset_done),
        .O(\FSM_onehot_fsm_tx[2]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h45454545FF454545)) 
    \FSM_onehot_fsm_tx[3]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx[3]_i_2__5_n_0 ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(\FSM_onehot_fsm_tx[3]_i_1__5_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_onehot_fsm_tx[3]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm_tx[3]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \FSM_onehot_fsm_tx[4]_i_1__5 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[4]_i_1__5_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm_tx[5]_i_1__5 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[5]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \FSM_onehot_fsm_tx[6]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx[6]_i_2__5_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_tx[6]_i_3__5_n_0 ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[6]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBBBBBB8)) 
    \FSM_onehot_fsm_tx[6]_i_2__5 
       (.I0(txeq_preset_done),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[6]_i_2__5_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_fsm_tx[6]_i_3__5 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .O(\FSM_onehot_fsm_tx[6]_i_3__5_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[1]_i_1__5_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[2]_i_1__5_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[3]_i_1__5_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[4]_i_1__5_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[5]_i_1__5_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[6]_i_1__5_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h838183C3)) 
    \FSM_sequential_fsm_rx[0]_i_2__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(rxeq_control_reg2[0]),
        .O(\FSM_sequential_fsm_rx[0]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFD000080)) 
    \FSM_sequential_fsm_rx[0]_i_3__5 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm_rx[0]_i_3__5_n_0 ));
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_fsm_rx[2]_i_2__5 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fsm_rx[2]_i_2__5_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_fsm_rx[2]_i_3__5 
       (.I0(rxeq_control_reg2[0]),
        .I1(rxeq_control_reg2[1]),
        .O(\FSM_sequential_fsm_rx[2]_i_3__5_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_2),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_1),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_0),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_31__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .O(TXPOSTCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_32__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[16] ),
        .O(TXPOSTCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_33__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .O(TXPOSTCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_34__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .O(TXPOSTCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_35__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[13] ),
        .O(TXPOSTCURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_36__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[4] ),
        .O(TXPRECURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_37__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[3] ),
        .O(TXPRECURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_38__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[2] ),
        .O(TXPRECURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_39__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[1] ),
        .O(TXPRECURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_40__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[0] ),
        .O(TXPRECURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_41__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .O(TXMAINCURSOR[6]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_42__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .O(TXMAINCURSOR[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_43__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .O(TXMAINCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_44__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[9] ),
        .O(TXMAINCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_45__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[8] ),
        .O(TXMAINCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_46__5 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[7] ),
        .O(TXMAINCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_47__1 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[6] ),
        .O(TXMAINCURSOR[0]));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_4),
        .Q(USER_RXEQ_ADAPT_DONE),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_5),
        .Q(rxeq_adapt_done_reg_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04041C10)) 
    \rxeq_cnt[0]_i_1__5 
       (.I0(\rxeq_cnt_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_cnt[0]));
  LUT5 #(
    .INIT(32'h00424200)) 
    \rxeq_cnt[1]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[1] ),
        .I4(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[1]));
  LUT6 #(
    .INIT(64'h0042420042004200)) 
    \rxeq_cnt[2]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[2] ),
        .I4(\rxeq_cnt_reg_n_0_[1] ),
        .I5(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[2]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[0]),
        .Q(\rxeq_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[1]),
        .Q(\rxeq_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[2]),
        .Q(\rxeq_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[0]),
        .Q(rxeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[1]),
        .Q(rxeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[0]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_fs[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[1]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_fs[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[2]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_fs[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[3]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_fs[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[4]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_fs[4]));
  LUT4 #(
    .INIT(16'hC203)) 
    \rxeq_fs[5]_i_1__5 
       (.I0(rxeq_control_reg2[1]),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_fs[5]_i_1__5_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[5]_i_2__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_fs[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__5_n_0 ),
        .D(rxeq_fs[0]),
        .Q(rxeq_fs__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__5_n_0 ),
        .D(rxeq_fs[1]),
        .Q(rxeq_fs__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__5_n_0 ),
        .D(rxeq_fs[2]),
        .Q(rxeq_fs__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__5_n_0 ),
        .D(rxeq_fs[3]),
        .Q(rxeq_fs__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__5_n_0 ),
        .D(rxeq_fs[4]),
        .Q(rxeq_fs__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__5_n_0 ),
        .D(rxeq_fs[5]),
        .Q(rxeq_fs__0[5]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[0]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_lf[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[1]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_lf[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[2]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_lf[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[3]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_lf[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[4]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_lf[4]));
  LUT6 #(
    .INIT(64'hFF000000000080FF)) 
    \rxeq_lf[5]_i_1__5 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\rxeq_cnt_reg_n_0_[2] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I5(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_lf[5]_i_1__5_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[5]_i_2__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_lf[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__5_n_0 ),
        .D(rxeq_lf[0]),
        .Q(rxeq_lf__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__5_n_0 ),
        .D(rxeq_lf[1]),
        .Q(rxeq_lf__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__5_n_0 ),
        .D(rxeq_lf[2]),
        .Q(rxeq_lf__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__5_n_0 ),
        .D(rxeq_lf[3]),
        .Q(rxeq_lf__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__5_n_0 ),
        .D(rxeq_lf[4]),
        .Q(rxeq_lf__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__5_n_0 ),
        .D(rxeq_lf[5]),
        .Q(rxeq_lf__0[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[0]),
        .Q(rxeq_lffs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[1]),
        .Q(rxeq_lffs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[2]),
        .Q(rxeq_lffs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[3]),
        .Q(rxeq_lffs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[4]),
        .Q(rxeq_lffs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[5]),
        .Q(rxeq_lffs_reg2[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_new_txcoeff_req_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_3),
        .Q(rxeq_new_txcoeff_req_reg_n_0),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[0]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[0]),
        .I4(\rxeq_preset[2]_i_2__5_n_0 ),
        .I5(rxeq_preset__0[0]),
        .O(\rxeq_preset[0]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[1]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[1]),
        .I4(\rxeq_preset[2]_i_2__5_n_0 ),
        .I5(rxeq_preset__0[1]),
        .O(\rxeq_preset[1]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[2]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[2]),
        .I4(\rxeq_preset[2]_i_2__5_n_0 ),
        .I5(rxeq_preset__0[2]),
        .O(\rxeq_preset[2]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hF00400FF)) 
    \rxeq_preset[2]_i_2__5 
       (.I0(rxeq_control_reg2[1]),
        .I1(rxeq_control_reg2[0]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_preset[2]_i_2__5_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[0]),
        .Q(rxeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[1]),
        .Q(rxeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[2]),
        .Q(rxeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[0]_i_1__5_n_0 ),
        .Q(rxeq_preset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[1]_i_1__5_n_0 ),
        .Q(rxeq_preset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[2]_i_1__5_n_0 ),
        .Q(rxeq_preset__0[2]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h04)) 
    rxeq_preset_valid_i_1__5
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(rxeq_preset_valid));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_preset_valid_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid),
        .Q(rxeq_preset_valid_reg_n_0),
        .R(RST_CPLLRESET));
  PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_72 rxeq_scan_i
       (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}),
        .\FSM_sequential_fsm_rx_reg[0] (\FSM_sequential_fsm_rx[0]_i_2__5_n_0 ),
        .\FSM_sequential_fsm_rx_reg[2] ({\FSM_sequential_fsm_rx_reg_n_0_[2] ,\FSM_sequential_fsm_rx_reg_n_0_[1] ,\FSM_sequential_fsm_rx_reg_n_0_[0] }),
        .Q(rxeq_txpreset__0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE),
        .out(rxeq_control_reg2),
        .pclk_sel_reg(pclk_sel_reg),
        .rxeq_adapt_done_reg(rxeq_scan_i_n_4),
        .rxeq_adapt_done_reg_reg(rxeq_scan_i_n_5),
        .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_reg_n_0),
        .\rxeq_cnt_reg[1] (\FSM_sequential_fsm_rx[0]_i_3__5_n_0 ),
        .\rxeq_cnt_reg[1]_0 (\FSM_sequential_fsm_rx[2]_i_2__5_n_0 ),
        .\rxeq_control_reg2_reg[0] (\FSM_sequential_fsm_rx[2]_i_3__5_n_0 ),
        .\rxeq_fs_reg[5] (rxeq_fs__0),
        .\rxeq_lf_reg[5] (rxeq_lf__0),
        .rxeq_new_txcoeff_req_reg(rxeq_scan_i_n_3),
        .rxeq_new_txcoeff_req_reg_0(rxeq_new_txcoeff_req_reg_n_0),
        .\rxeq_preset_reg[2] (rxeq_preset__0),
        .rxeq_preset_valid_reg(rxeq_preset_valid_reg_n_0),
        .\rxeq_txcoeff_reg[17] ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,rxeq_txcoeff__0}));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[0]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[6] ),
        .O(rxeq_txcoeff[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[10]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[16] ),
        .O(rxeq_txcoeff[10]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[11]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[17] ),
        .O(rxeq_txcoeff[11]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[12]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[0]),
        .O(rxeq_txcoeff[12]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[13]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[1]),
        .O(rxeq_txcoeff[13]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[14]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[2]),
        .O(rxeq_txcoeff[14]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[15]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[3]),
        .O(rxeq_txcoeff[15]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[16]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[4]),
        .O(rxeq_txcoeff[16]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[17]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[5]),
        .O(rxeq_txcoeff[17]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[1]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[7] ),
        .O(rxeq_txcoeff[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[2]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[8] ),
        .O(rxeq_txcoeff[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[3]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[9] ),
        .O(rxeq_txcoeff[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[4]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[10] ),
        .O(rxeq_txcoeff[4]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[5]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[11] ),
        .O(rxeq_txcoeff[5]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[6]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[12] ),
        .O(rxeq_txcoeff[6]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[7]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[13] ),
        .O(rxeq_txcoeff[7]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[8]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[14] ),
        .O(rxeq_txcoeff[8]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[9]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[15] ),
        .O(rxeq_txcoeff[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[0]),
        .Q(rxeq_txcoeff__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[10]),
        .Q(\rxeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[11]),
        .Q(\rxeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[12]),
        .Q(\rxeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[13]),
        .Q(\rxeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[14]),
        .Q(\rxeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[15]),
        .Q(\rxeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[16]),
        .Q(\rxeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[17]),
        .Q(\rxeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[1]),
        .Q(rxeq_txcoeff__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[2]),
        .Q(rxeq_txcoeff__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[3]),
        .Q(rxeq_txcoeff__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[4]),
        .Q(rxeq_txcoeff__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[5]),
        .Q(rxeq_txcoeff__0[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[6]),
        .Q(\rxeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[7]),
        .Q(\rxeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[8]),
        .Q(\rxeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txcoeff[9]),
        .Q(\rxeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[0]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[0]),
        .O(rxeq_txpreset[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[1]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[1]),
        .O(rxeq_txpreset[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[2]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[2]),
        .O(rxeq_txpreset[2]));
  LUT4 #(
    .INIT(16'hF405)) 
    \rxeq_txpreset[3]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_txpreset[3]_i_1__5_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[3]_i_2__5 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[3]),
        .O(rxeq_txpreset[3]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[0]),
        .Q(rxeq_txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[1]),
        .Q(rxeq_txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[2]),
        .Q(rxeq_txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[3]),
        .Q(rxeq_txpreset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txpreset[0]),
        .Q(rxeq_txpreset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txpreset[1]),
        .Q(rxeq_txpreset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txpreset[2]),
        .Q(rxeq_txpreset__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__5_n_0 ),
        .D(rxeq_txpreset[3]),
        .Q(rxeq_txpreset__0[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_en_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_en_reg1),
        .Q(rxeq_user_en_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_mode_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_mode_reg1),
        .Q(rxeq_user_mode_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[0]),
        .Q(rxeq_user_txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[10]),
        .Q(rxeq_user_txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[11]),
        .Q(rxeq_user_txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[12]),
        .Q(rxeq_user_txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[13]),
        .Q(rxeq_user_txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[14]),
        .Q(rxeq_user_txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[15]),
        .Q(rxeq_user_txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[16]),
        .Q(rxeq_user_txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[17]),
        .Q(rxeq_user_txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[1]),
        .Q(rxeq_user_txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[2]),
        .Q(rxeq_user_txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[3]),
        .Q(rxeq_user_txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[4]),
        .Q(rxeq_user_txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[5]),
        .Q(rxeq_user_txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[6]),
        .Q(rxeq_user_txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[7]),
        .Q(rxeq_user_txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[8]),
        .Q(rxeq_user_txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[9]),
        .Q(rxeq_user_txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[0]),
        .Q(txeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[1]),
        .Q(txeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[0]),
        .Q(txeq_deemph_reg2[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[1]),
        .Q(txeq_deemph_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[2]),
        .Q(txeq_deemph_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[3]),
        .Q(txeq_deemph_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[4]),
        .Q(txeq_deemph_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[5]),
        .Q(txeq_deemph_reg2[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00001000)) 
    \txeq_preset[0]_i_1__5 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[0]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hAEABBABB)) 
    \txeq_preset[10]_i_1__5 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[10]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hAEAABABB)) 
    \txeq_preset[11]_i_1__5 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[11]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h00001574)) 
    \txeq_preset[12]_i_1__5 
       (.I0(txeq_preset_reg2[3]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[12]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[13]_i_1__5 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[13]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h00000410)) 
    \txeq_preset[14]_i_1__5 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[14]_i_1__5_n_0 ));
  LUT4 #(
    .INIT(16'hAAAB)) 
    \txeq_preset[15]_i_1__5 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .O(\txeq_preset[15]_i_1__5_n_0 ));
  LUT4 #(
    .INIT(16'h0014)) 
    \txeq_preset[16]_i_1__5 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[16]_i_1__5_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \txeq_preset[17]_i_1__0 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(RST_CPLLRESET),
        .O(\txeq_preset[17]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hAAEABABB)) 
    \txeq_preset[17]_i_2__5 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[17]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[1]_i_1__5 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[1]_i_1__5_n_0 ));
  LUT4 #(
    .INIT(16'h00C8)) 
    \txeq_preset[2]_i_1__5 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[2]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h00003424)) 
    \txeq_preset[3]_i_1__5 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[3]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h00000408)) 
    \txeq_preset[7]_i_1__5 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[7]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hAAAEBBFB)) 
    \txeq_preset[8]_i_1__5 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[8]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hAEAEBABB)) 
    \txeq_preset[9]_i_1__5 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[9]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    txeq_preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .Q(txeq_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[0]),
        .Q(txeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[1]),
        .Q(txeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[2]),
        .Q(txeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[3]),
        .Q(txeq_preset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[0]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[10]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[11]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[12]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[13]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[14]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[15]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[16]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[17]_i_2__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[1]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[2]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[3]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[7]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[8]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1__0_n_0 ),
        .D(\txeq_preset[9]_i_1__5_n_0 ),
        .Q(\txeq_preset_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[0]_i_1__5 
       (.I0(\txeq_txcoeff_reg_n_0_[6] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\txeq_preset_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[0]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[0]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hAA208A00)) 
    \txeq_txcoeff[0]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .O(\txeq_txcoeff[0]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[10]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[10] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[9] ),
        .I4(\txeq_txcoeff[10]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[10]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[10]_i_2__5 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[16] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[10]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[11]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[11] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[10] ),
        .I4(\txeq_txcoeff[11]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[11]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[11]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[18] ),
        .I2(\txeq_txcoeff_reg_n_0_[17] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[11]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[12]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[11] ),
        .I4(\txeq_txcoeff[12]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[12]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[12]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[0]),
        .I2(\txeq_txcoeff_reg_n_0_[18] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[12]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[13]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[13] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[12] ),
        .I4(\txeq_txcoeff[13]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[13]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[13]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[1]),
        .I2(txeq_deemph_reg2[0]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[13]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[14]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[14] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[13] ),
        .I4(\txeq_txcoeff[14]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[14]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[14]_i_2__5 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[14]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[15]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[15] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[14] ),
        .I4(\txeq_txcoeff[15]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[15]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[15]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[3]),
        .I2(txeq_deemph_reg2[2]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[15]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[16]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[16] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[15] ),
        .I4(\txeq_txcoeff[16]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[16]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[16]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[4]),
        .I2(txeq_deemph_reg2[3]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[16]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[17]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[17] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[16] ),
        .I4(\txeq_txcoeff[17]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[17]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[17]_i_2__5 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[4]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[17]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h5557FF5755575557)) 
    \txeq_txcoeff[18]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx[1]_i_2__5_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[0]),
        .I5(txeq_control_reg2[1]),
        .O(\txeq_txcoeff[18]_i_1__5_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \txeq_txcoeff[18]_i_2__5 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\txeq_txcoeff[18]_i_3__5_n_0 ),
        .O(\txeq_txcoeff[18]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'hF888F8F888888888)) 
    \txeq_txcoeff[18]_i_3__5 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(txeq_deemph_reg2[5]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[18]_i_3__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[1]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[1]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[1]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[1]_i_2__5 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[1]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[2]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[1] ),
        .I4(\txeq_txcoeff[2]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[2]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[2]_i_2__5 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[8] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[2]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[3]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[2] ),
        .I4(\txeq_txcoeff[3]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[3]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[3]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .I2(\txeq_txcoeff_reg_n_0_[9] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[3]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[4]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[3] ),
        .I4(\txeq_txcoeff[4]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[4]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[4]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .I2(\txeq_txcoeff_reg_n_0_[10] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[4]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[5]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[5] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[4] ),
        .I4(\txeq_txcoeff[5]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[5]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[5]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .I2(\txeq_txcoeff_reg_n_0_[11] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[5]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[6]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[5] ),
        .I4(\txeq_txcoeff[6]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[6]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[6]_i_2__5 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[12] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[6]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[7]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[7] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff[7]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[7]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[7]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .I2(\txeq_txcoeff_reg_n_0_[13] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[7]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[8]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[8] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[7] ),
        .I4(\txeq_txcoeff[8]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[8]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[8]_i_2__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .I2(\txeq_txcoeff_reg_n_0_[14] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[8]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[9]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[9] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[8] ),
        .I4(\txeq_txcoeff[9]_i_2__5_n_0 ),
        .O(\txeq_txcoeff[9]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[9]_i_2__5 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[15] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[9]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h4444F444)) 
    \txeq_txcoeff_cnt[0]_i_1__5 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(txeq_control_reg2[1]),
        .I4(txeq_control_reg2[0]),
        .O(txeq_txcoeff_cnt[0]));
  LUT3 #(
    .INIT(8'h28)) 
    \txeq_txcoeff_cnt[1]_i_1__5 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(txeq_txcoeff_cnt[1]));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[0]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[1]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[0]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[10]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[11]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[12]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[13]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[14]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[15]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[16]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[17]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[18] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[18]_i_2__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[1]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[2]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[3]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[4]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[5]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[6]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[7]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[8]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__5_n_0 ),
        .D(\txeq_txcoeff[9]_i_1__5_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_eq" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_68
   (TXPRECURSOR,
    TXMAINCURSOR,
    TXPOSTCURSOR,
    USER_RXEQ_ADAPT_DONE,
    RST_CPLLRESET,
    pclk_sel_reg,
    gen3_reg);
  output [4:0]TXPRECURSOR;
  output [6:0]TXMAINCURSOR;
  output [4:0]TXPOSTCURSOR;
  output USER_RXEQ_ADAPT_DONE;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]gen3_reg;

  wire \FSM_onehot_fsm_tx[1]_i_1__6_n_0 ;
  wire \FSM_onehot_fsm_tx[1]_i_2__6_n_0 ;
  wire \FSM_onehot_fsm_tx[2]_i_1__6_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_1__6_n_0 ;
  wire \FSM_onehot_fsm_tx[3]_i_2__6_n_0 ;
  wire \FSM_onehot_fsm_tx[4]_i_1__6_n_0 ;
  wire \FSM_onehot_fsm_tx[5]_i_1__6_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_1__6_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_2__6_n_0 ;
  wire \FSM_onehot_fsm_tx[6]_i_3__6_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[4] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[5] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_tx_reg_n_0_[6] ;
  wire \FSM_sequential_fsm_rx[0]_i_2__6_n_0 ;
  wire \FSM_sequential_fsm_rx[0]_i_3__6_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_2__6_n_0 ;
  wire \FSM_sequential_fsm_rx[2]_i_3__6_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_rx_reg_n_0_[2] ;
  wire RST_CPLLRESET;
  wire [6:0]TXMAINCURSOR;
  wire [4:0]TXPOSTCURSOR;
  wire [4:0]TXPRECURSOR;
  wire USER_RXEQ_ADAPT_DONE;
  wire [0:0]gen3_reg;
  wire gen3_reg1;
  wire gen3_reg2;
  wire pclk_sel_reg;
  wire rxeq_adapt_done_reg_reg_n_0;
  wire [2:0]rxeq_cnt;
  wire \rxeq_cnt_reg_n_0_[0] ;
  wire \rxeq_cnt_reg_n_0_[1] ;
  wire \rxeq_cnt_reg_n_0_[2] ;
  wire [1:0]rxeq_control_reg1;
  wire [1:0]rxeq_control_reg2;
  wire [5:0]rxeq_fs;
  wire \rxeq_fs[5]_i_1__6_n_0 ;
  wire [5:0]rxeq_fs__0;
  wire [5:0]rxeq_lf;
  wire \rxeq_lf[5]_i_1__6_n_0 ;
  wire [5:0]rxeq_lf__0;
  wire [5:0]rxeq_lffs_reg1;
  wire [5:0]rxeq_lffs_reg2;
  wire rxeq_new_txcoeff_req_reg_n_0;
  wire \rxeq_preset[0]_i_1__6_n_0 ;
  wire \rxeq_preset[1]_i_1__6_n_0 ;
  wire \rxeq_preset[2]_i_1__6_n_0 ;
  wire \rxeq_preset[2]_i_2__6_n_0 ;
  wire [2:0]rxeq_preset__0;
  wire [2:0]rxeq_preset_reg1;
  wire [2:0]rxeq_preset_reg2;
  wire rxeq_preset_valid;
  wire rxeq_preset_valid_reg_n_0;
  wire rxeq_scan_i_n_0;
  wire rxeq_scan_i_n_1;
  wire rxeq_scan_i_n_2;
  wire rxeq_scan_i_n_3;
  wire rxeq_scan_i_n_4;
  wire rxeq_scan_i_n_5;
  wire [17:0]rxeq_txcoeff;
  wire [5:0]rxeq_txcoeff__0;
  wire \rxeq_txcoeff_reg_n_0_[10] ;
  wire \rxeq_txcoeff_reg_n_0_[11] ;
  wire \rxeq_txcoeff_reg_n_0_[12] ;
  wire \rxeq_txcoeff_reg_n_0_[13] ;
  wire \rxeq_txcoeff_reg_n_0_[14] ;
  wire \rxeq_txcoeff_reg_n_0_[15] ;
  wire \rxeq_txcoeff_reg_n_0_[16] ;
  wire \rxeq_txcoeff_reg_n_0_[17] ;
  wire \rxeq_txcoeff_reg_n_0_[6] ;
  wire \rxeq_txcoeff_reg_n_0_[7] ;
  wire \rxeq_txcoeff_reg_n_0_[8] ;
  wire \rxeq_txcoeff_reg_n_0_[9] ;
  wire [3:0]rxeq_txpreset;
  wire \rxeq_txpreset[3]_i_1__6_n_0 ;
  wire [3:0]rxeq_txpreset__0;
  wire [3:0]rxeq_txpreset_reg1;
  wire [3:0]rxeq_txpreset_reg2;
  wire rxeq_user_en_reg1;
  wire rxeq_user_en_reg2;
  wire rxeq_user_mode_reg1;
  wire rxeq_user_mode_reg2;
  wire [17:0]rxeq_user_txcoeff_reg1;
  wire [17:0]rxeq_user_txcoeff_reg2;
  wire [1:0]txeq_control_reg1;
  wire [1:0]txeq_control_reg2;
  wire [5:0]txeq_deemph_reg1;
  wire [5:0]txeq_deemph_reg2;
  wire \txeq_preset[0]_i_1__6_n_0 ;
  wire \txeq_preset[10]_i_1__6_n_0 ;
  wire \txeq_preset[11]_i_1__6_n_0 ;
  wire \txeq_preset[12]_i_1__6_n_0 ;
  wire \txeq_preset[13]_i_1__6_n_0 ;
  wire \txeq_preset[14]_i_1__6_n_0 ;
  wire \txeq_preset[15]_i_1__6_n_0 ;
  wire \txeq_preset[16]_i_1__6_n_0 ;
  wire \txeq_preset[17]_i_1_n_0 ;
  wire \txeq_preset[17]_i_2__6_n_0 ;
  wire \txeq_preset[1]_i_1__6_n_0 ;
  wire \txeq_preset[2]_i_1__6_n_0 ;
  wire \txeq_preset[3]_i_1__6_n_0 ;
  wire \txeq_preset[7]_i_1__6_n_0 ;
  wire \txeq_preset[8]_i_1__6_n_0 ;
  wire \txeq_preset[9]_i_1__6_n_0 ;
  wire txeq_preset_done;
  wire [3:0]txeq_preset_reg1;
  wire [3:0]txeq_preset_reg2;
  wire \txeq_preset_reg_n_0_[0] ;
  wire \txeq_preset_reg_n_0_[10] ;
  wire \txeq_preset_reg_n_0_[11] ;
  wire \txeq_preset_reg_n_0_[12] ;
  wire \txeq_preset_reg_n_0_[13] ;
  wire \txeq_preset_reg_n_0_[14] ;
  wire \txeq_preset_reg_n_0_[15] ;
  wire \txeq_preset_reg_n_0_[16] ;
  wire \txeq_preset_reg_n_0_[17] ;
  wire \txeq_preset_reg_n_0_[1] ;
  wire \txeq_preset_reg_n_0_[2] ;
  wire \txeq_preset_reg_n_0_[3] ;
  wire \txeq_preset_reg_n_0_[4] ;
  wire \txeq_preset_reg_n_0_[5] ;
  wire \txeq_preset_reg_n_0_[6] ;
  wire \txeq_preset_reg_n_0_[7] ;
  wire \txeq_preset_reg_n_0_[8] ;
  wire \txeq_preset_reg_n_0_[9] ;
  wire \txeq_txcoeff[0]_i_1__6_n_0 ;
  wire \txeq_txcoeff[0]_i_2__6_n_0 ;
  wire \txeq_txcoeff[10]_i_1__6_n_0 ;
  wire \txeq_txcoeff[10]_i_2__6_n_0 ;
  wire \txeq_txcoeff[11]_i_1__6_n_0 ;
  wire \txeq_txcoeff[11]_i_2__6_n_0 ;
  wire \txeq_txcoeff[12]_i_1__6_n_0 ;
  wire \txeq_txcoeff[12]_i_2__6_n_0 ;
  wire \txeq_txcoeff[13]_i_1__6_n_0 ;
  wire \txeq_txcoeff[13]_i_2__6_n_0 ;
  wire \txeq_txcoeff[14]_i_1__6_n_0 ;
  wire \txeq_txcoeff[14]_i_2__6_n_0 ;
  wire \txeq_txcoeff[15]_i_1__6_n_0 ;
  wire \txeq_txcoeff[15]_i_2__6_n_0 ;
  wire \txeq_txcoeff[16]_i_1__6_n_0 ;
  wire \txeq_txcoeff[16]_i_2__6_n_0 ;
  wire \txeq_txcoeff[17]_i_1__6_n_0 ;
  wire \txeq_txcoeff[17]_i_2__6_n_0 ;
  wire \txeq_txcoeff[18]_i_1__6_n_0 ;
  wire \txeq_txcoeff[18]_i_2__6_n_0 ;
  wire \txeq_txcoeff[18]_i_3__6_n_0 ;
  wire \txeq_txcoeff[1]_i_1__6_n_0 ;
  wire \txeq_txcoeff[1]_i_2__6_n_0 ;
  wire \txeq_txcoeff[2]_i_1__6_n_0 ;
  wire \txeq_txcoeff[2]_i_2__6_n_0 ;
  wire \txeq_txcoeff[3]_i_1__6_n_0 ;
  wire \txeq_txcoeff[3]_i_2__6_n_0 ;
  wire \txeq_txcoeff[4]_i_1__6_n_0 ;
  wire \txeq_txcoeff[4]_i_2__6_n_0 ;
  wire \txeq_txcoeff[5]_i_1__6_n_0 ;
  wire \txeq_txcoeff[5]_i_2__6_n_0 ;
  wire \txeq_txcoeff[6]_i_1__6_n_0 ;
  wire \txeq_txcoeff[6]_i_2__6_n_0 ;
  wire \txeq_txcoeff[7]_i_1__6_n_0 ;
  wire \txeq_txcoeff[7]_i_2__6_n_0 ;
  wire \txeq_txcoeff[8]_i_1__6_n_0 ;
  wire \txeq_txcoeff[8]_i_2__6_n_0 ;
  wire \txeq_txcoeff[9]_i_1__6_n_0 ;
  wire \txeq_txcoeff[9]_i_2__6_n_0 ;
  wire [1:0]txeq_txcoeff_cnt;
  wire \txeq_txcoeff_cnt_reg_n_0_[0] ;
  wire \txeq_txcoeff_cnt_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[0] ;
  wire \txeq_txcoeff_reg_n_0_[10] ;
  wire \txeq_txcoeff_reg_n_0_[11] ;
  wire \txeq_txcoeff_reg_n_0_[12] ;
  wire \txeq_txcoeff_reg_n_0_[13] ;
  wire \txeq_txcoeff_reg_n_0_[14] ;
  wire \txeq_txcoeff_reg_n_0_[15] ;
  wire \txeq_txcoeff_reg_n_0_[16] ;
  wire \txeq_txcoeff_reg_n_0_[17] ;
  wire \txeq_txcoeff_reg_n_0_[18] ;
  wire \txeq_txcoeff_reg_n_0_[1] ;
  wire \txeq_txcoeff_reg_n_0_[2] ;
  wire \txeq_txcoeff_reg_n_0_[3] ;
  wire \txeq_txcoeff_reg_n_0_[4] ;
  wire \txeq_txcoeff_reg_n_0_[5] ;
  wire \txeq_txcoeff_reg_n_0_[6] ;
  wire \txeq_txcoeff_reg_n_0_[7] ;
  wire \txeq_txcoeff_reg_n_0_[8] ;
  wire \txeq_txcoeff_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'h000000FF10101050)) 
    \FSM_onehot_fsm_tx[1]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx[1]_i_2__6_n_0 ),
        .I3(txeq_control_reg2[0]),
        .I4(txeq_control_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[1]_i_1__6_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_onehot_fsm_tx[1]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[1]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h20202F20)) 
    \FSM_onehot_fsm_tx[2]_i_1__6 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I4(txeq_preset_done),
        .O(\FSM_onehot_fsm_tx[2]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h45454545FF454545)) 
    \FSM_onehot_fsm_tx[3]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx[3]_i_2__6_n_0 ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[1]),
        .I5(txeq_control_reg2[0]),
        .O(\FSM_onehot_fsm_tx[3]_i_1__6_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \FSM_onehot_fsm_tx[3]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm_tx[3]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \FSM_onehot_fsm_tx[4]_i_1__6 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[4]_i_1__6_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm_tx[5]_i_1__6 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[5]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \FSM_onehot_fsm_tx[6]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx[6]_i_2__6_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_tx[6]_i_3__6_n_0 ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm_tx[6]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBBBBBB8)) 
    \FSM_onehot_fsm_tx[6]_i_2__6 
       (.I0(txeq_preset_done),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I4(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm_tx[6]_i_2__6_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_fsm_tx[6]_i_3__6 
       (.I0(txeq_control_reg2[0]),
        .I1(txeq_control_reg2[1]),
        .O(\FSM_onehot_fsm_tx[6]_i_3__6_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[1]_i_1__6_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[2]_i_1__6_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[3]_i_1__6_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[4]_i_1__6_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[5]_i_1__6_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_tx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx[6]_i_1__6_n_0 ),
        .Q(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h838183C3)) 
    \FSM_sequential_fsm_rx[0]_i_2__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(rxeq_control_reg2[0]),
        .O(\FSM_sequential_fsm_rx[0]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFD000080)) 
    \FSM_sequential_fsm_rx[0]_i_3__6 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm_rx[0]_i_3__6_n_0 ));
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_fsm_rx[2]_i_2__6 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[2] ),
        .I2(\rxeq_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fsm_rx[2]_i_2__6_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_fsm_rx[2]_i_3__6 
       (.I0(rxeq_control_reg2[0]),
        .I1(rxeq_control_reg2[1]),
        .O(\FSM_sequential_fsm_rx[2]_i_3__6_n_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_2),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_1),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_sequential_fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_0),
        .Q(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_31__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[17] ),
        .O(TXPOSTCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_32__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[16] ),
        .O(TXPOSTCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_33__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .O(TXPOSTCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_34__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .O(TXPOSTCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_35__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[13] ),
        .O(TXPOSTCURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_36__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[4] ),
        .O(TXPRECURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_37__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[3] ),
        .O(TXPRECURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_38__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[2] ),
        .O(TXPRECURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_39__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[1] ),
        .O(TXPRECURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_40__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[0] ),
        .O(TXPRECURSOR[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_41__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .O(TXMAINCURSOR[6]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_42__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .O(TXMAINCURSOR[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_43__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .O(TXMAINCURSOR[4]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_44__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[9] ),
        .O(TXMAINCURSOR[3]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_45__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[8] ),
        .O(TXMAINCURSOR[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_46__6 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[7] ),
        .O(TXMAINCURSOR[1]));
  LUT2 #(
    .INIT(4'h8)) 
    \gtx_channel.gtxe2_channel_i_i_47__2 
       (.I0(gen3_reg2),
        .I1(\txeq_txcoeff_reg_n_0_[6] ),
        .O(TXMAINCURSOR[0]));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_4),
        .Q(USER_RXEQ_ADAPT_DONE),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_adapt_done_reg_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_5),
        .Q(rxeq_adapt_done_reg_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04041C10)) 
    \rxeq_cnt[0]_i_1__6 
       (.I0(\rxeq_cnt_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I3(rxeq_control_reg2[1]),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .O(rxeq_cnt[0]));
  LUT5 #(
    .INIT(32'h00424200)) 
    \rxeq_cnt[1]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[1] ),
        .I4(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[1]));
  LUT6 #(
    .INIT(64'h0042420042004200)) 
    \rxeq_cnt[2]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\rxeq_cnt_reg_n_0_[2] ),
        .I4(\rxeq_cnt_reg_n_0_[1] ),
        .I5(\rxeq_cnt_reg_n_0_[0] ),
        .O(rxeq_cnt[2]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[0]),
        .Q(\rxeq_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[1]),
        .Q(\rxeq_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_cnt[2]),
        .Q(\rxeq_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[0]),
        .Q(rxeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_control_reg1[1]),
        .Q(rxeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[0]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_fs[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[1]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_fs[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[2]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_fs[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[3]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_fs[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[4]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_fs[4]));
  LUT4 #(
    .INIT(16'hC203)) 
    \rxeq_fs[5]_i_1__6 
       (.I0(rxeq_control_reg2[1]),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_fs[5]_i_1__6_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_fs[5]_i_2__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_fs[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__6_n_0 ),
        .D(rxeq_fs[0]),
        .Q(rxeq_fs__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__6_n_0 ),
        .D(rxeq_fs[1]),
        .Q(rxeq_fs__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__6_n_0 ),
        .D(rxeq_fs[2]),
        .Q(rxeq_fs__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__6_n_0 ),
        .D(rxeq_fs[3]),
        .Q(rxeq_fs__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__6_n_0 ),
        .D(rxeq_fs[4]),
        .Q(rxeq_fs__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_fs_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_fs[5]_i_1__6_n_0 ),
        .D(rxeq_fs[5]),
        .Q(rxeq_fs__0[5]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[0]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[0]),
        .O(rxeq_lf[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[1]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[1]),
        .O(rxeq_lf[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[2]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[2]),
        .O(rxeq_lf[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[3]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[3]),
        .O(rxeq_lf[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[4]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[4]),
        .O(rxeq_lf[4]));
  LUT6 #(
    .INIT(64'hFF000000000080FF)) 
    \rxeq_lf[5]_i_1__6 
       (.I0(\rxeq_cnt_reg_n_0_[1] ),
        .I1(\rxeq_cnt_reg_n_0_[0] ),
        .I2(\rxeq_cnt_reg_n_0_[2] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I5(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_lf[5]_i_1__6_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_lf[5]_i_2__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(rxeq_lffs_reg2[5]),
        .O(rxeq_lf[5]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__6_n_0 ),
        .D(rxeq_lf[0]),
        .Q(rxeq_lf__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__6_n_0 ),
        .D(rxeq_lf[1]),
        .Q(rxeq_lf__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__6_n_0 ),
        .D(rxeq_lf[2]),
        .Q(rxeq_lf__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__6_n_0 ),
        .D(rxeq_lf[3]),
        .Q(rxeq_lf__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__6_n_0 ),
        .D(rxeq_lf[4]),
        .Q(rxeq_lf__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_lf_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_lf[5]_i_1__6_n_0 ),
        .D(rxeq_lf[5]),
        .Q(rxeq_lf__0[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_lffs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[0]),
        .Q(rxeq_lffs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[1]),
        .Q(rxeq_lffs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[2]),
        .Q(rxeq_lffs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[3]),
        .Q(rxeq_lffs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[4]),
        .Q(rxeq_lffs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_lffs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_lffs_reg1[5]),
        .Q(rxeq_lffs_reg2[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_new_txcoeff_req_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_scan_i_n_3),
        .Q(rxeq_new_txcoeff_req_reg_n_0),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[0]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[0]),
        .I4(\rxeq_preset[2]_i_2__6_n_0 ),
        .I5(rxeq_preset__0[0]),
        .O(\rxeq_preset[0]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[1]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[1]),
        .I4(\rxeq_preset[2]_i_2__6_n_0 ),
        .I5(rxeq_preset__0[1]),
        .O(\rxeq_preset[1]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h3200FFFF32000000)) 
    \rxeq_preset[2]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(rxeq_preset_reg2[2]),
        .I4(\rxeq_preset[2]_i_2__6_n_0 ),
        .I5(rxeq_preset__0[2]),
        .O(\rxeq_preset[2]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hF00400FF)) 
    \rxeq_preset[2]_i_2__6 
       (.I0(rxeq_control_reg2[1]),
        .I1(rxeq_control_reg2[0]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_preset[2]_i_2__6_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[0]),
        .Q(rxeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[1]),
        .Q(rxeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_reg1[2]),
        .Q(rxeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[0]_i_1__6_n_0 ),
        .Q(rxeq_preset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[1]_i_1__6_n_0 ),
        .Q(rxeq_preset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset[2]_i_1__6_n_0 ),
        .Q(rxeq_preset__0[2]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h04)) 
    rxeq_preset_valid_i_1__6
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(rxeq_preset_valid));
  FDRE #(
    .INIT(1'b0)) 
    rxeq_preset_valid_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid),
        .Q(rxeq_preset_valid_reg_n_0),
        .R(RST_CPLLRESET));
  PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan rxeq_scan_i
       (.D({rxeq_scan_i_n_0,rxeq_scan_i_n_1,rxeq_scan_i_n_2}),
        .\FSM_sequential_fsm_rx_reg[0] (\FSM_sequential_fsm_rx[0]_i_2__6_n_0 ),
        .\FSM_sequential_fsm_rx_reg[2] ({\FSM_sequential_fsm_rx_reg_n_0_[2] ,\FSM_sequential_fsm_rx_reg_n_0_[1] ,\FSM_sequential_fsm_rx_reg_n_0_[0] }),
        .Q(rxeq_txpreset__0),
        .RST_CPLLRESET(RST_CPLLRESET),
        .USER_RXEQ_ADAPT_DONE(USER_RXEQ_ADAPT_DONE),
        .out(rxeq_control_reg2),
        .pclk_sel_reg(pclk_sel_reg),
        .rxeq_adapt_done_reg(rxeq_scan_i_n_4),
        .rxeq_adapt_done_reg_reg(rxeq_scan_i_n_5),
        .rxeq_adapt_done_reg_reg_0(rxeq_adapt_done_reg_reg_n_0),
        .\rxeq_cnt_reg[1] (\FSM_sequential_fsm_rx[0]_i_3__6_n_0 ),
        .\rxeq_cnt_reg[1]_0 (\FSM_sequential_fsm_rx[2]_i_2__6_n_0 ),
        .\rxeq_control_reg2_reg[0] (\FSM_sequential_fsm_rx[2]_i_3__6_n_0 ),
        .\rxeq_fs_reg[5] (rxeq_fs__0),
        .\rxeq_lf_reg[5] (rxeq_lf__0),
        .rxeq_new_txcoeff_req_reg(rxeq_scan_i_n_3),
        .rxeq_new_txcoeff_req_reg_0(rxeq_new_txcoeff_req_reg_n_0),
        .\rxeq_preset_reg[2] (rxeq_preset__0),
        .rxeq_preset_valid_reg(rxeq_preset_valid_reg_n_0),
        .\rxeq_txcoeff_reg[17] ({\rxeq_txcoeff_reg_n_0_[17] ,\rxeq_txcoeff_reg_n_0_[16] ,\rxeq_txcoeff_reg_n_0_[15] ,\rxeq_txcoeff_reg_n_0_[14] ,\rxeq_txcoeff_reg_n_0_[13] ,\rxeq_txcoeff_reg_n_0_[12] ,\rxeq_txcoeff_reg_n_0_[11] ,\rxeq_txcoeff_reg_n_0_[10] ,\rxeq_txcoeff_reg_n_0_[9] ,\rxeq_txcoeff_reg_n_0_[8] ,\rxeq_txcoeff_reg_n_0_[7] ,\rxeq_txcoeff_reg_n_0_[6] ,rxeq_txcoeff__0}));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[0]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[6] ),
        .O(rxeq_txcoeff[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[10]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[16] ),
        .O(rxeq_txcoeff[10]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[11]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[17] ),
        .O(rxeq_txcoeff[11]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[12]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[0]),
        .O(rxeq_txcoeff[12]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[13]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[1]),
        .O(rxeq_txcoeff[13]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[14]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[2]),
        .O(rxeq_txcoeff[14]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[15]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[3]),
        .O(rxeq_txcoeff[15]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[16]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[4]),
        .O(rxeq_txcoeff[16]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[17]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(txeq_deemph_reg2[5]),
        .O(rxeq_txcoeff[17]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[1]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[7] ),
        .O(rxeq_txcoeff[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[2]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[8] ),
        .O(rxeq_txcoeff[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[3]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[9] ),
        .O(rxeq_txcoeff[3]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[4]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[10] ),
        .O(rxeq_txcoeff[4]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[5]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[11] ),
        .O(rxeq_txcoeff[5]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[6]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[12] ),
        .O(rxeq_txcoeff[6]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[7]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[13] ),
        .O(rxeq_txcoeff[7]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[8]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[14] ),
        .O(rxeq_txcoeff[8]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txcoeff[9]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(\rxeq_txcoeff_reg_n_0_[15] ),
        .O(rxeq_txcoeff[9]));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[0]),
        .Q(rxeq_txcoeff__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[10]),
        .Q(\rxeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[11]),
        .Q(\rxeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[12]),
        .Q(\rxeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[13]),
        .Q(\rxeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[14]),
        .Q(\rxeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[15]),
        .Q(\rxeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[16]),
        .Q(\rxeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[17]),
        .Q(\rxeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[1]),
        .Q(rxeq_txcoeff__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[2]),
        .Q(rxeq_txcoeff__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[3]),
        .Q(rxeq_txcoeff__0[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[4]),
        .Q(rxeq_txcoeff__0[4]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[5]),
        .Q(rxeq_txcoeff__0[5]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[6]),
        .Q(\rxeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[7]),
        .Q(\rxeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[8]),
        .Q(\rxeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txcoeff[9]),
        .Q(\rxeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[0]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[0]),
        .O(rxeq_txpreset[0]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[1]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[1]),
        .O(rxeq_txpreset[1]));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[2]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[2]),
        .O(rxeq_txpreset[2]));
  LUT4 #(
    .INIT(16'hF405)) 
    \rxeq_txpreset[3]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(rxeq_control_reg2[1]),
        .I2(\FSM_sequential_fsm_rx_reg_n_0_[1] ),
        .I3(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .O(\rxeq_txpreset[3]_i_1__6_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \rxeq_txpreset[3]_i_2__6 
       (.I0(\FSM_sequential_fsm_rx_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_rx_reg_n_0_[0] ),
        .I2(rxeq_txpreset_reg2[3]),
        .O(rxeq_txpreset[3]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[0]),
        .Q(rxeq_txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[1]),
        .Q(rxeq_txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[2]),
        .Q(rxeq_txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_txpreset_reg1[3]),
        .Q(rxeq_txpreset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txpreset[0]),
        .Q(rxeq_txpreset__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txpreset[1]),
        .Q(rxeq_txpreset__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txpreset[2]),
        .Q(rxeq_txpreset__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxeq_txpreset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\rxeq_txpreset[3]_i_1__6_n_0 ),
        .D(rxeq_txpreset[3]),
        .Q(rxeq_txpreset__0[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_en_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_en_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_en_reg1),
        .Q(rxeq_user_en_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_mode_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_user_mode_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_mode_reg1),
        .Q(rxeq_user_mode_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxeq_user_txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[0]),
        .Q(rxeq_user_txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[10]),
        .Q(rxeq_user_txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[11]),
        .Q(rxeq_user_txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[12]),
        .Q(rxeq_user_txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[13]),
        .Q(rxeq_user_txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[14]),
        .Q(rxeq_user_txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[15]),
        .Q(rxeq_user_txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[16]),
        .Q(rxeq_user_txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[17]),
        .Q(rxeq_user_txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[1]),
        .Q(rxeq_user_txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[2]),
        .Q(rxeq_user_txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[3]),
        .Q(rxeq_user_txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[4]),
        .Q(rxeq_user_txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[5]),
        .Q(rxeq_user_txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[6]),
        .Q(rxeq_user_txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[7]),
        .Q(rxeq_user_txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[8]),
        .Q(rxeq_user_txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxeq_user_txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_user_txcoeff_reg1[9]),
        .Q(rxeq_user_txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_control_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[0]),
        .Q(txeq_control_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_control_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_control_reg1[1]),
        .Q(txeq_control_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_deemph_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \txeq_deemph_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[0]),
        .Q(txeq_deemph_reg2[0]),
        .S(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[1]),
        .Q(txeq_deemph_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[2]),
        .Q(txeq_deemph_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[3]),
        .Q(txeq_deemph_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[4]),
        .Q(txeq_deemph_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_deemph_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_deemph_reg1[5]),
        .Q(txeq_deemph_reg2[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00001000)) 
    \txeq_preset[0]_i_1__6 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[0]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hAEABBABB)) 
    \txeq_preset[10]_i_1__6 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[10]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hAEAABABB)) 
    \txeq_preset[11]_i_1__6 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[11]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h00001574)) 
    \txeq_preset[12]_i_1__6 
       (.I0(txeq_preset_reg2[3]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[12]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[13]_i_1__6 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[13]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h00000410)) 
    \txeq_preset[14]_i_1__6 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[14]_i_1__6_n_0 ));
  LUT4 #(
    .INIT(16'hAAAB)) 
    \txeq_preset[15]_i_1__6 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[2]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .O(\txeq_preset[15]_i_1__6_n_0 ));
  LUT4 #(
    .INIT(16'h0014)) 
    \txeq_preset[16]_i_1__6 
       (.I0(txeq_preset_reg2[2]),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[16]_i_1__6_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \txeq_preset[17]_i_1 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(RST_CPLLRESET),
        .O(\txeq_preset[17]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAEABABB)) 
    \txeq_preset[17]_i_2__6 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[17]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h00001004)) 
    \txeq_preset[1]_i_1__6 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[1]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[1]_i_1__6_n_0 ));
  LUT4 #(
    .INIT(16'h00C8)) 
    \txeq_preset[2]_i_1__6 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(RST_CPLLRESET),
        .O(\txeq_preset[2]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h00003424)) 
    \txeq_preset[3]_i_1__6 
       (.I0(txeq_preset_reg2[1]),
        .I1(txeq_preset_reg2[3]),
        .I2(txeq_preset_reg2[2]),
        .I3(txeq_preset_reg2[0]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[3]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h00000408)) 
    \txeq_preset[7]_i_1__6 
       (.I0(txeq_preset_reg2[0]),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[2]),
        .I4(RST_CPLLRESET),
        .O(\txeq_preset[7]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hAAAEBBFB)) 
    \txeq_preset[8]_i_1__6 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[1]),
        .I2(txeq_preset_reg2[0]),
        .I3(txeq_preset_reg2[3]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[8]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hAEAEBABB)) 
    \txeq_preset[9]_i_1__6 
       (.I0(RST_CPLLRESET),
        .I1(txeq_preset_reg2[0]),
        .I2(txeq_preset_reg2[3]),
        .I3(txeq_preset_reg2[1]),
        .I4(txeq_preset_reg2[2]),
        .O(\txeq_preset[9]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    txeq_preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .Q(txeq_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txeq_preset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[0]),
        .Q(txeq_preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[1]),
        .Q(txeq_preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[2]),
        .Q(txeq_preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txeq_preset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_preset_reg1[3]),
        .Q(txeq_preset_reg2[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[0]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[10]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[11]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[12]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[13]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[14]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[15]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[16]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[17]_i_2__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[1]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[2]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[3]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(1'b0),
        .Q(\txeq_preset_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[7]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[8]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_preset_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_preset[17]_i_1_n_0 ),
        .D(\txeq_preset[9]_i_1__6_n_0 ),
        .Q(\txeq_preset_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[0]_i_1__6 
       (.I0(\txeq_txcoeff_reg_n_0_[6] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I3(\txeq_preset_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[0]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[0]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hAA208A00)) 
    \txeq_txcoeff[0]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .O(\txeq_txcoeff[0]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[10]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[10] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[9] ),
        .I4(\txeq_txcoeff[10]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[10]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[10]_i_2__6 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[16] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[10]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[11]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[11] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[10] ),
        .I4(\txeq_txcoeff[11]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[11]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[11]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[18] ),
        .I2(\txeq_txcoeff_reg_n_0_[17] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[11]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[12]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[12] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[11] ),
        .I4(\txeq_txcoeff[12]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[12]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[12]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[0]),
        .I2(\txeq_txcoeff_reg_n_0_[18] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[12]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[13]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[13] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[12] ),
        .I4(\txeq_txcoeff[13]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[13]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[13]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[1]),
        .I2(txeq_deemph_reg2[0]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[13]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[14]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[14] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[13] ),
        .I4(\txeq_txcoeff[14]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[14]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[14]_i_2__6 
       (.I0(txeq_deemph_reg2[2]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[1]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[14]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[15]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[15] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[14] ),
        .I4(\txeq_txcoeff[15]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[15]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[15]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[3]),
        .I2(txeq_deemph_reg2[2]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[15]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[16]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[16] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[15] ),
        .I4(\txeq_txcoeff[16]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[16]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[16]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(txeq_deemph_reg2[4]),
        .I2(txeq_deemph_reg2[3]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[16]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[17]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[17] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[16] ),
        .I4(\txeq_txcoeff[17]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[17]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[17]_i_2__6 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(txeq_deemph_reg2[4]),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[17]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h5557FF5755575557)) 
    \txeq_txcoeff[18]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx[1]_i_2__6_n_0 ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[5] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I4(txeq_control_reg2[0]),
        .I5(txeq_control_reg2[1]),
        .O(\txeq_txcoeff[18]_i_1__6_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \txeq_txcoeff[18]_i_2__6 
       (.I0(txeq_deemph_reg2[5]),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I2(\txeq_txcoeff[18]_i_3__6_n_0 ),
        .O(\txeq_txcoeff[18]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'hF888F8F888888888)) 
    \txeq_txcoeff[18]_i_3__6 
       (.I0(\txeq_txcoeff_reg_n_0_[17] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I2(txeq_deemph_reg2[5]),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[18]_i_3__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[1]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[0] ),
        .I4(\txeq_txcoeff[1]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[1]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[1]_i_2__6 
       (.I0(\txeq_txcoeff_reg_n_0_[8] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[7] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[1]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[2]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[1] ),
        .I4(\txeq_txcoeff[2]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[2]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[2]_i_2__6 
       (.I0(\txeq_txcoeff_reg_n_0_[9] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[8] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[2]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[3]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[2] ),
        .I4(\txeq_txcoeff[3]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[3]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[3]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[10] ),
        .I2(\txeq_txcoeff_reg_n_0_[9] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[3]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[4]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[3] ),
        .I4(\txeq_txcoeff[4]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[4]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[4]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[11] ),
        .I2(\txeq_txcoeff_reg_n_0_[10] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[4]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[5]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[5] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[4] ),
        .I4(\txeq_txcoeff[5]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[5]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[5]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[12] ),
        .I2(\txeq_txcoeff_reg_n_0_[11] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[5]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[6]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[5] ),
        .I4(\txeq_txcoeff[6]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[6]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[6]_i_2__6 
       (.I0(\txeq_txcoeff_reg_n_0_[13] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[12] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[6]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[7]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[7] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[6] ),
        .I4(\txeq_txcoeff[7]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[7]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[7]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[14] ),
        .I2(\txeq_txcoeff_reg_n_0_[13] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[7]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[8]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[8] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[7] ),
        .I4(\txeq_txcoeff[8]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[8]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0ECF0A0A0A0A0)) 
    \txeq_txcoeff[8]_i_2__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I1(\txeq_txcoeff_reg_n_0_[15] ),
        .I2(\txeq_txcoeff_reg_n_0_[14] ),
        .I3(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I4(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .O(\txeq_txcoeff[8]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \txeq_txcoeff[9]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[2] ),
        .I1(\txeq_preset_reg_n_0_[9] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[4] ),
        .I3(\txeq_txcoeff_reg_n_0_[8] ),
        .I4(\txeq_txcoeff[9]_i_2__6_n_0 ),
        .O(\txeq_txcoeff[9]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0800FB000800)) 
    \txeq_txcoeff[9]_i_2__6 
       (.I0(\txeq_txcoeff_reg_n_0_[16] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I4(\txeq_txcoeff_reg_n_0_[15] ),
        .I5(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .O(\txeq_txcoeff[9]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h4444F444)) 
    \txeq_txcoeff_cnt[0]_i_1__6 
       (.I0(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I2(\FSM_onehot_fsm_tx_reg_n_0_[1] ),
        .I3(txeq_control_reg2[1]),
        .I4(txeq_control_reg2[0]),
        .O(txeq_txcoeff_cnt[0]));
  LUT3 #(
    .INIT(8'h28)) 
    \txeq_txcoeff_cnt[1]_i_1__6 
       (.I0(\FSM_onehot_fsm_tx_reg_n_0_[3] ),
        .I1(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .I2(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .O(txeq_txcoeff_cnt[1]));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[0]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txeq_txcoeff_cnt[1]),
        .Q(\txeq_txcoeff_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[0] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[0]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[10] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[10]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[11] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[11]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[12] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[12]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[13] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[13]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[14] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[14]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[15] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[15]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[16] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[16]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[17] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[17]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[18] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[18]_i_2__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[1] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[1]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[2] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[2]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[3] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[3]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[4] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[4]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[5] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[5]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[6] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[6]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[7] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[7]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[8] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[8]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txeq_txcoeff_reg[9] 
       (.C(pclk_sel_reg),
        .CE(\txeq_txcoeff[18]_i_1__6_n_0 ),
        .D(\txeq_txcoeff[9]_i_1__6_n_0 ),
        .Q(\txeq_txcoeff_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_rate" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate
   (Q,
    USER_RESETOVRD_START,
    RXSYSCLKSEL,
    SYNC_TXSYNC_START,
    DRP_X16X20_MODE0,
    DRP_X160,
    DRP_START0,
    \cplllock_reg1_reg[0] ,
    rate_gen3,
    \cplllock_reg1_reg[0]_0 ,
    RXRATE,
    USER_RATE_DONE,
    USER_RATE_RXSYNC,
    SYNC_RXSYNC_START,
    RST_RATE_IDLE,
    GT_TXPMARESET0,
    USER_PCLK_SEL,
    QRST_QPLLRESET_IN,
    p_0_in2_in,
    QRST_QPLLPD_IN,
    p_0_in3_in,
    out1,
    RST_DRP_X16X20_MODE,
    RST_DRP_X16,
    RST_DRP_START,
    RST_CPLLRESET,
    CLK,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    RATE_CPLLLOCK,
    RATE_QPLLLOCK,
    RATE_DRP_DONE,
    RATE_MMCM_LOCK,
    RATE_PHYSTATUS,
    USER_TXRESETDONE,
    USER_RXRESETDONE,
    RATE_TXRATEDONE,
    RATE_RXRATEDONE,
    RATE_RESETOVRD_DONE,
    RATE_TXSYNC_DONE,
    SYNC_RXSYNC_DONE,
    p_1_in8_in,
    p_0_in7_in);
  output [4:0]Q;
  output USER_RESETOVRD_START;
  output [1:0]RXSYSCLKSEL;
  output SYNC_TXSYNC_START;
  output DRP_X16X20_MODE0;
  output DRP_X160;
  output DRP_START0;
  output \cplllock_reg1_reg[0] ;
  output [0:0]rate_gen3;
  output \cplllock_reg1_reg[0]_0 ;
  output [2:0]RXRATE;
  output USER_RATE_DONE;
  output USER_RATE_RXSYNC;
  output SYNC_RXSYNC_START;
  output [0:0]RST_RATE_IDLE;
  output GT_TXPMARESET0;
  output USER_PCLK_SEL;
  output [0:0]QRST_QPLLRESET_IN;
  output p_0_in2_in;
  output [0:0]QRST_QPLLPD_IN;
  output p_0_in3_in;
  input [1:0]out1;
  input RST_DRP_X16X20_MODE;
  input RST_DRP_X16;
  input RST_DRP_START;
  input RST_CPLLRESET;
  input CLK;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input RATE_CPLLLOCK;
  input RATE_QPLLLOCK;
  input RATE_DRP_DONE;
  input RATE_MMCM_LOCK;
  input RATE_PHYSTATUS;
  input USER_TXRESETDONE;
  input USER_RXRESETDONE;
  input RATE_TXRATEDONE;
  input RATE_RXRATEDONE;
  input RATE_RESETOVRD_DONE;
  input RATE_TXSYNC_DONE;
  input SYNC_RXSYNC_DONE;
  input p_1_in8_in;
  input p_0_in7_in;

  wire CLK;
  wire DRP_START0;
  wire DRP_X160;
  wire DRP_X16X20_MODE0;
  wire GT_TXPMARESET0;
  wire [4:0]Q;
  wire [0:0]QRST_QPLLPD_IN;
  wire [0:0]QRST_QPLLRESET_IN;
  wire RATE_CPLLLOCK;
  wire RATE_DRP_DONE;
  wire RATE_MMCM_LOCK;
  wire RATE_PHYSTATUS;
  wire RATE_QPLLLOCK;
  wire RATE_RESETOVRD_DONE;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RATE_TXSYNC_DONE;
  wire RST_CPLLRESET;
  wire RST_DRP_START;
  wire RST_DRP_X16;
  wire RST_DRP_X16X20_MODE;
  wire [0:0]RST_RATE_IDLE;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXSYNC_START;
  wire USER_PCLK_SEL;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire cplllock_reg1;
  wire \cplllock_reg1_reg[0] ;
  wire \cplllock_reg1_reg[0]_0 ;
  wire cplllock_reg2;
  wire cpllpd_i_1_n_0;
  wire cpllreset_i_1__0_n_0;
  wire drp_done_reg1;
  wire drp_done_reg2;
  wire drp_start_i_1_n_0;
  wire drp_x16_i_1_n_0;
  wire drp_x16x20_mode_i_1_n_0;
  wire [4:0]fsm;
  wire fsm1;
  wire \fsm[0]_i_10_n_0 ;
  wire \fsm[0]_i_11_n_0 ;
  wire \fsm[0]_i_12_n_0 ;
  wire \fsm[0]_i_3_n_0 ;
  wire \fsm[0]_i_4_n_0 ;
  wire \fsm[0]_i_5_n_0 ;
  wire \fsm[0]_i_6_n_0 ;
  wire \fsm[0]_i_7_n_0 ;
  wire \fsm[0]_i_8_n_0 ;
  wire \fsm[0]_i_9_n_0 ;
  wire \fsm[1]_i_4_n_0 ;
  wire \fsm[1]_i_5_n_0 ;
  wire \fsm[1]_i_6_n_0 ;
  wire \fsm[1]_i_7_n_0 ;
  wire \fsm[1]_i_8_n_0 ;
  wire \fsm[1]_i_9_n_0 ;
  wire \fsm[2]_i_2_n_0 ;
  wire \fsm[2]_i_3_n_0 ;
  wire \fsm[2]_i_4_n_0 ;
  wire \fsm[2]_i_5_n_0 ;
  wire \fsm[3]_i_2_n_0 ;
  wire \fsm[3]_i_3_n_0 ;
  wire \fsm[3]_i_4_n_0 ;
  wire \fsm[3]_i_5_n_0 ;
  wire \fsm[3]_i_8_n_0 ;
  wire \fsm[3]_i_9_n_0 ;
  wire \fsm[4]_i_2_n_0 ;
  wire \fsm[4]_i_3_n_0 ;
  wire \fsm_reg[0]_i_2_n_0 ;
  wire \fsm_reg[1]_i_2_n_0 ;
  wire \fsm_reg[1]_i_3_n_0 ;
  wire gen3_exit;
  wire gen3_exit_i_1_n_0;
  wire gen3_exit_i_2_n_0;
  wire gen3_i_1_n_0;
  wire gen3_i_2_n_0;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire [1:0]out1;
  wire p_0_in2_in;
  wire p_0_in3_in;
  wire p_0_in4_in;
  wire p_0_in5_in;
  wire p_0_in6_in;
  wire p_0_in7_in;
  wire [3:0]p_0_in__0;
  wire p_1_in8_in;
  wire pclk_sel_i_1__0_n_0;
  wire pclk_sel_i_2_n_0;
  wire phystatus_i_1_n_0;
  wire phystatus_reg1;
  wire phystatus_reg2;
  wire phystatus_reg_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire pll_lock;
  wire qplllock_reg1;
  wire qplllock_reg2;
  wire qpllpd;
  wire qpllpd_i_1__0_n_0;
  wire qpllreset;
  wire qpllreset_i_1__0_n_0;
  wire [0:0]rate_gen3;
  wire [1:0]rate_in_reg1;
  wire [1:0]rate_in_reg2;
  wire \rate_out[0]_i_1_n_0 ;
  wire \rate_out[1]_i_1_n_0 ;
  wire \rate_out[2]_i_1_n_0 ;
  wire \rate_out[2]_i_2_n_0 ;
  wire \rate_out[2]_i_3_n_0 ;
  wire ratedone_i_1_n_0;
  wire ratedone_reg_n_0;
  wire resetovrd_done_reg1;
  wire resetovrd_done_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire rxpmaresetdone_reg1;
  wire rxpmaresetdone_reg2;
  wire rxratedone_i_1_n_0;
  wire rxratedone_reg1;
  wire rxratedone_reg2;
  wire rxratedone_reg_n_0;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxsync_done_reg1;
  wire rxsync_done_reg2;
  wire \sysclksel[0]_i_1_n_0 ;
  wire \sysclksel[0]_i_2_n_0 ;
  wire \sysclksel[0]_i_3_n_0 ;
  wire \sysclksel[1]_i_1_n_0 ;
  wire \txdata_wait_cnt[3]_i_2_n_0 ;
  wire [3:0]txdata_wait_cnt_reg__0;
  wire txpmareset_i_1_n_0;
  wire txpmareset_i_2_n_0;
  wire txratedone_i_1_n_0;
  wire txratedone_i_2_n_0;
  wire txratedone_reg1;
  wire txratedone_reg2;
  wire txratedone_reg_n_0;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire txsync_done_reg1;
  wire txsync_done_reg2;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(RATE_CPLLLOCK),
        .Q(cplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cplllock_reg1),
        .Q(cplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllpd_i_1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(p_0_in3_in),
        .O(cpllpd_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT5 #(
    .INIT(32'h80000084)) 
    cpllpd_i_2
       (.I0(Q[4]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(qpllpd));
  FDRE #(
    .INIT(1'b0)) 
    cpllpd_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cpllpd_i_1_n_0),
        .Q(p_0_in3_in),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllreset_i_1__0
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(p_0_in2_in),
        .O(cpllreset_i_1__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT5 #(
    .INIT(32'h81000002)) 
    cpllreset_i_2
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(qpllreset));
  FDRE #(
    .INIT(1'b0)) 
    cpllreset_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cpllreset_i_1__0_n_0),
        .Q(p_0_in2_in),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(RATE_DRP_DONE),
        .Q(drp_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'h08200108)) 
    drp_start_i_1
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(Q[1]),
        .O(drp_start_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(drp_start_i_1_n_0),
        .Q(p_0_in4_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT5 #(
    .INIT(32'h20020006)) 
    drp_x16_i_1
       (.I0(Q[2]),
        .I1(Q[4]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[0]),
        .O(drp_x16_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16_reg
       (.C(CLK),
        .CE(1'b1),
        .D(drp_x16_i_1_n_0),
        .Q(p_0_in5_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT5 #(
    .INIT(32'h20001584)) 
    drp_x16x20_mode_i_1
       (.I0(Q[1]),
        .I1(Q[4]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(drp_x16x20_mode_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16x20_mode_reg
       (.C(CLK),
        .CE(1'b1),
        .D(drp_x16x20_mode_i_1_n_0),
        .Q(p_0_in6_in),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hBBB88888BBB8BBB8)) 
    \fsm[0]_i_1 
       (.I0(\fsm_reg[0]_i_2_n_0 ),
        .I1(Q[4]),
        .I2(\fsm[0]_i_3_n_0 ),
        .I3(Q[3]),
        .I4(\fsm[0]_i_4_n_0 ),
        .I5(\fsm[0]_i_5_n_0 ),
        .O(fsm[0]));
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[0]_i_10 
       (.I0(txdata_wait_cnt_reg__0[3]),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[0]),
        .I3(txdata_wait_cnt_reg__0[1]),
        .O(\fsm[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000F404)) 
    \fsm[0]_i_11 
       (.I0(rxpmaresetdone_reg2),
        .I1(mmcm_lock_reg2),
        .I2(Q[0]),
        .I3(drp_done_reg2),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\fsm[0]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h4F4F737F4343404C)) 
    \fsm[0]_i_12 
       (.I0(resetovrd_done_reg2),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(rxpmaresetdone_reg2),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0344FF440344FF77)) 
    \fsm[0]_i_3 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(pll_lock),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\fsm[3]_i_9_n_0 ),
        .O(\fsm[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hF0000000F800F000)) 
    \fsm[0]_i_4 
       (.I0(pll_lock),
        .I1(rst_idle_reg2),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(drp_done_reg2),
        .I5(Q[0]),
        .O(\fsm[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000CCC8C0C8)) 
    \fsm[0]_i_5 
       (.I0(\fsm[0]_i_8_n_0 ),
        .I1(Q[3]),
        .I2(\fsm[0]_i_9_n_0 ),
        .I3(Q[0]),
        .I4(\fsm[0]_i_10_n_0 ),
        .I5(\fsm[0]_i_11_n_0 ),
        .O(\fsm[0]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0040)) 
    \fsm[0]_i_6 
       (.I0(fsm1),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(\fsm[0]_i_12_n_0 ),
        .O(\fsm[0]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h03880333)) 
    \fsm[0]_i_7 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[0]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h77770777)) 
    \fsm[0]_i_8 
       (.I0(p_0_in7_in),
        .I1(p_1_in8_in),
        .I2(rxresetdone_reg2),
        .I3(txresetdone_reg2),
        .I4(phystatus_reg2),
        .O(\fsm[0]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \fsm[0]_i_9 
       (.I0(Q[1]),
        .I1(Q[2]),
        .O(\fsm[0]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h30BBFC00)) 
    \fsm[1]_i_4 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(\fsm[1]_i_8_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hCC88300000BB3000)) 
    \fsm[1]_i_5 
       (.I0(\fsm[0]_i_10_n_0 ),
        .I1(Q[2]),
        .I2(\fsm[1]_i_9_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h70F040F0)) 
    \fsm[1]_i_6 
       (.I0(resetovrd_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(drp_done_reg2),
        .O(\fsm[1]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h03777700)) 
    \fsm[1]_i_7 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h53F5FFFFFFFFFFFF)) 
    \fsm[1]_i_8 
       (.I0(cplllock_reg2),
        .I1(qplllock_reg2),
        .I2(rate_in_reg2[0]),
        .I3(rate_in_reg2[1]),
        .I4(rst_idle_reg2),
        .I5(Q[0]),
        .O(\fsm[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF4575FFFFFFFF)) 
    \fsm[1]_i_9 
       (.I0(cplllock_reg2),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .I3(qplllock_reg2),
        .I4(rst_idle_reg2),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fsm[2]_i_1 
       (.I0(\fsm[2]_i_2_n_0 ),
        .I1(\fsm[2]_i_3_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[2]_i_4_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[2]_i_5_n_0 ),
        .O(fsm[2]));
  LUT5 #(
    .INIT(32'h3C0C4040)) 
    \fsm[2]_i_2 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_done_reg2),
        .I4(Q[0]),
        .O(\fsm[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h13CCD3CC1FCCDFCC)) 
    \fsm[2]_i_3 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(resetovrd_done_reg2),
        .I5(fsm1),
        .O(\fsm[2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hBC0C)) 
    \fsm[2]_i_4 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\fsm[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4A4A4A4AAAAFAAAA)) 
    \fsm[2]_i_5 
       (.I0(Q[2]),
        .I1(pll_lock),
        .I2(Q[1]),
        .I3(\fsm[3]_i_9_n_0 ),
        .I4(\fsm[3]_i_8_n_0 ),
        .I5(Q[0]),
        .O(\fsm[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hEFE0EFEFEFE0E0E0)) 
    \fsm[3]_i_1 
       (.I0(\fsm[3]_i_2_n_0 ),
        .I1(\fsm[3]_i_3_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[3]_i_4_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[3]_i_5_n_0 ),
        .O(fsm[3]));
  LUT5 #(
    .INIT(32'h22AA2A22)) 
    \fsm[3]_i_2 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(rxsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h3020002000000000)) 
    \fsm[3]_i_3 
       (.I0(fsm1),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(resetovrd_done_reg2),
        .I5(Q[0]),
        .O(\fsm[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hF545F555FFFFFFFF)) 
    \fsm[3]_i_4 
       (.I0(Q[2]),
        .I1(rst_idle_reg2),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(pll_lock),
        .I5(Q[1]),
        .O(\fsm[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT5 #(
    .INIT(32'h80808180)) 
    \fsm[3]_i_5 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\fsm[3]_i_8_n_0 ),
        .I4(\fsm[3]_i_9_n_0 ),
        .O(\fsm[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8F8FFF8)) 
    \fsm[3]_i_6 
       (.I0(p_1_in8_in),
        .I1(p_0_in7_in),
        .I2(ratedone_reg_n_0),
        .I3(rate_in_reg2[1]),
        .I4(rate_in_reg2[0]),
        .I5(gen3_exit),
        .O(fsm1));
  LUT4 #(
    .INIT(16'hFB08)) 
    \fsm[3]_i_7 
       (.I0(qplllock_reg2),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(cplllock_reg2),
        .O(pll_lock));
  LUT4 #(
    .INIT(16'hB0BB)) 
    \fsm[3]_i_8 
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg1[0]),
        .I3(rate_in_reg1[1]),
        .O(\fsm[3]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \fsm[3]_i_9 
       (.I0(rate_in_reg1[0]),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg1[1]),
        .I3(rate_in_reg2[1]),
        .O(\fsm[3]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h08880000)) 
    \fsm[4]_i_2 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\fsm[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h5F75FFFF)) 
    \fsm[4]_i_3 
       (.I0(Q[2]),
        .I1(rxsync_done_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\fsm[4]_i_3_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  MUXF7 \fsm_reg[0]_i_2 
       (.I0(\fsm[0]_i_6_n_0 ),
        .I1(\fsm[0]_i_7_n_0 ),
        .O(\fsm_reg[0]_i_2_n_0 ),
        .S(Q[3]));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .S(RST_CPLLRESET));
  MUXF8 \fsm_reg[1]_i_1 
       (.I0(\fsm_reg[1]_i_2_n_0 ),
        .I1(\fsm_reg[1]_i_3_n_0 ),
        .O(fsm[1]),
        .S(Q[4]));
  MUXF7 \fsm_reg[1]_i_2 
       (.I0(\fsm[1]_i_4_n_0 ),
        .I1(\fsm[1]_i_5_n_0 ),
        .O(\fsm_reg[1]_i_2_n_0 ),
        .S(Q[3]));
  MUXF7 \fsm_reg[1]_i_3 
       (.I0(\fsm[1]_i_6_n_0 ),
        .I1(\fsm[1]_i_7_n_0 ),
        .O(\fsm_reg[1]_i_3_n_0 ),
        .S(Q[3]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(fsm[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  MUXF7 \fsm_reg[4]_i_1 
       (.I0(\fsm[4]_i_2_n_0 ),
        .I1(\fsm[4]_i_3_n_0 ),
        .O(fsm[4]),
        .S(Q[4]));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_exit_i_1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_exit_i_2_n_0),
        .I4(gen3_exit),
        .O(gen3_exit_i_1_n_0));
  LUT6 #(
    .INIT(64'hC000000000000001)) 
    gen3_exit_i_2
       (.I0(\fsm[3]_i_9_n_0 ),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(gen3_exit_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_exit_reg
       (.C(CLK),
        .CE(1'b1),
        .D(gen3_exit_i_1_n_0),
        .Q(gen3_exit),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_i_1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_i_2_n_0),
        .I4(rate_gen3),
        .O(gen3_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT5 #(
    .INIT(32'h80000008)) 
    gen3_i_2
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[1]),
        .O(gen3_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg
       (.C(CLK),
        .CE(1'b1),
        .D(gen3_i_1_n_0),
        .Q(rate_gen3),
        .R(RST_CPLLRESET));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_6__6 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_7 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[0] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(RATE_MMCM_LOCK),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h06FF0600)) 
    pclk_sel_i_1__0
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(pclk_sel_i_2_n_0),
        .I4(USER_PCLK_SEL),
        .O(pclk_sel_i_1__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT5 #(
    .INIT(32'h80040800)) 
    pclk_sel_i_2
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(pclk_sel_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pclk_sel_i_1__0_n_0),
        .Q(USER_PCLK_SEL),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    phystatus_i_1
       (.I0(phystatus_reg2),
        .I1(txratedone_i_2_n_0),
        .I2(phystatus_reg_n_0),
        .O(phystatus_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    phystatus_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phystatus_i_1_n_0),
        .Q(phystatus_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(RATE_PHYSTATUS),
        .Q(phystatus_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phystatus_reg1),
        .Q(phystatus_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(RATE_QPLLLOCK),
        .Q(qplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllpd_i_1__0
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(QRST_QPLLPD_IN),
        .O(qpllpd_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllpd_reg
       (.C(CLK),
        .CE(1'b1),
        .D(qpllpd_i_1__0_n_0),
        .Q(QRST_QPLLPD_IN),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllreset_i_1__0
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(QRST_QPLLRESET_IN),
        .O(qpllreset_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllreset_reg
       (.C(CLK),
        .CE(1'b1),
        .D(qpllreset_i_1__0_n_0),
        .Q(QRST_QPLLRESET_IN),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    rate_done_reg1_i_1
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(USER_RATE_DONE));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \rate_idle_reg1[0]_i_1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(RST_RATE_IDLE));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_in_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_in_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rate_in_reg1[0]),
        .Q(rate_in_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rate_in_reg1[1]),
        .Q(rate_in_reg2[1]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    \rate_out[0]_i_1 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .I2(Q[1]),
        .I3(\rate_out[2]_i_2_n_0 ),
        .I4(RXRATE[0]),
        .O(\rate_out[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[1]_i_1 
       (.I0(\rate_out[2]_i_2_n_0 ),
        .I1(RXRATE[1]),
        .O(\rate_out[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[2]_i_1 
       (.I0(\rate_out[2]_i_2_n_0 ),
        .I1(RXRATE[2]),
        .O(\rate_out[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000002080000220)) 
    \rate_out[2]_i_2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\rate_out[2]_i_3_n_0 ),
        .O(\rate_out[2]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h45)) 
    \rate_out[2]_i_3 
       (.I0(gen3_exit),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .O(\rate_out[2]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rate_out[0]_i_1_n_0 ),
        .Q(RXRATE[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rate_out[1]_i_1_n_0 ),
        .Q(RXRATE[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rate_out[2]_i_1_n_0 ),
        .Q(RXRATE[2]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'h00808000)) 
    rate_rxsync_reg1_i_1
       (.I0(Q[3]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(USER_RATE_RXSYNC));
  LUT5 #(
    .INIT(32'hFF008000)) 
    ratedone_i_1
       (.I0(rxratedone_reg_n_0),
        .I1(txratedone_reg_n_0),
        .I2(phystatus_reg_n_0),
        .I3(txratedone_i_2_n_0),
        .I4(ratedone_reg_n_0),
        .O(ratedone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ratedone_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ratedone_i_1_n_0),
        .Q(ratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(RATE_RESETOVRD_DONE),
        .Q(resetovrd_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(resetovrd_done_reg1),
        .Q(resetovrd_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    resetovrd_start_reg1_i_1
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[4]),
        .I4(Q[2]),
        .O(USER_RESETOVRD_START));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(out1[1]),
        .Q(rst_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1),
        .Q(rxpmaresetdone_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    rxratedone_i_1
       (.I0(rxratedone_reg2),
        .I1(txratedone_i_2_n_0),
        .I2(rxratedone_reg_n_0),
        .O(rxratedone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxratedone_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxratedone_i_1_n_0),
        .Q(rxratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(RATE_RXRATEDONE),
        .Q(rxratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxratedone_reg1),
        .Q(rxratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONE),
        .Q(rxsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxsync_done_reg1),
        .Q(rxsync_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    rxsync_start_reg1_i_1
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(SYNC_RXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    start_reg1_i_1
       (.I0(p_0_in4_in),
        .I1(RST_DRP_START),
        .O(DRP_START0));
  LUT6 #(
    .INIT(64'hFFFF3EFF00000200)) 
    \sysclksel[0]_i_1 
       (.I0(\sysclksel[0]_i_2_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(\sysclksel[0]_i_3_n_0 ),
        .I5(RXSYSCLKSEL[0]),
        .O(\sysclksel[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \sysclksel[0]_i_2 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .O(\sysclksel[0]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \sysclksel[0]_i_3 
       (.I0(Q[2]),
        .I1(Q[1]),
        .O(\sysclksel[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6FFFFFFF00000000)) 
    \sysclksel[1]_i_1 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(RXSYSCLKSEL[1]),
        .O(\sysclksel[1]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\sysclksel[0]_i_1_n_0 ),
        .Q(RXSYSCLKSEL[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\sysclksel[1]_i_1_n_0 ),
        .Q(RXSYSCLKSEL[1]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT5 #(
    .INIT(32'h80AA00AA)) 
    \txdata_wait_cnt[0]_i_1 
       (.I0(\txdata_wait_cnt[3]_i_2_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT5 #(
    .INIT(32'hA8282828)) 
    \txdata_wait_cnt[1]_i_1 
       (.I0(\txdata_wait_cnt[3]_i_2_n_0 ),
        .I1(txdata_wait_cnt_reg__0[0]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[3]),
        .I4(txdata_wait_cnt_reg__0[2]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT5 #(
    .INIT(32'h8AA0A0A0)) 
    \txdata_wait_cnt[2]_i_1 
       (.I0(\txdata_wait_cnt[3]_i_2_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \txdata_wait_cnt[3]_i_1 
       (.I0(\txdata_wait_cnt[3]_i_2_n_0 ),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \txdata_wait_cnt[3]_i_2 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\txdata_wait_cnt[3]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(txdata_wait_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(txdata_wait_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(txdata_wait_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(txdata_wait_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h5504FFFF55040000)) 
    txpmareset_i_1
       (.I0(Q[3]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(gen3_exit),
        .I4(txpmareset_i_2_n_0),
        .I5(GT_TXPMARESET0),
        .O(txpmareset_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT5 #(
    .INIT(32'h82000400)) 
    txpmareset_i_2
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(txpmareset_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txpmareset_reg
       (.C(CLK),
        .CE(1'b1),
        .D(txpmareset_i_1_n_0),
        .Q(GT_TXPMARESET0),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    txratedone_i_1
       (.I0(txratedone_reg2),
        .I1(txratedone_i_2_n_0),
        .I2(txratedone_reg_n_0),
        .O(txratedone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    txratedone_i_2
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(RST_CPLLRESET),
        .O(txratedone_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txratedone_reg
       (.C(CLK),
        .CE(1'b1),
        .D(txratedone_i_1_n_0),
        .Q(txratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(RATE_TXRATEDONE),
        .Q(txratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(txratedone_reg1),
        .Q(txratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(RATE_TXSYNC_DONE),
        .Q(txsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(txsync_done_reg1),
        .Q(txsync_done_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAA)) 
    txsync_start_reg1_i_1
       (.I0(out1[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(SYNC_TXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    x16_reg1_i_1
       (.I0(p_0_in5_in),
        .I1(RST_DRP_X16),
        .O(DRP_X160));
  LUT2 #(
    .INIT(4'hE)) 
    x16x20_mode_reg1_i_1
       (.I0(p_0_in6_in),
        .I1(RST_DRP_X16X20_MODE),
        .O(DRP_X16X20_MODE0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_rate" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_32
   (Q,
    USER_RESETOVRD_START,
    RXSYSCLKSEL,
    SYNC_TXSYNC_START,
    DRP_X16X20_MODE0106_out,
    DRP_X160104_out,
    DRP_START0102_out,
    \cplllock_reg1_reg[1] ,
    rate_gen3,
    \cplllock_reg1_reg[1]_0 ,
    RXRATE,
    USER_RATE_DONE,
    USER_RATE_RXSYNC,
    SYNC_RXSYNC_START,
    RST_RATE_IDLE,
    GT_TXPMARESET092_out,
    USER_PCLK_SEL,
    QRST_QPLLRESET_IN,
    p_0_in93_in,
    QRST_QPLLPD_IN,
    p_0_in95_in,
    out1,
    RST_DRP_X16X20_MODE,
    RST_DRP_X16,
    RST_DRP_START,
    RST_CPLLRESET,
    pclk_sel_reg_0,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    RATE_CPLLLOCK,
    RATE_QPLLLOCK,
    RATE_DRP_DONE,
    RATE_MMCM_LOCK,
    RATE_PHYSTATUS,
    USER_TXRESETDONE,
    USER_RXRESETDONE,
    RATE_TXRATEDONE,
    RATE_RXRATEDONE,
    RATE_RESETOVRD_DONE,
    RATE_TXSYNC_DONE,
    SYNC_RXSYNC_DONE,
    p_1_in8_in,
    p_0_in7_in);
  output [4:0]Q;
  output USER_RESETOVRD_START;
  output [1:0]RXSYSCLKSEL;
  output SYNC_TXSYNC_START;
  output DRP_X16X20_MODE0106_out;
  output DRP_X160104_out;
  output DRP_START0102_out;
  output \cplllock_reg1_reg[1] ;
  output [0:0]rate_gen3;
  output \cplllock_reg1_reg[1]_0 ;
  output [2:0]RXRATE;
  output USER_RATE_DONE;
  output USER_RATE_RXSYNC;
  output SYNC_RXSYNC_START;
  output [0:0]RST_RATE_IDLE;
  output GT_TXPMARESET092_out;
  output USER_PCLK_SEL;
  output [0:0]QRST_QPLLRESET_IN;
  output p_0_in93_in;
  output [0:0]QRST_QPLLPD_IN;
  output p_0_in95_in;
  input [1:0]out1;
  input RST_DRP_X16X20_MODE;
  input RST_DRP_X16;
  input RST_DRP_START;
  input RST_CPLLRESET;
  input pclk_sel_reg_0;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input RATE_CPLLLOCK;
  input RATE_QPLLLOCK;
  input RATE_DRP_DONE;
  input RATE_MMCM_LOCK;
  input RATE_PHYSTATUS;
  input USER_TXRESETDONE;
  input USER_RXRESETDONE;
  input RATE_TXRATEDONE;
  input RATE_RXRATEDONE;
  input RATE_RESETOVRD_DONE;
  input RATE_TXSYNC_DONE;
  input SYNC_RXSYNC_DONE;
  input p_1_in8_in;
  input p_0_in7_in;

  wire DRP_START0102_out;
  wire DRP_X160104_out;
  wire DRP_X16X20_MODE0106_out;
  wire GT_TXPMARESET092_out;
  wire [4:0]Q;
  wire [0:0]QRST_QPLLPD_IN;
  wire [0:0]QRST_QPLLRESET_IN;
  wire RATE_CPLLLOCK;
  wire RATE_DRP_DONE;
  wire RATE_MMCM_LOCK;
  wire RATE_PHYSTATUS;
  wire RATE_QPLLLOCK;
  wire RATE_RESETOVRD_DONE;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RATE_TXSYNC_DONE;
  wire RST_CPLLRESET;
  wire RST_DRP_START;
  wire RST_DRP_X16;
  wire RST_DRP_X16X20_MODE;
  wire [0:0]RST_RATE_IDLE;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXSYNC_START;
  wire USER_PCLK_SEL;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire cplllock_reg1;
  wire \cplllock_reg1_reg[1] ;
  wire \cplllock_reg1_reg[1]_0 ;
  wire cplllock_reg2;
  wire cpllpd_i_1__0_n_0;
  wire cpllreset_i_1__1_n_0;
  wire drp_done_reg1;
  wire drp_done_reg2;
  wire drp_start_i_1__0_n_0;
  wire drp_x16_i_1__0_n_0;
  wire drp_x16x20_mode_i_1__0_n_0;
  wire [4:0]fsm;
  wire fsm1;
  wire \fsm[0]_i_10__0_n_0 ;
  wire \fsm[0]_i_11__0_n_0 ;
  wire \fsm[0]_i_12__0_n_0 ;
  wire \fsm[0]_i_3__1_n_0 ;
  wire \fsm[0]_i_4__0_n_0 ;
  wire \fsm[0]_i_5__0_n_0 ;
  wire \fsm[0]_i_6__0_n_0 ;
  wire \fsm[0]_i_7__0_n_0 ;
  wire \fsm[0]_i_8__0_n_0 ;
  wire \fsm[0]_i_9__0_n_0 ;
  wire \fsm[1]_i_4__0_n_0 ;
  wire \fsm[1]_i_5__0_n_0 ;
  wire \fsm[1]_i_6__0_n_0 ;
  wire \fsm[1]_i_7__0_n_0 ;
  wire \fsm[1]_i_8__0_n_0 ;
  wire \fsm[1]_i_9__0_n_0 ;
  wire \fsm[2]_i_2__0_n_0 ;
  wire \fsm[2]_i_3__0_n_0 ;
  wire \fsm[2]_i_4__0_n_0 ;
  wire \fsm[2]_i_5__0_n_0 ;
  wire \fsm[3]_i_2__0_n_0 ;
  wire \fsm[3]_i_3__0_n_0 ;
  wire \fsm[3]_i_4__0_n_0 ;
  wire \fsm[3]_i_5__0_n_0 ;
  wire \fsm[3]_i_8__0_n_0 ;
  wire \fsm[3]_i_9__0_n_0 ;
  wire \fsm[4]_i_2__0_n_0 ;
  wire \fsm[4]_i_3__0_n_0 ;
  wire \fsm_reg[0]_i_2__0_n_0 ;
  wire \fsm_reg[1]_i_2__0_n_0 ;
  wire \fsm_reg[1]_i_3__0_n_0 ;
  wire gen3_exit;
  wire gen3_exit_i_1__0_n_0;
  wire gen3_exit_i_2__0_n_0;
  wire gen3_i_1__0_n_0;
  wire gen3_i_2__0_n_0;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire [1:0]out1;
  wire p_0_in101_in;
  wire p_0_in103_in;
  wire p_0_in105_in;
  wire p_0_in7_in;
  wire p_0_in93_in;
  wire p_0_in95_in;
  wire [3:0]p_0_in__0;
  wire p_1_in8_in;
  wire pclk_sel_i_1__1_n_0;
  wire pclk_sel_i_2__0_n_0;
  wire pclk_sel_reg_0;
  wire phystatus_i_1__0_n_0;
  wire phystatus_reg1;
  wire phystatus_reg2;
  wire phystatus_reg_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire pll_lock;
  wire qplllock_reg1;
  wire qplllock_reg2;
  wire qpllpd;
  wire qpllpd_i_1__1_n_0;
  wire qpllreset;
  wire qpllreset_i_1__1_n_0;
  wire [0:0]rate_gen3;
  wire [1:0]rate_in_reg1;
  wire [1:0]rate_in_reg2;
  wire \rate_out[0]_i_1__0_n_0 ;
  wire \rate_out[1]_i_1__0_n_0 ;
  wire \rate_out[2]_i_1__0_n_0 ;
  wire \rate_out[2]_i_2__0_n_0 ;
  wire \rate_out[2]_i_3__0_n_0 ;
  wire ratedone_i_1__0_n_0;
  wire ratedone_reg_n_0;
  wire resetovrd_done_reg1;
  wire resetovrd_done_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire rxpmaresetdone_reg1;
  wire rxpmaresetdone_reg2;
  wire rxratedone_i_1__0_n_0;
  wire rxratedone_reg1;
  wire rxratedone_reg2;
  wire rxratedone_reg_n_0;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxsync_done_reg1;
  wire rxsync_done_reg2;
  wire \sysclksel[0]_i_1__0_n_0 ;
  wire \sysclksel[0]_i_2__0_n_0 ;
  wire \sysclksel[0]_i_3__0_n_0 ;
  wire \sysclksel[1]_i_1__0_n_0 ;
  wire \txdata_wait_cnt[3]_i_2__0_n_0 ;
  wire [3:0]txdata_wait_cnt_reg__0__0;
  wire txpmareset_i_1__0_n_0;
  wire txpmareset_i_2__0_n_0;
  wire txratedone_i_1__0_n_0;
  wire txratedone_i_2__0_n_0;
  wire txratedone_reg1;
  wire txratedone_reg2;
  wire txratedone_reg_n_0;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire txsync_done_reg1;
  wire txsync_done_reg2;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_CPLLLOCK),
        .Q(cplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cplllock_reg1),
        .Q(cplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllpd_i_1__0
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(p_0_in95_in),
        .O(cpllpd_i_1__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT5 #(
    .INIT(32'h80000084)) 
    cpllpd_i_2__0
       (.I0(Q[4]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(qpllpd));
  FDRE #(
    .INIT(1'b0)) 
    cpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllpd_i_1__0_n_0),
        .Q(p_0_in95_in),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllreset_i_1__1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(p_0_in93_in),
        .O(cpllreset_i_1__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT5 #(
    .INIT(32'h81000002)) 
    cpllreset_i_2__0
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(qpllreset));
  FDRE #(
    .INIT(1'b0)) 
    cpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllreset_i_1__1_n_0),
        .Q(p_0_in93_in),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_DRP_DONE),
        .Q(drp_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT5 #(
    .INIT(32'h08200108)) 
    drp_start_i_1__0
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(Q[1]),
        .O(drp_start_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_start_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_start_i_1__0_n_0),
        .Q(p_0_in101_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT5 #(
    .INIT(32'h20020006)) 
    drp_x16_i_1__0
       (.I0(Q[2]),
        .I1(Q[4]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[0]),
        .O(drp_x16_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16_i_1__0_n_0),
        .Q(p_0_in103_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT5 #(
    .INIT(32'h20001584)) 
    drp_x16x20_mode_i_1__0
       (.I0(Q[1]),
        .I1(Q[4]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(drp_x16x20_mode_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16x20_mode_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16x20_mode_i_1__0_n_0),
        .Q(p_0_in105_in),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[0]_i_10__0 
       (.I0(txdata_wait_cnt_reg__0__0[3]),
        .I1(txdata_wait_cnt_reg__0__0[2]),
        .I2(txdata_wait_cnt_reg__0__0[0]),
        .I3(txdata_wait_cnt_reg__0__0[1]),
        .O(\fsm[0]_i_10__0_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000F404)) 
    \fsm[0]_i_11__0 
       (.I0(rxpmaresetdone_reg2),
        .I1(mmcm_lock_reg2),
        .I2(Q[0]),
        .I3(drp_done_reg2),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\fsm[0]_i_11__0_n_0 ));
  LUT6 #(
    .INIT(64'h4F4F737F4343404C)) 
    \fsm[0]_i_12__0 
       (.I0(resetovrd_done_reg2),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(rxpmaresetdone_reg2),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[0]_i_12__0_n_0 ));
  LUT6 #(
    .INIT(64'hBBB88888BBB8BBB8)) 
    \fsm[0]_i_1__1 
       (.I0(\fsm_reg[0]_i_2__0_n_0 ),
        .I1(Q[4]),
        .I2(\fsm[0]_i_3__1_n_0 ),
        .I3(Q[3]),
        .I4(\fsm[0]_i_4__0_n_0 ),
        .I5(\fsm[0]_i_5__0_n_0 ),
        .O(fsm[0]));
  LUT6 #(
    .INIT(64'h0344FF440344FF77)) 
    \fsm[0]_i_3__1 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(pll_lock),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\fsm[3]_i_9__0_n_0 ),
        .O(\fsm[0]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0000000F800F000)) 
    \fsm[0]_i_4__0 
       (.I0(pll_lock),
        .I1(rst_idle_reg2),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(drp_done_reg2),
        .I5(Q[0]),
        .O(\fsm[0]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000CCC8C0C8)) 
    \fsm[0]_i_5__0 
       (.I0(\fsm[0]_i_8__0_n_0 ),
        .I1(Q[3]),
        .I2(\fsm[0]_i_9__0_n_0 ),
        .I3(Q[0]),
        .I4(\fsm[0]_i_10__0_n_0 ),
        .I5(\fsm[0]_i_11__0_n_0 ),
        .O(\fsm[0]_i_5__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0040)) 
    \fsm[0]_i_6__0 
       (.I0(fsm1),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(\fsm[0]_i_12__0_n_0 ),
        .O(\fsm[0]_i_6__0_n_0 ));
  LUT5 #(
    .INIT(32'h03880333)) 
    \fsm[0]_i_7__0 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[0]_i_7__0_n_0 ));
  LUT5 #(
    .INIT(32'h77770777)) 
    \fsm[0]_i_8__0 
       (.I0(p_0_in7_in),
        .I1(p_1_in8_in),
        .I2(rxresetdone_reg2),
        .I3(txresetdone_reg2),
        .I4(phystatus_reg2),
        .O(\fsm[0]_i_8__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \fsm[0]_i_9__0 
       (.I0(Q[1]),
        .I1(Q[2]),
        .O(\fsm[0]_i_9__0_n_0 ));
  LUT5 #(
    .INIT(32'h30BBFC00)) 
    \fsm[1]_i_4__0 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(\fsm[1]_i_8__0_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'hCC88300000BB3000)) 
    \fsm[1]_i_5__0 
       (.I0(\fsm[0]_i_10__0_n_0 ),
        .I1(Q[2]),
        .I2(\fsm[1]_i_9__0_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_5__0_n_0 ));
  LUT5 #(
    .INIT(32'h70F040F0)) 
    \fsm[1]_i_6__0 
       (.I0(resetovrd_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(drp_done_reg2),
        .O(\fsm[1]_i_6__0_n_0 ));
  LUT5 #(
    .INIT(32'h03777700)) 
    \fsm[1]_i_7__0 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_7__0_n_0 ));
  LUT6 #(
    .INIT(64'h53F5FFFFFFFFFFFF)) 
    \fsm[1]_i_8__0 
       (.I0(cplllock_reg2),
        .I1(qplllock_reg2),
        .I2(rate_in_reg2[0]),
        .I3(rate_in_reg2[1]),
        .I4(rst_idle_reg2),
        .I5(Q[0]),
        .O(\fsm[1]_i_8__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF4575FFFFFFFF)) 
    \fsm[1]_i_9__0 
       (.I0(cplllock_reg2),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .I3(qplllock_reg2),
        .I4(rst_idle_reg2),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_9__0_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fsm[2]_i_1__1 
       (.I0(\fsm[2]_i_2__0_n_0 ),
        .I1(\fsm[2]_i_3__0_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[2]_i_4__0_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[2]_i_5__0_n_0 ),
        .O(fsm[2]));
  LUT5 #(
    .INIT(32'h3C0C4040)) 
    \fsm[2]_i_2__0 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_done_reg2),
        .I4(Q[0]),
        .O(\fsm[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h13CCD3CC1FCCDFCC)) 
    \fsm[2]_i_3__0 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(resetovrd_done_reg2),
        .I5(fsm1),
        .O(\fsm[2]_i_3__0_n_0 ));
  LUT4 #(
    .INIT(16'hBC0C)) 
    \fsm[2]_i_4__0 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\fsm[2]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h4A4A4A4AAAAFAAAA)) 
    \fsm[2]_i_5__0 
       (.I0(Q[2]),
        .I1(pll_lock),
        .I2(Q[1]),
        .I3(\fsm[3]_i_9__0_n_0 ),
        .I4(\fsm[3]_i_8__0_n_0 ),
        .I5(Q[0]),
        .O(\fsm[2]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'hEFE0EFEFEFE0E0E0)) 
    \fsm[3]_i_1__0 
       (.I0(\fsm[3]_i_2__0_n_0 ),
        .I1(\fsm[3]_i_3__0_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[3]_i_4__0_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[3]_i_5__0_n_0 ),
        .O(fsm[3]));
  LUT5 #(
    .INIT(32'h22AA2A22)) 
    \fsm[3]_i_2__0 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(rxsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h3020002000000000)) 
    \fsm[3]_i_3__0 
       (.I0(fsm1),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(resetovrd_done_reg2),
        .I5(Q[0]),
        .O(\fsm[3]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hF545F555FFFFFFFF)) 
    \fsm[3]_i_4__0 
       (.I0(Q[2]),
        .I1(rst_idle_reg2),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(pll_lock),
        .I5(Q[1]),
        .O(\fsm[3]_i_4__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT5 #(
    .INIT(32'h80808180)) 
    \fsm[3]_i_5__0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\fsm[3]_i_8__0_n_0 ),
        .I4(\fsm[3]_i_9__0_n_0 ),
        .O(\fsm[3]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8F8FFF8)) 
    \fsm[3]_i_6__0 
       (.I0(p_1_in8_in),
        .I1(p_0_in7_in),
        .I2(ratedone_reg_n_0),
        .I3(rate_in_reg2[1]),
        .I4(rate_in_reg2[0]),
        .I5(gen3_exit),
        .O(fsm1));
  LUT4 #(
    .INIT(16'hFB08)) 
    \fsm[3]_i_7__0 
       (.I0(qplllock_reg2),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(cplllock_reg2),
        .O(pll_lock));
  LUT4 #(
    .INIT(16'hB0BB)) 
    \fsm[3]_i_8__0 
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg1[0]),
        .I3(rate_in_reg1[1]),
        .O(\fsm[3]_i_8__0_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \fsm[3]_i_9__0 
       (.I0(rate_in_reg1[0]),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg1[1]),
        .I3(rate_in_reg2[1]),
        .O(\fsm[3]_i_9__0_n_0 ));
  LUT5 #(
    .INIT(32'h08880000)) 
    \fsm[4]_i_2__0 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\fsm[4]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h5F75FFFF)) 
    \fsm[4]_i_3__0 
       (.I0(Q[2]),
        .I1(rxsync_done_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\fsm[4]_i_3__0_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  MUXF7 \fsm_reg[0]_i_2__0 
       (.I0(\fsm[0]_i_6__0_n_0 ),
        .I1(\fsm[0]_i_7__0_n_0 ),
        .O(\fsm_reg[0]_i_2__0_n_0 ),
        .S(Q[3]));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .S(RST_CPLLRESET));
  MUXF8 \fsm_reg[1]_i_1__0 
       (.I0(\fsm_reg[1]_i_2__0_n_0 ),
        .I1(\fsm_reg[1]_i_3__0_n_0 ),
        .O(fsm[1]),
        .S(Q[4]));
  MUXF7 \fsm_reg[1]_i_2__0 
       (.I0(\fsm[1]_i_4__0_n_0 ),
        .I1(\fsm[1]_i_5__0_n_0 ),
        .O(\fsm_reg[1]_i_2__0_n_0 ),
        .S(Q[3]));
  MUXF7 \fsm_reg[1]_i_3__0 
       (.I0(\fsm[1]_i_6__0_n_0 ),
        .I1(\fsm[1]_i_7__0_n_0 ),
        .O(\fsm_reg[1]_i_3__0_n_0 ),
        .S(Q[3]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  MUXF7 \fsm_reg[4]_i_1__0 
       (.I0(\fsm[4]_i_2__0_n_0 ),
        .I1(\fsm[4]_i_3__0_n_0 ),
        .O(fsm[4]),
        .S(Q[4]));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_exit_i_1__0
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_exit_i_2__0_n_0),
        .I4(gen3_exit),
        .O(gen3_exit_i_1__0_n_0));
  LUT6 #(
    .INIT(64'hC000000000000001)) 
    gen3_exit_i_2__0
       (.I0(\fsm[3]_i_9__0_n_0 ),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(gen3_exit_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_exit_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_exit_i_1__0_n_0),
        .Q(gen3_exit),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_i_1__0
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_i_2__0_n_0),
        .I4(rate_gen3),
        .O(gen3_i_1__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT5 #(
    .INIT(32'h80000008)) 
    gen3_i_2__0
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[1]),
        .O(gen3_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_i_1__0_n_0),
        .Q(rate_gen3),
        .R(RST_CPLLRESET));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_6__5 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[1]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_7__0 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[1] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_MMCM_LOCK),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h06FF0600)) 
    pclk_sel_i_1__1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(pclk_sel_i_2__0_n_0),
        .I4(USER_PCLK_SEL),
        .O(pclk_sel_i_1__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT5 #(
    .INIT(32'h80040800)) 
    pclk_sel_i_2__0
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(pclk_sel_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(pclk_sel_i_1__1_n_0),
        .Q(USER_PCLK_SEL),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    phystatus_i_1__0
       (.I0(phystatus_reg2),
        .I1(txratedone_i_2__0_n_0),
        .I2(phystatus_reg_n_0),
        .O(phystatus_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    phystatus_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_i_1__0_n_0),
        .Q(phystatus_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_PHYSTATUS),
        .Q(phystatus_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_reg1),
        .Q(phystatus_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_QPLLLOCK),
        .Q(qplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllpd_i_1__1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(QRST_QPLLPD_IN),
        .O(qpllpd_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllpd_i_1__1_n_0),
        .Q(QRST_QPLLPD_IN),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllreset_i_1__1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(QRST_QPLLRESET_IN),
        .O(qpllreset_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllreset_i_1__1_n_0),
        .Q(QRST_QPLLRESET_IN),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    rate_done_reg1_i_1__0
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(USER_RATE_DONE));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \rate_idle_reg1[1]_i_1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(RST_RATE_IDLE));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_in_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_in_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[0]),
        .Q(rate_in_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[1]),
        .Q(rate_in_reg2[1]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    \rate_out[0]_i_1__0 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .I2(Q[1]),
        .I3(\rate_out[2]_i_2__0_n_0 ),
        .I4(RXRATE[0]),
        .O(\rate_out[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[1]_i_1__0 
       (.I0(\rate_out[2]_i_2__0_n_0 ),
        .I1(RXRATE[1]),
        .O(\rate_out[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[2]_i_1__0 
       (.I0(\rate_out[2]_i_2__0_n_0 ),
        .I1(RXRATE[2]),
        .O(\rate_out[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h8000002080000220)) 
    \rate_out[2]_i_2__0 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\rate_out[2]_i_3__0_n_0 ),
        .O(\rate_out[2]_i_2__0_n_0 ));
  LUT3 #(
    .INIT(8'h45)) 
    \rate_out[2]_i_3__0 
       (.I0(gen3_exit),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .O(\rate_out[2]_i_3__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[0]_i_1__0_n_0 ),
        .Q(RXRATE[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[1]_i_1__0_n_0 ),
        .Q(RXRATE[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[2]_i_1__0_n_0 ),
        .Q(RXRATE[2]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT5 #(
    .INIT(32'h00808000)) 
    rate_rxsync_reg1_i_1__0
       (.I0(Q[3]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(USER_RATE_RXSYNC));
  LUT5 #(
    .INIT(32'hFF008000)) 
    ratedone_i_1__0
       (.I0(rxratedone_reg_n_0),
        .I1(txratedone_reg_n_0),
        .I2(phystatus_reg_n_0),
        .I3(txratedone_i_2__0_n_0),
        .I4(ratedone_reg_n_0),
        .O(ratedone_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(ratedone_i_1__0_n_0),
        .Q(ratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RESETOVRD_DONE),
        .Q(resetovrd_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(resetovrd_done_reg1),
        .Q(resetovrd_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    resetovrd_start_reg1_i_1__0
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[4]),
        .I4(Q[2]),
        .O(USER_RESETOVRD_START));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(out1[1]),
        .Q(rst_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1),
        .Q(rxpmaresetdone_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    rxratedone_i_1__0
       (.I0(rxratedone_reg2),
        .I1(txratedone_i_2__0_n_0),
        .I2(rxratedone_reg_n_0),
        .O(rxratedone_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_i_1__0_n_0),
        .Q(rxratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RXRATEDONE),
        .Q(rxratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_reg1),
        .Q(rxratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONE),
        .Q(rxsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxsync_done_reg1),
        .Q(rxsync_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    rxsync_start_reg1_i_1__0
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(SYNC_RXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    start_reg1_i_1__0
       (.I0(p_0_in101_in),
        .I1(RST_DRP_START),
        .O(DRP_START0102_out));
  LUT6 #(
    .INIT(64'hFFFF3EFF00000200)) 
    \sysclksel[0]_i_1__0 
       (.I0(\sysclksel[0]_i_2__0_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(\sysclksel[0]_i_3__0_n_0 ),
        .I5(RXSYSCLKSEL[0]),
        .O(\sysclksel[0]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \sysclksel[0]_i_2__0 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .O(\sysclksel[0]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \sysclksel[0]_i_3__0 
       (.I0(Q[2]),
        .I1(Q[1]),
        .O(\sysclksel[0]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h6FFFFFFF00000000)) 
    \sysclksel[1]_i_1__0 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(RXSYSCLKSEL[1]),
        .O(\sysclksel[1]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[0]_i_1__0_n_0 ),
        .Q(RXSYSCLKSEL[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[1]_i_1__0_n_0 ),
        .Q(RXSYSCLKSEL[1]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT5 #(
    .INIT(32'h80AA00AA)) 
    \txdata_wait_cnt[0]_i_1__0 
       (.I0(\txdata_wait_cnt[3]_i_2__0_n_0 ),
        .I1(txdata_wait_cnt_reg__0__0[3]),
        .I2(txdata_wait_cnt_reg__0__0[2]),
        .I3(txdata_wait_cnt_reg__0__0[0]),
        .I4(txdata_wait_cnt_reg__0__0[1]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT5 #(
    .INIT(32'hA8282828)) 
    \txdata_wait_cnt[1]_i_1__0 
       (.I0(\txdata_wait_cnt[3]_i_2__0_n_0 ),
        .I1(txdata_wait_cnt_reg__0__0[0]),
        .I2(txdata_wait_cnt_reg__0__0[1]),
        .I3(txdata_wait_cnt_reg__0__0[3]),
        .I4(txdata_wait_cnt_reg__0__0[2]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT5 #(
    .INIT(32'h8AA0A0A0)) 
    \txdata_wait_cnt[2]_i_1__0 
       (.I0(\txdata_wait_cnt[3]_i_2__0_n_0 ),
        .I1(txdata_wait_cnt_reg__0__0[3]),
        .I2(txdata_wait_cnt_reg__0__0[2]),
        .I3(txdata_wait_cnt_reg__0__0[0]),
        .I4(txdata_wait_cnt_reg__0__0[1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \txdata_wait_cnt[3]_i_1__0 
       (.I0(\txdata_wait_cnt[3]_i_2__0_n_0 ),
        .I1(txdata_wait_cnt_reg__0__0[2]),
        .I2(txdata_wait_cnt_reg__0__0[1]),
        .I3(txdata_wait_cnt_reg__0__0[0]),
        .I4(txdata_wait_cnt_reg__0__0[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \txdata_wait_cnt[3]_i_2__0 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\txdata_wait_cnt[3]_i_2__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(txdata_wait_cnt_reg__0__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(txdata_wait_cnt_reg__0__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(txdata_wait_cnt_reg__0__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(txdata_wait_cnt_reg__0__0[3]),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h5504FFFF55040000)) 
    txpmareset_i_1__0
       (.I0(Q[3]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(gen3_exit),
        .I4(txpmareset_i_2__0_n_0),
        .I5(GT_TXPMARESET092_out),
        .O(txpmareset_i_1__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT5 #(
    .INIT(32'h82000400)) 
    txpmareset_i_2__0
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(txpmareset_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txpmareset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txpmareset_i_1__0_n_0),
        .Q(GT_TXPMARESET092_out),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    txratedone_i_1__0
       (.I0(txratedone_reg2),
        .I1(txratedone_i_2__0_n_0),
        .I2(txratedone_reg_n_0),
        .O(txratedone_i_1__0_n_0));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    txratedone_i_2__0
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(RST_CPLLRESET),
        .O(txratedone_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_i_1__0_n_0),
        .Q(txratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXRATEDONE),
        .Q(txratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_reg1),
        .Q(txratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXSYNC_DONE),
        .Q(txsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txsync_done_reg1),
        .Q(txsync_done_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAA)) 
    txsync_start_reg1_i_1__0
       (.I0(out1[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(SYNC_TXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    x16_reg1_i_1__0
       (.I0(p_0_in103_in),
        .I1(RST_DRP_X16),
        .O(DRP_X160104_out));
  LUT2 #(
    .INIT(4'hE)) 
    x16x20_mode_reg1_i_1__0
       (.I0(p_0_in105_in),
        .I1(RST_DRP_X16X20_MODE),
        .O(DRP_X16X20_MODE0106_out));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_rate" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_38
   (Q,
    USER_RESETOVRD_START,
    RXSYSCLKSEL,
    SYNC_TXSYNC_START,
    DRP_X16X20_MODE0114_out,
    DRP_X160112_out,
    DRP_START0110_out,
    \cplllock_reg1_reg[2] ,
    rate_gen3,
    \cplllock_reg1_reg[2]_0 ,
    RXRATE,
    USER_RATE_DONE,
    USER_RATE_RXSYNC,
    SYNC_RXSYNC_START,
    RST_RATE_IDLE,
    GT_TXPMARESET0120_out,
    USER_PCLK_SEL,
    QRST_QPLLRESET_IN,
    p_0_in121_in,
    QRST_QPLLPD_IN,
    p_0_in123_in,
    out1,
    RST_DRP_X16X20_MODE,
    RST_DRP_X16,
    RST_DRP_START,
    RST_CPLLRESET,
    pclk_sel_reg_0,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    RATE_CPLLLOCK,
    RATE_QPLLLOCK,
    RATE_DRP_DONE,
    \resetovrd_disble.reset_reg[4] ,
    RATE_PHYSTATUS,
    USER_TXRESETDONE,
    USER_RXRESETDONE,
    RATE_TXRATEDONE,
    RATE_RXRATEDONE,
    RATE_RESETOVRD_DONE,
    RATE_TXSYNC_DONE,
    SYNC_RXSYNC_DONE,
    p_1_in8_in,
    p_0_in7_in);
  output [4:0]Q;
  output USER_RESETOVRD_START;
  output [1:0]RXSYSCLKSEL;
  output SYNC_TXSYNC_START;
  output DRP_X16X20_MODE0114_out;
  output DRP_X160112_out;
  output DRP_START0110_out;
  output \cplllock_reg1_reg[2] ;
  output [0:0]rate_gen3;
  output \cplllock_reg1_reg[2]_0 ;
  output [2:0]RXRATE;
  output USER_RATE_DONE;
  output USER_RATE_RXSYNC;
  output SYNC_RXSYNC_START;
  output [0:0]RST_RATE_IDLE;
  output GT_TXPMARESET0120_out;
  output USER_PCLK_SEL;
  output [0:0]QRST_QPLLRESET_IN;
  output p_0_in121_in;
  output [0:0]QRST_QPLLPD_IN;
  output p_0_in123_in;
  input [1:0]out1;
  input RST_DRP_X16X20_MODE;
  input RST_DRP_X16;
  input RST_DRP_START;
  input RST_CPLLRESET;
  input pclk_sel_reg_0;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input RATE_CPLLLOCK;
  input RATE_QPLLLOCK;
  input RATE_DRP_DONE;
  input \resetovrd_disble.reset_reg[4] ;
  input RATE_PHYSTATUS;
  input USER_TXRESETDONE;
  input USER_RXRESETDONE;
  input RATE_TXRATEDONE;
  input RATE_RXRATEDONE;
  input RATE_RESETOVRD_DONE;
  input RATE_TXSYNC_DONE;
  input SYNC_RXSYNC_DONE;
  input p_1_in8_in;
  input p_0_in7_in;

  wire DRP_START0110_out;
  wire DRP_X160112_out;
  wire DRP_X16X20_MODE0114_out;
  wire GT_TXPMARESET0120_out;
  wire [4:0]Q;
  wire [0:0]QRST_QPLLPD_IN;
  wire [0:0]QRST_QPLLRESET_IN;
  wire RATE_CPLLLOCK;
  wire RATE_DRP_DONE;
  wire RATE_PHYSTATUS;
  wire RATE_QPLLLOCK;
  wire RATE_RESETOVRD_DONE;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RATE_TXSYNC_DONE;
  wire RST_CPLLRESET;
  wire RST_DRP_START;
  wire RST_DRP_X16;
  wire RST_DRP_X16X20_MODE;
  wire [0:0]RST_RATE_IDLE;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXSYNC_START;
  wire USER_PCLK_SEL;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire cplllock_reg1;
  wire \cplllock_reg1_reg[2] ;
  wire \cplllock_reg1_reg[2]_0 ;
  wire cplllock_reg2;
  wire cpllpd_i_1__1_n_0;
  wire cpllreset_i_1__2_n_0;
  wire drp_done_reg1;
  wire drp_done_reg2;
  wire drp_start_i_1__1_n_0;
  wire drp_x16_i_1__1_n_0;
  wire drp_x16x20_mode_i_1__1_n_0;
  wire [4:0]fsm;
  wire fsm1;
  wire \fsm[0]_i_10__1_n_0 ;
  wire \fsm[0]_i_11__1_n_0 ;
  wire \fsm[0]_i_12__1_n_0 ;
  wire \fsm[0]_i_3__3_n_0 ;
  wire \fsm[0]_i_4__1_n_0 ;
  wire \fsm[0]_i_5__1_n_0 ;
  wire \fsm[0]_i_6__1_n_0 ;
  wire \fsm[0]_i_7__1_n_0 ;
  wire \fsm[0]_i_8__1_n_0 ;
  wire \fsm[0]_i_9__1_n_0 ;
  wire \fsm[1]_i_4__1_n_0 ;
  wire \fsm[1]_i_5__1_n_0 ;
  wire \fsm[1]_i_6__1_n_0 ;
  wire \fsm[1]_i_7__1_n_0 ;
  wire \fsm[1]_i_8__1_n_0 ;
  wire \fsm[1]_i_9__1_n_0 ;
  wire \fsm[2]_i_2__1_n_0 ;
  wire \fsm[2]_i_3__1_n_0 ;
  wire \fsm[2]_i_4__1_n_0 ;
  wire \fsm[2]_i_5__1_n_0 ;
  wire \fsm[3]_i_2__1_n_0 ;
  wire \fsm[3]_i_3__1_n_0 ;
  wire \fsm[3]_i_4__1_n_0 ;
  wire \fsm[3]_i_5__1_n_0 ;
  wire \fsm[3]_i_8__1_n_0 ;
  wire \fsm[3]_i_9__1_n_0 ;
  wire \fsm[4]_i_2__1_n_0 ;
  wire \fsm[4]_i_3__1_n_0 ;
  wire \fsm_reg[0]_i_2__1_n_0 ;
  wire \fsm_reg[1]_i_2__1_n_0 ;
  wire \fsm_reg[1]_i_3__1_n_0 ;
  wire gen3_exit;
  wire gen3_exit_i_1__1_n_0;
  wire gen3_exit_i_2__1_n_0;
  wire gen3_i_1__1_n_0;
  wire gen3_i_2__1_n_0;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire [1:0]out1;
  wire p_0_in109_in;
  wire p_0_in111_in;
  wire p_0_in113_in;
  wire p_0_in121_in;
  wire p_0_in123_in;
  wire p_0_in7_in;
  wire [3:0]p_0_in__0;
  wire p_1_in8_in;
  wire pclk_sel_i_1__2_n_0;
  wire pclk_sel_i_2__1_n_0;
  wire pclk_sel_reg_0;
  wire phystatus_i_1__1_n_0;
  wire phystatus_reg1;
  wire phystatus_reg2;
  wire phystatus_reg_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire pll_lock;
  wire qplllock_reg1;
  wire qplllock_reg2;
  wire qpllpd;
  wire qpllpd_i_1__2_n_0;
  wire qpllreset;
  wire qpllreset_i_1__2_n_0;
  wire [0:0]rate_gen3;
  wire [1:0]rate_in_reg1;
  wire [1:0]rate_in_reg2;
  wire \rate_out[0]_i_1__1_n_0 ;
  wire \rate_out[1]_i_1__1_n_0 ;
  wire \rate_out[2]_i_1__1_n_0 ;
  wire \rate_out[2]_i_2__1_n_0 ;
  wire \rate_out[2]_i_3__1_n_0 ;
  wire ratedone_i_1__1_n_0;
  wire ratedone_reg_n_0;
  wire \resetovrd_disble.reset_reg[4] ;
  wire resetovrd_done_reg1;
  wire resetovrd_done_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire rxpmaresetdone_reg1;
  wire rxpmaresetdone_reg2;
  wire rxratedone_i_1__1_n_0;
  wire rxratedone_reg1;
  wire rxratedone_reg2;
  wire rxratedone_reg_n_0;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxsync_done_reg1;
  wire rxsync_done_reg2;
  wire \sysclksel[0]_i_1__1_n_0 ;
  wire \sysclksel[0]_i_2__1_n_0 ;
  wire \sysclksel[0]_i_3__1_n_0 ;
  wire \sysclksel[1]_i_1__1_n_0 ;
  wire \txdata_wait_cnt[3]_i_2__1_n_0 ;
  wire [3:0]txdata_wait_cnt_reg__0;
  wire txpmareset_i_1__1_n_0;
  wire txpmareset_i_2__1_n_0;
  wire txratedone_i_1__1_n_0;
  wire txratedone_i_2__1_n_0;
  wire txratedone_reg1;
  wire txratedone_reg2;
  wire txratedone_reg_n_0;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire txsync_done_reg1;
  wire txsync_done_reg2;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_CPLLLOCK),
        .Q(cplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cplllock_reg1),
        .Q(cplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllpd_i_1__1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(p_0_in123_in),
        .O(cpllpd_i_1__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT5 #(
    .INIT(32'h80000084)) 
    cpllpd_i_2__1
       (.I0(Q[4]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(qpllpd));
  FDRE #(
    .INIT(1'b0)) 
    cpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllpd_i_1__1_n_0),
        .Q(p_0_in123_in),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllreset_i_1__2
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(p_0_in121_in),
        .O(cpllreset_i_1__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT5 #(
    .INIT(32'h81000002)) 
    cpllreset_i_2__1
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(qpllreset));
  FDRE #(
    .INIT(1'b0)) 
    cpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllreset_i_1__2_n_0),
        .Q(p_0_in121_in),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_DRP_DONE),
        .Q(drp_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT5 #(
    .INIT(32'h08200108)) 
    drp_start_i_1__1
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(Q[1]),
        .O(drp_start_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_start_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_start_i_1__1_n_0),
        .Q(p_0_in109_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT5 #(
    .INIT(32'h20020006)) 
    drp_x16_i_1__1
       (.I0(Q[2]),
        .I1(Q[4]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[0]),
        .O(drp_x16_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16_i_1__1_n_0),
        .Q(p_0_in111_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT5 #(
    .INIT(32'h20001584)) 
    drp_x16x20_mode_i_1__1
       (.I0(Q[1]),
        .I1(Q[4]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(drp_x16x20_mode_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16x20_mode_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16x20_mode_i_1__1_n_0),
        .Q(p_0_in113_in),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[0]_i_10__1 
       (.I0(txdata_wait_cnt_reg__0[3]),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[0]),
        .I3(txdata_wait_cnt_reg__0[1]),
        .O(\fsm[0]_i_10__1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000F404)) 
    \fsm[0]_i_11__1 
       (.I0(rxpmaresetdone_reg2),
        .I1(mmcm_lock_reg2),
        .I2(Q[0]),
        .I3(drp_done_reg2),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\fsm[0]_i_11__1_n_0 ));
  LUT6 #(
    .INIT(64'h4F4F737F4343404C)) 
    \fsm[0]_i_12__1 
       (.I0(resetovrd_done_reg2),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(rxpmaresetdone_reg2),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[0]_i_12__1_n_0 ));
  LUT6 #(
    .INIT(64'hBBB88888BBB8BBB8)) 
    \fsm[0]_i_1__3 
       (.I0(\fsm_reg[0]_i_2__1_n_0 ),
        .I1(Q[4]),
        .I2(\fsm[0]_i_3__3_n_0 ),
        .I3(Q[3]),
        .I4(\fsm[0]_i_4__1_n_0 ),
        .I5(\fsm[0]_i_5__1_n_0 ),
        .O(fsm[0]));
  LUT6 #(
    .INIT(64'h0344FF440344FF77)) 
    \fsm[0]_i_3__3 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(pll_lock),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\fsm[3]_i_9__1_n_0 ),
        .O(\fsm[0]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hF0000000F800F000)) 
    \fsm[0]_i_4__1 
       (.I0(pll_lock),
        .I1(rst_idle_reg2),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(drp_done_reg2),
        .I5(Q[0]),
        .O(\fsm[0]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000CCC8C0C8)) 
    \fsm[0]_i_5__1 
       (.I0(\fsm[0]_i_8__1_n_0 ),
        .I1(Q[3]),
        .I2(\fsm[0]_i_9__1_n_0 ),
        .I3(Q[0]),
        .I4(\fsm[0]_i_10__1_n_0 ),
        .I5(\fsm[0]_i_11__1_n_0 ),
        .O(\fsm[0]_i_5__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0040)) 
    \fsm[0]_i_6__1 
       (.I0(fsm1),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(\fsm[0]_i_12__1_n_0 ),
        .O(\fsm[0]_i_6__1_n_0 ));
  LUT5 #(
    .INIT(32'h03880333)) 
    \fsm[0]_i_7__1 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[0]_i_7__1_n_0 ));
  LUT5 #(
    .INIT(32'h77770777)) 
    \fsm[0]_i_8__1 
       (.I0(p_0_in7_in),
        .I1(p_1_in8_in),
        .I2(rxresetdone_reg2),
        .I3(txresetdone_reg2),
        .I4(phystatus_reg2),
        .O(\fsm[0]_i_8__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \fsm[0]_i_9__1 
       (.I0(Q[1]),
        .I1(Q[2]),
        .O(\fsm[0]_i_9__1_n_0 ));
  LUT5 #(
    .INIT(32'h30BBFC00)) 
    \fsm[1]_i_4__1 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(\fsm[1]_i_8__1_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'hCC88300000BB3000)) 
    \fsm[1]_i_5__1 
       (.I0(\fsm[0]_i_10__1_n_0 ),
        .I1(Q[2]),
        .I2(\fsm[1]_i_9__1_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_5__1_n_0 ));
  LUT5 #(
    .INIT(32'h70F040F0)) 
    \fsm[1]_i_6__1 
       (.I0(resetovrd_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(drp_done_reg2),
        .O(\fsm[1]_i_6__1_n_0 ));
  LUT5 #(
    .INIT(32'h03777700)) 
    \fsm[1]_i_7__1 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_7__1_n_0 ));
  LUT6 #(
    .INIT(64'h53F5FFFFFFFFFFFF)) 
    \fsm[1]_i_8__1 
       (.I0(cplllock_reg2),
        .I1(qplllock_reg2),
        .I2(rate_in_reg2[0]),
        .I3(rate_in_reg2[1]),
        .I4(rst_idle_reg2),
        .I5(Q[0]),
        .O(\fsm[1]_i_8__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF4575FFFFFFFF)) 
    \fsm[1]_i_9__1 
       (.I0(cplllock_reg2),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .I3(qplllock_reg2),
        .I4(rst_idle_reg2),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_9__1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fsm[2]_i_1__3 
       (.I0(\fsm[2]_i_2__1_n_0 ),
        .I1(\fsm[2]_i_3__1_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[2]_i_4__1_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[2]_i_5__1_n_0 ),
        .O(fsm[2]));
  LUT5 #(
    .INIT(32'h3C0C4040)) 
    \fsm[2]_i_2__1 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_done_reg2),
        .I4(Q[0]),
        .O(\fsm[2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h13CCD3CC1FCCDFCC)) 
    \fsm[2]_i_3__1 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(resetovrd_done_reg2),
        .I5(fsm1),
        .O(\fsm[2]_i_3__1_n_0 ));
  LUT4 #(
    .INIT(16'hBC0C)) 
    \fsm[2]_i_4__1 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\fsm[2]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'h4A4A4A4AAAAFAAAA)) 
    \fsm[2]_i_5__1 
       (.I0(Q[2]),
        .I1(pll_lock),
        .I2(Q[1]),
        .I3(\fsm[3]_i_9__1_n_0 ),
        .I4(\fsm[3]_i_8__1_n_0 ),
        .I5(Q[0]),
        .O(\fsm[2]_i_5__1_n_0 ));
  LUT6 #(
    .INIT(64'hEFE0EFEFEFE0E0E0)) 
    \fsm[3]_i_1__1 
       (.I0(\fsm[3]_i_2__1_n_0 ),
        .I1(\fsm[3]_i_3__1_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[3]_i_4__1_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[3]_i_5__1_n_0 ),
        .O(fsm[3]));
  LUT5 #(
    .INIT(32'h22AA2A22)) 
    \fsm[3]_i_2__1 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(rxsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[3]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h3020002000000000)) 
    \fsm[3]_i_3__1 
       (.I0(fsm1),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(resetovrd_done_reg2),
        .I5(Q[0]),
        .O(\fsm[3]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hF545F555FFFFFFFF)) 
    \fsm[3]_i_4__1 
       (.I0(Q[2]),
        .I1(rst_idle_reg2),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(pll_lock),
        .I5(Q[1]),
        .O(\fsm[3]_i_4__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT5 #(
    .INIT(32'h80808180)) 
    \fsm[3]_i_5__1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\fsm[3]_i_8__1_n_0 ),
        .I4(\fsm[3]_i_9__1_n_0 ),
        .O(\fsm[3]_i_5__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8F8FFF8)) 
    \fsm[3]_i_6__1 
       (.I0(p_1_in8_in),
        .I1(p_0_in7_in),
        .I2(ratedone_reg_n_0),
        .I3(rate_in_reg2[1]),
        .I4(rate_in_reg2[0]),
        .I5(gen3_exit),
        .O(fsm1));
  LUT4 #(
    .INIT(16'hFB08)) 
    \fsm[3]_i_7__1 
       (.I0(qplllock_reg2),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(cplllock_reg2),
        .O(pll_lock));
  LUT4 #(
    .INIT(16'hB0BB)) 
    \fsm[3]_i_8__1 
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg1[0]),
        .I3(rate_in_reg1[1]),
        .O(\fsm[3]_i_8__1_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \fsm[3]_i_9__1 
       (.I0(rate_in_reg1[0]),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg1[1]),
        .I3(rate_in_reg2[1]),
        .O(\fsm[3]_i_9__1_n_0 ));
  LUT5 #(
    .INIT(32'h08880000)) 
    \fsm[4]_i_2__1 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\fsm[4]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h5F75FFFF)) 
    \fsm[4]_i_3__1 
       (.I0(Q[2]),
        .I1(rxsync_done_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\fsm[4]_i_3__1_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  MUXF7 \fsm_reg[0]_i_2__1 
       (.I0(\fsm[0]_i_6__1_n_0 ),
        .I1(\fsm[0]_i_7__1_n_0 ),
        .O(\fsm_reg[0]_i_2__1_n_0 ),
        .S(Q[3]));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .S(RST_CPLLRESET));
  MUXF8 \fsm_reg[1]_i_1__1 
       (.I0(\fsm_reg[1]_i_2__1_n_0 ),
        .I1(\fsm_reg[1]_i_3__1_n_0 ),
        .O(fsm[1]),
        .S(Q[4]));
  MUXF7 \fsm_reg[1]_i_2__1 
       (.I0(\fsm[1]_i_4__1_n_0 ),
        .I1(\fsm[1]_i_5__1_n_0 ),
        .O(\fsm_reg[1]_i_2__1_n_0 ),
        .S(Q[3]));
  MUXF7 \fsm_reg[1]_i_3__1 
       (.I0(\fsm[1]_i_6__1_n_0 ),
        .I1(\fsm[1]_i_7__1_n_0 ),
        .O(\fsm_reg[1]_i_3__1_n_0 ),
        .S(Q[3]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  MUXF7 \fsm_reg[4]_i_1__1 
       (.I0(\fsm[4]_i_2__1_n_0 ),
        .I1(\fsm[4]_i_3__1_n_0 ),
        .O(fsm[4]),
        .S(Q[4]));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_exit_i_1__1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_exit_i_2__1_n_0),
        .I4(gen3_exit),
        .O(gen3_exit_i_1__1_n_0));
  LUT6 #(
    .INIT(64'hC000000000000001)) 
    gen3_exit_i_2__1
       (.I0(\fsm[3]_i_9__1_n_0 ),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(gen3_exit_i_2__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_exit_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_exit_i_1__1_n_0),
        .Q(gen3_exit),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_i_1__1
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_i_2__1_n_0),
        .I4(rate_gen3),
        .O(gen3_i_1__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT5 #(
    .INIT(32'h80000008)) 
    gen3_i_2__1
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[1]),
        .O(gen3_i_2__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_i_1__1_n_0),
        .Q(rate_gen3),
        .R(RST_CPLLRESET));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_6__4 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[2]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_7__1 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[2] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h06FF0600)) 
    pclk_sel_i_1__2
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(pclk_sel_i_2__1_n_0),
        .I4(USER_PCLK_SEL),
        .O(pclk_sel_i_1__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT5 #(
    .INIT(32'h80040800)) 
    pclk_sel_i_2__1
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(pclk_sel_i_2__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(pclk_sel_i_1__2_n_0),
        .Q(USER_PCLK_SEL),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    phystatus_i_1__1
       (.I0(phystatus_reg2),
        .I1(txratedone_i_2__1_n_0),
        .I2(phystatus_reg_n_0),
        .O(phystatus_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    phystatus_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_i_1__1_n_0),
        .Q(phystatus_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_PHYSTATUS),
        .Q(phystatus_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_reg1),
        .Q(phystatus_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_QPLLLOCK),
        .Q(qplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllpd_i_1__2
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(QRST_QPLLPD_IN),
        .O(qpllpd_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllpd_i_1__2_n_0),
        .Q(QRST_QPLLPD_IN),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllreset_i_1__2
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(QRST_QPLLRESET_IN),
        .O(qpllreset_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllreset_i_1__2_n_0),
        .Q(QRST_QPLLRESET_IN),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    rate_done_reg1_i_1__1
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(USER_RATE_DONE));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \rate_idle_reg1[2]_i_1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(RST_RATE_IDLE));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_in_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_in_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[0]),
        .Q(rate_in_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[1]),
        .Q(rate_in_reg2[1]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    \rate_out[0]_i_1__1 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .I2(Q[1]),
        .I3(\rate_out[2]_i_2__1_n_0 ),
        .I4(RXRATE[0]),
        .O(\rate_out[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[1]_i_1__1 
       (.I0(\rate_out[2]_i_2__1_n_0 ),
        .I1(RXRATE[1]),
        .O(\rate_out[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[2]_i_1__1 
       (.I0(\rate_out[2]_i_2__1_n_0 ),
        .I1(RXRATE[2]),
        .O(\rate_out[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h8000002080000220)) 
    \rate_out[2]_i_2__1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\rate_out[2]_i_3__1_n_0 ),
        .O(\rate_out[2]_i_2__1_n_0 ));
  LUT3 #(
    .INIT(8'h45)) 
    \rate_out[2]_i_3__1 
       (.I0(gen3_exit),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .O(\rate_out[2]_i_3__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[0]_i_1__1_n_0 ),
        .Q(RXRATE[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[1]_i_1__1_n_0 ),
        .Q(RXRATE[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[2]_i_1__1_n_0 ),
        .Q(RXRATE[2]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT5 #(
    .INIT(32'h00808000)) 
    rate_rxsync_reg1_i_1__1
       (.I0(Q[3]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(USER_RATE_RXSYNC));
  LUT5 #(
    .INIT(32'hFF008000)) 
    ratedone_i_1__1
       (.I0(rxratedone_reg_n_0),
        .I1(txratedone_reg_n_0),
        .I2(phystatus_reg_n_0),
        .I3(txratedone_i_2__1_n_0),
        .I4(ratedone_reg_n_0),
        .O(ratedone_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(ratedone_i_1__1_n_0),
        .Q(ratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RESETOVRD_DONE),
        .Q(resetovrd_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(resetovrd_done_reg1),
        .Q(resetovrd_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    resetovrd_start_reg1_i_1__1
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[4]),
        .I4(Q[2]),
        .O(USER_RESETOVRD_START));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(out1[1]),
        .Q(rst_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1),
        .Q(rxpmaresetdone_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    rxratedone_i_1__1
       (.I0(rxratedone_reg2),
        .I1(txratedone_i_2__1_n_0),
        .I2(rxratedone_reg_n_0),
        .O(rxratedone_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_i_1__1_n_0),
        .Q(rxratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RXRATEDONE),
        .Q(rxratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_reg1),
        .Q(rxratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONE),
        .Q(rxsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxsync_done_reg1),
        .Q(rxsync_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    rxsync_start_reg1_i_1__1
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(SYNC_RXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    start_reg1_i_1__1
       (.I0(p_0_in109_in),
        .I1(RST_DRP_START),
        .O(DRP_START0110_out));
  LUT6 #(
    .INIT(64'hFFFF3EFF00000200)) 
    \sysclksel[0]_i_1__1 
       (.I0(\sysclksel[0]_i_2__1_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(\sysclksel[0]_i_3__1_n_0 ),
        .I5(RXSYSCLKSEL[0]),
        .O(\sysclksel[0]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \sysclksel[0]_i_2__1 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .O(\sysclksel[0]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \sysclksel[0]_i_3__1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .O(\sysclksel[0]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'h6FFFFFFF00000000)) 
    \sysclksel[1]_i_1__1 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(RXSYSCLKSEL[1]),
        .O(\sysclksel[1]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[0]_i_1__1_n_0 ),
        .Q(RXSYSCLKSEL[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[1]_i_1__1_n_0 ),
        .Q(RXSYSCLKSEL[1]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT5 #(
    .INIT(32'h80AA00AA)) 
    \txdata_wait_cnt[0]_i_1__1 
       (.I0(\txdata_wait_cnt[3]_i_2__1_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT5 #(
    .INIT(32'hA8282828)) 
    \txdata_wait_cnt[1]_i_1__1 
       (.I0(\txdata_wait_cnt[3]_i_2__1_n_0 ),
        .I1(txdata_wait_cnt_reg__0[0]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[3]),
        .I4(txdata_wait_cnt_reg__0[2]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT5 #(
    .INIT(32'h8AA0A0A0)) 
    \txdata_wait_cnt[2]_i_1__1 
       (.I0(\txdata_wait_cnt[3]_i_2__1_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \txdata_wait_cnt[3]_i_1__1 
       (.I0(\txdata_wait_cnt[3]_i_2__1_n_0 ),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \txdata_wait_cnt[3]_i_2__1 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\txdata_wait_cnt[3]_i_2__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(txdata_wait_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(txdata_wait_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(txdata_wait_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(txdata_wait_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h5504FFFF55040000)) 
    txpmareset_i_1__1
       (.I0(Q[3]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(gen3_exit),
        .I4(txpmareset_i_2__1_n_0),
        .I5(GT_TXPMARESET0120_out),
        .O(txpmareset_i_1__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT5 #(
    .INIT(32'h82000400)) 
    txpmareset_i_2__1
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(txpmareset_i_2__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txpmareset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txpmareset_i_1__1_n_0),
        .Q(GT_TXPMARESET0120_out),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    txratedone_i_1__1
       (.I0(txratedone_reg2),
        .I1(txratedone_i_2__1_n_0),
        .I2(txratedone_reg_n_0),
        .O(txratedone_i_1__1_n_0));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    txratedone_i_2__1
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(RST_CPLLRESET),
        .O(txratedone_i_2__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_i_1__1_n_0),
        .Q(txratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXRATEDONE),
        .Q(txratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_reg1),
        .Q(txratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXSYNC_DONE),
        .Q(txsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txsync_done_reg1),
        .Q(txsync_done_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAA)) 
    txsync_start_reg1_i_1__1
       (.I0(out1[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(SYNC_TXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    x16_reg1_i_1__1
       (.I0(p_0_in111_in),
        .I1(RST_DRP_X16),
        .O(DRP_X160112_out));
  LUT2 #(
    .INIT(4'hE)) 
    x16x20_mode_reg1_i_1__1
       (.I0(p_0_in113_in),
        .I1(RST_DRP_X16X20_MODE),
        .O(DRP_X16X20_MODE0114_out));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_rate" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_44
   (Q,
    USER_RESETOVRD_START,
    RXSYSCLKSEL,
    SYNC_TXSYNC_START,
    DRP_X16X20_MODE086_out,
    DRP_X16084_out,
    DRP_START082_out,
    \cplllock_reg1_reg[3] ,
    rate_gen3,
    \cplllock_reg1_reg[3]_0 ,
    RXRATE,
    USER_RATE_DONE,
    USER_RATE_RXSYNC,
    SYNC_RXSYNC_START,
    RST_RATE_IDLE,
    GT_TXPMARESET074_out,
    USER_PCLK_SEL,
    QRST_QPLLRESET_IN,
    p_0_in75_in,
    QRST_QPLLPD_IN,
    p_0_in77_in,
    out1,
    RST_DRP_X16X20_MODE,
    RST_DRP_X16,
    RST_DRP_START,
    RST_CPLLRESET,
    pclk_sel_reg_0,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    RATE_CPLLLOCK,
    qpllpd_reg_0,
    RATE_DRP_DONE,
    \resetovrd_disble.reset_reg[4] ,
    RATE_PHYSTATUS,
    USER_TXRESETDONE,
    USER_RXRESETDONE,
    RATE_TXRATEDONE,
    RATE_RXRATEDONE,
    RATE_RESETOVRD_DONE,
    RATE_TXSYNC_DONE,
    SYNC_RXSYNC_DONE,
    p_1_in8_in,
    p_0_in7_in);
  output [4:0]Q;
  output USER_RESETOVRD_START;
  output [1:0]RXSYSCLKSEL;
  output SYNC_TXSYNC_START;
  output DRP_X16X20_MODE086_out;
  output DRP_X16084_out;
  output DRP_START082_out;
  output \cplllock_reg1_reg[3] ;
  output [0:0]rate_gen3;
  output \cplllock_reg1_reg[3]_0 ;
  output [2:0]RXRATE;
  output USER_RATE_DONE;
  output USER_RATE_RXSYNC;
  output SYNC_RXSYNC_START;
  output [0:0]RST_RATE_IDLE;
  output GT_TXPMARESET074_out;
  output USER_PCLK_SEL;
  output [0:0]QRST_QPLLRESET_IN;
  output p_0_in75_in;
  output [0:0]QRST_QPLLPD_IN;
  output p_0_in77_in;
  input [1:0]out1;
  input RST_DRP_X16X20_MODE;
  input RST_DRP_X16;
  input RST_DRP_START;
  input RST_CPLLRESET;
  input pclk_sel_reg_0;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input RATE_CPLLLOCK;
  input qpllpd_reg_0;
  input RATE_DRP_DONE;
  input \resetovrd_disble.reset_reg[4] ;
  input RATE_PHYSTATUS;
  input USER_TXRESETDONE;
  input USER_RXRESETDONE;
  input RATE_TXRATEDONE;
  input RATE_RXRATEDONE;
  input RATE_RESETOVRD_DONE;
  input RATE_TXSYNC_DONE;
  input SYNC_RXSYNC_DONE;
  input p_1_in8_in;
  input p_0_in7_in;

  wire DRP_START082_out;
  wire DRP_X16084_out;
  wire DRP_X16X20_MODE086_out;
  wire GT_TXPMARESET074_out;
  wire [4:0]Q;
  wire [0:0]QRST_QPLLPD_IN;
  wire [0:0]QRST_QPLLRESET_IN;
  wire RATE_CPLLLOCK;
  wire RATE_DRP_DONE;
  wire RATE_PHYSTATUS;
  wire RATE_RESETOVRD_DONE;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RATE_TXSYNC_DONE;
  wire RST_CPLLRESET;
  wire RST_DRP_START;
  wire RST_DRP_X16;
  wire RST_DRP_X16X20_MODE;
  wire [0:0]RST_RATE_IDLE;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXSYNC_START;
  wire USER_PCLK_SEL;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire cplllock_reg1;
  wire \cplllock_reg1_reg[3] ;
  wire \cplllock_reg1_reg[3]_0 ;
  wire cplllock_reg2;
  wire cpllpd_i_1__2_n_0;
  wire cpllreset_i_1__3_n_0;
  wire drp_done_reg1;
  wire drp_done_reg2;
  wire drp_start_i_1__2_n_0;
  wire drp_x16_i_1__2_n_0;
  wire drp_x16x20_mode_i_1__2_n_0;
  wire [4:0]fsm;
  wire fsm1;
  wire \fsm[0]_i_10__2_n_0 ;
  wire \fsm[0]_i_11__2_n_0 ;
  wire \fsm[0]_i_12__2_n_0 ;
  wire \fsm[0]_i_3__5_n_0 ;
  wire \fsm[0]_i_4__2_n_0 ;
  wire \fsm[0]_i_5__2_n_0 ;
  wire \fsm[0]_i_6__2_n_0 ;
  wire \fsm[0]_i_7__2_n_0 ;
  wire \fsm[0]_i_8__2_n_0 ;
  wire \fsm[0]_i_9__2_n_0 ;
  wire \fsm[1]_i_4__2_n_0 ;
  wire \fsm[1]_i_5__2_n_0 ;
  wire \fsm[1]_i_6__2_n_0 ;
  wire \fsm[1]_i_7__2_n_0 ;
  wire \fsm[1]_i_8__2_n_0 ;
  wire \fsm[1]_i_9__2_n_0 ;
  wire \fsm[2]_i_2__2_n_0 ;
  wire \fsm[2]_i_3__2_n_0 ;
  wire \fsm[2]_i_4__2_n_0 ;
  wire \fsm[2]_i_5__2_n_0 ;
  wire \fsm[3]_i_2__2_n_0 ;
  wire \fsm[3]_i_3__2_n_0 ;
  wire \fsm[3]_i_4__2_n_0 ;
  wire \fsm[3]_i_5__2_n_0 ;
  wire \fsm[3]_i_8__2_n_0 ;
  wire \fsm[3]_i_9__2_n_0 ;
  wire \fsm[4]_i_2__2_n_0 ;
  wire \fsm[4]_i_3__2_n_0 ;
  wire \fsm_reg[0]_i_2__2_n_0 ;
  wire \fsm_reg[1]_i_2__2_n_0 ;
  wire \fsm_reg[1]_i_3__2_n_0 ;
  wire gen3_exit;
  wire gen3_exit_i_1__2_n_0;
  wire gen3_exit_i_2__2_n_0;
  wire gen3_i_1__2_n_0;
  wire gen3_i_2__2_n_0;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire [1:0]out1;
  wire p_0_in75_in;
  wire p_0_in77_in;
  wire p_0_in7_in;
  wire p_0_in81_in;
  wire p_0_in83_in;
  wire p_0_in85_in;
  wire [3:0]p_0_in__0;
  wire p_1_in8_in;
  wire pclk_sel_i_1__3_n_0;
  wire pclk_sel_i_2__2_n_0;
  wire pclk_sel_reg_0;
  wire phystatus_i_1__2_n_0;
  wire phystatus_reg1;
  wire phystatus_reg2;
  wire phystatus_reg_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire pll_lock;
  wire qplllock_reg1;
  wire qplllock_reg2;
  wire qpllpd;
  wire qpllpd_i_1__3_n_0;
  wire qpllpd_reg_0;
  wire qpllreset;
  wire qpllreset_i_1__3_n_0;
  wire [0:0]rate_gen3;
  wire [1:0]rate_in_reg1;
  wire [1:0]rate_in_reg2;
  wire \rate_out[0]_i_1__2_n_0 ;
  wire \rate_out[1]_i_1__2_n_0 ;
  wire \rate_out[2]_i_1__2_n_0 ;
  wire \rate_out[2]_i_2__2_n_0 ;
  wire \rate_out[2]_i_3__2_n_0 ;
  wire ratedone_i_1__2_n_0;
  wire ratedone_reg_n_0;
  wire \resetovrd_disble.reset_reg[4] ;
  wire resetovrd_done_reg1;
  wire resetovrd_done_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire rxpmaresetdone_reg1;
  wire rxpmaresetdone_reg2;
  wire rxratedone_i_1__2_n_0;
  wire rxratedone_reg1;
  wire rxratedone_reg2;
  wire rxratedone_reg_n_0;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxsync_done_reg1;
  wire rxsync_done_reg2;
  wire \sysclksel[0]_i_1__2_n_0 ;
  wire \sysclksel[0]_i_2__2_n_0 ;
  wire \sysclksel[0]_i_3__2_n_0 ;
  wire \sysclksel[1]_i_1__2_n_0 ;
  wire \txdata_wait_cnt[3]_i_2__2_n_0 ;
  wire [3:0]txdata_wait_cnt_reg__0;
  wire txpmareset_i_1__2_n_0;
  wire txpmareset_i_2__2_n_0;
  wire txratedone_i_1__2_n_0;
  wire txratedone_i_2__2_n_0;
  wire txratedone_reg1;
  wire txratedone_reg2;
  wire txratedone_reg_n_0;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire txsync_done_reg1;
  wire txsync_done_reg2;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_CPLLLOCK),
        .Q(cplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cplllock_reg1),
        .Q(cplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllpd_i_1__2
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(p_0_in77_in),
        .O(cpllpd_i_1__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT5 #(
    .INIT(32'h80000084)) 
    cpllpd_i_2__2
       (.I0(Q[4]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(qpllpd));
  FDRE #(
    .INIT(1'b0)) 
    cpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllpd_i_1__2_n_0),
        .Q(p_0_in77_in),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllreset_i_1__3
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(p_0_in75_in),
        .O(cpllreset_i_1__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT5 #(
    .INIT(32'h81000002)) 
    cpllreset_i_2__2
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(qpllreset));
  FDRE #(
    .INIT(1'b0)) 
    cpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllreset_i_1__3_n_0),
        .Q(p_0_in75_in),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_DRP_DONE),
        .Q(drp_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT5 #(
    .INIT(32'h08200108)) 
    drp_start_i_1__2
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(Q[1]),
        .O(drp_start_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_start_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_start_i_1__2_n_0),
        .Q(p_0_in81_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT5 #(
    .INIT(32'h20020006)) 
    drp_x16_i_1__2
       (.I0(Q[2]),
        .I1(Q[4]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[0]),
        .O(drp_x16_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16_i_1__2_n_0),
        .Q(p_0_in83_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT5 #(
    .INIT(32'h20001584)) 
    drp_x16x20_mode_i_1__2
       (.I0(Q[1]),
        .I1(Q[4]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(drp_x16x20_mode_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16x20_mode_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16x20_mode_i_1__2_n_0),
        .Q(p_0_in85_in),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[0]_i_10__2 
       (.I0(txdata_wait_cnt_reg__0[3]),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[0]),
        .I3(txdata_wait_cnt_reg__0[1]),
        .O(\fsm[0]_i_10__2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000F404)) 
    \fsm[0]_i_11__2 
       (.I0(rxpmaresetdone_reg2),
        .I1(mmcm_lock_reg2),
        .I2(Q[0]),
        .I3(drp_done_reg2),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\fsm[0]_i_11__2_n_0 ));
  LUT6 #(
    .INIT(64'h4F4F737F4343404C)) 
    \fsm[0]_i_12__2 
       (.I0(resetovrd_done_reg2),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(rxpmaresetdone_reg2),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[0]_i_12__2_n_0 ));
  LUT6 #(
    .INIT(64'hBBB88888BBB8BBB8)) 
    \fsm[0]_i_1__5 
       (.I0(\fsm_reg[0]_i_2__2_n_0 ),
        .I1(Q[4]),
        .I2(\fsm[0]_i_3__5_n_0 ),
        .I3(Q[3]),
        .I4(\fsm[0]_i_4__2_n_0 ),
        .I5(\fsm[0]_i_5__2_n_0 ),
        .O(fsm[0]));
  LUT6 #(
    .INIT(64'h0344FF440344FF77)) 
    \fsm[0]_i_3__5 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(pll_lock),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\fsm[3]_i_9__2_n_0 ),
        .O(\fsm[0]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hF0000000F800F000)) 
    \fsm[0]_i_4__2 
       (.I0(pll_lock),
        .I1(rst_idle_reg2),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(drp_done_reg2),
        .I5(Q[0]),
        .O(\fsm[0]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000CCC8C0C8)) 
    \fsm[0]_i_5__2 
       (.I0(\fsm[0]_i_8__2_n_0 ),
        .I1(Q[3]),
        .I2(\fsm[0]_i_9__2_n_0 ),
        .I3(Q[0]),
        .I4(\fsm[0]_i_10__2_n_0 ),
        .I5(\fsm[0]_i_11__2_n_0 ),
        .O(\fsm[0]_i_5__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0040)) 
    \fsm[0]_i_6__2 
       (.I0(fsm1),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(\fsm[0]_i_12__2_n_0 ),
        .O(\fsm[0]_i_6__2_n_0 ));
  LUT5 #(
    .INIT(32'h03880333)) 
    \fsm[0]_i_7__2 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[0]_i_7__2_n_0 ));
  LUT5 #(
    .INIT(32'h77770777)) 
    \fsm[0]_i_8__2 
       (.I0(p_0_in7_in),
        .I1(p_1_in8_in),
        .I2(rxresetdone_reg2),
        .I3(txresetdone_reg2),
        .I4(phystatus_reg2),
        .O(\fsm[0]_i_8__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \fsm[0]_i_9__2 
       (.I0(Q[1]),
        .I1(Q[2]),
        .O(\fsm[0]_i_9__2_n_0 ));
  LUT5 #(
    .INIT(32'h30BBFC00)) 
    \fsm[1]_i_4__2 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(\fsm[1]_i_8__2_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'hCC88300000BB3000)) 
    \fsm[1]_i_5__2 
       (.I0(\fsm[0]_i_10__2_n_0 ),
        .I1(Q[2]),
        .I2(\fsm[1]_i_9__2_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_5__2_n_0 ));
  LUT5 #(
    .INIT(32'h70F040F0)) 
    \fsm[1]_i_6__2 
       (.I0(resetovrd_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(drp_done_reg2),
        .O(\fsm[1]_i_6__2_n_0 ));
  LUT5 #(
    .INIT(32'h03777700)) 
    \fsm[1]_i_7__2 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_7__2_n_0 ));
  LUT6 #(
    .INIT(64'h53F5FFFFFFFFFFFF)) 
    \fsm[1]_i_8__2 
       (.I0(cplllock_reg2),
        .I1(qplllock_reg2),
        .I2(rate_in_reg2[0]),
        .I3(rate_in_reg2[1]),
        .I4(rst_idle_reg2),
        .I5(Q[0]),
        .O(\fsm[1]_i_8__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF4575FFFFFFFF)) 
    \fsm[1]_i_9__2 
       (.I0(cplllock_reg2),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .I3(qplllock_reg2),
        .I4(rst_idle_reg2),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_9__2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fsm[2]_i_1__5 
       (.I0(\fsm[2]_i_2__2_n_0 ),
        .I1(\fsm[2]_i_3__2_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[2]_i_4__2_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[2]_i_5__2_n_0 ),
        .O(fsm[2]));
  LUT5 #(
    .INIT(32'h3C0C4040)) 
    \fsm[2]_i_2__2 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_done_reg2),
        .I4(Q[0]),
        .O(\fsm[2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h13CCD3CC1FCCDFCC)) 
    \fsm[2]_i_3__2 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(resetovrd_done_reg2),
        .I5(fsm1),
        .O(\fsm[2]_i_3__2_n_0 ));
  LUT4 #(
    .INIT(16'hBC0C)) 
    \fsm[2]_i_4__2 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\fsm[2]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'h4A4A4A4AAAAFAAAA)) 
    \fsm[2]_i_5__2 
       (.I0(Q[2]),
        .I1(pll_lock),
        .I2(Q[1]),
        .I3(\fsm[3]_i_9__2_n_0 ),
        .I4(\fsm[3]_i_8__2_n_0 ),
        .I5(Q[0]),
        .O(\fsm[2]_i_5__2_n_0 ));
  LUT6 #(
    .INIT(64'hEFE0EFEFEFE0E0E0)) 
    \fsm[3]_i_1__2 
       (.I0(\fsm[3]_i_2__2_n_0 ),
        .I1(\fsm[3]_i_3__2_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[3]_i_4__2_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[3]_i_5__2_n_0 ),
        .O(fsm[3]));
  LUT5 #(
    .INIT(32'h22AA2A22)) 
    \fsm[3]_i_2__2 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(rxsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[3]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h3020002000000000)) 
    \fsm[3]_i_3__2 
       (.I0(fsm1),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(resetovrd_done_reg2),
        .I5(Q[0]),
        .O(\fsm[3]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hF545F555FFFFFFFF)) 
    \fsm[3]_i_4__2 
       (.I0(Q[2]),
        .I1(rst_idle_reg2),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(pll_lock),
        .I5(Q[1]),
        .O(\fsm[3]_i_4__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT5 #(
    .INIT(32'h80808180)) 
    \fsm[3]_i_5__2 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\fsm[3]_i_8__2_n_0 ),
        .I4(\fsm[3]_i_9__2_n_0 ),
        .O(\fsm[3]_i_5__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8F8FFF8)) 
    \fsm[3]_i_6__2 
       (.I0(p_1_in8_in),
        .I1(p_0_in7_in),
        .I2(ratedone_reg_n_0),
        .I3(rate_in_reg2[1]),
        .I4(rate_in_reg2[0]),
        .I5(gen3_exit),
        .O(fsm1));
  LUT4 #(
    .INIT(16'hFB08)) 
    \fsm[3]_i_7__2 
       (.I0(qplllock_reg2),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(cplllock_reg2),
        .O(pll_lock));
  LUT4 #(
    .INIT(16'hB0BB)) 
    \fsm[3]_i_8__2 
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg1[0]),
        .I3(rate_in_reg1[1]),
        .O(\fsm[3]_i_8__2_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \fsm[3]_i_9__2 
       (.I0(rate_in_reg1[0]),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg1[1]),
        .I3(rate_in_reg2[1]),
        .O(\fsm[3]_i_9__2_n_0 ));
  LUT5 #(
    .INIT(32'h08880000)) 
    \fsm[4]_i_2__2 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\fsm[4]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'h5F75FFFF)) 
    \fsm[4]_i_3__2 
       (.I0(Q[2]),
        .I1(rxsync_done_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\fsm[4]_i_3__2_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  MUXF7 \fsm_reg[0]_i_2__2 
       (.I0(\fsm[0]_i_6__2_n_0 ),
        .I1(\fsm[0]_i_7__2_n_0 ),
        .O(\fsm_reg[0]_i_2__2_n_0 ),
        .S(Q[3]));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .S(RST_CPLLRESET));
  MUXF8 \fsm_reg[1]_i_1__2 
       (.I0(\fsm_reg[1]_i_2__2_n_0 ),
        .I1(\fsm_reg[1]_i_3__2_n_0 ),
        .O(fsm[1]),
        .S(Q[4]));
  MUXF7 \fsm_reg[1]_i_2__2 
       (.I0(\fsm[1]_i_4__2_n_0 ),
        .I1(\fsm[1]_i_5__2_n_0 ),
        .O(\fsm_reg[1]_i_2__2_n_0 ),
        .S(Q[3]));
  MUXF7 \fsm_reg[1]_i_3__2 
       (.I0(\fsm[1]_i_6__2_n_0 ),
        .I1(\fsm[1]_i_7__2_n_0 ),
        .O(\fsm_reg[1]_i_3__2_n_0 ),
        .S(Q[3]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  MUXF7 \fsm_reg[4]_i_1__2 
       (.I0(\fsm[4]_i_2__2_n_0 ),
        .I1(\fsm[4]_i_3__2_n_0 ),
        .O(fsm[4]),
        .S(Q[4]));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_exit_i_1__2
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_exit_i_2__2_n_0),
        .I4(gen3_exit),
        .O(gen3_exit_i_1__2_n_0));
  LUT6 #(
    .INIT(64'hC000000000000001)) 
    gen3_exit_i_2__2
       (.I0(\fsm[3]_i_9__2_n_0 ),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(gen3_exit_i_2__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_exit_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_exit_i_1__2_n_0),
        .Q(gen3_exit),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_i_1__2
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_i_2__2_n_0),
        .I4(rate_gen3),
        .O(gen3_i_1__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT5 #(
    .INIT(32'h80000008)) 
    gen3_i_2__2
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[1]),
        .O(gen3_i_2__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_i_1__2_n_0),
        .Q(rate_gen3),
        .R(RST_CPLLRESET));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_6__3 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_7__2 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[3] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h06FF0600)) 
    pclk_sel_i_1__3
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(pclk_sel_i_2__2_n_0),
        .I4(USER_PCLK_SEL),
        .O(pclk_sel_i_1__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT5 #(
    .INIT(32'h80040800)) 
    pclk_sel_i_2__2
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(pclk_sel_i_2__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(pclk_sel_i_1__3_n_0),
        .Q(USER_PCLK_SEL),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    phystatus_i_1__2
       (.I0(phystatus_reg2),
        .I1(txratedone_i_2__2_n_0),
        .I2(phystatus_reg_n_0),
        .O(phystatus_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    phystatus_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_i_1__2_n_0),
        .Q(phystatus_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_PHYSTATUS),
        .Q(phystatus_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_reg1),
        .Q(phystatus_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllpd_reg_0),
        .Q(qplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllpd_i_1__3
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(QRST_QPLLPD_IN),
        .O(qpllpd_i_1__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllpd_i_1__3_n_0),
        .Q(QRST_QPLLPD_IN),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllreset_i_1__3
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(QRST_QPLLRESET_IN),
        .O(qpllreset_i_1__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllreset_i_1__3_n_0),
        .Q(QRST_QPLLRESET_IN),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    rate_done_reg1_i_1__2
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(USER_RATE_DONE));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \rate_idle_reg1[3]_i_1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(RST_RATE_IDLE));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_in_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_in_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[0]),
        .Q(rate_in_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[1]),
        .Q(rate_in_reg2[1]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    \rate_out[0]_i_1__2 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .I2(Q[1]),
        .I3(\rate_out[2]_i_2__2_n_0 ),
        .I4(RXRATE[0]),
        .O(\rate_out[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[1]_i_1__2 
       (.I0(\rate_out[2]_i_2__2_n_0 ),
        .I1(RXRATE[1]),
        .O(\rate_out[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[2]_i_1__2 
       (.I0(\rate_out[2]_i_2__2_n_0 ),
        .I1(RXRATE[2]),
        .O(\rate_out[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h8000002080000220)) 
    \rate_out[2]_i_2__2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\rate_out[2]_i_3__2_n_0 ),
        .O(\rate_out[2]_i_2__2_n_0 ));
  LUT3 #(
    .INIT(8'h45)) 
    \rate_out[2]_i_3__2 
       (.I0(gen3_exit),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .O(\rate_out[2]_i_3__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[0]_i_1__2_n_0 ),
        .Q(RXRATE[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[1]_i_1__2_n_0 ),
        .Q(RXRATE[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[2]_i_1__2_n_0 ),
        .Q(RXRATE[2]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT5 #(
    .INIT(32'h00808000)) 
    rate_rxsync_reg1_i_1__2
       (.I0(Q[3]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(USER_RATE_RXSYNC));
  LUT5 #(
    .INIT(32'hFF008000)) 
    ratedone_i_1__2
       (.I0(rxratedone_reg_n_0),
        .I1(txratedone_reg_n_0),
        .I2(phystatus_reg_n_0),
        .I3(txratedone_i_2__2_n_0),
        .I4(ratedone_reg_n_0),
        .O(ratedone_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(ratedone_i_1__2_n_0),
        .Q(ratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RESETOVRD_DONE),
        .Q(resetovrd_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(resetovrd_done_reg1),
        .Q(resetovrd_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    resetovrd_start_reg1_i_1__2
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[4]),
        .I4(Q[2]),
        .O(USER_RESETOVRD_START));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(out1[1]),
        .Q(rst_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1),
        .Q(rxpmaresetdone_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    rxratedone_i_1__2
       (.I0(rxratedone_reg2),
        .I1(txratedone_i_2__2_n_0),
        .I2(rxratedone_reg_n_0),
        .O(rxratedone_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_i_1__2_n_0),
        .Q(rxratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RXRATEDONE),
        .Q(rxratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_reg1),
        .Q(rxratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONE),
        .Q(rxsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxsync_done_reg1),
        .Q(rxsync_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    rxsync_start_reg1_i_1__2
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(SYNC_RXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    start_reg1_i_1__2
       (.I0(p_0_in81_in),
        .I1(RST_DRP_START),
        .O(DRP_START082_out));
  LUT6 #(
    .INIT(64'hFFFF3EFF00000200)) 
    \sysclksel[0]_i_1__2 
       (.I0(\sysclksel[0]_i_2__2_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(\sysclksel[0]_i_3__2_n_0 ),
        .I5(RXSYSCLKSEL[0]),
        .O(\sysclksel[0]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \sysclksel[0]_i_2__2 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .O(\sysclksel[0]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \sysclksel[0]_i_3__2 
       (.I0(Q[2]),
        .I1(Q[1]),
        .O(\sysclksel[0]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'h6FFFFFFF00000000)) 
    \sysclksel[1]_i_1__2 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(RXSYSCLKSEL[1]),
        .O(\sysclksel[1]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[0]_i_1__2_n_0 ),
        .Q(RXSYSCLKSEL[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[1]_i_1__2_n_0 ),
        .Q(RXSYSCLKSEL[1]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT5 #(
    .INIT(32'h80AA00AA)) 
    \txdata_wait_cnt[0]_i_1__2 
       (.I0(\txdata_wait_cnt[3]_i_2__2_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT5 #(
    .INIT(32'hA8282828)) 
    \txdata_wait_cnt[1]_i_1__2 
       (.I0(\txdata_wait_cnt[3]_i_2__2_n_0 ),
        .I1(txdata_wait_cnt_reg__0[0]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[3]),
        .I4(txdata_wait_cnt_reg__0[2]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT5 #(
    .INIT(32'h8AA0A0A0)) 
    \txdata_wait_cnt[2]_i_1__2 
       (.I0(\txdata_wait_cnt[3]_i_2__2_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \txdata_wait_cnt[3]_i_1__2 
       (.I0(\txdata_wait_cnt[3]_i_2__2_n_0 ),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \txdata_wait_cnt[3]_i_2__2 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\txdata_wait_cnt[3]_i_2__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(txdata_wait_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(txdata_wait_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(txdata_wait_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(txdata_wait_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h5504FFFF55040000)) 
    txpmareset_i_1__2
       (.I0(Q[3]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(gen3_exit),
        .I4(txpmareset_i_2__2_n_0),
        .I5(GT_TXPMARESET074_out),
        .O(txpmareset_i_1__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT5 #(
    .INIT(32'h82000400)) 
    txpmareset_i_2__2
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(txpmareset_i_2__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txpmareset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txpmareset_i_1__2_n_0),
        .Q(GT_TXPMARESET074_out),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    txratedone_i_1__2
       (.I0(txratedone_reg2),
        .I1(txratedone_i_2__2_n_0),
        .I2(txratedone_reg_n_0),
        .O(txratedone_i_1__2_n_0));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    txratedone_i_2__2
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(RST_CPLLRESET),
        .O(txratedone_i_2__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_i_1__2_n_0),
        .Q(txratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXRATEDONE),
        .Q(txratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_reg1),
        .Q(txratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXSYNC_DONE),
        .Q(txsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txsync_done_reg1),
        .Q(txsync_done_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAA)) 
    txsync_start_reg1_i_1__2
       (.I0(out1[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(SYNC_TXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    x16_reg1_i_1__2
       (.I0(p_0_in83_in),
        .I1(RST_DRP_X16),
        .O(DRP_X16084_out));
  LUT2 #(
    .INIT(4'hE)) 
    x16x20_mode_reg1_i_1__2
       (.I0(p_0_in85_in),
        .I1(RST_DRP_X16X20_MODE),
        .O(DRP_X16X20_MODE086_out));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_rate" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_51
   (Q,
    USER_RESETOVRD_START,
    RXSYSCLKSEL,
    SYNC_TXSYNC_START,
    DRP_X16X20_MODE0134_out,
    DRP_X160132_out,
    DRP_START0130_out,
    \cplllock_reg1_reg[4] ,
    rate_gen3,
    \cplllock_reg1_reg[4]_0 ,
    RXRATE,
    USER_RATE_DONE,
    USER_RATE_RXSYNC,
    SYNC_RXSYNC_START,
    RST_RATE_IDLE,
    GT_TXPMARESET064_out,
    USER_PCLK_SEL,
    QRST_QPLLRESET_IN,
    p_0_in65_in,
    QRST_QPLLPD_IN,
    p_0_in67_in,
    out1,
    RST_DRP_X16X20_MODE,
    RST_DRP_X16,
    RST_DRP_START,
    RST_CPLLRESET,
    pclk_sel_reg_0,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    RATE_CPLLLOCK,
    RATE_QPLLLOCK,
    RATE_DRP_DONE,
    \resetovrd_disble.reset_reg[4] ,
    RATE_PHYSTATUS,
    USER_TXRESETDONE,
    USER_RXRESETDONE,
    RATE_TXRATEDONE,
    RATE_RXRATEDONE,
    RATE_RESETOVRD_DONE,
    RATE_TXSYNC_DONE,
    SYNC_RXSYNC_DONE,
    p_1_in8_in,
    p_0_in7_in);
  output [4:0]Q;
  output USER_RESETOVRD_START;
  output [1:0]RXSYSCLKSEL;
  output SYNC_TXSYNC_START;
  output DRP_X16X20_MODE0134_out;
  output DRP_X160132_out;
  output DRP_START0130_out;
  output \cplllock_reg1_reg[4] ;
  output [0:0]rate_gen3;
  output \cplllock_reg1_reg[4]_0 ;
  output [2:0]RXRATE;
  output USER_RATE_DONE;
  output USER_RATE_RXSYNC;
  output SYNC_RXSYNC_START;
  output [0:0]RST_RATE_IDLE;
  output GT_TXPMARESET064_out;
  output USER_PCLK_SEL;
  output [0:0]QRST_QPLLRESET_IN;
  output p_0_in65_in;
  output [0:0]QRST_QPLLPD_IN;
  output p_0_in67_in;
  input [1:0]out1;
  input RST_DRP_X16X20_MODE;
  input RST_DRP_X16;
  input RST_DRP_START;
  input RST_CPLLRESET;
  input pclk_sel_reg_0;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input RATE_CPLLLOCK;
  input RATE_QPLLLOCK;
  input RATE_DRP_DONE;
  input \resetovrd_disble.reset_reg[4] ;
  input RATE_PHYSTATUS;
  input USER_TXRESETDONE;
  input USER_RXRESETDONE;
  input RATE_TXRATEDONE;
  input RATE_RXRATEDONE;
  input RATE_RESETOVRD_DONE;
  input RATE_TXSYNC_DONE;
  input SYNC_RXSYNC_DONE;
  input p_1_in8_in;
  input p_0_in7_in;

  wire DRP_START0130_out;
  wire DRP_X160132_out;
  wire DRP_X16X20_MODE0134_out;
  wire GT_TXPMARESET064_out;
  wire [4:0]Q;
  wire [0:0]QRST_QPLLPD_IN;
  wire [0:0]QRST_QPLLRESET_IN;
  wire RATE_CPLLLOCK;
  wire RATE_DRP_DONE;
  wire RATE_PHYSTATUS;
  wire RATE_QPLLLOCK;
  wire RATE_RESETOVRD_DONE;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RATE_TXSYNC_DONE;
  wire RST_CPLLRESET;
  wire RST_DRP_START;
  wire RST_DRP_X16;
  wire RST_DRP_X16X20_MODE;
  wire [0:0]RST_RATE_IDLE;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXSYNC_START;
  wire USER_PCLK_SEL;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire cplllock_reg1;
  wire \cplllock_reg1_reg[4] ;
  wire \cplllock_reg1_reg[4]_0 ;
  wire cplllock_reg2;
  wire cpllpd_i_1__3_n_0;
  wire cpllreset_i_1__4_n_0;
  wire drp_done_reg1;
  wire drp_done_reg2;
  wire drp_start_i_1__3_n_0;
  wire drp_x16_i_1__3_n_0;
  wire drp_x16x20_mode_i_1__3_n_0;
  wire [4:0]fsm;
  wire fsm1;
  wire \fsm[0]_i_10__3_n_0 ;
  wire \fsm[0]_i_11__3_n_0 ;
  wire \fsm[0]_i_12__3_n_0 ;
  wire \fsm[0]_i_3__7_n_0 ;
  wire \fsm[0]_i_4__3_n_0 ;
  wire \fsm[0]_i_5__3_n_0 ;
  wire \fsm[0]_i_6__3_n_0 ;
  wire \fsm[0]_i_7__3_n_0 ;
  wire \fsm[0]_i_8__3_n_0 ;
  wire \fsm[0]_i_9__3_n_0 ;
  wire \fsm[1]_i_4__3_n_0 ;
  wire \fsm[1]_i_5__3_n_0 ;
  wire \fsm[1]_i_6__3_n_0 ;
  wire \fsm[1]_i_7__3_n_0 ;
  wire \fsm[1]_i_8__3_n_0 ;
  wire \fsm[1]_i_9__3_n_0 ;
  wire \fsm[2]_i_2__3_n_0 ;
  wire \fsm[2]_i_3__3_n_0 ;
  wire \fsm[2]_i_4__3_n_0 ;
  wire \fsm[2]_i_5__3_n_0 ;
  wire \fsm[3]_i_2__3_n_0 ;
  wire \fsm[3]_i_3__3_n_0 ;
  wire \fsm[3]_i_4__3_n_0 ;
  wire \fsm[3]_i_5__3_n_0 ;
  wire \fsm[3]_i_8__3_n_0 ;
  wire \fsm[3]_i_9__3_n_0 ;
  wire \fsm[4]_i_2__3_n_0 ;
  wire \fsm[4]_i_3__3_n_0 ;
  wire \fsm_reg[0]_i_2__3_n_0 ;
  wire \fsm_reg[1]_i_2__3_n_0 ;
  wire \fsm_reg[1]_i_3__3_n_0 ;
  wire gen3_exit;
  wire gen3_exit_i_1__3_n_0;
  wire gen3_exit_i_2__3_n_0;
  wire gen3_i_1__3_n_0;
  wire gen3_i_2__3_n_0;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire [1:0]out1;
  wire p_0_in129_in;
  wire p_0_in131_in;
  wire p_0_in133_in;
  wire p_0_in65_in;
  wire p_0_in67_in;
  wire p_0_in7_in;
  wire [3:0]p_0_in__0;
  wire p_1_in8_in;
  wire pclk_sel_i_1__4_n_0;
  wire pclk_sel_i_2__3_n_0;
  wire pclk_sel_reg_0;
  wire phystatus_i_1__3_n_0;
  wire phystatus_reg1;
  wire phystatus_reg2;
  wire phystatus_reg_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire pll_lock;
  wire qplllock_reg1;
  wire qplllock_reg2;
  wire qpllpd;
  wire qpllpd_i_1__4_n_0;
  wire qpllreset;
  wire qpllreset_i_1__4_n_0;
  wire [0:0]rate_gen3;
  wire [1:0]rate_in_reg1;
  wire [1:0]rate_in_reg2;
  wire \rate_out[0]_i_1__3_n_0 ;
  wire \rate_out[1]_i_1__3_n_0 ;
  wire \rate_out[2]_i_1__3_n_0 ;
  wire \rate_out[2]_i_2__3_n_0 ;
  wire \rate_out[2]_i_3__3_n_0 ;
  wire ratedone_i_1__3_n_0;
  wire ratedone_reg_n_0;
  wire \resetovrd_disble.reset_reg[4] ;
  wire resetovrd_done_reg1;
  wire resetovrd_done_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire rxpmaresetdone_reg1;
  wire rxpmaresetdone_reg2;
  wire rxratedone_i_1__3_n_0;
  wire rxratedone_reg1;
  wire rxratedone_reg2;
  wire rxratedone_reg_n_0;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxsync_done_reg1;
  wire rxsync_done_reg2;
  wire \sysclksel[0]_i_1__3_n_0 ;
  wire \sysclksel[0]_i_2__3_n_0 ;
  wire \sysclksel[0]_i_3__3_n_0 ;
  wire \sysclksel[1]_i_1__3_n_0 ;
  wire \txdata_wait_cnt[3]_i_2__3_n_0 ;
  wire [3:0]txdata_wait_cnt_reg__0;
  wire txpmareset_i_1__3_n_0;
  wire txpmareset_i_2__3_n_0;
  wire txratedone_i_1__3_n_0;
  wire txratedone_i_2__3_n_0;
  wire txratedone_reg1;
  wire txratedone_reg2;
  wire txratedone_reg_n_0;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire txsync_done_reg1;
  wire txsync_done_reg2;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_CPLLLOCK),
        .Q(cplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cplllock_reg1),
        .Q(cplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllpd_i_1__3
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(p_0_in67_in),
        .O(cpllpd_i_1__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT5 #(
    .INIT(32'h80000084)) 
    cpllpd_i_2__3
       (.I0(Q[4]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(qpllpd));
  FDRE #(
    .INIT(1'b0)) 
    cpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllpd_i_1__3_n_0),
        .Q(p_0_in67_in),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllreset_i_1__4
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(p_0_in65_in),
        .O(cpllreset_i_1__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT5 #(
    .INIT(32'h81000002)) 
    cpllreset_i_2__3
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(qpllreset));
  FDRE #(
    .INIT(1'b0)) 
    cpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllreset_i_1__4_n_0),
        .Q(p_0_in65_in),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_DRP_DONE),
        .Q(drp_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT5 #(
    .INIT(32'h08200108)) 
    drp_start_i_1__3
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(Q[1]),
        .O(drp_start_i_1__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_start_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_start_i_1__3_n_0),
        .Q(p_0_in129_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT5 #(
    .INIT(32'h20020006)) 
    drp_x16_i_1__3
       (.I0(Q[2]),
        .I1(Q[4]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[0]),
        .O(drp_x16_i_1__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16_i_1__3_n_0),
        .Q(p_0_in131_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT5 #(
    .INIT(32'h20001584)) 
    drp_x16x20_mode_i_1__3
       (.I0(Q[1]),
        .I1(Q[4]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(drp_x16x20_mode_i_1__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16x20_mode_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16x20_mode_i_1__3_n_0),
        .Q(p_0_in133_in),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[0]_i_10__3 
       (.I0(txdata_wait_cnt_reg__0[3]),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[0]),
        .I3(txdata_wait_cnt_reg__0[1]),
        .O(\fsm[0]_i_10__3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000F404)) 
    \fsm[0]_i_11__3 
       (.I0(rxpmaresetdone_reg2),
        .I1(mmcm_lock_reg2),
        .I2(Q[0]),
        .I3(drp_done_reg2),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\fsm[0]_i_11__3_n_0 ));
  LUT6 #(
    .INIT(64'h4F4F737F4343404C)) 
    \fsm[0]_i_12__3 
       (.I0(resetovrd_done_reg2),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(rxpmaresetdone_reg2),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[0]_i_12__3_n_0 ));
  LUT6 #(
    .INIT(64'hBBB88888BBB8BBB8)) 
    \fsm[0]_i_1__7 
       (.I0(\fsm_reg[0]_i_2__3_n_0 ),
        .I1(Q[4]),
        .I2(\fsm[0]_i_3__7_n_0 ),
        .I3(Q[3]),
        .I4(\fsm[0]_i_4__3_n_0 ),
        .I5(\fsm[0]_i_5__3_n_0 ),
        .O(fsm[0]));
  LUT6 #(
    .INIT(64'h0344FF440344FF77)) 
    \fsm[0]_i_3__7 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(pll_lock),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\fsm[3]_i_9__3_n_0 ),
        .O(\fsm[0]_i_3__7_n_0 ));
  LUT6 #(
    .INIT(64'hF0000000F800F000)) 
    \fsm[0]_i_4__3 
       (.I0(pll_lock),
        .I1(rst_idle_reg2),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(drp_done_reg2),
        .I5(Q[0]),
        .O(\fsm[0]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000CCC8C0C8)) 
    \fsm[0]_i_5__3 
       (.I0(\fsm[0]_i_8__3_n_0 ),
        .I1(Q[3]),
        .I2(\fsm[0]_i_9__3_n_0 ),
        .I3(Q[0]),
        .I4(\fsm[0]_i_10__3_n_0 ),
        .I5(\fsm[0]_i_11__3_n_0 ),
        .O(\fsm[0]_i_5__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0040)) 
    \fsm[0]_i_6__3 
       (.I0(fsm1),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(\fsm[0]_i_12__3_n_0 ),
        .O(\fsm[0]_i_6__3_n_0 ));
  LUT5 #(
    .INIT(32'h03880333)) 
    \fsm[0]_i_7__3 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[0]_i_7__3_n_0 ));
  LUT5 #(
    .INIT(32'h77770777)) 
    \fsm[0]_i_8__3 
       (.I0(p_0_in7_in),
        .I1(p_1_in8_in),
        .I2(rxresetdone_reg2),
        .I3(txresetdone_reg2),
        .I4(phystatus_reg2),
        .O(\fsm[0]_i_8__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \fsm[0]_i_9__3 
       (.I0(Q[1]),
        .I1(Q[2]),
        .O(\fsm[0]_i_9__3_n_0 ));
  LUT5 #(
    .INIT(32'h30BBFC00)) 
    \fsm[1]_i_4__3 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(\fsm[1]_i_8__3_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'hCC88300000BB3000)) 
    \fsm[1]_i_5__3 
       (.I0(\fsm[0]_i_10__3_n_0 ),
        .I1(Q[2]),
        .I2(\fsm[1]_i_9__3_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_5__3_n_0 ));
  LUT5 #(
    .INIT(32'h70F040F0)) 
    \fsm[1]_i_6__3 
       (.I0(resetovrd_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(drp_done_reg2),
        .O(\fsm[1]_i_6__3_n_0 ));
  LUT5 #(
    .INIT(32'h03777700)) 
    \fsm[1]_i_7__3 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_7__3_n_0 ));
  LUT6 #(
    .INIT(64'h53F5FFFFFFFFFFFF)) 
    \fsm[1]_i_8__3 
       (.I0(cplllock_reg2),
        .I1(qplllock_reg2),
        .I2(rate_in_reg2[0]),
        .I3(rate_in_reg2[1]),
        .I4(rst_idle_reg2),
        .I5(Q[0]),
        .O(\fsm[1]_i_8__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF4575FFFFFFFF)) 
    \fsm[1]_i_9__3 
       (.I0(cplllock_reg2),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .I3(qplllock_reg2),
        .I4(rst_idle_reg2),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_9__3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fsm[2]_i_1__7 
       (.I0(\fsm[2]_i_2__3_n_0 ),
        .I1(\fsm[2]_i_3__3_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[2]_i_4__3_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[2]_i_5__3_n_0 ),
        .O(fsm[2]));
  LUT5 #(
    .INIT(32'h3C0C4040)) 
    \fsm[2]_i_2__3 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_done_reg2),
        .I4(Q[0]),
        .O(\fsm[2]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h13CCD3CC1FCCDFCC)) 
    \fsm[2]_i_3__3 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(resetovrd_done_reg2),
        .I5(fsm1),
        .O(\fsm[2]_i_3__3_n_0 ));
  LUT4 #(
    .INIT(16'hBC0C)) 
    \fsm[2]_i_4__3 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\fsm[2]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'h4A4A4A4AAAAFAAAA)) 
    \fsm[2]_i_5__3 
       (.I0(Q[2]),
        .I1(pll_lock),
        .I2(Q[1]),
        .I3(\fsm[3]_i_9__3_n_0 ),
        .I4(\fsm[3]_i_8__3_n_0 ),
        .I5(Q[0]),
        .O(\fsm[2]_i_5__3_n_0 ));
  LUT6 #(
    .INIT(64'hEFE0EFEFEFE0E0E0)) 
    \fsm[3]_i_1__3 
       (.I0(\fsm[3]_i_2__3_n_0 ),
        .I1(\fsm[3]_i_3__3_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[3]_i_4__3_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[3]_i_5__3_n_0 ),
        .O(fsm[3]));
  LUT5 #(
    .INIT(32'h22AA2A22)) 
    \fsm[3]_i_2__3 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(rxsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[3]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h3020002000000000)) 
    \fsm[3]_i_3__3 
       (.I0(fsm1),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(resetovrd_done_reg2),
        .I5(Q[0]),
        .O(\fsm[3]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hF545F555FFFFFFFF)) 
    \fsm[3]_i_4__3 
       (.I0(Q[2]),
        .I1(rst_idle_reg2),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(pll_lock),
        .I5(Q[1]),
        .O(\fsm[3]_i_4__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT5 #(
    .INIT(32'h80808180)) 
    \fsm[3]_i_5__3 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\fsm[3]_i_8__3_n_0 ),
        .I4(\fsm[3]_i_9__3_n_0 ),
        .O(\fsm[3]_i_5__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8F8FFF8)) 
    \fsm[3]_i_6__3 
       (.I0(p_1_in8_in),
        .I1(p_0_in7_in),
        .I2(ratedone_reg_n_0),
        .I3(rate_in_reg2[1]),
        .I4(rate_in_reg2[0]),
        .I5(gen3_exit),
        .O(fsm1));
  LUT4 #(
    .INIT(16'hFB08)) 
    \fsm[3]_i_7__3 
       (.I0(qplllock_reg2),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(cplllock_reg2),
        .O(pll_lock));
  LUT4 #(
    .INIT(16'hB0BB)) 
    \fsm[3]_i_8__3 
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg1[0]),
        .I3(rate_in_reg1[1]),
        .O(\fsm[3]_i_8__3_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \fsm[3]_i_9__3 
       (.I0(rate_in_reg1[0]),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg1[1]),
        .I3(rate_in_reg2[1]),
        .O(\fsm[3]_i_9__3_n_0 ));
  LUT5 #(
    .INIT(32'h08880000)) 
    \fsm[4]_i_2__3 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\fsm[4]_i_2__3_n_0 ));
  LUT5 #(
    .INIT(32'h5F75FFFF)) 
    \fsm[4]_i_3__3 
       (.I0(Q[2]),
        .I1(rxsync_done_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\fsm[4]_i_3__3_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  MUXF7 \fsm_reg[0]_i_2__3 
       (.I0(\fsm[0]_i_6__3_n_0 ),
        .I1(\fsm[0]_i_7__3_n_0 ),
        .O(\fsm_reg[0]_i_2__3_n_0 ),
        .S(Q[3]));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .S(RST_CPLLRESET));
  MUXF8 \fsm_reg[1]_i_1__3 
       (.I0(\fsm_reg[1]_i_2__3_n_0 ),
        .I1(\fsm_reg[1]_i_3__3_n_0 ),
        .O(fsm[1]),
        .S(Q[4]));
  MUXF7 \fsm_reg[1]_i_2__3 
       (.I0(\fsm[1]_i_4__3_n_0 ),
        .I1(\fsm[1]_i_5__3_n_0 ),
        .O(\fsm_reg[1]_i_2__3_n_0 ),
        .S(Q[3]));
  MUXF7 \fsm_reg[1]_i_3__3 
       (.I0(\fsm[1]_i_6__3_n_0 ),
        .I1(\fsm[1]_i_7__3_n_0 ),
        .O(\fsm_reg[1]_i_3__3_n_0 ),
        .S(Q[3]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  MUXF7 \fsm_reg[4]_i_1__3 
       (.I0(\fsm[4]_i_2__3_n_0 ),
        .I1(\fsm[4]_i_3__3_n_0 ),
        .O(fsm[4]),
        .S(Q[4]));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_exit_i_1__3
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_exit_i_2__3_n_0),
        .I4(gen3_exit),
        .O(gen3_exit_i_1__3_n_0));
  LUT6 #(
    .INIT(64'hC000000000000001)) 
    gen3_exit_i_2__3
       (.I0(\fsm[3]_i_9__3_n_0 ),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(gen3_exit_i_2__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_exit_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_exit_i_1__3_n_0),
        .Q(gen3_exit),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_i_1__3
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_i_2__3_n_0),
        .I4(rate_gen3),
        .O(gen3_i_1__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT5 #(
    .INIT(32'h80000008)) 
    gen3_i_2__3
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[1]),
        .O(gen3_i_2__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_i_1__3_n_0),
        .Q(rate_gen3),
        .R(RST_CPLLRESET));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_6__2 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[4]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_7__3 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[4] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h06FF0600)) 
    pclk_sel_i_1__4
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(pclk_sel_i_2__3_n_0),
        .I4(USER_PCLK_SEL),
        .O(pclk_sel_i_1__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT5 #(
    .INIT(32'h80040800)) 
    pclk_sel_i_2__3
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(pclk_sel_i_2__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(pclk_sel_i_1__4_n_0),
        .Q(USER_PCLK_SEL),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    phystatus_i_1__3
       (.I0(phystatus_reg2),
        .I1(txratedone_i_2__3_n_0),
        .I2(phystatus_reg_n_0),
        .O(phystatus_i_1__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    phystatus_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_i_1__3_n_0),
        .Q(phystatus_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_PHYSTATUS),
        .Q(phystatus_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_reg1),
        .Q(phystatus_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    pipe_rate_idle_INST_0_i_2
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(RST_RATE_IDLE));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_QPLLLOCK),
        .Q(qplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllpd_i_1__4
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(QRST_QPLLPD_IN),
        .O(qpllpd_i_1__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllpd_i_1__4_n_0),
        .Q(QRST_QPLLPD_IN),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllreset_i_1__4
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(QRST_QPLLRESET_IN),
        .O(qpllreset_i_1__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllreset_i_1__4_n_0),
        .Q(QRST_QPLLRESET_IN),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    rate_done_reg1_i_1__3
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(USER_RATE_DONE));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_in_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_in_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[0]),
        .Q(rate_in_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[1]),
        .Q(rate_in_reg2[1]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    \rate_out[0]_i_1__3 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .I2(Q[1]),
        .I3(\rate_out[2]_i_2__3_n_0 ),
        .I4(RXRATE[0]),
        .O(\rate_out[0]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[1]_i_1__3 
       (.I0(\rate_out[2]_i_2__3_n_0 ),
        .I1(RXRATE[1]),
        .O(\rate_out[1]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[2]_i_1__3 
       (.I0(\rate_out[2]_i_2__3_n_0 ),
        .I1(RXRATE[2]),
        .O(\rate_out[2]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h8000002080000220)) 
    \rate_out[2]_i_2__3 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\rate_out[2]_i_3__3_n_0 ),
        .O(\rate_out[2]_i_2__3_n_0 ));
  LUT3 #(
    .INIT(8'h45)) 
    \rate_out[2]_i_3__3 
       (.I0(gen3_exit),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .O(\rate_out[2]_i_3__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[0]_i_1__3_n_0 ),
        .Q(RXRATE[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[1]_i_1__3_n_0 ),
        .Q(RXRATE[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[2]_i_1__3_n_0 ),
        .Q(RXRATE[2]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT5 #(
    .INIT(32'h00808000)) 
    rate_rxsync_reg1_i_1__3
       (.I0(Q[3]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(USER_RATE_RXSYNC));
  LUT5 #(
    .INIT(32'hFF008000)) 
    ratedone_i_1__3
       (.I0(rxratedone_reg_n_0),
        .I1(txratedone_reg_n_0),
        .I2(phystatus_reg_n_0),
        .I3(txratedone_i_2__3_n_0),
        .I4(ratedone_reg_n_0),
        .O(ratedone_i_1__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(ratedone_i_1__3_n_0),
        .Q(ratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RESETOVRD_DONE),
        .Q(resetovrd_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(resetovrd_done_reg1),
        .Q(resetovrd_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    resetovrd_start_reg1_i_1__3
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[4]),
        .I4(Q[2]),
        .O(USER_RESETOVRD_START));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(out1[1]),
        .Q(rst_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1),
        .Q(rxpmaresetdone_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    rxratedone_i_1__3
       (.I0(rxratedone_reg2),
        .I1(txratedone_i_2__3_n_0),
        .I2(rxratedone_reg_n_0),
        .O(rxratedone_i_1__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_i_1__3_n_0),
        .Q(rxratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RXRATEDONE),
        .Q(rxratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_reg1),
        .Q(rxratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONE),
        .Q(rxsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxsync_done_reg1),
        .Q(rxsync_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    rxsync_start_reg1_i_1__3
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(SYNC_RXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    start_reg1_i_1__3
       (.I0(p_0_in129_in),
        .I1(RST_DRP_START),
        .O(DRP_START0130_out));
  LUT6 #(
    .INIT(64'hFFFF3EFF00000200)) 
    \sysclksel[0]_i_1__3 
       (.I0(\sysclksel[0]_i_2__3_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(\sysclksel[0]_i_3__3_n_0 ),
        .I5(RXSYSCLKSEL[0]),
        .O(\sysclksel[0]_i_1__3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \sysclksel[0]_i_2__3 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .O(\sysclksel[0]_i_2__3_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \sysclksel[0]_i_3__3 
       (.I0(Q[2]),
        .I1(Q[1]),
        .O(\sysclksel[0]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'h6FFFFFFF00000000)) 
    \sysclksel[1]_i_1__3 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(RXSYSCLKSEL[1]),
        .O(\sysclksel[1]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[0]_i_1__3_n_0 ),
        .Q(RXSYSCLKSEL[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[1]_i_1__3_n_0 ),
        .Q(RXSYSCLKSEL[1]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT5 #(
    .INIT(32'h80AA00AA)) 
    \txdata_wait_cnt[0]_i_1__3 
       (.I0(\txdata_wait_cnt[3]_i_2__3_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT5 #(
    .INIT(32'hA8282828)) 
    \txdata_wait_cnt[1]_i_1__3 
       (.I0(\txdata_wait_cnt[3]_i_2__3_n_0 ),
        .I1(txdata_wait_cnt_reg__0[0]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[3]),
        .I4(txdata_wait_cnt_reg__0[2]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT5 #(
    .INIT(32'h8AA0A0A0)) 
    \txdata_wait_cnt[2]_i_1__3 
       (.I0(\txdata_wait_cnt[3]_i_2__3_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \txdata_wait_cnt[3]_i_1__3 
       (.I0(\txdata_wait_cnt[3]_i_2__3_n_0 ),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \txdata_wait_cnt[3]_i_2__3 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\txdata_wait_cnt[3]_i_2__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(txdata_wait_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(txdata_wait_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(txdata_wait_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(txdata_wait_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h5504FFFF55040000)) 
    txpmareset_i_1__3
       (.I0(Q[3]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(gen3_exit),
        .I4(txpmareset_i_2__3_n_0),
        .I5(GT_TXPMARESET064_out),
        .O(txpmareset_i_1__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT5 #(
    .INIT(32'h82000400)) 
    txpmareset_i_2__3
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(txpmareset_i_2__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txpmareset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txpmareset_i_1__3_n_0),
        .Q(GT_TXPMARESET064_out),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    txratedone_i_1__3
       (.I0(txratedone_reg2),
        .I1(txratedone_i_2__3_n_0),
        .I2(txratedone_reg_n_0),
        .O(txratedone_i_1__3_n_0));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    txratedone_i_2__3
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(RST_CPLLRESET),
        .O(txratedone_i_2__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_i_1__3_n_0),
        .Q(txratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXRATEDONE),
        .Q(txratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_reg1),
        .Q(txratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXSYNC_DONE),
        .Q(txsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txsync_done_reg1),
        .Q(txsync_done_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAA)) 
    txsync_start_reg1_i_1__3
       (.I0(out1[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(SYNC_TXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    x16_reg1_i_1__3
       (.I0(p_0_in131_in),
        .I1(RST_DRP_X16),
        .O(DRP_X160132_out));
  LUT2 #(
    .INIT(4'hE)) 
    x16x20_mode_reg1_i_1__3
       (.I0(p_0_in133_in),
        .I1(RST_DRP_X16X20_MODE),
        .O(DRP_X16X20_MODE0134_out));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_rate" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_57
   (Q,
    USER_RESETOVRD_START,
    RXSYSCLKSEL,
    SYNC_TXSYNC_START,
    DRP_X16X20_MODE058_out,
    DRP_X16056_out,
    DRP_START054_out,
    \cplllock_reg1_reg[5] ,
    rate_gen3,
    \cplllock_reg1_reg[5]_0 ,
    RXRATE,
    USER_RATE_DONE,
    USER_RATE_RXSYNC,
    SYNC_RXSYNC_START,
    RST_RATE_IDLE,
    GT_TXPMARESET046_out,
    USER_PCLK_SEL,
    QRST_QPLLRESET_IN,
    p_0_in47_in,
    QRST_QPLLPD_IN,
    p_0_in49_in,
    out1,
    RST_DRP_X16X20_MODE,
    RST_DRP_X16,
    RST_DRP_START,
    RST_CPLLRESET,
    pclk_sel_reg_0,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    RATE_CPLLLOCK,
    RATE_QPLLLOCK,
    RATE_DRP_DONE,
    \resetovrd_disble.reset_reg[4] ,
    RATE_PHYSTATUS,
    USER_TXRESETDONE,
    USER_RXRESETDONE,
    RATE_TXRATEDONE,
    RATE_RXRATEDONE,
    RATE_RESETOVRD_DONE,
    RATE_TXSYNC_DONE,
    SYNC_RXSYNC_DONE,
    p_1_in8_in,
    p_0_in7_in);
  output [4:0]Q;
  output USER_RESETOVRD_START;
  output [1:0]RXSYSCLKSEL;
  output SYNC_TXSYNC_START;
  output DRP_X16X20_MODE058_out;
  output DRP_X16056_out;
  output DRP_START054_out;
  output \cplllock_reg1_reg[5] ;
  output [0:0]rate_gen3;
  output \cplllock_reg1_reg[5]_0 ;
  output [2:0]RXRATE;
  output USER_RATE_DONE;
  output USER_RATE_RXSYNC;
  output SYNC_RXSYNC_START;
  output [0:0]RST_RATE_IDLE;
  output GT_TXPMARESET046_out;
  output USER_PCLK_SEL;
  output [0:0]QRST_QPLLRESET_IN;
  output p_0_in47_in;
  output [0:0]QRST_QPLLPD_IN;
  output p_0_in49_in;
  input [1:0]out1;
  input RST_DRP_X16X20_MODE;
  input RST_DRP_X16;
  input RST_DRP_START;
  input RST_CPLLRESET;
  input pclk_sel_reg_0;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input RATE_CPLLLOCK;
  input RATE_QPLLLOCK;
  input RATE_DRP_DONE;
  input \resetovrd_disble.reset_reg[4] ;
  input RATE_PHYSTATUS;
  input USER_TXRESETDONE;
  input USER_RXRESETDONE;
  input RATE_TXRATEDONE;
  input RATE_RXRATEDONE;
  input RATE_RESETOVRD_DONE;
  input RATE_TXSYNC_DONE;
  input SYNC_RXSYNC_DONE;
  input p_1_in8_in;
  input p_0_in7_in;

  wire DRP_START054_out;
  wire DRP_X16056_out;
  wire DRP_X16X20_MODE058_out;
  wire GT_TXPMARESET046_out;
  wire [4:0]Q;
  wire [0:0]QRST_QPLLPD_IN;
  wire [0:0]QRST_QPLLRESET_IN;
  wire RATE_CPLLLOCK;
  wire RATE_DRP_DONE;
  wire RATE_PHYSTATUS;
  wire RATE_QPLLLOCK;
  wire RATE_RESETOVRD_DONE;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RATE_TXSYNC_DONE;
  wire RST_CPLLRESET;
  wire RST_DRP_START;
  wire RST_DRP_X16;
  wire RST_DRP_X16X20_MODE;
  wire [0:0]RST_RATE_IDLE;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXSYNC_START;
  wire USER_PCLK_SEL;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire cplllock_reg1;
  wire \cplllock_reg1_reg[5] ;
  wire \cplllock_reg1_reg[5]_0 ;
  wire cplllock_reg2;
  wire cpllpd_i_1__4_n_0;
  wire cpllreset_i_1__5_n_0;
  wire drp_done_reg1;
  wire drp_done_reg2;
  wire drp_start_i_1__4_n_0;
  wire drp_x16_i_1__4_n_0;
  wire drp_x16x20_mode_i_1__4_n_0;
  wire [4:0]fsm;
  wire fsm1;
  wire \fsm[0]_i_10__4_n_0 ;
  wire \fsm[0]_i_11__4_n_0 ;
  wire \fsm[0]_i_12__4_n_0 ;
  wire \fsm[0]_i_3__9_n_0 ;
  wire \fsm[0]_i_4__4_n_0 ;
  wire \fsm[0]_i_5__4_n_0 ;
  wire \fsm[0]_i_6__4_n_0 ;
  wire \fsm[0]_i_7__4_n_0 ;
  wire \fsm[0]_i_8__4_n_0 ;
  wire \fsm[0]_i_9__4_n_0 ;
  wire \fsm[1]_i_4__4_n_0 ;
  wire \fsm[1]_i_5__4_n_0 ;
  wire \fsm[1]_i_6__4_n_0 ;
  wire \fsm[1]_i_7__4_n_0 ;
  wire \fsm[1]_i_8__4_n_0 ;
  wire \fsm[1]_i_9__4_n_0 ;
  wire \fsm[2]_i_2__4_n_0 ;
  wire \fsm[2]_i_3__4_n_0 ;
  wire \fsm[2]_i_4__4_n_0 ;
  wire \fsm[2]_i_5__4_n_0 ;
  wire \fsm[3]_i_2__4_n_0 ;
  wire \fsm[3]_i_3__4_n_0 ;
  wire \fsm[3]_i_4__4_n_0 ;
  wire \fsm[3]_i_5__4_n_0 ;
  wire \fsm[3]_i_8__4_n_0 ;
  wire \fsm[3]_i_9__4_n_0 ;
  wire \fsm[4]_i_2__4_n_0 ;
  wire \fsm[4]_i_3__4_n_0 ;
  wire \fsm_reg[0]_i_2__4_n_0 ;
  wire \fsm_reg[1]_i_2__4_n_0 ;
  wire \fsm_reg[1]_i_3__4_n_0 ;
  wire gen3_exit;
  wire gen3_exit_i_1__4_n_0;
  wire gen3_exit_i_2__4_n_0;
  wire gen3_i_1__4_n_0;
  wire gen3_i_2__4_n_0;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire [1:0]out1;
  wire p_0_in47_in;
  wire p_0_in49_in;
  wire p_0_in53_in;
  wire p_0_in55_in;
  wire p_0_in57_in;
  wire p_0_in7_in;
  wire [3:0]p_0_in__0;
  wire p_1_in8_in;
  wire pclk_sel_i_1__5_n_0;
  wire pclk_sel_i_2__4_n_0;
  wire pclk_sel_reg_0;
  wire phystatus_i_1__4_n_0;
  wire phystatus_reg1;
  wire phystatus_reg2;
  wire phystatus_reg_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire pll_lock;
  wire qplllock_reg1;
  wire qplllock_reg2;
  wire qpllpd;
  wire qpllpd_i_1__5_n_0;
  wire qpllreset;
  wire qpllreset_i_1__5_n_0;
  wire [0:0]rate_gen3;
  wire [1:0]rate_in_reg1;
  wire [1:0]rate_in_reg2;
  wire \rate_out[0]_i_1__4_n_0 ;
  wire \rate_out[1]_i_1__4_n_0 ;
  wire \rate_out[2]_i_1__4_n_0 ;
  wire \rate_out[2]_i_2__4_n_0 ;
  wire \rate_out[2]_i_3__4_n_0 ;
  wire ratedone_i_1__4_n_0;
  wire ratedone_reg_n_0;
  wire \resetovrd_disble.reset_reg[4] ;
  wire resetovrd_done_reg1;
  wire resetovrd_done_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire rxpmaresetdone_reg1;
  wire rxpmaresetdone_reg2;
  wire rxratedone_i_1__4_n_0;
  wire rxratedone_reg1;
  wire rxratedone_reg2;
  wire rxratedone_reg_n_0;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxsync_done_reg1;
  wire rxsync_done_reg2;
  wire \sysclksel[0]_i_1__4_n_0 ;
  wire \sysclksel[0]_i_2__4_n_0 ;
  wire \sysclksel[0]_i_3__4_n_0 ;
  wire \sysclksel[1]_i_1__4_n_0 ;
  wire \txdata_wait_cnt[3]_i_2__4_n_0 ;
  wire [3:0]txdata_wait_cnt_reg__0;
  wire txpmareset_i_1__4_n_0;
  wire txpmareset_i_2__4_n_0;
  wire txratedone_i_1__4_n_0;
  wire txratedone_i_2__4_n_0;
  wire txratedone_reg1;
  wire txratedone_reg2;
  wire txratedone_reg_n_0;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire txsync_done_reg1;
  wire txsync_done_reg2;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_CPLLLOCK),
        .Q(cplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cplllock_reg1),
        .Q(cplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllpd_i_1__4
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(p_0_in49_in),
        .O(cpllpd_i_1__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT5 #(
    .INIT(32'h80000084)) 
    cpllpd_i_2__4
       (.I0(Q[4]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(qpllpd));
  FDRE #(
    .INIT(1'b0)) 
    cpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllpd_i_1__4_n_0),
        .Q(p_0_in49_in),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllreset_i_1__5
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(p_0_in47_in),
        .O(cpllreset_i_1__5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT5 #(
    .INIT(32'h81000002)) 
    cpllreset_i_2__4
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(qpllreset));
  FDRE #(
    .INIT(1'b0)) 
    cpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllreset_i_1__5_n_0),
        .Q(p_0_in47_in),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_DRP_DONE),
        .Q(drp_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT5 #(
    .INIT(32'h08200108)) 
    drp_start_i_1__4
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(Q[1]),
        .O(drp_start_i_1__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_start_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_start_i_1__4_n_0),
        .Q(p_0_in53_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT5 #(
    .INIT(32'h20020006)) 
    drp_x16_i_1__4
       (.I0(Q[2]),
        .I1(Q[4]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[0]),
        .O(drp_x16_i_1__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16_i_1__4_n_0),
        .Q(p_0_in55_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT5 #(
    .INIT(32'h20001584)) 
    drp_x16x20_mode_i_1__4
       (.I0(Q[1]),
        .I1(Q[4]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(drp_x16x20_mode_i_1__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16x20_mode_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16x20_mode_i_1__4_n_0),
        .Q(p_0_in57_in),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[0]_i_10__4 
       (.I0(txdata_wait_cnt_reg__0[3]),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[0]),
        .I3(txdata_wait_cnt_reg__0[1]),
        .O(\fsm[0]_i_10__4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000F404)) 
    \fsm[0]_i_11__4 
       (.I0(rxpmaresetdone_reg2),
        .I1(mmcm_lock_reg2),
        .I2(Q[0]),
        .I3(drp_done_reg2),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\fsm[0]_i_11__4_n_0 ));
  LUT6 #(
    .INIT(64'h4F4F737F4343404C)) 
    \fsm[0]_i_12__4 
       (.I0(resetovrd_done_reg2),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(rxpmaresetdone_reg2),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[0]_i_12__4_n_0 ));
  LUT6 #(
    .INIT(64'hBBB88888BBB8BBB8)) 
    \fsm[0]_i_1__9 
       (.I0(\fsm_reg[0]_i_2__4_n_0 ),
        .I1(Q[4]),
        .I2(\fsm[0]_i_3__9_n_0 ),
        .I3(Q[3]),
        .I4(\fsm[0]_i_4__4_n_0 ),
        .I5(\fsm[0]_i_5__4_n_0 ),
        .O(fsm[0]));
  LUT6 #(
    .INIT(64'h0344FF440344FF77)) 
    \fsm[0]_i_3__9 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(pll_lock),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\fsm[3]_i_9__4_n_0 ),
        .O(\fsm[0]_i_3__9_n_0 ));
  LUT6 #(
    .INIT(64'hF0000000F800F000)) 
    \fsm[0]_i_4__4 
       (.I0(pll_lock),
        .I1(rst_idle_reg2),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(drp_done_reg2),
        .I5(Q[0]),
        .O(\fsm[0]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000CCC8C0C8)) 
    \fsm[0]_i_5__4 
       (.I0(\fsm[0]_i_8__4_n_0 ),
        .I1(Q[3]),
        .I2(\fsm[0]_i_9__4_n_0 ),
        .I3(Q[0]),
        .I4(\fsm[0]_i_10__4_n_0 ),
        .I5(\fsm[0]_i_11__4_n_0 ),
        .O(\fsm[0]_i_5__4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0040)) 
    \fsm[0]_i_6__4 
       (.I0(fsm1),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(\fsm[0]_i_12__4_n_0 ),
        .O(\fsm[0]_i_6__4_n_0 ));
  LUT5 #(
    .INIT(32'h03880333)) 
    \fsm[0]_i_7__4 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[0]_i_7__4_n_0 ));
  LUT5 #(
    .INIT(32'h77770777)) 
    \fsm[0]_i_8__4 
       (.I0(p_0_in7_in),
        .I1(p_1_in8_in),
        .I2(rxresetdone_reg2),
        .I3(txresetdone_reg2),
        .I4(phystatus_reg2),
        .O(\fsm[0]_i_8__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \fsm[0]_i_9__4 
       (.I0(Q[1]),
        .I1(Q[2]),
        .O(\fsm[0]_i_9__4_n_0 ));
  LUT5 #(
    .INIT(32'h30BBFC00)) 
    \fsm[1]_i_4__4 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(\fsm[1]_i_8__4_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'hCC88300000BB3000)) 
    \fsm[1]_i_5__4 
       (.I0(\fsm[0]_i_10__4_n_0 ),
        .I1(Q[2]),
        .I2(\fsm[1]_i_9__4_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_5__4_n_0 ));
  LUT5 #(
    .INIT(32'h70F040F0)) 
    \fsm[1]_i_6__4 
       (.I0(resetovrd_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(drp_done_reg2),
        .O(\fsm[1]_i_6__4_n_0 ));
  LUT5 #(
    .INIT(32'h03777700)) 
    \fsm[1]_i_7__4 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_7__4_n_0 ));
  LUT6 #(
    .INIT(64'h53F5FFFFFFFFFFFF)) 
    \fsm[1]_i_8__4 
       (.I0(cplllock_reg2),
        .I1(qplllock_reg2),
        .I2(rate_in_reg2[0]),
        .I3(rate_in_reg2[1]),
        .I4(rst_idle_reg2),
        .I5(Q[0]),
        .O(\fsm[1]_i_8__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF4575FFFFFFFF)) 
    \fsm[1]_i_9__4 
       (.I0(cplllock_reg2),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .I3(qplllock_reg2),
        .I4(rst_idle_reg2),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_9__4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fsm[2]_i_1__9 
       (.I0(\fsm[2]_i_2__4_n_0 ),
        .I1(\fsm[2]_i_3__4_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[2]_i_4__4_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[2]_i_5__4_n_0 ),
        .O(fsm[2]));
  LUT5 #(
    .INIT(32'h3C0C4040)) 
    \fsm[2]_i_2__4 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_done_reg2),
        .I4(Q[0]),
        .O(\fsm[2]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h13CCD3CC1FCCDFCC)) 
    \fsm[2]_i_3__4 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(resetovrd_done_reg2),
        .I5(fsm1),
        .O(\fsm[2]_i_3__4_n_0 ));
  LUT4 #(
    .INIT(16'hBC0C)) 
    \fsm[2]_i_4__4 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\fsm[2]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'h4A4A4A4AAAAFAAAA)) 
    \fsm[2]_i_5__4 
       (.I0(Q[2]),
        .I1(pll_lock),
        .I2(Q[1]),
        .I3(\fsm[3]_i_9__4_n_0 ),
        .I4(\fsm[3]_i_8__4_n_0 ),
        .I5(Q[0]),
        .O(\fsm[2]_i_5__4_n_0 ));
  LUT6 #(
    .INIT(64'hEFE0EFEFEFE0E0E0)) 
    \fsm[3]_i_1__4 
       (.I0(\fsm[3]_i_2__4_n_0 ),
        .I1(\fsm[3]_i_3__4_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[3]_i_4__4_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[3]_i_5__4_n_0 ),
        .O(fsm[3]));
  LUT5 #(
    .INIT(32'h22AA2A22)) 
    \fsm[3]_i_2__4 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(rxsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[3]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h3020002000000000)) 
    \fsm[3]_i_3__4 
       (.I0(fsm1),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(resetovrd_done_reg2),
        .I5(Q[0]),
        .O(\fsm[3]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hF545F555FFFFFFFF)) 
    \fsm[3]_i_4__4 
       (.I0(Q[2]),
        .I1(rst_idle_reg2),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(pll_lock),
        .I5(Q[1]),
        .O(\fsm[3]_i_4__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT5 #(
    .INIT(32'h80808180)) 
    \fsm[3]_i_5__4 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\fsm[3]_i_8__4_n_0 ),
        .I4(\fsm[3]_i_9__4_n_0 ),
        .O(\fsm[3]_i_5__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8F8FFF8)) 
    \fsm[3]_i_6__4 
       (.I0(p_1_in8_in),
        .I1(p_0_in7_in),
        .I2(ratedone_reg_n_0),
        .I3(rate_in_reg2[1]),
        .I4(rate_in_reg2[0]),
        .I5(gen3_exit),
        .O(fsm1));
  LUT4 #(
    .INIT(16'hFB08)) 
    \fsm[3]_i_7__4 
       (.I0(qplllock_reg2),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(cplllock_reg2),
        .O(pll_lock));
  LUT4 #(
    .INIT(16'hB0BB)) 
    \fsm[3]_i_8__4 
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg1[0]),
        .I3(rate_in_reg1[1]),
        .O(\fsm[3]_i_8__4_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \fsm[3]_i_9__4 
       (.I0(rate_in_reg1[0]),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg1[1]),
        .I3(rate_in_reg2[1]),
        .O(\fsm[3]_i_9__4_n_0 ));
  LUT5 #(
    .INIT(32'h08880000)) 
    \fsm[4]_i_2__4 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\fsm[4]_i_2__4_n_0 ));
  LUT5 #(
    .INIT(32'h5F75FFFF)) 
    \fsm[4]_i_3__4 
       (.I0(Q[2]),
        .I1(rxsync_done_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\fsm[4]_i_3__4_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  MUXF7 \fsm_reg[0]_i_2__4 
       (.I0(\fsm[0]_i_6__4_n_0 ),
        .I1(\fsm[0]_i_7__4_n_0 ),
        .O(\fsm_reg[0]_i_2__4_n_0 ),
        .S(Q[3]));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .S(RST_CPLLRESET));
  MUXF8 \fsm_reg[1]_i_1__4 
       (.I0(\fsm_reg[1]_i_2__4_n_0 ),
        .I1(\fsm_reg[1]_i_3__4_n_0 ),
        .O(fsm[1]),
        .S(Q[4]));
  MUXF7 \fsm_reg[1]_i_2__4 
       (.I0(\fsm[1]_i_4__4_n_0 ),
        .I1(\fsm[1]_i_5__4_n_0 ),
        .O(\fsm_reg[1]_i_2__4_n_0 ),
        .S(Q[3]));
  MUXF7 \fsm_reg[1]_i_3__4 
       (.I0(\fsm[1]_i_6__4_n_0 ),
        .I1(\fsm[1]_i_7__4_n_0 ),
        .O(\fsm_reg[1]_i_3__4_n_0 ),
        .S(Q[3]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  MUXF7 \fsm_reg[4]_i_1__4 
       (.I0(\fsm[4]_i_2__4_n_0 ),
        .I1(\fsm[4]_i_3__4_n_0 ),
        .O(fsm[4]),
        .S(Q[4]));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_exit_i_1__4
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_exit_i_2__4_n_0),
        .I4(gen3_exit),
        .O(gen3_exit_i_1__4_n_0));
  LUT6 #(
    .INIT(64'hC000000000000001)) 
    gen3_exit_i_2__4
       (.I0(\fsm[3]_i_9__4_n_0 ),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(gen3_exit_i_2__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_exit_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_exit_i_1__4_n_0),
        .Q(gen3_exit),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_i_1__4
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_i_2__4_n_0),
        .I4(rate_gen3),
        .O(gen3_i_1__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT5 #(
    .INIT(32'h80000008)) 
    gen3_i_2__4
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[1]),
        .O(gen3_i_2__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_i_1__4_n_0),
        .Q(rate_gen3),
        .R(RST_CPLLRESET));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_6__1 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[5]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_7__4 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[5] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h06FF0600)) 
    pclk_sel_i_1__5
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(pclk_sel_i_2__4_n_0),
        .I4(USER_PCLK_SEL),
        .O(pclk_sel_i_1__5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT5 #(
    .INIT(32'h80040800)) 
    pclk_sel_i_2__4
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(pclk_sel_i_2__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(pclk_sel_i_1__5_n_0),
        .Q(USER_PCLK_SEL),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    phystatus_i_1__4
       (.I0(phystatus_reg2),
        .I1(txratedone_i_2__4_n_0),
        .I2(phystatus_reg_n_0),
        .O(phystatus_i_1__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    phystatus_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_i_1__4_n_0),
        .Q(phystatus_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_PHYSTATUS),
        .Q(phystatus_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_reg1),
        .Q(phystatus_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    pipe_rate_idle_INST_0_i_3
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(RST_RATE_IDLE));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_QPLLLOCK),
        .Q(qplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllpd_i_1__5
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(QRST_QPLLPD_IN),
        .O(qpllpd_i_1__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllpd_i_1__5_n_0),
        .Q(QRST_QPLLPD_IN),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllreset_i_1__5
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(QRST_QPLLRESET_IN),
        .O(qpllreset_i_1__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllreset_i_1__5_n_0),
        .Q(QRST_QPLLRESET_IN),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    rate_done_reg1_i_1__4
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(USER_RATE_DONE));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_in_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_in_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[0]),
        .Q(rate_in_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[1]),
        .Q(rate_in_reg2[1]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    \rate_out[0]_i_1__4 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .I2(Q[1]),
        .I3(\rate_out[2]_i_2__4_n_0 ),
        .I4(RXRATE[0]),
        .O(\rate_out[0]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[1]_i_1__4 
       (.I0(\rate_out[2]_i_2__4_n_0 ),
        .I1(RXRATE[1]),
        .O(\rate_out[1]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[2]_i_1__4 
       (.I0(\rate_out[2]_i_2__4_n_0 ),
        .I1(RXRATE[2]),
        .O(\rate_out[2]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h8000002080000220)) 
    \rate_out[2]_i_2__4 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\rate_out[2]_i_3__4_n_0 ),
        .O(\rate_out[2]_i_2__4_n_0 ));
  LUT3 #(
    .INIT(8'h45)) 
    \rate_out[2]_i_3__4 
       (.I0(gen3_exit),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .O(\rate_out[2]_i_3__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[0]_i_1__4_n_0 ),
        .Q(RXRATE[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[1]_i_1__4_n_0 ),
        .Q(RXRATE[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[2]_i_1__4_n_0 ),
        .Q(RXRATE[2]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT5 #(
    .INIT(32'h00808000)) 
    rate_rxsync_reg1_i_1__4
       (.I0(Q[3]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(USER_RATE_RXSYNC));
  LUT5 #(
    .INIT(32'hFF008000)) 
    ratedone_i_1__4
       (.I0(rxratedone_reg_n_0),
        .I1(txratedone_reg_n_0),
        .I2(phystatus_reg_n_0),
        .I3(txratedone_i_2__4_n_0),
        .I4(ratedone_reg_n_0),
        .O(ratedone_i_1__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(ratedone_i_1__4_n_0),
        .Q(ratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RESETOVRD_DONE),
        .Q(resetovrd_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(resetovrd_done_reg1),
        .Q(resetovrd_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    resetovrd_start_reg1_i_1__4
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[4]),
        .I4(Q[2]),
        .O(USER_RESETOVRD_START));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(out1[1]),
        .Q(rst_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1),
        .Q(rxpmaresetdone_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    rxratedone_i_1__4
       (.I0(rxratedone_reg2),
        .I1(txratedone_i_2__4_n_0),
        .I2(rxratedone_reg_n_0),
        .O(rxratedone_i_1__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_i_1__4_n_0),
        .Q(rxratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RXRATEDONE),
        .Q(rxratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_reg1),
        .Q(rxratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONE),
        .Q(rxsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxsync_done_reg1),
        .Q(rxsync_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    rxsync_start_reg1_i_1__4
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(SYNC_RXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    start_reg1_i_1__4
       (.I0(p_0_in53_in),
        .I1(RST_DRP_START),
        .O(DRP_START054_out));
  LUT6 #(
    .INIT(64'hFFFF3EFF00000200)) 
    \sysclksel[0]_i_1__4 
       (.I0(\sysclksel[0]_i_2__4_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(\sysclksel[0]_i_3__4_n_0 ),
        .I5(RXSYSCLKSEL[0]),
        .O(\sysclksel[0]_i_1__4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \sysclksel[0]_i_2__4 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .O(\sysclksel[0]_i_2__4_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \sysclksel[0]_i_3__4 
       (.I0(Q[2]),
        .I1(Q[1]),
        .O(\sysclksel[0]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'h6FFFFFFF00000000)) 
    \sysclksel[1]_i_1__4 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(RXSYSCLKSEL[1]),
        .O(\sysclksel[1]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[0]_i_1__4_n_0 ),
        .Q(RXSYSCLKSEL[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[1]_i_1__4_n_0 ),
        .Q(RXSYSCLKSEL[1]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT5 #(
    .INIT(32'h80AA00AA)) 
    \txdata_wait_cnt[0]_i_1__4 
       (.I0(\txdata_wait_cnt[3]_i_2__4_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT5 #(
    .INIT(32'hA8282828)) 
    \txdata_wait_cnt[1]_i_1__4 
       (.I0(\txdata_wait_cnt[3]_i_2__4_n_0 ),
        .I1(txdata_wait_cnt_reg__0[0]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[3]),
        .I4(txdata_wait_cnt_reg__0[2]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT5 #(
    .INIT(32'h8AA0A0A0)) 
    \txdata_wait_cnt[2]_i_1__4 
       (.I0(\txdata_wait_cnt[3]_i_2__4_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \txdata_wait_cnt[3]_i_1__4 
       (.I0(\txdata_wait_cnt[3]_i_2__4_n_0 ),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \txdata_wait_cnt[3]_i_2__4 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\txdata_wait_cnt[3]_i_2__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(txdata_wait_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(txdata_wait_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(txdata_wait_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(txdata_wait_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h5504FFFF55040000)) 
    txpmareset_i_1__4
       (.I0(Q[3]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(gen3_exit),
        .I4(txpmareset_i_2__4_n_0),
        .I5(GT_TXPMARESET046_out),
        .O(txpmareset_i_1__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT5 #(
    .INIT(32'h82000400)) 
    txpmareset_i_2__4
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(txpmareset_i_2__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txpmareset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txpmareset_i_1__4_n_0),
        .Q(GT_TXPMARESET046_out),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    txratedone_i_1__4
       (.I0(txratedone_reg2),
        .I1(txratedone_i_2__4_n_0),
        .I2(txratedone_reg_n_0),
        .O(txratedone_i_1__4_n_0));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    txratedone_i_2__4
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(RST_CPLLRESET),
        .O(txratedone_i_2__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_i_1__4_n_0),
        .Q(txratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXRATEDONE),
        .Q(txratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_reg1),
        .Q(txratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXSYNC_DONE),
        .Q(txsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txsync_done_reg1),
        .Q(txsync_done_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAA)) 
    txsync_start_reg1_i_1__4
       (.I0(out1[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(SYNC_TXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    x16_reg1_i_1__4
       (.I0(p_0_in55_in),
        .I1(RST_DRP_X16),
        .O(DRP_X16056_out));
  LUT2 #(
    .INIT(4'hE)) 
    x16x20_mode_reg1_i_1__4
       (.I0(p_0_in57_in),
        .I1(RST_DRP_X16X20_MODE),
        .O(DRP_X16X20_MODE058_out));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_rate" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_63
   (Q,
    USER_RESETOVRD_START,
    RXSYSCLKSEL,
    SYNC_TXSYNC_START,
    DRP_X16X20_MODE029_out,
    DRP_X16027_out,
    DRP_START025_out,
    \cplllock_reg1_reg[6] ,
    rate_gen3,
    gen3_reg1_reg,
    \cplllock_reg1_reg[6]_0 ,
    pipe_rate_idle,
    \rate_idle_reg1_reg[6] ,
    RXRATE,
    USER_RATE_DONE,
    USER_RATE_RXSYNC,
    SYNC_RXSYNC_START,
    GT_TXPMARESET035_out,
    USER_PCLK_SEL,
    QRST_QPLLRESET_IN,
    p_0_in36_in,
    QRST_QPLLPD_IN,
    p_0_in38_in,
    out1,
    RST_DRP_X16X20_MODE,
    RST_DRP_X16,
    RST_DRP_START,
    gen3_reg_0,
    gen3_reg_1,
    RST_RATE_IDLE,
    RST_CPLLRESET,
    pclk_sel_reg_0,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    RATE_CPLLLOCK,
    RATE_QPLLLOCK,
    RATE_DRP_DONE,
    \resetovrd_disble.reset_reg[4] ,
    RATE_PHYSTATUS,
    USER_TXRESETDONE,
    USER_RXRESETDONE,
    RATE_TXRATEDONE,
    RATE_RXRATEDONE,
    RATE_RESETOVRD_DONE,
    RATE_TXSYNC_DONE,
    SYNC_RXSYNC_DONE,
    p_1_in8_in,
    p_0_in7_in);
  output [4:0]Q;
  output USER_RESETOVRD_START;
  output [1:0]RXSYSCLKSEL;
  output SYNC_TXSYNC_START;
  output DRP_X16X20_MODE029_out;
  output DRP_X16027_out;
  output DRP_START025_out;
  output \cplllock_reg1_reg[6] ;
  output [0:0]rate_gen3;
  output gen3_reg1_reg;
  output \cplllock_reg1_reg[6]_0 ;
  output pipe_rate_idle;
  output [0:0]\rate_idle_reg1_reg[6] ;
  output [2:0]RXRATE;
  output USER_RATE_DONE;
  output USER_RATE_RXSYNC;
  output SYNC_RXSYNC_START;
  output GT_TXPMARESET035_out;
  output USER_PCLK_SEL;
  output [0:0]QRST_QPLLRESET_IN;
  output p_0_in36_in;
  output [0:0]QRST_QPLLPD_IN;
  output p_0_in38_in;
  input [1:0]out1;
  input RST_DRP_X16X20_MODE;
  input RST_DRP_X16;
  input RST_DRP_START;
  input [5:0]gen3_reg_0;
  input [0:0]gen3_reg_1;
  input [6:0]RST_RATE_IDLE;
  input RST_CPLLRESET;
  input pclk_sel_reg_0;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input RATE_CPLLLOCK;
  input RATE_QPLLLOCK;
  input RATE_DRP_DONE;
  input \resetovrd_disble.reset_reg[4] ;
  input RATE_PHYSTATUS;
  input USER_TXRESETDONE;
  input USER_RXRESETDONE;
  input RATE_TXRATEDONE;
  input RATE_RXRATEDONE;
  input RATE_RESETOVRD_DONE;
  input RATE_TXSYNC_DONE;
  input SYNC_RXSYNC_DONE;
  input p_1_in8_in;
  input p_0_in7_in;

  wire DRP_START025_out;
  wire DRP_X16027_out;
  wire DRP_X16X20_MODE029_out;
  wire GT_TXPMARESET035_out;
  wire [4:0]Q;
  wire [0:0]QRST_QPLLPD_IN;
  wire [0:0]QRST_QPLLRESET_IN;
  wire RATE_CPLLLOCK;
  wire RATE_DRP_DONE;
  wire RATE_PHYSTATUS;
  wire RATE_QPLLLOCK;
  wire RATE_RESETOVRD_DONE;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RATE_TXSYNC_DONE;
  wire RST_CPLLRESET;
  wire RST_DRP_START;
  wire RST_DRP_X16;
  wire RST_DRP_X16X20_MODE;
  wire [6:0]RST_RATE_IDLE;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RXSYNC_DONE;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXSYNC_START;
  wire USER_PCLK_SEL;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire cplllock_reg1;
  wire \cplllock_reg1_reg[6] ;
  wire \cplllock_reg1_reg[6]_0 ;
  wire cplllock_reg2;
  wire cpllpd_i_1__5_n_0;
  wire cpllreset_i_1__6_n_0;
  wire drp_done_reg1;
  wire drp_done_reg2;
  wire drp_start_i_1__5_n_0;
  wire drp_x16_i_1__5_n_0;
  wire drp_x16x20_mode_i_1__5_n_0;
  wire [4:0]fsm;
  wire fsm1;
  wire \fsm[0]_i_10__5_n_0 ;
  wire \fsm[0]_i_11__5_n_0 ;
  wire \fsm[0]_i_12__5_n_0 ;
  wire \fsm[0]_i_3__11_n_0 ;
  wire \fsm[0]_i_4__5_n_0 ;
  wire \fsm[0]_i_5__5_n_0 ;
  wire \fsm[0]_i_6__5_n_0 ;
  wire \fsm[0]_i_7__5_n_0 ;
  wire \fsm[0]_i_8__5_n_0 ;
  wire \fsm[0]_i_9__5_n_0 ;
  wire \fsm[1]_i_4__5_n_0 ;
  wire \fsm[1]_i_5__5_n_0 ;
  wire \fsm[1]_i_6__5_n_0 ;
  wire \fsm[1]_i_7__5_n_0 ;
  wire \fsm[1]_i_8__5_n_0 ;
  wire \fsm[1]_i_9__5_n_0 ;
  wire \fsm[2]_i_2__5_n_0 ;
  wire \fsm[2]_i_3__5_n_0 ;
  wire \fsm[2]_i_4__5_n_0 ;
  wire \fsm[2]_i_5__5_n_0 ;
  wire \fsm[3]_i_2__5_n_0 ;
  wire \fsm[3]_i_3__5_n_0 ;
  wire \fsm[3]_i_4__5_n_0 ;
  wire \fsm[3]_i_5__5_n_0 ;
  wire \fsm[3]_i_8__5_n_0 ;
  wire \fsm[3]_i_9__5_n_0 ;
  wire \fsm[4]_i_2__5_n_0 ;
  wire \fsm[4]_i_3__5_n_0 ;
  wire \fsm_reg[0]_i_2__5_n_0 ;
  wire \fsm_reg[1]_i_2__5_n_0 ;
  wire \fsm_reg[1]_i_3__5_n_0 ;
  wire gen3_exit;
  wire gen3_exit_i_1__5_n_0;
  wire gen3_exit_i_2__5_n_0;
  wire gen3_i_1__5_n_0;
  wire gen3_i_2__5_n_0;
  wire gen3_reg1_i_2_n_0;
  wire gen3_reg1_reg;
  wire [5:0]gen3_reg_0;
  wire [0:0]gen3_reg_1;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire [1:0]out1;
  wire p_0_in24_in;
  wire p_0_in26_in;
  wire p_0_in28_in;
  wire p_0_in36_in;
  wire p_0_in38_in;
  wire p_0_in7_in;
  wire [3:0]p_0_in__0;
  wire p_1_in8_in;
  wire pclk_sel_i_1__6_n_0;
  wire pclk_sel_i_2__5_n_0;
  wire pclk_sel_reg_0;
  wire phystatus_i_1__5_n_0;
  wire phystatus_reg1;
  wire phystatus_reg2;
  wire phystatus_reg_n_0;
  wire pipe_rate_idle;
  wire pipe_rate_idle_INST_0_i_1_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire pll_lock;
  wire qplllock_reg1;
  wire qplllock_reg2;
  wire qpllpd;
  wire qpllpd_i_1__6_n_0;
  wire qpllreset;
  wire qpllreset_i_1__6_n_0;
  wire [0:0]rate_gen3;
  wire [0:0]\rate_idle_reg1_reg[6] ;
  wire [1:0]rate_in_reg1;
  wire [1:0]rate_in_reg2;
  wire \rate_out[0]_i_1__5_n_0 ;
  wire \rate_out[1]_i_1__5_n_0 ;
  wire \rate_out[2]_i_1__5_n_0 ;
  wire \rate_out[2]_i_2__5_n_0 ;
  wire \rate_out[2]_i_3__5_n_0 ;
  wire ratedone_i_1__5_n_0;
  wire ratedone_reg_n_0;
  wire \resetovrd_disble.reset_reg[4] ;
  wire resetovrd_done_reg1;
  wire resetovrd_done_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire rxpmaresetdone_reg1;
  wire rxpmaresetdone_reg2;
  wire rxratedone_i_1__5_n_0;
  wire rxratedone_reg1;
  wire rxratedone_reg2;
  wire rxratedone_reg_n_0;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxsync_done_reg1;
  wire rxsync_done_reg2;
  wire \sysclksel[0]_i_1__5_n_0 ;
  wire \sysclksel[0]_i_2__5_n_0 ;
  wire \sysclksel[0]_i_3__5_n_0 ;
  wire \sysclksel[1]_i_1__5_n_0 ;
  wire \txdata_wait_cnt[3]_i_2__5_n_0 ;
  wire [3:0]txdata_wait_cnt_reg__0;
  wire txpmareset_i_1__5_n_0;
  wire txpmareset_i_2__5_n_0;
  wire txratedone_i_1__5_n_0;
  wire txratedone_i_2__5_n_0;
  wire txratedone_reg1;
  wire txratedone_reg2;
  wire txratedone_reg_n_0;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire txsync_done_reg1;
  wire txsync_done_reg2;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_CPLLLOCK),
        .Q(cplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cplllock_reg1),
        .Q(cplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllpd_i_1__5
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(p_0_in38_in),
        .O(cpllpd_i_1__5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT5 #(
    .INIT(32'h80000084)) 
    cpllpd_i_2__5
       (.I0(Q[4]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(qpllpd));
  FDRE #(
    .INIT(1'b0)) 
    cpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllpd_i_1__5_n_0),
        .Q(p_0_in38_in),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllreset_i_1__6
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(p_0_in36_in),
        .O(cpllreset_i_1__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT5 #(
    .INIT(32'h81000002)) 
    cpllreset_i_2__5
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(qpllreset));
  FDRE #(
    .INIT(1'b0)) 
    cpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllreset_i_1__6_n_0),
        .Q(p_0_in36_in),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_DRP_DONE),
        .Q(drp_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT5 #(
    .INIT(32'h08200108)) 
    drp_start_i_1__5
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(Q[1]),
        .O(drp_start_i_1__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_start_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_start_i_1__5_n_0),
        .Q(p_0_in24_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT5 #(
    .INIT(32'h20020006)) 
    drp_x16_i_1__5
       (.I0(Q[2]),
        .I1(Q[4]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[0]),
        .O(drp_x16_i_1__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16_i_1__5_n_0),
        .Q(p_0_in26_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT5 #(
    .INIT(32'h20001584)) 
    drp_x16x20_mode_i_1__5
       (.I0(Q[1]),
        .I1(Q[4]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(drp_x16x20_mode_i_1__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16x20_mode_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16x20_mode_i_1__5_n_0),
        .Q(p_0_in28_in),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[0]_i_10__5 
       (.I0(txdata_wait_cnt_reg__0[3]),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[0]),
        .I3(txdata_wait_cnt_reg__0[1]),
        .O(\fsm[0]_i_10__5_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000F404)) 
    \fsm[0]_i_11__5 
       (.I0(rxpmaresetdone_reg2),
        .I1(mmcm_lock_reg2),
        .I2(Q[0]),
        .I3(drp_done_reg2),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\fsm[0]_i_11__5_n_0 ));
  LUT6 #(
    .INIT(64'h4F4F737F4343404C)) 
    \fsm[0]_i_12__5 
       (.I0(resetovrd_done_reg2),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(rxpmaresetdone_reg2),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[0]_i_12__5_n_0 ));
  LUT6 #(
    .INIT(64'hBBB88888BBB8BBB8)) 
    \fsm[0]_i_1__11 
       (.I0(\fsm_reg[0]_i_2__5_n_0 ),
        .I1(Q[4]),
        .I2(\fsm[0]_i_3__11_n_0 ),
        .I3(Q[3]),
        .I4(\fsm[0]_i_4__5_n_0 ),
        .I5(\fsm[0]_i_5__5_n_0 ),
        .O(fsm[0]));
  LUT6 #(
    .INIT(64'h0344FF440344FF77)) 
    \fsm[0]_i_3__11 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(pll_lock),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\fsm[3]_i_9__5_n_0 ),
        .O(\fsm[0]_i_3__11_n_0 ));
  LUT6 #(
    .INIT(64'hF0000000F800F000)) 
    \fsm[0]_i_4__5 
       (.I0(pll_lock),
        .I1(rst_idle_reg2),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(drp_done_reg2),
        .I5(Q[0]),
        .O(\fsm[0]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000CCC8C0C8)) 
    \fsm[0]_i_5__5 
       (.I0(\fsm[0]_i_8__5_n_0 ),
        .I1(Q[3]),
        .I2(\fsm[0]_i_9__5_n_0 ),
        .I3(Q[0]),
        .I4(\fsm[0]_i_10__5_n_0 ),
        .I5(\fsm[0]_i_11__5_n_0 ),
        .O(\fsm[0]_i_5__5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0040)) 
    \fsm[0]_i_6__5 
       (.I0(fsm1),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(\fsm[0]_i_12__5_n_0 ),
        .O(\fsm[0]_i_6__5_n_0 ));
  LUT5 #(
    .INIT(32'h03880333)) 
    \fsm[0]_i_7__5 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[0]_i_7__5_n_0 ));
  LUT5 #(
    .INIT(32'h77770777)) 
    \fsm[0]_i_8__5 
       (.I0(p_0_in7_in),
        .I1(p_1_in8_in),
        .I2(rxresetdone_reg2),
        .I3(txresetdone_reg2),
        .I4(phystatus_reg2),
        .O(\fsm[0]_i_8__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \fsm[0]_i_9__5 
       (.I0(Q[1]),
        .I1(Q[2]),
        .O(\fsm[0]_i_9__5_n_0 ));
  LUT5 #(
    .INIT(32'h30BBFC00)) 
    \fsm[1]_i_4__5 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(\fsm[1]_i_8__5_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'hCC88300000BB3000)) 
    \fsm[1]_i_5__5 
       (.I0(\fsm[0]_i_10__5_n_0 ),
        .I1(Q[2]),
        .I2(\fsm[1]_i_9__5_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_5__5_n_0 ));
  LUT5 #(
    .INIT(32'h70F040F0)) 
    \fsm[1]_i_6__5 
       (.I0(resetovrd_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(drp_done_reg2),
        .O(\fsm[1]_i_6__5_n_0 ));
  LUT5 #(
    .INIT(32'h03777700)) 
    \fsm[1]_i_7__5 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_7__5_n_0 ));
  LUT6 #(
    .INIT(64'h53F5FFFFFFFFFFFF)) 
    \fsm[1]_i_8__5 
       (.I0(cplllock_reg2),
        .I1(qplllock_reg2),
        .I2(rate_in_reg2[0]),
        .I3(rate_in_reg2[1]),
        .I4(rst_idle_reg2),
        .I5(Q[0]),
        .O(\fsm[1]_i_8__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF4575FFFFFFFF)) 
    \fsm[1]_i_9__5 
       (.I0(cplllock_reg2),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .I3(qplllock_reg2),
        .I4(rst_idle_reg2),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_9__5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fsm[2]_i_1__11 
       (.I0(\fsm[2]_i_2__5_n_0 ),
        .I1(\fsm[2]_i_3__5_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[2]_i_4__5_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[2]_i_5__5_n_0 ),
        .O(fsm[2]));
  LUT5 #(
    .INIT(32'h3C0C4040)) 
    \fsm[2]_i_2__5 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_done_reg2),
        .I4(Q[0]),
        .O(\fsm[2]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h13CCD3CC1FCCDFCC)) 
    \fsm[2]_i_3__5 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(resetovrd_done_reg2),
        .I5(fsm1),
        .O(\fsm[2]_i_3__5_n_0 ));
  LUT4 #(
    .INIT(16'hBC0C)) 
    \fsm[2]_i_4__5 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\fsm[2]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'h4A4A4A4AAAAFAAAA)) 
    \fsm[2]_i_5__5 
       (.I0(Q[2]),
        .I1(pll_lock),
        .I2(Q[1]),
        .I3(\fsm[3]_i_9__5_n_0 ),
        .I4(\fsm[3]_i_8__5_n_0 ),
        .I5(Q[0]),
        .O(\fsm[2]_i_5__5_n_0 ));
  LUT6 #(
    .INIT(64'hEFE0EFEFEFE0E0E0)) 
    \fsm[3]_i_1__5 
       (.I0(\fsm[3]_i_2__5_n_0 ),
        .I1(\fsm[3]_i_3__5_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[3]_i_4__5_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[3]_i_5__5_n_0 ),
        .O(fsm[3]));
  LUT5 #(
    .INIT(32'h22AA2A22)) 
    \fsm[3]_i_2__5 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(rxsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[3]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h3020002000000000)) 
    \fsm[3]_i_3__5 
       (.I0(fsm1),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(resetovrd_done_reg2),
        .I5(Q[0]),
        .O(\fsm[3]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hF545F555FFFFFFFF)) 
    \fsm[3]_i_4__5 
       (.I0(Q[2]),
        .I1(rst_idle_reg2),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(pll_lock),
        .I5(Q[1]),
        .O(\fsm[3]_i_4__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT5 #(
    .INIT(32'h80808180)) 
    \fsm[3]_i_5__5 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\fsm[3]_i_8__5_n_0 ),
        .I4(\fsm[3]_i_9__5_n_0 ),
        .O(\fsm[3]_i_5__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8F8FFF8)) 
    \fsm[3]_i_6__5 
       (.I0(p_1_in8_in),
        .I1(p_0_in7_in),
        .I2(ratedone_reg_n_0),
        .I3(rate_in_reg2[1]),
        .I4(rate_in_reg2[0]),
        .I5(gen3_exit),
        .O(fsm1));
  LUT4 #(
    .INIT(16'hFB08)) 
    \fsm[3]_i_7__5 
       (.I0(qplllock_reg2),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(cplllock_reg2),
        .O(pll_lock));
  LUT4 #(
    .INIT(16'hB0BB)) 
    \fsm[3]_i_8__5 
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg1[0]),
        .I3(rate_in_reg1[1]),
        .O(\fsm[3]_i_8__5_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \fsm[3]_i_9__5 
       (.I0(rate_in_reg1[0]),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg1[1]),
        .I3(rate_in_reg2[1]),
        .O(\fsm[3]_i_9__5_n_0 ));
  LUT5 #(
    .INIT(32'h08880000)) 
    \fsm[4]_i_2__5 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\fsm[4]_i_2__5_n_0 ));
  LUT5 #(
    .INIT(32'h5F75FFFF)) 
    \fsm[4]_i_3__5 
       (.I0(Q[2]),
        .I1(rxsync_done_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\fsm[4]_i_3__5_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  MUXF7 \fsm_reg[0]_i_2__5 
       (.I0(\fsm[0]_i_6__5_n_0 ),
        .I1(\fsm[0]_i_7__5_n_0 ),
        .O(\fsm_reg[0]_i_2__5_n_0 ),
        .S(Q[3]));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .S(RST_CPLLRESET));
  MUXF8 \fsm_reg[1]_i_1__5 
       (.I0(\fsm_reg[1]_i_2__5_n_0 ),
        .I1(\fsm_reg[1]_i_3__5_n_0 ),
        .O(fsm[1]),
        .S(Q[4]));
  MUXF7 \fsm_reg[1]_i_2__5 
       (.I0(\fsm[1]_i_4__5_n_0 ),
        .I1(\fsm[1]_i_5__5_n_0 ),
        .O(\fsm_reg[1]_i_2__5_n_0 ),
        .S(Q[3]));
  MUXF7 \fsm_reg[1]_i_3__5 
       (.I0(\fsm[1]_i_6__5_n_0 ),
        .I1(\fsm[1]_i_7__5_n_0 ),
        .O(\fsm_reg[1]_i_3__5_n_0 ),
        .S(Q[3]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  MUXF7 \fsm_reg[4]_i_1__5 
       (.I0(\fsm[4]_i_2__5_n_0 ),
        .I1(\fsm[4]_i_3__5_n_0 ),
        .O(fsm[4]),
        .S(Q[4]));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_exit_i_1__5
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_exit_i_2__5_n_0),
        .I4(gen3_exit),
        .O(gen3_exit_i_1__5_n_0));
  LUT6 #(
    .INIT(64'hC000000000000001)) 
    gen3_exit_i_2__5
       (.I0(\fsm[3]_i_9__5_n_0 ),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(gen3_exit_i_2__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_exit_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_exit_i_1__5_n_0),
        .Q(gen3_exit),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_i_1__5
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_i_2__5_n_0),
        .I4(rate_gen3),
        .O(gen3_i_1__5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT5 #(
    .INIT(32'h80000008)) 
    gen3_i_2__5
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[1]),
        .O(gen3_i_2__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_i_1__5_n_0),
        .Q(rate_gen3),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h80)) 
    gen3_reg1_i_1
       (.I0(gen3_reg1_i_2_n_0),
        .I1(gen3_reg_0[3]),
        .I2(gen3_reg_0[4]),
        .O(gen3_reg1_reg));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    gen3_reg1_i_2
       (.I0(rate_gen3),
        .I1(gen3_reg_0[5]),
        .I2(gen3_reg_0[0]),
        .I3(gen3_reg_1),
        .I4(gen3_reg_0[2]),
        .I5(gen3_reg_0[1]),
        .O(gen3_reg1_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_6__0 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[6]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_7__5 
       (.I0(rate_gen3),
        .O(\cplllock_reg1_reg[6] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h06FF0600)) 
    pclk_sel_i_1__6
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(pclk_sel_i_2__5_n_0),
        .I4(USER_PCLK_SEL),
        .O(pclk_sel_i_1__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT5 #(
    .INIT(32'h80040800)) 
    pclk_sel_i_2__5
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(pclk_sel_i_2__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(pclk_sel_i_1__6_n_0),
        .Q(USER_PCLK_SEL),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    phystatus_i_1__5
       (.I0(phystatus_reg2),
        .I1(txratedone_i_2__5_n_0),
        .I2(phystatus_reg_n_0),
        .O(phystatus_i_1__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    phystatus_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_i_1__5_n_0),
        .Q(phystatus_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_PHYSTATUS),
        .Q(phystatus_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_reg1),
        .Q(phystatus_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h80)) 
    pipe_rate_idle_INST_0
       (.I0(pipe_rate_idle_INST_0_i_1_n_0),
        .I1(RST_RATE_IDLE[4]),
        .I2(RST_RATE_IDLE[5]),
        .O(pipe_rate_idle));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    pipe_rate_idle_INST_0_i_1
       (.I0(\rate_idle_reg1_reg[6] ),
        .I1(RST_RATE_IDLE[6]),
        .I2(RST_RATE_IDLE[1]),
        .I3(RST_RATE_IDLE[0]),
        .I4(RST_RATE_IDLE[3]),
        .I5(RST_RATE_IDLE[2]),
        .O(pipe_rate_idle_INST_0_i_1_n_0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_QPLLLOCK),
        .Q(qplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllpd_i_1__6
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(QRST_QPLLPD_IN),
        .O(qpllpd_i_1__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllpd_i_1__6_n_0),
        .Q(QRST_QPLLPD_IN),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllreset_i_1__6
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(QRST_QPLLRESET_IN),
        .O(qpllreset_i_1__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllreset_i_1__6_n_0),
        .Q(QRST_QPLLRESET_IN),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    rate_done_reg1_i_1__5
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(USER_RATE_DONE));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \rate_idle_reg1[6]_i_1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(\rate_idle_reg1_reg[6] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_in_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_in_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[0]),
        .Q(rate_in_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[1]),
        .Q(rate_in_reg2[1]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    \rate_out[0]_i_1__5 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .I2(Q[1]),
        .I3(\rate_out[2]_i_2__5_n_0 ),
        .I4(RXRATE[0]),
        .O(\rate_out[0]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[1]_i_1__5 
       (.I0(\rate_out[2]_i_2__5_n_0 ),
        .I1(RXRATE[1]),
        .O(\rate_out[1]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[2]_i_1__5 
       (.I0(\rate_out[2]_i_2__5_n_0 ),
        .I1(RXRATE[2]),
        .O(\rate_out[2]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h8000002080000220)) 
    \rate_out[2]_i_2__5 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\rate_out[2]_i_3__5_n_0 ),
        .O(\rate_out[2]_i_2__5_n_0 ));
  LUT3 #(
    .INIT(8'h45)) 
    \rate_out[2]_i_3__5 
       (.I0(gen3_exit),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .O(\rate_out[2]_i_3__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[0]_i_1__5_n_0 ),
        .Q(RXRATE[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[1]_i_1__5_n_0 ),
        .Q(RXRATE[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[2]_i_1__5_n_0 ),
        .Q(RXRATE[2]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT5 #(
    .INIT(32'h00808000)) 
    rate_rxsync_reg1_i_1__5
       (.I0(Q[3]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(USER_RATE_RXSYNC));
  LUT5 #(
    .INIT(32'hFF008000)) 
    ratedone_i_1__5
       (.I0(rxratedone_reg_n_0),
        .I1(txratedone_reg_n_0),
        .I2(phystatus_reg_n_0),
        .I3(txratedone_i_2__5_n_0),
        .I4(ratedone_reg_n_0),
        .O(ratedone_i_1__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(ratedone_i_1__5_n_0),
        .Q(ratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RESETOVRD_DONE),
        .Q(resetovrd_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(resetovrd_done_reg1),
        .Q(resetovrd_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    resetovrd_start_reg1_i_1__5
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[4]),
        .I4(Q[2]),
        .O(USER_RESETOVRD_START));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(out1[1]),
        .Q(rst_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1),
        .Q(rxpmaresetdone_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    rxratedone_i_1__5
       (.I0(rxratedone_reg2),
        .I1(txratedone_i_2__5_n_0),
        .I2(rxratedone_reg_n_0),
        .O(rxratedone_i_1__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_i_1__5_n_0),
        .Q(rxratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RXRATEDONE),
        .Q(rxratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_reg1),
        .Q(rxratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONE),
        .Q(rxsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxsync_done_reg1),
        .Q(rxsync_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    rxsync_start_reg1_i_1__5
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(SYNC_RXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    start_reg1_i_1__5
       (.I0(p_0_in24_in),
        .I1(RST_DRP_START),
        .O(DRP_START025_out));
  LUT6 #(
    .INIT(64'hFFFF3EFF00000200)) 
    \sysclksel[0]_i_1__5 
       (.I0(\sysclksel[0]_i_2__5_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(\sysclksel[0]_i_3__5_n_0 ),
        .I5(RXSYSCLKSEL[0]),
        .O(\sysclksel[0]_i_1__5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \sysclksel[0]_i_2__5 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .O(\sysclksel[0]_i_2__5_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \sysclksel[0]_i_3__5 
       (.I0(Q[2]),
        .I1(Q[1]),
        .O(\sysclksel[0]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'h6FFFFFFF00000000)) 
    \sysclksel[1]_i_1__5 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(RXSYSCLKSEL[1]),
        .O(\sysclksel[1]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[0]_i_1__5_n_0 ),
        .Q(RXSYSCLKSEL[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[1]_i_1__5_n_0 ),
        .Q(RXSYSCLKSEL[1]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT5 #(
    .INIT(32'h80AA00AA)) 
    \txdata_wait_cnt[0]_i_1__5 
       (.I0(\txdata_wait_cnt[3]_i_2__5_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT5 #(
    .INIT(32'hA8282828)) 
    \txdata_wait_cnt[1]_i_1__5 
       (.I0(\txdata_wait_cnt[3]_i_2__5_n_0 ),
        .I1(txdata_wait_cnt_reg__0[0]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[3]),
        .I4(txdata_wait_cnt_reg__0[2]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT5 #(
    .INIT(32'h8AA0A0A0)) 
    \txdata_wait_cnt[2]_i_1__5 
       (.I0(\txdata_wait_cnt[3]_i_2__5_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \txdata_wait_cnt[3]_i_1__5 
       (.I0(\txdata_wait_cnt[3]_i_2__5_n_0 ),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \txdata_wait_cnt[3]_i_2__5 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\txdata_wait_cnt[3]_i_2__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(txdata_wait_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(txdata_wait_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(txdata_wait_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(txdata_wait_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h5504FFFF55040000)) 
    txpmareset_i_1__5
       (.I0(Q[3]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(gen3_exit),
        .I4(txpmareset_i_2__5_n_0),
        .I5(GT_TXPMARESET035_out),
        .O(txpmareset_i_1__5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT5 #(
    .INIT(32'h82000400)) 
    txpmareset_i_2__5
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(txpmareset_i_2__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txpmareset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txpmareset_i_1__5_n_0),
        .Q(GT_TXPMARESET035_out),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    txratedone_i_1__5
       (.I0(txratedone_reg2),
        .I1(txratedone_i_2__5_n_0),
        .I2(txratedone_reg_n_0),
        .O(txratedone_i_1__5_n_0));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    txratedone_i_2__5
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(RST_CPLLRESET),
        .O(txratedone_i_2__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_i_1__5_n_0),
        .Q(txratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXRATEDONE),
        .Q(txratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_reg1),
        .Q(txratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXSYNC_DONE),
        .Q(txsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txsync_done_reg1),
        .Q(txsync_done_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAA)) 
    txsync_start_reg1_i_1__5
       (.I0(out1[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(SYNC_TXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    x16_reg1_i_1__5
       (.I0(p_0_in26_in),
        .I1(RST_DRP_X16),
        .O(DRP_X16027_out));
  LUT2 #(
    .INIT(4'hE)) 
    x16x20_mode_reg1_i_1__5
       (.I0(p_0_in28_in),
        .I1(RST_DRP_X16X20_MODE),
        .O(DRP_X16X20_MODE029_out));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_rate" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_69
   (Q,
    USER_RESETOVRD_START,
    RXSYSCLKSEL,
    SYNC_TXSYNC_START,
    DRP_X16X20_MODE0136_out,
    DRP_X16010_out,
    DRP_START08_out,
    \cplllock_reg1_reg[7] ,
    rate_gen3_reg1_reg,
    \cplllock_reg1_reg[7]_0 ,
    RXRATE,
    USER_RATE_DONE,
    USER_RATE_RXSYNC,
    SYNC_RXSYNC_START,
    SYNC_RATE_IDLE,
    GT_TXPMARESET017_out,
    USER_PCLK_SEL,
    QRST_QPLLRESET_IN,
    p_0_in18_in,
    QRST_QPLLPD_IN,
    p_0_in20_in,
    out1,
    RST_DRP_X16X20_MODE,
    RST_DRP_X16,
    RST_DRP_START,
    RST_CPLLRESET,
    pclk_sel_reg_0,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    RATE_CPLLLOCK,
    qpllpd_reg_0,
    RATE_DRP_DONE,
    \resetovrd_disble.reset_reg[4] ,
    RATE_PHYSTATUS,
    USER_TXRESETDONE,
    USER_RXRESETDONE,
    RATE_TXRATEDONE,
    RATE_RXRATEDONE,
    RATE_RESETOVRD_DONE,
    RATE_TXSYNC_DONE,
    SYNC_RXSYNC_DONE,
    p_1_in8_in,
    p_0_in7_in);
  output [4:0]Q;
  output USER_RESETOVRD_START;
  output [1:0]RXSYSCLKSEL;
  output SYNC_TXSYNC_START;
  output DRP_X16X20_MODE0136_out;
  output DRP_X16010_out;
  output DRP_START08_out;
  output \cplllock_reg1_reg[7] ;
  output [0:0]rate_gen3_reg1_reg;
  output \cplllock_reg1_reg[7]_0 ;
  output [2:0]RXRATE;
  output USER_RATE_DONE;
  output USER_RATE_RXSYNC;
  output SYNC_RXSYNC_START;
  output SYNC_RATE_IDLE;
  output GT_TXPMARESET017_out;
  output USER_PCLK_SEL;
  output [0:0]QRST_QPLLRESET_IN;
  output p_0_in18_in;
  output [0:0]QRST_QPLLPD_IN;
  output p_0_in20_in;
  input [1:0]out1;
  input RST_DRP_X16X20_MODE;
  input RST_DRP_X16;
  input RST_DRP_START;
  input RST_CPLLRESET;
  input pclk_sel_reg_0;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input RATE_CPLLLOCK;
  input qpllpd_reg_0;
  input RATE_DRP_DONE;
  input \resetovrd_disble.reset_reg[4] ;
  input RATE_PHYSTATUS;
  input USER_TXRESETDONE;
  input USER_RXRESETDONE;
  input RATE_TXRATEDONE;
  input RATE_RXRATEDONE;
  input RATE_RESETOVRD_DONE;
  input RATE_TXSYNC_DONE;
  input SYNC_RXSYNC_DONE;
  input p_1_in8_in;
  input p_0_in7_in;

  wire DRP_START08_out;
  wire DRP_X16010_out;
  wire DRP_X16X20_MODE0136_out;
  wire GT_TXPMARESET017_out;
  wire [4:0]Q;
  wire [0:0]QRST_QPLLPD_IN;
  wire [0:0]QRST_QPLLRESET_IN;
  wire RATE_CPLLLOCK;
  wire RATE_DRP_DONE;
  wire RATE_PHYSTATUS;
  wire RATE_RESETOVRD_DONE;
  wire RATE_RXRATEDONE;
  wire RATE_TXRATEDONE;
  wire RATE_TXSYNC_DONE;
  wire RST_CPLLRESET;
  wire RST_DRP_START;
  wire RST_DRP_X16;
  wire RST_DRP_X16X20_MODE;
  wire [2:0]RXRATE;
  wire [1:0]RXSYSCLKSEL;
  wire SYNC_RATE_IDLE;
  wire SYNC_RXSYNC_DONE;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXSYNC_START;
  wire USER_PCLK_SEL;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire cplllock_reg1;
  wire \cplllock_reg1_reg[7] ;
  wire \cplllock_reg1_reg[7]_0 ;
  wire cplllock_reg2;
  wire cpllpd_i_1__6_n_0;
  wire cpllreset_i_1__7_n_0;
  wire drp_done_reg1;
  wire drp_done_reg2;
  wire drp_start_i_1__6_n_0;
  wire drp_x16_i_1__6_n_0;
  wire drp_x16x20_mode_i_1__6_n_0;
  wire [4:0]fsm;
  wire fsm1;
  wire \fsm[0]_i_10__6_n_0 ;
  wire \fsm[0]_i_11__6_n_0 ;
  wire \fsm[0]_i_12__6_n_0 ;
  wire \fsm[0]_i_3__13_n_0 ;
  wire \fsm[0]_i_4__6_n_0 ;
  wire \fsm[0]_i_5__6_n_0 ;
  wire \fsm[0]_i_6__6_n_0 ;
  wire \fsm[0]_i_7__6_n_0 ;
  wire \fsm[0]_i_8__6_n_0 ;
  wire \fsm[0]_i_9__6_n_0 ;
  wire \fsm[1]_i_4__6_n_0 ;
  wire \fsm[1]_i_5__6_n_0 ;
  wire \fsm[1]_i_6__6_n_0 ;
  wire \fsm[1]_i_7__6_n_0 ;
  wire \fsm[1]_i_8__6_n_0 ;
  wire \fsm[1]_i_9__6_n_0 ;
  wire \fsm[2]_i_2__6_n_0 ;
  wire \fsm[2]_i_3__6_n_0 ;
  wire \fsm[2]_i_4__6_n_0 ;
  wire \fsm[2]_i_5__6_n_0 ;
  wire \fsm[3]_i_2__6_n_0 ;
  wire \fsm[3]_i_3__6_n_0 ;
  wire \fsm[3]_i_4__6_n_0 ;
  wire \fsm[3]_i_5__6_n_0 ;
  wire \fsm[3]_i_8__6_n_0 ;
  wire \fsm[3]_i_9__6_n_0 ;
  wire \fsm[4]_i_2__6_n_0 ;
  wire \fsm[4]_i_3__6_n_0 ;
  wire \fsm_reg[0]_i_2__6_n_0 ;
  wire \fsm_reg[1]_i_2__6_n_0 ;
  wire \fsm_reg[1]_i_3__6_n_0 ;
  wire gen3_exit;
  wire gen3_exit_i_1__6_n_0;
  wire gen3_exit_i_2__6_n_0;
  wire gen3_i_1__6_n_0;
  wire gen3_i_2__6_n_0;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire [1:0]out1;
  wire p_0_in135_in;
  wire p_0_in18_in;
  wire p_0_in20_in;
  wire p_0_in7_in;
  wire p_0_in7_in__0;
  wire p_0_in9_in;
  wire [3:0]p_0_in__0;
  wire p_1_in8_in;
  wire pclk_sel_i_1__7_n_0;
  wire pclk_sel_i_2__6_n_0;
  wire pclk_sel_reg_0;
  wire phystatus_i_1__6_n_0;
  wire phystatus_reg1;
  wire phystatus_reg2;
  wire phystatus_reg_n_0;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire pll_lock;
  wire qplllock_reg1;
  wire qplllock_reg2;
  wire qpllpd;
  wire qpllpd_i_1__7_n_0;
  wire qpllpd_reg_0;
  wire qpllreset;
  wire qpllreset_i_1__7_n_0;
  wire [0:0]rate_gen3_reg1_reg;
  wire [1:0]rate_in_reg1;
  wire [1:0]rate_in_reg2;
  wire \rate_out[0]_i_1__6_n_0 ;
  wire \rate_out[1]_i_1__6_n_0 ;
  wire \rate_out[2]_i_1__6_n_0 ;
  wire \rate_out[2]_i_2__6_n_0 ;
  wire \rate_out[2]_i_3__6_n_0 ;
  wire ratedone_i_1__6_n_0;
  wire ratedone_reg_n_0;
  wire \resetovrd_disble.reset_reg[4] ;
  wire resetovrd_done_reg1;
  wire resetovrd_done_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire rxpmaresetdone_reg1;
  wire rxpmaresetdone_reg2;
  wire rxratedone_i_1__6_n_0;
  wire rxratedone_reg1;
  wire rxratedone_reg2;
  wire rxratedone_reg_n_0;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxsync_done_reg1;
  wire rxsync_done_reg2;
  wire \sysclksel[0]_i_1__6_n_0 ;
  wire \sysclksel[0]_i_2__6_n_0 ;
  wire \sysclksel[0]_i_3__6_n_0 ;
  wire \sysclksel[1]_i_1__6_n_0 ;
  wire \txdata_wait_cnt[3]_i_2__6_n_0 ;
  wire [3:0]txdata_wait_cnt_reg__0;
  wire txpmareset_i_1__6_n_0;
  wire txpmareset_i_2__6_n_0;
  wire txratedone_i_1__6_n_0;
  wire txratedone_i_2__6_n_0;
  wire txratedone_reg1;
  wire txratedone_reg2;
  wire txratedone_reg_n_0;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire txsync_done_reg1;
  wire txsync_done_reg2;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_CPLLLOCK),
        .Q(cplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE cplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cplllock_reg1),
        .Q(cplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllpd_i_1__6
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(p_0_in20_in),
        .O(cpllpd_i_1__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT5 #(
    .INIT(32'h80000084)) 
    cpllpd_i_2__6
       (.I0(Q[4]),
        .I1(Q[0]),
        .I2(Q[3]),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(qpllpd));
  FDRE #(
    .INIT(1'b0)) 
    cpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllpd_i_1__6_n_0),
        .Q(p_0_in20_in),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
    cpllreset_i_1__7
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(p_0_in18_in),
        .O(cpllreset_i_1__7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT5 #(
    .INIT(32'h81000002)) 
    cpllreset_i_2__6
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(qpllreset));
  FDRE #(
    .INIT(1'b0)) 
    cpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(cpllreset_i_1__7_n_0),
        .Q(p_0_in18_in),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_DRP_DONE),
        .Q(drp_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE drp_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_done_reg1),
        .Q(drp_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT5 #(
    .INIT(32'h08200108)) 
    drp_start_i_1__6
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(Q[1]),
        .O(drp_start_i_1__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_start_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_start_i_1__6_n_0),
        .Q(p_0_in7_in__0),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT5 #(
    .INIT(32'h20020006)) 
    drp_x16_i_1__6
       (.I0(Q[2]),
        .I1(Q[4]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[0]),
        .O(drp_x16_i_1__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16_i_1__6_n_0),
        .Q(p_0_in9_in),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT5 #(
    .INIT(32'h20001584)) 
    drp_x16x20_mode_i_1__6
       (.I0(Q[1]),
        .I1(Q[4]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(drp_x16x20_mode_i_1__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    drp_x16x20_mode_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(drp_x16x20_mode_i_1__6_n_0),
        .Q(p_0_in135_in),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[0]_i_10__6 
       (.I0(txdata_wait_cnt_reg__0[3]),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[0]),
        .I3(txdata_wait_cnt_reg__0[1]),
        .O(\fsm[0]_i_10__6_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000F404)) 
    \fsm[0]_i_11__6 
       (.I0(rxpmaresetdone_reg2),
        .I1(mmcm_lock_reg2),
        .I2(Q[0]),
        .I3(drp_done_reg2),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\fsm[0]_i_11__6_n_0 ));
  LUT6 #(
    .INIT(64'h4F4F737F4343404C)) 
    \fsm[0]_i_12__6 
       (.I0(resetovrd_done_reg2),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(rxpmaresetdone_reg2),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[0]_i_12__6_n_0 ));
  LUT6 #(
    .INIT(64'hBBB88888BBB8BBB8)) 
    \fsm[0]_i_1__13 
       (.I0(\fsm_reg[0]_i_2__6_n_0 ),
        .I1(Q[4]),
        .I2(\fsm[0]_i_3__13_n_0 ),
        .I3(Q[3]),
        .I4(\fsm[0]_i_4__6_n_0 ),
        .I5(\fsm[0]_i_5__6_n_0 ),
        .O(fsm[0]));
  LUT6 #(
    .INIT(64'h0344FF440344FF77)) 
    \fsm[0]_i_3__13 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(pll_lock),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\fsm[3]_i_9__6_n_0 ),
        .O(\fsm[0]_i_3__13_n_0 ));
  LUT6 #(
    .INIT(64'hF0000000F800F000)) 
    \fsm[0]_i_4__6 
       (.I0(pll_lock),
        .I1(rst_idle_reg2),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(drp_done_reg2),
        .I5(Q[0]),
        .O(\fsm[0]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000CCC8C0C8)) 
    \fsm[0]_i_5__6 
       (.I0(\fsm[0]_i_8__6_n_0 ),
        .I1(Q[3]),
        .I2(\fsm[0]_i_9__6_n_0 ),
        .I3(Q[0]),
        .I4(\fsm[0]_i_10__6_n_0 ),
        .I5(\fsm[0]_i_11__6_n_0 ),
        .O(\fsm[0]_i_5__6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0040)) 
    \fsm[0]_i_6__6 
       (.I0(fsm1),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(\fsm[0]_i_12__6_n_0 ),
        .O(\fsm[0]_i_6__6_n_0 ));
  LUT5 #(
    .INIT(32'h03880333)) 
    \fsm[0]_i_7__6 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[0]_i_7__6_n_0 ));
  LUT5 #(
    .INIT(32'h77770777)) 
    \fsm[0]_i_8__6 
       (.I0(p_0_in7_in),
        .I1(p_1_in8_in),
        .I2(rxresetdone_reg2),
        .I3(txresetdone_reg2),
        .I4(phystatus_reg2),
        .O(\fsm[0]_i_8__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \fsm[0]_i_9__6 
       (.I0(Q[1]),
        .I1(Q[2]),
        .O(\fsm[0]_i_9__6_n_0 ));
  LUT5 #(
    .INIT(32'h30BBFC00)) 
    \fsm[1]_i_4__6 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(\fsm[1]_i_8__6_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'hCC88300000BB3000)) 
    \fsm[1]_i_5__6 
       (.I0(\fsm[0]_i_10__6_n_0 ),
        .I1(Q[2]),
        .I2(\fsm[1]_i_9__6_n_0 ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_5__6_n_0 ));
  LUT5 #(
    .INIT(32'h70F040F0)) 
    \fsm[1]_i_6__6 
       (.I0(resetovrd_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(drp_done_reg2),
        .O(\fsm[1]_i_6__6_n_0 ));
  LUT5 #(
    .INIT(32'h03777700)) 
    \fsm[1]_i_7__6 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(txsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[1]_i_7__6_n_0 ));
  LUT6 #(
    .INIT(64'h53F5FFFFFFFFFFFF)) 
    \fsm[1]_i_8__6 
       (.I0(cplllock_reg2),
        .I1(qplllock_reg2),
        .I2(rate_in_reg2[0]),
        .I3(rate_in_reg2[1]),
        .I4(rst_idle_reg2),
        .I5(Q[0]),
        .O(\fsm[1]_i_8__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF4575FFFFFFFF)) 
    \fsm[1]_i_9__6 
       (.I0(cplllock_reg2),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .I3(qplllock_reg2),
        .I4(rst_idle_reg2),
        .I5(drp_done_reg2),
        .O(\fsm[1]_i_9__6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fsm[2]_i_1__13 
       (.I0(\fsm[2]_i_2__6_n_0 ),
        .I1(\fsm[2]_i_3__6_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[2]_i_4__6_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[2]_i_5__6_n_0 ),
        .O(fsm[2]));
  LUT5 #(
    .INIT(32'h3C0C4040)) 
    \fsm[2]_i_2__6 
       (.I0(rxsync_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_done_reg2),
        .I4(Q[0]),
        .O(\fsm[2]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h13CCD3CC1FCCDFCC)) 
    \fsm[2]_i_3__6 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(resetovrd_done_reg2),
        .I5(fsm1),
        .O(\fsm[2]_i_3__6_n_0 ));
  LUT4 #(
    .INIT(16'hBC0C)) 
    \fsm[2]_i_4__6 
       (.I0(drp_done_reg2),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\fsm[2]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'h4A4A4A4AAAAFAAAA)) 
    \fsm[2]_i_5__6 
       (.I0(Q[2]),
        .I1(pll_lock),
        .I2(Q[1]),
        .I3(\fsm[3]_i_9__6_n_0 ),
        .I4(\fsm[3]_i_8__6_n_0 ),
        .I5(Q[0]),
        .O(\fsm[2]_i_5__6_n_0 ));
  LUT6 #(
    .INIT(64'hEFE0EFEFEFE0E0E0)) 
    \fsm[3]_i_1__6 
       (.I0(\fsm[3]_i_2__6_n_0 ),
        .I1(\fsm[3]_i_3__6_n_0 ),
        .I2(Q[4]),
        .I3(\fsm[3]_i_4__6_n_0 ),
        .I4(Q[3]),
        .I5(\fsm[3]_i_5__6_n_0 ),
        .O(fsm[3]));
  LUT5 #(
    .INIT(32'h22AA2A22)) 
    \fsm[3]_i_2__6 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(rxsync_done_reg2),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\fsm[3]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h3020002000000000)) 
    \fsm[3]_i_3__6 
       (.I0(fsm1),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(resetovrd_done_reg2),
        .I5(Q[0]),
        .O(\fsm[3]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hF545F555FFFFFFFF)) 
    \fsm[3]_i_4__6 
       (.I0(Q[2]),
        .I1(rst_idle_reg2),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(pll_lock),
        .I5(Q[1]),
        .O(\fsm[3]_i_4__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT5 #(
    .INIT(32'h80808180)) 
    \fsm[3]_i_5__6 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\fsm[3]_i_8__6_n_0 ),
        .I4(\fsm[3]_i_9__6_n_0 ),
        .O(\fsm[3]_i_5__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8F8FFF8)) 
    \fsm[3]_i_6__6 
       (.I0(p_1_in8_in),
        .I1(p_0_in7_in),
        .I2(ratedone_reg_n_0),
        .I3(rate_in_reg2[1]),
        .I4(rate_in_reg2[0]),
        .I5(gen3_exit),
        .O(fsm1));
  LUT4 #(
    .INIT(16'hFB08)) 
    \fsm[3]_i_7__6 
       (.I0(qplllock_reg2),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(cplllock_reg2),
        .O(pll_lock));
  LUT4 #(
    .INIT(16'hB0BB)) 
    \fsm[3]_i_8__6 
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg1[0]),
        .I3(rate_in_reg1[1]),
        .O(\fsm[3]_i_8__6_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \fsm[3]_i_9__6 
       (.I0(rate_in_reg1[0]),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg1[1]),
        .I3(rate_in_reg2[1]),
        .O(\fsm[3]_i_9__6_n_0 ));
  LUT5 #(
    .INIT(32'h08880000)) 
    \fsm[4]_i_2__6 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(drp_done_reg2),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\fsm[4]_i_2__6_n_0 ));
  LUT5 #(
    .INIT(32'h5F75FFFF)) 
    \fsm[4]_i_3__6 
       (.I0(Q[2]),
        .I1(rxsync_done_reg2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[3]),
        .O(\fsm[4]_i_3__6_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  MUXF7 \fsm_reg[0]_i_2__6 
       (.I0(\fsm[0]_i_6__6_n_0 ),
        .I1(\fsm[0]_i_7__6_n_0 ),
        .O(\fsm_reg[0]_i_2__6_n_0 ),
        .S(Q[3]));
  FDSE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(Q[1]),
        .S(RST_CPLLRESET));
  MUXF8 \fsm_reg[1]_i_1__6 
       (.I0(\fsm_reg[1]_i_2__6_n_0 ),
        .I1(\fsm_reg[1]_i_3__6_n_0 ),
        .O(fsm[1]),
        .S(Q[4]));
  MUXF7 \fsm_reg[1]_i_2__6 
       (.I0(\fsm[1]_i_4__6_n_0 ),
        .I1(\fsm[1]_i_5__6_n_0 ),
        .O(\fsm_reg[1]_i_2__6_n_0 ),
        .S(Q[3]));
  MUXF7 \fsm_reg[1]_i_3__6 
       (.I0(\fsm[1]_i_6__6_n_0 ),
        .I1(\fsm[1]_i_7__6_n_0 ),
        .O(\fsm_reg[1]_i_3__6_n_0 ),
        .S(Q[3]));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(fsm[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  MUXF7 \fsm_reg[4]_i_1__6 
       (.I0(\fsm[4]_i_2__6_n_0 ),
        .I1(\fsm[4]_i_3__6_n_0 ),
        .O(fsm[4]),
        .S(Q[4]));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_exit_i_1__6
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_exit_i_2__6_n_0),
        .I4(gen3_exit),
        .O(gen3_exit_i_1__6_n_0));
  LUT6 #(
    .INIT(64'hC000000000000001)) 
    gen3_exit_i_2__6
       (.I0(\fsm[3]_i_9__6_n_0 ),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(gen3_exit_i_2__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_exit_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_exit_i_1__6_n_0),
        .Q(gen3_exit),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    gen3_i_1__6
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(gen3_i_2__6_n_0),
        .I4(rate_gen3_reg1_reg),
        .O(gen3_i_1__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT5 #(
    .INIT(32'h80000008)) 
    gen3_i_2__6
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[1]),
        .O(gen3_i_2__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gen3_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(gen3_i_1__6_n_0),
        .Q(rate_gen3_reg1_reg),
        .R(RST_CPLLRESET));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_6 
       (.I0(rate_gen3_reg1_reg),
        .O(\cplllock_reg1_reg[7]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \gtx_channel.gtxe2_channel_i_i_7__6 
       (.I0(rate_gen3_reg1_reg),
        .O(\cplllock_reg1_reg[7] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h06FF0600)) 
    pclk_sel_i_1__7
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(pclk_sel_i_2__6_n_0),
        .I4(USER_PCLK_SEL),
        .O(pclk_sel_i_1__7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT5 #(
    .INIT(32'h80040800)) 
    pclk_sel_i_2__6
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(pclk_sel_i_2__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    pclk_sel_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(pclk_sel_i_1__7_n_0),
        .Q(USER_PCLK_SEL),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    phystatus_i_1__6
       (.I0(phystatus_reg2),
        .I1(txratedone_i_2__6_n_0),
        .I2(phystatus_reg_n_0),
        .O(phystatus_i_1__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    phystatus_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_i_1__6_n_0),
        .Q(phystatus_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_PHYSTATUS),
        .Q(phystatus_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE phystatus_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(phystatus_reg1),
        .Q(phystatus_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllpd_reg_0),
        .Q(qplllock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllpd_i_1__7
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllpd),
        .I5(QRST_QPLLPD_IN),
        .O(qpllpd_i_1__7_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllpd_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllpd_i_1__7_n_0),
        .Q(QRST_QPLLPD_IN),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h00B0FFFF00B00000)) 
    qpllreset_i_1__7
       (.I0(rate_in_reg2[0]),
        .I1(rate_in_reg2[1]),
        .I2(Q[4]),
        .I3(Q[2]),
        .I4(qpllreset),
        .I5(QRST_QPLLRESET_IN),
        .O(qpllreset_i_1__7_n_0));
  FDRE #(
    .INIT(1'b0)) 
    qpllreset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(qpllreset_i_1__7_n_0),
        .Q(QRST_QPLLRESET_IN),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    rate_done_reg1_i_1__6
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(USER_RATE_DONE));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \rate_idle_reg1[7]_i_1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(SYNC_RATE_IDLE));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_in_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg1_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_in_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[0]),
        .Q(rate_in_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_in_reg2_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rate_in_reg1[1]),
        .Q(rate_in_reg2[1]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    \rate_out[0]_i_1__6 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .I2(Q[1]),
        .I3(\rate_out[2]_i_2__6_n_0 ),
        .I4(RXRATE[0]),
        .O(\rate_out[0]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[1]_i_1__6 
       (.I0(\rate_out[2]_i_2__6_n_0 ),
        .I1(RXRATE[1]),
        .O(\rate_out[1]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rate_out[2]_i_1__6 
       (.I0(\rate_out[2]_i_2__6_n_0 ),
        .I1(RXRATE[2]),
        .O(\rate_out[2]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h8000002080000220)) 
    \rate_out[2]_i_2__6 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\rate_out[2]_i_3__6_n_0 ),
        .O(\rate_out[2]_i_2__6_n_0 ));
  LUT3 #(
    .INIT(8'h45)) 
    \rate_out[2]_i_3__6 
       (.I0(gen3_exit),
        .I1(rate_in_reg2[0]),
        .I2(rate_in_reg2[1]),
        .O(\rate_out[2]_i_3__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[0]_i_1__6_n_0 ),
        .Q(RXRATE[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[1]_i_1__6_n_0 ),
        .Q(RXRATE[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rate_out_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\rate_out[2]_i_1__6_n_0 ),
        .Q(RXRATE[2]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT5 #(
    .INIT(32'h00808000)) 
    rate_rxsync_reg1_i_1__6
       (.I0(Q[3]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(USER_RATE_RXSYNC));
  LUT5 #(
    .INIT(32'hFF008000)) 
    ratedone_i_1__6
       (.I0(rxratedone_reg_n_0),
        .I1(txratedone_reg_n_0),
        .I2(phystatus_reg_n_0),
        .I3(txratedone_i_2__6_n_0),
        .I4(ratedone_reg_n_0),
        .O(ratedone_i_1__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(ratedone_i_1__6_n_0),
        .Q(ratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RESETOVRD_DONE),
        .Q(resetovrd_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(resetovrd_done_reg1),
        .Q(resetovrd_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT5 #(
    .INIT(32'h04000000)) 
    resetovrd_start_reg1_i_1__6
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[4]),
        .I4(Q[2]),
        .O(USER_RESETOVRD_START));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(out1[1]),
        .Q(rst_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxpmaresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1),
        .Q(rxpmaresetdone_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    rxratedone_i_1__6
       (.I0(rxratedone_reg2),
        .I1(txratedone_i_2__6_n_0),
        .I2(rxratedone_reg_n_0),
        .O(rxratedone_i_1__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rxratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_i_1__6_n_0),
        .Q(rxratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_RXRATEDONE),
        .Q(rxratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxratedone_reg1),
        .Q(rxratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONE),
        .Q(rxsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(rxsync_done_reg1),
        .Q(rxsync_done_reg2),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    rxsync_start_reg1_i_1__6
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(SYNC_RXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    start_reg1_i_1__6
       (.I0(p_0_in7_in__0),
        .I1(RST_DRP_START),
        .O(DRP_START08_out));
  LUT6 #(
    .INIT(64'hFFFF3EFF00000200)) 
    \sysclksel[0]_i_1__6 
       (.I0(\sysclksel[0]_i_2__6_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(\sysclksel[0]_i_3__6_n_0 ),
        .I5(RXSYSCLKSEL[0]),
        .O(\sysclksel[0]_i_1__6_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \sysclksel[0]_i_2__6 
       (.I0(rate_in_reg2[1]),
        .I1(rate_in_reg2[0]),
        .O(\sysclksel[0]_i_2__6_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \sysclksel[0]_i_3__6 
       (.I0(Q[2]),
        .I1(Q[1]),
        .O(\sysclksel[0]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'h6FFFFFFF00000000)) 
    \sysclksel[1]_i_1__6 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(RXSYSCLKSEL[1]),
        .O(\sysclksel[1]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[0]_i_1__6_n_0 ),
        .Q(RXSYSCLKSEL[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \sysclksel_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(\sysclksel[1]_i_1__6_n_0 ),
        .Q(RXSYSCLKSEL[1]),
        .R(RST_CPLLRESET));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT5 #(
    .INIT(32'h80AA00AA)) 
    \txdata_wait_cnt[0]_i_1__6 
       (.I0(\txdata_wait_cnt[3]_i_2__6_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT5 #(
    .INIT(32'hA8282828)) 
    \txdata_wait_cnt[1]_i_1__6 
       (.I0(\txdata_wait_cnt[3]_i_2__6_n_0 ),
        .I1(txdata_wait_cnt_reg__0[0]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[3]),
        .I4(txdata_wait_cnt_reg__0[2]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT5 #(
    .INIT(32'h8AA0A0A0)) 
    \txdata_wait_cnt[2]_i_1__6 
       (.I0(\txdata_wait_cnt[3]_i_2__6_n_0 ),
        .I1(txdata_wait_cnt_reg__0[3]),
        .I2(txdata_wait_cnt_reg__0[2]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \txdata_wait_cnt[3]_i_1__6 
       (.I0(\txdata_wait_cnt[3]_i_2__6_n_0 ),
        .I1(txdata_wait_cnt_reg__0[2]),
        .I2(txdata_wait_cnt_reg__0[1]),
        .I3(txdata_wait_cnt_reg__0[0]),
        .I4(txdata_wait_cnt_reg__0[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \txdata_wait_cnt[3]_i_2__6 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(\txdata_wait_cnt[3]_i_2__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[0] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(txdata_wait_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[1] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(txdata_wait_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[2] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(txdata_wait_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \txdata_wait_cnt_reg[3] 
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(txdata_wait_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h5504FFFF55040000)) 
    txpmareset_i_1__6
       (.I0(Q[3]),
        .I1(rate_in_reg2[1]),
        .I2(rate_in_reg2[0]),
        .I3(gen3_exit),
        .I4(txpmareset_i_2__6_n_0),
        .I5(GT_TXPMARESET017_out),
        .O(txpmareset_i_1__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT5 #(
    .INIT(32'h82000400)) 
    txpmareset_i_2__6
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(txpmareset_i_2__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txpmareset_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txpmareset_i_1__6_n_0),
        .Q(GT_TXPMARESET017_out),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hC8)) 
    txratedone_i_1__6
       (.I0(txratedone_reg2),
        .I1(txratedone_i_2__6_n_0),
        .I2(txratedone_reg_n_0),
        .O(txratedone_i_1__6_n_0));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    txratedone_i_2__6
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(RST_CPLLRESET),
        .O(txratedone_i_2__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    txratedone_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_i_1__6_n_0),
        .Q(txratedone_reg_n_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXRATEDONE),
        .Q(txratedone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txratedone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txratedone_reg1),
        .Q(txratedone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg1_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(RATE_TXSYNC_DONE),
        .Q(txsync_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_done_reg2_reg
       (.C(pclk_sel_reg_0),
        .CE(1'b1),
        .D(txsync_done_reg1),
        .Q(txsync_done_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEAAA)) 
    txsync_start_reg1_i_1__6
       (.I0(out1[0]),
        .I1(Q[1]),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(SYNC_TXSYNC_START));
  LUT2 #(
    .INIT(4'hE)) 
    x16_reg1_i_1__6
       (.I0(p_0_in9_in),
        .I1(RST_DRP_X16),
        .O(DRP_X16010_out));
  LUT2 #(
    .INIT(4'hE)) 
    x16x20_mode_reg1_i_1__6
       (.I0(p_0_in135_in),
        .I1(RST_DRP_X16X20_MODE),
        .O(DRP_X16X20_MODE0136_out));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_reset" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_reset
   (rst_cpllpd,
    out,
    \cfg_wait_cnt_reg[5]_0 ,
    pipe_rst_fsm,
    RST_CPLLRESET,
    RST_RXUSRCLK_RESET,
    RST_DCLK_RESET,
    RST_DRP_START,
    RST_DRP_X16X20_MODE,
    RST_DRP_X16,
    rst_userrdy,
    rst_gtreset,
    userrdy_reg_rep_0,
    userrdy_reg_rep__0_0,
    userrdy_reg_rep__1_0,
    userrdy_reg_rep__2_0,
    userrdy_reg_rep__3_0,
    userrdy_reg_rep__4_0,
    userrdy_reg_rep__5_0,
    pclk_sel_reg,
    \resetovrd_disble.reset_reg[4] ,
    D,
    \resetovrd_disble.reset_reg[4]_0 ,
    rate_idle,
    done_reg,
    \resetovrd_disble.reset_reg[4]_1 ,
    \txsync_fsm.txsync_done_reg ,
    \resetovrd_disble.reset_reg[4]_2 ,
    pipe_qrst_idle,
    \rxcdrlock_cnt_reg[3] ,
    reset_n_reg2_reg);
  output rst_cpllpd;
  output [2:0]out;
  output \cfg_wait_cnt_reg[5]_0 ;
  output [3:0]pipe_rst_fsm;
  output RST_CPLLRESET;
  output RST_RXUSRCLK_RESET;
  output RST_DCLK_RESET;
  output RST_DRP_START;
  output RST_DRP_X16X20_MODE;
  output RST_DRP_X16;
  output rst_userrdy;
  output rst_gtreset;
  output userrdy_reg_rep_0;
  output userrdy_reg_rep__0_0;
  output userrdy_reg_rep__1_0;
  output userrdy_reg_rep__2_0;
  output userrdy_reg_rep__3_0;
  output userrdy_reg_rep__4_0;
  output userrdy_reg_rep__5_0;
  input pclk_sel_reg;
  input \resetovrd_disble.reset_reg[4] ;
  input [7:0]D;
  input [7:0]\resetovrd_disble.reset_reg[4]_0 ;
  input [7:0]rate_idle;
  input [7:0]done_reg;
  input [7:0]\resetovrd_disble.reset_reg[4]_1 ;
  input [7:0]\txsync_fsm.txsync_done_reg ;
  input \resetovrd_disble.reset_reg[4]_2 ;
  input pipe_qrst_idle;
  input [7:0]\rxcdrlock_cnt_reg[3] ;
  input reset_n_reg2_reg;

  wire [7:0]D;
  wire \FSM_onehot_fsm[0]_i_1_n_0 ;
  wire \FSM_onehot_fsm[0]_i_2_n_0 ;
  wire \FSM_onehot_fsm[13]_i_1_n_0 ;
  wire \FSM_onehot_fsm[13]_i_2_n_0 ;
  wire \FSM_onehot_fsm[13]_i_3_n_0 ;
  wire \FSM_onehot_fsm[14]_i_1_n_0 ;
  wire \FSM_onehot_fsm[14]_i_2_n_0 ;
  wire \FSM_onehot_fsm[14]_i_3_n_0 ;
  wire \FSM_onehot_fsm[14]_i_4_n_0 ;
  wire \FSM_onehot_fsm[14]_i_5_n_0 ;
  wire \FSM_onehot_fsm[15]_i_1_n_0 ;
  wire \FSM_onehot_fsm[16]_i_2_n_0 ;
  wire \FSM_onehot_fsm[16]_i_3_n_0 ;
  wire \FSM_onehot_fsm[16]_i_4_n_0 ;
  wire \FSM_onehot_fsm[16]_i_5_n_0 ;
  wire \FSM_onehot_fsm[16]_i_6_n_0 ;
  wire \FSM_onehot_fsm[16]_i_7_n_0 ;
  wire \FSM_onehot_fsm[16]_i_8_n_0 ;
  wire \FSM_onehot_fsm[16]_i_9_n_0 ;
  wire \FSM_onehot_fsm[1]_i_1_n_0 ;
  wire \FSM_onehot_fsm[1]_i_2_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1_n_0 ;
  wire \FSM_onehot_fsm[2]_i_2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_3_n_0 ;
  wire \FSM_onehot_fsm[3]_i_4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2__7_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4__7_n_0 ;
  wire \FSM_onehot_fsm[5]_i_1_n_0 ;
  wire \FSM_onehot_fsm[5]_i_2_n_0 ;
  wire \FSM_onehot_fsm[5]_i_3_n_0 ;
  wire \FSM_onehot_fsm[8]_i_1_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[10] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[11] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[12] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[13] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[14] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[4] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[5] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[6] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[7] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[8] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[9] ;
  wire RST_DRP_START;
  wire RST_DRP_START0;
  wire RST_DRP_X16;
  wire RST_DRP_X16X20_MODE;
  wire RST_DRP_X16X20_MODE0;
  wire \cfg_wait_cnt[3]_i_2_n_0 ;
  wire \cfg_wait_cnt[5]_i_2_n_0 ;
  wire \cfg_wait_cnt_reg[5]_0 ;
  wire [5:0]cfg_wait_cnt_reg__0;
  wire [7:0]cplllock_reg1;
  wire [7:0]cplllock_reg2;
  wire cpllpd_i_1__7_n_0;
  wire cpllreset;
  wire cpllreset_i_1_n_0;
  wire dclk_rst;
  wire dclk_rst_reg1;
  wire dclk_rst_reg2;
  wire [7:0]done_reg;
  wire [7:0]drp_done_reg1;
  wire [7:0]drp_done_reg2;
  wire gtreset_i_1_n_0;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  (* RTL_KEEP = "yes" *) wire [2:0]out;
  wire [5:0]p_0_in__0;
  wire p_2_in;
  wire pclk_sel_reg;
  wire [7:0]phystatus_reg1;
  wire [7:0]phystatus_reg2;
  wire pipe_qrst_idle;
  wire [3:0]pipe_rst_fsm;
  wire \pipe_rst_fsm[2]_INST_0_i_1_n_0 ;
  wire qpll_idle_reg1;
  wire qpll_idle_reg2;
  wire [7:0]rate_idle;
  wire [7:0]rate_idle_reg1;
  wire [7:0]rate_idle_reg2;
  wire reset_n_reg2_reg;
  wire [7:0]resetdone_reg1;
  wire [7:0]resetdone_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire [7:0]\resetovrd_disble.reset_reg[4]_0 ;
  wire [7:0]\resetovrd_disble.reset_reg[4]_1 ;
  wire \resetovrd_disble.reset_reg[4]_2 ;
  wire rst_cpllpd;
  wire rst_gtreset;
  wire rst_userrdy;
  wire [7:0]\rxcdrlock_cnt_reg[3] ;
  wire [7:0]rxcdrlock_reg1;
  wire [7:0]rxcdrlock_reg2;
  wire [7:0]rxpmaresetdone_reg1;
  wire [7:0]rxpmaresetdone_reg2;
  wire rxusrclk_rst_reg1;
  wire rxusrclk_rst_reg2;
  wire [7:0]txsync_done_reg1;
  wire [7:0]txsync_done_reg2;
  wire [7:0]\txsync_fsm.txsync_done_reg ;
  wire userrdy_i_1_n_0;
  wire userrdy_reg_rep_0;
  wire userrdy_reg_rep__0_0;
  wire userrdy_reg_rep__1_0;
  wire userrdy_reg_rep__2_0;
  wire userrdy_reg_rep__3_0;
  wire userrdy_reg_rep__4_0;
  wire userrdy_reg_rep__5_0;
  wire userrdy_rep_i_1__0_n_0;
  wire userrdy_rep_i_1__1_n_0;
  wire userrdy_rep_i_1__2_n_0;
  wire userrdy_rep_i_1__3_n_0;
  wire userrdy_rep_i_1__4_n_0;
  wire userrdy_rep_i_1__5_n_0;
  wire userrdy_rep_i_1_n_0;

  assign RST_CPLLRESET = cpllreset;
  assign RST_DCLK_RESET = dclk_rst_reg2;
  assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
  LUT5 #(
    .INIT(32'h13101010)) 
    \FSM_onehot_fsm[0]_i_1 
       (.I0(\FSM_onehot_fsm[1]_i_2_n_0 ),
        .I1(out[0]),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I4(\FSM_onehot_fsm[0]_i_2_n_0 ),
        .O(\FSM_onehot_fsm[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF7)) 
    \FSM_onehot_fsm[0]_i_2 
       (.I0(\FSM_onehot_fsm[3]_i_4_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_2_n_0 ),
        .I2(cplllock_reg2[1]),
        .I3(cplllock_reg2[0]),
        .I4(cplllock_reg2[3]),
        .I5(cplllock_reg2[2]),
        .O(\FSM_onehot_fsm[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0A0C00000A000000)) 
    \FSM_onehot_fsm[13]_i_1 
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[13] ),
        .I2(\FSM_onehot_fsm[13]_i_2_n_0 ),
        .I3(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I4(\FSM_onehot_fsm[16]_i_4_n_0 ),
        .I5(\FSM_onehot_fsm[13]_i_3_n_0 ),
        .O(\FSM_onehot_fsm[13]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_fsm[13]_i_2 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[5] ),
        .O(\FSM_onehot_fsm[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFDFFFFFFFF)) 
    \FSM_onehot_fsm[13]_i_3 
       (.I0(\FSM_onehot_fsm[14]_i_3_n_0 ),
        .I1(phystatus_reg2[1]),
        .I2(phystatus_reg2[0]),
        .I3(phystatus_reg2[3]),
        .I4(phystatus_reg2[2]),
        .I5(\FSM_onehot_fsm[14]_i_5_n_0 ),
        .O(\FSM_onehot_fsm[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \FSM_onehot_fsm[14]_i_1 
       (.I0(\FSM_onehot_fsm[14]_i_2_n_0 ),
        .I1(\FSM_onehot_fsm[14]_i_3_n_0 ),
        .I2(\FSM_onehot_fsm[14]_i_4_n_0 ),
        .I3(\FSM_onehot_fsm_reg_n_0_[13] ),
        .I4(\FSM_onehot_fsm[14]_i_5_n_0 ),
        .I5(\FSM_onehot_fsm[16]_i_4_n_0 ),
        .O(\FSM_onehot_fsm[14]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \FSM_onehot_fsm[14]_i_2 
       (.I0(\FSM_onehot_fsm_reg_n_0_[5] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[8] ),
        .O(\FSM_onehot_fsm[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \FSM_onehot_fsm[14]_i_3 
       (.I0(resetdone_reg2[4]),
        .I1(resetdone_reg2[5]),
        .I2(resetdone_reg2[2]),
        .I3(resetdone_reg2[3]),
        .I4(resetdone_reg2[7]),
        .I5(resetdone_reg2[6]),
        .O(\FSM_onehot_fsm[14]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \FSM_onehot_fsm[14]_i_4 
       (.I0(phystatus_reg2[1]),
        .I1(phystatus_reg2[0]),
        .I2(phystatus_reg2[3]),
        .I3(phystatus_reg2[2]),
        .O(\FSM_onehot_fsm[14]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    \FSM_onehot_fsm[14]_i_5 
       (.I0(phystatus_reg2[6]),
        .I1(phystatus_reg2[7]),
        .I2(phystatus_reg2[4]),
        .I3(phystatus_reg2[5]),
        .I4(resetdone_reg2[1]),
        .I5(resetdone_reg2[0]),
        .O(\FSM_onehot_fsm[14]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h55100000)) 
    \FSM_onehot_fsm[15]_i_1 
       (.I0(\FSM_onehot_fsm[16]_i_6_n_0 ),
        .I1(\FSM_onehot_fsm[16]_i_5_n_0 ),
        .I2(out[1]),
        .I3(\FSM_onehot_fsm_reg_n_0_[14] ),
        .I4(\FSM_onehot_fsm[16]_i_4_n_0 ),
        .O(\FSM_onehot_fsm[15]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \FSM_onehot_fsm[16]_i_1 
       (.I0(reset_n_reg2_reg),
        .O(\cfg_wait_cnt_reg[5]_0 ));
  LUT6 #(
    .INIT(64'h000000000000C0AA)) 
    \FSM_onehot_fsm[16]_i_2 
       (.I0(\FSM_onehot_fsm[16]_i_3_n_0 ),
        .I1(\FSM_onehot_fsm[16]_i_4_n_0 ),
        .I2(\FSM_onehot_fsm[16]_i_5_n_0 ),
        .I3(out[1]),
        .I4(\FSM_onehot_fsm_reg_n_0_[14] ),
        .I5(\FSM_onehot_fsm[16]_i_6_n_0 ),
        .O(\FSM_onehot_fsm[16]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \FSM_onehot_fsm[16]_i_3 
       (.I0(\FSM_onehot_fsm[16]_i_7_n_0 ),
        .I1(out[2]),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(out[0]),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[0] ),
        .O(\FSM_onehot_fsm[16]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \FSM_onehot_fsm[16]_i_4 
       (.I0(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(out[0]),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[16]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_onehot_fsm[16]_i_5 
       (.I0(\FSM_onehot_fsm[16]_i_8_n_0 ),
        .I1(txsync_done_reg2[5]),
        .I2(txsync_done_reg2[4]),
        .O(\FSM_onehot_fsm[16]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \FSM_onehot_fsm[16]_i_6 
       (.I0(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[5] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[13] ),
        .O(\FSM_onehot_fsm[16]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm[16]_i_7 
       (.I0(\FSM_onehot_fsm[16]_i_9_n_0 ),
        .I1(txsync_done_reg2[4]),
        .I2(txsync_done_reg2[5]),
        .O(\FSM_onehot_fsm[16]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \FSM_onehot_fsm[16]_i_8 
       (.I0(txsync_done_reg2[7]),
        .I1(txsync_done_reg2[6]),
        .I2(txsync_done_reg2[0]),
        .I3(txsync_done_reg2[1]),
        .I4(txsync_done_reg2[2]),
        .I5(txsync_done_reg2[3]),
        .O(\FSM_onehot_fsm[16]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \FSM_onehot_fsm[16]_i_9 
       (.I0(txsync_done_reg2[6]),
        .I1(txsync_done_reg2[7]),
        .I2(txsync_done_reg2[1]),
        .I3(txsync_done_reg2[0]),
        .I4(txsync_done_reg2[3]),
        .I5(txsync_done_reg2[2]),
        .O(\FSM_onehot_fsm[16]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'h20)) 
    \FSM_onehot_fsm[1]_i_1 
       (.I0(\FSM_onehot_fsm[1]_i_2_n_0 ),
        .I1(out[0]),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[1]_i_2 
       (.I0(cfg_wait_cnt_reg__0[4]),
        .I1(cfg_wait_cnt_reg__0[5]),
        .I2(cfg_wait_cnt_reg__0[2]),
        .I3(cfg_wait_cnt_reg__0[3]),
        .I4(cfg_wait_cnt_reg__0[1]),
        .I5(cfg_wait_cnt_reg__0[0]),
        .O(\FSM_onehot_fsm[1]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hF4)) 
    \FSM_onehot_fsm[2]_i_1 
       (.I0(\pipe_rst_fsm[2]_INST_0_i_1_n_0 ),
        .I1(\FSM_onehot_fsm[2]_i_2_n_0 ),
        .I2(out[0]),
        .O(\FSM_onehot_fsm[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00020000)) 
    \FSM_onehot_fsm[2]_i_2 
       (.I0(\FSM_onehot_fsm[16]_i_7_n_0 ),
        .I1(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(out[2]),
        .O(\FSM_onehot_fsm[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h02020202020F0202)) 
    \FSM_onehot_fsm[3]_i_1 
       (.I0(\FSM_onehot_fsm[3]_i_2_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_3_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_3_n_0 ),
        .I3(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I5(\FSM_onehot_fsm[4]_i_2__7_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \FSM_onehot_fsm[3]_i_2 
       (.I0(resetdone_reg2[4]),
        .I1(resetdone_reg2[5]),
        .I2(resetdone_reg2[2]),
        .I3(resetdone_reg2[3]),
        .I4(resetdone_reg2[7]),
        .I5(resetdone_reg2[6]),
        .O(\FSM_onehot_fsm[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF7)) 
    \FSM_onehot_fsm[3]_i_3 
       (.I0(\FSM_onehot_fsm[3]_i_4_n_0 ),
        .I1(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I2(cplllock_reg2[1]),
        .I3(cplllock_reg2[0]),
        .I4(cplllock_reg2[3]),
        .I5(cplllock_reg2[2]),
        .O(\FSM_onehot_fsm[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \FSM_onehot_fsm[3]_i_4 
       (.I0(cplllock_reg2[6]),
        .I1(cplllock_reg2[7]),
        .I2(cplllock_reg2[4]),
        .I3(cplllock_reg2[5]),
        .I4(resetdone_reg2[1]),
        .I5(resetdone_reg2[0]),
        .O(\FSM_onehot_fsm[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0200020002030200)) 
    \FSM_onehot_fsm[4]_i_1 
       (.I0(\FSM_onehot_fsm[4]_i_2__7_n_0 ),
        .I1(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I2(\FSM_onehot_fsm[4]_i_3_n_0 ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm[5]_i_2_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm[4]_i_2__7 
       (.I0(cplllock_reg2[1]),
        .I1(cplllock_reg2[0]),
        .I2(\FSM_onehot_fsm[4]_i_4__7_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2__7_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_fsm[4]_i_3 
       (.I0(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I1(out[0]),
        .O(\FSM_onehot_fsm[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \FSM_onehot_fsm[4]_i_4__7 
       (.I0(cplllock_reg2[3]),
        .I1(cplllock_reg2[2]),
        .I2(cplllock_reg2[6]),
        .I3(cplllock_reg2[7]),
        .I4(cplllock_reg2[4]),
        .I5(cplllock_reg2[5]),
        .O(\FSM_onehot_fsm[4]_i_4__7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    \FSM_onehot_fsm[5]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(\FSM_onehot_fsm[5]_i_2_n_0 ),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(out[0]),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[0] ),
        .O(\FSM_onehot_fsm[5]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_onehot_fsm[5]_i_2 
       (.I0(\FSM_onehot_fsm[5]_i_3_n_0 ),
        .I1(rate_idle_reg2[4]),
        .I2(rate_idle_reg2[5]),
        .O(\FSM_onehot_fsm[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \FSM_onehot_fsm[5]_i_3 
       (.I0(rate_idle_reg2[6]),
        .I1(rate_idle_reg2[7]),
        .I2(rate_idle_reg2[1]),
        .I3(rate_idle_reg2[0]),
        .I4(rate_idle_reg2[3]),
        .I5(rate_idle_reg2[2]),
        .O(\FSM_onehot_fsm[5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h55100000)) 
    \FSM_onehot_fsm[8]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(mmcm_lock_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm[16]_i_4_n_0 ),
        .O(\FSM_onehot_fsm[8]_i_1_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[0]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[10] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[11] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[12] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[13]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[13] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[14]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[14] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[15]_i_1_n_0 ),
        .Q(out[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[16]_i_2_n_0 ),
        .Q(out[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1_n_0 ),
        .Q(out[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[5]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[5] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[6] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[7] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[8]_i_1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[8] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[9] ),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    RST_DRP_START_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[6] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[11] ),
        .O(RST_DRP_START0));
  FDRE RST_DRP_START_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_DRP_START0),
        .Q(RST_DRP_START),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    RST_DRP_X16X20_MODE_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[12] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[6] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[7] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[11] ),
        .O(RST_DRP_X16X20_MODE0));
  FDRE RST_DRP_X16X20_MODE_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_DRP_X16X20_MODE0),
        .Q(RST_DRP_X16X20_MODE),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    RST_DRP_X16_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[6] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[7] ),
        .O(p_2_in));
  FDRE RST_DRP_X16_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_2_in),
        .Q(RST_DRP_X16),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  LUT5 #(
    .INIT(32'h2000AAAA)) 
    \cfg_wait_cnt[0]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I1(\cfg_wait_cnt[5]_i_2_n_0 ),
        .I2(cfg_wait_cnt_reg__0[5]),
        .I3(cfg_wait_cnt_reg__0[4]),
        .I4(cfg_wait_cnt_reg__0[0]),
        .O(p_0_in__0[0]));
  LUT6 #(
    .INIT(64'h28AA282828282828)) 
    \cfg_wait_cnt[1]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I1(cfg_wait_cnt_reg__0[0]),
        .I2(cfg_wait_cnt_reg__0[1]),
        .I3(\cfg_wait_cnt[5]_i_2_n_0 ),
        .I4(cfg_wait_cnt_reg__0[5]),
        .I5(cfg_wait_cnt_reg__0[4]),
        .O(p_0_in__0[1]));
  LUT6 #(
    .INIT(64'h88A2882288228822)) 
    \cfg_wait_cnt[2]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I1(cfg_wait_cnt_reg__0[2]),
        .I2(cfg_wait_cnt_reg__0[3]),
        .I3(\cfg_wait_cnt[3]_i_2_n_0 ),
        .I4(cfg_wait_cnt_reg__0[5]),
        .I5(cfg_wait_cnt_reg__0[4]),
        .O(p_0_in__0[2]));
  LUT6 #(
    .INIT(64'h8A88828882888288)) 
    \cfg_wait_cnt[3]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I1(cfg_wait_cnt_reg__0[3]),
        .I2(\cfg_wait_cnt[3]_i_2_n_0 ),
        .I3(cfg_wait_cnt_reg__0[2]),
        .I4(cfg_wait_cnt_reg__0[5]),
        .I5(cfg_wait_cnt_reg__0[4]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \cfg_wait_cnt[3]_i_2 
       (.I0(cfg_wait_cnt_reg__0[0]),
        .I1(cfg_wait_cnt_reg__0[1]),
        .O(\cfg_wait_cnt[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hC80C)) 
    \cfg_wait_cnt[4]_i_1 
       (.I0(cfg_wait_cnt_reg__0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\cfg_wait_cnt[5]_i_2_n_0 ),
        .I3(cfg_wait_cnt_reg__0[4]),
        .O(p_0_in__0[4]));
  LUT4 #(
    .INIT(16'h8A88)) 
    \cfg_wait_cnt[5]_i_1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I1(cfg_wait_cnt_reg__0[5]),
        .I2(\cfg_wait_cnt[5]_i_2_n_0 ),
        .I3(cfg_wait_cnt_reg__0[4]),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \cfg_wait_cnt[5]_i_2 
       (.I0(cfg_wait_cnt_reg__0[1]),
        .I1(cfg_wait_cnt_reg__0[0]),
        .I2(cfg_wait_cnt_reg__0[3]),
        .I3(cfg_wait_cnt_reg__0[2]),
        .O(\cfg_wait_cnt[5]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(cfg_wait_cnt_reg__0[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(cfg_wait_cnt_reg__0[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(cfg_wait_cnt_reg__0[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(cfg_wait_cnt_reg__0[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[4]),
        .Q(cfg_wait_cnt_reg__0[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \cfg_wait_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[5]),
        .Q(cfg_wait_cnt_reg__0[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 [0]),
        .Q(cplllock_reg1[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 [1]),
        .Q(cplllock_reg1[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 [2]),
        .Q(cplllock_reg1[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 [3]),
        .Q(cplllock_reg1[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 [4]),
        .Q(cplllock_reg1[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 [5]),
        .Q(cplllock_reg1[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 [6]),
        .Q(cplllock_reg1[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 [7]),
        .Q(cplllock_reg1[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[0]),
        .Q(cplllock_reg2[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[1]),
        .Q(cplllock_reg2[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[2]),
        .Q(cplllock_reg2[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[3]),
        .Q(cplllock_reg2[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[4]),
        .Q(cplllock_reg2[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[5]),
        .Q(cplllock_reg2[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[6]),
        .Q(cplllock_reg2[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cplllock_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[7]),
        .Q(cplllock_reg2[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    cpllpd_i_1__7
       (.I0(rst_cpllpd),
        .I1(\FSM_onehot_fsm_reg_n_0_[14] ),
        .O(cpllpd_i_1__7_n_0));
  FDRE #(
    .INIT(1'b0)) 
    cpllpd_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cpllpd_i_1__7_n_0),
        .Q(rst_cpllpd),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF00FFFEFF00)) 
    cpllreset_i_1
       (.I0(\pipe_rst_fsm[2]_INST_0_i_1_n_0 ),
        .I1(out[0]),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I4(cpllreset),
        .I5(out[2]),
        .O(cpllreset_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    cpllreset_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cpllreset_i_1_n_0),
        .Q(cpllreset),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    dclk_rst_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm_reg_n_0_[1] ),
        .Q(dclk_rst),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    dclk_rst_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4]_2 ),
        .CE(1'b1),
        .D(dclk_rst),
        .Q(dclk_rst_reg1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    dclk_rst_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4]_2 ),
        .CE(1'b1),
        .D(dclk_rst_reg1),
        .Q(dclk_rst_reg2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(done_reg[0]),
        .Q(drp_done_reg1[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(done_reg[1]),
        .Q(drp_done_reg1[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(done_reg[2]),
        .Q(drp_done_reg1[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(done_reg[3]),
        .Q(drp_done_reg1[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(done_reg[4]),
        .Q(drp_done_reg1[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(done_reg[5]),
        .Q(drp_done_reg1[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(done_reg[6]),
        .Q(drp_done_reg1[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(done_reg[7]),
        .Q(drp_done_reg1[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(drp_done_reg1[0]),
        .Q(drp_done_reg2[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(drp_done_reg1[1]),
        .Q(drp_done_reg2[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(drp_done_reg1[2]),
        .Q(drp_done_reg2[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(drp_done_reg1[3]),
        .Q(drp_done_reg2[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(drp_done_reg1[4]),
        .Q(drp_done_reg2[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(drp_done_reg1[5]),
        .Q(drp_done_reg2[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(drp_done_reg1[6]),
        .Q(drp_done_reg2[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(drp_done_reg1[7]),
        .Q(drp_done_reg2[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  LUT3 #(
    .INIT(8'hBA)) 
    gtreset_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[0] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[5] ),
        .I2(rst_gtreset),
        .O(gtreset_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    gtreset_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gtreset_i_1_n_0),
        .Q(rst_gtreset),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 [0]),
        .Q(phystatus_reg1[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 [1]),
        .Q(phystatus_reg1[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 [2]),
        .Q(phystatus_reg1[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 [3]),
        .Q(phystatus_reg1[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 [4]),
        .Q(phystatus_reg1[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 [5]),
        .Q(phystatus_reg1[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 [6]),
        .Q(phystatus_reg1[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 [7]),
        .Q(phystatus_reg1[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(phystatus_reg1[0]),
        .Q(phystatus_reg2[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(phystatus_reg1[1]),
        .Q(phystatus_reg2[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(phystatus_reg1[2]),
        .Q(phystatus_reg2[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(phystatus_reg1[3]),
        .Q(phystatus_reg2[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(phystatus_reg1[4]),
        .Q(phystatus_reg2[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(phystatus_reg1[5]),
        .Q(phystatus_reg2[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(phystatus_reg1[6]),
        .Q(phystatus_reg2[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \phystatus_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(phystatus_reg1[7]),
        .Q(phystatus_reg2[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \pipe_rst_fsm[0]_INST_0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[13] ),
        .I2(out[1]),
        .I3(\FSM_onehot_fsm_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(pipe_rst_fsm[0]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \pipe_rst_fsm[1]_INST_0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[14] ),
        .I1(out[1]),
        .I2(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[0] ),
        .O(pipe_rst_fsm[1]));
  LUT2 #(
    .INIT(4'hE)) 
    \pipe_rst_fsm[2]_INST_0 
       (.I0(\pipe_rst_fsm[2]_INST_0_i_1_n_0 ),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(pipe_rst_fsm[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \pipe_rst_fsm[2]_INST_0_i_1 
       (.I0(out[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[14] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[13] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[5] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[8] ),
        .O(\pipe_rst_fsm[2]_INST_0_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pipe_rst_fsm[3]_INST_0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[14] ),
        .I1(out[1]),
        .I2(\FSM_onehot_fsm_reg_n_0_[13] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[8] ),
        .O(pipe_rst_fsm[3]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qpll_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pipe_qrst_idle),
        .Q(qpll_idle_reg1),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qpll_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpll_idle_reg1),
        .Q(qpll_idle_reg2),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle[0]),
        .Q(rate_idle_reg1[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle[1]),
        .Q(rate_idle_reg1[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle[2]),
        .Q(rate_idle_reg1[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle[3]),
        .Q(rate_idle_reg1[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle[4]),
        .Q(rate_idle_reg1[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle[5]),
        .Q(rate_idle_reg1[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle[6]),
        .Q(rate_idle_reg1[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle[7]),
        .Q(rate_idle_reg1[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1[0]),
        .Q(rate_idle_reg2[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1[1]),
        .Q(rate_idle_reg2[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1[2]),
        .Q(rate_idle_reg2[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1[3]),
        .Q(rate_idle_reg2[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1[4]),
        .Q(rate_idle_reg2[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1[5]),
        .Q(rate_idle_reg2[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1[6]),
        .Q(rate_idle_reg2[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_idle_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1[7]),
        .Q(rate_idle_reg2[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[0]),
        .Q(resetdone_reg1[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[1]),
        .Q(resetdone_reg1[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[2]),
        .Q(resetdone_reg1[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[3]),
        .Q(resetdone_reg1[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[4]),
        .Q(resetdone_reg1[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[5]),
        .Q(resetdone_reg1[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[6]),
        .Q(resetdone_reg1[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[7]),
        .Q(resetdone_reg1[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetdone_reg1[0]),
        .Q(resetdone_reg2[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetdone_reg1[1]),
        .Q(resetdone_reg2[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetdone_reg1[2]),
        .Q(resetdone_reg2[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetdone_reg1[3]),
        .Q(resetdone_reg2[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetdone_reg1[4]),
        .Q(resetdone_reg2[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetdone_reg1[5]),
        .Q(resetdone_reg2[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetdone_reg1[6]),
        .Q(resetdone_reg2[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \resetdone_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetdone_reg1[7]),
        .Q(resetdone_reg2[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxcdrlock_cnt_reg[3] [0]),
        .Q(rxcdrlock_reg1[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxcdrlock_cnt_reg[3] [1]),
        .Q(rxcdrlock_reg1[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxcdrlock_cnt_reg[3] [2]),
        .Q(rxcdrlock_reg1[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxcdrlock_cnt_reg[3] [3]),
        .Q(rxcdrlock_reg1[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxcdrlock_cnt_reg[3] [4]),
        .Q(rxcdrlock_reg1[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxcdrlock_cnt_reg[3] [5]),
        .Q(rxcdrlock_reg1[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxcdrlock_cnt_reg[3] [6]),
        .Q(rxcdrlock_reg1[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxcdrlock_cnt_reg[3] [7]),
        .Q(rxcdrlock_reg1[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1[0]),
        .Q(rxcdrlock_reg2[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1[1]),
        .Q(rxcdrlock_reg2[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1[2]),
        .Q(rxcdrlock_reg2[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1[3]),
        .Q(rxcdrlock_reg2[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1[4]),
        .Q(rxcdrlock_reg2[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1[5]),
        .Q(rxcdrlock_reg2[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1[6]),
        .Q(rxcdrlock_reg2[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxcdrlock_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1[7]),
        .Q(rxcdrlock_reg2[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxpmaresetdone_reg1[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1[0]),
        .Q(rxpmaresetdone_reg2[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1[1]),
        .Q(rxpmaresetdone_reg2[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1[2]),
        .Q(rxpmaresetdone_reg2[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1[3]),
        .Q(rxpmaresetdone_reg2[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1[4]),
        .Q(rxpmaresetdone_reg2[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1[5]),
        .Q(rxpmaresetdone_reg2[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1[6]),
        .Q(rxpmaresetdone_reg2[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rxpmaresetdone_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxpmaresetdone_reg1[7]),
        .Q(rxpmaresetdone_reg2[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    rxusrclk_rst_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cpllreset),
        .Q(rxusrclk_rst_reg1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    rxusrclk_rst_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxusrclk_rst_reg1),
        .Q(rxusrclk_rst_reg2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_reg [0]),
        .Q(txsync_done_reg1[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_reg [1]),
        .Q(txsync_done_reg1[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_reg [2]),
        .Q(txsync_done_reg1[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_reg [3]),
        .Q(txsync_done_reg1[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_reg [4]),
        .Q(txsync_done_reg1[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_reg [5]),
        .Q(txsync_done_reg1[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_reg [6]),
        .Q(txsync_done_reg1[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_reg [7]),
        .Q(txsync_done_reg1[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_done_reg1[0]),
        .Q(txsync_done_reg2[0]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_done_reg1[1]),
        .Q(txsync_done_reg2[1]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_done_reg1[2]),
        .Q(txsync_done_reg2[2]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_done_reg1[3]),
        .Q(txsync_done_reg2[3]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_done_reg1[4]),
        .Q(txsync_done_reg2[4]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_done_reg1[5]),
        .Q(txsync_done_reg2[5]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_done_reg1[6]),
        .Q(txsync_done_reg2[6]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txsync_done_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_done_reg1[7]),
        .Q(txsync_done_reg2[7]),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    userrdy_i_1
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I2(rst_userrdy),
        .O(userrdy_i_1_n_0));
  (* ORIG_CELL_NAME = "userrdy_reg" *) 
  FDRE #(
    .INIT(1'b0)) 
    userrdy_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(userrdy_i_1_n_0),
        .Q(rst_userrdy),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ORIG_CELL_NAME = "userrdy_reg" *) 
  FDRE #(
    .INIT(1'b0)) 
    userrdy_reg_rep
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(userrdy_rep_i_1_n_0),
        .Q(userrdy_reg_rep_0),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ORIG_CELL_NAME = "userrdy_reg" *) 
  FDRE #(
    .INIT(1'b0)) 
    userrdy_reg_rep__0
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(userrdy_rep_i_1__0_n_0),
        .Q(userrdy_reg_rep__0_0),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ORIG_CELL_NAME = "userrdy_reg" *) 
  FDRE #(
    .INIT(1'b0)) 
    userrdy_reg_rep__1
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(userrdy_rep_i_1__1_n_0),
        .Q(userrdy_reg_rep__1_0),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ORIG_CELL_NAME = "userrdy_reg" *) 
  FDRE #(
    .INIT(1'b0)) 
    userrdy_reg_rep__2
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(userrdy_rep_i_1__2_n_0),
        .Q(userrdy_reg_rep__2_0),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ORIG_CELL_NAME = "userrdy_reg" *) 
  FDRE #(
    .INIT(1'b0)) 
    userrdy_reg_rep__3
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(userrdy_rep_i_1__3_n_0),
        .Q(userrdy_reg_rep__3_0),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ORIG_CELL_NAME = "userrdy_reg" *) 
  FDRE #(
    .INIT(1'b0)) 
    userrdy_reg_rep__4
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(userrdy_rep_i_1__4_n_0),
        .Q(userrdy_reg_rep__4_0),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  (* ORIG_CELL_NAME = "userrdy_reg" *) 
  FDRE #(
    .INIT(1'b0)) 
    userrdy_reg_rep__5
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(userrdy_rep_i_1__5_n_0),
        .Q(userrdy_reg_rep__5_0),
        .R(\cfg_wait_cnt_reg[5]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    userrdy_rep_i_1
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I2(userrdy_reg_rep_0),
        .O(userrdy_rep_i_1_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    userrdy_rep_i_1__0
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I2(userrdy_reg_rep__0_0),
        .O(userrdy_rep_i_1__0_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    userrdy_rep_i_1__1
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I2(userrdy_reg_rep__1_0),
        .O(userrdy_rep_i_1__1_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    userrdy_rep_i_1__2
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I2(userrdy_reg_rep__2_0),
        .O(userrdy_rep_i_1__2_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    userrdy_rep_i_1__3
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I2(userrdy_reg_rep__3_0),
        .O(userrdy_rep_i_1__3_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    userrdy_rep_i_1__4
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I2(userrdy_reg_rep__4_0),
        .O(userrdy_rep_i_1__4_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    userrdy_rep_i_1__5
       (.I0(mmcm_lock_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[8] ),
        .I2(userrdy_reg_rep__5_0),
        .O(userrdy_rep_i_1__5_n_0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_sync" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync
   (Q,
    RST_TXSYNC_DONE,
    pipe_sync_fsm_rx,
    SYNC_RXSYNC_DONEM_IN,
    SYNC_RXDLYEN,
    \cplllock_reg1_reg[0] ,
    \cplllock_reg1_reg[0]_0 ,
    \cplllock_reg1_reg[0]_1 ,
    \cplllock_reg1_reg[0]_2 ,
    \cplllock_reg1_reg[0]_3 ,
    \txsync_fsm.txdlyen_reg_0 ,
    user_active_lane,
    RST_CPLLRESET,
    SYNC_TXSYNC_START,
    pclk_sel_reg,
    RATE_MMCM_LOCK,
    SYNC_TXDLYSRESETDONE0,
    SYNC_TXPHINITDONE,
    SYNC_TXPHALIGNDONE,
    rate_gen3,
    RST_RATE_IDLE,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXCDRLOCK,
    SYNC_RXSYNC_START,
    SYNC_RXDLYSRESETDONE0,
    SYNC_RXPHALIGNDONE_M,
    SYNC_RXPHALIGNDONE_S,
    p_0_in7_in,
    p_1_in8_in);
  output [5:0]Q;
  output [0:0]RST_TXSYNC_DONE;
  output [6:0]pipe_sync_fsm_rx;
  output SYNC_RXSYNC_DONEM_IN;
  output SYNC_RXDLYEN;
  output \cplllock_reg1_reg[0] ;
  output \cplllock_reg1_reg[0]_0 ;
  output \cplllock_reg1_reg[0]_1 ;
  output \cplllock_reg1_reg[0]_2 ;
  output \cplllock_reg1_reg[0]_3 ;
  output \txsync_fsm.txdlyen_reg_0 ;
  input [0:0]user_active_lane;
  input RST_CPLLRESET;
  input SYNC_TXSYNC_START;
  input pclk_sel_reg;
  input RATE_MMCM_LOCK;
  input SYNC_TXDLYSRESETDONE0;
  input SYNC_TXPHINITDONE;
  input SYNC_TXPHALIGNDONE;
  input [0:0]rate_gen3;
  input [0:0]RST_RATE_IDLE;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input SYNC_RXCDRLOCK;
  input SYNC_RXSYNC_START;
  input SYNC_RXDLYSRESETDONE0;
  input SYNC_RXPHALIGNDONE_M;
  input SYNC_RXPHALIGNDONE_S;
  input p_0_in7_in;
  input p_1_in8_in;

  wire [5:0]Q;
  wire RATE_MMCM_LOCK;
  wire RST_CPLLRESET;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_TXSYNC_DONE;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXDLYEN;
  wire SYNC_RXDLYSRESETDONE0;
  wire SYNC_RXPHALIGNDONE_M;
  wire SYNC_RXPHALIGNDONE_S;
  wire SYNC_RXSYNC_DONEM_IN;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXDLYSRESETDONE0;
  wire SYNC_TXPHALIGNDONE;
  wire SYNC_TXPHINITDONE;
  wire SYNC_TXSYNC_START;
  wire \cplllock_reg1_reg[0] ;
  wire \cplllock_reg1_reg[0]_0 ;
  wire \cplllock_reg1_reg[0]_1 ;
  wire \cplllock_reg1_reg[0]_2 ;
  wire \cplllock_reg1_reg[0]_3 ;
  wire [5:0]fsm_tx;
  wire fsm_tx1;
  wire gen3_reg1;
  wire gen3_reg2;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire \gtx_channel.gtxe2_channel_i_i_56_n_0 ;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire p_0_in7_in;
  wire p_1_in8_in;
  wire pclk_sel_reg;
  wire [6:0]pipe_sync_fsm_rx;
  wire [0:0]rate_gen3;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxdlysresetdone_reg1;
  wire rxdlysresetdone_reg2;
  wire rxelecidle_reg1;
  wire rxelecidle_reg2;
  wire rxphaligndone_m_reg1;
  wire rxphaligndone_m_reg2;
  wire rxphaligndone_s_reg1;
  wire rxphaligndone_s_reg2;
  wire rxsync_donem_reg1;
  wire rxsync_donem_reg2;
  wire rxsync_start_reg1;
  wire rxsync_start_reg2;
  wire rxsyncdone_reg1;
  wire rxsyncdone_reg2;
  wire txdlysresetdone_reg1;
  wire txdlysresetdone_reg2;
  wire txdlysresetdone_reg3;
  wire txphaligndone_reg1;
  wire txphaligndone_reg2;
  wire txphaligndone_reg3;
  wire txphinitdone_reg1;
  wire txphinitdone_reg2;
  wire txphinitdone_reg3;
  wire \txsync_fsm.fsm_tx[4]_i_2_n_0 ;
  wire \txsync_fsm.fsm_tx[5]_i_2_n_0 ;
  wire \txsync_fsm.txdlyen_i_1_n_0 ;
  wire \txsync_fsm.txdlyen_i_2_n_0 ;
  wire \txsync_fsm.txdlyen_i_3_n_0 ;
  wire \txsync_fsm.txdlyen_reg_0 ;
  wire \txsync_fsm.txsync_done_i_1__6_n_0 ;
  wire \txsync_fsm.txsync_done_i_2_n_0 ;
  wire txsync_start_reg1;
  wire txsync_start_reg2;
  wire txsync_start_reg3;
  wire txsyncdone_reg1;
  wire txsyncdone_reg2;
  wire txsyncdone_reg3;
  wire [0:0]user_active_lane;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_11 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(\cplllock_reg1_reg[0] ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_12 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[0]_1 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \gtx_channel.gtxe2_channel_i_i_13 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[0]_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \gtx_channel.gtxe2_channel_i_i_56 
       (.I0(pipe_sync_fsm_rx[0]),
        .I1(pipe_sync_fsm_rx[1]),
        .I2(pipe_sync_fsm_rx[6]),
        .I3(pipe_sync_fsm_rx[4]),
        .O(\gtx_channel.gtxe2_channel_i_i_56_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_8 
       (.I0(pipe_sync_fsm_rx[2]),
        .I1(pipe_sync_fsm_rx[3]),
        .I2(pipe_sync_fsm_rx[5]),
        .I3(\gtx_channel.gtxe2_channel_i_i_56_n_0 ),
        .O(\cplllock_reg1_reg[0]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \gtx_channel.gtxe2_channel_i_i_9 
       (.I0(pipe_sync_fsm_rx[2]),
        .I1(pipe_sync_fsm_rx[3]),
        .I2(pipe_sync_fsm_rx[5]),
        .I3(\gtx_channel.gtxe2_channel_i_i_56_n_0 ),
        .O(\cplllock_reg1_reg[0]_2 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RATE_MMCM_LOCK),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXCDRLOCK),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXDLYSRESETDONE0),
        .Q(rxdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxdlysresetdone_reg1),
        .Q(rxdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gt_rx_elec_idle_wire_filter),
        .Q(rxelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxelecidle_reg1),
        .Q(rxelecidle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXPHALIGNDONE_M),
        .Q(rxphaligndone_m_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_m_reg1),
        .Q(rxphaligndone_m_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXPHALIGNDONE_S),
        .Q(rxphaligndone_s_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_s_reg1),
        .Q(rxphaligndone_s_reg2),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'h0004)) 
    rxsync_donem_reg1_i_1
       (.I0(pipe_sync_fsm_rx[2]),
        .I1(pipe_sync_fsm_rx[5]),
        .I2(pipe_sync_fsm_rx[3]),
        .I3(\gtx_channel.gtxe2_channel_i_i_56_n_0 ),
        .O(SYNC_RXSYNC_DONEM_IN));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONEM_IN),
        .Q(rxsync_donem_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_donem_reg1),
        .Q(rxsync_donem_reg2),
        .R(RST_CPLLRESET));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b1),
        .Q(pipe_sync_fsm_rx[0]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[1]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[2]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[3]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[4]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[5]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[6]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.rxdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(SYNC_RXDLYEN),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_START),
        .Q(rxsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_start_reg1),
        .Q(rxsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsyncdone_reg1),
        .Q(rxsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXDLYSRESETDONE0),
        .Q(txdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg1),
        .Q(txdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg2),
        .Q(txdlysresetdone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXPHALIGNDONE),
        .Q(txphaligndone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg1),
        .Q(txphaligndone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg2),
        .Q(txphaligndone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXPHINITDONE),
        .Q(txphinitdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg1),
        .Q(txphinitdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg2),
        .Q(txphinitdone_reg3),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hF222FFFF)) 
    \txsync_fsm.fsm_tx[0]_i_1 
       (.I0(Q[0]),
        .I1(txsync_start_reg2),
        .I2(fsm_tx1),
        .I3(Q[5]),
        .I4(\txsync_fsm.fsm_tx[5]_i_2_n_0 ),
        .O(fsm_tx[0]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[1]_i_1 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2_n_0 ),
        .I1(Q[0]),
        .I2(txsync_start_reg2),
        .I3(Q[1]),
        .I4(mmcm_lock_reg2),
        .O(fsm_tx[1]));
  LUT6 #(
    .INIT(64'hAAAA80AA80808080)) 
    \txsync_fsm.fsm_tx[2]_i_1 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2_n_0 ),
        .I1(Q[1]),
        .I2(mmcm_lock_reg2),
        .I3(txdlysresetdone_reg2),
        .I4(txdlysresetdone_reg3),
        .I5(Q[2]),
        .O(fsm_tx[2]));
  LUT6 #(
    .INIT(64'h00800080AAAA0080)) 
    \txsync_fsm.fsm_tx[3]_i_1 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(txdlysresetdone_reg2),
        .I3(txdlysresetdone_reg3),
        .I4(Q[3]),
        .I5(\txsync_fsm.fsm_tx[4]_i_2_n_0 ),
        .O(fsm_tx[3]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[4]_i_1 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2_n_0 ),
        .I1(\txsync_fsm.fsm_tx[4]_i_2_n_0 ),
        .I2(Q[3]),
        .I3(Q[4]),
        .I4(fsm_tx1),
        .O(fsm_tx[4]));
  LUT4 #(
    .INIT(16'hF222)) 
    \txsync_fsm.fsm_tx[4]_i_2 
       (.I0(txphinitdone_reg2),
        .I1(txphinitdone_reg3),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \txsync_fsm.fsm_tx[4]_i_3 
       (.I0(txphaligndone_reg3),
        .I1(txphaligndone_reg2),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(fsm_tx1));
  LUT6 #(
    .INIT(64'h8A8AAA8A80800080)) 
    \txsync_fsm.fsm_tx[5]_i_1 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2_n_0 ),
        .I1(Q[5]),
        .I2(user_active_lane),
        .I3(txphaligndone_reg2),
        .I4(txphaligndone_reg3),
        .I5(Q[4]),
        .O(fsm_tx[5]));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \txsync_fsm.fsm_tx[5]_i_2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(Q[5]),
        .O(\txsync_fsm.fsm_tx[5]_i_2_n_0 ));
  FDSE \txsync_fsm.fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[1]),
        .Q(Q[1]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[5]),
        .Q(Q[5]),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \txsync_fsm.txdlyen_i_1 
       (.I0(\txsync_fsm.txdlyen_i_2_n_0 ),
        .I1(\txsync_fsm.txdlyen_i_3_n_0 ),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(\txsync_fsm.txdlyen_reg_0 ),
        .O(\txsync_fsm.txdlyen_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \txsync_fsm.txdlyen_i_2 
       (.I0(Q[3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(\txsync_fsm.txdlyen_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \txsync_fsm.txdlyen_i_3 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_start_reg2),
        .O(\txsync_fsm.txdlyen_i_3_n_0 ));
  FDRE \txsync_fsm.txdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txdlyen_i_1_n_0 ),
        .Q(\txsync_fsm.txdlyen_reg_0 ),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0301000103000000)) 
    \txsync_fsm.txsync_done_i_1__6 
       (.I0(\txsync_fsm.txdlyen_i_3_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[5]),
        .I4(\txsync_fsm.txsync_done_i_2_n_0 ),
        .I5(RST_TXSYNC_DONE),
        .O(\txsync_fsm.txsync_done_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001055)) 
    \txsync_fsm.txsync_done_i_2 
       (.I0(Q[0]),
        .I1(txphaligndone_reg3),
        .I2(txphaligndone_reg2),
        .I3(user_active_lane),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\txsync_fsm.txsync_done_i_2_n_0 ));
  FDRE \txsync_fsm.txsync_done_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_i_1__6_n_0 ),
        .Q(RST_TXSYNC_DONE),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXSYNC_START),
        .Q(txsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg1),
        .Q(txsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg2),
        .Q(txsync_start_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg1),
        .Q(txsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg2),
        .Q(txsyncdone_reg3),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_sync" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_33
   (Q,
    \txsync_fsm.txdlyen_reg_0 ,
    pipe_sync_fsm_rx,
    SYNC_RXDLYEN,
    \cplllock_reg1_reg[1] ,
    \cplllock_reg1_reg[1]_0 ,
    \cplllock_reg1_reg[1]_1 ,
    \cplllock_reg1_reg[1]_2 ,
    \cplllock_reg1_reg[1]_3 ,
    RST_TXSYNC_DONE,
    p_0_in7_in,
    p_1_in8_in,
    RST_CPLLRESET,
    SYNC_TXSYNC_START,
    pclk_sel_reg,
    \resetovrd_disble.reset_reg[4] ,
    SYNC_TXDLYSRESETDONE0,
    SYNC_TXPHINITDONE,
    SYNC_TXPHALIGNDONE,
    SYNC_RXSYNC_DONEM_IN,
    SYNC_GEN3,
    RST_RATE_IDLE,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXCDRLOCK,
    SYNC_RXSYNC_START,
    SYNC_RXDLYSRESETDONE0,
    SYNC_RXPHALIGNDONE_M,
    SYNC_RXPHALIGNDONE_S);
  output [5:0]Q;
  output \txsync_fsm.txdlyen_reg_0 ;
  output [6:0]pipe_sync_fsm_rx;
  output SYNC_RXDLYEN;
  output \cplllock_reg1_reg[1] ;
  output \cplllock_reg1_reg[1]_0 ;
  output \cplllock_reg1_reg[1]_1 ;
  output \cplllock_reg1_reg[1]_2 ;
  output \cplllock_reg1_reg[1]_3 ;
  output [0:0]RST_TXSYNC_DONE;
  input p_0_in7_in;
  input p_1_in8_in;
  input RST_CPLLRESET;
  input SYNC_TXSYNC_START;
  input pclk_sel_reg;
  input \resetovrd_disble.reset_reg[4] ;
  input SYNC_TXDLYSRESETDONE0;
  input SYNC_TXPHINITDONE;
  input SYNC_TXPHALIGNDONE;
  input SYNC_RXSYNC_DONEM_IN;
  input SYNC_GEN3;
  input [0:0]RST_RATE_IDLE;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input SYNC_RXCDRLOCK;
  input SYNC_RXSYNC_START;
  input SYNC_RXDLYSRESETDONE0;
  input SYNC_RXPHALIGNDONE_M;
  input SYNC_RXPHALIGNDONE_S;

  wire [5:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_TXSYNC_DONE;
  wire SYNC_GEN3;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXDLYEN;
  wire SYNC_RXDLYSRESETDONE0;
  wire SYNC_RXPHALIGNDONE_M;
  wire SYNC_RXPHALIGNDONE_S;
  wire SYNC_RXSYNC_DONEM_IN;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXDLYSRESETDONE0;
  wire SYNC_TXPHALIGNDONE;
  wire SYNC_TXPHINITDONE;
  wire SYNC_TXSYNC_START;
  wire \cplllock_reg1_reg[1] ;
  wire \cplllock_reg1_reg[1]_0 ;
  wire \cplllock_reg1_reg[1]_1 ;
  wire \cplllock_reg1_reg[1]_2 ;
  wire \cplllock_reg1_reg[1]_3 ;
  wire [5:0]fsm_tx;
  wire gen3_reg1;
  wire gen3_reg2;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire \gtx_channel.gtxe2_channel_i_i_56__0_n_0 ;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire p_0_in7_in;
  wire p_1_in8_in;
  wire pclk_sel_reg;
  wire [6:0]pipe_sync_fsm_rx;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxdlysresetdone_reg1;
  wire rxdlysresetdone_reg2;
  wire rxelecidle_reg1;
  wire rxelecidle_reg2;
  wire rxphaligndone_m_reg1;
  wire rxphaligndone_m_reg2;
  wire rxphaligndone_s_reg1;
  wire rxphaligndone_s_reg2;
  wire rxsync_donem_reg1;
  wire rxsync_donem_reg2;
  wire rxsync_start_reg1;
  wire rxsync_start_reg2;
  wire rxsyncdone_reg1;
  wire rxsyncdone_reg2;
  wire txdlysresetdone_reg1;
  wire txdlysresetdone_reg2;
  wire txdlysresetdone_reg3;
  wire txphaligndone_reg1;
  wire txphaligndone_reg2;
  wire txphaligndone_reg3;
  wire txphinitdone_reg1;
  wire txphinitdone_reg2;
  wire txphinitdone_reg3;
  wire txsync_done;
  wire \txsync_fsm.fsm_tx[4]_i_2__0_n_0 ;
  wire \txsync_fsm.fsm_tx[4]_i_3__0_n_0 ;
  wire \txsync_fsm.fsm_tx[5]_i_2__0_n_0 ;
  wire \txsync_fsm.txdlyen_i_1__0_n_0 ;
  wire \txsync_fsm.txdlyen_i_2__0_n_0 ;
  wire \txsync_fsm.txdlyen_reg_0 ;
  wire \txsync_fsm.txsync_done_i_1_n_0 ;
  wire txsync_start_reg1;
  wire txsync_start_reg2;
  wire txsync_start_reg3;
  wire txsyncdone_reg1;
  wire txsyncdone_reg2;
  wire txsyncdone_reg3;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_GEN3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_11__0 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(\cplllock_reg1_reg[1] ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_12__0 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \gtx_channel.gtxe2_channel_i_i_13__0 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[1]_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \gtx_channel.gtxe2_channel_i_i_56__0 
       (.I0(pipe_sync_fsm_rx[0]),
        .I1(pipe_sync_fsm_rx[1]),
        .I2(pipe_sync_fsm_rx[6]),
        .I3(pipe_sync_fsm_rx[4]),
        .O(\gtx_channel.gtxe2_channel_i_i_56__0_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_8__0 
       (.I0(pipe_sync_fsm_rx[2]),
        .I1(pipe_sync_fsm_rx[3]),
        .I2(pipe_sync_fsm_rx[5]),
        .I3(\gtx_channel.gtxe2_channel_i_i_56__0_n_0 ),
        .O(\cplllock_reg1_reg[1]_3 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \gtx_channel.gtxe2_channel_i_i_9__0 
       (.I0(rxsync_donem_reg2),
        .I1(pipe_sync_fsm_rx[5]),
        .I2(pipe_sync_fsm_rx[3]),
        .I3(pipe_sync_fsm_rx[2]),
        .I4(\gtx_channel.gtxe2_channel_i_i_56__0_n_0 ),
        .O(\cplllock_reg1_reg[1]_2 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXCDRLOCK),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXDLYSRESETDONE0),
        .Q(rxdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxdlysresetdone_reg1),
        .Q(rxdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gt_rx_elec_idle_wire_filter),
        .Q(rxelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxelecidle_reg1),
        .Q(rxelecidle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXPHALIGNDONE_M),
        .Q(rxphaligndone_m_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_m_reg1),
        .Q(rxphaligndone_m_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXPHALIGNDONE_S),
        .Q(rxphaligndone_s_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_s_reg1),
        .Q(rxphaligndone_s_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONEM_IN),
        .Q(rxsync_donem_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_donem_reg1),
        .Q(rxsync_donem_reg2),
        .R(RST_CPLLRESET));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b1),
        .Q(pipe_sync_fsm_rx[0]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[1]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[2]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[3]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[4]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[5]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[6]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.rxdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(SYNC_RXDLYEN),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_START),
        .Q(rxsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_start_reg1),
        .Q(rxsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsyncdone_reg1),
        .Q(rxsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXDLYSRESETDONE0),
        .Q(txdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg1),
        .Q(txdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg2),
        .Q(txdlysresetdone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXPHALIGNDONE),
        .Q(txphaligndone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg1),
        .Q(txphaligndone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg2),
        .Q(txphaligndone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXPHINITDONE),
        .Q(txphinitdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg1),
        .Q(txphinitdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg2),
        .Q(txphinitdone_reg3),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'hF2FF)) 
    \txsync_fsm.fsm_tx[0]_i_1__0 
       (.I0(Q[0]),
        .I1(txsync_start_reg2),
        .I2(Q[5]),
        .I3(\txsync_fsm.fsm_tx[5]_i_2__0_n_0 ),
        .O(fsm_tx[0]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[1]_i_1__0 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__0_n_0 ),
        .I1(Q[0]),
        .I2(txsync_start_reg2),
        .I3(Q[1]),
        .I4(mmcm_lock_reg2),
        .O(fsm_tx[1]));
  LUT6 #(
    .INIT(64'hAAAA80AA80808080)) 
    \txsync_fsm.fsm_tx[2]_i_1__0 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__0_n_0 ),
        .I1(Q[1]),
        .I2(mmcm_lock_reg2),
        .I3(txdlysresetdone_reg2),
        .I4(txdlysresetdone_reg3),
        .I5(Q[2]),
        .O(fsm_tx[2]));
  LUT6 #(
    .INIT(64'h00800080AAAA0080)) 
    \txsync_fsm.fsm_tx[3]_i_1__0 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__0_n_0 ),
        .I1(Q[2]),
        .I2(txdlysresetdone_reg2),
        .I3(txdlysresetdone_reg3),
        .I4(Q[3]),
        .I5(\txsync_fsm.fsm_tx[4]_i_2__0_n_0 ),
        .O(fsm_tx[3]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[4]_i_1__0 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__0_n_0 ),
        .I1(\txsync_fsm.fsm_tx[4]_i_2__0_n_0 ),
        .I2(Q[3]),
        .I3(Q[4]),
        .I4(\txsync_fsm.fsm_tx[4]_i_3__0_n_0 ),
        .O(fsm_tx[4]));
  LUT4 #(
    .INIT(16'hF222)) 
    \txsync_fsm.fsm_tx[4]_i_2__0 
       (.I0(txphinitdone_reg2),
        .I1(txphinitdone_reg3),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \txsync_fsm.fsm_tx[4]_i_3__0 
       (.I0(txphaligndone_reg3),
        .I1(txphaligndone_reg2),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hAA20202000000000)) 
    \txsync_fsm.fsm_tx[5]_i_1__0 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__0_n_0 ),
        .I1(txphaligndone_reg3),
        .I2(txphaligndone_reg2),
        .I3(p_0_in7_in),
        .I4(p_1_in8_in),
        .I5(Q[4]),
        .O(fsm_tx[5]));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \txsync_fsm.fsm_tx[5]_i_2__0 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(Q[5]),
        .O(\txsync_fsm.fsm_tx[5]_i_2__0_n_0 ));
  FDSE \txsync_fsm.fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[1]),
        .Q(Q[1]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[5]),
        .Q(Q[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00010000)) 
    \txsync_fsm.txdlyen_i_1__0 
       (.I0(\txsync_fsm.txdlyen_i_2__0_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[5]),
        .I4(\txsync_fsm.txdlyen_reg_0 ),
        .O(\txsync_fsm.txdlyen_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \txsync_fsm.txdlyen_i_2__0 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_start_reg2),
        .O(\txsync_fsm.txdlyen_i_2__0_n_0 ));
  FDRE \txsync_fsm.txdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txdlyen_i_1__0_n_0 ),
        .Q(\txsync_fsm.txdlyen_reg_0 ),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \txsync_fsm.txsync_done_i_1 
       (.I0(txsync_done),
        .I1(\txsync_fsm.txdlyen_i_2__0_n_0 ),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(RST_TXSYNC_DONE),
        .O(\txsync_fsm.txsync_done_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \txsync_fsm.txsync_done_i_2__0 
       (.I0(Q[3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(txsync_done));
  FDRE \txsync_fsm.txsync_done_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_i_1_n_0 ),
        .Q(RST_TXSYNC_DONE),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXSYNC_START),
        .Q(txsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg1),
        .Q(txsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg2),
        .Q(txsync_start_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg1),
        .Q(txsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg2),
        .Q(txsyncdone_reg3),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_sync" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_39
   (Q,
    \txsync_fsm.txdlyen_reg_0 ,
    pipe_sync_fsm_rx,
    SYNC_RXDLYEN,
    \cplllock_reg1_reg[2] ,
    \cplllock_reg1_reg[2]_0 ,
    \cplllock_reg1_reg[2]_1 ,
    \cplllock_reg1_reg[2]_2 ,
    \cplllock_reg1_reg[2]_3 ,
    RST_TXSYNC_DONE,
    p_0_in7_in,
    p_1_in8_in,
    RST_CPLLRESET,
    SYNC_TXSYNC_START,
    pclk_sel_reg,
    \resetovrd_disble.reset_reg[4] ,
    SYNC_TXDLYSRESETDONE0,
    SYNC_TXPHINITDONE,
    SYNC_TXPHALIGNDONE,
    SYNC_RXSYNC_DONEM_IN,
    SYNC_GEN3,
    RST_RATE_IDLE,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXCDRLOCK,
    SYNC_RXSYNC_START,
    SYNC_RXDLYSRESETDONE0,
    SYNC_RXPHALIGNDONE_M,
    SYNC_RXPHALIGNDONE_S);
  output [5:0]Q;
  output \txsync_fsm.txdlyen_reg_0 ;
  output [6:0]pipe_sync_fsm_rx;
  output SYNC_RXDLYEN;
  output \cplllock_reg1_reg[2] ;
  output \cplllock_reg1_reg[2]_0 ;
  output \cplllock_reg1_reg[2]_1 ;
  output \cplllock_reg1_reg[2]_2 ;
  output \cplllock_reg1_reg[2]_3 ;
  output [0:0]RST_TXSYNC_DONE;
  input p_0_in7_in;
  input p_1_in8_in;
  input RST_CPLLRESET;
  input SYNC_TXSYNC_START;
  input pclk_sel_reg;
  input \resetovrd_disble.reset_reg[4] ;
  input SYNC_TXDLYSRESETDONE0;
  input SYNC_TXPHINITDONE;
  input SYNC_TXPHALIGNDONE;
  input SYNC_RXSYNC_DONEM_IN;
  input SYNC_GEN3;
  input [0:0]RST_RATE_IDLE;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input SYNC_RXCDRLOCK;
  input SYNC_RXSYNC_START;
  input SYNC_RXDLYSRESETDONE0;
  input SYNC_RXPHALIGNDONE_M;
  input SYNC_RXPHALIGNDONE_S;

  wire [5:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_TXSYNC_DONE;
  wire SYNC_GEN3;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXDLYEN;
  wire SYNC_RXDLYSRESETDONE0;
  wire SYNC_RXPHALIGNDONE_M;
  wire SYNC_RXPHALIGNDONE_S;
  wire SYNC_RXSYNC_DONEM_IN;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXDLYSRESETDONE0;
  wire SYNC_TXPHALIGNDONE;
  wire SYNC_TXPHINITDONE;
  wire SYNC_TXSYNC_START;
  wire \cplllock_reg1_reg[2] ;
  wire \cplllock_reg1_reg[2]_0 ;
  wire \cplllock_reg1_reg[2]_1 ;
  wire \cplllock_reg1_reg[2]_2 ;
  wire \cplllock_reg1_reg[2]_3 ;
  wire [5:0]fsm_tx;
  wire gen3_reg1;
  wire gen3_reg2;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire \gtx_channel.gtxe2_channel_i_i_57_n_0 ;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire p_0_in7_in;
  wire p_1_in8_in;
  wire pclk_sel_reg;
  wire [6:0]pipe_sync_fsm_rx;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxdlysresetdone_reg1;
  wire rxdlysresetdone_reg2;
  wire rxelecidle_reg1;
  wire rxelecidle_reg2;
  wire rxphaligndone_m_reg1;
  wire rxphaligndone_m_reg2;
  wire rxphaligndone_s_reg1;
  wire rxphaligndone_s_reg2;
  wire rxsync_donem_reg1;
  wire rxsync_donem_reg2;
  wire rxsync_start_reg1;
  wire rxsync_start_reg2;
  wire rxsyncdone_reg1;
  wire rxsyncdone_reg2;
  wire txdlysresetdone_reg1;
  wire txdlysresetdone_reg2;
  wire txdlysresetdone_reg3;
  wire txphaligndone_reg1;
  wire txphaligndone_reg2;
  wire txphaligndone_reg3;
  wire txphinitdone_reg1;
  wire txphinitdone_reg2;
  wire txphinitdone_reg3;
  wire txsync_done;
  wire \txsync_fsm.fsm_tx[4]_i_2__1_n_0 ;
  wire \txsync_fsm.fsm_tx[4]_i_3__1_n_0 ;
  wire \txsync_fsm.fsm_tx[5]_i_2__1_n_0 ;
  wire \txsync_fsm.txdlyen_i_1__1_n_0 ;
  wire \txsync_fsm.txdlyen_i_2__1_n_0 ;
  wire \txsync_fsm.txdlyen_reg_0 ;
  wire \txsync_fsm.txsync_done_i_1__0_n_0 ;
  wire txsync_start_reg1;
  wire txsync_start_reg2;
  wire txsync_start_reg3;
  wire txsyncdone_reg1;
  wire txsyncdone_reg2;
  wire txsyncdone_reg3;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_GEN3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00000020)) 
    \gtx_channel.gtxe2_channel_i_i_10 
       (.I0(rxsync_donem_reg2),
        .I1(pipe_sync_fsm_rx[5]),
        .I2(pipe_sync_fsm_rx[3]),
        .I3(pipe_sync_fsm_rx[2]),
        .I4(\gtx_channel.gtxe2_channel_i_i_57_n_0 ),
        .O(\cplllock_reg1_reg[2]_2 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_12__1 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(\cplllock_reg1_reg[2] ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_13__1 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[2]_1 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \gtx_channel.gtxe2_channel_i_i_14 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[2]_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \gtx_channel.gtxe2_channel_i_i_57 
       (.I0(pipe_sync_fsm_rx[0]),
        .I1(pipe_sync_fsm_rx[1]),
        .I2(pipe_sync_fsm_rx[6]),
        .I3(pipe_sync_fsm_rx[4]),
        .O(\gtx_channel.gtxe2_channel_i_i_57_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_9__1 
       (.I0(pipe_sync_fsm_rx[2]),
        .I1(pipe_sync_fsm_rx[3]),
        .I2(pipe_sync_fsm_rx[5]),
        .I3(\gtx_channel.gtxe2_channel_i_i_57_n_0 ),
        .O(\cplllock_reg1_reg[2]_3 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXCDRLOCK),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXDLYSRESETDONE0),
        .Q(rxdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxdlysresetdone_reg1),
        .Q(rxdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gt_rx_elec_idle_wire_filter),
        .Q(rxelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxelecidle_reg1),
        .Q(rxelecidle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXPHALIGNDONE_M),
        .Q(rxphaligndone_m_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_m_reg1),
        .Q(rxphaligndone_m_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXPHALIGNDONE_S),
        .Q(rxphaligndone_s_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_s_reg1),
        .Q(rxphaligndone_s_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONEM_IN),
        .Q(rxsync_donem_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_donem_reg1),
        .Q(rxsync_donem_reg2),
        .R(RST_CPLLRESET));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b1),
        .Q(pipe_sync_fsm_rx[0]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[1]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[2]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[3]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[4]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[5]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[6]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.rxdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(SYNC_RXDLYEN),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_START),
        .Q(rxsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_start_reg1),
        .Q(rxsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsyncdone_reg1),
        .Q(rxsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXDLYSRESETDONE0),
        .Q(txdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg1),
        .Q(txdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg2),
        .Q(txdlysresetdone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXPHALIGNDONE),
        .Q(txphaligndone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg1),
        .Q(txphaligndone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg2),
        .Q(txphaligndone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXPHINITDONE),
        .Q(txphinitdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg1),
        .Q(txphinitdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg2),
        .Q(txphinitdone_reg3),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'hF2FF)) 
    \txsync_fsm.fsm_tx[0]_i_1__1 
       (.I0(Q[0]),
        .I1(txsync_start_reg2),
        .I2(Q[5]),
        .I3(\txsync_fsm.fsm_tx[5]_i_2__1_n_0 ),
        .O(fsm_tx[0]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[1]_i_1__1 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__1_n_0 ),
        .I1(Q[0]),
        .I2(txsync_start_reg2),
        .I3(Q[1]),
        .I4(mmcm_lock_reg2),
        .O(fsm_tx[1]));
  LUT6 #(
    .INIT(64'hAAAA80AA80808080)) 
    \txsync_fsm.fsm_tx[2]_i_1__1 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__1_n_0 ),
        .I1(Q[1]),
        .I2(mmcm_lock_reg2),
        .I3(txdlysresetdone_reg2),
        .I4(txdlysresetdone_reg3),
        .I5(Q[2]),
        .O(fsm_tx[2]));
  LUT6 #(
    .INIT(64'h00800080AAAA0080)) 
    \txsync_fsm.fsm_tx[3]_i_1__1 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__1_n_0 ),
        .I1(Q[2]),
        .I2(txdlysresetdone_reg2),
        .I3(txdlysresetdone_reg3),
        .I4(Q[3]),
        .I5(\txsync_fsm.fsm_tx[4]_i_2__1_n_0 ),
        .O(fsm_tx[3]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[4]_i_1__1 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__1_n_0 ),
        .I1(\txsync_fsm.fsm_tx[4]_i_2__1_n_0 ),
        .I2(Q[3]),
        .I3(Q[4]),
        .I4(\txsync_fsm.fsm_tx[4]_i_3__1_n_0 ),
        .O(fsm_tx[4]));
  LUT4 #(
    .INIT(16'hF222)) 
    \txsync_fsm.fsm_tx[4]_i_2__1 
       (.I0(txphinitdone_reg2),
        .I1(txphinitdone_reg3),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_2__1_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \txsync_fsm.fsm_tx[4]_i_3__1 
       (.I0(txphaligndone_reg3),
        .I1(txphaligndone_reg2),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hAA20202000000000)) 
    \txsync_fsm.fsm_tx[5]_i_1__1 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__1_n_0 ),
        .I1(txphaligndone_reg3),
        .I2(txphaligndone_reg2),
        .I3(p_0_in7_in),
        .I4(p_1_in8_in),
        .I5(Q[4]),
        .O(fsm_tx[5]));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \txsync_fsm.fsm_tx[5]_i_2__1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(Q[5]),
        .O(\txsync_fsm.fsm_tx[5]_i_2__1_n_0 ));
  FDSE \txsync_fsm.fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[1]),
        .Q(Q[1]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[5]),
        .Q(Q[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00010000)) 
    \txsync_fsm.txdlyen_i_1__1 
       (.I0(\txsync_fsm.txdlyen_i_2__1_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[5]),
        .I4(\txsync_fsm.txdlyen_reg_0 ),
        .O(\txsync_fsm.txdlyen_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \txsync_fsm.txdlyen_i_2__1 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_start_reg2),
        .O(\txsync_fsm.txdlyen_i_2__1_n_0 ));
  FDRE \txsync_fsm.txdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txdlyen_i_1__1_n_0 ),
        .Q(\txsync_fsm.txdlyen_reg_0 ),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \txsync_fsm.txsync_done_i_1__0 
       (.I0(txsync_done),
        .I1(\txsync_fsm.txdlyen_i_2__1_n_0 ),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(RST_TXSYNC_DONE),
        .O(\txsync_fsm.txsync_done_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \txsync_fsm.txsync_done_i_2__1 
       (.I0(Q[3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(txsync_done));
  FDRE \txsync_fsm.txsync_done_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_i_1__0_n_0 ),
        .Q(RST_TXSYNC_DONE),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXSYNC_START),
        .Q(txsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg1),
        .Q(txsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg2),
        .Q(txsync_start_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg1),
        .Q(txsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg2),
        .Q(txsyncdone_reg3),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_sync" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_45
   (Q,
    \txsync_fsm.txdlyen_reg_0 ,
    pipe_sync_fsm_rx,
    SYNC_RXDLYEN,
    \cplllock_reg1_reg[3] ,
    \cplllock_reg1_reg[3]_0 ,
    \cplllock_reg1_reg[3]_1 ,
    \cplllock_reg1_reg[3]_2 ,
    \cplllock_reg1_reg[3]_3 ,
    RST_TXSYNC_DONE,
    p_0_in7_in,
    p_1_in8_in,
    RST_CPLLRESET,
    SYNC_TXSYNC_START,
    pclk_sel_reg,
    \resetovrd_disble.reset_reg[4] ,
    SYNC_TXDLYSRESETDONE0,
    txelecidle_reg2_reg,
    txsyncallin,
    SYNC_RXSYNC_DONEM_IN,
    SYNC_GEN3,
    RST_RATE_IDLE,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXCDRLOCK,
    SYNC_RXSYNC_START,
    SYNC_RXDLYSRESETDONE0,
    \resetovrd_disble.reset_reg[4]_0 ,
    \resetovrd_disble.reset_reg[4]_1 );
  output [5:0]Q;
  output \txsync_fsm.txdlyen_reg_0 ;
  output [6:0]pipe_sync_fsm_rx;
  output SYNC_RXDLYEN;
  output \cplllock_reg1_reg[3] ;
  output \cplllock_reg1_reg[3]_0 ;
  output \cplllock_reg1_reg[3]_1 ;
  output \cplllock_reg1_reg[3]_2 ;
  output \cplllock_reg1_reg[3]_3 ;
  output [0:0]RST_TXSYNC_DONE;
  input p_0_in7_in;
  input p_1_in8_in;
  input RST_CPLLRESET;
  input SYNC_TXSYNC_START;
  input pclk_sel_reg;
  input \resetovrd_disble.reset_reg[4] ;
  input SYNC_TXDLYSRESETDONE0;
  input txelecidle_reg2_reg;
  input txsyncallin;
  input SYNC_RXSYNC_DONEM_IN;
  input SYNC_GEN3;
  input [0:0]RST_RATE_IDLE;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input SYNC_RXCDRLOCK;
  input SYNC_RXSYNC_START;
  input SYNC_RXDLYSRESETDONE0;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input \resetovrd_disble.reset_reg[4]_1 ;

  wire [5:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_TXSYNC_DONE;
  wire SYNC_GEN3;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXDLYEN;
  wire SYNC_RXDLYSRESETDONE0;
  wire SYNC_RXSYNC_DONEM_IN;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXDLYSRESETDONE0;
  wire SYNC_TXSYNC_START;
  wire \cplllock_reg1_reg[3] ;
  wire \cplllock_reg1_reg[3]_0 ;
  wire \cplllock_reg1_reg[3]_1 ;
  wire \cplllock_reg1_reg[3]_2 ;
  wire \cplllock_reg1_reg[3]_3 ;
  wire [5:0]fsm_tx;
  wire gen3_reg1;
  wire gen3_reg2;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire \gtx_channel.gtxe2_channel_i_i_57__0_n_0 ;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire p_0_in7_in;
  wire p_1_in8_in;
  wire pclk_sel_reg;
  wire [6:0]pipe_sync_fsm_rx;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxdlysresetdone_reg1;
  wire rxdlysresetdone_reg2;
  wire rxelecidle_reg1;
  wire rxelecidle_reg2;
  wire rxphaligndone_m_reg1;
  wire rxphaligndone_m_reg2;
  wire rxphaligndone_s_reg1;
  wire rxphaligndone_s_reg2;
  wire rxsync_donem_reg1;
  wire rxsync_donem_reg2;
  wire rxsync_start_reg1;
  wire rxsync_start_reg2;
  wire rxsyncdone_reg1;
  wire rxsyncdone_reg2;
  wire txdlysresetdone_reg1;
  wire txdlysresetdone_reg2;
  wire txdlysresetdone_reg3;
  wire txelecidle_reg2_reg;
  wire txphaligndone_reg1;
  wire txphaligndone_reg2;
  wire txphaligndone_reg3;
  wire txphinitdone_reg1;
  wire txphinitdone_reg2;
  wire txphinitdone_reg3;
  wire txsync_done;
  wire \txsync_fsm.fsm_tx[4]_i_2__2_n_0 ;
  wire \txsync_fsm.fsm_tx[4]_i_3__2_n_0 ;
  wire \txsync_fsm.fsm_tx[5]_i_2__2_n_0 ;
  wire \txsync_fsm.txdlyen_i_1__2_n_0 ;
  wire \txsync_fsm.txdlyen_i_2__2_n_0 ;
  wire \txsync_fsm.txdlyen_reg_0 ;
  wire \txsync_fsm.txsync_done_i_1__1_n_0 ;
  wire txsync_start_reg1;
  wire txsync_start_reg2;
  wire txsync_start_reg3;
  wire txsyncallin;
  wire txsyncdone_reg1;
  wire txsyncdone_reg2;
  wire txsyncdone_reg3;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_GEN3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00000020)) 
    \gtx_channel.gtxe2_channel_i_i_10__0 
       (.I0(rxsync_donem_reg2),
        .I1(pipe_sync_fsm_rx[5]),
        .I2(pipe_sync_fsm_rx[3]),
        .I3(pipe_sync_fsm_rx[2]),
        .I4(\gtx_channel.gtxe2_channel_i_i_57__0_n_0 ),
        .O(\cplllock_reg1_reg[3]_2 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_12__2 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(\cplllock_reg1_reg[3] ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_13__2 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[3]_1 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \gtx_channel.gtxe2_channel_i_i_14__0 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[3]_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \gtx_channel.gtxe2_channel_i_i_57__0 
       (.I0(pipe_sync_fsm_rx[0]),
        .I1(pipe_sync_fsm_rx[1]),
        .I2(pipe_sync_fsm_rx[6]),
        .I3(pipe_sync_fsm_rx[4]),
        .O(\gtx_channel.gtxe2_channel_i_i_57__0_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_9__2 
       (.I0(pipe_sync_fsm_rx[2]),
        .I1(pipe_sync_fsm_rx[3]),
        .I2(pipe_sync_fsm_rx[5]),
        .I3(\gtx_channel.gtxe2_channel_i_i_57__0_n_0 ),
        .O(\cplllock_reg1_reg[3]_3 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXCDRLOCK),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXDLYSRESETDONE0),
        .Q(rxdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxdlysresetdone_reg1),
        .Q(rxdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gt_rx_elec_idle_wire_filter),
        .Q(rxelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxelecidle_reg1),
        .Q(rxelecidle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxphaligndone_m_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_m_reg1),
        .Q(rxphaligndone_m_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxphaligndone_s_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_s_reg1),
        .Q(rxphaligndone_s_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_DONEM_IN),
        .Q(rxsync_donem_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_donem_reg1),
        .Q(rxsync_donem_reg2),
        .R(RST_CPLLRESET));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b1),
        .Q(pipe_sync_fsm_rx[0]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[1]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[2]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[3]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[4]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[5]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[6]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.rxdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(SYNC_RXDLYEN),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_START),
        .Q(rxsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_start_reg1),
        .Q(rxsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsyncdone_reg1),
        .Q(rxsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXDLYSRESETDONE0),
        .Q(txdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg1),
        .Q(txdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg2),
        .Q(txdlysresetdone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncallin),
        .Q(txphaligndone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg1),
        .Q(txphaligndone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg2),
        .Q(txphaligndone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg2_reg),
        .Q(txphinitdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg1),
        .Q(txphinitdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg2),
        .Q(txphinitdone_reg3),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'hF2FF)) 
    \txsync_fsm.fsm_tx[0]_i_1__2 
       (.I0(Q[0]),
        .I1(txsync_start_reg2),
        .I2(Q[5]),
        .I3(\txsync_fsm.fsm_tx[5]_i_2__2_n_0 ),
        .O(fsm_tx[0]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[1]_i_1__2 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__2_n_0 ),
        .I1(Q[0]),
        .I2(txsync_start_reg2),
        .I3(Q[1]),
        .I4(mmcm_lock_reg2),
        .O(fsm_tx[1]));
  LUT6 #(
    .INIT(64'hAAAA80AA80808080)) 
    \txsync_fsm.fsm_tx[2]_i_1__2 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__2_n_0 ),
        .I1(Q[1]),
        .I2(mmcm_lock_reg2),
        .I3(txdlysresetdone_reg2),
        .I4(txdlysresetdone_reg3),
        .I5(Q[2]),
        .O(fsm_tx[2]));
  LUT6 #(
    .INIT(64'h00800080AAAA0080)) 
    \txsync_fsm.fsm_tx[3]_i_1__2 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__2_n_0 ),
        .I1(Q[2]),
        .I2(txdlysresetdone_reg2),
        .I3(txdlysresetdone_reg3),
        .I4(Q[3]),
        .I5(\txsync_fsm.fsm_tx[4]_i_2__2_n_0 ),
        .O(fsm_tx[3]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[4]_i_1__2 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__2_n_0 ),
        .I1(\txsync_fsm.fsm_tx[4]_i_2__2_n_0 ),
        .I2(Q[3]),
        .I3(Q[4]),
        .I4(\txsync_fsm.fsm_tx[4]_i_3__2_n_0 ),
        .O(fsm_tx[4]));
  LUT4 #(
    .INIT(16'hF222)) 
    \txsync_fsm.fsm_tx[4]_i_2__2 
       (.I0(txphinitdone_reg2),
        .I1(txphinitdone_reg3),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_2__2_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \txsync_fsm.fsm_tx[4]_i_3__2 
       (.I0(txphaligndone_reg3),
        .I1(txphaligndone_reg2),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hAA20202000000000)) 
    \txsync_fsm.fsm_tx[5]_i_1__2 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__2_n_0 ),
        .I1(txphaligndone_reg3),
        .I2(txphaligndone_reg2),
        .I3(p_0_in7_in),
        .I4(p_1_in8_in),
        .I5(Q[4]),
        .O(fsm_tx[5]));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \txsync_fsm.fsm_tx[5]_i_2__2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(Q[5]),
        .O(\txsync_fsm.fsm_tx[5]_i_2__2_n_0 ));
  FDSE \txsync_fsm.fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[1]),
        .Q(Q[1]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[5]),
        .Q(Q[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00010000)) 
    \txsync_fsm.txdlyen_i_1__2 
       (.I0(\txsync_fsm.txdlyen_i_2__2_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[5]),
        .I4(\txsync_fsm.txdlyen_reg_0 ),
        .O(\txsync_fsm.txdlyen_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \txsync_fsm.txdlyen_i_2__2 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_start_reg2),
        .O(\txsync_fsm.txdlyen_i_2__2_n_0 ));
  FDRE \txsync_fsm.txdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txdlyen_i_1__2_n_0 ),
        .Q(\txsync_fsm.txdlyen_reg_0 ),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \txsync_fsm.txsync_done_i_1__1 
       (.I0(txsync_done),
        .I1(\txsync_fsm.txdlyen_i_2__2_n_0 ),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(RST_TXSYNC_DONE),
        .O(\txsync_fsm.txsync_done_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \txsync_fsm.txsync_done_i_2__2 
       (.I0(Q[3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(txsync_done));
  FDRE \txsync_fsm.txsync_done_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_i_1__1_n_0 ),
        .Q(RST_TXSYNC_DONE),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXSYNC_START),
        .Q(txsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg1),
        .Q(txsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg2),
        .Q(txsync_start_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg1),
        .Q(txsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg2),
        .Q(txsyncdone_reg3),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_sync" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_52
   (Q,
    \txsync_fsm.txdlyen_reg_0 ,
    pipe_sync_fsm_rx,
    SYNC_RXDLYEN,
    \cplllock_reg1_reg[4] ,
    \cplllock_reg1_reg[4]_0 ,
    \cplllock_reg1_reg[4]_1 ,
    \cplllock_reg1_reg[4]_2 ,
    \cplllock_reg1_reg[4]_3 ,
    RST_TXSYNC_DONE,
    p_0_in7_in,
    p_1_in8_in,
    RST_CPLLRESET,
    SYNC_TXSYNC_START,
    pclk_sel_reg,
    \resetovrd_disble.reset_reg[4] ,
    SYNC_TXDLYSRESETDONE0,
    txelecidle_reg2_reg,
    txsyncallin,
    \rxsync_fsm_disable.fsm_rx_reg[2]_0 ,
    SYNC_GEN3,
    RST_RATE_IDLE,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXCDRLOCK,
    SYNC_RXSYNC_START,
    SYNC_RXDLYSRESETDONE0,
    \resetovrd_disble.reset_reg[4]_0 ,
    \resetovrd_disble.reset_reg[4]_1 );
  output [5:0]Q;
  output \txsync_fsm.txdlyen_reg_0 ;
  output [6:0]pipe_sync_fsm_rx;
  output SYNC_RXDLYEN;
  output \cplllock_reg1_reg[4] ;
  output \cplllock_reg1_reg[4]_0 ;
  output \cplllock_reg1_reg[4]_1 ;
  output \cplllock_reg1_reg[4]_2 ;
  output \cplllock_reg1_reg[4]_3 ;
  output [0:0]RST_TXSYNC_DONE;
  input p_0_in7_in;
  input p_1_in8_in;
  input RST_CPLLRESET;
  input SYNC_TXSYNC_START;
  input pclk_sel_reg;
  input \resetovrd_disble.reset_reg[4] ;
  input SYNC_TXDLYSRESETDONE0;
  input txelecidle_reg2_reg;
  input txsyncallin;
  input \rxsync_fsm_disable.fsm_rx_reg[2]_0 ;
  input SYNC_GEN3;
  input [0:0]RST_RATE_IDLE;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input SYNC_RXCDRLOCK;
  input SYNC_RXSYNC_START;
  input SYNC_RXDLYSRESETDONE0;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input \resetovrd_disble.reset_reg[4]_1 ;

  wire [5:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_TXSYNC_DONE;
  wire SYNC_GEN3;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXDLYEN;
  wire SYNC_RXDLYSRESETDONE0;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXDLYSRESETDONE0;
  wire SYNC_TXSYNC_START;
  wire \cplllock_reg1_reg[4] ;
  wire \cplllock_reg1_reg[4]_0 ;
  wire \cplllock_reg1_reg[4]_1 ;
  wire \cplllock_reg1_reg[4]_2 ;
  wire \cplllock_reg1_reg[4]_3 ;
  wire [5:0]fsm_tx;
  wire gen3_reg1;
  wire gen3_reg2;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire \gtx_channel.gtxe2_channel_i_i_56__1_n_0 ;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire p_0_in7_in;
  wire p_1_in8_in;
  wire pclk_sel_reg;
  wire [6:0]pipe_sync_fsm_rx;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxdlysresetdone_reg1;
  wire rxdlysresetdone_reg2;
  wire rxelecidle_reg1;
  wire rxelecidle_reg2;
  wire rxphaligndone_m_reg1;
  wire rxphaligndone_m_reg2;
  wire rxphaligndone_s_reg1;
  wire rxphaligndone_s_reg2;
  wire rxsync_donem_reg1;
  wire rxsync_donem_reg2;
  wire \rxsync_fsm_disable.fsm_rx_reg[2]_0 ;
  wire rxsync_start_reg1;
  wire rxsync_start_reg2;
  wire rxsyncdone_reg1;
  wire rxsyncdone_reg2;
  wire txdlysresetdone_reg1;
  wire txdlysresetdone_reg2;
  wire txdlysresetdone_reg3;
  wire txelecidle_reg2_reg;
  wire txphaligndone_reg1;
  wire txphaligndone_reg2;
  wire txphaligndone_reg3;
  wire txphinitdone_reg1;
  wire txphinitdone_reg2;
  wire txphinitdone_reg3;
  wire txsync_done;
  wire \txsync_fsm.fsm_tx[4]_i_2__3_n_0 ;
  wire \txsync_fsm.fsm_tx[4]_i_3__3_n_0 ;
  wire \txsync_fsm.fsm_tx[5]_i_2__3_n_0 ;
  wire \txsync_fsm.txdlyen_i_1__3_n_0 ;
  wire \txsync_fsm.txdlyen_i_2__3_n_0 ;
  wire \txsync_fsm.txdlyen_reg_0 ;
  wire \txsync_fsm.txsync_done_i_1__2_n_0 ;
  wire txsync_start_reg1;
  wire txsync_start_reg2;
  wire txsync_start_reg3;
  wire txsyncallin;
  wire txsyncdone_reg1;
  wire txsyncdone_reg2;
  wire txsyncdone_reg3;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_GEN3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_11__1 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(\cplllock_reg1_reg[4] ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_12__3 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[4]_1 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \gtx_channel.gtxe2_channel_i_i_13__3 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[4]_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \gtx_channel.gtxe2_channel_i_i_56__1 
       (.I0(pipe_sync_fsm_rx[0]),
        .I1(pipe_sync_fsm_rx[1]),
        .I2(pipe_sync_fsm_rx[6]),
        .I3(pipe_sync_fsm_rx[4]),
        .O(\gtx_channel.gtxe2_channel_i_i_56__1_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_8__1 
       (.I0(pipe_sync_fsm_rx[2]),
        .I1(pipe_sync_fsm_rx[3]),
        .I2(pipe_sync_fsm_rx[5]),
        .I3(\gtx_channel.gtxe2_channel_i_i_56__1_n_0 ),
        .O(\cplllock_reg1_reg[4]_3 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \gtx_channel.gtxe2_channel_i_i_9__3 
       (.I0(rxsync_donem_reg2),
        .I1(pipe_sync_fsm_rx[5]),
        .I2(pipe_sync_fsm_rx[3]),
        .I3(pipe_sync_fsm_rx[2]),
        .I4(\gtx_channel.gtxe2_channel_i_i_56__1_n_0 ),
        .O(\cplllock_reg1_reg[4]_2 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXCDRLOCK),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXDLYSRESETDONE0),
        .Q(rxdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxdlysresetdone_reg1),
        .Q(rxdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gt_rx_elec_idle_wire_filter),
        .Q(rxelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxelecidle_reg1),
        .Q(rxelecidle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxphaligndone_m_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_m_reg1),
        .Q(rxphaligndone_m_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxphaligndone_s_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_s_reg1),
        .Q(rxphaligndone_s_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxsync_fsm_disable.fsm_rx_reg[2]_0 ),
        .Q(rxsync_donem_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_donem_reg1),
        .Q(rxsync_donem_reg2),
        .R(RST_CPLLRESET));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b1),
        .Q(pipe_sync_fsm_rx[0]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[1]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[2]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[3]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[4]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[5]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[6]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.rxdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(SYNC_RXDLYEN),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_START),
        .Q(rxsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_start_reg1),
        .Q(rxsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsyncdone_reg1),
        .Q(rxsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXDLYSRESETDONE0),
        .Q(txdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg1),
        .Q(txdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg2),
        .Q(txdlysresetdone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncallin),
        .Q(txphaligndone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg1),
        .Q(txphaligndone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg2),
        .Q(txphaligndone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg2_reg),
        .Q(txphinitdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg1),
        .Q(txphinitdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg2),
        .Q(txphinitdone_reg3),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'hF2FF)) 
    \txsync_fsm.fsm_tx[0]_i_1__3 
       (.I0(Q[0]),
        .I1(txsync_start_reg2),
        .I2(Q[5]),
        .I3(\txsync_fsm.fsm_tx[5]_i_2__3_n_0 ),
        .O(fsm_tx[0]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[1]_i_1__3 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__3_n_0 ),
        .I1(Q[0]),
        .I2(txsync_start_reg2),
        .I3(Q[1]),
        .I4(mmcm_lock_reg2),
        .O(fsm_tx[1]));
  LUT6 #(
    .INIT(64'hAAAA80AA80808080)) 
    \txsync_fsm.fsm_tx[2]_i_1__3 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__3_n_0 ),
        .I1(Q[1]),
        .I2(mmcm_lock_reg2),
        .I3(txdlysresetdone_reg2),
        .I4(txdlysresetdone_reg3),
        .I5(Q[2]),
        .O(fsm_tx[2]));
  LUT6 #(
    .INIT(64'h00800080AAAA0080)) 
    \txsync_fsm.fsm_tx[3]_i_1__3 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__3_n_0 ),
        .I1(Q[2]),
        .I2(txdlysresetdone_reg2),
        .I3(txdlysresetdone_reg3),
        .I4(Q[3]),
        .I5(\txsync_fsm.fsm_tx[4]_i_2__3_n_0 ),
        .O(fsm_tx[3]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[4]_i_1__3 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__3_n_0 ),
        .I1(\txsync_fsm.fsm_tx[4]_i_2__3_n_0 ),
        .I2(Q[3]),
        .I3(Q[4]),
        .I4(\txsync_fsm.fsm_tx[4]_i_3__3_n_0 ),
        .O(fsm_tx[4]));
  LUT4 #(
    .INIT(16'hF222)) 
    \txsync_fsm.fsm_tx[4]_i_2__3 
       (.I0(txphinitdone_reg2),
        .I1(txphinitdone_reg3),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_2__3_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \txsync_fsm.fsm_tx[4]_i_3__3 
       (.I0(txphaligndone_reg3),
        .I1(txphaligndone_reg2),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hAA20202000000000)) 
    \txsync_fsm.fsm_tx[5]_i_1__3 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__3_n_0 ),
        .I1(txphaligndone_reg3),
        .I2(txphaligndone_reg2),
        .I3(p_0_in7_in),
        .I4(p_1_in8_in),
        .I5(Q[4]),
        .O(fsm_tx[5]));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \txsync_fsm.fsm_tx[5]_i_2__3 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(Q[5]),
        .O(\txsync_fsm.fsm_tx[5]_i_2__3_n_0 ));
  FDSE \txsync_fsm.fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[1]),
        .Q(Q[1]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[5]),
        .Q(Q[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00010000)) 
    \txsync_fsm.txdlyen_i_1__3 
       (.I0(\txsync_fsm.txdlyen_i_2__3_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[5]),
        .I4(\txsync_fsm.txdlyen_reg_0 ),
        .O(\txsync_fsm.txdlyen_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \txsync_fsm.txdlyen_i_2__3 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_start_reg2),
        .O(\txsync_fsm.txdlyen_i_2__3_n_0 ));
  FDRE \txsync_fsm.txdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txdlyen_i_1__3_n_0 ),
        .Q(\txsync_fsm.txdlyen_reg_0 ),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \txsync_fsm.txsync_done_i_1__2 
       (.I0(txsync_done),
        .I1(\txsync_fsm.txdlyen_i_2__3_n_0 ),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(RST_TXSYNC_DONE),
        .O(\txsync_fsm.txsync_done_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \txsync_fsm.txsync_done_i_2__3 
       (.I0(Q[3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(txsync_done));
  FDRE \txsync_fsm.txsync_done_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_i_1__2_n_0 ),
        .Q(RST_TXSYNC_DONE),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXSYNC_START),
        .Q(txsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg1),
        .Q(txsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg2),
        .Q(txsync_start_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg1),
        .Q(txsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg2),
        .Q(txsyncdone_reg3),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_sync" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_58
   (Q,
    \txsync_fsm.txdlyen_reg_0 ,
    pipe_sync_fsm_rx,
    SYNC_RXDLYEN,
    \cplllock_reg1_reg[5] ,
    \cplllock_reg1_reg[5]_0 ,
    \cplllock_reg1_reg[5]_1 ,
    \cplllock_reg1_reg[5]_2 ,
    \cplllock_reg1_reg[5]_3 ,
    RST_TXSYNC_DONE,
    p_0_in7_in,
    p_1_in8_in,
    RST_CPLLRESET,
    SYNC_TXSYNC_START,
    pclk_sel_reg,
    \resetovrd_disble.reset_reg[4] ,
    SYNC_TXDLYSRESETDONE0,
    txelecidle_reg2_reg,
    txsyncallin,
    \rxsync_fsm_disable.fsm_rx_reg[2]_0 ,
    SYNC_GEN3,
    RST_RATE_IDLE,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXCDRLOCK,
    SYNC_RXSYNC_START,
    SYNC_RXDLYSRESETDONE0,
    \resetovrd_disble.reset_reg[4]_0 ,
    \resetovrd_disble.reset_reg[4]_1 );
  output [5:0]Q;
  output \txsync_fsm.txdlyen_reg_0 ;
  output [6:0]pipe_sync_fsm_rx;
  output SYNC_RXDLYEN;
  output \cplllock_reg1_reg[5] ;
  output \cplllock_reg1_reg[5]_0 ;
  output \cplllock_reg1_reg[5]_1 ;
  output \cplllock_reg1_reg[5]_2 ;
  output \cplllock_reg1_reg[5]_3 ;
  output [0:0]RST_TXSYNC_DONE;
  input p_0_in7_in;
  input p_1_in8_in;
  input RST_CPLLRESET;
  input SYNC_TXSYNC_START;
  input pclk_sel_reg;
  input \resetovrd_disble.reset_reg[4] ;
  input SYNC_TXDLYSRESETDONE0;
  input txelecidle_reg2_reg;
  input txsyncallin;
  input \rxsync_fsm_disable.fsm_rx_reg[2]_0 ;
  input SYNC_GEN3;
  input [0:0]RST_RATE_IDLE;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input SYNC_RXCDRLOCK;
  input SYNC_RXSYNC_START;
  input SYNC_RXDLYSRESETDONE0;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input \resetovrd_disble.reset_reg[4]_1 ;

  wire [5:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_TXSYNC_DONE;
  wire SYNC_GEN3;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXDLYEN;
  wire SYNC_RXDLYSRESETDONE0;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXDLYSRESETDONE0;
  wire SYNC_TXSYNC_START;
  wire \cplllock_reg1_reg[5] ;
  wire \cplllock_reg1_reg[5]_0 ;
  wire \cplllock_reg1_reg[5]_1 ;
  wire \cplllock_reg1_reg[5]_2 ;
  wire \cplllock_reg1_reg[5]_3 ;
  wire [5:0]fsm_tx;
  wire gen3_reg1;
  wire gen3_reg2;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire \gtx_channel.gtxe2_channel_i_i_56__2_n_0 ;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire p_0_in7_in;
  wire p_1_in8_in;
  wire pclk_sel_reg;
  wire [6:0]pipe_sync_fsm_rx;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxdlysresetdone_reg1;
  wire rxdlysresetdone_reg2;
  wire rxelecidle_reg1;
  wire rxelecidle_reg2;
  wire rxphaligndone_m_reg1;
  wire rxphaligndone_m_reg2;
  wire rxphaligndone_s_reg1;
  wire rxphaligndone_s_reg2;
  wire rxsync_donem_reg1;
  wire rxsync_donem_reg2;
  wire \rxsync_fsm_disable.fsm_rx_reg[2]_0 ;
  wire rxsync_start_reg1;
  wire rxsync_start_reg2;
  wire rxsyncdone_reg1;
  wire rxsyncdone_reg2;
  wire txdlysresetdone_reg1;
  wire txdlysresetdone_reg2;
  wire txdlysresetdone_reg3;
  wire txelecidle_reg2_reg;
  wire txphaligndone_reg1;
  wire txphaligndone_reg2;
  wire txphaligndone_reg3;
  wire txphinitdone_reg1;
  wire txphinitdone_reg2;
  wire txphinitdone_reg3;
  wire txsync_done;
  wire \txsync_fsm.fsm_tx[4]_i_2__4_n_0 ;
  wire \txsync_fsm.fsm_tx[4]_i_3__4_n_0 ;
  wire \txsync_fsm.fsm_tx[5]_i_2__4_n_0 ;
  wire \txsync_fsm.txdlyen_i_1__4_n_0 ;
  wire \txsync_fsm.txdlyen_i_2__4_n_0 ;
  wire \txsync_fsm.txdlyen_reg_0 ;
  wire \txsync_fsm.txsync_done_i_1__3_n_0 ;
  wire txsync_start_reg1;
  wire txsync_start_reg2;
  wire txsync_start_reg3;
  wire txsyncallin;
  wire txsyncdone_reg1;
  wire txsyncdone_reg2;
  wire txsyncdone_reg3;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_GEN3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_11__2 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(\cplllock_reg1_reg[5] ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_12__4 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[5]_1 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \gtx_channel.gtxe2_channel_i_i_13__4 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[5]_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \gtx_channel.gtxe2_channel_i_i_56__2 
       (.I0(pipe_sync_fsm_rx[0]),
        .I1(pipe_sync_fsm_rx[1]),
        .I2(pipe_sync_fsm_rx[6]),
        .I3(pipe_sync_fsm_rx[4]),
        .O(\gtx_channel.gtxe2_channel_i_i_56__2_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_8__2 
       (.I0(pipe_sync_fsm_rx[2]),
        .I1(pipe_sync_fsm_rx[3]),
        .I2(pipe_sync_fsm_rx[5]),
        .I3(\gtx_channel.gtxe2_channel_i_i_56__2_n_0 ),
        .O(\cplllock_reg1_reg[5]_3 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \gtx_channel.gtxe2_channel_i_i_9__4 
       (.I0(rxsync_donem_reg2),
        .I1(pipe_sync_fsm_rx[5]),
        .I2(pipe_sync_fsm_rx[3]),
        .I3(pipe_sync_fsm_rx[2]),
        .I4(\gtx_channel.gtxe2_channel_i_i_56__2_n_0 ),
        .O(\cplllock_reg1_reg[5]_2 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXCDRLOCK),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXDLYSRESETDONE0),
        .Q(rxdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxdlysresetdone_reg1),
        .Q(rxdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gt_rx_elec_idle_wire_filter),
        .Q(rxelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxelecidle_reg1),
        .Q(rxelecidle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxphaligndone_m_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_m_reg1),
        .Q(rxphaligndone_m_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxphaligndone_s_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_s_reg1),
        .Q(rxphaligndone_s_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxsync_fsm_disable.fsm_rx_reg[2]_0 ),
        .Q(rxsync_donem_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_donem_reg1),
        .Q(rxsync_donem_reg2),
        .R(RST_CPLLRESET));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b1),
        .Q(pipe_sync_fsm_rx[0]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[1]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[2]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[3]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[4]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[5]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[6]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.rxdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(SYNC_RXDLYEN),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_START),
        .Q(rxsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_start_reg1),
        .Q(rxsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsyncdone_reg1),
        .Q(rxsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXDLYSRESETDONE0),
        .Q(txdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg1),
        .Q(txdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg2),
        .Q(txdlysresetdone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncallin),
        .Q(txphaligndone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg1),
        .Q(txphaligndone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg2),
        .Q(txphaligndone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg2_reg),
        .Q(txphinitdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg1),
        .Q(txphinitdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg2),
        .Q(txphinitdone_reg3),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'hF2FF)) 
    \txsync_fsm.fsm_tx[0]_i_1__4 
       (.I0(Q[0]),
        .I1(txsync_start_reg2),
        .I2(Q[5]),
        .I3(\txsync_fsm.fsm_tx[5]_i_2__4_n_0 ),
        .O(fsm_tx[0]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[1]_i_1__4 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__4_n_0 ),
        .I1(Q[0]),
        .I2(txsync_start_reg2),
        .I3(Q[1]),
        .I4(mmcm_lock_reg2),
        .O(fsm_tx[1]));
  LUT6 #(
    .INIT(64'hAAAA80AA80808080)) 
    \txsync_fsm.fsm_tx[2]_i_1__4 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__4_n_0 ),
        .I1(Q[1]),
        .I2(mmcm_lock_reg2),
        .I3(txdlysresetdone_reg2),
        .I4(txdlysresetdone_reg3),
        .I5(Q[2]),
        .O(fsm_tx[2]));
  LUT6 #(
    .INIT(64'h00800080AAAA0080)) 
    \txsync_fsm.fsm_tx[3]_i_1__4 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__4_n_0 ),
        .I1(Q[2]),
        .I2(txdlysresetdone_reg2),
        .I3(txdlysresetdone_reg3),
        .I4(Q[3]),
        .I5(\txsync_fsm.fsm_tx[4]_i_2__4_n_0 ),
        .O(fsm_tx[3]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[4]_i_1__4 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__4_n_0 ),
        .I1(\txsync_fsm.fsm_tx[4]_i_2__4_n_0 ),
        .I2(Q[3]),
        .I3(Q[4]),
        .I4(\txsync_fsm.fsm_tx[4]_i_3__4_n_0 ),
        .O(fsm_tx[4]));
  LUT4 #(
    .INIT(16'hF222)) 
    \txsync_fsm.fsm_tx[4]_i_2__4 
       (.I0(txphinitdone_reg2),
        .I1(txphinitdone_reg3),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_2__4_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \txsync_fsm.fsm_tx[4]_i_3__4 
       (.I0(txphaligndone_reg3),
        .I1(txphaligndone_reg2),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hAA20202000000000)) 
    \txsync_fsm.fsm_tx[5]_i_1__4 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__4_n_0 ),
        .I1(txphaligndone_reg3),
        .I2(txphaligndone_reg2),
        .I3(p_0_in7_in),
        .I4(p_1_in8_in),
        .I5(Q[4]),
        .O(fsm_tx[5]));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \txsync_fsm.fsm_tx[5]_i_2__4 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(Q[5]),
        .O(\txsync_fsm.fsm_tx[5]_i_2__4_n_0 ));
  FDSE \txsync_fsm.fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[1]),
        .Q(Q[1]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[5]),
        .Q(Q[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00010000)) 
    \txsync_fsm.txdlyen_i_1__4 
       (.I0(\txsync_fsm.txdlyen_i_2__4_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[5]),
        .I4(\txsync_fsm.txdlyen_reg_0 ),
        .O(\txsync_fsm.txdlyen_i_1__4_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \txsync_fsm.txdlyen_i_2__4 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_start_reg2),
        .O(\txsync_fsm.txdlyen_i_2__4_n_0 ));
  FDRE \txsync_fsm.txdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txdlyen_i_1__4_n_0 ),
        .Q(\txsync_fsm.txdlyen_reg_0 ),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \txsync_fsm.txsync_done_i_1__3 
       (.I0(txsync_done),
        .I1(\txsync_fsm.txdlyen_i_2__4_n_0 ),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(RST_TXSYNC_DONE),
        .O(\txsync_fsm.txsync_done_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \txsync_fsm.txsync_done_i_2__4 
       (.I0(Q[3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(txsync_done));
  FDRE \txsync_fsm.txsync_done_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_i_1__3_n_0 ),
        .Q(RST_TXSYNC_DONE),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXSYNC_START),
        .Q(txsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg1),
        .Q(txsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg2),
        .Q(txsync_start_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg1),
        .Q(txsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg2),
        .Q(txsyncdone_reg3),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_sync" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_64
   (Q,
    \txsync_fsm.txdlyen_reg_0 ,
    pipe_sync_fsm_rx,
    SYNC_RXDLYEN,
    \cplllock_reg1_reg[6] ,
    \cplllock_reg1_reg[6]_0 ,
    \cplllock_reg1_reg[6]_1 ,
    \cplllock_reg1_reg[6]_2 ,
    \cplllock_reg1_reg[6]_3 ,
    RST_TXSYNC_DONE,
    p_0_in7_in,
    p_1_in8_in,
    RST_CPLLRESET,
    SYNC_TXSYNC_START,
    pclk_sel_reg,
    \resetovrd_disble.reset_reg[4] ,
    \resetovrd_disble.reset_reg[4]_0 ,
    txelecidle_reg2_reg,
    txsyncallin,
    \rxsync_fsm_disable.fsm_rx_reg[2]_0 ,
    SYNC_GEN3,
    SYNC_RATE_IDLE,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXCDRLOCK,
    SYNC_RXSYNC_START,
    \resetovrd_disble.reset_reg[4]_1 ,
    \resetovrd_disble.reset_reg[4]_2 ,
    \resetovrd_disble.reset_reg[4]_3 );
  output [5:0]Q;
  output \txsync_fsm.txdlyen_reg_0 ;
  output [6:0]pipe_sync_fsm_rx;
  output SYNC_RXDLYEN;
  output \cplllock_reg1_reg[6] ;
  output \cplllock_reg1_reg[6]_0 ;
  output \cplllock_reg1_reg[6]_1 ;
  output \cplllock_reg1_reg[6]_2 ;
  output \cplllock_reg1_reg[6]_3 ;
  output [0:0]RST_TXSYNC_DONE;
  input p_0_in7_in;
  input p_1_in8_in;
  input RST_CPLLRESET;
  input SYNC_TXSYNC_START;
  input pclk_sel_reg;
  input \resetovrd_disble.reset_reg[4] ;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input txelecidle_reg2_reg;
  input txsyncallin;
  input \rxsync_fsm_disable.fsm_rx_reg[2]_0 ;
  input SYNC_GEN3;
  input SYNC_RATE_IDLE;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input SYNC_RXCDRLOCK;
  input SYNC_RXSYNC_START;
  input \resetovrd_disble.reset_reg[4]_1 ;
  input \resetovrd_disble.reset_reg[4]_2 ;
  input \resetovrd_disble.reset_reg[4]_3 ;

  wire [5:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_TXSYNC_DONE;
  wire SYNC_GEN3;
  wire SYNC_RATE_IDLE;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXDLYEN;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXSYNC_START;
  wire \cplllock_reg1_reg[6] ;
  wire \cplllock_reg1_reg[6]_0 ;
  wire \cplllock_reg1_reg[6]_1 ;
  wire \cplllock_reg1_reg[6]_2 ;
  wire \cplllock_reg1_reg[6]_3 ;
  wire [5:0]fsm_tx;
  wire gen3_reg1;
  wire gen3_reg2;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire \gtx_channel.gtxe2_channel_i_i_57__1_n_0 ;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire p_0_in7_in;
  wire p_1_in8_in;
  wire pclk_sel_reg;
  wire [6:0]pipe_sync_fsm_rx;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire \resetovrd_disble.reset_reg[4]_2 ;
  wire \resetovrd_disble.reset_reg[4]_3 ;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxdlysresetdone_reg1;
  wire rxdlysresetdone_reg2;
  wire rxelecidle_reg1;
  wire rxelecidle_reg2;
  wire rxphaligndone_m_reg1;
  wire rxphaligndone_m_reg2;
  wire rxphaligndone_s_reg1;
  wire rxphaligndone_s_reg2;
  wire rxsync_donem_reg1;
  wire rxsync_donem_reg2;
  wire \rxsync_fsm_disable.fsm_rx_reg[2]_0 ;
  wire rxsync_start_reg1;
  wire rxsync_start_reg2;
  wire rxsyncdone_reg1;
  wire rxsyncdone_reg2;
  wire txdlysresetdone_reg1;
  wire txdlysresetdone_reg2;
  wire txdlysresetdone_reg3;
  wire txelecidle_reg2_reg;
  wire txphaligndone_reg1;
  wire txphaligndone_reg2;
  wire txphaligndone_reg3;
  wire txphinitdone_reg1;
  wire txphinitdone_reg2;
  wire txphinitdone_reg3;
  wire txsync_done;
  wire \txsync_fsm.fsm_tx[4]_i_2__5_n_0 ;
  wire \txsync_fsm.fsm_tx[4]_i_3__5_n_0 ;
  wire \txsync_fsm.fsm_tx[5]_i_2__5_n_0 ;
  wire \txsync_fsm.txdlyen_i_1__5_n_0 ;
  wire \txsync_fsm.txdlyen_i_2__5_n_0 ;
  wire \txsync_fsm.txdlyen_reg_0 ;
  wire \txsync_fsm.txsync_done_i_1__4_n_0 ;
  wire txsync_start_reg1;
  wire txsync_start_reg2;
  wire txsync_start_reg3;
  wire txsyncallin;
  wire txsyncdone_reg1;
  wire txsyncdone_reg2;
  wire txsyncdone_reg3;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_GEN3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00000020)) 
    \gtx_channel.gtxe2_channel_i_i_10__1 
       (.I0(rxsync_donem_reg2),
        .I1(pipe_sync_fsm_rx[5]),
        .I2(pipe_sync_fsm_rx[3]),
        .I3(pipe_sync_fsm_rx[2]),
        .I4(\gtx_channel.gtxe2_channel_i_i_57__1_n_0 ),
        .O(\cplllock_reg1_reg[6]_2 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_12__5 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(\cplllock_reg1_reg[6] ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_13__5 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[6]_1 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \gtx_channel.gtxe2_channel_i_i_14__1 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[6]_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \gtx_channel.gtxe2_channel_i_i_57__1 
       (.I0(pipe_sync_fsm_rx[0]),
        .I1(pipe_sync_fsm_rx[1]),
        .I2(pipe_sync_fsm_rx[6]),
        .I3(pipe_sync_fsm_rx[4]),
        .O(\gtx_channel.gtxe2_channel_i_i_57__1_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_9__5 
       (.I0(pipe_sync_fsm_rx[2]),
        .I1(pipe_sync_fsm_rx[3]),
        .I2(pipe_sync_fsm_rx[5]),
        .I3(\gtx_channel.gtxe2_channel_i_i_57__1_n_0 ),
        .O(\cplllock_reg1_reg[6]_3 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXCDRLOCK),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxdlysresetdone_reg1),
        .Q(rxdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gt_rx_elec_idle_wire_filter),
        .Q(rxelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxelecidle_reg1),
        .Q(rxelecidle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_2 ),
        .Q(rxphaligndone_m_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_m_reg1),
        .Q(rxphaligndone_m_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_3 ),
        .Q(rxphaligndone_s_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_s_reg1),
        .Q(rxphaligndone_s_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxsync_fsm_disable.fsm_rx_reg[2]_0 ),
        .Q(rxsync_donem_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_donem_reg1),
        .Q(rxsync_donem_reg2),
        .R(RST_CPLLRESET));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b1),
        .Q(pipe_sync_fsm_rx[0]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[1]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[2]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[3]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[4]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[5]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[6]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.rxdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(SYNC_RXDLYEN),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_START),
        .Q(rxsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_start_reg1),
        .Q(rxsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsyncdone_reg1),
        .Q(rxsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(txdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg1),
        .Q(txdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg2),
        .Q(txdlysresetdone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncallin),
        .Q(txphaligndone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg1),
        .Q(txphaligndone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg2),
        .Q(txphaligndone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg2_reg),
        .Q(txphinitdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg1),
        .Q(txphinitdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg2),
        .Q(txphinitdone_reg3),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'hF2FF)) 
    \txsync_fsm.fsm_tx[0]_i_1__5 
       (.I0(Q[0]),
        .I1(txsync_start_reg2),
        .I2(Q[5]),
        .I3(\txsync_fsm.fsm_tx[5]_i_2__5_n_0 ),
        .O(fsm_tx[0]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[1]_i_1__5 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__5_n_0 ),
        .I1(Q[0]),
        .I2(txsync_start_reg2),
        .I3(Q[1]),
        .I4(mmcm_lock_reg2),
        .O(fsm_tx[1]));
  LUT6 #(
    .INIT(64'hAAAA80AA80808080)) 
    \txsync_fsm.fsm_tx[2]_i_1__5 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__5_n_0 ),
        .I1(Q[1]),
        .I2(mmcm_lock_reg2),
        .I3(txdlysresetdone_reg2),
        .I4(txdlysresetdone_reg3),
        .I5(Q[2]),
        .O(fsm_tx[2]));
  LUT6 #(
    .INIT(64'h00800080AAAA0080)) 
    \txsync_fsm.fsm_tx[3]_i_1__5 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__5_n_0 ),
        .I1(Q[2]),
        .I2(txdlysresetdone_reg2),
        .I3(txdlysresetdone_reg3),
        .I4(Q[3]),
        .I5(\txsync_fsm.fsm_tx[4]_i_2__5_n_0 ),
        .O(fsm_tx[3]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[4]_i_1__5 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__5_n_0 ),
        .I1(\txsync_fsm.fsm_tx[4]_i_2__5_n_0 ),
        .I2(Q[3]),
        .I3(Q[4]),
        .I4(\txsync_fsm.fsm_tx[4]_i_3__5_n_0 ),
        .O(fsm_tx[4]));
  LUT4 #(
    .INIT(16'hF222)) 
    \txsync_fsm.fsm_tx[4]_i_2__5 
       (.I0(txphinitdone_reg2),
        .I1(txphinitdone_reg3),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_2__5_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \txsync_fsm.fsm_tx[4]_i_3__5 
       (.I0(txphaligndone_reg3),
        .I1(txphaligndone_reg2),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hAA20202000000000)) 
    \txsync_fsm.fsm_tx[5]_i_1__5 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__5_n_0 ),
        .I1(txphaligndone_reg3),
        .I2(txphaligndone_reg2),
        .I3(p_0_in7_in),
        .I4(p_1_in8_in),
        .I5(Q[4]),
        .O(fsm_tx[5]));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \txsync_fsm.fsm_tx[5]_i_2__5 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(Q[5]),
        .O(\txsync_fsm.fsm_tx[5]_i_2__5_n_0 ));
  FDSE \txsync_fsm.fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[1]),
        .Q(Q[1]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[5]),
        .Q(Q[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00010000)) 
    \txsync_fsm.txdlyen_i_1__5 
       (.I0(\txsync_fsm.txdlyen_i_2__5_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[5]),
        .I4(\txsync_fsm.txdlyen_reg_0 ),
        .O(\txsync_fsm.txdlyen_i_1__5_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \txsync_fsm.txdlyen_i_2__5 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_start_reg2),
        .O(\txsync_fsm.txdlyen_i_2__5_n_0 ));
  FDRE \txsync_fsm.txdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txdlyen_i_1__5_n_0 ),
        .Q(\txsync_fsm.txdlyen_reg_0 ),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \txsync_fsm.txsync_done_i_1__4 
       (.I0(txsync_done),
        .I1(\txsync_fsm.txdlyen_i_2__5_n_0 ),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(RST_TXSYNC_DONE),
        .O(\txsync_fsm.txsync_done_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \txsync_fsm.txsync_done_i_2__5 
       (.I0(Q[3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(txsync_done));
  FDRE \txsync_fsm.txsync_done_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_i_1__4_n_0 ),
        .Q(RST_TXSYNC_DONE),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXSYNC_START),
        .Q(txsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg1),
        .Q(txsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg2),
        .Q(txsync_start_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg1),
        .Q(txsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg2),
        .Q(txsyncdone_reg3),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_sync" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_70
   (Q,
    \txsync_fsm.txdlyen_reg_0 ,
    pipe_sync_fsm_rx,
    SYNC_RXDLYEN,
    \cplllock_reg1_reg[7] ,
    \cplllock_reg1_reg[7]_0 ,
    \cplllock_reg1_reg[7]_1 ,
    \cplllock_reg1_reg[7]_2 ,
    \cplllock_reg1_reg[7]_3 ,
    RST_TXSYNC_DONE,
    p_0_in7_in,
    p_1_in8_in,
    RST_CPLLRESET,
    SYNC_TXSYNC_START,
    pclk_sel_reg,
    \resetovrd_disble.reset_reg[4] ,
    \resetovrd_disble.reset_reg[4]_0 ,
    txelecidle_reg2_reg,
    txsyncallin,
    \rxsync_fsm_disable.fsm_rx_reg[2]_0 ,
    SYNC_GEN3,
    SYNC_RATE_IDLE,
    gt_rx_elec_idle_wire_filter,
    SYNC_RXCDRLOCK,
    SYNC_RXSYNC_START,
    \resetovrd_disble.reset_reg[4]_1 ,
    \resetovrd_disble.reset_reg[4]_2 ,
    \resetovrd_disble.reset_reg[4]_3 );
  output [5:0]Q;
  output \txsync_fsm.txdlyen_reg_0 ;
  output [6:0]pipe_sync_fsm_rx;
  output SYNC_RXDLYEN;
  output \cplllock_reg1_reg[7] ;
  output \cplllock_reg1_reg[7]_0 ;
  output \cplllock_reg1_reg[7]_1 ;
  output \cplllock_reg1_reg[7]_2 ;
  output \cplllock_reg1_reg[7]_3 ;
  output [0:0]RST_TXSYNC_DONE;
  input p_0_in7_in;
  input p_1_in8_in;
  input RST_CPLLRESET;
  input SYNC_TXSYNC_START;
  input pclk_sel_reg;
  input \resetovrd_disble.reset_reg[4] ;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input txelecidle_reg2_reg;
  input txsyncallin;
  input \rxsync_fsm_disable.fsm_rx_reg[2]_0 ;
  input SYNC_GEN3;
  input SYNC_RATE_IDLE;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input SYNC_RXCDRLOCK;
  input SYNC_RXSYNC_START;
  input \resetovrd_disble.reset_reg[4]_1 ;
  input \resetovrd_disble.reset_reg[4]_2 ;
  input \resetovrd_disble.reset_reg[4]_3 ;

  wire [5:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_TXSYNC_DONE;
  wire SYNC_GEN3;
  wire SYNC_RATE_IDLE;
  wire SYNC_RXCDRLOCK;
  wire SYNC_RXDLYEN;
  wire SYNC_RXSYNC_START;
  wire SYNC_TXSYNC_START;
  wire \cplllock_reg1_reg[7] ;
  wire \cplllock_reg1_reg[7]_0 ;
  wire \cplllock_reg1_reg[7]_1 ;
  wire \cplllock_reg1_reg[7]_2 ;
  wire \cplllock_reg1_reg[7]_3 ;
  wire [5:0]fsm_tx;
  wire gen3_reg1;
  wire gen3_reg2;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire \gtx_channel.gtxe2_channel_i_i_60_n_0 ;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire p_0_in7_in;
  wire p_1_in8_in;
  wire pclk_sel_reg;
  wire [6:0]pipe_sync_fsm_rx;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire \resetovrd_disble.reset_reg[4]_2 ;
  wire \resetovrd_disble.reset_reg[4]_3 ;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxdlysresetdone_reg1;
  wire rxdlysresetdone_reg2;
  wire rxelecidle_reg1;
  wire rxelecidle_reg2;
  wire rxphaligndone_m_reg1;
  wire rxphaligndone_m_reg2;
  wire rxphaligndone_s_reg1;
  wire rxphaligndone_s_reg2;
  wire rxsync_donem_reg1;
  wire rxsync_donem_reg2;
  wire \rxsync_fsm_disable.fsm_rx_reg[2]_0 ;
  wire rxsync_start_reg1;
  wire rxsync_start_reg2;
  wire rxsyncdone_reg1;
  wire rxsyncdone_reg2;
  wire txdlysresetdone_reg1;
  wire txdlysresetdone_reg2;
  wire txdlysresetdone_reg3;
  wire txelecidle_reg2_reg;
  wire txphaligndone_reg1;
  wire txphaligndone_reg2;
  wire txphaligndone_reg3;
  wire txphinitdone_reg1;
  wire txphinitdone_reg2;
  wire txphinitdone_reg3;
  wire txsync_done;
  wire \txsync_fsm.fsm_tx[4]_i_2__6_n_0 ;
  wire \txsync_fsm.fsm_tx[4]_i_3__6_n_0 ;
  wire \txsync_fsm.fsm_tx[5]_i_2__6_n_0 ;
  wire \txsync_fsm.txdlyen_i_1__6_n_0 ;
  wire \txsync_fsm.txdlyen_i_2__6_n_0 ;
  wire \txsync_fsm.txdlyen_reg_0 ;
  wire \txsync_fsm.txsync_done_i_1__5_n_0 ;
  wire txsync_start_reg1;
  wire txsync_start_reg2;
  wire txsync_start_reg3;
  wire txsyncallin;
  wire txsyncdone_reg1;
  wire txsyncdone_reg2;
  wire txsyncdone_reg3;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_GEN3),
        .Q(gen3_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00000020)) 
    \gtx_channel.gtxe2_channel_i_i_10__2 
       (.I0(rxsync_donem_reg2),
        .I1(pipe_sync_fsm_rx[5]),
        .I2(pipe_sync_fsm_rx[3]),
        .I3(pipe_sync_fsm_rx[2]),
        .I4(\gtx_channel.gtxe2_channel_i_i_60_n_0 ),
        .O(\cplllock_reg1_reg[7]_2 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_12__6 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(\cplllock_reg1_reg[7] ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \gtx_channel.gtxe2_channel_i_i_13__6 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[0]),
        .I3(Q[3]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[7]_1 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \gtx_channel.gtxe2_channel_i_i_14__2 
       (.I0(Q[4]),
        .I1(Q[5]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cplllock_reg1_reg[7]_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \gtx_channel.gtxe2_channel_i_i_60 
       (.I0(pipe_sync_fsm_rx[0]),
        .I1(pipe_sync_fsm_rx[1]),
        .I2(pipe_sync_fsm_rx[6]),
        .I3(pipe_sync_fsm_rx[4]),
        .O(\gtx_channel.gtxe2_channel_i_i_60_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \gtx_channel.gtxe2_channel_i_i_9__6 
       (.I0(pipe_sync_fsm_rx[2]),
        .I1(pipe_sync_fsm_rx[3]),
        .I2(pipe_sync_fsm_rx[5]),
        .I3(\gtx_channel.gtxe2_channel_i_i_60_n_0 ),
        .O(\cplllock_reg1_reg[7]_3 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] ),
        .Q(mmcm_lock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXCDRLOCK),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxdlysresetdone_reg1),
        .Q(rxdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gt_rx_elec_idle_wire_filter),
        .Q(rxelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxelecidle_reg1),
        .Q(rxelecidle_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_2 ),
        .Q(rxphaligndone_m_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_m_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_m_reg1),
        .Q(rxphaligndone_m_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_3 ),
        .Q(rxphaligndone_s_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxphaligndone_s_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxphaligndone_s_reg1),
        .Q(rxphaligndone_s_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxsync_fsm_disable.fsm_rx_reg[2]_0 ),
        .Q(rxsync_donem_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_donem_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_donem_reg1),
        .Q(rxsync_donem_reg2),
        .R(RST_CPLLRESET));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b1),
        .Q(pipe_sync_fsm_rx[0]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[1]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[2]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[3]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[4]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[5]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.fsm_rx_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(pipe_sync_fsm_rx[6]),
        .R(1'b0));
  FDRE \rxsync_fsm_disable.rxdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(SYNC_RXDLYEN),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_RXSYNC_START),
        .Q(rxsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsync_start_reg1),
        .Q(rxsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rxsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxsyncdone_reg1),
        .Q(rxsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(txdlysresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg1),
        .Q(txdlysresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txdlysresetdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txdlysresetdone_reg2),
        .Q(txdlysresetdone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncallin),
        .Q(txphaligndone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg1),
        .Q(txphaligndone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphaligndone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphaligndone_reg2),
        .Q(txphaligndone_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg2_reg),
        .Q(txphinitdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg1),
        .Q(txphinitdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txphinitdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txphinitdone_reg2),
        .Q(txphinitdone_reg3),
        .R(RST_CPLLRESET));
  LUT4 #(
    .INIT(16'hF2FF)) 
    \txsync_fsm.fsm_tx[0]_i_1__6 
       (.I0(Q[0]),
        .I1(txsync_start_reg2),
        .I2(Q[5]),
        .I3(\txsync_fsm.fsm_tx[5]_i_2__6_n_0 ),
        .O(fsm_tx[0]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[1]_i_1__6 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__6_n_0 ),
        .I1(Q[0]),
        .I2(txsync_start_reg2),
        .I3(Q[1]),
        .I4(mmcm_lock_reg2),
        .O(fsm_tx[1]));
  LUT6 #(
    .INIT(64'hAAAA80AA80808080)) 
    \txsync_fsm.fsm_tx[2]_i_1__6 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__6_n_0 ),
        .I1(Q[1]),
        .I2(mmcm_lock_reg2),
        .I3(txdlysresetdone_reg2),
        .I4(txdlysresetdone_reg3),
        .I5(Q[2]),
        .O(fsm_tx[2]));
  LUT6 #(
    .INIT(64'h00800080AAAA0080)) 
    \txsync_fsm.fsm_tx[3]_i_1__6 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__6_n_0 ),
        .I1(Q[2]),
        .I2(txdlysresetdone_reg2),
        .I3(txdlysresetdone_reg3),
        .I4(Q[3]),
        .I5(\txsync_fsm.fsm_tx[4]_i_2__6_n_0 ),
        .O(fsm_tx[3]));
  LUT5 #(
    .INIT(32'h8080AA80)) 
    \txsync_fsm.fsm_tx[4]_i_1__6 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__6_n_0 ),
        .I1(\txsync_fsm.fsm_tx[4]_i_2__6_n_0 ),
        .I2(Q[3]),
        .I3(Q[4]),
        .I4(\txsync_fsm.fsm_tx[4]_i_3__6_n_0 ),
        .O(fsm_tx[4]));
  LUT4 #(
    .INIT(16'hF222)) 
    \txsync_fsm.fsm_tx[4]_i_2__6 
       (.I0(txphinitdone_reg2),
        .I1(txphinitdone_reg3),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_2__6_n_0 ));
  LUT4 #(
    .INIT(16'hF444)) 
    \txsync_fsm.fsm_tx[4]_i_3__6 
       (.I0(txphaligndone_reg3),
        .I1(txphaligndone_reg2),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .O(\txsync_fsm.fsm_tx[4]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hAA20202000000000)) 
    \txsync_fsm.fsm_tx[5]_i_1__6 
       (.I0(\txsync_fsm.fsm_tx[5]_i_2__6_n_0 ),
        .I1(txphaligndone_reg3),
        .I2(txphaligndone_reg2),
        .I3(p_0_in7_in),
        .I4(p_1_in8_in),
        .I5(Q[4]),
        .O(fsm_tx[5]));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \txsync_fsm.fsm_tx[5]_i_2__6 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(Q[4]),
        .I5(Q[5]),
        .O(\txsync_fsm.fsm_tx[5]_i_2__6_n_0 ));
  FDSE \txsync_fsm.fsm_tx_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[0]),
        .Q(Q[0]),
        .S(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[1]),
        .Q(Q[1]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[2]),
        .Q(Q[2]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[3]),
        .Q(Q[3]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[4]),
        .Q(Q[4]),
        .R(RST_CPLLRESET));
  FDRE \txsync_fsm.fsm_tx_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fsm_tx[5]),
        .Q(Q[5]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h00010000)) 
    \txsync_fsm.txdlyen_i_1__6 
       (.I0(\txsync_fsm.txdlyen_i_2__6_n_0 ),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[5]),
        .I4(\txsync_fsm.txdlyen_reg_0 ),
        .O(\txsync_fsm.txdlyen_i_1__6_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \txsync_fsm.txdlyen_i_2__6 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(txsync_start_reg2),
        .O(\txsync_fsm.txdlyen_i_2__6_n_0 ));
  FDRE \txsync_fsm.txdlyen_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txdlyen_i_1__6_n_0 ),
        .Q(\txsync_fsm.txdlyen_reg_0 ),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \txsync_fsm.txsync_done_i_1__5 
       (.I0(txsync_done),
        .I1(\txsync_fsm.txdlyen_i_2__6_n_0 ),
        .I2(Q[4]),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(RST_TXSYNC_DONE),
        .O(\txsync_fsm.txsync_done_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \txsync_fsm.txsync_done_i_2__6 
       (.I0(Q[3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(txsync_done));
  FDRE \txsync_fsm.txsync_done_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\txsync_fsm.txsync_done_i_1__5_n_0 ),
        .Q(RST_TXSYNC_DONE),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(SYNC_TXSYNC_START),
        .Q(txsync_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg1),
        .Q(txsync_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsync_start_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsync_start_reg2),
        .Q(txsync_start_reg3),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(txsyncdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg1),
        .Q(txsyncdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txsyncdone_reg3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txsyncdone_reg2),
        .Q(txsyncdone_reg3),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_user" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_user
   (txphinitdone_reg1_reg,
    p_1_in8_in,
    p_0_in7_in,
    gt_rxvalid_q_reg,
    p_2_in,
    USER_OOBCLK,
    Q,
    RST_RXCDRLOCK,
    gt_rx_phy_status_wire_filter,
    user_rx_converge,
    \cplllock_reg1_reg[0] ,
    resetovrd_done_reg1_reg,
    RST_RESETDONE,
    user_active_lane,
    pipe_txphinitdone,
    p_1_in8_in_0,
    p_0_in7_in_1,
    txelecidle_reg2_reg_0,
    gt_rxvalid_q_reg_0,
    gt_rx_elec_idle_wire_filter,
    \resetovrd_disble.reset_reg[4]_0 ,
    RST_CPLLRESET,
    pclk_sel_reg,
    CLK_PCLK_SEL,
    USER_RXRESETDONE,
    USER_TXRESETDONE,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    \resetovrd_disble.reset_reg[4]_1 ,
    RST_RXUSRCLK_RESET,
    pipe_rxstatus,
    out1,
    RST_RATE_IDLE,
    USER_RATE_RXSYNC,
    USER_RATE_DONE,
    rate_gen3,
    USER_RXEQ_ADAPT_DONE,
    USER_RESETOVRD_START,
    RST_PHYSTATUS);
  output txphinitdone_reg1_reg;
  output p_1_in8_in;
  output p_0_in7_in;
  output gt_rxvalid_q_reg;
  output p_2_in;
  output USER_OOBCLK;
  output [6:0]Q;
  output [0:0]RST_RXCDRLOCK;
  output [0:0]gt_rx_phy_status_wire_filter;
  output [0:0]user_rx_converge;
  output \cplllock_reg1_reg[0] ;
  output resetovrd_done_reg1_reg;
  output [0:0]RST_RESETDONE;
  output [0:0]user_active_lane;
  input [0:0]pipe_txphinitdone;
  input p_1_in8_in_0;
  input p_0_in7_in_1;
  input txelecidle_reg2_reg_0;
  input gt_rxvalid_q_reg_0;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]CLK_PCLK_SEL;
  input USER_RXRESETDONE;
  input USER_TXRESETDONE;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [0:0]PIPE_TXELECIDLE;
  input \resetovrd_disble.reset_reg[4]_1 ;
  input RST_RXUSRCLK_RESET;
  input [0:0]pipe_rxstatus;
  input [0:0]out1;
  input [0:0]RST_RATE_IDLE;
  input USER_RATE_RXSYNC;
  input USER_RATE_DONE;
  input [0:0]rate_gen3;
  input USER_RXEQ_ADAPT_DONE;
  input USER_RESETOVRD_START;
  input [0:0]RST_PHYSTATUS;

  wire [0:0]CLK_PCLK_SEL;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [0:0]PIPE_TXELECIDLE;
  wire [6:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_PHYSTATUS;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_RESETDONE;
  wire [0:0]RST_RXCDRLOCK;
  wire RST_RXUSRCLK_RESET;
  wire USER_OOBCLK;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXEQ_ADAPT_DONE;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire \converge_cnt[0]_i_1_n_0 ;
  wire \converge_cnt[0]_i_4_n_0 ;
  wire \converge_cnt[0]_i_5_n_0 ;
  wire \converge_cnt[0]_i_6_n_0 ;
  wire \converge_cnt[0]_i_7_n_0 ;
  wire \converge_cnt[0]_i_8_n_0 ;
  wire \converge_cnt[0]_i_9_n_0 ;
  wire [21:0]converge_cnt_reg;
  wire \converge_cnt_reg[0]_i_3_n_0 ;
  wire \converge_cnt_reg[10]_i_1_n_0 ;
  wire \converge_cnt_reg[10]_i_2_n_0 ;
  wire \converge_cnt_reg[11]_i_1_n_0 ;
  wire \converge_cnt_reg[11]_i_2_n_0 ;
  wire \converge_cnt_reg[12]_i_1_n_0 ;
  wire \converge_cnt_reg[12]_i_2_n_0 ;
  wire \converge_cnt_reg[13]_i_1_n_0 ;
  wire \converge_cnt_reg[13]_i_2_n_0 ;
  wire \converge_cnt_reg[14]_i_1_n_0 ;
  wire \converge_cnt_reg[14]_i_2_n_0 ;
  wire \converge_cnt_reg[15]_i_1_n_0 ;
  wire \converge_cnt_reg[15]_i_2_n_0 ;
  wire \converge_cnt_reg[16]_i_1_n_0 ;
  wire \converge_cnt_reg[16]_i_2_n_0 ;
  wire \converge_cnt_reg[17]_i_1_n_0 ;
  wire \converge_cnt_reg[17]_i_2_n_0 ;
  wire \converge_cnt_reg[18]_i_1_n_0 ;
  wire \converge_cnt_reg[18]_i_2_n_0 ;
  wire \converge_cnt_reg[19]_i_1_n_0 ;
  wire \converge_cnt_reg[19]_i_2_n_0 ;
  wire \converge_cnt_reg[1]_i_1_n_0 ;
  wire \converge_cnt_reg[1]_i_2_n_0 ;
  wire \converge_cnt_reg[20]_i_1_n_0 ;
  wire \converge_cnt_reg[20]_i_2_n_0 ;
  wire \converge_cnt_reg[21]_i_1_n_0 ;
  wire \converge_cnt_reg[2]_i_1_n_0 ;
  wire \converge_cnt_reg[2]_i_2_n_0 ;
  wire \converge_cnt_reg[3]_i_1_n_0 ;
  wire \converge_cnt_reg[3]_i_2_n_0 ;
  wire \converge_cnt_reg[4]_i_1_n_0 ;
  wire \converge_cnt_reg[4]_i_2_n_0 ;
  wire \converge_cnt_reg[5]_i_1_n_0 ;
  wire \converge_cnt_reg[5]_i_2_n_0 ;
  wire \converge_cnt_reg[6]_i_1_n_0 ;
  wire \converge_cnt_reg[6]_i_2_n_0 ;
  wire \converge_cnt_reg[7]_i_1_n_0 ;
  wire \converge_cnt_reg[7]_i_2_n_0 ;
  wire \converge_cnt_reg[8]_i_1_n_0 ;
  wire \converge_cnt_reg[8]_i_2_n_0 ;
  wire \converge_cnt_reg[9]_i_1_n_0 ;
  wire \converge_cnt_reg[9]_i_2_n_0 ;
  wire converge_gen3_i_1_n_0;
  wire converge_gen3_reg_n_0;
  wire \cplllock_reg1_reg[0] ;
  wire [1:0]fsm;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire gt_rxvalid_q_i_6_n_0;
  wire gt_rxvalid_q_reg;
  wire gt_rxvalid_q_reg_0;
  wire \gtx_channel.gtxe2_channel_i_i_74_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_75_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_83_n_0 ;
  wire [1:0]oobclk_cnt;
  wire \oobclk_div.oobclk_i_1_n_0 ;
  wire [0:0]out1;
  wire p_0_in7_in_1;
  wire [3:0]p_0_in__0;
  wire [3:0]p_0_in__0__0;
  wire p_1_in8_in_0;
  wire [1:0]p_1_in__0;
  wire pclk_sel_reg;
  wire pclk_sel_reg1;
  wire pclk_sel_reg2;
  wire [0:0]pipe_rxstatus;
  wire [0:0]pipe_txphinitdone;
  wire rate_done_reg1;
  wire rate_done_reg2;
  wire [0:0]rate_gen3;
  wire rate_gen3_reg1;
  wire rate_gen3_reg2;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire rate_rxsync_reg1;
  wire rate_rxsync_reg2;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire resetovrd_done_reg1_reg;
  wire resetovrd_start_reg1;
  wire resetovrd_start_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire [3:0]rxcdrlock_cnt_reg__0;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxeq_adapt_done_reg1;
  wire rxeq_adapt_done_reg2;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxstatus_reg1;
  wire rxstatus_reg2;
  wire [3:0]rxvalid_cnt_reg__0;
  wire rxvalid_reg1;
  wire rxvalid_reg2;
  wire sel;
  wire txcompliance_reg1;
  wire txcompliance_reg2;
  wire txelecidle_reg1;
  wire txelecidle_reg2;
  wire txelecidle_reg2_reg_0;
  wire txphinitdone_reg1_reg;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire [0:0]user_active_lane;
  wire [0:0]user_rx_converge;
  wire [3:0]\NLW_converge_cnt_reg[21]_i_2_CARRY4_CO_UNCONNECTED ;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2_CARRY4_DI_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2_CARRY4_O_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2_CARRY4_S_UNCONNECTED ;

  assign p_0_in7_in = txcompliance_reg2;
  assign p_1_in8_in = txelecidle_reg2;
  assign p_2_in = rst_idle_reg2;
  LUT4 #(
    .INIT(16'hFFF7)) 
    \converge_cnt[0]_i_1 
       (.I0(rate_idle_reg2),
        .I1(rst_idle_reg2),
        .I2(RST_CPLLRESET),
        .I3(rate_gen3_reg2),
        .O(\converge_cnt[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h5D5D555D)) 
    \converge_cnt[0]_i_2 
       (.I0(converge_cnt_reg[21]),
        .I1(\converge_cnt[0]_i_4_n_0 ),
        .I2(converge_cnt_reg[20]),
        .I3(\converge_cnt[0]_i_5_n_0 ),
        .I4(\converge_cnt[0]_i_6_n_0 ),
        .O(sel));
  LUT6 #(
    .INIT(64'h13FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_4 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(converge_cnt_reg[13]),
        .I3(converge_cnt_reg[16]),
        .I4(converge_cnt_reg[15]),
        .I5(\converge_cnt[0]_i_8_n_0 ),
        .O(\converge_cnt[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \converge_cnt[0]_i_5 
       (.I0(\converge_cnt[0]_i_8_n_0 ),
        .I1(converge_cnt_reg[16]),
        .I2(converge_cnt_reg[15]),
        .I3(converge_cnt_reg[13]),
        .I4(converge_cnt_reg[11]),
        .O(\converge_cnt[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h10FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_6 
       (.I0(converge_cnt_reg[3]),
        .I1(converge_cnt_reg[6]),
        .I2(\converge_cnt[0]_i_9_n_0 ),
        .I3(converge_cnt_reg[10]),
        .I4(converge_cnt_reg[8]),
        .I5(converge_cnt_reg[9]),
        .O(\converge_cnt[0]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[0]_i_7 
       (.I0(converge_cnt_reg[0]),
        .O(\converge_cnt[0]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \converge_cnt[0]_i_8 
       (.I0(converge_cnt_reg[17]),
        .I1(converge_cnt_reg[18]),
        .I2(converge_cnt_reg[19]),
        .O(\converge_cnt[0]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \converge_cnt[0]_i_9 
       (.I0(converge_cnt_reg[4]),
        .I1(converge_cnt_reg[5]),
        .I2(converge_cnt_reg[7]),
        .O(\converge_cnt[0]_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[0]_i_3_n_0 ),
        .Q(converge_cnt_reg[0]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[10]_i_1_n_0 ),
        .Q(converge_cnt_reg[10]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[11]_i_1_n_0 ),
        .Q(converge_cnt_reg[11]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[12]_i_1_n_0 ),
        .Q(converge_cnt_reg[12]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[13]_i_1_n_0 ),
        .Q(converge_cnt_reg[13]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[13]_i_2_CARRY4 
       (.CI(\converge_cnt_reg[12]_i_2_n_0 ),
        .CO({\converge_cnt_reg[16]_i_2_n_0 ,\converge_cnt_reg[15]_i_2_n_0 ,\converge_cnt_reg[14]_i_2_n_0 ,\converge_cnt_reg[13]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[15]_i_1_n_0 ,\converge_cnt_reg[14]_i_1_n_0 ,\converge_cnt_reg[13]_i_1_n_0 ,\converge_cnt_reg[12]_i_1_n_0 }),
        .S(converge_cnt_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[14]_i_1_n_0 ),
        .Q(converge_cnt_reg[14]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[15]_i_1_n_0 ),
        .Q(converge_cnt_reg[15]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[16]_i_1_n_0 ),
        .Q(converge_cnt_reg[16]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[17]_i_1_n_0 ),
        .Q(converge_cnt_reg[17]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[17]_i_2_CARRY4 
       (.CI(\converge_cnt_reg[16]_i_2_n_0 ),
        .CO({\converge_cnt_reg[20]_i_2_n_0 ,\converge_cnt_reg[19]_i_2_n_0 ,\converge_cnt_reg[18]_i_2_n_0 ,\converge_cnt_reg[17]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[19]_i_1_n_0 ,\converge_cnt_reg[18]_i_1_n_0 ,\converge_cnt_reg[17]_i_1_n_0 ,\converge_cnt_reg[16]_i_1_n_0 }),
        .S(converge_cnt_reg[19:16]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[18]_i_1_n_0 ),
        .Q(converge_cnt_reg[18]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[19]_i_1_n_0 ),
        .Q(converge_cnt_reg[19]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[1]_i_1_n_0 ),
        .Q(converge_cnt_reg[1]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[1]_i_2_CARRY4 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[4]_i_2_n_0 ,\converge_cnt_reg[3]_i_2_n_0 ,\converge_cnt_reg[2]_i_2_n_0 ,\converge_cnt_reg[1]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\converge_cnt_reg[3]_i_1_n_0 ,\converge_cnt_reg[2]_i_1_n_0 ,\converge_cnt_reg[1]_i_1_n_0 ,\converge_cnt_reg[0]_i_3_n_0 }),
        .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_7_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[20]_i_1_n_0 ),
        .Q(converge_cnt_reg[20]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[21]_i_1_n_0 ),
        .Q(converge_cnt_reg[21]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[21]_i_2_CARRY4 
       (.CI(\converge_cnt_reg[20]_i_2_n_0 ),
        .CO(\NLW_converge_cnt_reg[21]_i_2_CARRY4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({\NLW_converge_cnt_reg[21]_i_2_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2_CARRY4_O_UNCONNECTED [3:2],\converge_cnt_reg[21]_i_1_n_0 ,\converge_cnt_reg[20]_i_1_n_0 }),
        .S({\NLW_converge_cnt_reg[21]_i_2_CARRY4_S_UNCONNECTED [3:2],converge_cnt_reg[21:20]}));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[2]_i_1_n_0 ),
        .Q(converge_cnt_reg[2]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[3]_i_1_n_0 ),
        .Q(converge_cnt_reg[3]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[4]_i_1_n_0 ),
        .Q(converge_cnt_reg[4]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[5]_i_1_n_0 ),
        .Q(converge_cnt_reg[5]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[5]_i_2_CARRY4 
       (.CI(\converge_cnt_reg[4]_i_2_n_0 ),
        .CO({\converge_cnt_reg[8]_i_2_n_0 ,\converge_cnt_reg[7]_i_2_n_0 ,\converge_cnt_reg[6]_i_2_n_0 ,\converge_cnt_reg[5]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[7]_i_1_n_0 ,\converge_cnt_reg[6]_i_1_n_0 ,\converge_cnt_reg[5]_i_1_n_0 ,\converge_cnt_reg[4]_i_1_n_0 }),
        .S(converge_cnt_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[6]_i_1_n_0 ),
        .Q(converge_cnt_reg[6]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[7]_i_1_n_0 ),
        .Q(converge_cnt_reg[7]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[8]_i_1_n_0 ),
        .Q(converge_cnt_reg[8]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[9]_i_1_n_0 ),
        .Q(converge_cnt_reg[9]),
        .R(\converge_cnt[0]_i_1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[9]_i_2_CARRY4 
       (.CI(\converge_cnt_reg[8]_i_2_n_0 ),
        .CO({\converge_cnt_reg[12]_i_2_n_0 ,\converge_cnt_reg[11]_i_2_n_0 ,\converge_cnt_reg[10]_i_2_n_0 ,\converge_cnt_reg[9]_i_2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[11]_i_1_n_0 ,\converge_cnt_reg[10]_i_1_n_0 ,\converge_cnt_reg[9]_i_1_n_0 ,\converge_cnt_reg[8]_i_1_n_0 }),
        .S(converge_cnt_reg[11:8]));
  LUT4 #(
    .INIT(16'h0C08)) 
    converge_gen3_i_1
       (.I0(rxeq_adapt_done_reg2),
        .I1(rate_gen3_reg2),
        .I2(RST_CPLLRESET),
        .I3(converge_gen3_reg_n_0),
        .O(converge_gen3_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    converge_gen3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_gen3_i_1_n_0),
        .Q(converge_gen3_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFE0FF)) 
    gt_rx_phy_status_q_i_1
       (.I0(rate_idle_reg2),
        .I1(rate_rxsync_reg2),
        .I2(RST_PHYSTATUS),
        .I3(rst_idle_reg2),
        .I4(rate_done_reg2),
        .O(gt_rx_phy_status_wire_filter));
  LUT6 #(
    .INIT(64'h4500000000000000)) 
    gt_rxvalid_q_i_4
       (.I0(gt_rxvalid_q_i_6_n_0),
        .I1(gt_rxvalid_q_reg_0),
        .I2(gt_rx_elec_idle_wire_filter),
        .I3(rst_idle_reg2),
        .I4(rate_idle_reg2),
        .I5(\resetovrd_disble.reset_reg[4]_0 ),
        .O(gt_rxvalid_q_reg));
  LUT4 #(
    .INIT(16'h7FFF)) 
    gt_rxvalid_q_i_6
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[1]),
        .O(gt_rxvalid_q_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_5 
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(\cplllock_reg1_reg[0] ));
  LUT6 #(
    .INIT(64'hAAAAAAAEAAAAAAAA)) 
    \gtx_channel.gtxe2_channel_i_i_64 
       (.I0(converge_gen3_reg_n_0),
        .I1(\gtx_channel.gtxe2_channel_i_i_74_n_0 ),
        .I2(\gtx_channel.gtxe2_channel_i_i_75_n_0 ),
        .I3(converge_cnt_reg[14]),
        .I4(converge_cnt_reg[12]),
        .I5(\converge_cnt[0]_i_5_n_0 ),
        .O(user_rx_converge));
  LUT6 #(
    .INIT(64'h0000000001000000)) 
    \gtx_channel.gtxe2_channel_i_i_74 
       (.I0(converge_cnt_reg[7]),
        .I1(converge_cnt_reg[5]),
        .I2(converge_cnt_reg[4]),
        .I3(\gtx_channel.gtxe2_channel_i_i_83_n_0 ),
        .I4(converge_cnt_reg[21]),
        .I5(converge_cnt_reg[0]),
        .O(\gtx_channel.gtxe2_channel_i_i_74_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \gtx_channel.gtxe2_channel_i_i_75 
       (.I0(converge_cnt_reg[8]),
        .I1(converge_cnt_reg[9]),
        .O(\gtx_channel.gtxe2_channel_i_i_75_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000100000)) 
    \gtx_channel.gtxe2_channel_i_i_83 
       (.I0(converge_cnt_reg[6]),
        .I1(converge_cnt_reg[1]),
        .I2(converge_cnt_reg[3]),
        .I3(converge_cnt_reg[20]),
        .I4(converge_cnt_reg[10]),
        .I5(converge_cnt_reg[2]),
        .O(\gtx_channel.gtxe2_channel_i_i_83_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oobclk_div.oobclk_cnt[0]_i_1 
       (.I0(oobclk_cnt[0]),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \oobclk_div.oobclk_cnt[1]_i_1 
       (.I0(oobclk_cnt[0]),
        .I1(oobclk_cnt[1]),
        .O(p_1_in__0[1]));
  FDRE \oobclk_div.oobclk_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[0]),
        .Q(oobclk_cnt[0]),
        .R(RST_CPLLRESET));
  FDRE \oobclk_div.oobclk_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[1]),
        .Q(oobclk_cnt[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hB8)) 
    \oobclk_div.oobclk_i_1 
       (.I0(oobclk_cnt[1]),
        .I1(pclk_sel_reg2),
        .I2(oobclk_cnt[0]),
        .O(\oobclk_div.oobclk_i_1_n_0 ));
  FDRE \oobclk_div.oobclk_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\oobclk_div.oobclk_i_1_n_0 ),
        .Q(USER_OOBCLK),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(CLK_PCLK_SEL),
        .Q(pclk_sel_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pclk_sel_reg1),
        .Q(pclk_sel_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_DONE),
        .Q(rate_done_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_done_reg1),
        .Q(rate_done_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(rate_gen3_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3_reg1),
        .Q(rate_gen3_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_RXSYNC),
        .Q(rate_rxsync_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_rxsync_reg1),
        .Q(rate_rxsync_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT2 #(
    .INIT(4'h8)) 
    \resetdone_reg1[0]_i_1 
       (.I0(txresetdone_reg2),
        .I1(rxresetdone_reg2),
        .O(RST_RESETDONE));
  FDRE \resetovrd_disble.fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT2 #(
    .INIT(4'h1)) 
    resetovrd_done_reg1_i_1
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(resetovrd_done_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RESETOVRD_START),
        .Q(resetovrd_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetovrd_start_reg1),
        .Q(resetovrd_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(out1),
        .Q(rst_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT5 #(
    .INIT(32'h8A0A0A0A)) 
    \rxcdrlock_cnt[0]_i_1 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[2]),
        .I2(rxcdrlock_cnt_reg__0[0]),
        .I3(rxcdrlock_cnt_reg__0[1]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[0]));
  LUT5 #(
    .INIT(32'hA8282828)) 
    \rxcdrlock_cnt[1]_i_1 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[0]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[2]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[1]));
  LUT5 #(
    .INIT(32'h8CCCC000)) 
    \rxcdrlock_cnt[2]_i_1 
       (.I0(rxcdrlock_cnt_reg__0[3]),
        .I1(rxcdrlock_reg2),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \rxcdrlock_cnt[3]_i_1 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(rxcdrlock_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(rxcdrlock_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(rxcdrlock_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(rxcdrlock_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h80000000)) 
    \rxcdrlock_reg1[0]_i_1 
       (.I0(\resetovrd_disble.reset_reg[4]_1 ),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(RST_RXCDRLOCK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXEQ_ADAPT_DONE),
        .Q(rxeq_adapt_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_adapt_done_reg1),
        .Q(rxeq_adapt_done_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pipe_rxstatus),
        .Q(rxstatus_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxstatus_reg1),
        .Q(rxstatus_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT6 #(
    .INIT(64'h8080000000FF0000)) 
    \rxvalid_cnt[0]_i_1 
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[1]),
        .I3(rxstatus_reg2),
        .I4(rxvalid_reg2),
        .I5(rxvalid_cnt_reg__0[0]),
        .O(p_0_in__0__0[0]));
  LUT6 #(
    .INIT(64'h80000000E6660000)) 
    \rxvalid_cnt[1]_i_1 
       (.I0(rxvalid_cnt_reg__0[0]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[1]));
  LUT6 #(
    .INIT(64'h80000000EA6A0000)) 
    \rxvalid_cnt[2]_i_1 
       (.I0(rxvalid_cnt_reg__0[2]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'hD444444400000000)) 
    \rxvalid_cnt[3]_i_1 
       (.I0(rxstatus_reg2),
        .I1(rxvalid_cnt_reg__0[3]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[0]),
        .I4(rxvalid_cnt_reg__0[1]),
        .I5(rxvalid_reg2),
        .O(p_0_in__0__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(rxvalid_cnt_reg__0[0]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(rxvalid_cnt_reg__0[1]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(rxvalid_cnt_reg__0[2]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(rxvalid_cnt_reg__0[3]),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxvalid_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxvalid_reg1),
        .Q(rxvalid_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXCOMPLIANCE),
        .Q(txcompliance_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcompliance_reg1),
        .Q(txcompliance_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXELECIDLE),
        .Q(txelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg1),
        .Q(txelecidle_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0000000088808080)) 
    txphinitdone_reg1_i_4
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .I2(pipe_txphinitdone),
        .I3(p_1_in8_in_0),
        .I4(p_0_in7_in_1),
        .I5(txelecidle_reg2_reg_0),
        .O(txphinitdone_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h7)) 
    \txsync_fsm.fsm_tx[5]_i_3 
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .O(user_active_lane));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_user" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_34
   (txphaligndone_reg1_reg,
    p_1_in8_in,
    p_0_in7_in,
    txphaligndone_reg1_reg_0,
    txphinitdone_reg1_reg,
    gt_rxvalid_q_reg,
    p_2_in,
    USER_OOBCLK,
    Q,
    RST_RXCDRLOCK,
    gt_rx_phy_status_wire_filter,
    user_rx_converge,
    \cplllock_reg1_reg[1] ,
    resetovrd_done_reg1_reg,
    RST_RESETDONE,
    user_active_lane,
    txelecidle_reg2_reg_0,
    pipe_txphaligndone,
    pipe_txphinitdone,
    p_1_in8_in_0,
    p_0_in7_in_1,
    gt_rxvalid_q_reg_0,
    gt_rx_elec_idle_wire_filter,
    \resetovrd_disble.reset_reg[4]_0 ,
    RST_CPLLRESET,
    pclk_sel_reg,
    CLK_PCLK_SEL,
    USER_RXRESETDONE,
    USER_TXRESETDONE,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    \resetovrd_disble.reset_reg[4]_1 ,
    RST_RXUSRCLK_RESET,
    pipe_rxstatus,
    out1,
    RST_RATE_IDLE,
    USER_RATE_RXSYNC,
    USER_RATE_DONE,
    rate_gen3,
    USER_RXEQ_ADAPT_DONE,
    USER_RESETOVRD_START,
    RST_PHYSTATUS);
  output txphaligndone_reg1_reg;
  output p_1_in8_in;
  output p_0_in7_in;
  output txphaligndone_reg1_reg_0;
  output txphinitdone_reg1_reg;
  output gt_rxvalid_q_reg;
  output p_2_in;
  output USER_OOBCLK;
  output [6:0]Q;
  output [0:0]RST_RXCDRLOCK;
  output [0:0]gt_rx_phy_status_wire_filter;
  output [0:0]user_rx_converge;
  output \cplllock_reg1_reg[1] ;
  output resetovrd_done_reg1_reg;
  output [0:0]RST_RESETDONE;
  input [0:0]user_active_lane;
  input txelecidle_reg2_reg_0;
  input [1:0]pipe_txphaligndone;
  input [1:0]pipe_txphinitdone;
  input p_1_in8_in_0;
  input p_0_in7_in_1;
  input gt_rxvalid_q_reg_0;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]CLK_PCLK_SEL;
  input USER_RXRESETDONE;
  input USER_TXRESETDONE;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [0:0]PIPE_TXELECIDLE;
  input \resetovrd_disble.reset_reg[4]_1 ;
  input RST_RXUSRCLK_RESET;
  input [0:0]pipe_rxstatus;
  input [0:0]out1;
  input [0:0]RST_RATE_IDLE;
  input USER_RATE_RXSYNC;
  input USER_RATE_DONE;
  input [0:0]rate_gen3;
  input USER_RXEQ_ADAPT_DONE;
  input USER_RESETOVRD_START;
  input [0:0]RST_PHYSTATUS;

  wire [0:0]CLK_PCLK_SEL;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [0:0]PIPE_TXELECIDLE;
  wire [6:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_PHYSTATUS;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_RESETDONE;
  wire [0:0]RST_RXCDRLOCK;
  wire RST_RXUSRCLK_RESET;
  wire USER_OOBCLK;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXEQ_ADAPT_DONE;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire \converge_cnt[0]_i_1__0_n_0 ;
  wire \converge_cnt[0]_i_4__0_n_0 ;
  wire \converge_cnt[0]_i_5__0_n_0 ;
  wire \converge_cnt[0]_i_6__0_n_0 ;
  wire \converge_cnt[0]_i_7__0_n_0 ;
  wire \converge_cnt[0]_i_8__0_n_0 ;
  wire \converge_cnt[0]_i_9__0_n_0 ;
  wire [21:0]converge_cnt_reg;
  wire \converge_cnt_reg[0]_i_3__0_n_0 ;
  wire \converge_cnt_reg[10]_i_1__0_n_0 ;
  wire \converge_cnt_reg[10]_i_2__0_n_0 ;
  wire \converge_cnt_reg[11]_i_1__0_n_0 ;
  wire \converge_cnt_reg[11]_i_2__0_n_0 ;
  wire \converge_cnt_reg[12]_i_1__0_n_0 ;
  wire \converge_cnt_reg[12]_i_2__0_n_0 ;
  wire \converge_cnt_reg[13]_i_1__0_n_0 ;
  wire \converge_cnt_reg[13]_i_2__0_n_0 ;
  wire \converge_cnt_reg[14]_i_1__0_n_0 ;
  wire \converge_cnt_reg[14]_i_2__0_n_0 ;
  wire \converge_cnt_reg[15]_i_1__0_n_0 ;
  wire \converge_cnt_reg[15]_i_2__0_n_0 ;
  wire \converge_cnt_reg[16]_i_1__0_n_0 ;
  wire \converge_cnt_reg[16]_i_2__0_n_0 ;
  wire \converge_cnt_reg[17]_i_1__0_n_0 ;
  wire \converge_cnt_reg[17]_i_2__0_n_0 ;
  wire \converge_cnt_reg[18]_i_1__0_n_0 ;
  wire \converge_cnt_reg[18]_i_2__0_n_0 ;
  wire \converge_cnt_reg[19]_i_1__0_n_0 ;
  wire \converge_cnt_reg[19]_i_2__0_n_0 ;
  wire \converge_cnt_reg[1]_i_1__0_n_0 ;
  wire \converge_cnt_reg[1]_i_2__0_n_0 ;
  wire \converge_cnt_reg[20]_i_1__0_n_0 ;
  wire \converge_cnt_reg[20]_i_2__0_n_0 ;
  wire \converge_cnt_reg[21]_i_1__0_n_0 ;
  wire \converge_cnt_reg[2]_i_1__0_n_0 ;
  wire \converge_cnt_reg[2]_i_2__0_n_0 ;
  wire \converge_cnt_reg[3]_i_1__0_n_0 ;
  wire \converge_cnt_reg[3]_i_2__0_n_0 ;
  wire \converge_cnt_reg[4]_i_1__0_n_0 ;
  wire \converge_cnt_reg[4]_i_2__0_n_0 ;
  wire \converge_cnt_reg[5]_i_1__0_n_0 ;
  wire \converge_cnt_reg[5]_i_2__0_n_0 ;
  wire \converge_cnt_reg[6]_i_1__0_n_0 ;
  wire \converge_cnt_reg[6]_i_2__0_n_0 ;
  wire \converge_cnt_reg[7]_i_1__0_n_0 ;
  wire \converge_cnt_reg[7]_i_2__0_n_0 ;
  wire \converge_cnt_reg[8]_i_1__0_n_0 ;
  wire \converge_cnt_reg[8]_i_2__0_n_0 ;
  wire \converge_cnt_reg[9]_i_1__0_n_0 ;
  wire \converge_cnt_reg[9]_i_2__0_n_0 ;
  wire converge_gen3_i_1__0_n_0;
  wire converge_gen3_reg_n_0;
  wire \cplllock_reg1_reg[1] ;
  wire [1:0]fsm;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire gt_rxvalid_q_i_6__0_n_0;
  wire gt_rxvalid_q_reg;
  wire gt_rxvalid_q_reg_0;
  wire \gtx_channel.gtxe2_channel_i_i_73_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_82_n_0 ;
  wire [1:0]oobclk_cnt;
  wire \oobclk_div.oobclk_i_1__0_n_0 ;
  wire [0:0]out1;
  wire p_0_in7_in_1;
  wire [3:0]p_0_in__0;
  wire [3:0]p_0_in__0__0;
  wire p_1_in8_in_0;
  wire [1:0]p_1_in__0;
  wire pclk_sel_reg;
  wire pclk_sel_reg1;
  wire pclk_sel_reg2;
  wire [0:0]pipe_rxstatus;
  wire [1:0]pipe_txphaligndone;
  wire [1:0]pipe_txphinitdone;
  wire rate_done_reg1;
  wire rate_done_reg2;
  wire [0:0]rate_gen3;
  wire rate_gen3_reg1;
  wire rate_gen3_reg2;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire rate_rxsync_reg1;
  wire rate_rxsync_reg2;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire resetovrd_done_reg1_reg;
  wire resetovrd_start_reg1;
  wire resetovrd_start_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire [3:0]rxcdrlock_cnt_reg__0__0;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxeq_adapt_done_reg1;
  wire rxeq_adapt_done_reg2;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxstatus_reg1;
  wire rxstatus_reg2;
  wire [3:0]rxvalid_cnt_reg__0__0;
  wire rxvalid_reg1;
  wire rxvalid_reg2;
  wire sel;
  wire txcompliance_reg1;
  wire txcompliance_reg2;
  wire txelecidle_reg1;
  wire txelecidle_reg2;
  wire txelecidle_reg2_reg_0;
  wire txphaligndone_reg1_reg;
  wire txphaligndone_reg1_reg_0;
  wire txphinitdone_reg1_reg;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire [0:0]user_active_lane;
  wire [0:0]user_rx_converge;
  wire [3:0]\NLW_converge_cnt_reg[21]_i_2__0_CARRY4_CO_UNCONNECTED ;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__0_CARRY4_DI_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__0_CARRY4_O_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__0_CARRY4_S_UNCONNECTED ;

  assign p_0_in7_in = txcompliance_reg2;
  assign p_1_in8_in = txelecidle_reg2;
  assign p_2_in = rst_idle_reg2;
  LUT4 #(
    .INIT(16'hFFF7)) 
    \converge_cnt[0]_i_1__0 
       (.I0(rate_idle_reg2),
        .I1(rst_idle_reg2),
        .I2(RST_CPLLRESET),
        .I3(rate_gen3_reg2),
        .O(\converge_cnt[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h5D5D555D)) 
    \converge_cnt[0]_i_2__0 
       (.I0(converge_cnt_reg[21]),
        .I1(\converge_cnt[0]_i_4__0_n_0 ),
        .I2(converge_cnt_reg[20]),
        .I3(\converge_cnt[0]_i_5__0_n_0 ),
        .I4(\converge_cnt[0]_i_6__0_n_0 ),
        .O(sel));
  LUT6 #(
    .INIT(64'h13FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_4__0 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(converge_cnt_reg[13]),
        .I3(converge_cnt_reg[16]),
        .I4(converge_cnt_reg[15]),
        .I5(\converge_cnt[0]_i_8__0_n_0 ),
        .O(\converge_cnt[0]_i_4__0_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \converge_cnt[0]_i_5__0 
       (.I0(\converge_cnt[0]_i_8__0_n_0 ),
        .I1(converge_cnt_reg[16]),
        .I2(converge_cnt_reg[15]),
        .I3(converge_cnt_reg[13]),
        .I4(converge_cnt_reg[11]),
        .O(\converge_cnt[0]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'h10FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_6__0 
       (.I0(converge_cnt_reg[3]),
        .I1(converge_cnt_reg[6]),
        .I2(\converge_cnt[0]_i_9__0_n_0 ),
        .I3(converge_cnt_reg[10]),
        .I4(converge_cnt_reg[8]),
        .I5(converge_cnt_reg[9]),
        .O(\converge_cnt[0]_i_6__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[0]_i_7__0 
       (.I0(converge_cnt_reg[0]),
        .O(\converge_cnt[0]_i_7__0_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \converge_cnt[0]_i_8__0 
       (.I0(converge_cnt_reg[17]),
        .I1(converge_cnt_reg[18]),
        .I2(converge_cnt_reg[19]),
        .O(\converge_cnt[0]_i_8__0_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \converge_cnt[0]_i_9__0 
       (.I0(converge_cnt_reg[4]),
        .I1(converge_cnt_reg[5]),
        .I2(converge_cnt_reg[7]),
        .O(\converge_cnt[0]_i_9__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[0]_i_3__0_n_0 ),
        .Q(converge_cnt_reg[0]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[10]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[10]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[11]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[11]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[12]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[12]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[13]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[13]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[13]_i_2__0_CARRY4 
       (.CI(\converge_cnt_reg[12]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[16]_i_2__0_n_0 ,\converge_cnt_reg[15]_i_2__0_n_0 ,\converge_cnt_reg[14]_i_2__0_n_0 ,\converge_cnt_reg[13]_i_2__0_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[15]_i_1__0_n_0 ,\converge_cnt_reg[14]_i_1__0_n_0 ,\converge_cnt_reg[13]_i_1__0_n_0 ,\converge_cnt_reg[12]_i_1__0_n_0 }),
        .S(converge_cnt_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[14]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[14]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[15]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[15]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[16]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[16]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[17]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[17]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[17]_i_2__0_CARRY4 
       (.CI(\converge_cnt_reg[16]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[20]_i_2__0_n_0 ,\converge_cnt_reg[19]_i_2__0_n_0 ,\converge_cnt_reg[18]_i_2__0_n_0 ,\converge_cnt_reg[17]_i_2__0_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[19]_i_1__0_n_0 ,\converge_cnt_reg[18]_i_1__0_n_0 ,\converge_cnt_reg[17]_i_1__0_n_0 ,\converge_cnt_reg[16]_i_1__0_n_0 }),
        .S(converge_cnt_reg[19:16]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[18]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[18]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[19]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[19]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[1]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[1]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[1]_i_2__0_CARRY4 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[4]_i_2__0_n_0 ,\converge_cnt_reg[3]_i_2__0_n_0 ,\converge_cnt_reg[2]_i_2__0_n_0 ,\converge_cnt_reg[1]_i_2__0_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\converge_cnt_reg[3]_i_1__0_n_0 ,\converge_cnt_reg[2]_i_1__0_n_0 ,\converge_cnt_reg[1]_i_1__0_n_0 ,\converge_cnt_reg[0]_i_3__0_n_0 }),
        .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_7__0_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[20]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[20]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[21]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[21]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[21]_i_2__0_CARRY4 
       (.CI(\converge_cnt_reg[20]_i_2__0_n_0 ),
        .CO(\NLW_converge_cnt_reg[21]_i_2__0_CARRY4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({\NLW_converge_cnt_reg[21]_i_2__0_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__0_CARRY4_O_UNCONNECTED [3:2],\converge_cnt_reg[21]_i_1__0_n_0 ,\converge_cnt_reg[20]_i_1__0_n_0 }),
        .S({\NLW_converge_cnt_reg[21]_i_2__0_CARRY4_S_UNCONNECTED [3:2],converge_cnt_reg[21:20]}));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[2]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[2]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[3]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[3]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[4]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[4]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[5]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[5]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[5]_i_2__0_CARRY4 
       (.CI(\converge_cnt_reg[4]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[8]_i_2__0_n_0 ,\converge_cnt_reg[7]_i_2__0_n_0 ,\converge_cnt_reg[6]_i_2__0_n_0 ,\converge_cnt_reg[5]_i_2__0_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[7]_i_1__0_n_0 ,\converge_cnt_reg[6]_i_1__0_n_0 ,\converge_cnt_reg[5]_i_1__0_n_0 ,\converge_cnt_reg[4]_i_1__0_n_0 }),
        .S(converge_cnt_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[6]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[6]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[7]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[7]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[8]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[8]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[9]_i_1__0_n_0 ),
        .Q(converge_cnt_reg[9]),
        .R(\converge_cnt[0]_i_1__0_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[9]_i_2__0_CARRY4 
       (.CI(\converge_cnt_reg[8]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[12]_i_2__0_n_0 ,\converge_cnt_reg[11]_i_2__0_n_0 ,\converge_cnt_reg[10]_i_2__0_n_0 ,\converge_cnt_reg[9]_i_2__0_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[11]_i_1__0_n_0 ,\converge_cnt_reg[10]_i_1__0_n_0 ,\converge_cnt_reg[9]_i_1__0_n_0 ,\converge_cnt_reg[8]_i_1__0_n_0 }),
        .S(converge_cnt_reg[11:8]));
  LUT4 #(
    .INIT(16'h0C08)) 
    converge_gen3_i_1__0
       (.I0(rxeq_adapt_done_reg2),
        .I1(rate_gen3_reg2),
        .I2(RST_CPLLRESET),
        .I3(converge_gen3_reg_n_0),
        .O(converge_gen3_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    converge_gen3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_gen3_i_1__0_n_0),
        .Q(converge_gen3_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFE0FF)) 
    gt_rx_phy_status_q_i_1__0
       (.I0(rate_idle_reg2),
        .I1(rate_rxsync_reg2),
        .I2(RST_PHYSTATUS),
        .I3(rst_idle_reg2),
        .I4(rate_done_reg2),
        .O(gt_rx_phy_status_wire_filter));
  LUT6 #(
    .INIT(64'h4500000000000000)) 
    gt_rxvalid_q_i_4__0
       (.I0(gt_rxvalid_q_i_6__0_n_0),
        .I1(gt_rxvalid_q_reg_0),
        .I2(gt_rx_elec_idle_wire_filter),
        .I3(rst_idle_reg2),
        .I4(rate_idle_reg2),
        .I5(\resetovrd_disble.reset_reg[4]_0 ),
        .O(gt_rxvalid_q_reg));
  LUT4 #(
    .INIT(16'h7FFF)) 
    gt_rxvalid_q_i_6__0
       (.I0(rxvalid_cnt_reg__0__0[3]),
        .I1(rxvalid_cnt_reg__0__0[2]),
        .I2(rxvalid_cnt_reg__0__0[0]),
        .I3(rxvalid_cnt_reg__0__0[1]),
        .O(gt_rxvalid_q_i_6__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_5__0 
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(\cplllock_reg1_reg[1] ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \gtx_channel.gtxe2_channel_i_i_63 
       (.I0(converge_gen3_reg_n_0),
        .I1(\gtx_channel.gtxe2_channel_i_i_73_n_0 ),
        .I2(converge_cnt_reg[8]),
        .I3(converge_cnt_reg[9]),
        .I4(\converge_cnt[0]_i_9__0_n_0 ),
        .I5(\converge_cnt[0]_i_5__0_n_0 ),
        .O(user_rx_converge));
  LUT5 #(
    .INIT(32'h00000010)) 
    \gtx_channel.gtxe2_channel_i_i_73 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(\gtx_channel.gtxe2_channel_i_i_82_n_0 ),
        .I3(converge_cnt_reg[2]),
        .I4(converge_cnt_reg[6]),
        .O(\gtx_channel.gtxe2_channel_i_i_73_n_0 ));
  LUT6 #(
    .INIT(64'h0004000000000000)) 
    \gtx_channel.gtxe2_channel_i_i_82 
       (.I0(converge_cnt_reg[20]),
        .I1(converge_cnt_reg[3]),
        .I2(converge_cnt_reg[0]),
        .I3(converge_cnt_reg[1]),
        .I4(converge_cnt_reg[10]),
        .I5(converge_cnt_reg[21]),
        .O(\gtx_channel.gtxe2_channel_i_i_82_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oobclk_div.oobclk_cnt[0]_i_1__0 
       (.I0(oobclk_cnt[0]),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \oobclk_div.oobclk_cnt[1]_i_1__0 
       (.I0(oobclk_cnt[0]),
        .I1(oobclk_cnt[1]),
        .O(p_1_in__0[1]));
  FDRE \oobclk_div.oobclk_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[0]),
        .Q(oobclk_cnt[0]),
        .R(RST_CPLLRESET));
  FDRE \oobclk_div.oobclk_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[1]),
        .Q(oobclk_cnt[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hB8)) 
    \oobclk_div.oobclk_i_1__0 
       (.I0(oobclk_cnt[1]),
        .I1(pclk_sel_reg2),
        .I2(oobclk_cnt[0]),
        .O(\oobclk_div.oobclk_i_1__0_n_0 ));
  FDRE \oobclk_div.oobclk_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\oobclk_div.oobclk_i_1__0_n_0 ),
        .Q(USER_OOBCLK),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(CLK_PCLK_SEL),
        .Q(pclk_sel_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pclk_sel_reg1),
        .Q(pclk_sel_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_DONE),
        .Q(rate_done_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_done_reg1),
        .Q(rate_done_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(rate_gen3_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3_reg1),
        .Q(rate_gen3_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_RXSYNC),
        .Q(rate_rxsync_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_rxsync_reg1),
        .Q(rate_rxsync_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT2 #(
    .INIT(4'h8)) 
    \resetdone_reg1[1]_i_1 
       (.I0(txresetdone_reg2),
        .I1(rxresetdone_reg2),
        .O(RST_RESETDONE));
  FDRE \resetovrd_disble.fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT2 #(
    .INIT(4'h1)) 
    resetovrd_done_reg1_i_1__0
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(resetovrd_done_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RESETOVRD_START),
        .Q(resetovrd_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetovrd_start_reg1),
        .Q(resetovrd_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(out1),
        .Q(rst_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT5 #(
    .INIT(32'h8A0A0A0A)) 
    \rxcdrlock_cnt[0]_i_1__0 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0__0[2]),
        .I2(rxcdrlock_cnt_reg__0__0[0]),
        .I3(rxcdrlock_cnt_reg__0__0[1]),
        .I4(rxcdrlock_cnt_reg__0__0[3]),
        .O(p_0_in__0[0]));
  LUT5 #(
    .INIT(32'hA8282828)) 
    \rxcdrlock_cnt[1]_i_1__0 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0__0[0]),
        .I2(rxcdrlock_cnt_reg__0__0[1]),
        .I3(rxcdrlock_cnt_reg__0__0[2]),
        .I4(rxcdrlock_cnt_reg__0__0[3]),
        .O(p_0_in__0[1]));
  LUT5 #(
    .INIT(32'h8CCCC000)) 
    \rxcdrlock_cnt[2]_i_1__0 
       (.I0(rxcdrlock_cnt_reg__0__0[3]),
        .I1(rxcdrlock_reg2),
        .I2(rxcdrlock_cnt_reg__0__0[1]),
        .I3(rxcdrlock_cnt_reg__0__0[0]),
        .I4(rxcdrlock_cnt_reg__0__0[2]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \rxcdrlock_cnt[3]_i_1__0 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0__0[3]),
        .I2(rxcdrlock_cnt_reg__0__0[1]),
        .I3(rxcdrlock_cnt_reg__0__0[0]),
        .I4(rxcdrlock_cnt_reg__0__0[2]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(rxcdrlock_cnt_reg__0__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(rxcdrlock_cnt_reg__0__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(rxcdrlock_cnt_reg__0__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(rxcdrlock_cnt_reg__0__0[3]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h80000000)) 
    \rxcdrlock_reg1[1]_i_1 
       (.I0(\resetovrd_disble.reset_reg[4]_1 ),
        .I1(rxcdrlock_cnt_reg__0__0[3]),
        .I2(rxcdrlock_cnt_reg__0__0[1]),
        .I3(rxcdrlock_cnt_reg__0__0[0]),
        .I4(rxcdrlock_cnt_reg__0__0[2]),
        .O(RST_RXCDRLOCK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXEQ_ADAPT_DONE),
        .Q(rxeq_adapt_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_adapt_done_reg1),
        .Q(rxeq_adapt_done_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pipe_rxstatus),
        .Q(rxstatus_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxstatus_reg1),
        .Q(rxstatus_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT6 #(
    .INIT(64'h8080000000FF0000)) 
    \rxvalid_cnt[0]_i_1__0 
       (.I0(rxvalid_cnt_reg__0__0[3]),
        .I1(rxvalid_cnt_reg__0__0[2]),
        .I2(rxvalid_cnt_reg__0__0[1]),
        .I3(rxstatus_reg2),
        .I4(rxvalid_reg2),
        .I5(rxvalid_cnt_reg__0__0[0]),
        .O(p_0_in__0__0[0]));
  LUT6 #(
    .INIT(64'h80000000E6660000)) 
    \rxvalid_cnt[1]_i_1__0 
       (.I0(rxvalid_cnt_reg__0__0[0]),
        .I1(rxvalid_cnt_reg__0__0[1]),
        .I2(rxvalid_cnt_reg__0__0[2]),
        .I3(rxvalid_cnt_reg__0__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[1]));
  LUT6 #(
    .INIT(64'h80000000EA6A0000)) 
    \rxvalid_cnt[2]_i_1__0 
       (.I0(rxvalid_cnt_reg__0__0[2]),
        .I1(rxvalid_cnt_reg__0__0[1]),
        .I2(rxvalid_cnt_reg__0__0[0]),
        .I3(rxvalid_cnt_reg__0__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'hD444444400000000)) 
    \rxvalid_cnt[3]_i_1__0 
       (.I0(rxstatus_reg2),
        .I1(rxvalid_cnt_reg__0__0[3]),
        .I2(rxvalid_cnt_reg__0__0[2]),
        .I3(rxvalid_cnt_reg__0__0[0]),
        .I4(rxvalid_cnt_reg__0__0[1]),
        .I5(rxvalid_reg2),
        .O(p_0_in__0__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(rxvalid_cnt_reg__0__0[0]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(rxvalid_cnt_reg__0__0[1]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(rxvalid_cnt_reg__0__0[2]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(rxvalid_cnt_reg__0__0[3]),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxvalid_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxvalid_reg1),
        .Q(rxvalid_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXCOMPLIANCE),
        .Q(txcompliance_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcompliance_reg1),
        .Q(txcompliance_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXELECIDLE),
        .Q(txelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg1),
        .Q(txelecidle_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h8A8A8AAA8AAA8AAA)) 
    txphaligndone_reg1_i_3
       (.I0(user_active_lane),
        .I1(txelecidle_reg2_reg_0),
        .I2(pipe_txphaligndone[1]),
        .I3(pipe_txphaligndone[0]),
        .I4(txelecidle_reg2),
        .I5(txcompliance_reg2),
        .O(txphaligndone_reg1_reg));
  LUT3 #(
    .INIT(8'h07)) 
    txphaligndone_reg1_i_9
       (.I0(txcompliance_reg2),
        .I1(txelecidle_reg2),
        .I2(pipe_txphaligndone[0]),
        .O(txphaligndone_reg1_reg_0));
  LUT6 #(
    .INIT(64'hF8F8F8F8F8000000)) 
    txphinitdone_reg1_i_9
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .I2(pipe_txphinitdone[0]),
        .I3(p_1_in8_in_0),
        .I4(p_0_in7_in_1),
        .I5(pipe_txphinitdone[1]),
        .O(txphinitdone_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_user" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_40
   (txphaligndone_reg1_reg,
    p_1_in8_in,
    p_0_in7_in,
    txphinitdone_reg1_reg,
    txphinitdone_reg1_reg_0,
    gt_rxvalid_q_reg,
    p_2_in,
    USER_OOBCLK,
    Q,
    RST_RXCDRLOCK,
    gt_rx_phy_status_wire_filter,
    user_rx_converge,
    \cplllock_reg1_reg[2] ,
    resetovrd_done_reg1_reg,
    RST_RESETDONE,
    user_active_lane,
    pipe_txphaligndone,
    p_1_in8_in_0,
    p_0_in7_in_1,
    pipe_txphinitdone,
    txelecidle_reg2_reg_0,
    p_1_in8_in_2,
    p_0_in7_in_3,
    gt_rxvalid_q_reg_0,
    gt_rx_elec_idle_wire_filter,
    \resetovrd_disble.reset_reg[4]_0 ,
    RST_CPLLRESET,
    pclk_sel_reg,
    CLK_PCLK_SEL,
    USER_RXRESETDONE,
    USER_TXRESETDONE,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    \resetovrd_disble.reset_reg[4]_1 ,
    RST_RXUSRCLK_RESET,
    pipe_rxstatus,
    out1,
    RST_RATE_IDLE,
    USER_RATE_RXSYNC,
    USER_RATE_DONE,
    rate_gen3,
    USER_RXEQ_ADAPT_DONE,
    USER_RESETOVRD_START,
    RST_PHYSTATUS);
  output txphaligndone_reg1_reg;
  output p_1_in8_in;
  output p_0_in7_in;
  output txphinitdone_reg1_reg;
  output txphinitdone_reg1_reg_0;
  output gt_rxvalid_q_reg;
  output p_2_in;
  output USER_OOBCLK;
  output [6:0]Q;
  output [0:0]RST_RXCDRLOCK;
  output [0:0]gt_rx_phy_status_wire_filter;
  output [0:0]user_rx_converge;
  output \cplllock_reg1_reg[2] ;
  output resetovrd_done_reg1_reg;
  output [0:0]RST_RESETDONE;
  output [0:0]user_active_lane;
  input [1:0]pipe_txphaligndone;
  input p_1_in8_in_0;
  input p_0_in7_in_1;
  input [2:0]pipe_txphinitdone;
  input txelecidle_reg2_reg_0;
  input p_1_in8_in_2;
  input p_0_in7_in_3;
  input gt_rxvalid_q_reg_0;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]CLK_PCLK_SEL;
  input USER_RXRESETDONE;
  input USER_TXRESETDONE;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [0:0]PIPE_TXELECIDLE;
  input \resetovrd_disble.reset_reg[4]_1 ;
  input RST_RXUSRCLK_RESET;
  input [0:0]pipe_rxstatus;
  input [0:0]out1;
  input [0:0]RST_RATE_IDLE;
  input USER_RATE_RXSYNC;
  input USER_RATE_DONE;
  input [0:0]rate_gen3;
  input USER_RXEQ_ADAPT_DONE;
  input USER_RESETOVRD_START;
  input [0:0]RST_PHYSTATUS;

  wire [0:0]CLK_PCLK_SEL;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [0:0]PIPE_TXELECIDLE;
  wire [6:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_PHYSTATUS;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_RESETDONE;
  wire [0:0]RST_RXCDRLOCK;
  wire RST_RXUSRCLK_RESET;
  wire USER_OOBCLK;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXEQ_ADAPT_DONE;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire \converge_cnt[0]_i_1__1_n_0 ;
  wire \converge_cnt[0]_i_4__1_n_0 ;
  wire \converge_cnt[0]_i_5__1_n_0 ;
  wire \converge_cnt[0]_i_6__1_n_0 ;
  wire \converge_cnt[0]_i_7__1_n_0 ;
  wire \converge_cnt[0]_i_8__1_n_0 ;
  wire \converge_cnt[0]_i_9__1_n_0 ;
  wire [21:0]converge_cnt_reg;
  wire \converge_cnt_reg[0]_i_3__1_n_0 ;
  wire \converge_cnt_reg[10]_i_1__1_n_0 ;
  wire \converge_cnt_reg[10]_i_2__1_n_0 ;
  wire \converge_cnt_reg[11]_i_1__1_n_0 ;
  wire \converge_cnt_reg[11]_i_2__1_n_0 ;
  wire \converge_cnt_reg[12]_i_1__1_n_0 ;
  wire \converge_cnt_reg[12]_i_2__1_n_0 ;
  wire \converge_cnt_reg[13]_i_1__1_n_0 ;
  wire \converge_cnt_reg[13]_i_2__1_n_0 ;
  wire \converge_cnt_reg[14]_i_1__1_n_0 ;
  wire \converge_cnt_reg[14]_i_2__1_n_0 ;
  wire \converge_cnt_reg[15]_i_1__1_n_0 ;
  wire \converge_cnt_reg[15]_i_2__1_n_0 ;
  wire \converge_cnt_reg[16]_i_1__1_n_0 ;
  wire \converge_cnt_reg[16]_i_2__1_n_0 ;
  wire \converge_cnt_reg[17]_i_1__1_n_0 ;
  wire \converge_cnt_reg[17]_i_2__1_n_0 ;
  wire \converge_cnt_reg[18]_i_1__1_n_0 ;
  wire \converge_cnt_reg[18]_i_2__1_n_0 ;
  wire \converge_cnt_reg[19]_i_1__1_n_0 ;
  wire \converge_cnt_reg[19]_i_2__1_n_0 ;
  wire \converge_cnt_reg[1]_i_1__1_n_0 ;
  wire \converge_cnt_reg[1]_i_2__1_n_0 ;
  wire \converge_cnt_reg[20]_i_1__1_n_0 ;
  wire \converge_cnt_reg[20]_i_2__1_n_0 ;
  wire \converge_cnt_reg[21]_i_1__1_n_0 ;
  wire \converge_cnt_reg[2]_i_1__1_n_0 ;
  wire \converge_cnt_reg[2]_i_2__1_n_0 ;
  wire \converge_cnt_reg[3]_i_1__1_n_0 ;
  wire \converge_cnt_reg[3]_i_2__1_n_0 ;
  wire \converge_cnt_reg[4]_i_1__1_n_0 ;
  wire \converge_cnt_reg[4]_i_2__1_n_0 ;
  wire \converge_cnt_reg[5]_i_1__1_n_0 ;
  wire \converge_cnt_reg[5]_i_2__1_n_0 ;
  wire \converge_cnt_reg[6]_i_1__1_n_0 ;
  wire \converge_cnt_reg[6]_i_2__1_n_0 ;
  wire \converge_cnt_reg[7]_i_1__1_n_0 ;
  wire \converge_cnt_reg[7]_i_2__1_n_0 ;
  wire \converge_cnt_reg[8]_i_1__1_n_0 ;
  wire \converge_cnt_reg[8]_i_2__1_n_0 ;
  wire \converge_cnt_reg[9]_i_1__1_n_0 ;
  wire \converge_cnt_reg[9]_i_2__1_n_0 ;
  wire converge_gen3_i_1__1_n_0;
  wire converge_gen3_reg_n_0;
  wire \cplllock_reg1_reg[2] ;
  wire [1:0]fsm;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire gt_rxvalid_q_i_6__1_n_0;
  wire gt_rxvalid_q_reg;
  wire gt_rxvalid_q_reg_0;
  wire \gtx_channel.gtxe2_channel_i_i_77_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_85_n_0 ;
  wire [1:0]oobclk_cnt;
  wire \oobclk_div.oobclk_i_1__1_n_0 ;
  wire [0:0]out1;
  wire p_0_in7_in_1;
  wire p_0_in7_in_3;
  wire [3:0]p_0_in__0;
  wire [3:0]p_0_in__0__0;
  wire p_1_in8_in_0;
  wire p_1_in8_in_2;
  wire [1:0]p_1_in__0;
  wire pclk_sel_reg;
  wire pclk_sel_reg1;
  wire pclk_sel_reg2;
  wire [0:0]pipe_rxstatus;
  wire [1:0]pipe_txphaligndone;
  wire [2:0]pipe_txphinitdone;
  wire rate_done_reg1;
  wire rate_done_reg2;
  wire [0:0]rate_gen3;
  wire rate_gen3_reg1;
  wire rate_gen3_reg2;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire rate_rxsync_reg1;
  wire rate_rxsync_reg2;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire resetovrd_done_reg1_reg;
  wire resetovrd_start_reg1;
  wire resetovrd_start_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire [3:0]rxcdrlock_cnt_reg__0;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxeq_adapt_done_reg1;
  wire rxeq_adapt_done_reg2;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxstatus_reg1;
  wire rxstatus_reg2;
  wire [3:0]rxvalid_cnt_reg__0;
  wire rxvalid_reg1;
  wire rxvalid_reg2;
  wire sel;
  wire txcompliance_reg1;
  wire txcompliance_reg2;
  wire txelecidle_reg1;
  wire txelecidle_reg2;
  wire txelecidle_reg2_reg_0;
  wire txphaligndone_reg1_reg;
  wire txphinitdone_reg1_reg;
  wire txphinitdone_reg1_reg_0;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire [0:0]user_active_lane;
  wire [0:0]user_rx_converge;
  wire [3:0]\NLW_converge_cnt_reg[21]_i_2__1_CARRY4_CO_UNCONNECTED ;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__1_CARRY4_DI_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__1_CARRY4_O_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__1_CARRY4_S_UNCONNECTED ;

  assign p_0_in7_in = txcompliance_reg2;
  assign p_1_in8_in = txelecidle_reg2;
  assign p_2_in = rst_idle_reg2;
  LUT4 #(
    .INIT(16'hFFF7)) 
    \converge_cnt[0]_i_1__1 
       (.I0(rate_idle_reg2),
        .I1(rst_idle_reg2),
        .I2(RST_CPLLRESET),
        .I3(rate_gen3_reg2),
        .O(\converge_cnt[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h5D5D555D)) 
    \converge_cnt[0]_i_2__1 
       (.I0(converge_cnt_reg[21]),
        .I1(\converge_cnt[0]_i_4__1_n_0 ),
        .I2(converge_cnt_reg[20]),
        .I3(\converge_cnt[0]_i_5__1_n_0 ),
        .I4(\converge_cnt[0]_i_6__1_n_0 ),
        .O(sel));
  LUT6 #(
    .INIT(64'h13FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_4__1 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(converge_cnt_reg[13]),
        .I3(converge_cnt_reg[16]),
        .I4(converge_cnt_reg[15]),
        .I5(\converge_cnt[0]_i_8__1_n_0 ),
        .O(\converge_cnt[0]_i_4__1_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \converge_cnt[0]_i_5__1 
       (.I0(\converge_cnt[0]_i_8__1_n_0 ),
        .I1(converge_cnt_reg[16]),
        .I2(converge_cnt_reg[15]),
        .I3(converge_cnt_reg[13]),
        .I4(converge_cnt_reg[11]),
        .O(\converge_cnt[0]_i_5__1_n_0 ));
  LUT6 #(
    .INIT(64'h10FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_6__1 
       (.I0(converge_cnt_reg[3]),
        .I1(converge_cnt_reg[6]),
        .I2(\converge_cnt[0]_i_9__1_n_0 ),
        .I3(converge_cnt_reg[10]),
        .I4(converge_cnt_reg[8]),
        .I5(converge_cnt_reg[9]),
        .O(\converge_cnt[0]_i_6__1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[0]_i_7__1 
       (.I0(converge_cnt_reg[0]),
        .O(\converge_cnt[0]_i_7__1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \converge_cnt[0]_i_8__1 
       (.I0(converge_cnt_reg[17]),
        .I1(converge_cnt_reg[18]),
        .I2(converge_cnt_reg[19]),
        .O(\converge_cnt[0]_i_8__1_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \converge_cnt[0]_i_9__1 
       (.I0(converge_cnt_reg[4]),
        .I1(converge_cnt_reg[5]),
        .I2(converge_cnt_reg[7]),
        .O(\converge_cnt[0]_i_9__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[0]_i_3__1_n_0 ),
        .Q(converge_cnt_reg[0]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[10]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[10]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[11]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[11]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[12]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[12]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[13]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[13]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[13]_i_2__1_CARRY4 
       (.CI(\converge_cnt_reg[12]_i_2__1_n_0 ),
        .CO({\converge_cnt_reg[16]_i_2__1_n_0 ,\converge_cnt_reg[15]_i_2__1_n_0 ,\converge_cnt_reg[14]_i_2__1_n_0 ,\converge_cnt_reg[13]_i_2__1_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[15]_i_1__1_n_0 ,\converge_cnt_reg[14]_i_1__1_n_0 ,\converge_cnt_reg[13]_i_1__1_n_0 ,\converge_cnt_reg[12]_i_1__1_n_0 }),
        .S(converge_cnt_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[14]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[14]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[15]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[15]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[16]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[16]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[17]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[17]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[17]_i_2__1_CARRY4 
       (.CI(\converge_cnt_reg[16]_i_2__1_n_0 ),
        .CO({\converge_cnt_reg[20]_i_2__1_n_0 ,\converge_cnt_reg[19]_i_2__1_n_0 ,\converge_cnt_reg[18]_i_2__1_n_0 ,\converge_cnt_reg[17]_i_2__1_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[19]_i_1__1_n_0 ,\converge_cnt_reg[18]_i_1__1_n_0 ,\converge_cnt_reg[17]_i_1__1_n_0 ,\converge_cnt_reg[16]_i_1__1_n_0 }),
        .S(converge_cnt_reg[19:16]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[18]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[18]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[19]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[19]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[1]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[1]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[1]_i_2__1_CARRY4 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[4]_i_2__1_n_0 ,\converge_cnt_reg[3]_i_2__1_n_0 ,\converge_cnt_reg[2]_i_2__1_n_0 ,\converge_cnt_reg[1]_i_2__1_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\converge_cnt_reg[3]_i_1__1_n_0 ,\converge_cnt_reg[2]_i_1__1_n_0 ,\converge_cnt_reg[1]_i_1__1_n_0 ,\converge_cnt_reg[0]_i_3__1_n_0 }),
        .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_7__1_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[20]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[20]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[21]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[21]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[21]_i_2__1_CARRY4 
       (.CI(\converge_cnt_reg[20]_i_2__1_n_0 ),
        .CO(\NLW_converge_cnt_reg[21]_i_2__1_CARRY4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({\NLW_converge_cnt_reg[21]_i_2__1_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__1_CARRY4_O_UNCONNECTED [3:2],\converge_cnt_reg[21]_i_1__1_n_0 ,\converge_cnt_reg[20]_i_1__1_n_0 }),
        .S({\NLW_converge_cnt_reg[21]_i_2__1_CARRY4_S_UNCONNECTED [3:2],converge_cnt_reg[21:20]}));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[2]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[2]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[3]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[3]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[4]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[4]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[5]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[5]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[5]_i_2__1_CARRY4 
       (.CI(\converge_cnt_reg[4]_i_2__1_n_0 ),
        .CO({\converge_cnt_reg[8]_i_2__1_n_0 ,\converge_cnt_reg[7]_i_2__1_n_0 ,\converge_cnt_reg[6]_i_2__1_n_0 ,\converge_cnt_reg[5]_i_2__1_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[7]_i_1__1_n_0 ,\converge_cnt_reg[6]_i_1__1_n_0 ,\converge_cnt_reg[5]_i_1__1_n_0 ,\converge_cnt_reg[4]_i_1__1_n_0 }),
        .S(converge_cnt_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[6]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[6]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[7]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[7]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[8]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[8]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[9]_i_1__1_n_0 ),
        .Q(converge_cnt_reg[9]),
        .R(\converge_cnt[0]_i_1__1_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[9]_i_2__1_CARRY4 
       (.CI(\converge_cnt_reg[8]_i_2__1_n_0 ),
        .CO({\converge_cnt_reg[12]_i_2__1_n_0 ,\converge_cnt_reg[11]_i_2__1_n_0 ,\converge_cnt_reg[10]_i_2__1_n_0 ,\converge_cnt_reg[9]_i_2__1_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[11]_i_1__1_n_0 ,\converge_cnt_reg[10]_i_1__1_n_0 ,\converge_cnt_reg[9]_i_1__1_n_0 ,\converge_cnt_reg[8]_i_1__1_n_0 }),
        .S(converge_cnt_reg[11:8]));
  LUT4 #(
    .INIT(16'h0C08)) 
    converge_gen3_i_1__1
       (.I0(rxeq_adapt_done_reg2),
        .I1(rate_gen3_reg2),
        .I2(RST_CPLLRESET),
        .I3(converge_gen3_reg_n_0),
        .O(converge_gen3_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    converge_gen3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_gen3_i_1__1_n_0),
        .Q(converge_gen3_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFE0FF)) 
    gt_rx_phy_status_q_i_1__1
       (.I0(rate_idle_reg2),
        .I1(rate_rxsync_reg2),
        .I2(RST_PHYSTATUS),
        .I3(rst_idle_reg2),
        .I4(rate_done_reg2),
        .O(gt_rx_phy_status_wire_filter));
  LUT6 #(
    .INIT(64'h4500000000000000)) 
    gt_rxvalid_q_i_4__1
       (.I0(gt_rxvalid_q_i_6__1_n_0),
        .I1(gt_rxvalid_q_reg_0),
        .I2(gt_rx_elec_idle_wire_filter),
        .I3(rst_idle_reg2),
        .I4(rate_idle_reg2),
        .I5(\resetovrd_disble.reset_reg[4]_0 ),
        .O(gt_rxvalid_q_reg));
  LUT4 #(
    .INIT(16'h7FFF)) 
    gt_rxvalid_q_i_6__1
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[1]),
        .O(gt_rxvalid_q_i_6__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_5__1 
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(\cplllock_reg1_reg[2] ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \gtx_channel.gtxe2_channel_i_i_66 
       (.I0(converge_gen3_reg_n_0),
        .I1(\gtx_channel.gtxe2_channel_i_i_77_n_0 ),
        .I2(converge_cnt_reg[8]),
        .I3(converge_cnt_reg[9]),
        .I4(\converge_cnt[0]_i_9__1_n_0 ),
        .I5(\converge_cnt[0]_i_5__1_n_0 ),
        .O(user_rx_converge));
  LUT5 #(
    .INIT(32'h00000010)) 
    \gtx_channel.gtxe2_channel_i_i_77 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(\gtx_channel.gtxe2_channel_i_i_85_n_0 ),
        .I3(converge_cnt_reg[2]),
        .I4(converge_cnt_reg[6]),
        .O(\gtx_channel.gtxe2_channel_i_i_77_n_0 ));
  LUT6 #(
    .INIT(64'h0004000000000000)) 
    \gtx_channel.gtxe2_channel_i_i_85 
       (.I0(converge_cnt_reg[20]),
        .I1(converge_cnt_reg[3]),
        .I2(converge_cnt_reg[0]),
        .I3(converge_cnt_reg[1]),
        .I4(converge_cnt_reg[10]),
        .I5(converge_cnt_reg[21]),
        .O(\gtx_channel.gtxe2_channel_i_i_85_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oobclk_div.oobclk_cnt[0]_i_1__1 
       (.I0(oobclk_cnt[0]),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \oobclk_div.oobclk_cnt[1]_i_1__1 
       (.I0(oobclk_cnt[0]),
        .I1(oobclk_cnt[1]),
        .O(p_1_in__0[1]));
  FDRE \oobclk_div.oobclk_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[0]),
        .Q(oobclk_cnt[0]),
        .R(RST_CPLLRESET));
  FDRE \oobclk_div.oobclk_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[1]),
        .Q(oobclk_cnt[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hB8)) 
    \oobclk_div.oobclk_i_1__1 
       (.I0(oobclk_cnt[1]),
        .I1(pclk_sel_reg2),
        .I2(oobclk_cnt[0]),
        .O(\oobclk_div.oobclk_i_1__1_n_0 ));
  FDRE \oobclk_div.oobclk_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\oobclk_div.oobclk_i_1__1_n_0 ),
        .Q(USER_OOBCLK),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(CLK_PCLK_SEL),
        .Q(pclk_sel_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pclk_sel_reg1),
        .Q(pclk_sel_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_DONE),
        .Q(rate_done_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_done_reg1),
        .Q(rate_done_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(rate_gen3_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3_reg1),
        .Q(rate_gen3_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_RXSYNC),
        .Q(rate_rxsync_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_rxsync_reg1),
        .Q(rate_rxsync_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT2 #(
    .INIT(4'h8)) 
    \resetdone_reg1[2]_i_1 
       (.I0(txresetdone_reg2),
        .I1(rxresetdone_reg2),
        .O(RST_RESETDONE));
  FDRE \resetovrd_disble.fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT2 #(
    .INIT(4'h1)) 
    resetovrd_done_reg1_i_1__1
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(resetovrd_done_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RESETOVRD_START),
        .Q(resetovrd_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetovrd_start_reg1),
        .Q(resetovrd_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(out1),
        .Q(rst_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT5 #(
    .INIT(32'h8A0A0A0A)) 
    \rxcdrlock_cnt[0]_i_1__1 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[2]),
        .I2(rxcdrlock_cnt_reg__0[0]),
        .I3(rxcdrlock_cnt_reg__0[1]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[0]));
  LUT5 #(
    .INIT(32'hA8282828)) 
    \rxcdrlock_cnt[1]_i_1__1 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[0]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[2]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[1]));
  LUT5 #(
    .INIT(32'h8CCCC000)) 
    \rxcdrlock_cnt[2]_i_1__1 
       (.I0(rxcdrlock_cnt_reg__0[3]),
        .I1(rxcdrlock_reg2),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \rxcdrlock_cnt[3]_i_1__1 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(rxcdrlock_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(rxcdrlock_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(rxcdrlock_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(rxcdrlock_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h80000000)) 
    \rxcdrlock_reg1[2]_i_1 
       (.I0(\resetovrd_disble.reset_reg[4]_1 ),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(RST_RXCDRLOCK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXEQ_ADAPT_DONE),
        .Q(rxeq_adapt_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_adapt_done_reg1),
        .Q(rxeq_adapt_done_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pipe_rxstatus),
        .Q(rxstatus_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxstatus_reg1),
        .Q(rxstatus_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT6 #(
    .INIT(64'h8080000000FF0000)) 
    \rxvalid_cnt[0]_i_1__1 
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[1]),
        .I3(rxstatus_reg2),
        .I4(rxvalid_reg2),
        .I5(rxvalid_cnt_reg__0[0]),
        .O(p_0_in__0__0[0]));
  LUT6 #(
    .INIT(64'h80000000E6660000)) 
    \rxvalid_cnt[1]_i_1__1 
       (.I0(rxvalid_cnt_reg__0[0]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[1]));
  LUT6 #(
    .INIT(64'h80000000EA6A0000)) 
    \rxvalid_cnt[2]_i_1__1 
       (.I0(rxvalid_cnt_reg__0[2]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'hD444444400000000)) 
    \rxvalid_cnt[3]_i_1__1 
       (.I0(rxstatus_reg2),
        .I1(rxvalid_cnt_reg__0[3]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[0]),
        .I4(rxvalid_cnt_reg__0[1]),
        .I5(rxvalid_reg2),
        .O(p_0_in__0__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(rxvalid_cnt_reg__0[0]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(rxvalid_cnt_reg__0[1]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(rxvalid_cnt_reg__0[2]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(rxvalid_cnt_reg__0[3]),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxvalid_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxvalid_reg1),
        .Q(rxvalid_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXCOMPLIANCE),
        .Q(txcompliance_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcompliance_reg1),
        .Q(txcompliance_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXELECIDLE),
        .Q(txelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg1),
        .Q(txelecidle_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h7)) 
    txphaligndone_reg1_i_10
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .O(user_active_lane));
  LUT6 #(
    .INIT(64'h0707070707FFFFFF)) 
    txphaligndone_reg1_i_8
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .I2(pipe_txphaligndone[1]),
        .I3(p_1_in8_in_0),
        .I4(p_0_in7_in_1),
        .I5(pipe_txphaligndone[0]),
        .O(txphaligndone_reg1_reg));
  LUT5 #(
    .INIT(32'h002AAAAA)) 
    txphinitdone_reg1_i_7
       (.I0(pipe_txphinitdone[0]),
        .I1(txcompliance_reg2),
        .I2(txelecidle_reg2),
        .I3(pipe_txphinitdone[1]),
        .I4(txelecidle_reg2_reg_0),
        .O(txphinitdone_reg1_reg));
  LUT6 #(
    .INIT(64'h151515FF15FF15FF)) 
    txphinitdone_reg1_i_8
       (.I0(pipe_txphinitdone[1]),
        .I1(txelecidle_reg2),
        .I2(txcompliance_reg2),
        .I3(pipe_txphinitdone[2]),
        .I4(p_1_in8_in_2),
        .I5(p_0_in7_in_3),
        .O(txphinitdone_reg1_reg_0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_user" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_46
   (txphaligndone_reg1_reg,
    user_active_lane,
    gt_rxvalid_q_reg,
    p_2_in,
    p_0_in7_in,
    p_1_in8_in,
    USER_OOBCLK,
    Q,
    RST_RXCDRLOCK,
    gt_rx_phy_status_wire_filter,
    user_rx_converge,
    \cplllock_reg1_reg[3] ,
    resetovrd_done_reg1_reg,
    RST_RESETDONE,
    txcompliance_reg2_reg_0,
    txelecidle_reg2_reg_0,
    pipe_txphaligndone,
    gt_rxvalid_q_reg_0,
    gt_rx_elec_idle_wire_filter,
    \resetovrd_disble.reset_reg[4]_0 ,
    RST_CPLLRESET,
    pclk_sel_reg,
    CLK_PCLK_SEL,
    USER_RXRESETDONE,
    USER_TXRESETDONE,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    \resetovrd_disble.reset_reg[4]_1 ,
    RST_RXUSRCLK_RESET,
    pipe_rxstatus,
    out1,
    RST_RATE_IDLE,
    USER_RATE_RXSYNC,
    USER_RATE_DONE,
    rate_gen3,
    USER_RXEQ_ADAPT_DONE,
    USER_RESETOVRD_START,
    RST_PHYSTATUS);
  output txphaligndone_reg1_reg;
  output [0:0]user_active_lane;
  output gt_rxvalid_q_reg;
  output p_2_in;
  output p_0_in7_in;
  output p_1_in8_in;
  output USER_OOBCLK;
  output [6:0]Q;
  output [0:0]RST_RXCDRLOCK;
  output [0:0]gt_rx_phy_status_wire_filter;
  output [0:0]user_rx_converge;
  output \cplllock_reg1_reg[3] ;
  output resetovrd_done_reg1_reg;
  output [0:0]RST_RESETDONE;
  input txcompliance_reg2_reg_0;
  input [1:0]txelecidle_reg2_reg_0;
  input [1:0]pipe_txphaligndone;
  input gt_rxvalid_q_reg_0;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]CLK_PCLK_SEL;
  input USER_RXRESETDONE;
  input USER_TXRESETDONE;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [0:0]PIPE_TXELECIDLE;
  input \resetovrd_disble.reset_reg[4]_1 ;
  input RST_RXUSRCLK_RESET;
  input [0:0]pipe_rxstatus;
  input [0:0]out1;
  input [0:0]RST_RATE_IDLE;
  input USER_RATE_RXSYNC;
  input USER_RATE_DONE;
  input [0:0]rate_gen3;
  input USER_RXEQ_ADAPT_DONE;
  input USER_RESETOVRD_START;
  input [0:0]RST_PHYSTATUS;

  wire [0:0]CLK_PCLK_SEL;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [0:0]PIPE_TXELECIDLE;
  wire [6:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_PHYSTATUS;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_RESETDONE;
  wire [0:0]RST_RXCDRLOCK;
  wire RST_RXUSRCLK_RESET;
  wire USER_OOBCLK;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXEQ_ADAPT_DONE;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire \converge_cnt[0]_i_1__2_n_0 ;
  wire \converge_cnt[0]_i_4__2_n_0 ;
  wire \converge_cnt[0]_i_5__2_n_0 ;
  wire \converge_cnt[0]_i_6__2_n_0 ;
  wire \converge_cnt[0]_i_7__2_n_0 ;
  wire \converge_cnt[0]_i_8__2_n_0 ;
  wire \converge_cnt[0]_i_9__2_n_0 ;
  wire [21:0]converge_cnt_reg;
  wire \converge_cnt_reg[0]_i_3__2_n_0 ;
  wire \converge_cnt_reg[10]_i_1__2_n_0 ;
  wire \converge_cnt_reg[10]_i_2__2_n_0 ;
  wire \converge_cnt_reg[11]_i_1__2_n_0 ;
  wire \converge_cnt_reg[11]_i_2__2_n_0 ;
  wire \converge_cnt_reg[12]_i_1__2_n_0 ;
  wire \converge_cnt_reg[12]_i_2__2_n_0 ;
  wire \converge_cnt_reg[13]_i_1__2_n_0 ;
  wire \converge_cnt_reg[13]_i_2__2_n_0 ;
  wire \converge_cnt_reg[14]_i_1__2_n_0 ;
  wire \converge_cnt_reg[14]_i_2__2_n_0 ;
  wire \converge_cnt_reg[15]_i_1__2_n_0 ;
  wire \converge_cnt_reg[15]_i_2__2_n_0 ;
  wire \converge_cnt_reg[16]_i_1__2_n_0 ;
  wire \converge_cnt_reg[16]_i_2__2_n_0 ;
  wire \converge_cnt_reg[17]_i_1__2_n_0 ;
  wire \converge_cnt_reg[17]_i_2__2_n_0 ;
  wire \converge_cnt_reg[18]_i_1__2_n_0 ;
  wire \converge_cnt_reg[18]_i_2__2_n_0 ;
  wire \converge_cnt_reg[19]_i_1__2_n_0 ;
  wire \converge_cnt_reg[19]_i_2__2_n_0 ;
  wire \converge_cnt_reg[1]_i_1__2_n_0 ;
  wire \converge_cnt_reg[1]_i_2__2_n_0 ;
  wire \converge_cnt_reg[20]_i_1__2_n_0 ;
  wire \converge_cnt_reg[20]_i_2__2_n_0 ;
  wire \converge_cnt_reg[21]_i_1__2_n_0 ;
  wire \converge_cnt_reg[2]_i_1__2_n_0 ;
  wire \converge_cnt_reg[2]_i_2__2_n_0 ;
  wire \converge_cnt_reg[3]_i_1__2_n_0 ;
  wire \converge_cnt_reg[3]_i_2__2_n_0 ;
  wire \converge_cnt_reg[4]_i_1__2_n_0 ;
  wire \converge_cnt_reg[4]_i_2__2_n_0 ;
  wire \converge_cnt_reg[5]_i_1__2_n_0 ;
  wire \converge_cnt_reg[5]_i_2__2_n_0 ;
  wire \converge_cnt_reg[6]_i_1__2_n_0 ;
  wire \converge_cnt_reg[6]_i_2__2_n_0 ;
  wire \converge_cnt_reg[7]_i_1__2_n_0 ;
  wire \converge_cnt_reg[7]_i_2__2_n_0 ;
  wire \converge_cnt_reg[8]_i_1__2_n_0 ;
  wire \converge_cnt_reg[8]_i_2__2_n_0 ;
  wire \converge_cnt_reg[9]_i_1__2_n_0 ;
  wire \converge_cnt_reg[9]_i_2__2_n_0 ;
  wire converge_gen3_i_1__2_n_0;
  wire converge_gen3_reg_n_0;
  wire \cplllock_reg1_reg[3] ;
  wire [1:0]fsm;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire gt_rxvalid_q_i_6__2_n_0;
  wire gt_rxvalid_q_reg;
  wire gt_rxvalid_q_reg_0;
  wire \gtx_channel.gtxe2_channel_i_i_76_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_84_n_0 ;
  wire [1:0]oobclk_cnt;
  wire \oobclk_div.oobclk_i_1__2_n_0 ;
  wire [0:0]out1;
  wire [3:0]p_0_in__0;
  wire [3:0]p_0_in__0__0;
  wire [1:0]p_1_in__0;
  wire pclk_sel_reg;
  wire pclk_sel_reg1;
  wire pclk_sel_reg2;
  wire [0:0]pipe_rxstatus;
  wire [1:0]pipe_txphaligndone;
  wire rate_done_reg1;
  wire rate_done_reg2;
  wire [0:0]rate_gen3;
  wire rate_gen3_reg1;
  wire rate_gen3_reg2;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire rate_rxsync_reg1;
  wire rate_rxsync_reg2;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire resetovrd_done_reg1_reg;
  wire resetovrd_start_reg1;
  wire resetovrd_start_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire [3:0]rxcdrlock_cnt_reg__0;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxeq_adapt_done_reg1;
  wire rxeq_adapt_done_reg2;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxstatus_reg1;
  wire rxstatus_reg2;
  wire [3:0]rxvalid_cnt_reg__0;
  wire rxvalid_reg1;
  wire rxvalid_reg2;
  wire sel;
  wire txcompliance_reg1;
  wire txcompliance_reg2;
  wire txcompliance_reg2_reg_0;
  wire txelecidle_reg1;
  wire txelecidle_reg2;
  wire [1:0]txelecidle_reg2_reg_0;
  wire txphaligndone_reg1_reg;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire [0:0]user_active_lane;
  wire [0:0]user_rx_converge;
  wire [3:0]\NLW_converge_cnt_reg[21]_i_2__2_CARRY4_CO_UNCONNECTED ;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__2_CARRY4_DI_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__2_CARRY4_O_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__2_CARRY4_S_UNCONNECTED ;

  assign p_0_in7_in = txcompliance_reg2;
  assign p_1_in8_in = txelecidle_reg2;
  assign p_2_in = rst_idle_reg2;
  LUT4 #(
    .INIT(16'hFFF7)) 
    \converge_cnt[0]_i_1__2 
       (.I0(rate_idle_reg2),
        .I1(rst_idle_reg2),
        .I2(RST_CPLLRESET),
        .I3(rate_gen3_reg2),
        .O(\converge_cnt[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h5D5D555D)) 
    \converge_cnt[0]_i_2__2 
       (.I0(converge_cnt_reg[21]),
        .I1(\converge_cnt[0]_i_4__2_n_0 ),
        .I2(converge_cnt_reg[20]),
        .I3(\converge_cnt[0]_i_5__2_n_0 ),
        .I4(\converge_cnt[0]_i_6__2_n_0 ),
        .O(sel));
  LUT6 #(
    .INIT(64'h13FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_4__2 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(converge_cnt_reg[13]),
        .I3(converge_cnt_reg[16]),
        .I4(converge_cnt_reg[15]),
        .I5(\converge_cnt[0]_i_8__2_n_0 ),
        .O(\converge_cnt[0]_i_4__2_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \converge_cnt[0]_i_5__2 
       (.I0(\converge_cnt[0]_i_8__2_n_0 ),
        .I1(converge_cnt_reg[16]),
        .I2(converge_cnt_reg[15]),
        .I3(converge_cnt_reg[13]),
        .I4(converge_cnt_reg[11]),
        .O(\converge_cnt[0]_i_5__2_n_0 ));
  LUT6 #(
    .INIT(64'h10FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_6__2 
       (.I0(converge_cnt_reg[3]),
        .I1(converge_cnt_reg[6]),
        .I2(\converge_cnt[0]_i_9__2_n_0 ),
        .I3(converge_cnt_reg[10]),
        .I4(converge_cnt_reg[8]),
        .I5(converge_cnt_reg[9]),
        .O(\converge_cnt[0]_i_6__2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[0]_i_7__2 
       (.I0(converge_cnt_reg[0]),
        .O(\converge_cnt[0]_i_7__2_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \converge_cnt[0]_i_8__2 
       (.I0(converge_cnt_reg[17]),
        .I1(converge_cnt_reg[18]),
        .I2(converge_cnt_reg[19]),
        .O(\converge_cnt[0]_i_8__2_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \converge_cnt[0]_i_9__2 
       (.I0(converge_cnt_reg[4]),
        .I1(converge_cnt_reg[5]),
        .I2(converge_cnt_reg[7]),
        .O(\converge_cnt[0]_i_9__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[0]_i_3__2_n_0 ),
        .Q(converge_cnt_reg[0]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[10]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[10]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[11]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[11]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[12]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[12]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[13]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[13]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[13]_i_2__2_CARRY4 
       (.CI(\converge_cnt_reg[12]_i_2__2_n_0 ),
        .CO({\converge_cnt_reg[16]_i_2__2_n_0 ,\converge_cnt_reg[15]_i_2__2_n_0 ,\converge_cnt_reg[14]_i_2__2_n_0 ,\converge_cnt_reg[13]_i_2__2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[15]_i_1__2_n_0 ,\converge_cnt_reg[14]_i_1__2_n_0 ,\converge_cnt_reg[13]_i_1__2_n_0 ,\converge_cnt_reg[12]_i_1__2_n_0 }),
        .S(converge_cnt_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[14]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[14]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[15]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[15]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[16]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[16]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[17]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[17]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[17]_i_2__2_CARRY4 
       (.CI(\converge_cnt_reg[16]_i_2__2_n_0 ),
        .CO({\converge_cnt_reg[20]_i_2__2_n_0 ,\converge_cnt_reg[19]_i_2__2_n_0 ,\converge_cnt_reg[18]_i_2__2_n_0 ,\converge_cnt_reg[17]_i_2__2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[19]_i_1__2_n_0 ,\converge_cnt_reg[18]_i_1__2_n_0 ,\converge_cnt_reg[17]_i_1__2_n_0 ,\converge_cnt_reg[16]_i_1__2_n_0 }),
        .S(converge_cnt_reg[19:16]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[18]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[18]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[19]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[19]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[1]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[1]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[1]_i_2__2_CARRY4 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[4]_i_2__2_n_0 ,\converge_cnt_reg[3]_i_2__2_n_0 ,\converge_cnt_reg[2]_i_2__2_n_0 ,\converge_cnt_reg[1]_i_2__2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\converge_cnt_reg[3]_i_1__2_n_0 ,\converge_cnt_reg[2]_i_1__2_n_0 ,\converge_cnt_reg[1]_i_1__2_n_0 ,\converge_cnt_reg[0]_i_3__2_n_0 }),
        .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_7__2_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[20]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[20]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[21]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[21]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[21]_i_2__2_CARRY4 
       (.CI(\converge_cnt_reg[20]_i_2__2_n_0 ),
        .CO(\NLW_converge_cnt_reg[21]_i_2__2_CARRY4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({\NLW_converge_cnt_reg[21]_i_2__2_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__2_CARRY4_O_UNCONNECTED [3:2],\converge_cnt_reg[21]_i_1__2_n_0 ,\converge_cnt_reg[20]_i_1__2_n_0 }),
        .S({\NLW_converge_cnt_reg[21]_i_2__2_CARRY4_S_UNCONNECTED [3:2],converge_cnt_reg[21:20]}));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[2]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[2]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[3]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[3]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[4]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[4]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[5]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[5]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[5]_i_2__2_CARRY4 
       (.CI(\converge_cnt_reg[4]_i_2__2_n_0 ),
        .CO({\converge_cnt_reg[8]_i_2__2_n_0 ,\converge_cnt_reg[7]_i_2__2_n_0 ,\converge_cnt_reg[6]_i_2__2_n_0 ,\converge_cnt_reg[5]_i_2__2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[7]_i_1__2_n_0 ,\converge_cnt_reg[6]_i_1__2_n_0 ,\converge_cnt_reg[5]_i_1__2_n_0 ,\converge_cnt_reg[4]_i_1__2_n_0 }),
        .S(converge_cnt_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[6]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[6]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[7]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[7]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[8]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[8]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[9]_i_1__2_n_0 ),
        .Q(converge_cnt_reg[9]),
        .R(\converge_cnt[0]_i_1__2_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[9]_i_2__2_CARRY4 
       (.CI(\converge_cnt_reg[8]_i_2__2_n_0 ),
        .CO({\converge_cnt_reg[12]_i_2__2_n_0 ,\converge_cnt_reg[11]_i_2__2_n_0 ,\converge_cnt_reg[10]_i_2__2_n_0 ,\converge_cnt_reg[9]_i_2__2_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[11]_i_1__2_n_0 ,\converge_cnt_reg[10]_i_1__2_n_0 ,\converge_cnt_reg[9]_i_1__2_n_0 ,\converge_cnt_reg[8]_i_1__2_n_0 }),
        .S(converge_cnt_reg[11:8]));
  LUT4 #(
    .INIT(16'h0C08)) 
    converge_gen3_i_1__2
       (.I0(rxeq_adapt_done_reg2),
        .I1(rate_gen3_reg2),
        .I2(RST_CPLLRESET),
        .I3(converge_gen3_reg_n_0),
        .O(converge_gen3_i_1__2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    converge_gen3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_gen3_i_1__2_n_0),
        .Q(converge_gen3_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFE0FF)) 
    gt_rx_phy_status_q_i_1__2
       (.I0(rate_idle_reg2),
        .I1(rate_rxsync_reg2),
        .I2(RST_PHYSTATUS),
        .I3(rst_idle_reg2),
        .I4(rate_done_reg2),
        .O(gt_rx_phy_status_wire_filter));
  LUT6 #(
    .INIT(64'h4500000000000000)) 
    gt_rxvalid_q_i_4__2
       (.I0(gt_rxvalid_q_i_6__2_n_0),
        .I1(gt_rxvalid_q_reg_0),
        .I2(gt_rx_elec_idle_wire_filter),
        .I3(rst_idle_reg2),
        .I4(rate_idle_reg2),
        .I5(\resetovrd_disble.reset_reg[4]_0 ),
        .O(gt_rxvalid_q_reg));
  LUT4 #(
    .INIT(16'h7FFF)) 
    gt_rxvalid_q_i_6__2
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[1]),
        .O(gt_rxvalid_q_i_6__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_5__2 
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(\cplllock_reg1_reg[3] ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \gtx_channel.gtxe2_channel_i_i_65 
       (.I0(converge_gen3_reg_n_0),
        .I1(\gtx_channel.gtxe2_channel_i_i_76_n_0 ),
        .I2(converge_cnt_reg[8]),
        .I3(converge_cnt_reg[9]),
        .I4(\converge_cnt[0]_i_9__2_n_0 ),
        .I5(\converge_cnt[0]_i_5__2_n_0 ),
        .O(user_rx_converge));
  LUT5 #(
    .INIT(32'h00000010)) 
    \gtx_channel.gtxe2_channel_i_i_76 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(\gtx_channel.gtxe2_channel_i_i_84_n_0 ),
        .I3(converge_cnt_reg[2]),
        .I4(converge_cnt_reg[6]),
        .O(\gtx_channel.gtxe2_channel_i_i_76_n_0 ));
  LUT6 #(
    .INIT(64'h0004000000000000)) 
    \gtx_channel.gtxe2_channel_i_i_84 
       (.I0(converge_cnt_reg[20]),
        .I1(converge_cnt_reg[3]),
        .I2(converge_cnt_reg[0]),
        .I3(converge_cnt_reg[1]),
        .I4(converge_cnt_reg[10]),
        .I5(converge_cnt_reg[21]),
        .O(\gtx_channel.gtxe2_channel_i_i_84_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oobclk_div.oobclk_cnt[0]_i_1__2 
       (.I0(oobclk_cnt[0]),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \oobclk_div.oobclk_cnt[1]_i_1__2 
       (.I0(oobclk_cnt[0]),
        .I1(oobclk_cnt[1]),
        .O(p_1_in__0[1]));
  FDRE \oobclk_div.oobclk_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[0]),
        .Q(oobclk_cnt[0]),
        .R(RST_CPLLRESET));
  FDRE \oobclk_div.oobclk_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[1]),
        .Q(oobclk_cnt[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hB8)) 
    \oobclk_div.oobclk_i_1__2 
       (.I0(oobclk_cnt[1]),
        .I1(pclk_sel_reg2),
        .I2(oobclk_cnt[0]),
        .O(\oobclk_div.oobclk_i_1__2_n_0 ));
  FDRE \oobclk_div.oobclk_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\oobclk_div.oobclk_i_1__2_n_0 ),
        .Q(USER_OOBCLK),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(CLK_PCLK_SEL),
        .Q(pclk_sel_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pclk_sel_reg1),
        .Q(pclk_sel_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_DONE),
        .Q(rate_done_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_done_reg1),
        .Q(rate_done_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(rate_gen3_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3_reg1),
        .Q(rate_gen3_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_RXSYNC),
        .Q(rate_rxsync_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_rxsync_reg1),
        .Q(rate_rxsync_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT2 #(
    .INIT(4'h8)) 
    \resetdone_reg1[3]_i_1 
       (.I0(txresetdone_reg2),
        .I1(rxresetdone_reg2),
        .O(RST_RESETDONE));
  FDRE \resetovrd_disble.fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT2 #(
    .INIT(4'h1)) 
    resetovrd_done_reg1_i_1__2
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(resetovrd_done_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RESETOVRD_START),
        .Q(resetovrd_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetovrd_start_reg1),
        .Q(resetovrd_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(out1),
        .Q(rst_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT5 #(
    .INIT(32'h8A0A0A0A)) 
    \rxcdrlock_cnt[0]_i_1__2 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[2]),
        .I2(rxcdrlock_cnt_reg__0[0]),
        .I3(rxcdrlock_cnt_reg__0[1]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[0]));
  LUT5 #(
    .INIT(32'hA8282828)) 
    \rxcdrlock_cnt[1]_i_1__2 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[0]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[2]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[1]));
  LUT5 #(
    .INIT(32'h8CCCC000)) 
    \rxcdrlock_cnt[2]_i_1__2 
       (.I0(rxcdrlock_cnt_reg__0[3]),
        .I1(rxcdrlock_reg2),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \rxcdrlock_cnt[3]_i_1__2 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(rxcdrlock_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(rxcdrlock_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(rxcdrlock_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(rxcdrlock_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h80000000)) 
    \rxcdrlock_reg1[3]_i_1 
       (.I0(\resetovrd_disble.reset_reg[4]_1 ),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(RST_RXCDRLOCK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXEQ_ADAPT_DONE),
        .Q(rxeq_adapt_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_adapt_done_reg1),
        .Q(rxeq_adapt_done_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pipe_rxstatus),
        .Q(rxstatus_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxstatus_reg1),
        .Q(rxstatus_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT6 #(
    .INIT(64'h8080000000FF0000)) 
    \rxvalid_cnt[0]_i_1__2 
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[1]),
        .I3(rxstatus_reg2),
        .I4(rxvalid_reg2),
        .I5(rxvalid_cnt_reg__0[0]),
        .O(p_0_in__0__0[0]));
  LUT6 #(
    .INIT(64'h80000000E6660000)) 
    \rxvalid_cnt[1]_i_1__2 
       (.I0(rxvalid_cnt_reg__0[0]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[1]));
  LUT6 #(
    .INIT(64'h80000000EA6A0000)) 
    \rxvalid_cnt[2]_i_1__2 
       (.I0(rxvalid_cnt_reg__0[2]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'hD444444400000000)) 
    \rxvalid_cnt[3]_i_1__2 
       (.I0(rxstatus_reg2),
        .I1(rxvalid_cnt_reg__0[3]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[0]),
        .I4(rxvalid_cnt_reg__0[1]),
        .I5(rxvalid_reg2),
        .O(p_0_in__0__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(rxvalid_cnt_reg__0[0]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(rxvalid_cnt_reg__0[1]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(rxvalid_cnt_reg__0[2]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(rxvalid_cnt_reg__0[3]),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxvalid_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxvalid_reg1),
        .Q(rxvalid_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXCOMPLIANCE),
        .Q(txcompliance_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcompliance_reg1),
        .Q(txcompliance_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXELECIDLE),
        .Q(txelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg1),
        .Q(txelecidle_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hBBABBBABAAAABBAB)) 
    txphaligndone_reg1_i_5
       (.I0(user_active_lane),
        .I1(txcompliance_reg2_reg_0),
        .I2(txelecidle_reg2_reg_0[0]),
        .I3(pipe_txphaligndone[0]),
        .I4(txelecidle_reg2_reg_0[1]),
        .I5(pipe_txphaligndone[1]),
        .O(txphaligndone_reg1_reg));
  LUT2 #(
    .INIT(4'h7)) 
    txphaligndone_reg1_i_7
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .O(user_active_lane));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_user" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_53
   (txphinitdone_reg1_reg,
    p_0_in7_in,
    p_1_in8_in,
    txphaligndone_reg1_reg,
    gt_rxvalid_q_reg,
    p_2_in,
    USER_OOBCLK,
    Q,
    RST_RXCDRLOCK,
    gt_rx_phy_status_wire_filter,
    p_216_out,
    \cplllock_reg1_reg[4] ,
    resetovrd_done_reg1_reg,
    RST_RESETDONE,
    txelecidle_reg2_reg_0,
    txelecidle_reg2_reg_1,
    pipe_txphinitdone,
    user_active_lane,
    txcompliance_reg2_reg_0,
    pipe_txphaligndone,
    p_1_in8_in_0,
    p_0_in7_in_1,
    gt_rxvalid_q_reg_0,
    gt_rx_elec_idle_wire_filter,
    \resetovrd_disble.reset_reg[4]_0 ,
    RST_CPLLRESET,
    pclk_sel_reg,
    CLK_PCLK_SEL,
    USER_RXRESETDONE,
    USER_TXRESETDONE,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    \resetovrd_disble.reset_reg[4]_1 ,
    RST_RXUSRCLK_RESET,
    pipe_rxstatus,
    out1,
    RST_RATE_IDLE,
    USER_RATE_RXSYNC,
    USER_RATE_DONE,
    rate_gen3,
    USER_RXEQ_ADAPT_DONE,
    USER_RESETOVRD_START,
    RST_PHYSTATUS);
  output txphinitdone_reg1_reg;
  output p_0_in7_in;
  output p_1_in8_in;
  output txphaligndone_reg1_reg;
  output gt_rxvalid_q_reg;
  output p_2_in;
  output USER_OOBCLK;
  output [6:0]Q;
  output [0:0]RST_RXCDRLOCK;
  output [0:0]gt_rx_phy_status_wire_filter;
  output p_216_out;
  output \cplllock_reg1_reg[4] ;
  output resetovrd_done_reg1_reg;
  output [0:0]RST_RESETDONE;
  input txelecidle_reg2_reg_0;
  input txelecidle_reg2_reg_1;
  input [2:0]pipe_txphinitdone;
  input [0:0]user_active_lane;
  input txcompliance_reg2_reg_0;
  input [1:0]pipe_txphaligndone;
  input p_1_in8_in_0;
  input p_0_in7_in_1;
  input gt_rxvalid_q_reg_0;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]CLK_PCLK_SEL;
  input USER_RXRESETDONE;
  input USER_TXRESETDONE;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [0:0]PIPE_TXELECIDLE;
  input \resetovrd_disble.reset_reg[4]_1 ;
  input RST_RXUSRCLK_RESET;
  input [0:0]pipe_rxstatus;
  input [0:0]out1;
  input [0:0]RST_RATE_IDLE;
  input USER_RATE_RXSYNC;
  input USER_RATE_DONE;
  input [0:0]rate_gen3;
  input USER_RXEQ_ADAPT_DONE;
  input USER_RESETOVRD_START;
  input [0:0]RST_PHYSTATUS;

  wire [0:0]CLK_PCLK_SEL;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [0:0]PIPE_TXELECIDLE;
  wire [6:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_PHYSTATUS;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_RESETDONE;
  wire [0:0]RST_RXCDRLOCK;
  wire RST_RXUSRCLK_RESET;
  wire USER_OOBCLK;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXEQ_ADAPT_DONE;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire \converge_cnt[0]_i_1__3_n_0 ;
  wire \converge_cnt[0]_i_4__3_n_0 ;
  wire \converge_cnt[0]_i_5__3_n_0 ;
  wire \converge_cnt[0]_i_6__3_n_0 ;
  wire \converge_cnt[0]_i_7__3_n_0 ;
  wire \converge_cnt[0]_i_8__3_n_0 ;
  wire [21:0]converge_cnt_reg;
  wire \converge_cnt_reg[0]_i_3__3_n_0 ;
  wire \converge_cnt_reg[10]_i_1__3_n_0 ;
  wire \converge_cnt_reg[10]_i_2__3_n_0 ;
  wire \converge_cnt_reg[11]_i_1__3_n_0 ;
  wire \converge_cnt_reg[11]_i_2__3_n_0 ;
  wire \converge_cnt_reg[12]_i_1__3_n_0 ;
  wire \converge_cnt_reg[12]_i_2__3_n_0 ;
  wire \converge_cnt_reg[13]_i_1__3_n_0 ;
  wire \converge_cnt_reg[13]_i_2__3_n_0 ;
  wire \converge_cnt_reg[14]_i_1__3_n_0 ;
  wire \converge_cnt_reg[14]_i_2__3_n_0 ;
  wire \converge_cnt_reg[15]_i_1__3_n_0 ;
  wire \converge_cnt_reg[15]_i_2__3_n_0 ;
  wire \converge_cnt_reg[16]_i_1__3_n_0 ;
  wire \converge_cnt_reg[16]_i_2__3_n_0 ;
  wire \converge_cnt_reg[17]_i_1__3_n_0 ;
  wire \converge_cnt_reg[17]_i_2__3_n_0 ;
  wire \converge_cnt_reg[18]_i_1__3_n_0 ;
  wire \converge_cnt_reg[18]_i_2__3_n_0 ;
  wire \converge_cnt_reg[19]_i_1__3_n_0 ;
  wire \converge_cnt_reg[19]_i_2__3_n_0 ;
  wire \converge_cnt_reg[1]_i_1__3_n_0 ;
  wire \converge_cnt_reg[1]_i_2__3_n_0 ;
  wire \converge_cnt_reg[20]_i_1__3_n_0 ;
  wire \converge_cnt_reg[20]_i_2__3_n_0 ;
  wire \converge_cnt_reg[21]_i_1__3_n_0 ;
  wire \converge_cnt_reg[2]_i_1__3_n_0 ;
  wire \converge_cnt_reg[2]_i_2__3_n_0 ;
  wire \converge_cnt_reg[3]_i_1__3_n_0 ;
  wire \converge_cnt_reg[3]_i_2__3_n_0 ;
  wire \converge_cnt_reg[4]_i_1__3_n_0 ;
  wire \converge_cnt_reg[4]_i_2__3_n_0 ;
  wire \converge_cnt_reg[5]_i_1__3_n_0 ;
  wire \converge_cnt_reg[5]_i_2__3_n_0 ;
  wire \converge_cnt_reg[6]_i_1__3_n_0 ;
  wire \converge_cnt_reg[6]_i_2__3_n_0 ;
  wire \converge_cnt_reg[7]_i_1__3_n_0 ;
  wire \converge_cnt_reg[7]_i_2__3_n_0 ;
  wire \converge_cnt_reg[8]_i_1__3_n_0 ;
  wire \converge_cnt_reg[8]_i_2__3_n_0 ;
  wire \converge_cnt_reg[9]_i_1__3_n_0 ;
  wire \converge_cnt_reg[9]_i_2__3_n_0 ;
  wire converge_gen3_i_1__3_n_0;
  wire converge_gen3_reg_n_0;
  wire \cplllock_reg1_reg[4] ;
  wire [1:0]fsm;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire gt_rxvalid_q_i_6__3_n_0;
  wire gt_rxvalid_q_reg;
  wire gt_rxvalid_q_reg_0;
  wire \gtx_channel.gtxe2_channel_i_i_67_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_68_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_78_n_0 ;
  wire [1:0]oobclk_cnt;
  wire \oobclk_div.oobclk_i_1__3_n_0 ;
  wire [0:0]out1;
  wire p_0_in7_in_1;
  wire [3:0]p_0_in__0;
  wire [3:0]p_0_in__0__0;
  wire p_1_in8_in_0;
  wire [1:0]p_1_in__0;
  wire p_216_out;
  wire pclk_sel_reg;
  wire pclk_sel_reg1;
  wire pclk_sel_reg2;
  wire [0:0]pipe_rxstatus;
  wire [1:0]pipe_txphaligndone;
  wire [2:0]pipe_txphinitdone;
  wire rate_done_reg1;
  wire rate_done_reg2;
  wire [0:0]rate_gen3;
  wire rate_gen3_reg1;
  wire rate_gen3_reg2;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire rate_rxsync_reg1;
  wire rate_rxsync_reg2;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire resetovrd_done_reg1_reg;
  wire resetovrd_start_reg1;
  wire resetovrd_start_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire [3:0]rxcdrlock_cnt_reg__0;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxeq_adapt_done_reg1;
  wire rxeq_adapt_done_reg2;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxstatus_reg1;
  wire rxstatus_reg2;
  wire [3:0]rxvalid_cnt_reg__0;
  wire rxvalid_reg1;
  wire rxvalid_reg2;
  wire sel;
  wire txcompliance_reg1;
  wire txcompliance_reg2;
  wire txcompliance_reg2_reg_0;
  wire txelecidle_reg1;
  wire txelecidle_reg2;
  wire txelecidle_reg2_reg_0;
  wire txelecidle_reg2_reg_1;
  wire txphaligndone_reg1_reg;
  wire txphinitdone_reg1_i_3_n_0;
  wire txphinitdone_reg1_i_5_n_0;
  wire txphinitdone_reg1_reg;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire [0:0]user_active_lane;
  wire [3:0]\NLW_converge_cnt_reg[21]_i_2__3_CARRY4_CO_UNCONNECTED ;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__3_CARRY4_DI_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__3_CARRY4_O_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__3_CARRY4_S_UNCONNECTED ;

  assign p_0_in7_in = txcompliance_reg2;
  assign p_1_in8_in = txelecidle_reg2;
  assign p_2_in = rst_idle_reg2;
  LUT4 #(
    .INIT(16'hFFF7)) 
    \converge_cnt[0]_i_1__3 
       (.I0(rate_idle_reg2),
        .I1(rst_idle_reg2),
        .I2(RST_CPLLRESET),
        .I3(rate_gen3_reg2),
        .O(\converge_cnt[0]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h5D5D555D)) 
    \converge_cnt[0]_i_2__3 
       (.I0(converge_cnt_reg[21]),
        .I1(\converge_cnt[0]_i_4__3_n_0 ),
        .I2(converge_cnt_reg[20]),
        .I3(\converge_cnt[0]_i_5__3_n_0 ),
        .I4(\converge_cnt[0]_i_6__3_n_0 ),
        .O(sel));
  LUT6 #(
    .INIT(64'h13FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_4__3 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(converge_cnt_reg[13]),
        .I3(converge_cnt_reg[16]),
        .I4(converge_cnt_reg[15]),
        .I5(\converge_cnt[0]_i_8__3_n_0 ),
        .O(\converge_cnt[0]_i_4__3_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \converge_cnt[0]_i_5__3 
       (.I0(\converge_cnt[0]_i_8__3_n_0 ),
        .I1(converge_cnt_reg[16]),
        .I2(converge_cnt_reg[15]),
        .I3(converge_cnt_reg[13]),
        .I4(converge_cnt_reg[11]),
        .O(\converge_cnt[0]_i_5__3_n_0 ));
  LUT6 #(
    .INIT(64'h10FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_6__3 
       (.I0(converge_cnt_reg[3]),
        .I1(converge_cnt_reg[6]),
        .I2(\gtx_channel.gtxe2_channel_i_i_68_n_0 ),
        .I3(converge_cnt_reg[10]),
        .I4(converge_cnt_reg[8]),
        .I5(converge_cnt_reg[9]),
        .O(\converge_cnt[0]_i_6__3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[0]_i_7__3 
       (.I0(converge_cnt_reg[0]),
        .O(\converge_cnt[0]_i_7__3_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \converge_cnt[0]_i_8__3 
       (.I0(converge_cnt_reg[17]),
        .I1(converge_cnt_reg[18]),
        .I2(converge_cnt_reg[19]),
        .O(\converge_cnt[0]_i_8__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[0]_i_3__3_n_0 ),
        .Q(converge_cnt_reg[0]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[10]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[10]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[11]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[11]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[12]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[12]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[13]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[13]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[13]_i_2__3_CARRY4 
       (.CI(\converge_cnt_reg[12]_i_2__3_n_0 ),
        .CO({\converge_cnt_reg[16]_i_2__3_n_0 ,\converge_cnt_reg[15]_i_2__3_n_0 ,\converge_cnt_reg[14]_i_2__3_n_0 ,\converge_cnt_reg[13]_i_2__3_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[15]_i_1__3_n_0 ,\converge_cnt_reg[14]_i_1__3_n_0 ,\converge_cnt_reg[13]_i_1__3_n_0 ,\converge_cnt_reg[12]_i_1__3_n_0 }),
        .S(converge_cnt_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[14]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[14]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[15]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[15]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[16]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[16]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[17]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[17]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[17]_i_2__3_CARRY4 
       (.CI(\converge_cnt_reg[16]_i_2__3_n_0 ),
        .CO({\converge_cnt_reg[20]_i_2__3_n_0 ,\converge_cnt_reg[19]_i_2__3_n_0 ,\converge_cnt_reg[18]_i_2__3_n_0 ,\converge_cnt_reg[17]_i_2__3_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[19]_i_1__3_n_0 ,\converge_cnt_reg[18]_i_1__3_n_0 ,\converge_cnt_reg[17]_i_1__3_n_0 ,\converge_cnt_reg[16]_i_1__3_n_0 }),
        .S(converge_cnt_reg[19:16]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[18]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[18]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[19]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[19]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[1]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[1]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[1]_i_2__3_CARRY4 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[4]_i_2__3_n_0 ,\converge_cnt_reg[3]_i_2__3_n_0 ,\converge_cnt_reg[2]_i_2__3_n_0 ,\converge_cnt_reg[1]_i_2__3_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\converge_cnt_reg[3]_i_1__3_n_0 ,\converge_cnt_reg[2]_i_1__3_n_0 ,\converge_cnt_reg[1]_i_1__3_n_0 ,\converge_cnt_reg[0]_i_3__3_n_0 }),
        .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_7__3_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[20]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[20]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[21]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[21]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[21]_i_2__3_CARRY4 
       (.CI(\converge_cnt_reg[20]_i_2__3_n_0 ),
        .CO(\NLW_converge_cnt_reg[21]_i_2__3_CARRY4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({\NLW_converge_cnt_reg[21]_i_2__3_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__3_CARRY4_O_UNCONNECTED [3:2],\converge_cnt_reg[21]_i_1__3_n_0 ,\converge_cnt_reg[20]_i_1__3_n_0 }),
        .S({\NLW_converge_cnt_reg[21]_i_2__3_CARRY4_S_UNCONNECTED [3:2],converge_cnt_reg[21:20]}));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[2]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[2]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[3]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[3]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[4]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[4]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[5]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[5]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[5]_i_2__3_CARRY4 
       (.CI(\converge_cnt_reg[4]_i_2__3_n_0 ),
        .CO({\converge_cnt_reg[8]_i_2__3_n_0 ,\converge_cnt_reg[7]_i_2__3_n_0 ,\converge_cnt_reg[6]_i_2__3_n_0 ,\converge_cnt_reg[5]_i_2__3_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[7]_i_1__3_n_0 ,\converge_cnt_reg[6]_i_1__3_n_0 ,\converge_cnt_reg[5]_i_1__3_n_0 ,\converge_cnt_reg[4]_i_1__3_n_0 }),
        .S(converge_cnt_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[6]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[6]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[7]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[7]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[8]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[8]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[9]_i_1__3_n_0 ),
        .Q(converge_cnt_reg[9]),
        .R(\converge_cnt[0]_i_1__3_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[9]_i_2__3_CARRY4 
       (.CI(\converge_cnt_reg[8]_i_2__3_n_0 ),
        .CO({\converge_cnt_reg[12]_i_2__3_n_0 ,\converge_cnt_reg[11]_i_2__3_n_0 ,\converge_cnt_reg[10]_i_2__3_n_0 ,\converge_cnt_reg[9]_i_2__3_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[11]_i_1__3_n_0 ,\converge_cnt_reg[10]_i_1__3_n_0 ,\converge_cnt_reg[9]_i_1__3_n_0 ,\converge_cnt_reg[8]_i_1__3_n_0 }),
        .S(converge_cnt_reg[11:8]));
  LUT4 #(
    .INIT(16'h0C08)) 
    converge_gen3_i_1__3
       (.I0(rxeq_adapt_done_reg2),
        .I1(rate_gen3_reg2),
        .I2(RST_CPLLRESET),
        .I3(converge_gen3_reg_n_0),
        .O(converge_gen3_i_1__3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    converge_gen3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_gen3_i_1__3_n_0),
        .Q(converge_gen3_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFE0FF)) 
    gt_rx_phy_status_q_i_1__3
       (.I0(rate_idle_reg2),
        .I1(rate_rxsync_reg2),
        .I2(RST_PHYSTATUS),
        .I3(rst_idle_reg2),
        .I4(rate_done_reg2),
        .O(gt_rx_phy_status_wire_filter));
  LUT6 #(
    .INIT(64'h4500000000000000)) 
    gt_rxvalid_q_i_4__3
       (.I0(gt_rxvalid_q_i_6__3_n_0),
        .I1(gt_rxvalid_q_reg_0),
        .I2(gt_rx_elec_idle_wire_filter),
        .I3(rst_idle_reg2),
        .I4(rate_idle_reg2),
        .I5(\resetovrd_disble.reset_reg[4]_0 ),
        .O(gt_rxvalid_q_reg));
  LUT4 #(
    .INIT(16'h7FFF)) 
    gt_rxvalid_q_i_6__3
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[1]),
        .O(gt_rxvalid_q_i_6__3_n_0));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \gtx_channel.gtxe2_channel_i_i_58 
       (.I0(converge_gen3_reg_n_0),
        .I1(\gtx_channel.gtxe2_channel_i_i_67_n_0 ),
        .I2(converge_cnt_reg[8]),
        .I3(converge_cnt_reg[9]),
        .I4(\gtx_channel.gtxe2_channel_i_i_68_n_0 ),
        .I5(\converge_cnt[0]_i_5__3_n_0 ),
        .O(p_216_out));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_5__3 
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(\cplllock_reg1_reg[4] ));
  LUT5 #(
    .INIT(32'h00000010)) 
    \gtx_channel.gtxe2_channel_i_i_67 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(\gtx_channel.gtxe2_channel_i_i_78_n_0 ),
        .I3(converge_cnt_reg[2]),
        .I4(converge_cnt_reg[6]),
        .O(\gtx_channel.gtxe2_channel_i_i_67_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \gtx_channel.gtxe2_channel_i_i_68 
       (.I0(converge_cnt_reg[4]),
        .I1(converge_cnt_reg[5]),
        .I2(converge_cnt_reg[7]),
        .O(\gtx_channel.gtxe2_channel_i_i_68_n_0 ));
  LUT6 #(
    .INIT(64'h0004000000000000)) 
    \gtx_channel.gtxe2_channel_i_i_78 
       (.I0(converge_cnt_reg[20]),
        .I1(converge_cnt_reg[3]),
        .I2(converge_cnt_reg[0]),
        .I3(converge_cnt_reg[1]),
        .I4(converge_cnt_reg[10]),
        .I5(converge_cnt_reg[21]),
        .O(\gtx_channel.gtxe2_channel_i_i_78_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oobclk_div.oobclk_cnt[0]_i_1__3 
       (.I0(oobclk_cnt[0]),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \oobclk_div.oobclk_cnt[1]_i_1__3 
       (.I0(oobclk_cnt[0]),
        .I1(oobclk_cnt[1]),
        .O(p_1_in__0[1]));
  FDRE \oobclk_div.oobclk_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[0]),
        .Q(oobclk_cnt[0]),
        .R(RST_CPLLRESET));
  FDRE \oobclk_div.oobclk_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[1]),
        .Q(oobclk_cnt[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hB8)) 
    \oobclk_div.oobclk_i_1__3 
       (.I0(oobclk_cnt[1]),
        .I1(pclk_sel_reg2),
        .I2(oobclk_cnt[0]),
        .O(\oobclk_div.oobclk_i_1__3_n_0 ));
  FDRE \oobclk_div.oobclk_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\oobclk_div.oobclk_i_1__3_n_0 ),
        .Q(USER_OOBCLK),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(CLK_PCLK_SEL),
        .Q(pclk_sel_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pclk_sel_reg1),
        .Q(pclk_sel_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_DONE),
        .Q(rate_done_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_done_reg1),
        .Q(rate_done_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(rate_gen3_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3_reg1),
        .Q(rate_gen3_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_RXSYNC),
        .Q(rate_rxsync_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_rxsync_reg1),
        .Q(rate_rxsync_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT2 #(
    .INIT(4'h8)) 
    \resetdone_reg1[4]_i_1 
       (.I0(txresetdone_reg2),
        .I1(rxresetdone_reg2),
        .O(RST_RESETDONE));
  FDRE \resetovrd_disble.fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT2 #(
    .INIT(4'h1)) 
    resetovrd_done_reg1_i_1__3
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(resetovrd_done_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RESETOVRD_START),
        .Q(resetovrd_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetovrd_start_reg1),
        .Q(resetovrd_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(out1),
        .Q(rst_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT5 #(
    .INIT(32'h8A0A0A0A)) 
    \rxcdrlock_cnt[0]_i_1__3 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[2]),
        .I2(rxcdrlock_cnt_reg__0[0]),
        .I3(rxcdrlock_cnt_reg__0[1]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[0]));
  LUT5 #(
    .INIT(32'hA8282828)) 
    \rxcdrlock_cnt[1]_i_1__3 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[0]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[2]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[1]));
  LUT5 #(
    .INIT(32'h8CCCC000)) 
    \rxcdrlock_cnt[2]_i_1__3 
       (.I0(rxcdrlock_cnt_reg__0[3]),
        .I1(rxcdrlock_reg2),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \rxcdrlock_cnt[3]_i_1__3 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(rxcdrlock_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(rxcdrlock_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(rxcdrlock_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(rxcdrlock_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h80000000)) 
    \rxcdrlock_reg1[4]_i_1 
       (.I0(\resetovrd_disble.reset_reg[4]_1 ),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(RST_RXCDRLOCK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXEQ_ADAPT_DONE),
        .Q(rxeq_adapt_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_adapt_done_reg1),
        .Q(rxeq_adapt_done_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pipe_rxstatus),
        .Q(rxstatus_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxstatus_reg1),
        .Q(rxstatus_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT6 #(
    .INIT(64'h8080000000FF0000)) 
    \rxvalid_cnt[0]_i_1__3 
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[1]),
        .I3(rxstatus_reg2),
        .I4(rxvalid_reg2),
        .I5(rxvalid_cnt_reg__0[0]),
        .O(p_0_in__0__0[0]));
  LUT6 #(
    .INIT(64'h80000000E6660000)) 
    \rxvalid_cnt[1]_i_1__3 
       (.I0(rxvalid_cnt_reg__0[0]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[1]));
  LUT6 #(
    .INIT(64'h80000000EA6A0000)) 
    \rxvalid_cnt[2]_i_1__3 
       (.I0(rxvalid_cnt_reg__0[2]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'hD444444400000000)) 
    \rxvalid_cnt[3]_i_1__3 
       (.I0(rxstatus_reg2),
        .I1(rxvalid_cnt_reg__0[3]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[0]),
        .I4(rxvalid_cnt_reg__0[1]),
        .I5(rxvalid_reg2),
        .O(p_0_in__0__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(rxvalid_cnt_reg__0[0]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(rxvalid_cnt_reg__0[1]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(rxvalid_cnt_reg__0[2]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(rxvalid_cnt_reg__0[3]),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxvalid_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxvalid_reg1),
        .Q(rxvalid_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXCOMPLIANCE),
        .Q(txcompliance_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcompliance_reg1),
        .Q(txcompliance_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXELECIDLE),
        .Q(txelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg1),
        .Q(txelecidle_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'hF8F8F800F800F800)) 
    txphaligndone_reg1_i_4
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .I2(pipe_txphaligndone[0]),
        .I3(pipe_txphaligndone[1]),
        .I4(p_1_in8_in_0),
        .I5(p_0_in7_in_1),
        .O(txphaligndone_reg1_reg));
  LUT6 #(
    .INIT(64'h1110111000005550)) 
    txphinitdone_reg1_i_1
       (.I0(txelecidle_reg2_reg_0),
        .I1(txphinitdone_reg1_i_3_n_0),
        .I2(txelecidle_reg2_reg_1),
        .I3(pipe_txphinitdone[0]),
        .I4(txphinitdone_reg1_i_5_n_0),
        .I5(user_active_lane),
        .O(txphinitdone_reg1_reg));
  LUT5 #(
    .INIT(32'hFFFF557F)) 
    txphinitdone_reg1_i_3
       (.I0(pipe_txphinitdone[2]),
        .I1(txcompliance_reg2),
        .I2(txelecidle_reg2),
        .I3(pipe_txphinitdone[1]),
        .I4(txcompliance_reg2_reg_0),
        .O(txphinitdone_reg1_i_3_n_0));
  LUT4 #(
    .INIT(16'hFF15)) 
    txphinitdone_reg1_i_5
       (.I0(pipe_txphinitdone[1]),
        .I1(txelecidle_reg2),
        .I2(txcompliance_reg2),
        .I3(txcompliance_reg2_reg_0),
        .O(txphinitdone_reg1_i_5_n_0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_user" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_59
   (gt_rxvalid_q_reg,
    D,
    p_0_in7_in,
    p_1_in8_in,
    USER_OOBCLK,
    Q,
    RST_RXCDRLOCK,
    gt_rx_phy_status_wire_filter,
    p_159_out,
    \cplllock_reg1_reg[5] ,
    resetovrd_done_reg1_reg,
    RST_RESETDONE,
    user_active_lane,
    gt_rxvalid_q_reg_0,
    gt_rx_elec_idle_wire_filter,
    \resetovrd_disble.reset_reg[4]_0 ,
    p_2_in,
    rst_idle_reg2_reg_0,
    RST_CPLLRESET,
    pclk_sel_reg,
    CLK_PCLK_SEL,
    USER_RXRESETDONE,
    USER_TXRESETDONE,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    \resetovrd_disble.reset_reg[4]_1 ,
    RST_RXUSRCLK_RESET,
    pipe_rxstatus,
    out1,
    RST_RATE_IDLE,
    USER_RATE_RXSYNC,
    USER_RATE_DONE,
    rate_gen3,
    USER_RXEQ_ADAPT_DONE,
    USER_RESETOVRD_START,
    RST_PHYSTATUS);
  output gt_rxvalid_q_reg;
  output D;
  output p_0_in7_in;
  output p_1_in8_in;
  output USER_OOBCLK;
  output [6:0]Q;
  output [0:0]RST_RXCDRLOCK;
  output [0:0]gt_rx_phy_status_wire_filter;
  output p_159_out;
  output \cplllock_reg1_reg[5] ;
  output resetovrd_done_reg1_reg;
  output [0:0]RST_RESETDONE;
  output [0:0]user_active_lane;
  input gt_rxvalid_q_reg_0;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input p_2_in;
  input rst_idle_reg2_reg_0;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]CLK_PCLK_SEL;
  input USER_RXRESETDONE;
  input USER_TXRESETDONE;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [0:0]PIPE_TXELECIDLE;
  input \resetovrd_disble.reset_reg[4]_1 ;
  input RST_RXUSRCLK_RESET;
  input [0:0]pipe_rxstatus;
  input [0:0]out1;
  input [0:0]RST_RATE_IDLE;
  input USER_RATE_RXSYNC;
  input USER_RATE_DONE;
  input [0:0]rate_gen3;
  input USER_RXEQ_ADAPT_DONE;
  input USER_RESETOVRD_START;
  input [0:0]RST_PHYSTATUS;

  wire [0:0]CLK_PCLK_SEL;
  wire D;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [0:0]PIPE_TXELECIDLE;
  wire [6:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_PHYSTATUS;
  wire [0:0]RST_RATE_IDLE;
  wire [0:0]RST_RESETDONE;
  wire [0:0]RST_RXCDRLOCK;
  wire RST_RXUSRCLK_RESET;
  wire USER_OOBCLK;
  wire USER_RATE_DONE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXEQ_ADAPT_DONE;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire \converge_cnt[0]_i_1__4_n_0 ;
  wire \converge_cnt[0]_i_4__4_n_0 ;
  wire \converge_cnt[0]_i_5__4_n_0 ;
  wire \converge_cnt[0]_i_6__4_n_0 ;
  wire \converge_cnt[0]_i_7__4_n_0 ;
  wire \converge_cnt[0]_i_8__4_n_0 ;
  wire [21:0]converge_cnt_reg;
  wire \converge_cnt_reg[0]_i_3__4_n_0 ;
  wire \converge_cnt_reg[10]_i_1__4_n_0 ;
  wire \converge_cnt_reg[10]_i_2__4_n_0 ;
  wire \converge_cnt_reg[11]_i_1__4_n_0 ;
  wire \converge_cnt_reg[11]_i_2__4_n_0 ;
  wire \converge_cnt_reg[12]_i_1__4_n_0 ;
  wire \converge_cnt_reg[12]_i_2__4_n_0 ;
  wire \converge_cnt_reg[13]_i_1__4_n_0 ;
  wire \converge_cnt_reg[13]_i_2__4_n_0 ;
  wire \converge_cnt_reg[14]_i_1__4_n_0 ;
  wire \converge_cnt_reg[14]_i_2__4_n_0 ;
  wire \converge_cnt_reg[15]_i_1__4_n_0 ;
  wire \converge_cnt_reg[15]_i_2__4_n_0 ;
  wire \converge_cnt_reg[16]_i_1__4_n_0 ;
  wire \converge_cnt_reg[16]_i_2__4_n_0 ;
  wire \converge_cnt_reg[17]_i_1__4_n_0 ;
  wire \converge_cnt_reg[17]_i_2__4_n_0 ;
  wire \converge_cnt_reg[18]_i_1__4_n_0 ;
  wire \converge_cnt_reg[18]_i_2__4_n_0 ;
  wire \converge_cnt_reg[19]_i_1__4_n_0 ;
  wire \converge_cnt_reg[19]_i_2__4_n_0 ;
  wire \converge_cnt_reg[1]_i_1__4_n_0 ;
  wire \converge_cnt_reg[1]_i_2__4_n_0 ;
  wire \converge_cnt_reg[20]_i_1__4_n_0 ;
  wire \converge_cnt_reg[20]_i_2__4_n_0 ;
  wire \converge_cnt_reg[21]_i_1__4_n_0 ;
  wire \converge_cnt_reg[2]_i_1__4_n_0 ;
  wire \converge_cnt_reg[2]_i_2__4_n_0 ;
  wire \converge_cnt_reg[3]_i_1__4_n_0 ;
  wire \converge_cnt_reg[3]_i_2__4_n_0 ;
  wire \converge_cnt_reg[4]_i_1__4_n_0 ;
  wire \converge_cnt_reg[4]_i_2__4_n_0 ;
  wire \converge_cnt_reg[5]_i_1__4_n_0 ;
  wire \converge_cnt_reg[5]_i_2__4_n_0 ;
  wire \converge_cnt_reg[6]_i_1__4_n_0 ;
  wire \converge_cnt_reg[6]_i_2__4_n_0 ;
  wire \converge_cnt_reg[7]_i_1__4_n_0 ;
  wire \converge_cnt_reg[7]_i_2__4_n_0 ;
  wire \converge_cnt_reg[8]_i_1__4_n_0 ;
  wire \converge_cnt_reg[8]_i_2__4_n_0 ;
  wire \converge_cnt_reg[9]_i_1__4_n_0 ;
  wire \converge_cnt_reg[9]_i_2__4_n_0 ;
  wire converge_gen3_i_1__4_n_0;
  wire converge_gen3_reg_n_0;
  wire \cplllock_reg1_reg[5] ;
  wire [1:0]fsm;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire gt_rxvalid_q_i_6__4_n_0;
  wire gt_rxvalid_q_reg;
  wire gt_rxvalid_q_reg_0;
  wire \gtx_channel.gtxe2_channel_i_i_69_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_70_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_79_n_0 ;
  wire [1:0]oobclk_cnt;
  wire \oobclk_div.oobclk_i_1__4_n_0 ;
  wire [0:0]out1;
  wire [3:0]p_0_in__0;
  wire [3:0]p_0_in__0__0;
  wire p_159_out;
  wire [1:0]p_1_in__0;
  wire p_2_in;
  wire pclk_sel_reg;
  wire pclk_sel_reg1;
  wire pclk_sel_reg2;
  wire [0:0]pipe_rxstatus;
  wire rate_done_reg1;
  wire rate_done_reg2;
  wire [0:0]rate_gen3;
  wire rate_gen3_reg1;
  wire rate_gen3_reg2;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire rate_rxsync_reg1;
  wire rate_rxsync_reg2;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire resetovrd_done_reg1_reg;
  wire resetovrd_start_reg1;
  wire resetovrd_start_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire rst_idle_reg2_reg_0;
  wire [3:0]rxcdrlock_cnt_reg__0;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxeq_adapt_done_reg1;
  wire rxeq_adapt_done_reg2;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxstatus_reg1;
  wire rxstatus_reg2;
  wire [3:0]rxvalid_cnt_reg__0;
  wire rxvalid_reg1;
  wire rxvalid_reg2;
  wire sel;
  wire txcompliance_reg1;
  wire txcompliance_reg2;
  wire txelecidle_reg1;
  wire txelecidle_reg2;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire [0:0]user_active_lane;
  wire [3:0]\NLW_converge_cnt_reg[21]_i_2__4_CARRY4_CO_UNCONNECTED ;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__4_CARRY4_DI_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__4_CARRY4_O_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__4_CARRY4_S_UNCONNECTED ;

  assign p_0_in7_in = txcompliance_reg2;
  assign p_1_in8_in = txelecidle_reg2;
  LUT4 #(
    .INIT(16'hFFF7)) 
    \converge_cnt[0]_i_1__4 
       (.I0(rate_idle_reg2),
        .I1(rst_idle_reg2),
        .I2(RST_CPLLRESET),
        .I3(rate_gen3_reg2),
        .O(\converge_cnt[0]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h5D5D555D)) 
    \converge_cnt[0]_i_2__4 
       (.I0(converge_cnt_reg[21]),
        .I1(\converge_cnt[0]_i_4__4_n_0 ),
        .I2(converge_cnt_reg[20]),
        .I3(\converge_cnt[0]_i_5__4_n_0 ),
        .I4(\converge_cnt[0]_i_6__4_n_0 ),
        .O(sel));
  LUT6 #(
    .INIT(64'h13FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_4__4 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(converge_cnt_reg[13]),
        .I3(converge_cnt_reg[16]),
        .I4(converge_cnt_reg[15]),
        .I5(\converge_cnt[0]_i_8__4_n_0 ),
        .O(\converge_cnt[0]_i_4__4_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \converge_cnt[0]_i_5__4 
       (.I0(\converge_cnt[0]_i_8__4_n_0 ),
        .I1(converge_cnt_reg[16]),
        .I2(converge_cnt_reg[15]),
        .I3(converge_cnt_reg[13]),
        .I4(converge_cnt_reg[11]),
        .O(\converge_cnt[0]_i_5__4_n_0 ));
  LUT6 #(
    .INIT(64'h10FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_6__4 
       (.I0(converge_cnt_reg[3]),
        .I1(converge_cnt_reg[6]),
        .I2(\gtx_channel.gtxe2_channel_i_i_70_n_0 ),
        .I3(converge_cnt_reg[10]),
        .I4(converge_cnt_reg[8]),
        .I5(converge_cnt_reg[9]),
        .O(\converge_cnt[0]_i_6__4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[0]_i_7__4 
       (.I0(converge_cnt_reg[0]),
        .O(\converge_cnt[0]_i_7__4_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \converge_cnt[0]_i_8__4 
       (.I0(converge_cnt_reg[17]),
        .I1(converge_cnt_reg[18]),
        .I2(converge_cnt_reg[19]),
        .O(\converge_cnt[0]_i_8__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[0]_i_3__4_n_0 ),
        .Q(converge_cnt_reg[0]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[10]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[10]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[11]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[11]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[12]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[12]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[13]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[13]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[13]_i_2__4_CARRY4 
       (.CI(\converge_cnt_reg[12]_i_2__4_n_0 ),
        .CO({\converge_cnt_reg[16]_i_2__4_n_0 ,\converge_cnt_reg[15]_i_2__4_n_0 ,\converge_cnt_reg[14]_i_2__4_n_0 ,\converge_cnt_reg[13]_i_2__4_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[15]_i_1__4_n_0 ,\converge_cnt_reg[14]_i_1__4_n_0 ,\converge_cnt_reg[13]_i_1__4_n_0 ,\converge_cnt_reg[12]_i_1__4_n_0 }),
        .S(converge_cnt_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[14]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[14]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[15]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[15]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[16]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[16]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[17]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[17]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[17]_i_2__4_CARRY4 
       (.CI(\converge_cnt_reg[16]_i_2__4_n_0 ),
        .CO({\converge_cnt_reg[20]_i_2__4_n_0 ,\converge_cnt_reg[19]_i_2__4_n_0 ,\converge_cnt_reg[18]_i_2__4_n_0 ,\converge_cnt_reg[17]_i_2__4_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[19]_i_1__4_n_0 ,\converge_cnt_reg[18]_i_1__4_n_0 ,\converge_cnt_reg[17]_i_1__4_n_0 ,\converge_cnt_reg[16]_i_1__4_n_0 }),
        .S(converge_cnt_reg[19:16]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[18]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[18]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[19]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[19]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[1]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[1]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[1]_i_2__4_CARRY4 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[4]_i_2__4_n_0 ,\converge_cnt_reg[3]_i_2__4_n_0 ,\converge_cnt_reg[2]_i_2__4_n_0 ,\converge_cnt_reg[1]_i_2__4_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\converge_cnt_reg[3]_i_1__4_n_0 ,\converge_cnt_reg[2]_i_1__4_n_0 ,\converge_cnt_reg[1]_i_1__4_n_0 ,\converge_cnt_reg[0]_i_3__4_n_0 }),
        .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_7__4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[20]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[20]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[21]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[21]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[21]_i_2__4_CARRY4 
       (.CI(\converge_cnt_reg[20]_i_2__4_n_0 ),
        .CO(\NLW_converge_cnt_reg[21]_i_2__4_CARRY4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({\NLW_converge_cnt_reg[21]_i_2__4_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__4_CARRY4_O_UNCONNECTED [3:2],\converge_cnt_reg[21]_i_1__4_n_0 ,\converge_cnt_reg[20]_i_1__4_n_0 }),
        .S({\NLW_converge_cnt_reg[21]_i_2__4_CARRY4_S_UNCONNECTED [3:2],converge_cnt_reg[21:20]}));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[2]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[2]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[3]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[3]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[4]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[4]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[5]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[5]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[5]_i_2__4_CARRY4 
       (.CI(\converge_cnt_reg[4]_i_2__4_n_0 ),
        .CO({\converge_cnt_reg[8]_i_2__4_n_0 ,\converge_cnt_reg[7]_i_2__4_n_0 ,\converge_cnt_reg[6]_i_2__4_n_0 ,\converge_cnt_reg[5]_i_2__4_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[7]_i_1__4_n_0 ,\converge_cnt_reg[6]_i_1__4_n_0 ,\converge_cnt_reg[5]_i_1__4_n_0 ,\converge_cnt_reg[4]_i_1__4_n_0 }),
        .S(converge_cnt_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[6]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[6]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[7]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[7]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[8]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[8]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[9]_i_1__4_n_0 ),
        .Q(converge_cnt_reg[9]),
        .R(\converge_cnt[0]_i_1__4_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[9]_i_2__4_CARRY4 
       (.CI(\converge_cnt_reg[8]_i_2__4_n_0 ),
        .CO({\converge_cnt_reg[12]_i_2__4_n_0 ,\converge_cnt_reg[11]_i_2__4_n_0 ,\converge_cnt_reg[10]_i_2__4_n_0 ,\converge_cnt_reg[9]_i_2__4_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[11]_i_1__4_n_0 ,\converge_cnt_reg[10]_i_1__4_n_0 ,\converge_cnt_reg[9]_i_1__4_n_0 ,\converge_cnt_reg[8]_i_1__4_n_0 }),
        .S(converge_cnt_reg[11:8]));
  LUT4 #(
    .INIT(16'h0C08)) 
    converge_gen3_i_1__4
       (.I0(rxeq_adapt_done_reg2),
        .I1(rate_gen3_reg2),
        .I2(RST_CPLLRESET),
        .I3(converge_gen3_reg_n_0),
        .O(converge_gen3_i_1__4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    converge_gen3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_gen3_i_1__4_n_0),
        .Q(converge_gen3_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFE0FF)) 
    gt_rx_phy_status_q_i_1__4
       (.I0(rate_idle_reg2),
        .I1(rate_rxsync_reg2),
        .I2(RST_PHYSTATUS),
        .I3(rst_idle_reg2),
        .I4(rate_done_reg2),
        .O(gt_rx_phy_status_wire_filter));
  LUT6 #(
    .INIT(64'h4500000000000000)) 
    gt_rxvalid_q_i_4__4
       (.I0(gt_rxvalid_q_i_6__4_n_0),
        .I1(gt_rxvalid_q_reg_0),
        .I2(gt_rx_elec_idle_wire_filter),
        .I3(rst_idle_reg2),
        .I4(rate_idle_reg2),
        .I5(\resetovrd_disble.reset_reg[4]_0 ),
        .O(gt_rxvalid_q_reg));
  LUT4 #(
    .INIT(16'h7FFF)) 
    gt_rxvalid_q_i_6__4
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[1]),
        .O(gt_rxvalid_q_i_6__4_n_0));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \gtx_channel.gtxe2_channel_i_i_59 
       (.I0(converge_gen3_reg_n_0),
        .I1(\gtx_channel.gtxe2_channel_i_i_69_n_0 ),
        .I2(converge_cnt_reg[8]),
        .I3(converge_cnt_reg[9]),
        .I4(\gtx_channel.gtxe2_channel_i_i_70_n_0 ),
        .I5(\converge_cnt[0]_i_5__4_n_0 ),
        .O(p_159_out));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_5__4 
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(\cplllock_reg1_reg[5] ));
  LUT5 #(
    .INIT(32'h00000010)) 
    \gtx_channel.gtxe2_channel_i_i_69 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(\gtx_channel.gtxe2_channel_i_i_79_n_0 ),
        .I3(converge_cnt_reg[2]),
        .I4(converge_cnt_reg[6]),
        .O(\gtx_channel.gtxe2_channel_i_i_69_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \gtx_channel.gtxe2_channel_i_i_70 
       (.I0(converge_cnt_reg[4]),
        .I1(converge_cnt_reg[5]),
        .I2(converge_cnt_reg[7]),
        .O(\gtx_channel.gtxe2_channel_i_i_70_n_0 ));
  LUT6 #(
    .INIT(64'h0004000000000000)) 
    \gtx_channel.gtxe2_channel_i_i_79 
       (.I0(converge_cnt_reg[20]),
        .I1(converge_cnt_reg[3]),
        .I2(converge_cnt_reg[0]),
        .I3(converge_cnt_reg[1]),
        .I4(converge_cnt_reg[10]),
        .I5(converge_cnt_reg[21]),
        .O(\gtx_channel.gtxe2_channel_i_i_79_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oobclk_div.oobclk_cnt[0]_i_1__4 
       (.I0(oobclk_cnt[0]),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \oobclk_div.oobclk_cnt[1]_i_1__4 
       (.I0(oobclk_cnt[0]),
        .I1(oobclk_cnt[1]),
        .O(p_1_in__0[1]));
  FDRE \oobclk_div.oobclk_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[0]),
        .Q(oobclk_cnt[0]),
        .R(RST_CPLLRESET));
  FDRE \oobclk_div.oobclk_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[1]),
        .Q(oobclk_cnt[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hB8)) 
    \oobclk_div.oobclk_i_1__4 
       (.I0(oobclk_cnt[1]),
        .I1(pclk_sel_reg2),
        .I2(oobclk_cnt[0]),
        .O(\oobclk_div.oobclk_i_1__4_n_0 ));
  FDRE \oobclk_div.oobclk_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\oobclk_div.oobclk_i_1__4_n_0 ),
        .Q(USER_OOBCLK),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(CLK_PCLK_SEL),
        .Q(pclk_sel_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pclk_sel_reg1),
        .Q(pclk_sel_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h10)) 
    phy_rdy_n_int_i_1
       (.I0(rst_idle_reg2),
        .I1(p_2_in),
        .I2(rst_idle_reg2_reg_0),
        .O(D));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_DONE),
        .Q(rate_done_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_done_reg1),
        .Q(rate_done_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3),
        .Q(rate_gen3_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3_reg1),
        .Q(rate_gen3_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(RST_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_RXSYNC),
        .Q(rate_rxsync_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_rxsync_reg1),
        .Q(rate_rxsync_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT2 #(
    .INIT(4'h8)) 
    \resetdone_reg1[5]_i_1 
       (.I0(txresetdone_reg2),
        .I1(rxresetdone_reg2),
        .O(RST_RESETDONE));
  FDRE \resetovrd_disble.fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT2 #(
    .INIT(4'h1)) 
    resetovrd_done_reg1_i_1__4
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(resetovrd_done_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RESETOVRD_START),
        .Q(resetovrd_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetovrd_start_reg1),
        .Q(resetovrd_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(out1),
        .Q(rst_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT5 #(
    .INIT(32'h8A0A0A0A)) 
    \rxcdrlock_cnt[0]_i_1__4 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[2]),
        .I2(rxcdrlock_cnt_reg__0[0]),
        .I3(rxcdrlock_cnt_reg__0[1]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[0]));
  LUT5 #(
    .INIT(32'hA8282828)) 
    \rxcdrlock_cnt[1]_i_1__4 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[0]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[2]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[1]));
  LUT5 #(
    .INIT(32'h8CCCC000)) 
    \rxcdrlock_cnt[2]_i_1__4 
       (.I0(rxcdrlock_cnt_reg__0[3]),
        .I1(rxcdrlock_reg2),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \rxcdrlock_cnt[3]_i_1__4 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(rxcdrlock_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(rxcdrlock_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(rxcdrlock_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(rxcdrlock_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h80000000)) 
    \rxcdrlock_reg1[5]_i_1 
       (.I0(\resetovrd_disble.reset_reg[4]_1 ),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(RST_RXCDRLOCK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXEQ_ADAPT_DONE),
        .Q(rxeq_adapt_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_adapt_done_reg1),
        .Q(rxeq_adapt_done_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pipe_rxstatus),
        .Q(rxstatus_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxstatus_reg1),
        .Q(rxstatus_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT6 #(
    .INIT(64'h8080000000FF0000)) 
    \rxvalid_cnt[0]_i_1__4 
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[1]),
        .I3(rxstatus_reg2),
        .I4(rxvalid_reg2),
        .I5(rxvalid_cnt_reg__0[0]),
        .O(p_0_in__0__0[0]));
  LUT6 #(
    .INIT(64'h80000000E6660000)) 
    \rxvalid_cnt[1]_i_1__4 
       (.I0(rxvalid_cnt_reg__0[0]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[1]));
  LUT6 #(
    .INIT(64'h80000000EA6A0000)) 
    \rxvalid_cnt[2]_i_1__4 
       (.I0(rxvalid_cnt_reg__0[2]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'hD444444400000000)) 
    \rxvalid_cnt[3]_i_1__4 
       (.I0(rxstatus_reg2),
        .I1(rxvalid_cnt_reg__0[3]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[0]),
        .I4(rxvalid_cnt_reg__0[1]),
        .I5(rxvalid_reg2),
        .O(p_0_in__0__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(rxvalid_cnt_reg__0[0]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(rxvalid_cnt_reg__0[1]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(rxvalid_cnt_reg__0[2]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(rxvalid_cnt_reg__0[3]),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxvalid_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxvalid_reg1),
        .Q(rxvalid_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXCOMPLIANCE),
        .Q(txcompliance_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcompliance_reg1),
        .Q(txcompliance_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXELECIDLE),
        .Q(txelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg1),
        .Q(txelecidle_reg2),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h7)) 
    txphinitdone_reg1_i_6
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .O(user_active_lane));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_user" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_65
   (txsyncallin,
    gt_rxvalid_q_reg,
    p_2_in,
    GT_RX_CONVERGE0,
    \cplllock_reg1_reg[2] ,
    \cplllock_reg1_reg[3] ,
    \cplllock_reg1_reg[7] ,
    p_0_in7_in,
    p_1_in8_in,
    USER_OOBCLK,
    Q,
    RST_RXCDRLOCK,
    gt_rx_phy_status_wire_filter,
    \cplllock_reg1_reg[6] ,
    resetovrd_done_reg1_reg,
    RST_RESETDONE,
    txelecidle_reg2_reg_0,
    pipe_txphaligndone,
    txelecidle_reg2_reg_1,
    txelecidle_reg2_reg_2,
    txcompliance_reg2_reg_0,
    gt_rxvalid_q_reg_0,
    gt_rx_elec_idle_wire_filter,
    \resetovrd_disble.reset_reg[4]_0 ,
    p_216_out,
    p_159_out,
    user_rx_converge,
    RST_CPLLRESET,
    pclk_sel_reg,
    CLK_PCLK_SEL,
    USER_RXRESETDONE,
    USER_TXRESETDONE,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    \resetovrd_disble.reset_reg[4]_1 ,
    RST_RXUSRCLK_RESET,
    pipe_rxstatus,
    out1,
    USER_RATE_IDLE,
    USER_RATE_RXSYNC,
    USER_RATE_DONE,
    USER_RATE_GEN3,
    USER_RXEQ_ADAPT_DONE,
    USER_RESETOVRD_START,
    RST_PHYSTATUS);
  output txsyncallin;
  output gt_rxvalid_q_reg;
  output p_2_in;
  output GT_RX_CONVERGE0;
  output \cplllock_reg1_reg[2] ;
  output \cplllock_reg1_reg[3] ;
  output \cplllock_reg1_reg[7] ;
  output p_0_in7_in;
  output p_1_in8_in;
  output USER_OOBCLK;
  output [6:0]Q;
  output [0:0]RST_RXCDRLOCK;
  output [0:0]gt_rx_phy_status_wire_filter;
  output \cplllock_reg1_reg[6] ;
  output resetovrd_done_reg1_reg;
  output [0:0]RST_RESETDONE;
  input txelecidle_reg2_reg_0;
  input [0:0]pipe_txphaligndone;
  input txelecidle_reg2_reg_1;
  input txelecidle_reg2_reg_2;
  input txcompliance_reg2_reg_0;
  input gt_rxvalid_q_reg_0;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input p_216_out;
  input p_159_out;
  input [4:0]user_rx_converge;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]CLK_PCLK_SEL;
  input USER_RXRESETDONE;
  input USER_TXRESETDONE;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [0:0]PIPE_TXELECIDLE;
  input \resetovrd_disble.reset_reg[4]_1 ;
  input RST_RXUSRCLK_RESET;
  input [0:0]pipe_rxstatus;
  input [0:0]out1;
  input USER_RATE_IDLE;
  input USER_RATE_RXSYNC;
  input USER_RATE_DONE;
  input USER_RATE_GEN3;
  input USER_RXEQ_ADAPT_DONE;
  input USER_RESETOVRD_START;
  input [0:0]RST_PHYSTATUS;

  wire [0:0]CLK_PCLK_SEL;
  wire GT_RX_CONVERGE0;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [0:0]PIPE_TXELECIDLE;
  wire [6:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_PHYSTATUS;
  wire [0:0]RST_RESETDONE;
  wire [0:0]RST_RXCDRLOCK;
  wire RST_RXUSRCLK_RESET;
  wire USER_OOBCLK;
  wire USER_RATE_DONE;
  wire USER_RATE_GEN3;
  wire USER_RATE_IDLE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXEQ_ADAPT_DONE;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire \converge_cnt[0]_i_1__5_n_0 ;
  wire \converge_cnt[0]_i_4__5_n_0 ;
  wire \converge_cnt[0]_i_5__5_n_0 ;
  wire \converge_cnt[0]_i_6__5_n_0 ;
  wire \converge_cnt[0]_i_7__5_n_0 ;
  wire \converge_cnt[0]_i_8__5_n_0 ;
  wire \converge_cnt[0]_i_9__3_n_0 ;
  wire [21:0]converge_cnt_reg;
  wire \converge_cnt_reg[0]_i_3__5_n_0 ;
  wire \converge_cnt_reg[10]_i_1__5_n_0 ;
  wire \converge_cnt_reg[10]_i_2__5_n_0 ;
  wire \converge_cnt_reg[11]_i_1__5_n_0 ;
  wire \converge_cnt_reg[11]_i_2__5_n_0 ;
  wire \converge_cnt_reg[12]_i_1__5_n_0 ;
  wire \converge_cnt_reg[12]_i_2__5_n_0 ;
  wire \converge_cnt_reg[13]_i_1__5_n_0 ;
  wire \converge_cnt_reg[13]_i_2__5_n_0 ;
  wire \converge_cnt_reg[14]_i_1__5_n_0 ;
  wire \converge_cnt_reg[14]_i_2__5_n_0 ;
  wire \converge_cnt_reg[15]_i_1__5_n_0 ;
  wire \converge_cnt_reg[15]_i_2__5_n_0 ;
  wire \converge_cnt_reg[16]_i_1__5_n_0 ;
  wire \converge_cnt_reg[16]_i_2__5_n_0 ;
  wire \converge_cnt_reg[17]_i_1__5_n_0 ;
  wire \converge_cnt_reg[17]_i_2__5_n_0 ;
  wire \converge_cnt_reg[18]_i_1__5_n_0 ;
  wire \converge_cnt_reg[18]_i_2__5_n_0 ;
  wire \converge_cnt_reg[19]_i_1__5_n_0 ;
  wire \converge_cnt_reg[19]_i_2__5_n_0 ;
  wire \converge_cnt_reg[1]_i_1__5_n_0 ;
  wire \converge_cnt_reg[1]_i_2__5_n_0 ;
  wire \converge_cnt_reg[20]_i_1__5_n_0 ;
  wire \converge_cnt_reg[20]_i_2__5_n_0 ;
  wire \converge_cnt_reg[21]_i_1__5_n_0 ;
  wire \converge_cnt_reg[2]_i_1__5_n_0 ;
  wire \converge_cnt_reg[2]_i_2__5_n_0 ;
  wire \converge_cnt_reg[3]_i_1__5_n_0 ;
  wire \converge_cnt_reg[3]_i_2__5_n_0 ;
  wire \converge_cnt_reg[4]_i_1__5_n_0 ;
  wire \converge_cnt_reg[4]_i_2__5_n_0 ;
  wire \converge_cnt_reg[5]_i_1__5_n_0 ;
  wire \converge_cnt_reg[5]_i_2__5_n_0 ;
  wire \converge_cnt_reg[6]_i_1__5_n_0 ;
  wire \converge_cnt_reg[6]_i_2__5_n_0 ;
  wire \converge_cnt_reg[7]_i_1__5_n_0 ;
  wire \converge_cnt_reg[7]_i_2__5_n_0 ;
  wire \converge_cnt_reg[8]_i_1__5_n_0 ;
  wire \converge_cnt_reg[8]_i_2__5_n_0 ;
  wire \converge_cnt_reg[9]_i_1__5_n_0 ;
  wire \converge_cnt_reg[9]_i_2__5_n_0 ;
  wire converge_gen3_i_1__5_n_0;
  wire converge_gen3_reg_n_0;
  wire \cplllock_reg1_reg[2] ;
  wire \cplllock_reg1_reg[3] ;
  wire \cplllock_reg1_reg[6] ;
  wire \cplllock_reg1_reg[7] ;
  wire [1:0]fsm;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire gt_rxvalid_q_i_6__5_n_0;
  wire gt_rxvalid_q_reg;
  wire gt_rxvalid_q_reg_0;
  wire \gtx_channel.gtxe2_channel_i_i_57__2_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_71_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_80_n_0 ;
  wire [1:0]oobclk_cnt;
  wire \oobclk_div.oobclk_i_1__5_n_0 ;
  wire [0:0]out1;
  wire [3:0]p_0_in__0;
  wire [3:0]p_0_in__0__0;
  wire p_106_out;
  wire p_159_out;
  wire [1:0]p_1_in__0;
  wire p_216_out;
  wire pclk_sel_reg;
  wire pclk_sel_reg1;
  wire pclk_sel_reg2;
  wire [0:0]pipe_rxstatus;
  wire [0:0]pipe_txphaligndone;
  wire rate_done_reg1;
  wire rate_done_reg2;
  wire rate_gen3_reg1;
  wire rate_gen3_reg2;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire rate_rxsync_reg1;
  wire rate_rxsync_reg2;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire resetovrd_done_reg1_reg;
  wire resetovrd_start_reg1;
  wire resetovrd_start_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire [3:0]rxcdrlock_cnt_reg__0;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxeq_adapt_done_reg1;
  wire rxeq_adapt_done_reg2;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxstatus_reg1;
  wire rxstatus_reg2;
  wire [3:0]rxvalid_cnt_reg__0;
  wire rxvalid_reg1;
  wire rxvalid_reg2;
  wire sel;
  wire txcompliance_reg1;
  wire txcompliance_reg2;
  wire txcompliance_reg2_reg_0;
  wire txelecidle_reg1;
  wire txelecidle_reg2;
  wire txelecidle_reg2_reg_0;
  wire txelecidle_reg2_reg_1;
  wire txelecidle_reg2_reg_2;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire txsyncallin;
  wire [6:6]user_active_lane;
  wire [4:0]user_rx_converge;
  wire [3:0]\NLW_converge_cnt_reg[21]_i_2__5_CARRY4_CO_UNCONNECTED ;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__5_CARRY4_DI_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__5_CARRY4_O_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__5_CARRY4_S_UNCONNECTED ;

  assign p_0_in7_in = txcompliance_reg2;
  assign p_1_in8_in = txelecidle_reg2;
  assign p_2_in = rst_idle_reg2;
  LUT4 #(
    .INIT(16'hFFF7)) 
    \converge_cnt[0]_i_1__5 
       (.I0(rate_idle_reg2),
        .I1(rst_idle_reg2),
        .I2(RST_CPLLRESET),
        .I3(rate_gen3_reg2),
        .O(\converge_cnt[0]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h5D5D555D)) 
    \converge_cnt[0]_i_2__5 
       (.I0(converge_cnt_reg[21]),
        .I1(\converge_cnt[0]_i_4__5_n_0 ),
        .I2(converge_cnt_reg[20]),
        .I3(\converge_cnt[0]_i_5__5_n_0 ),
        .I4(\converge_cnt[0]_i_6__5_n_0 ),
        .O(sel));
  LUT6 #(
    .INIT(64'h13FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_4__5 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(converge_cnt_reg[13]),
        .I3(converge_cnt_reg[16]),
        .I4(converge_cnt_reg[15]),
        .I5(\converge_cnt[0]_i_8__5_n_0 ),
        .O(\converge_cnt[0]_i_4__5_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \converge_cnt[0]_i_5__5 
       (.I0(\converge_cnt[0]_i_8__5_n_0 ),
        .I1(converge_cnt_reg[16]),
        .I2(converge_cnt_reg[15]),
        .I3(converge_cnt_reg[13]),
        .I4(converge_cnt_reg[11]),
        .O(\converge_cnt[0]_i_5__5_n_0 ));
  LUT6 #(
    .INIT(64'h10FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_6__5 
       (.I0(converge_cnt_reg[3]),
        .I1(converge_cnt_reg[6]),
        .I2(\converge_cnt[0]_i_9__3_n_0 ),
        .I3(converge_cnt_reg[10]),
        .I4(converge_cnt_reg[8]),
        .I5(converge_cnt_reg[9]),
        .O(\converge_cnt[0]_i_6__5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[0]_i_7__5 
       (.I0(converge_cnt_reg[0]),
        .O(\converge_cnt[0]_i_7__5_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \converge_cnt[0]_i_8__5 
       (.I0(converge_cnt_reg[17]),
        .I1(converge_cnt_reg[18]),
        .I2(converge_cnt_reg[19]),
        .O(\converge_cnt[0]_i_8__5_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \converge_cnt[0]_i_9__3 
       (.I0(converge_cnt_reg[4]),
        .I1(converge_cnt_reg[5]),
        .I2(converge_cnt_reg[7]),
        .O(\converge_cnt[0]_i_9__3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[0]_i_3__5_n_0 ),
        .Q(converge_cnt_reg[0]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[10]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[10]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[11]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[11]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[12]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[12]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[13]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[13]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[13]_i_2__5_CARRY4 
       (.CI(\converge_cnt_reg[12]_i_2__5_n_0 ),
        .CO({\converge_cnt_reg[16]_i_2__5_n_0 ,\converge_cnt_reg[15]_i_2__5_n_0 ,\converge_cnt_reg[14]_i_2__5_n_0 ,\converge_cnt_reg[13]_i_2__5_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[15]_i_1__5_n_0 ,\converge_cnt_reg[14]_i_1__5_n_0 ,\converge_cnt_reg[13]_i_1__5_n_0 ,\converge_cnt_reg[12]_i_1__5_n_0 }),
        .S(converge_cnt_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[14]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[14]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[15]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[15]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[16]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[16]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[17]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[17]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[17]_i_2__5_CARRY4 
       (.CI(\converge_cnt_reg[16]_i_2__5_n_0 ),
        .CO({\converge_cnt_reg[20]_i_2__5_n_0 ,\converge_cnt_reg[19]_i_2__5_n_0 ,\converge_cnt_reg[18]_i_2__5_n_0 ,\converge_cnt_reg[17]_i_2__5_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[19]_i_1__5_n_0 ,\converge_cnt_reg[18]_i_1__5_n_0 ,\converge_cnt_reg[17]_i_1__5_n_0 ,\converge_cnt_reg[16]_i_1__5_n_0 }),
        .S(converge_cnt_reg[19:16]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[18]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[18]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[19]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[19]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[1]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[1]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[1]_i_2__5_CARRY4 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[4]_i_2__5_n_0 ,\converge_cnt_reg[3]_i_2__5_n_0 ,\converge_cnt_reg[2]_i_2__5_n_0 ,\converge_cnt_reg[1]_i_2__5_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\converge_cnt_reg[3]_i_1__5_n_0 ,\converge_cnt_reg[2]_i_1__5_n_0 ,\converge_cnt_reg[1]_i_1__5_n_0 ,\converge_cnt_reg[0]_i_3__5_n_0 }),
        .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_7__5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[20]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[20]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[21]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[21]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[21]_i_2__5_CARRY4 
       (.CI(\converge_cnt_reg[20]_i_2__5_n_0 ),
        .CO(\NLW_converge_cnt_reg[21]_i_2__5_CARRY4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({\NLW_converge_cnt_reg[21]_i_2__5_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__5_CARRY4_O_UNCONNECTED [3:2],\converge_cnt_reg[21]_i_1__5_n_0 ,\converge_cnt_reg[20]_i_1__5_n_0 }),
        .S({\NLW_converge_cnt_reg[21]_i_2__5_CARRY4_S_UNCONNECTED [3:2],converge_cnt_reg[21:20]}));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[2]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[2]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[3]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[3]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[4]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[4]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[5]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[5]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[5]_i_2__5_CARRY4 
       (.CI(\converge_cnt_reg[4]_i_2__5_n_0 ),
        .CO({\converge_cnt_reg[8]_i_2__5_n_0 ,\converge_cnt_reg[7]_i_2__5_n_0 ,\converge_cnt_reg[6]_i_2__5_n_0 ,\converge_cnt_reg[5]_i_2__5_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[7]_i_1__5_n_0 ,\converge_cnt_reg[6]_i_1__5_n_0 ,\converge_cnt_reg[5]_i_1__5_n_0 ,\converge_cnt_reg[4]_i_1__5_n_0 }),
        .S(converge_cnt_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[6]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[6]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[7]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[7]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[8]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[8]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[9]_i_1__5_n_0 ),
        .Q(converge_cnt_reg[9]),
        .R(\converge_cnt[0]_i_1__5_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[9]_i_2__5_CARRY4 
       (.CI(\converge_cnt_reg[8]_i_2__5_n_0 ),
        .CO({\converge_cnt_reg[12]_i_2__5_n_0 ,\converge_cnt_reg[11]_i_2__5_n_0 ,\converge_cnt_reg[10]_i_2__5_n_0 ,\converge_cnt_reg[9]_i_2__5_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[11]_i_1__5_n_0 ,\converge_cnt_reg[10]_i_1__5_n_0 ,\converge_cnt_reg[9]_i_1__5_n_0 ,\converge_cnt_reg[8]_i_1__5_n_0 }),
        .S(converge_cnt_reg[11:8]));
  LUT4 #(
    .INIT(16'h0C08)) 
    converge_gen3_i_1__5
       (.I0(rxeq_adapt_done_reg2),
        .I1(rate_gen3_reg2),
        .I2(RST_CPLLRESET),
        .I3(converge_gen3_reg_n_0),
        .O(converge_gen3_i_1__5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    converge_gen3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_gen3_i_1__5_n_0),
        .Q(converge_gen3_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFE0FF)) 
    gt_rx_phy_status_q_i_1__5
       (.I0(rate_idle_reg2),
        .I1(rate_rxsync_reg2),
        .I2(RST_PHYSTATUS),
        .I3(rst_idle_reg2),
        .I4(rate_done_reg2),
        .O(gt_rx_phy_status_wire_filter));
  LUT6 #(
    .INIT(64'h4500000000000000)) 
    gt_rxvalid_q_i_4__5
       (.I0(gt_rxvalid_q_i_6__5_n_0),
        .I1(gt_rxvalid_q_reg_0),
        .I2(gt_rx_elec_idle_wire_filter),
        .I3(rst_idle_reg2),
        .I4(rate_idle_reg2),
        .I5(\resetovrd_disble.reset_reg[4]_0 ),
        .O(gt_rxvalid_q_reg));
  LUT4 #(
    .INIT(16'h7FFF)) 
    gt_rxvalid_q_i_6__5
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[1]),
        .O(gt_rxvalid_q_i_6__5_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gtx_channel.gtxe2_channel_i_i_57__2 
       (.I0(p_106_out),
        .I1(user_rx_converge[4]),
        .I2(user_rx_converge[1]),
        .I3(user_rx_converge[0]),
        .I4(user_rx_converge[3]),
        .I5(user_rx_converge[2]),
        .O(\gtx_channel.gtxe2_channel_i_i_57__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_5__5 
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(\cplllock_reg1_reg[6] ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \gtx_channel.gtxe2_channel_i_i_61 
       (.I0(converge_gen3_reg_n_0),
        .I1(\gtx_channel.gtxe2_channel_i_i_71_n_0 ),
        .I2(converge_cnt_reg[8]),
        .I3(converge_cnt_reg[9]),
        .I4(\converge_cnt[0]_i_9__3_n_0 ),
        .I5(\converge_cnt[0]_i_5__5_n_0 ),
        .O(p_106_out));
  LUT5 #(
    .INIT(32'h00000010)) 
    \gtx_channel.gtxe2_channel_i_i_71 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(\gtx_channel.gtxe2_channel_i_i_80_n_0 ),
        .I3(converge_cnt_reg[2]),
        .I4(converge_cnt_reg[6]),
        .O(\gtx_channel.gtxe2_channel_i_i_71_n_0 ));
  LUT6 #(
    .INIT(64'h0004000000000000)) 
    \gtx_channel.gtxe2_channel_i_i_80 
       (.I0(converge_cnt_reg[20]),
        .I1(converge_cnt_reg[3]),
        .I2(converge_cnt_reg[0]),
        .I3(converge_cnt_reg[1]),
        .I4(converge_cnt_reg[10]),
        .I5(converge_cnt_reg[21]),
        .O(\gtx_channel.gtxe2_channel_i_i_80_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gtx_channel.gtxe2_channel_i_i_8__3 
       (.I0(\gtx_channel.gtxe2_channel_i_i_57__2_n_0 ),
        .I1(p_216_out),
        .I2(p_159_out),
        .O(GT_RX_CONVERGE0));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gtx_channel.gtxe2_channel_i_i_8__4 
       (.I0(\gtx_channel.gtxe2_channel_i_i_57__2_n_0 ),
        .I1(p_216_out),
        .I2(p_159_out),
        .O(\cplllock_reg1_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gtx_channel.gtxe2_channel_i_i_8__5 
       (.I0(\gtx_channel.gtxe2_channel_i_i_57__2_n_0 ),
        .I1(p_216_out),
        .I2(p_159_out),
        .O(\cplllock_reg1_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gtx_channel.gtxe2_channel_i_i_8__6 
       (.I0(\gtx_channel.gtxe2_channel_i_i_57__2_n_0 ),
        .I1(p_216_out),
        .I2(p_159_out),
        .O(\cplllock_reg1_reg[7] ));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oobclk_div.oobclk_cnt[0]_i_1__5 
       (.I0(oobclk_cnt[0]),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \oobclk_div.oobclk_cnt[1]_i_1__5 
       (.I0(oobclk_cnt[0]),
        .I1(oobclk_cnt[1]),
        .O(p_1_in__0[1]));
  FDRE \oobclk_div.oobclk_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[0]),
        .Q(oobclk_cnt[0]),
        .R(RST_CPLLRESET));
  FDRE \oobclk_div.oobclk_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[1]),
        .Q(oobclk_cnt[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hB8)) 
    \oobclk_div.oobclk_i_1__5 
       (.I0(oobclk_cnt[1]),
        .I1(pclk_sel_reg2),
        .I2(oobclk_cnt[0]),
        .O(\oobclk_div.oobclk_i_1__5_n_0 ));
  FDRE \oobclk_div.oobclk_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\oobclk_div.oobclk_i_1__5_n_0 ),
        .Q(USER_OOBCLK),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(CLK_PCLK_SEL),
        .Q(pclk_sel_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pclk_sel_reg1),
        .Q(pclk_sel_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_DONE),
        .Q(rate_done_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_done_reg1),
        .Q(rate_done_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_GEN3),
        .Q(rate_gen3_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3_reg1),
        .Q(rate_gen3_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_RXSYNC),
        .Q(rate_rxsync_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_rxsync_reg1),
        .Q(rate_rxsync_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT2 #(
    .INIT(4'h8)) 
    \resetdone_reg1[6]_i_1 
       (.I0(txresetdone_reg2),
        .I1(rxresetdone_reg2),
        .O(RST_RESETDONE));
  FDRE \resetovrd_disble.fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT2 #(
    .INIT(4'h1)) 
    resetovrd_done_reg1_i_1__5
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(resetovrd_done_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RESETOVRD_START),
        .Q(resetovrd_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetovrd_start_reg1),
        .Q(resetovrd_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(out1),
        .Q(rst_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT5 #(
    .INIT(32'h8A0A0A0A)) 
    \rxcdrlock_cnt[0]_i_1__5 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[2]),
        .I2(rxcdrlock_cnt_reg__0[0]),
        .I3(rxcdrlock_cnt_reg__0[1]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[0]));
  LUT5 #(
    .INIT(32'hA8282828)) 
    \rxcdrlock_cnt[1]_i_1__5 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[0]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[2]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[1]));
  LUT5 #(
    .INIT(32'h8CCCC000)) 
    \rxcdrlock_cnt[2]_i_1__5 
       (.I0(rxcdrlock_cnt_reg__0[3]),
        .I1(rxcdrlock_reg2),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \rxcdrlock_cnt[3]_i_1__5 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(rxcdrlock_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(rxcdrlock_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(rxcdrlock_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(rxcdrlock_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h80000000)) 
    \rxcdrlock_reg1[6]_i_1 
       (.I0(\resetovrd_disble.reset_reg[4]_1 ),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(RST_RXCDRLOCK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXEQ_ADAPT_DONE),
        .Q(rxeq_adapt_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_adapt_done_reg1),
        .Q(rxeq_adapt_done_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pipe_rxstatus),
        .Q(rxstatus_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxstatus_reg1),
        .Q(rxstatus_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT6 #(
    .INIT(64'h8080000000FF0000)) 
    \rxvalid_cnt[0]_i_1__5 
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[1]),
        .I3(rxstatus_reg2),
        .I4(rxvalid_reg2),
        .I5(rxvalid_cnt_reg__0[0]),
        .O(p_0_in__0__0[0]));
  LUT6 #(
    .INIT(64'h80000000E6660000)) 
    \rxvalid_cnt[1]_i_1__5 
       (.I0(rxvalid_cnt_reg__0[0]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[1]));
  LUT6 #(
    .INIT(64'h80000000EA6A0000)) 
    \rxvalid_cnt[2]_i_1__5 
       (.I0(rxvalid_cnt_reg__0[2]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'hD444444400000000)) 
    \rxvalid_cnt[3]_i_1__5 
       (.I0(rxstatus_reg2),
        .I1(rxvalid_cnt_reg__0[3]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[0]),
        .I4(rxvalid_cnt_reg__0[1]),
        .I5(rxvalid_reg2),
        .O(p_0_in__0__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(rxvalid_cnt_reg__0[0]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(rxvalid_cnt_reg__0[1]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(rxvalid_cnt_reg__0[2]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(rxvalid_cnt_reg__0[3]),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxvalid_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxvalid_reg1),
        .Q(rxvalid_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXCOMPLIANCE),
        .Q(txcompliance_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcompliance_reg1),
        .Q(txcompliance_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXELECIDLE),
        .Q(txelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg1),
        .Q(txelecidle_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0000000031000000)) 
    txphaligndone_reg1_i_1
       (.I0(user_active_lane),
        .I1(txelecidle_reg2_reg_0),
        .I2(pipe_txphaligndone),
        .I3(txelecidle_reg2_reg_1),
        .I4(txelecidle_reg2_reg_2),
        .I5(txcompliance_reg2_reg_0),
        .O(txsyncallin));
  LUT2 #(
    .INIT(4'h7)) 
    txphaligndone_reg1_i_2
       (.I0(txelecidle_reg2),
        .I1(txcompliance_reg2),
        .O(user_active_lane));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_user" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_71
   (txphinitdone_reg1_reg,
    p_1_in8_in,
    p_0_in7_in,
    txphaligndone_reg1_reg,
    gt_rxvalid_q_reg,
    phy_rdy_n_int_reg,
    USER_OOBCLK,
    Q,
    RST_RXCDRLOCK,
    gt_rx_phy_status_wire_filter,
    user_rx_converge,
    \cplllock_reg1_reg[7] ,
    resetovrd_done_reg1_reg,
    RST_RESETDONE,
    pipe_txphinitdone,
    p_0_in7_in_0,
    p_1_in8_in_1,
    pipe_txphaligndone,
    gt_rxvalid_q_reg_0,
    gt_rx_elec_idle_wire_filter,
    \resetovrd_disble.reset_reg[4]_0 ,
    p_2_in,
    p_2_in_2,
    p_2_in_3,
    p_2_in_4,
    p_2_in_5,
    RST_CPLLRESET,
    pclk_sel_reg,
    CLK_PCLK_SEL,
    USER_RXRESETDONE,
    USER_TXRESETDONE,
    PIPE_TXCOMPLIANCE,
    PIPE_TXELECIDLE,
    \resetovrd_disble.reset_reg[4]_1 ,
    RST_RXUSRCLK_RESET,
    pipe_rxstatus,
    out1,
    USER_RATE_IDLE,
    USER_RATE_RXSYNC,
    USER_RATE_DONE,
    gen3_reg,
    USER_RXEQ_ADAPT_DONE,
    USER_RESETOVRD_START,
    RST_PHYSTATUS);
  output txphinitdone_reg1_reg;
  output p_1_in8_in;
  output p_0_in7_in;
  output txphaligndone_reg1_reg;
  output gt_rxvalid_q_reg;
  output phy_rdy_n_int_reg;
  output USER_OOBCLK;
  output [6:0]Q;
  output [0:0]RST_RXCDRLOCK;
  output [0:0]gt_rx_phy_status_wire_filter;
  output [0:0]user_rx_converge;
  output \cplllock_reg1_reg[7] ;
  output resetovrd_done_reg1_reg;
  output [0:0]RST_RESETDONE;
  input [1:0]pipe_txphinitdone;
  input p_0_in7_in_0;
  input p_1_in8_in_1;
  input [0:0]pipe_txphaligndone;
  input gt_rxvalid_q_reg_0;
  input [0:0]gt_rx_elec_idle_wire_filter;
  input \resetovrd_disble.reset_reg[4]_0 ;
  input p_2_in;
  input p_2_in_2;
  input p_2_in_3;
  input p_2_in_4;
  input p_2_in_5;
  input RST_CPLLRESET;
  input pclk_sel_reg;
  input [0:0]CLK_PCLK_SEL;
  input USER_RXRESETDONE;
  input USER_TXRESETDONE;
  input [0:0]PIPE_TXCOMPLIANCE;
  input [0:0]PIPE_TXELECIDLE;
  input \resetovrd_disble.reset_reg[4]_1 ;
  input RST_RXUSRCLK_RESET;
  input [0:0]pipe_rxstatus;
  input [0:0]out1;
  input USER_RATE_IDLE;
  input USER_RATE_RXSYNC;
  input USER_RATE_DONE;
  input [0:0]gen3_reg;
  input USER_RXEQ_ADAPT_DONE;
  input USER_RESETOVRD_START;
  input [0:0]RST_PHYSTATUS;

  wire [0:0]CLK_PCLK_SEL;
  wire [0:0]PIPE_TXCOMPLIANCE;
  wire [0:0]PIPE_TXELECIDLE;
  wire [6:0]Q;
  wire RST_CPLLRESET;
  wire [0:0]RST_PHYSTATUS;
  wire [0:0]RST_RESETDONE;
  wire [0:0]RST_RXCDRLOCK;
  wire RST_RXUSRCLK_RESET;
  wire USER_OOBCLK;
  wire USER_RATE_DONE;
  wire USER_RATE_IDLE;
  wire USER_RATE_RXSYNC;
  wire USER_RESETOVRD_START;
  wire USER_RXEQ_ADAPT_DONE;
  wire USER_RXRESETDONE;
  wire USER_TXRESETDONE;
  wire \converge_cnt[0]_i_1__6_n_0 ;
  wire \converge_cnt[0]_i_4__6_n_0 ;
  wire \converge_cnt[0]_i_5__6_n_0 ;
  wire \converge_cnt[0]_i_6__6_n_0 ;
  wire \converge_cnt[0]_i_7__6_n_0 ;
  wire \converge_cnt[0]_i_8__6_n_0 ;
  wire \converge_cnt[0]_i_9__4_n_0 ;
  wire [21:0]converge_cnt_reg;
  wire \converge_cnt_reg[0]_i_3__6_n_0 ;
  wire \converge_cnt_reg[10]_i_1__6_n_0 ;
  wire \converge_cnt_reg[10]_i_2__6_n_0 ;
  wire \converge_cnt_reg[11]_i_1__6_n_0 ;
  wire \converge_cnt_reg[11]_i_2__6_n_0 ;
  wire \converge_cnt_reg[12]_i_1__6_n_0 ;
  wire \converge_cnt_reg[12]_i_2__6_n_0 ;
  wire \converge_cnt_reg[13]_i_1__6_n_0 ;
  wire \converge_cnt_reg[13]_i_2__6_n_0 ;
  wire \converge_cnt_reg[14]_i_1__6_n_0 ;
  wire \converge_cnt_reg[14]_i_2__6_n_0 ;
  wire \converge_cnt_reg[15]_i_1__6_n_0 ;
  wire \converge_cnt_reg[15]_i_2__6_n_0 ;
  wire \converge_cnt_reg[16]_i_1__6_n_0 ;
  wire \converge_cnt_reg[16]_i_2__6_n_0 ;
  wire \converge_cnt_reg[17]_i_1__6_n_0 ;
  wire \converge_cnt_reg[17]_i_2__6_n_0 ;
  wire \converge_cnt_reg[18]_i_1__6_n_0 ;
  wire \converge_cnt_reg[18]_i_2__6_n_0 ;
  wire \converge_cnt_reg[19]_i_1__6_n_0 ;
  wire \converge_cnt_reg[19]_i_2__6_n_0 ;
  wire \converge_cnt_reg[1]_i_1__6_n_0 ;
  wire \converge_cnt_reg[1]_i_2__6_n_0 ;
  wire \converge_cnt_reg[20]_i_1__6_n_0 ;
  wire \converge_cnt_reg[20]_i_2__6_n_0 ;
  wire \converge_cnt_reg[21]_i_1__6_n_0 ;
  wire \converge_cnt_reg[2]_i_1__6_n_0 ;
  wire \converge_cnt_reg[2]_i_2__6_n_0 ;
  wire \converge_cnt_reg[3]_i_1__6_n_0 ;
  wire \converge_cnt_reg[3]_i_2__6_n_0 ;
  wire \converge_cnt_reg[4]_i_1__6_n_0 ;
  wire \converge_cnt_reg[4]_i_2__6_n_0 ;
  wire \converge_cnt_reg[5]_i_1__6_n_0 ;
  wire \converge_cnt_reg[5]_i_2__6_n_0 ;
  wire \converge_cnt_reg[6]_i_1__6_n_0 ;
  wire \converge_cnt_reg[6]_i_2__6_n_0 ;
  wire \converge_cnt_reg[7]_i_1__6_n_0 ;
  wire \converge_cnt_reg[7]_i_2__6_n_0 ;
  wire \converge_cnt_reg[8]_i_1__6_n_0 ;
  wire \converge_cnt_reg[8]_i_2__6_n_0 ;
  wire \converge_cnt_reg[9]_i_1__6_n_0 ;
  wire \converge_cnt_reg[9]_i_2__6_n_0 ;
  wire converge_gen3_i_1__6_n_0;
  wire converge_gen3_reg_n_0;
  wire \cplllock_reg1_reg[7] ;
  wire [1:0]fsm;
  wire [0:0]gen3_reg;
  wire [0:0]gt_rx_elec_idle_wire_filter;
  wire [0:0]gt_rx_phy_status_wire_filter;
  wire gt_rxvalid_q_i_6__6_n_0;
  wire gt_rxvalid_q_reg;
  wire gt_rxvalid_q_reg_0;
  wire \gtx_channel.gtxe2_channel_i_i_72_n_0 ;
  wire \gtx_channel.gtxe2_channel_i_i_81_n_0 ;
  wire [1:0]oobclk_cnt;
  wire \oobclk_div.oobclk_i_1__6_n_0 ;
  wire [0:0]out1;
  wire p_0_in7_in_0;
  wire [3:0]p_0_in__0;
  wire [3:0]p_0_in__0__0;
  wire p_1_in8_in_1;
  wire [1:0]p_1_in__0;
  wire p_2_in;
  wire p_2_in_2;
  wire p_2_in_3;
  wire p_2_in_4;
  wire p_2_in_5;
  wire pclk_sel_reg;
  wire pclk_sel_reg1;
  wire pclk_sel_reg2;
  wire phy_rdy_n_int_reg;
  wire [0:0]pipe_rxstatus;
  wire [0:0]pipe_txphaligndone;
  wire [1:0]pipe_txphinitdone;
  wire rate_done_reg1;
  wire rate_done_reg2;
  wire rate_gen3_reg1;
  wire rate_gen3_reg2;
  wire rate_idle_reg1;
  wire rate_idle_reg2;
  wire rate_rxsync_reg1;
  wire rate_rxsync_reg2;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire \resetovrd_disble.reset_reg[4]_1 ;
  wire resetovrd_done_reg1_reg;
  wire resetovrd_start_reg1;
  wire resetovrd_start_reg2;
  wire rst_idle_reg1;
  wire rst_idle_reg2;
  wire [3:0]rxcdrlock_cnt_reg__0;
  wire rxcdrlock_reg1;
  wire rxcdrlock_reg2;
  wire rxeq_adapt_done_reg1;
  wire rxeq_adapt_done_reg2;
  wire rxresetdone_reg1;
  wire rxresetdone_reg2;
  wire rxstatus_reg1;
  wire rxstatus_reg2;
  wire [3:0]rxvalid_cnt_reg__0;
  wire rxvalid_reg1;
  wire rxvalid_reg2;
  wire sel;
  wire txcompliance_reg1;
  wire txcompliance_reg2;
  wire txelecidle_reg1;
  wire txelecidle_reg2;
  wire txphaligndone_reg1_reg;
  wire txphinitdone_reg1_reg;
  wire txresetdone_reg1;
  wire txresetdone_reg2;
  wire [0:0]user_rx_converge;
  wire [3:0]\NLW_converge_cnt_reg[21]_i_2__6_CARRY4_CO_UNCONNECTED ;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__6_CARRY4_DI_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__6_CARRY4_O_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__6_CARRY4_S_UNCONNECTED ;

  assign p_0_in7_in = txcompliance_reg2;
  assign p_1_in8_in = txelecidle_reg2;
  LUT4 #(
    .INIT(16'hFFF7)) 
    \converge_cnt[0]_i_1__6 
       (.I0(rate_idle_reg2),
        .I1(rst_idle_reg2),
        .I2(RST_CPLLRESET),
        .I3(rate_gen3_reg2),
        .O(\converge_cnt[0]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h5D5D555D)) 
    \converge_cnt[0]_i_2__6 
       (.I0(converge_cnt_reg[21]),
        .I1(\converge_cnt[0]_i_4__6_n_0 ),
        .I2(converge_cnt_reg[20]),
        .I3(\converge_cnt[0]_i_5__6_n_0 ),
        .I4(\converge_cnt[0]_i_6__6_n_0 ),
        .O(sel));
  LUT6 #(
    .INIT(64'h13FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_4__6 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(converge_cnt_reg[13]),
        .I3(converge_cnt_reg[16]),
        .I4(converge_cnt_reg[15]),
        .I5(\converge_cnt[0]_i_8__6_n_0 ),
        .O(\converge_cnt[0]_i_4__6_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \converge_cnt[0]_i_5__6 
       (.I0(\converge_cnt[0]_i_8__6_n_0 ),
        .I1(converge_cnt_reg[16]),
        .I2(converge_cnt_reg[15]),
        .I3(converge_cnt_reg[13]),
        .I4(converge_cnt_reg[11]),
        .O(\converge_cnt[0]_i_5__6_n_0 ));
  LUT6 #(
    .INIT(64'h10FFFFFFFFFFFFFF)) 
    \converge_cnt[0]_i_6__6 
       (.I0(converge_cnt_reg[3]),
        .I1(converge_cnt_reg[6]),
        .I2(\converge_cnt[0]_i_9__4_n_0 ),
        .I3(converge_cnt_reg[10]),
        .I4(converge_cnt_reg[8]),
        .I5(converge_cnt_reg[9]),
        .O(\converge_cnt[0]_i_6__6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[0]_i_7__6 
       (.I0(converge_cnt_reg[0]),
        .O(\converge_cnt[0]_i_7__6_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \converge_cnt[0]_i_8__6 
       (.I0(converge_cnt_reg[17]),
        .I1(converge_cnt_reg[18]),
        .I2(converge_cnt_reg[19]),
        .O(\converge_cnt[0]_i_8__6_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \converge_cnt[0]_i_9__4 
       (.I0(converge_cnt_reg[4]),
        .I1(converge_cnt_reg[5]),
        .I2(converge_cnt_reg[7]),
        .O(\converge_cnt[0]_i_9__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[0]_i_3__6_n_0 ),
        .Q(converge_cnt_reg[0]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[10]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[10]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[11]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[11]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[12]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[12]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[13]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[13]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[13]_i_2__6_CARRY4 
       (.CI(\converge_cnt_reg[12]_i_2__6_n_0 ),
        .CO({\converge_cnt_reg[16]_i_2__6_n_0 ,\converge_cnt_reg[15]_i_2__6_n_0 ,\converge_cnt_reg[14]_i_2__6_n_0 ,\converge_cnt_reg[13]_i_2__6_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[15]_i_1__6_n_0 ,\converge_cnt_reg[14]_i_1__6_n_0 ,\converge_cnt_reg[13]_i_1__6_n_0 ,\converge_cnt_reg[12]_i_1__6_n_0 }),
        .S(converge_cnt_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[14]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[14]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[15]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[15]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[16]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[16]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[17]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[17]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[17]_i_2__6_CARRY4 
       (.CI(\converge_cnt_reg[16]_i_2__6_n_0 ),
        .CO({\converge_cnt_reg[20]_i_2__6_n_0 ,\converge_cnt_reg[19]_i_2__6_n_0 ,\converge_cnt_reg[18]_i_2__6_n_0 ,\converge_cnt_reg[17]_i_2__6_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[19]_i_1__6_n_0 ,\converge_cnt_reg[18]_i_1__6_n_0 ,\converge_cnt_reg[17]_i_1__6_n_0 ,\converge_cnt_reg[16]_i_1__6_n_0 }),
        .S(converge_cnt_reg[19:16]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[18]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[18]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[19]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[19]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[1]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[1]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[1]_i_2__6_CARRY4 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[4]_i_2__6_n_0 ,\converge_cnt_reg[3]_i_2__6_n_0 ,\converge_cnt_reg[2]_i_2__6_n_0 ,\converge_cnt_reg[1]_i_2__6_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\converge_cnt_reg[3]_i_1__6_n_0 ,\converge_cnt_reg[2]_i_1__6_n_0 ,\converge_cnt_reg[1]_i_1__6_n_0 ,\converge_cnt_reg[0]_i_3__6_n_0 }),
        .S({converge_cnt_reg[3:1],\converge_cnt[0]_i_7__6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[20]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[20]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[21]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[21]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[21]_i_2__6_CARRY4 
       (.CI(\converge_cnt_reg[20]_i_2__6_n_0 ),
        .CO(\NLW_converge_cnt_reg[21]_i_2__6_CARRY4_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({\NLW_converge_cnt_reg[21]_i_2__6_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__6_CARRY4_O_UNCONNECTED [3:2],\converge_cnt_reg[21]_i_1__6_n_0 ,\converge_cnt_reg[20]_i_1__6_n_0 }),
        .S({\NLW_converge_cnt_reg[21]_i_2__6_CARRY4_S_UNCONNECTED [3:2],converge_cnt_reg[21:20]}));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[2]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[2]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[3]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[3]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[4]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[4]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[5]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[5]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[5]_i_2__6_CARRY4 
       (.CI(\converge_cnt_reg[4]_i_2__6_n_0 ),
        .CO({\converge_cnt_reg[8]_i_2__6_n_0 ,\converge_cnt_reg[7]_i_2__6_n_0 ,\converge_cnt_reg[6]_i_2__6_n_0 ,\converge_cnt_reg[5]_i_2__6_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[7]_i_1__6_n_0 ,\converge_cnt_reg[6]_i_1__6_n_0 ,\converge_cnt_reg[5]_i_1__6_n_0 ,\converge_cnt_reg[4]_i_1__6_n_0 }),
        .S(converge_cnt_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[6]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[6]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[7]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[7]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[8]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[8]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(sel),
        .D(\converge_cnt_reg[9]_i_1__6_n_0 ),
        .Q(converge_cnt_reg[9]),
        .R(\converge_cnt[0]_i_1__6_n_0 ));
  (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  CARRY4 \converge_cnt_reg[9]_i_2__6_CARRY4 
       (.CI(\converge_cnt_reg[8]_i_2__6_n_0 ),
        .CO({\converge_cnt_reg[12]_i_2__6_n_0 ,\converge_cnt_reg[11]_i_2__6_n_0 ,\converge_cnt_reg[10]_i_2__6_n_0 ,\converge_cnt_reg[9]_i_2__6_n_0 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\converge_cnt_reg[11]_i_1__6_n_0 ,\converge_cnt_reg[10]_i_1__6_n_0 ,\converge_cnt_reg[9]_i_1__6_n_0 ,\converge_cnt_reg[8]_i_1__6_n_0 }),
        .S(converge_cnt_reg[11:8]));
  LUT4 #(
    .INIT(16'h0C08)) 
    converge_gen3_i_1__6
       (.I0(rxeq_adapt_done_reg2),
        .I1(rate_gen3_reg2),
        .I2(RST_CPLLRESET),
        .I3(converge_gen3_reg_n_0),
        .O(converge_gen3_i_1__6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    converge_gen3_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_gen3_i_1__6_n_0),
        .Q(converge_gen3_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFE0FF)) 
    gt_rx_phy_status_q_i_1__6
       (.I0(rate_idle_reg2),
        .I1(rate_rxsync_reg2),
        .I2(RST_PHYSTATUS),
        .I3(rst_idle_reg2),
        .I4(rate_done_reg2),
        .O(gt_rx_phy_status_wire_filter));
  LUT6 #(
    .INIT(64'h4500000000000000)) 
    gt_rxvalid_q_i_4__6
       (.I0(gt_rxvalid_q_i_6__6_n_0),
        .I1(gt_rxvalid_q_reg_0),
        .I2(gt_rx_elec_idle_wire_filter),
        .I3(rst_idle_reg2),
        .I4(rate_idle_reg2),
        .I5(\resetovrd_disble.reset_reg[4]_0 ),
        .O(gt_rxvalid_q_reg));
  LUT4 #(
    .INIT(16'h7FFF)) 
    gt_rxvalid_q_i_6__6
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[1]),
        .O(gt_rxvalid_q_i_6__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_channel.gtxe2_channel_i_i_5__6 
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(\cplllock_reg1_reg[7] ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \gtx_channel.gtxe2_channel_i_i_62 
       (.I0(converge_gen3_reg_n_0),
        .I1(\gtx_channel.gtxe2_channel_i_i_72_n_0 ),
        .I2(converge_cnt_reg[8]),
        .I3(converge_cnt_reg[9]),
        .I4(\converge_cnt[0]_i_9__4_n_0 ),
        .I5(\converge_cnt[0]_i_5__6_n_0 ),
        .O(user_rx_converge));
  LUT5 #(
    .INIT(32'h00000010)) 
    \gtx_channel.gtxe2_channel_i_i_72 
       (.I0(converge_cnt_reg[12]),
        .I1(converge_cnt_reg[14]),
        .I2(\gtx_channel.gtxe2_channel_i_i_81_n_0 ),
        .I3(converge_cnt_reg[2]),
        .I4(converge_cnt_reg[6]),
        .O(\gtx_channel.gtxe2_channel_i_i_72_n_0 ));
  LUT6 #(
    .INIT(64'h0004000000000000)) 
    \gtx_channel.gtxe2_channel_i_i_81 
       (.I0(converge_cnt_reg[20]),
        .I1(converge_cnt_reg[3]),
        .I2(converge_cnt_reg[0]),
        .I3(converge_cnt_reg[1]),
        .I4(converge_cnt_reg[10]),
        .I5(converge_cnt_reg[21]),
        .O(\gtx_channel.gtxe2_channel_i_i_81_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oobclk_div.oobclk_cnt[0]_i_1__6 
       (.I0(oobclk_cnt[0]),
        .O(p_1_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \oobclk_div.oobclk_cnt[1]_i_1__6 
       (.I0(oobclk_cnt[0]),
        .I1(oobclk_cnt[1]),
        .O(p_1_in__0[1]));
  FDRE \oobclk_div.oobclk_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[0]),
        .Q(oobclk_cnt[0]),
        .R(RST_CPLLRESET));
  FDRE \oobclk_div.oobclk_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_1_in__0[1]),
        .Q(oobclk_cnt[1]),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hB8)) 
    \oobclk_div.oobclk_i_1__6 
       (.I0(oobclk_cnt[1]),
        .I1(pclk_sel_reg2),
        .I2(oobclk_cnt[0]),
        .O(\oobclk_div.oobclk_i_1__6_n_0 ));
  FDRE \oobclk_div.oobclk_reg 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\oobclk_div.oobclk_i_1__6_n_0 ),
        .Q(USER_OOBCLK),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(CLK_PCLK_SEL),
        .Q(pclk_sel_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pclk_sel_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pclk_sel_reg1),
        .Q(pclk_sel_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    phy_rdy_n_int_i_3
       (.I0(rst_idle_reg2),
        .I1(p_2_in),
        .I2(p_2_in_2),
        .I3(p_2_in_3),
        .I4(p_2_in_4),
        .I5(p_2_in_5),
        .O(phy_rdy_n_int_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_DONE),
        .Q(rate_done_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_done_reg1),
        .Q(rate_done_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(gen3_reg),
        .Q(rate_gen3_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_gen3_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_gen3_reg1),
        .Q(rate_gen3_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_IDLE),
        .Q(rate_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_idle_reg1),
        .Q(rate_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RATE_RXSYNC),
        .Q(rate_rxsync_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rate_rxsync_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_rxsync_reg1),
        .Q(rate_rxsync_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT2 #(
    .INIT(4'h8)) 
    \resetdone_reg1[7]_i_1 
       (.I0(txresetdone_reg2),
        .I1(rxresetdone_reg2),
        .O(RST_RESETDONE));
  FDRE \resetovrd_disble.fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(fsm[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \resetovrd_disble.reset_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT2 #(
    .INIT(4'h1)) 
    resetovrd_done_reg1_i_1__6
       (.I0(fsm[1]),
        .I1(fsm[0]),
        .O(resetovrd_done_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RESETOVRD_START),
        .Q(resetovrd_start_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE resetovrd_start_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(resetovrd_start_reg1),
        .Q(resetovrd_start_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(out1),
        .Q(rst_idle_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rst_idle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rst_idle_reg1),
        .Q(rst_idle_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT5 #(
    .INIT(32'h8A0A0A0A)) 
    \rxcdrlock_cnt[0]_i_1__6 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[2]),
        .I2(rxcdrlock_cnt_reg__0[0]),
        .I3(rxcdrlock_cnt_reg__0[1]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[0]));
  LUT5 #(
    .INIT(32'hA8282828)) 
    \rxcdrlock_cnt[1]_i_1__6 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[0]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[2]),
        .I4(rxcdrlock_cnt_reg__0[3]),
        .O(p_0_in__0[1]));
  LUT5 #(
    .INIT(32'h8CCCC000)) 
    \rxcdrlock_cnt[2]_i_1__6 
       (.I0(rxcdrlock_cnt_reg__0[3]),
        .I1(rxcdrlock_reg2),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hA8888888)) 
    \rxcdrlock_cnt[3]_i_1__6 
       (.I0(rxcdrlock_reg2),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(rxcdrlock_cnt_reg__0[0]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(rxcdrlock_cnt_reg__0[1]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(rxcdrlock_cnt_reg__0[2]),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxcdrlock_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(rxcdrlock_cnt_reg__0[3]),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h80000000)) 
    \rxcdrlock_reg1[7]_i_1 
       (.I0(\resetovrd_disble.reset_reg[4]_1 ),
        .I1(rxcdrlock_cnt_reg__0[3]),
        .I2(rxcdrlock_cnt_reg__0[1]),
        .I3(rxcdrlock_cnt_reg__0[0]),
        .I4(rxcdrlock_cnt_reg__0[2]),
        .O(RST_RXCDRLOCK));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_1 ),
        .Q(rxcdrlock_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxcdrlock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxcdrlock_reg1),
        .Q(rxcdrlock_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXEQ_ADAPT_DONE),
        .Q(rxeq_adapt_done_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxeq_adapt_done_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_adapt_done_reg1),
        .Q(rxeq_adapt_done_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_RXRESETDONE),
        .Q(rxresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxresetdone_reg1),
        .Q(rxresetdone_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(pipe_rxstatus),
        .Q(rxstatus_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxstatus_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxstatus_reg1),
        .Q(rxstatus_reg2),
        .R(RST_RXUSRCLK_RESET));
  LUT6 #(
    .INIT(64'h8080000000FF0000)) 
    \rxvalid_cnt[0]_i_1__6 
       (.I0(rxvalid_cnt_reg__0[3]),
        .I1(rxvalid_cnt_reg__0[2]),
        .I2(rxvalid_cnt_reg__0[1]),
        .I3(rxstatus_reg2),
        .I4(rxvalid_reg2),
        .I5(rxvalid_cnt_reg__0[0]),
        .O(p_0_in__0__0[0]));
  LUT6 #(
    .INIT(64'h80000000E6660000)) 
    \rxvalid_cnt[1]_i_1__6 
       (.I0(rxvalid_cnt_reg__0[0]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[1]));
  LUT6 #(
    .INIT(64'h80000000EA6A0000)) 
    \rxvalid_cnt[2]_i_1__6 
       (.I0(rxvalid_cnt_reg__0[2]),
        .I1(rxvalid_cnt_reg__0[1]),
        .I2(rxvalid_cnt_reg__0[0]),
        .I3(rxvalid_cnt_reg__0[3]),
        .I4(rxvalid_reg2),
        .I5(rxstatus_reg2),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'hD444444400000000)) 
    \rxvalid_cnt[3]_i_1__6 
       (.I0(rxstatus_reg2),
        .I1(rxvalid_cnt_reg__0[3]),
        .I2(rxvalid_cnt_reg__0[2]),
        .I3(rxvalid_cnt_reg__0[0]),
        .I4(rxvalid_cnt_reg__0[1]),
        .I5(rxvalid_reg2),
        .O(p_0_in__0__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(rxvalid_cnt_reg__0[0]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(rxvalid_cnt_reg__0[1]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(rxvalid_cnt_reg__0[2]),
        .R(RST_RXUSRCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \rxvalid_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(rxvalid_cnt_reg__0[3]),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(rxvalid_reg1),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rxvalid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxvalid_reg1),
        .Q(rxvalid_reg2),
        .R(RST_RXUSRCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXCOMPLIANCE),
        .Q(txcompliance_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txcompliance_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcompliance_reg1),
        .Q(txcompliance_reg2),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(PIPE_TXELECIDLE),
        .Q(txelecidle_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txelecidle_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txelecidle_reg1),
        .Q(txelecidle_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'h07)) 
    txphaligndone_reg1_i_6
       (.I0(txcompliance_reg2),
        .I1(txelecidle_reg2),
        .I2(pipe_txphaligndone),
        .O(txphaligndone_reg1_reg));
  LUT6 #(
    .INIT(64'h1515151515FFFFFF)) 
    txphinitdone_reg1_i_2
       (.I0(pipe_txphinitdone[1]),
        .I1(txelecidle_reg2),
        .I2(txcompliance_reg2),
        .I3(p_0_in7_in_0),
        .I4(p_1_in8_in_1),
        .I5(pipe_txphinitdone[0]),
        .O(txphinitdone_reg1_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(USER_TXRESETDONE),
        .Q(txresetdone_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE txresetdone_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txresetdone_reg1),
        .Q(txresetdone_reg2),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_pipe_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_pipe_wrapper
   (QRST_QPLLLOCK,
    \cplllock_reg1_reg[3] ,
    \cplllock_reg1_reg[3]_0 ,
    CLK_DCLK,
    QRST_CPLLLOCK,
    ext_ch_gt_drprdy,
    pipe_eyescandataerror,
    pci_exp_txn,
    pci_exp_txp,
    PIPE_RXCHANISALIGNED,
    pipe_rxcommadet,
    pipe_rxdlysresetdone,
    gt_rx_elec_idle_wire_filter,
    pipe_rxoutclk_out,
    SYNC_RXPHALIGNDONE_M,
    pipe_rxprbserr,
    pipe_txdlysresetdone,
    pipe_txoutclk_out,
    pipe_txphaligndone,
    pipe_txphinitdone,
    ext_ch_gt_drpdo,
    pipe_rxbufstatus,
    pipe_rxstatus,
    PIPE_RXDATA,
    pipe_dmonitorout,
    PIPE_RXDATAK,
    pipe_rxdisperr,
    pipe_rxnotintable,
    CLK_OOBCLK,
    GT_TXPMARESET0,
    pipe_rxphaligndone,
    \gt_rxdata_q_reg[15] ,
    \gt_rxcharisk_q_reg[1] ,
    GT_TXPMARESET092_out,
    \gt_rxdata_q_reg[15]_0 ,
    \gt_rxcharisk_q_reg[1]_0 ,
    GT_TXPMARESET0120_out,
    \gt_rxdata_q_reg[15]_1 ,
    \gt_rxcharisk_q_reg[1]_1 ,
    GT_TXPMARESET074_out,
    \cplllock_reg1_reg[7] ,
    \cplllock_reg1_reg[7]_0 ,
    \gt_rxdata_q_reg[15]_2 ,
    \gt_rxcharisk_q_reg[1]_2 ,
    GT_TXPMARESET064_out,
    \gt_rxdata_q_reg[15]_3 ,
    \gt_rxcharisk_q_reg[1]_3 ,
    GT_TXPMARESET046_out,
    \gt_rxdata_q_reg[15]_4 ,
    \gt_rxcharisk_q_reg[1]_4 ,
    GT_TXPMARESET035_out,
    \gt_rxdata_q_reg[15]_5 ,
    \gt_rxcharisk_q_reg[1]_5 ,
    GT_TXPMARESET017_out,
    reset_n_reg2_reg_0,
    pipe_qrst_fsm,
    SYNC_FSM_TX,
    RATE_FSM,
    gt_rxvalid_q_reg,
    DRP_FSM,
    \txsync_fsm.txdlyen_reg ,
    \sysclksel_reg[1] ,
    gt_rxvalid_q_reg_0,
    \index_reg[1] ,
    \txsync_fsm.txdlyen_reg_0 ,
    \sysclksel_reg[1]_0 ,
    gt_rxvalid_q_reg_1,
    \index_reg[1]_0 ,
    \txsync_fsm.txdlyen_reg_1 ,
    \sysclksel_reg[1]_1 ,
    gt_rxvalid_q_reg_2,
    \index_reg[1]_1 ,
    \txsync_fsm.txdlyen_reg_2 ,
    \sysclksel_reg[1]_2 ,
    gt_rxvalid_q_reg_3,
    \index_reg[1]_2 ,
    \txsync_fsm.txdlyen_reg_3 ,
    \sysclksel_reg[1]_3 ,
    gt_rxvalid_q_reg_4,
    \index_reg[1]_3 ,
    \txsync_fsm.txdlyen_reg_4 ,
    \sysclksel_reg[1]_4 ,
    gt_rxvalid_q_reg_5,
    \index_reg[1]_4 ,
    \txsync_fsm.txdlyen_reg_5 ,
    \sysclksel_reg[1]_5 ,
    gt_rxvalid_q_reg_6,
    \index_reg[1]_5 ,
    D,
    \gt_rx_status_q_reg[2] ,
    \gt_rx_status_q_reg[2]_0 ,
    \gt_rx_status_q_reg[2]_1 ,
    \gt_rx_status_q_reg[2]_2 ,
    \gt_rx_status_q_reg[2]_3 ,
    \gt_rx_status_q_reg[2]_4 ,
    \gt_rx_status_q_reg[2]_5 ,
    \gt_rx_status_q_reg[2]_6 ,
    pipe_rate_idle,
    EQ_GEN3,
    CLK_MMCM_LOCK,
    CLK_USERCLK1,
    CLK_PCLK_SEL,
    pipe_qrst_idle,
    gt_ch_drp_rdy,
    out,
    pipe_rst_fsm,
    USER_RXPMARESET,
    gt_rx_phy_status_wire_filter,
    \cplllock_reg1_reg[1] ,
    \cplllock_reg1_reg[2] ,
    \cplllock_reg1_reg[3]_1 ,
    \cplllock_reg1_reg[4] ,
    \cplllock_reg1_reg[5] ,
    \cplllock_reg1_reg[6] ,
    \cplllock_reg1_reg[7]_1 ,
    pipe_sync_fsm_rx,
    sys_clk,
    pci_exp_rxn,
    pci_exp_rxp,
    GT_RXPMARESET0,
    PIPE_RXPOLARITY,
    PIPE_TXDEEMPH,
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ,
    PIPE_TXELECIDLE,
    pipe_txinhibit,
    PIPE_POWERDOWN,
    TXMARGIN,
    PIPE_TXDATA,
    PIPE_TXCOMPLIANCE,
    PIPE_TXDATAK,
    GT_RXPMARESET089_out,
    \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ,
    \pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ,
    GT_RXPMARESET0117_out,
    GT_RXPMARESET071_out,
    GT_RXPMARESET061_out,
    PIPE_TXDETECTRX,
    PIPE_TXMARGIN,
    GT_RXPMARESET043_out,
    pipe_tx_rcvr_det,
    \pipe_stages_1.pipe_tx_margin_q_reg[2] ,
    GT_RXPMARESET032_out,
    GT_RXPMARESET014_out,
    gt_rxvalid_q_reg_7,
    gt_rxvalid_q_reg_8,
    gt_rxvalid_q_reg_9,
    gt_rxvalid_q_reg_10,
    gt_rxvalid_q_reg_11,
    gt_rxvalid_q_reg_12,
    gt_rxvalid_q_reg_13,
    gt_rxvalid_q_reg_14,
    ext_ch_gt_drpaddr,
    Q,
    \pl_ltssm_state_q_reg[4] ,
    sys_rst_n,
    int_pclk_sel_slave,
    pipe_mmcm_rst_n,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    ext_ch_gt_drpen,
    ext_ch_gt_drpwe,
    ext_ch_gt_drpdi);
  output [1:0]QRST_QPLLLOCK;
  output \cplllock_reg1_reg[3] ;
  output \cplllock_reg1_reg[3]_0 ;
  output CLK_DCLK;
  output [7:0]QRST_CPLLLOCK;
  output [7:0]ext_ch_gt_drprdy;
  output [7:0]pipe_eyescandataerror;
  output [7:0]pci_exp_txn;
  output [7:0]pci_exp_txp;
  output [7:0]PIPE_RXCHANISALIGNED;
  output [7:0]pipe_rxcommadet;
  output [7:0]pipe_rxdlysresetdone;
  output [7:0]gt_rx_elec_idle_wire_filter;
  output [7:0]pipe_rxoutclk_out;
  output SYNC_RXPHALIGNDONE_M;
  output [7:0]pipe_rxprbserr;
  output [7:0]pipe_txdlysresetdone;
  output pipe_txoutclk_out;
  output [7:0]pipe_txphaligndone;
  output [7:0]pipe_txphinitdone;
  output [127:0]ext_ch_gt_drpdo;
  output [23:0]pipe_rxbufstatus;
  output [23:0]pipe_rxstatus;
  output [15:0]PIPE_RXDATA;
  output [63:0]pipe_dmonitorout;
  output [1:0]PIPE_RXDATAK;
  output [63:0]pipe_rxdisperr;
  output [63:0]pipe_rxnotintable;
  output CLK_OOBCLK;
  output GT_TXPMARESET0;
  output [6:0]pipe_rxphaligndone;
  output [15:0]\gt_rxdata_q_reg[15] ;
  output [1:0]\gt_rxcharisk_q_reg[1] ;
  output GT_TXPMARESET092_out;
  output [15:0]\gt_rxdata_q_reg[15]_0 ;
  output [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  output GT_TXPMARESET0120_out;
  output [15:0]\gt_rxdata_q_reg[15]_1 ;
  output [1:0]\gt_rxcharisk_q_reg[1]_1 ;
  output GT_TXPMARESET074_out;
  output \cplllock_reg1_reg[7] ;
  output \cplllock_reg1_reg[7]_0 ;
  output [15:0]\gt_rxdata_q_reg[15]_2 ;
  output [1:0]\gt_rxcharisk_q_reg[1]_2 ;
  output GT_TXPMARESET064_out;
  output [15:0]\gt_rxdata_q_reg[15]_3 ;
  output [1:0]\gt_rxcharisk_q_reg[1]_3 ;
  output GT_TXPMARESET046_out;
  output [15:0]\gt_rxdata_q_reg[15]_4 ;
  output [1:0]\gt_rxcharisk_q_reg[1]_4 ;
  output GT_TXPMARESET035_out;
  output [15:0]\gt_rxdata_q_reg[15]_5 ;
  output [1:0]\gt_rxcharisk_q_reg[1]_5 ;
  output GT_TXPMARESET017_out;
  output reset_n_reg2_reg_0;
  output [3:0]pipe_qrst_fsm;
  output [5:0]SYNC_FSM_TX;
  output [4:0]RATE_FSM;
  output gt_rxvalid_q_reg;
  output [2:0]DRP_FSM;
  output [5:0]\txsync_fsm.txdlyen_reg ;
  output [4:0]\sysclksel_reg[1] ;
  output gt_rxvalid_q_reg_0;
  output [2:0]\index_reg[1] ;
  output [5:0]\txsync_fsm.txdlyen_reg_0 ;
  output [4:0]\sysclksel_reg[1]_0 ;
  output gt_rxvalid_q_reg_1;
  output [2:0]\index_reg[1]_0 ;
  output [5:0]\txsync_fsm.txdlyen_reg_1 ;
  output [4:0]\sysclksel_reg[1]_1 ;
  output gt_rxvalid_q_reg_2;
  output [2:0]\index_reg[1]_1 ;
  output [5:0]\txsync_fsm.txdlyen_reg_2 ;
  output [4:0]\sysclksel_reg[1]_2 ;
  output gt_rxvalid_q_reg_3;
  output [2:0]\index_reg[1]_2 ;
  output [5:0]\txsync_fsm.txdlyen_reg_3 ;
  output [4:0]\sysclksel_reg[1]_3 ;
  output gt_rxvalid_q_reg_4;
  output [2:0]\index_reg[1]_3 ;
  output [5:0]\txsync_fsm.txdlyen_reg_4 ;
  output [4:0]\sysclksel_reg[1]_4 ;
  output gt_rxvalid_q_reg_5;
  output [2:0]\index_reg[1]_4 ;
  output [5:0]\txsync_fsm.txdlyen_reg_5 ;
  output [4:0]\sysclksel_reg[1]_5 ;
  output gt_rxvalid_q_reg_6;
  output [2:0]\index_reg[1]_5 ;
  output D;
  output [2:0]\gt_rx_status_q_reg[2] ;
  output [2:0]\gt_rx_status_q_reg[2]_0 ;
  output [2:0]\gt_rx_status_q_reg[2]_1 ;
  output [2:0]\gt_rx_status_q_reg[2]_2 ;
  output [2:0]\gt_rx_status_q_reg[2]_3 ;
  output [2:0]\gt_rx_status_q_reg[2]_4 ;
  output [2:0]\gt_rx_status_q_reg[2]_5 ;
  output [2:0]\gt_rx_status_q_reg[2]_6 ;
  output pipe_rate_idle;
  output EQ_GEN3;
  output CLK_MMCM_LOCK;
  output CLK_USERCLK1;
  output [7:0]CLK_PCLK_SEL;
  output pipe_qrst_idle;
  output [7:0]gt_ch_drp_rdy;
  output [1:0]out;
  output [3:0]pipe_rst_fsm;
  output USER_RXPMARESET;
  output [7:0]gt_rx_phy_status_wire_filter;
  output \cplllock_reg1_reg[1] ;
  output \cplllock_reg1_reg[2] ;
  output \cplllock_reg1_reg[3]_1 ;
  output \cplllock_reg1_reg[4] ;
  output \cplllock_reg1_reg[5] ;
  output \cplllock_reg1_reg[6] ;
  output \cplllock_reg1_reg[7]_1 ;
  output [55:0]pipe_sync_fsm_rx;
  input sys_clk;
  input [7:0]pci_exp_rxn;
  input [7:0]pci_exp_rxp;
  input GT_RXPMARESET0;
  input [7:0]PIPE_RXPOLARITY;
  input [3:0]PIPE_TXDEEMPH;
  input \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ;
  input [7:0]PIPE_TXELECIDLE;
  input [7:0]pipe_txinhibit;
  input [15:0]PIPE_POWERDOWN;
  input [2:0]TXMARGIN;
  input [127:0]PIPE_TXDATA;
  input [7:0]PIPE_TXCOMPLIANCE;
  input [15:0]PIPE_TXDATAK;
  input GT_RXPMARESET089_out;
  input \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ;
  input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ;
  input GT_RXPMARESET0117_out;
  input GT_RXPMARESET071_out;
  input GT_RXPMARESET061_out;
  input PIPE_TXDETECTRX;
  input [2:0]PIPE_TXMARGIN;
  input GT_RXPMARESET043_out;
  input pipe_tx_rcvr_det;
  input [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  input GT_RXPMARESET032_out;
  input GT_RXPMARESET014_out;
  input gt_rxvalid_q_reg_7;
  input gt_rxvalid_q_reg_8;
  input gt_rxvalid_q_reg_9;
  input gt_rxvalid_q_reg_10;
  input gt_rxvalid_q_reg_11;
  input gt_rxvalid_q_reg_12;
  input gt_rxvalid_q_reg_13;
  input gt_rxvalid_q_reg_14;
  input [71:0]ext_ch_gt_drpaddr;
  input [1:0]Q;
  input \pl_ltssm_state_q_reg[4] ;
  input sys_rst_n;
  input [7:0]int_pclk_sel_slave;
  input pipe_mmcm_rst_n;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input [7:0]ext_ch_gt_drpen;
  input [7:0]ext_ch_gt_drpwe;
  input [127:0]ext_ch_gt_drpdi;

  wire CLK_DCLK;
  wire CLK_MMCM_LOCK;
  wire CLK_OOBCLK;
  wire [7:0]CLK_PCLK_SEL;
  wire CLK_USERCLK1;
  wire D;
  wire [2:0]DRP_FSM;
  wire DRP_START0;
  wire DRP_START0102_out;
  wire DRP_START0110_out;
  wire DRP_START0130_out;
  wire DRP_START025_out;
  wire DRP_START054_out;
  wire DRP_START082_out;
  wire DRP_START08_out;
  wire DRP_X160;
  wire DRP_X160104_out;
  wire DRP_X16010_out;
  wire DRP_X160112_out;
  wire DRP_X160132_out;
  wire DRP_X16027_out;
  wire DRP_X16056_out;
  wire DRP_X16084_out;
  wire DRP_X16X20_MODE0;
  wire DRP_X16X20_MODE0106_out;
  wire DRP_X16X20_MODE0114_out;
  wire DRP_X16X20_MODE0134_out;
  wire DRP_X16X20_MODE0136_out;
  wire DRP_X16X20_MODE029_out;
  wire DRP_X16X20_MODE058_out;
  wire DRP_X16X20_MODE086_out;
  wire EQ_GEN3;
  wire GT_RXPMARESET0;
  wire GT_RXPMARESET0117_out;
  wire GT_RXPMARESET014_out;
  wire GT_RXPMARESET032_out;
  wire GT_RXPMARESET043_out;
  wire GT_RXPMARESET061_out;
  wire GT_RXPMARESET071_out;
  wire GT_RXPMARESET089_out;
  wire GT_TXPMARESET0;
  wire GT_TXPMARESET0120_out;
  wire GT_TXPMARESET017_out;
  wire GT_TXPMARESET035_out;
  wire GT_TXPMARESET046_out;
  wire GT_TXPMARESET064_out;
  wire GT_TXPMARESET074_out;
  wire GT_TXPMARESET092_out;
  wire [15:0]PIPE_POWERDOWN;
  wire [7:0]PIPE_RXCHANISALIGNED;
  wire [15:0]PIPE_RXDATA;
  wire [1:0]PIPE_RXDATAK;
  wire [7:0]PIPE_RXPOLARITY;
  wire [7:0]PIPE_TXCOMPLIANCE;
  wire [127:0]PIPE_TXDATA;
  wire [15:0]PIPE_TXDATAK;
  wire [3:0]PIPE_TXDEEMPH;
  wire PIPE_TXDETECTRX;
  wire [7:0]PIPE_TXELECIDLE;
  wire [2:0]PIPE_TXMARGIN;
  wire [1:0]Q;
  wire [7:0]QRST_CPLLLOCK;
  wire [1:0]QRST_QPLLLOCK;
  wire [4:0]RATE_FSM;
  wire [5:0]SYNC_FSM_TX;
  wire SYNC_RXPHALIGNDONE_M;
  wire SYNC_TXSYNC_START0;
  wire SYNC_TXSYNC_START0100_out;
  wire SYNC_TXSYNC_START0108_out;
  wire SYNC_TXSYNC_START0128_out;
  wire SYNC_TXSYNC_START023_out;
  wire SYNC_TXSYNC_START052_out;
  wire SYNC_TXSYNC_START080_out;
  wire SYNC_TXSYNC_START098_out;
  wire [2:0]TXMARGIN;
  wire USER_RXPMARESET;
  wire \cplllock_reg1_reg[1] ;
  wire \cplllock_reg1_reg[2] ;
  wire \cplllock_reg1_reg[3] ;
  wire \cplllock_reg1_reg[3]_0 ;
  wire \cplllock_reg1_reg[3]_1 ;
  wire \cplllock_reg1_reg[4] ;
  wire \cplllock_reg1_reg[5] ;
  wire \cplllock_reg1_reg[6] ;
  wire \cplllock_reg1_reg[7] ;
  wire \cplllock_reg1_reg[7]_0 ;
  wire \cplllock_reg1_reg[7]_1 ;
  wire [71:0]ext_ch_gt_drpaddr;
  wire [127:0]ext_ch_gt_drpdi;
  wire [127:0]ext_ch_gt_drpdo;
  wire [7:0]ext_ch_gt_drpen;
  wire [7:0]ext_ch_gt_drprdy;
  wire [7:0]ext_ch_gt_drpwe;
  wire [7:0]gt_ch_drp_rdy;
  wire gt_cpllpdrefclk;
  wire [7:0]gt_rx_elec_idle_wire_filter;
  wire [7:0]gt_rx_phy_status_wire_filter;
  wire [2:0]\gt_rx_status_q_reg[2] ;
  wire [2:0]\gt_rx_status_q_reg[2]_0 ;
  wire [2:0]\gt_rx_status_q_reg[2]_1 ;
  wire [2:0]\gt_rx_status_q_reg[2]_2 ;
  wire [2:0]\gt_rx_status_q_reg[2]_3 ;
  wire [2:0]\gt_rx_status_q_reg[2]_4 ;
  wire [2:0]\gt_rx_status_q_reg[2]_5 ;
  wire [2:0]\gt_rx_status_q_reg[2]_6 ;
  wire [1:0]\gt_rxcharisk_q_reg[1] ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_0 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_1 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_2 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_3 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_4 ;
  wire [1:0]\gt_rxcharisk_q_reg[1]_5 ;
  wire [4:0]\gt_rxchbondo[1]_0 ;
  wire [15:0]\gt_rxdata_q_reg[15] ;
  wire [15:0]\gt_rxdata_q_reg[15]_0 ;
  wire [15:0]\gt_rxdata_q_reg[15]_1 ;
  wire [15:0]\gt_rxdata_q_reg[15]_2 ;
  wire [15:0]\gt_rxdata_q_reg[15]_3 ;
  wire [15:0]\gt_rxdata_q_reg[15]_4 ;
  wire [15:0]\gt_rxdata_q_reg[15]_5 ;
  wire gt_rxvalid_q_reg;
  wire gt_rxvalid_q_reg_0;
  wire gt_rxvalid_q_reg_1;
  wire gt_rxvalid_q_reg_10;
  wire gt_rxvalid_q_reg_11;
  wire gt_rxvalid_q_reg_12;
  wire gt_rxvalid_q_reg_13;
  wire gt_rxvalid_q_reg_14;
  wire gt_rxvalid_q_reg_2;
  wire gt_rxvalid_q_reg_3;
  wire gt_rxvalid_q_reg_4;
  wire gt_rxvalid_q_reg_5;
  wire gt_rxvalid_q_reg_6;
  wire gt_rxvalid_q_reg_7;
  wire gt_rxvalid_q_reg_8;
  wire gt_rxvalid_q_reg_9;
  wire [2:0]\index_reg[1] ;
  wire [2:0]\index_reg[1]_0 ;
  wire [2:0]\index_reg[1]_1 ;
  wire [2:0]\index_reg[1]_2 ;
  wire [2:0]\index_reg[1]_3 ;
  wire [2:0]\index_reg[1]_4 ;
  wire [2:0]\index_reg[1]_5 ;
  wire [7:0]int_pclk_sel_slave;
  wire [1:0]out;
  wire p_0_in121_in;
  wire p_0_in123_in;
  wire p_0_in18_in;
  wire p_0_in20_in;
  wire p_0_in2_in;
  wire p_0_in36_in;
  wire p_0_in38_in;
  wire p_0_in3_in;
  wire p_0_in47_in;
  wire p_0_in49_in;
  wire p_0_in65_in;
  wire p_0_in67_in;
  wire p_0_in75_in;
  wire p_0_in77_in;
  wire p_0_in7_in;
  wire p_0_in7_in_1;
  wire p_0_in7_in_11;
  wire p_0_in7_in_13;
  wire p_0_in7_in_15;
  wire p_0_in7_in_17;
  wire p_0_in7_in_4;
  wire p_0_in7_in_7;
  wire p_0_in93_in;
  wire p_0_in95_in;
  wire p_0_in__0;
  wire p_104_out;
  wire p_105_out;
  wire p_111_out;
  wire p_113_out;
  wire p_131_out;
  wire p_149_out;
  wire p_152_out;
  wire p_157_out;
  wire p_158_out;
  wire p_159_out;
  wire p_164_out;
  wire p_166_out;
  wire p_184_out;
  wire p_196_out;
  wire p_1_in8_in;
  wire p_1_in8_in_10;
  wire p_1_in8_in_12;
  wire p_1_in8_in_14;
  wire p_1_in8_in_18;
  wire p_1_in8_in_2;
  wire p_1_in8_in_5;
  wire p_1_in8_in_6;
  wire p_206_out;
  wire p_209_out;
  wire p_214_out;
  wire p_215_out;
  wire p_216_out;
  wire p_221_out;
  wire p_223_out;
  wire p_241_out;
  wire p_259_out;
  wire p_25_out;
  wire p_262_out;
  wire p_267_out;
  wire p_268_out;
  wire p_269_out;
  wire p_274_out;
  wire p_276_out;
  wire p_294_out;
  wire p_2_in;
  wire p_2_in_0;
  wire p_2_in_16;
  wire p_2_in_3;
  wire p_2_in_8;
  wire p_2_in_9;
  wire p_312_out;
  wire p_315_out;
  wire p_320_out;
  wire p_321_out;
  wire p_322_out;
  wire p_327_out;
  wire p_329_out;
  wire p_347_out;
  wire p_365_out;
  wire p_368_out;
  wire p_373_out;
  wire p_374_out;
  wire p_375_out;
  wire p_380_out;
  wire p_382_out;
  wire p_400_out;
  wire p_412_out;
  wire p_422_out;
  wire p_425_out;
  wire p_429_out;
  wire p_430_out;
  wire p_431_out;
  wire p_436_out;
  wire p_438_out;
  wire p_43_out;
  wire p_46_out;
  wire p_51_out;
  wire p_52_out;
  wire p_53_out;
  wire p_58_out;
  wire p_60_out;
  wire p_78_out;
  wire p_96_out;
  wire p_99_out;
  wire [7:0]pci_exp_rxn;
  wire [7:0]pci_exp_rxp;
  wire [7:0]pci_exp_txn;
  wire [7:0]pci_exp_txp;
  wire [63:0]pipe_dmonitorout;
  wire [7:0]pipe_eyescandataerror;
  wire \pipe_lane[0].gt_wrapper_i_n_14 ;
  wire \pipe_lane[0].gt_wrapper_i_n_15 ;
  wire \pipe_lane[0].gt_wrapper_i_n_16 ;
  wire \pipe_lane[0].gt_wrapper_i_n_21 ;
  wire \pipe_lane[0].gt_wrapper_i_n_22 ;
  wire \pipe_lane[0].gt_wrapper_i_n_6 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_10 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_11 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_12 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_13 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_15 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_16 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_17 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_18 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_19 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_20 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_21 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_22 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_23 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_24 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_25 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_26 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_27 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_28 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_29 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_3 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_30 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_4 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_5 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_6 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_7 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_8 ;
  wire \pipe_lane[0].pipe_drp.pipe_drp_i_n_9 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_0 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_1 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_10 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_11 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_12 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_13 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_14 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_15 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_16 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_17 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_2 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_3 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_4 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_5 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_6 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_7 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_8 ;
  wire \pipe_lane[0].pipe_eq.pipe_eq_i_n_9 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_12 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_14 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_15 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_16 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_17 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_18 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_19 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_20 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_5 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_6 ;
  wire \pipe_lane[0].pipe_rate.pipe_rate_i_n_7 ;
  wire \pipe_lane[0].pipe_sync_i_n_14 ;
  wire \pipe_lane[0].pipe_sync_i_n_15 ;
  wire \pipe_lane[0].pipe_sync_i_n_16 ;
  wire \pipe_lane[0].pipe_sync_i_n_17 ;
  wire \pipe_lane[0].pipe_sync_i_n_18 ;
  wire \pipe_lane[0].pipe_sync_i_n_19 ;
  wire \pipe_lane[0].pipe_sync_i_n_20 ;
  wire \pipe_lane[0].pipe_sync_i_n_21 ;
  wire \pipe_lane[0].pipe_user_i_n_0 ;
  wire \pipe_lane[0].pipe_user_i_n_10 ;
  wire \pipe_lane[0].pipe_user_i_n_11 ;
  wire \pipe_lane[0].pipe_user_i_n_16 ;
  wire \pipe_lane[0].pipe_user_i_n_17 ;
  wire \pipe_lane[0].pipe_user_i_n_5 ;
  wire \pipe_lane[0].pipe_user_i_n_6 ;
  wire \pipe_lane[0].pipe_user_i_n_7 ;
  wire \pipe_lane[0].pipe_user_i_n_8 ;
  wire \pipe_lane[0].pipe_user_i_n_9 ;
  wire \pipe_lane[1].gt_wrapper_i_n_14 ;
  wire \pipe_lane[1].gt_wrapper_i_n_15 ;
  wire \pipe_lane[1].gt_wrapper_i_n_16 ;
  wire \pipe_lane[1].gt_wrapper_i_n_20 ;
  wire \pipe_lane[1].gt_wrapper_i_n_21 ;
  wire \pipe_lane[1].gt_wrapper_i_n_6 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_10 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_11 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_12 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_13 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_15 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_16 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_17 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_18 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_19 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_20 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_21 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_22 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_23 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_24 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_25 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_26 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_27 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_28 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_29 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_3 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_30 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_4 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_5 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_6 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_7 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_8 ;
  wire \pipe_lane[1].pipe_drp.pipe_drp_i_n_9 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_0 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_1 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_10 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_11 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_12 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_13 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_14 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_15 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_16 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_17 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_2 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_3 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_4 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_5 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_6 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_7 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_8 ;
  wire \pipe_lane[1].pipe_eq.pipe_eq_i_n_9 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_12 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_14 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_15 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_16 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_17 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_18 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_19 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_20 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_5 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_6 ;
  wire \pipe_lane[1].pipe_rate.pipe_rate_i_n_7 ;
  wire \pipe_lane[1].pipe_sync_i_n_14 ;
  wire \pipe_lane[1].pipe_sync_i_n_15 ;
  wire \pipe_lane[1].pipe_sync_i_n_16 ;
  wire \pipe_lane[1].pipe_sync_i_n_17 ;
  wire \pipe_lane[1].pipe_sync_i_n_18 ;
  wire \pipe_lane[1].pipe_sync_i_n_19 ;
  wire \pipe_lane[1].pipe_sync_i_n_6 ;
  wire \pipe_lane[1].pipe_user_i_n_0 ;
  wire \pipe_lane[1].pipe_user_i_n_10 ;
  wire \pipe_lane[1].pipe_user_i_n_11 ;
  wire \pipe_lane[1].pipe_user_i_n_12 ;
  wire \pipe_lane[1].pipe_user_i_n_13 ;
  wire \pipe_lane[1].pipe_user_i_n_18 ;
  wire \pipe_lane[1].pipe_user_i_n_19 ;
  wire \pipe_lane[1].pipe_user_i_n_3 ;
  wire \pipe_lane[1].pipe_user_i_n_4 ;
  wire \pipe_lane[1].pipe_user_i_n_7 ;
  wire \pipe_lane[1].pipe_user_i_n_8 ;
  wire \pipe_lane[1].pipe_user_i_n_9 ;
  wire \pipe_lane[2].gt_wrapper_i_n_14 ;
  wire \pipe_lane[2].gt_wrapper_i_n_15 ;
  wire \pipe_lane[2].gt_wrapper_i_n_16 ;
  wire \pipe_lane[2].gt_wrapper_i_n_20 ;
  wire \pipe_lane[2].gt_wrapper_i_n_21 ;
  wire \pipe_lane[2].gt_wrapper_i_n_6 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_10 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_11 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_12 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_13 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_15 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_16 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_17 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_18 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_19 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_20 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_21 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_22 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_23 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_24 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_25 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_26 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_27 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_28 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_29 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_3 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_30 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_4 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_5 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_6 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_7 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_8 ;
  wire \pipe_lane[2].pipe_drp.pipe_drp_i_n_9 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_0 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_1 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_10 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_11 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_12 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_13 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_14 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_15 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_16 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_17 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_2 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_3 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_4 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_5 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_6 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_7 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_8 ;
  wire \pipe_lane[2].pipe_eq.pipe_eq_i_n_9 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_12 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_14 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_15 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_16 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_17 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_18 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_19 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_20 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_5 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_6 ;
  wire \pipe_lane[2].pipe_rate.pipe_rate_i_n_7 ;
  wire \pipe_lane[2].pipe_sync_i_n_14 ;
  wire \pipe_lane[2].pipe_sync_i_n_15 ;
  wire \pipe_lane[2].pipe_sync_i_n_16 ;
  wire \pipe_lane[2].pipe_sync_i_n_17 ;
  wire \pipe_lane[2].pipe_sync_i_n_18 ;
  wire \pipe_lane[2].pipe_sync_i_n_19 ;
  wire \pipe_lane[2].pipe_sync_i_n_6 ;
  wire \pipe_lane[2].pipe_user_i_n_0 ;
  wire \pipe_lane[2].pipe_user_i_n_10 ;
  wire \pipe_lane[2].pipe_user_i_n_11 ;
  wire \pipe_lane[2].pipe_user_i_n_12 ;
  wire \pipe_lane[2].pipe_user_i_n_13 ;
  wire \pipe_lane[2].pipe_user_i_n_18 ;
  wire \pipe_lane[2].pipe_user_i_n_19 ;
  wire \pipe_lane[2].pipe_user_i_n_3 ;
  wire \pipe_lane[2].pipe_user_i_n_4 ;
  wire \pipe_lane[2].pipe_user_i_n_7 ;
  wire \pipe_lane[2].pipe_user_i_n_8 ;
  wire \pipe_lane[2].pipe_user_i_n_9 ;
  wire \pipe_lane[3].gt_wrapper_i_n_14 ;
  wire \pipe_lane[3].gt_wrapper_i_n_15 ;
  wire \pipe_lane[3].gt_wrapper_i_n_16 ;
  wire \pipe_lane[3].gt_wrapper_i_n_20 ;
  wire \pipe_lane[3].gt_wrapper_i_n_21 ;
  wire \pipe_lane[3].gt_wrapper_i_n_6 ;
  wire \pipe_lane[3].gt_wrapper_i_n_86 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_10 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_11 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_12 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_13 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_15 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_16 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_17 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_18 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_19 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_20 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_21 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_22 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_23 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_24 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_25 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_26 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_27 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_28 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_29 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_3 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_30 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_4 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_5 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_6 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_7 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_8 ;
  wire \pipe_lane[3].pipe_drp.pipe_drp_i_n_9 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_0 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_1 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_10 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_11 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_12 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_13 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_14 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_15 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_16 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_17 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_2 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_3 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_4 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_5 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_6 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_7 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_8 ;
  wire \pipe_lane[3].pipe_eq.pipe_eq_i_n_9 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_12 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_14 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_15 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_16 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_17 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_18 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_19 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_20 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_5 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_6 ;
  wire \pipe_lane[3].pipe_rate.pipe_rate_i_n_7 ;
  wire \pipe_lane[3].pipe_sync_i_n_14 ;
  wire \pipe_lane[3].pipe_sync_i_n_15 ;
  wire \pipe_lane[3].pipe_sync_i_n_16 ;
  wire \pipe_lane[3].pipe_sync_i_n_17 ;
  wire \pipe_lane[3].pipe_sync_i_n_18 ;
  wire \pipe_lane[3].pipe_sync_i_n_19 ;
  wire \pipe_lane[3].pipe_sync_i_n_6 ;
  wire \pipe_lane[3].pipe_user_i_n_0 ;
  wire \pipe_lane[3].pipe_user_i_n_10 ;
  wire \pipe_lane[3].pipe_user_i_n_11 ;
  wire \pipe_lane[3].pipe_user_i_n_12 ;
  wire \pipe_lane[3].pipe_user_i_n_17 ;
  wire \pipe_lane[3].pipe_user_i_n_18 ;
  wire \pipe_lane[3].pipe_user_i_n_6 ;
  wire \pipe_lane[3].pipe_user_i_n_7 ;
  wire \pipe_lane[3].pipe_user_i_n_8 ;
  wire \pipe_lane[3].pipe_user_i_n_9 ;
  wire \pipe_lane[4].gt_wrapper_i_n_14 ;
  wire \pipe_lane[4].gt_wrapper_i_n_15 ;
  wire \pipe_lane[4].gt_wrapper_i_n_16 ;
  wire \pipe_lane[4].gt_wrapper_i_n_20 ;
  wire \pipe_lane[4].gt_wrapper_i_n_21 ;
  wire \pipe_lane[4].gt_wrapper_i_n_6 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_10 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_11 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_12 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_13 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_15 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_16 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_17 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_18 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_19 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_20 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_21 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_22 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_23 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_24 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_25 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_26 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_27 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_28 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_29 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_3 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_30 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_4 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_5 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_6 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_7 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_8 ;
  wire \pipe_lane[4].pipe_drp.pipe_drp_i_n_9 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_0 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_1 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_10 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_11 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_12 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_13 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_14 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_15 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_16 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_17 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_2 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_3 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_4 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_5 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_6 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_7 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_8 ;
  wire \pipe_lane[4].pipe_eq.pipe_eq_i_n_9 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_12 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_14 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_15 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_16 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_17 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_18 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_19 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_20 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_5 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_6 ;
  wire \pipe_lane[4].pipe_rate.pipe_rate_i_n_7 ;
  wire \pipe_lane[4].pipe_sync_i_n_14 ;
  wire \pipe_lane[4].pipe_sync_i_n_15 ;
  wire \pipe_lane[4].pipe_sync_i_n_16 ;
  wire \pipe_lane[4].pipe_sync_i_n_17 ;
  wire \pipe_lane[4].pipe_sync_i_n_18 ;
  wire \pipe_lane[4].pipe_sync_i_n_19 ;
  wire \pipe_lane[4].pipe_sync_i_n_6 ;
  wire \pipe_lane[4].pipe_user_i_n_0 ;
  wire \pipe_lane[4].pipe_user_i_n_10 ;
  wire \pipe_lane[4].pipe_user_i_n_11 ;
  wire \pipe_lane[4].pipe_user_i_n_12 ;
  wire \pipe_lane[4].pipe_user_i_n_17 ;
  wire \pipe_lane[4].pipe_user_i_n_18 ;
  wire \pipe_lane[4].pipe_user_i_n_3 ;
  wire \pipe_lane[4].pipe_user_i_n_6 ;
  wire \pipe_lane[4].pipe_user_i_n_7 ;
  wire \pipe_lane[4].pipe_user_i_n_8 ;
  wire \pipe_lane[4].pipe_user_i_n_9 ;
  wire \pipe_lane[5].gt_wrapper_i_n_14 ;
  wire \pipe_lane[5].gt_wrapper_i_n_15 ;
  wire \pipe_lane[5].gt_wrapper_i_n_16 ;
  wire \pipe_lane[5].gt_wrapper_i_n_20 ;
  wire \pipe_lane[5].gt_wrapper_i_n_21 ;
  wire \pipe_lane[5].gt_wrapper_i_n_6 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_10 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_11 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_12 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_13 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_15 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_16 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_17 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_18 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_19 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_20 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_21 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_22 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_23 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_24 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_25 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_26 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_27 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_28 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_29 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_3 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_30 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_4 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_5 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_6 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_7 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_8 ;
  wire \pipe_lane[5].pipe_drp.pipe_drp_i_n_9 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_0 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_1 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_10 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_11 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_12 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_13 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_14 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_15 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_16 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_17 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_2 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_3 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_4 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_5 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_6 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_7 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_8 ;
  wire \pipe_lane[5].pipe_eq.pipe_eq_i_n_9 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_12 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_14 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_15 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_16 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_17 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_18 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_19 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_20 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_5 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_6 ;
  wire \pipe_lane[5].pipe_rate.pipe_rate_i_n_7 ;
  wire \pipe_lane[5].pipe_sync_i_n_14 ;
  wire \pipe_lane[5].pipe_sync_i_n_15 ;
  wire \pipe_lane[5].pipe_sync_i_n_16 ;
  wire \pipe_lane[5].pipe_sync_i_n_17 ;
  wire \pipe_lane[5].pipe_sync_i_n_18 ;
  wire \pipe_lane[5].pipe_sync_i_n_19 ;
  wire \pipe_lane[5].pipe_sync_i_n_6 ;
  wire \pipe_lane[5].pipe_user_i_n_10 ;
  wire \pipe_lane[5].pipe_user_i_n_15 ;
  wire \pipe_lane[5].pipe_user_i_n_16 ;
  wire \pipe_lane[5].pipe_user_i_n_4 ;
  wire \pipe_lane[5].pipe_user_i_n_5 ;
  wire \pipe_lane[5].pipe_user_i_n_6 ;
  wire \pipe_lane[5].pipe_user_i_n_7 ;
  wire \pipe_lane[5].pipe_user_i_n_8 ;
  wire \pipe_lane[5].pipe_user_i_n_9 ;
  wire \pipe_lane[6].gt_wrapper_i_n_14 ;
  wire \pipe_lane[6].gt_wrapper_i_n_15 ;
  wire \pipe_lane[6].gt_wrapper_i_n_16 ;
  wire \pipe_lane[6].gt_wrapper_i_n_20 ;
  wire \pipe_lane[6].gt_wrapper_i_n_21 ;
  wire \pipe_lane[6].gt_wrapper_i_n_6 ;
  wire \pipe_lane[6].gt_wrapper_i_n_89 ;
  wire \pipe_lane[6].gt_wrapper_i_n_90 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_10 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_11 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_12 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_13 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_15 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_16 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_17 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_18 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_19 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_20 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_21 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_22 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_23 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_24 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_25 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_26 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_27 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_28 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_29 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_3 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_30 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_4 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_5 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_6 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_7 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_8 ;
  wire \pipe_lane[6].pipe_drp.pipe_drp_i_n_9 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_0 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_1 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_10 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_11 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_12 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_13 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_14 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_15 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_16 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_17 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_2 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_3 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_4 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_5 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_6 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_7 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_8 ;
  wire \pipe_lane[6].pipe_eq.pipe_eq_i_n_9 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_12 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_14 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_15 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_18 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_19 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_20 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_21 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_22 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_23 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_5 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_6 ;
  wire \pipe_lane[6].pipe_rate.pipe_rate_i_n_7 ;
  wire \pipe_lane[6].pipe_sync_i_n_14 ;
  wire \pipe_lane[6].pipe_sync_i_n_15 ;
  wire \pipe_lane[6].pipe_sync_i_n_16 ;
  wire \pipe_lane[6].pipe_sync_i_n_17 ;
  wire \pipe_lane[6].pipe_sync_i_n_18 ;
  wire \pipe_lane[6].pipe_sync_i_n_19 ;
  wire \pipe_lane[6].pipe_sync_i_n_6 ;
  wire \pipe_lane[6].pipe_user_i_n_10 ;
  wire \pipe_lane[6].pipe_user_i_n_11 ;
  wire \pipe_lane[6].pipe_user_i_n_12 ;
  wire \pipe_lane[6].pipe_user_i_n_13 ;
  wire \pipe_lane[6].pipe_user_i_n_14 ;
  wire \pipe_lane[6].pipe_user_i_n_15 ;
  wire \pipe_lane[6].pipe_user_i_n_19 ;
  wire \pipe_lane[6].pipe_user_i_n_20 ;
  wire \pipe_lane[6].pipe_user_i_n_3 ;
  wire \pipe_lane[6].pipe_user_i_n_4 ;
  wire \pipe_lane[6].pipe_user_i_n_5 ;
  wire \pipe_lane[6].pipe_user_i_n_6 ;
  wire \pipe_lane[6].pipe_user_i_n_9 ;
  wire \pipe_lane[7].gt_wrapper_i_n_14 ;
  wire \pipe_lane[7].gt_wrapper_i_n_15 ;
  wire \pipe_lane[7].gt_wrapper_i_n_16 ;
  wire \pipe_lane[7].gt_wrapper_i_n_20 ;
  wire \pipe_lane[7].gt_wrapper_i_n_21 ;
  wire \pipe_lane[7].gt_wrapper_i_n_6 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_10 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_11 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_12 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_13 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_15 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_16 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_17 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_18 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_19 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_20 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_21 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_22 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_23 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_24 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_25 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_26 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_27 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_28 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_29 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_3 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_30 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_4 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_5 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_6 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_7 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_8 ;
  wire \pipe_lane[7].pipe_drp.pipe_drp_i_n_9 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_0 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_1 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_10 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_11 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_12 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_13 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_14 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_15 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_16 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_17 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_2 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_3 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_4 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_5 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_6 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_7 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_8 ;
  wire \pipe_lane[7].pipe_eq.pipe_eq_i_n_9 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_12 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_14 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_15 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_16 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_17 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_18 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_19 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_20 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_5 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_6 ;
  wire \pipe_lane[7].pipe_rate.pipe_rate_i_n_7 ;
  wire \pipe_lane[7].pipe_sync_i_n_14 ;
  wire \pipe_lane[7].pipe_sync_i_n_15 ;
  wire \pipe_lane[7].pipe_sync_i_n_16 ;
  wire \pipe_lane[7].pipe_sync_i_n_17 ;
  wire \pipe_lane[7].pipe_sync_i_n_18 ;
  wire \pipe_lane[7].pipe_sync_i_n_19 ;
  wire \pipe_lane[7].pipe_sync_i_n_6 ;
  wire \pipe_lane[7].pipe_user_i_n_0 ;
  wire \pipe_lane[7].pipe_user_i_n_10 ;
  wire \pipe_lane[7].pipe_user_i_n_11 ;
  wire \pipe_lane[7].pipe_user_i_n_12 ;
  wire \pipe_lane[7].pipe_user_i_n_17 ;
  wire \pipe_lane[7].pipe_user_i_n_18 ;
  wire \pipe_lane[7].pipe_user_i_n_3 ;
  wire \pipe_lane[7].pipe_user_i_n_5 ;
  wire \pipe_lane[7].pipe_user_i_n_6 ;
  wire \pipe_lane[7].pipe_user_i_n_7 ;
  wire \pipe_lane[7].pipe_user_i_n_8 ;
  wire \pipe_lane[7].pipe_user_i_n_9 ;
  wire pipe_mmcm_rst_n;
  wire [3:0]pipe_qrst_fsm;
  wire pipe_qrst_idle;
  wire pipe_rate_idle;
  wire \pipe_reset.pipe_reset_i_n_17 ;
  wire \pipe_reset.pipe_reset_i_n_18 ;
  wire \pipe_reset.pipe_reset_i_n_19 ;
  wire \pipe_reset.pipe_reset_i_n_20 ;
  wire \pipe_reset.pipe_reset_i_n_21 ;
  wire \pipe_reset.pipe_reset_i_n_22 ;
  wire \pipe_reset.pipe_reset_i_n_23 ;
  wire \pipe_reset.pipe_reset_i_n_4 ;
  wire [3:0]pipe_rst_fsm;
  wire [23:0]pipe_rxbufstatus;
  wire [7:0]pipe_rxcommadet;
  wire [63:0]pipe_rxdisperr;
  wire [7:0]pipe_rxdlysresetdone;
  wire [63:0]pipe_rxnotintable;
  wire [7:0]pipe_rxoutclk_out;
  wire [6:0]pipe_rxphaligndone;
  wire [7:0]pipe_rxprbserr;
  wire [23:0]pipe_rxstatus;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2] ;
  wire [2:0]\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ;
  wire \pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ;
  wire [55:0]pipe_sync_fsm_rx;
  wire pipe_tx_rcvr_det;
  wire [7:0]pipe_txdlysresetdone;
  wire [7:0]pipe_txinhibit;
  wire pipe_txoutclk_out;
  wire [7:0]pipe_txphaligndone;
  wire [7:0]pipe_txphinitdone;
  wire \pl_ltssm_state_q_reg[4] ;
  wire \qpll_reset.qpll_reset_i_n_4 ;
  wire qpllpd;
  wire qrst_ovrd;
  wire qrst_qpllreset;
  wire [7:1]rate_gen3;
  wire [7:0]rate_idle;
  wire reset_n_reg1;
  wire reset_n_reg2;
  wire reset_n_reg2_reg_0;
  wire rst_cpllpd;
  wire rst_dclk_reset;
  wire rst_drp_start;
  wire rst_drp_x16;
  wire rst_drp_x16x20_mode;
  wire rst_gtreset;
  wire rst_rxusrclk_reset;
  wire rst_txsync_start;
  wire rst_userrdy;
  wire sys_clk;
  wire sys_rst_n;
  wire [4:0]\sysclksel_reg[1] ;
  wire [4:0]\sysclksel_reg[1]_0 ;
  wire [4:0]\sysclksel_reg[1]_1 ;
  wire [4:0]\sysclksel_reg[1]_2 ;
  wire [4:0]\sysclksel_reg[1]_3 ;
  wire [4:0]\sysclksel_reg[1]_4 ;
  wire [4:0]\sysclksel_reg[1]_5 ;
  wire [5:0]\txsync_fsm.txdlyen_reg ;
  wire [5:0]\txsync_fsm.txdlyen_reg_0 ;
  wire [5:0]\txsync_fsm.txdlyen_reg_1 ;
  wire [5:0]\txsync_fsm.txdlyen_reg_2 ;
  wire [5:0]\txsync_fsm.txdlyen_reg_3 ;
  wire [5:0]\txsync_fsm.txdlyen_reg_4 ;
  wire [5:0]\txsync_fsm.txdlyen_reg_5 ;
  wire txsyncallin;
  wire [5:0]user_active_lane;

  (* box_type = "PRIMITIVE" *) 
  BUFG cpllpd_refclk_inst
       (.I(sys_clk),
        .O(gt_cpllpdrefclk));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_clock \pipe_clock_int.pipe_clock_i 
       (.CLK_DCLK(CLK_DCLK),
        .CLK_MMCM_LOCK(CLK_MMCM_LOCK),
        .CLK_PCLK(CLK_OOBCLK),
        .CLK_USERCLK1(CLK_USERCLK1),
        .D(CLK_PCLK_SEL),
        .int_pclk_sel_slave(int_pclk_sel_slave),
        .pipe_mmcm_rst_n(pipe_mmcm_rst_n),
        .pipe_txoutclk_out(pipe_txoutclk_out),
        .rate_gen3(EQ_GEN3));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper \pipe_lane[0].gt_wrapper_i 
       (.CLK(CLK_DCLK),
        .DRPADDR({\pipe_lane[0].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[0].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_30 }),
        .DRP_GTXRESET(rst_gtreset),
        .GT_RXPMARESET0(GT_RXPMARESET0),
        .GT_TXPMARESET0(GT_TXPMARESET0),
        .O1671(\pipe_lane[0].pipe_rate.pipe_rate_i_n_12 ),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[1:0]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[0]),
        .PIPE_RXDATA(PIPE_RXDATA),
        .PIPE_RXDATAK(PIPE_RXDATAK),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[0]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[0]),
        .PIPE_TXDATA(PIPE_TXDATA[15:0]),
        .PIPE_TXDATAK(PIPE_TXDATAK[1:0]),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH[0]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[0]),
        .Q(Q),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[0]),
        .RATE_PHYSTATUS(p_400_out),
        .RATE_RXRATEDONE(\pipe_lane[0].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[0].gt_wrapper_i_n_21 ),
        .RST_CPLLRESET(p_0_in__0),
        .RXCHBONDO(\gt_rxchbondo[1]_0 ),
        .RXRATE({\pipe_lane[0].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[0].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[0].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[0].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[0].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXPHALIGNDONE_M(SYNC_RXPHALIGNDONE_M),
        .SYNC_RXSYNC_DONE(\pipe_lane[0].pipe_sync_i_n_15 ),
        .TXMAINCURSOR({\pipe_lane[0].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_11 }),
        .TXMARGIN(TXMARGIN),
        .TXPOSTCURSOR({\pipe_lane[0].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[0].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_4 }),
        .USER_EYESCANRESET(\pipe_lane[0].pipe_user_i_n_8 ),
        .USER_OOBCLK(\pipe_lane[0].pipe_user_i_n_5 ),
        .USER_RXBUFRESET(\pipe_lane[0].pipe_user_i_n_6 ),
        .USER_RXCDRFREQRESET(\pipe_lane[0].pipe_user_i_n_10 ),
        .USER_RXCDRRESET(\pipe_lane[0].pipe_user_i_n_11 ),
        .USER_RXDFELPMRESET(\pipe_lane[0].pipe_user_i_n_9 ),
        .USER_RXPCSRESET(\pipe_lane[0].pipe_user_i_n_7 ),
        .USER_RXRESETDONE(\pipe_lane[0].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[0].gt_wrapper_i_n_22 ),
        .converge_gen3_reg(\pipe_lane[6].pipe_user_i_n_4 ),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[15:0]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[0]),
        .\fsm_reg[0] (\pipe_lane[0].pipe_drp.pipe_drp_i_n_13 ),
        .\fsm_reg[2] (\pipe_lane[0].pipe_drp.pipe_drp_i_n_12 ),
        .gen3_reg(\pipe_lane[0].pipe_rate.pipe_rate_i_n_14 ),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[0]),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_6 ),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_7),
        .p_0_in2_in(p_0_in2_in),
        .p_0_in3_in(p_0_in3_in),
        .pci_exp_rxn(pci_exp_rxn[0]),
        .pci_exp_rxp(pci_exp_rxp[0]),
        .pci_exp_txn(pci_exp_txn[0]),
        .pci_exp_txp(pci_exp_txp[0]),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_dmonitorout(pipe_dmonitorout[7:0]),
        .pipe_eyescandataerror(pipe_eyescandataerror[0]),
        .pipe_rxbufstatus(pipe_rxbufstatus[2:0]),
        .pipe_rxcommadet(pipe_rxcommadet[0]),
        .pipe_rxdisperr(pipe_rxdisperr[7:0]),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone[0]),
        .pipe_rxnotintable(pipe_rxnotintable[7:0]),
        .pipe_rxoutclk_out(pipe_rxoutclk_out[0]),
        .pipe_rxprbserr(pipe_rxprbserr[0]),
        .pipe_rxstatus(pipe_rxstatus[2:0]),
        .\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 (\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ),
        .pipe_txdlysresetdone(pipe_txdlysresetdone[0]),
        .pipe_txinhibit(pipe_txinhibit[0]),
        .pipe_txoutclk_out(pipe_txoutclk_out),
        .pipe_txphaligndone(pipe_txphaligndone[0]),
        .pipe_txphinitdone(pipe_txphinitdone[0]),
        .\pl_ltssm_state_q_reg[4] (\pl_ltssm_state_q_reg[4] ),
        .qpllpd_reg(\cplllock_reg1_reg[3] ),
        .qpllpd_reg_0(\cplllock_reg1_reg[3]_0 ),
        .\resetovrd_disble.fsm_reg[1] (\pipe_lane[0].pipe_user_i_n_16 ),
        .rst_cpllpd(rst_cpllpd),
        .rxcdrlock_reg1_reg(\pipe_lane[0].gt_wrapper_i_n_6 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2] (\pipe_lane[0].pipe_sync_i_n_20 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2]_0 (\pipe_lane[0].pipe_sync_i_n_19 ),
        .rxvalid_reg1_reg(\pipe_lane[0].gt_wrapper_i_n_16 ),
        .sys_clk(sys_clk),
        .\txsync_fsm.fsm_tx_reg[2] (\pipe_lane[0].pipe_sync_i_n_16 ),
        .\txsync_fsm.fsm_tx_reg[4] (\pipe_lane[0].pipe_sync_i_n_18 ),
        .\txsync_fsm.fsm_tx_reg[4]_0 (\pipe_lane[0].pipe_sync_i_n_17 ),
        .\txsync_fsm.txdlyen_reg (\pipe_lane[0].pipe_sync_i_n_21 ),
        .userrdy_reg_rep__5(\pipe_reset.pipe_reset_i_n_23 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp \pipe_lane[0].pipe_drp.pipe_drp_i 
       (.DRPADDR({\pipe_lane[0].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[0].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[0].pipe_drp.pipe_drp_i_n_30 }),
        .DRP_DONE(p_422_out),
        .DRP_GTXRESET(rst_gtreset),
        .DRP_START(DRP_START0),
        .DRP_X16(DRP_X160),
        .DRP_X16X20_MODE(DRP_X16X20_MODE0),
        .Q(DRP_FSM),
        .RST_DCLK_RESET(rst_dclk_reset),
        .\cplllock_reg1_reg[0] (\pipe_lane[0].pipe_drp.pipe_drp_i_n_12 ),
        .\cplllock_reg1_reg[0]_0 (\pipe_lane[0].pipe_drp.pipe_drp_i_n_13 ),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr[8:0]),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi[15:0]),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[15:0]),
        .ext_ch_gt_drpen(ext_ch_gt_drpen[0]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[0]),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe[0]),
        .gt_ch_drp_rdy(gt_ch_drp_rdy[0]),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq \pipe_lane[0].pipe_eq.pipe_eq_i 
       (.CLK(CLK_OOBCLK),
        .RST_CPLLRESET(p_0_in__0),
        .TXMAINCURSOR({\pipe_lane[0].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[0].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[0].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[0].pipe_eq.pipe_eq_i_n_4 }),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[0].pipe_eq.pipe_eq_i_n_17 ),
        .rate_gen3(EQ_GEN3));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_common \pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i 
       (.DRP_DONE(p_412_out),
        .DRP_OVRD(qrst_ovrd),
        .DRP_START(\qpll_reset.qpll_reset_i_n_4 ),
        .O1687(\pipe_lane[6].pipe_rate.pipe_rate_i_n_14 ),
        .RATE_QPLLLOCK(QRST_QPLLLOCK[0]),
        .RST_DCLK_RESET(rst_dclk_reset),
        .\cplllock_reg1_reg[3] (\cplllock_reg1_reg[3] ),
        .\cplllock_reg1_reg[3]_0 (\cplllock_reg1_reg[3]_0 ),
        .qpllpd(qpllpd),
        .qrst_qpllreset(qrst_qpllreset),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .sys_clk(sys_clk));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate \pipe_lane[0].pipe_rate.pipe_rate_i 
       (.CLK(CLK_OOBCLK),
        .DRP_START0(DRP_START0),
        .DRP_X160(DRP_X160),
        .DRP_X16X20_MODE0(DRP_X16X20_MODE0),
        .GT_TXPMARESET0(GT_TXPMARESET0),
        .Q(RATE_FSM),
        .QRST_QPLLPD_IN(p_430_out),
        .QRST_QPLLRESET_IN(p_429_out),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[0]),
        .RATE_DRP_DONE(p_422_out),
        .RATE_MMCM_LOCK(CLK_MMCM_LOCK),
        .RATE_PHYSTATUS(p_400_out),
        .RATE_QPLLLOCK(QRST_QPLLLOCK[0]),
        .RATE_RESETOVRD_DONE(\pipe_lane[0].pipe_user_i_n_17 ),
        .RATE_RXRATEDONE(\pipe_lane[0].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[0].gt_wrapper_i_n_21 ),
        .RATE_TXSYNC_DONE(p_425_out),
        .RST_CPLLRESET(p_0_in__0),
        .RST_DRP_START(rst_drp_start),
        .RST_DRP_X16(rst_drp_x16),
        .RST_DRP_X16X20_MODE(rst_drp_x16x20_mode),
        .RST_RATE_IDLE(rate_idle[0]),
        .RXRATE({\pipe_lane[0].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[0].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[0].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[0].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[0].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[0].pipe_sync_i_n_15 ),
        .SYNC_RXSYNC_START(\pipe_lane[0].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START098_out),
        .USER_PCLK_SEL(CLK_PCLK_SEL[0]),
        .USER_RATE_DONE(\pipe_lane[0].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[0].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[0].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXRESETDONE(\pipe_lane[0].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[0].gt_wrapper_i_n_22 ),
        .\cplllock_reg1_reg[0] (\pipe_lane[0].pipe_rate.pipe_rate_i_n_12 ),
        .\cplllock_reg1_reg[0]_0 (\pipe_lane[0].pipe_rate.pipe_rate_i_n_14 ),
        .out1({out[0],rst_txsync_start}),
        .p_0_in2_in(p_0_in2_in),
        .p_0_in3_in(p_0_in3_in),
        .p_0_in7_in(p_0_in7_in),
        .p_1_in8_in(p_1_in8_in),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .rate_gen3(EQ_GEN3));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync \pipe_lane[0].pipe_sync_i 
       (.Q(SYNC_FSM_TX),
        .RATE_MMCM_LOCK(CLK_MMCM_LOCK),
        .RST_CPLLRESET(p_0_in__0),
        .RST_RATE_IDLE(rate_idle[0]),
        .RST_TXSYNC_DONE(p_425_out),
        .SYNC_RXCDRLOCK(p_436_out),
        .SYNC_RXDLYEN(\pipe_lane[0].pipe_sync_i_n_15 ),
        .SYNC_RXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_90 ),
        .SYNC_RXPHALIGNDONE_M(SYNC_RXPHALIGNDONE_M),
        .SYNC_RXPHALIGNDONE_S(\pipe_lane[3].gt_wrapper_i_n_86 ),
        .SYNC_RXSYNC_DONEM_IN(\pipe_lane[0].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[0].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_89 ),
        .SYNC_TXPHALIGNDONE(txsyncallin),
        .SYNC_TXPHINITDONE(\pipe_lane[4].pipe_user_i_n_0 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START098_out),
        .\cplllock_reg1_reg[0] (\pipe_lane[0].pipe_sync_i_n_16 ),
        .\cplllock_reg1_reg[0]_0 (\pipe_lane[0].pipe_sync_i_n_17 ),
        .\cplllock_reg1_reg[0]_1 (\pipe_lane[0].pipe_sync_i_n_18 ),
        .\cplllock_reg1_reg[0]_2 (\pipe_lane[0].pipe_sync_i_n_19 ),
        .\cplllock_reg1_reg[0]_3 (\pipe_lane[0].pipe_sync_i_n_20 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[0]),
        .p_0_in7_in(p_0_in7_in),
        .p_1_in8_in(p_1_in8_in),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx[6:0]),
        .rate_gen3(EQ_GEN3),
        .\txsync_fsm.txdlyen_reg_0 (\pipe_lane[0].pipe_sync_i_n_21 ),
        .user_active_lane(user_active_lane[0]));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_user \pipe_lane[0].pipe_user_i 
       (.CLK_PCLK_SEL(CLK_PCLK_SEL[0]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[0]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[0]),
        .Q({\pipe_lane[0].pipe_user_i_n_6 ,\pipe_lane[0].pipe_user_i_n_7 ,\pipe_lane[0].pipe_user_i_n_8 ,\pipe_lane[0].pipe_user_i_n_9 ,\pipe_lane[0].pipe_user_i_n_10 ,\pipe_lane[0].pipe_user_i_n_11 ,USER_RXPMARESET}),
        .RST_CPLLRESET(p_0_in__0),
        .RST_PHYSTATUS(p_400_out),
        .RST_RATE_IDLE(rate_idle[0]),
        .RST_RESETDONE(p_438_out),
        .RST_RXCDRLOCK(p_436_out),
        .RST_RXUSRCLK_RESET(rst_rxusrclk_reset),
        .USER_OOBCLK(\pipe_lane[0].pipe_user_i_n_5 ),
        .USER_RATE_DONE(\pipe_lane[0].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[0].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[0].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[0].pipe_eq.pipe_eq_i_n_17 ),
        .USER_RXRESETDONE(\pipe_lane[0].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[0].gt_wrapper_i_n_22 ),
        .\cplllock_reg1_reg[0] (\pipe_lane[0].pipe_user_i_n_16 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[0]),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[0]),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg),
        .gt_rxvalid_q_reg_0(gt_rxvalid_q_reg_7),
        .out1(out[0]),
        .p_0_in7_in(p_0_in7_in),
        .p_0_in7_in_1(p_0_in7_in_1),
        .p_1_in8_in(p_1_in8_in),
        .p_1_in8_in_0(p_1_in8_in_2),
        .p_2_in(p_2_in),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_rxstatus(pipe_rxstatus[2]),
        .pipe_txphinitdone(pipe_txphinitdone[1]),
        .rate_gen3(EQ_GEN3),
        .\resetovrd_disble.reset_reg[4]_0 (\pipe_lane[0].gt_wrapper_i_n_16 ),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[0].gt_wrapper_i_n_6 ),
        .resetovrd_done_reg1_reg(\pipe_lane[0].pipe_user_i_n_17 ),
        .txelecidle_reg2_reg_0(\pipe_lane[2].pipe_user_i_n_4 ),
        .txphinitdone_reg1_reg(\pipe_lane[0].pipe_user_i_n_0 ),
        .user_active_lane(user_active_lane[0]),
        .user_rx_converge(p_431_out));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_29 \pipe_lane[1].gt_wrapper_i 
       (.DRPADDR({\pipe_lane[1].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[1].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_30 }),
        .GT_RXPMARESET089_out(GT_RXPMARESET089_out),
        .GT_TXPMARESET092_out(GT_TXPMARESET092_out),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[3:2]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[1]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[1]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[1]),
        .PIPE_TXDATA(PIPE_TXDATA[31:16]),
        .PIPE_TXDATAK(PIPE_TXDATAK[3:2]),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH[0]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[1]),
        .Q(Q),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[1]),
        .RATE_PHYSTATUS(p_347_out),
        .RATE_RXRATEDONE(\pipe_lane[1].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[1].gt_wrapper_i_n_20 ),
        .RST_CPLLRESET(p_0_in__0),
        .RXCHBONDO(\gt_rxchbondo[1]_0 ),
        .RXRATE({\pipe_lane[1].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[1].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[1].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[1].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[1].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[1].pipe_sync_i_n_14 ),
        .TXMAINCURSOR({\pipe_lane[1].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[1].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[1].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_4 }),
        .USER_EYESCANRESET(\pipe_lane[1].pipe_user_i_n_10 ),
        .USER_OOBCLK(\pipe_lane[1].pipe_user_i_n_7 ),
        .USER_RXBUFRESET(\pipe_lane[1].pipe_user_i_n_8 ),
        .USER_RXCDRFREQRESET(\pipe_lane[1].pipe_user_i_n_12 ),
        .USER_RXCDRRESET(\pipe_lane[1].pipe_user_i_n_13 ),
        .USER_RXDFELPMRESET(\pipe_lane[1].pipe_user_i_n_11 ),
        .USER_RXPCSRESET(\pipe_lane[1].pipe_user_i_n_9 ),
        .USER_RXRESETDONE(\pipe_lane[1].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[1].gt_wrapper_i_n_21 ),
        .converge_gen3_reg(\pipe_lane[6].pipe_user_i_n_5 ),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[31:16]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[1]),
        .\fsm_reg[0] (\pipe_lane[1].pipe_drp.pipe_drp_i_n_13 ),
        .\fsm_reg[2] (\pipe_lane[1].pipe_drp.pipe_drp_i_n_12 ),
        .gen3_reg(\pipe_lane[1].pipe_rate.pipe_rate_i_n_14 ),
        .gen3_reg_0(\pipe_lane[1].pipe_rate.pipe_rate_i_n_12 ),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[1]),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_5 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1] ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15] ),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_8),
        .p_0_in93_in(p_0_in93_in),
        .p_0_in95_in(p_0_in95_in),
        .pci_exp_rxn(pci_exp_rxn[1]),
        .pci_exp_rxp(pci_exp_rxp[1]),
        .pci_exp_txn(pci_exp_txn[1]),
        .pci_exp_txp(pci_exp_txp[1]),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_dmonitorout(pipe_dmonitorout[15:8]),
        .pipe_eyescandataerror(pipe_eyescandataerror[1]),
        .pipe_rxbufstatus(pipe_rxbufstatus[5:3]),
        .pipe_rxcommadet(pipe_rxcommadet[1]),
        .pipe_rxdisperr(pipe_rxdisperr[15:8]),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone[1]),
        .pipe_rxnotintable(pipe_rxnotintable[15:8]),
        .pipe_rxoutclk_out(pipe_rxoutclk_out[1]),
        .pipe_rxphaligndone(pipe_rxphaligndone[0]),
        .pipe_rxprbserr(pipe_rxprbserr[1]),
        .pipe_rxstatus(pipe_rxstatus[5:3]),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep (\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ),
        .\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep (\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ),
        .pipe_txdlysresetdone(pipe_txdlysresetdone[1]),
        .pipe_txinhibit(pipe_txinhibit[1]),
        .pipe_txphaligndone(pipe_txphaligndone[1]),
        .pipe_txphinitdone(pipe_txphinitdone[1]),
        .\pl_ltssm_state_q_reg[4] (\pl_ltssm_state_q_reg[4] ),
        .qpllpd_reg(\cplllock_reg1_reg[3] ),
        .qpllpd_reg_0(\cplllock_reg1_reg[3]_0 ),
        .\resetovrd_disble.fsm_reg[1] (\pipe_lane[1].pipe_user_i_n_18 ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_cpllpd(rst_cpllpd),
        .rst_gtreset(rst_gtreset),
        .rxcdrlock_reg1_reg(\pipe_lane[1].gt_wrapper_i_n_6 ),
        .rxsync_donem_reg2_reg(\pipe_lane[1].pipe_sync_i_n_18 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2] (\pipe_lane[1].pipe_sync_i_n_19 ),
        .rxvalid_reg1_reg(\pipe_lane[1].gt_wrapper_i_n_16 ),
        .sys_clk(sys_clk),
        .\txsync_fsm.fsm_tx_reg[2] (\pipe_lane[1].pipe_sync_i_n_15 ),
        .\txsync_fsm.fsm_tx_reg[4] (\pipe_lane[1].pipe_sync_i_n_17 ),
        .\txsync_fsm.fsm_tx_reg[4]_0 (\pipe_lane[1].pipe_sync_i_n_16 ),
        .\txsync_fsm.txdlyen_reg (\pipe_lane[1].pipe_sync_i_n_6 ),
        .userrdy_reg_rep__4(\pipe_reset.pipe_reset_i_n_22 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_30 \pipe_lane[1].pipe_drp.pipe_drp_i 
       (.DRPADDR({\pipe_lane[1].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[1].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[1].pipe_drp.pipe_drp_i_n_30 }),
        .DRP_DONE(p_365_out),
        .DRP_START(DRP_START0102_out),
        .DRP_X16(DRP_X160104_out),
        .DRP_X16X20_MODE(DRP_X16X20_MODE0106_out),
        .Q(\index_reg[1] ),
        .RST_DCLK_RESET(rst_dclk_reset),
        .\cplllock_reg1_reg[1] (\pipe_lane[1].pipe_drp.pipe_drp_i_n_12 ),
        .\cplllock_reg1_reg[1]_0 (\pipe_lane[1].pipe_drp.pipe_drp_i_n_13 ),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr[17:9]),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi[31:16]),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[31:16]),
        .ext_ch_gt_drpen(ext_ch_gt_drpen[1]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[1]),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe[1]),
        .gt_ch_drp_rdy(gt_ch_drp_rdy[1]),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_gtreset(rst_gtreset));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_31 \pipe_lane[1].pipe_eq.pipe_eq_i 
       (.RST_CPLLRESET(p_0_in__0),
        .TXMAINCURSOR({\pipe_lane[1].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[1].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[1].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[1].pipe_eq.pipe_eq_i_n_4 }),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[1].pipe_eq.pipe_eq_i_n_17 ),
        .pclk_sel_reg(CLK_OOBCLK),
        .rate_gen3(rate_gen3[1]));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_32 \pipe_lane[1].pipe_rate.pipe_rate_i 
       (.DRP_START0102_out(DRP_START0102_out),
        .DRP_X160104_out(DRP_X160104_out),
        .DRP_X16X20_MODE0106_out(DRP_X16X20_MODE0106_out),
        .GT_TXPMARESET092_out(GT_TXPMARESET092_out),
        .Q(\sysclksel_reg[1] ),
        .QRST_QPLLPD_IN(p_374_out),
        .QRST_QPLLRESET_IN(p_373_out),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[1]),
        .RATE_DRP_DONE(p_365_out),
        .RATE_MMCM_LOCK(CLK_MMCM_LOCK),
        .RATE_PHYSTATUS(p_347_out),
        .RATE_QPLLLOCK(QRST_QPLLLOCK[0]),
        .RATE_RESETOVRD_DONE(\pipe_lane[1].pipe_user_i_n_19 ),
        .RATE_RXRATEDONE(\pipe_lane[1].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[1].gt_wrapper_i_n_20 ),
        .RATE_TXSYNC_DONE(p_368_out),
        .RST_CPLLRESET(p_0_in__0),
        .RST_DRP_START(rst_drp_start),
        .RST_DRP_X16(rst_drp_x16),
        .RST_DRP_X16X20_MODE(rst_drp_x16x20_mode),
        .RST_RATE_IDLE(rate_idle[1]),
        .RXRATE({\pipe_lane[1].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[1].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[1].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[1].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[1].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[1].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[1].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START0100_out),
        .USER_PCLK_SEL(CLK_PCLK_SEL[1]),
        .USER_RATE_DONE(\pipe_lane[1].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[1].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[1].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXRESETDONE(\pipe_lane[1].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[1].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[1] (\pipe_lane[1].pipe_rate.pipe_rate_i_n_12 ),
        .\cplllock_reg1_reg[1]_0 (\pipe_lane[1].pipe_rate.pipe_rate_i_n_14 ),
        .out1({out[0],rst_txsync_start}),
        .p_0_in7_in(p_0_in7_in_1),
        .p_0_in93_in(p_0_in93_in),
        .p_0_in95_in(p_0_in95_in),
        .p_1_in8_in(p_1_in8_in_2),
        .pclk_sel_reg_0(CLK_OOBCLK),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .rate_gen3(rate_gen3[1]));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_33 \pipe_lane[1].pipe_sync_i 
       (.Q(\txsync_fsm.txdlyen_reg ),
        .RST_CPLLRESET(p_0_in__0),
        .RST_RATE_IDLE(rate_idle[1]),
        .RST_TXSYNC_DONE(p_368_out),
        .SYNC_GEN3(rate_gen3[1]),
        .SYNC_RXCDRLOCK(p_380_out),
        .SYNC_RXDLYEN(\pipe_lane[1].pipe_sync_i_n_14 ),
        .SYNC_RXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_90 ),
        .SYNC_RXPHALIGNDONE_M(SYNC_RXPHALIGNDONE_M),
        .SYNC_RXPHALIGNDONE_S(\pipe_lane[3].gt_wrapper_i_n_86 ),
        .SYNC_RXSYNC_DONEM_IN(\pipe_lane[0].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[1].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_89 ),
        .SYNC_TXPHALIGNDONE(txsyncallin),
        .SYNC_TXPHINITDONE(\pipe_lane[4].pipe_user_i_n_0 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START0100_out),
        .\cplllock_reg1_reg[1] (\pipe_lane[1].pipe_sync_i_n_15 ),
        .\cplllock_reg1_reg[1]_0 (\pipe_lane[1].pipe_sync_i_n_16 ),
        .\cplllock_reg1_reg[1]_1 (\pipe_lane[1].pipe_sync_i_n_17 ),
        .\cplllock_reg1_reg[1]_2 (\pipe_lane[1].pipe_sync_i_n_18 ),
        .\cplllock_reg1_reg[1]_3 (\pipe_lane[1].pipe_sync_i_n_19 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[1]),
        .p_0_in7_in(p_0_in7_in_1),
        .p_1_in8_in(p_1_in8_in_2),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx[13:7]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK),
        .\txsync_fsm.txdlyen_reg_0 (\pipe_lane[1].pipe_sync_i_n_6 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_34 \pipe_lane[1].pipe_user_i 
       (.CLK_PCLK_SEL(CLK_PCLK_SEL[1]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[1]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[1]),
        .Q({\pipe_lane[1].pipe_user_i_n_8 ,\pipe_lane[1].pipe_user_i_n_9 ,\pipe_lane[1].pipe_user_i_n_10 ,\pipe_lane[1].pipe_user_i_n_11 ,\pipe_lane[1].pipe_user_i_n_12 ,\pipe_lane[1].pipe_user_i_n_13 ,\cplllock_reg1_reg[1] }),
        .RST_CPLLRESET(p_0_in__0),
        .RST_PHYSTATUS(p_347_out),
        .RST_RATE_IDLE(rate_idle[1]),
        .RST_RESETDONE(p_382_out),
        .RST_RXCDRLOCK(p_380_out),
        .RST_RXUSRCLK_RESET(rst_rxusrclk_reset),
        .USER_OOBCLK(\pipe_lane[1].pipe_user_i_n_7 ),
        .USER_RATE_DONE(\pipe_lane[1].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[1].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[1].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[1].pipe_eq.pipe_eq_i_n_17 ),
        .USER_RXRESETDONE(\pipe_lane[1].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[1].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[1] (\pipe_lane[1].pipe_user_i_n_18 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[1]),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[1]),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_0),
        .gt_rxvalid_q_reg_0(gt_rxvalid_q_reg_8),
        .out1(out[0]),
        .p_0_in7_in(p_0_in7_in_1),
        .p_0_in7_in_1(p_0_in7_in_7),
        .p_1_in8_in(p_1_in8_in_2),
        .p_1_in8_in_0(p_1_in8_in_6),
        .p_2_in(p_2_in_0),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_rxstatus(pipe_rxstatus[5]),
        .pipe_txphaligndone({pipe_txphaligndone[3],pipe_txphaligndone[1]}),
        .pipe_txphinitdone({pipe_txphinitdone[3],pipe_txphinitdone[1]}),
        .rate_gen3(rate_gen3[1]),
        .\resetovrd_disble.reset_reg[4]_0 (\pipe_lane[1].gt_wrapper_i_n_16 ),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[1].gt_wrapper_i_n_6 ),
        .resetovrd_done_reg1_reg(\pipe_lane[1].pipe_user_i_n_19 ),
        .txelecidle_reg2_reg_0(\pipe_lane[2].pipe_user_i_n_0 ),
        .txphaligndone_reg1_reg(\pipe_lane[1].pipe_user_i_n_0 ),
        .txphaligndone_reg1_reg_0(\pipe_lane[1].pipe_user_i_n_3 ),
        .txphinitdone_reg1_reg(\pipe_lane[1].pipe_user_i_n_4 ),
        .user_active_lane(user_active_lane[3]),
        .user_rx_converge(p_375_out));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_35 \pipe_lane[2].gt_wrapper_i 
       (.DRPADDR({\pipe_lane[2].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[2].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_30 }),
        .GT_RXPMARESET0117_out(GT_RXPMARESET0117_out),
        .GT_TXPMARESET0120_out(GT_TXPMARESET0120_out),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[5:4]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[2]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[2]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[2]),
        .PIPE_TXDATA(PIPE_TXDATA[47:32]),
        .PIPE_TXDATAK(PIPE_TXDATAK[5:4]),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH[1]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[2]),
        .Q(Q),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[2]),
        .RATE_PHYSTATUS(p_294_out),
        .RATE_RXRATEDONE(\pipe_lane[2].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[2].gt_wrapper_i_n_20 ),
        .RST_CPLLRESET(p_0_in__0),
        .RXCHBONDO(\gt_rxchbondo[1]_0 ),
        .RXRATE({\pipe_lane[2].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[2].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[2].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[2].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[2].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[2].pipe_sync_i_n_14 ),
        .TXMAINCURSOR({\pipe_lane[2].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_11 }),
        .TXMARGIN(TXMARGIN),
        .TXPOSTCURSOR({\pipe_lane[2].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[2].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_4 }),
        .USER_EYESCANRESET(\pipe_lane[2].pipe_user_i_n_10 ),
        .USER_OOBCLK(\pipe_lane[2].pipe_user_i_n_7 ),
        .USER_RXBUFRESET(\pipe_lane[2].pipe_user_i_n_8 ),
        .USER_RXCDRFREQRESET(\pipe_lane[2].pipe_user_i_n_12 ),
        .USER_RXCDRRESET(\pipe_lane[2].pipe_user_i_n_13 ),
        .USER_RXDFELPMRESET(\pipe_lane[2].pipe_user_i_n_11 ),
        .USER_RXPCSRESET(\pipe_lane[2].pipe_user_i_n_9 ),
        .USER_RXRESETDONE(\pipe_lane[2].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[2].gt_wrapper_i_n_21 ),
        .converge_gen3_reg(\pipe_lane[6].pipe_user_i_n_4 ),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[47:32]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[2]),
        .\fsm_reg[0] (\pipe_lane[2].pipe_drp.pipe_drp_i_n_13 ),
        .\fsm_reg[2] (\pipe_lane[2].pipe_drp.pipe_drp_i_n_12 ),
        .gen3_reg(\pipe_lane[2].pipe_rate.pipe_rate_i_n_14 ),
        .gen3_reg_0(\pipe_lane[2].pipe_rate.pipe_rate_i_n_12 ),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[2]),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_4 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_0 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_0 ),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_9),
        .p_0_in121_in(p_0_in121_in),
        .p_0_in123_in(p_0_in123_in),
        .pci_exp_rxn(pci_exp_rxn[2]),
        .pci_exp_rxp(pci_exp_rxp[2]),
        .pci_exp_txn(pci_exp_txn[2]),
        .pci_exp_txp(pci_exp_txp[2]),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_dmonitorout(pipe_dmonitorout[23:16]),
        .pipe_eyescandataerror(pipe_eyescandataerror[2]),
        .pipe_rxbufstatus(pipe_rxbufstatus[8:6]),
        .pipe_rxcommadet(pipe_rxcommadet[2]),
        .pipe_rxdisperr(pipe_rxdisperr[23:16]),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone[2]),
        .pipe_rxnotintable(pipe_rxnotintable[23:16]),
        .pipe_rxoutclk_out(pipe_rxoutclk_out[2]),
        .pipe_rxphaligndone(pipe_rxphaligndone[1]),
        .pipe_rxprbserr(pipe_rxprbserr[2]),
        .pipe_rxstatus(pipe_rxstatus[8:6]),
        .\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 (\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep__0 ),
        .pipe_txdlysresetdone(pipe_txdlysresetdone[2]),
        .pipe_txinhibit(pipe_txinhibit[2]),
        .pipe_txphaligndone(pipe_txphaligndone[2]),
        .pipe_txphinitdone(pipe_txphinitdone[2]),
        .\pl_ltssm_state_q_reg[4] (\pl_ltssm_state_q_reg[4] ),
        .qpllpd_reg(\cplllock_reg1_reg[3] ),
        .qpllpd_reg_0(\cplllock_reg1_reg[3]_0 ),
        .\resetovrd_disble.fsm_reg[1] (\pipe_lane[2].pipe_user_i_n_18 ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_cpllpd(rst_cpllpd),
        .rst_gtreset(rst_gtreset),
        .rxcdrlock_reg1_reg(\pipe_lane[2].gt_wrapper_i_n_6 ),
        .rxsync_donem_reg2_reg(\pipe_lane[2].pipe_sync_i_n_18 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2] (\pipe_lane[2].pipe_sync_i_n_19 ),
        .rxvalid_reg1_reg(\pipe_lane[2].gt_wrapper_i_n_16 ),
        .sys_clk(sys_clk),
        .\txsync_fsm.fsm_tx_reg[2] (\pipe_lane[2].pipe_sync_i_n_15 ),
        .\txsync_fsm.fsm_tx_reg[4] (\pipe_lane[2].pipe_sync_i_n_17 ),
        .\txsync_fsm.fsm_tx_reg[4]_0 (\pipe_lane[2].pipe_sync_i_n_16 ),
        .\txsync_fsm.txdlyen_reg (\pipe_lane[2].pipe_sync_i_n_6 ),
        .userrdy_reg_rep__3(\pipe_reset.pipe_reset_i_n_21 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_36 \pipe_lane[2].pipe_drp.pipe_drp_i 
       (.DRPADDR({\pipe_lane[2].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[2].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[2].pipe_drp.pipe_drp_i_n_30 }),
        .DRP_DONE(p_312_out),
        .DRP_START(DRP_START0110_out),
        .DRP_X16(DRP_X160112_out),
        .DRP_X16X20_MODE(DRP_X16X20_MODE0114_out),
        .Q(\index_reg[1]_0 ),
        .RST_DCLK_RESET(rst_dclk_reset),
        .\cplllock_reg1_reg[2] (\pipe_lane[2].pipe_drp.pipe_drp_i_n_12 ),
        .\cplllock_reg1_reg[2]_0 (\pipe_lane[2].pipe_drp.pipe_drp_i_n_13 ),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr[26:18]),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi[47:32]),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[47:32]),
        .ext_ch_gt_drpen(ext_ch_gt_drpen[2]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[2]),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe[2]),
        .gt_ch_drp_rdy(gt_ch_drp_rdy[2]),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_gtreset(rst_gtreset));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_37 \pipe_lane[2].pipe_eq.pipe_eq_i 
       (.RST_CPLLRESET(p_0_in__0),
        .TXMAINCURSOR({\pipe_lane[2].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[2].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[2].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[2].pipe_eq.pipe_eq_i_n_4 }),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[2].pipe_eq.pipe_eq_i_n_17 ),
        .pclk_sel_reg(CLK_OOBCLK),
        .rate_gen3(rate_gen3[2]));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_38 \pipe_lane[2].pipe_rate.pipe_rate_i 
       (.DRP_START0110_out(DRP_START0110_out),
        .DRP_X160112_out(DRP_X160112_out),
        .DRP_X16X20_MODE0114_out(DRP_X16X20_MODE0114_out),
        .GT_TXPMARESET0120_out(GT_TXPMARESET0120_out),
        .Q(\sysclksel_reg[1]_0 ),
        .QRST_QPLLPD_IN(p_321_out),
        .QRST_QPLLRESET_IN(p_320_out),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[2]),
        .RATE_DRP_DONE(p_312_out),
        .RATE_PHYSTATUS(p_294_out),
        .RATE_QPLLLOCK(QRST_QPLLLOCK[0]),
        .RATE_RESETOVRD_DONE(\pipe_lane[2].pipe_user_i_n_19 ),
        .RATE_RXRATEDONE(\pipe_lane[2].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[2].gt_wrapper_i_n_20 ),
        .RATE_TXSYNC_DONE(p_315_out),
        .RST_CPLLRESET(p_0_in__0),
        .RST_DRP_START(rst_drp_start),
        .RST_DRP_X16(rst_drp_x16),
        .RST_DRP_X16X20_MODE(rst_drp_x16x20_mode),
        .RST_RATE_IDLE(rate_idle[2]),
        .RXRATE({\pipe_lane[2].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[2].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[2].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[2].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[2].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[2].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[2].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START0108_out),
        .USER_PCLK_SEL(CLK_PCLK_SEL[2]),
        .USER_RATE_DONE(\pipe_lane[2].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[2].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[2].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXRESETDONE(\pipe_lane[2].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[2].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[2] (\pipe_lane[2].pipe_rate.pipe_rate_i_n_12 ),
        .\cplllock_reg1_reg[2]_0 (\pipe_lane[2].pipe_rate.pipe_rate_i_n_14 ),
        .out1({out[0],rst_txsync_start}),
        .p_0_in121_in(p_0_in121_in),
        .p_0_in123_in(p_0_in123_in),
        .p_0_in7_in(p_0_in7_in_4),
        .p_1_in8_in(p_1_in8_in_5),
        .pclk_sel_reg_0(CLK_OOBCLK),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .rate_gen3(rate_gen3[2]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_39 \pipe_lane[2].pipe_sync_i 
       (.Q(\txsync_fsm.txdlyen_reg_0 ),
        .RST_CPLLRESET(p_0_in__0),
        .RST_RATE_IDLE(rate_idle[2]),
        .RST_TXSYNC_DONE(p_315_out),
        .SYNC_GEN3(rate_gen3[2]),
        .SYNC_RXCDRLOCK(p_327_out),
        .SYNC_RXDLYEN(\pipe_lane[2].pipe_sync_i_n_14 ),
        .SYNC_RXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_90 ),
        .SYNC_RXPHALIGNDONE_M(SYNC_RXPHALIGNDONE_M),
        .SYNC_RXPHALIGNDONE_S(\pipe_lane[3].gt_wrapper_i_n_86 ),
        .SYNC_RXSYNC_DONEM_IN(\pipe_lane[0].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[2].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_89 ),
        .SYNC_TXPHALIGNDONE(txsyncallin),
        .SYNC_TXPHINITDONE(\pipe_lane[4].pipe_user_i_n_0 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START0108_out),
        .\cplllock_reg1_reg[2] (\pipe_lane[2].pipe_sync_i_n_15 ),
        .\cplllock_reg1_reg[2]_0 (\pipe_lane[2].pipe_sync_i_n_16 ),
        .\cplllock_reg1_reg[2]_1 (\pipe_lane[2].pipe_sync_i_n_17 ),
        .\cplllock_reg1_reg[2]_2 (\pipe_lane[2].pipe_sync_i_n_18 ),
        .\cplllock_reg1_reg[2]_3 (\pipe_lane[2].pipe_sync_i_n_19 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[2]),
        .p_0_in7_in(p_0_in7_in_4),
        .p_1_in8_in(p_1_in8_in_5),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx[20:14]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK),
        .\txsync_fsm.txdlyen_reg_0 (\pipe_lane[2].pipe_sync_i_n_6 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_40 \pipe_lane[2].pipe_user_i 
       (.CLK_PCLK_SEL(CLK_PCLK_SEL[2]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[2]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[2]),
        .Q({\pipe_lane[2].pipe_user_i_n_8 ,\pipe_lane[2].pipe_user_i_n_9 ,\pipe_lane[2].pipe_user_i_n_10 ,\pipe_lane[2].pipe_user_i_n_11 ,\pipe_lane[2].pipe_user_i_n_12 ,\pipe_lane[2].pipe_user_i_n_13 ,\cplllock_reg1_reg[2] }),
        .RST_CPLLRESET(p_0_in__0),
        .RST_PHYSTATUS(p_294_out),
        .RST_RATE_IDLE(rate_idle[2]),
        .RST_RESETDONE(p_329_out),
        .RST_RXCDRLOCK(p_327_out),
        .RST_RXUSRCLK_RESET(rst_rxusrclk_reset),
        .USER_OOBCLK(\pipe_lane[2].pipe_user_i_n_7 ),
        .USER_RATE_DONE(\pipe_lane[2].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[2].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[2].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[2].pipe_eq.pipe_eq_i_n_17 ),
        .USER_RXRESETDONE(\pipe_lane[2].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[2].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[2] (\pipe_lane[2].pipe_user_i_n_18 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[2]),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[2]),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_1),
        .gt_rxvalid_q_reg_0(gt_rxvalid_q_reg_9),
        .out1(out[0]),
        .p_0_in7_in(p_0_in7_in_4),
        .p_0_in7_in_1(p_0_in7_in),
        .p_0_in7_in_3(p_0_in7_in_7),
        .p_1_in8_in(p_1_in8_in_5),
        .p_1_in8_in_0(p_1_in8_in),
        .p_1_in8_in_2(p_1_in8_in_6),
        .p_2_in(p_2_in_3),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_rxstatus(pipe_rxstatus[8]),
        .pipe_txphaligndone({pipe_txphaligndone[2],pipe_txphaligndone[0]}),
        .pipe_txphinitdone({pipe_txphinitdone[3:2],pipe_txphinitdone[0]}),
        .rate_gen3(rate_gen3[2]),
        .\resetovrd_disble.reset_reg[4]_0 (\pipe_lane[2].gt_wrapper_i_n_16 ),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[2].gt_wrapper_i_n_6 ),
        .resetovrd_done_reg1_reg(\pipe_lane[2].pipe_user_i_n_19 ),
        .txelecidle_reg2_reg_0(\pipe_lane[1].pipe_user_i_n_4 ),
        .txphaligndone_reg1_reg(\pipe_lane[2].pipe_user_i_n_0 ),
        .txphinitdone_reg1_reg(\pipe_lane[2].pipe_user_i_n_3 ),
        .txphinitdone_reg1_reg_0(\pipe_lane[2].pipe_user_i_n_4 ),
        .user_active_lane(user_active_lane[2]),
        .user_rx_converge(p_322_out));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_41 \pipe_lane[3].gt_wrapper_i 
       (.DRPADDR({\pipe_lane[3].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[3].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_30 }),
        .GT_RXPMARESET071_out(GT_RXPMARESET071_out),
        .GT_TXPMARESET074_out(GT_TXPMARESET074_out),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[7:6]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[3]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[3]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[3]),
        .PIPE_TXDATA(PIPE_TXDATA[63:48]),
        .PIPE_TXDATAK(PIPE_TXDATAK[7:6]),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH[1]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[3]),
        .Q(Q),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[3]),
        .RATE_PHYSTATUS(p_241_out),
        .RATE_RXRATEDONE(\pipe_lane[3].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[3].gt_wrapper_i_n_20 ),
        .RST_CPLLRESET(p_0_in__0),
        .RXCHBONDO(\gt_rxchbondo[1]_0 ),
        .RXRATE({\pipe_lane[3].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[3].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[3].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[3].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[3].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[3].pipe_sync_i_n_14 ),
        .TXMAINCURSOR({\pipe_lane[3].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[3].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[3].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_4 }),
        .USER_EYESCANRESET(\pipe_lane[3].pipe_user_i_n_9 ),
        .USER_OOBCLK(\pipe_lane[3].pipe_user_i_n_6 ),
        .USER_RXBUFRESET(\pipe_lane[3].pipe_user_i_n_7 ),
        .USER_RXCDRFREQRESET(\pipe_lane[3].pipe_user_i_n_11 ),
        .USER_RXCDRRESET(\pipe_lane[3].pipe_user_i_n_12 ),
        .USER_RXDFELPMRESET(\pipe_lane[3].pipe_user_i_n_10 ),
        .USER_RXPCSRESET(\pipe_lane[3].pipe_user_i_n_8 ),
        .USER_RXRESETDONE(\pipe_lane[3].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[3].gt_wrapper_i_n_21 ),
        .converge_gen3_reg(\pipe_lane[6].pipe_user_i_n_5 ),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[63:48]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[3]),
        .\fsm_reg[0] (\pipe_lane[3].pipe_drp.pipe_drp_i_n_13 ),
        .\fsm_reg[2] (\pipe_lane[3].pipe_drp.pipe_drp_i_n_12 ),
        .gen3_reg(\pipe_lane[3].pipe_rate.pipe_rate_i_n_14 ),
        .gen3_reg_0(\pipe_lane[3].pipe_rate.pipe_rate_i_n_12 ),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[3]),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_3 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_1 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_1 ),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_10),
        .p_0_in75_in(p_0_in75_in),
        .p_0_in77_in(p_0_in77_in),
        .pci_exp_rxn(pci_exp_rxn[3]),
        .pci_exp_rxp(pci_exp_rxp[3]),
        .pci_exp_txn(pci_exp_txn[3]),
        .pci_exp_txp(pci_exp_txp[3]),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_dmonitorout(pipe_dmonitorout[31:24]),
        .pipe_eyescandataerror(pipe_eyescandataerror[3]),
        .pipe_rxbufstatus(pipe_rxbufstatus[11:9]),
        .pipe_rxcommadet(pipe_rxcommadet[3]),
        .pipe_rxdisperr(pipe_rxdisperr[31:24]),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone[3]),
        .pipe_rxnotintable(pipe_rxnotintable[31:24]),
        .pipe_rxoutclk_out(pipe_rxoutclk_out[3]),
        .pipe_rxphaligndone(pipe_rxphaligndone[2]),
        .pipe_rxprbserr(pipe_rxprbserr[3]),
        .pipe_rxstatus(pipe_rxstatus[11:9]),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep (\pipe_stages_1.pipe_tx_margin_q_reg[2]_rep ),
        .\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep (\pipe_stages_1.pipe_tx_rcvr_det_q_reg_rep ),
        .pipe_txdlysresetdone(pipe_txdlysresetdone[3]),
        .pipe_txinhibit(pipe_txinhibit[3]),
        .pipe_txphaligndone(pipe_txphaligndone[3]),
        .pipe_txphinitdone(pipe_txphinitdone[3]),
        .\pl_ltssm_state_q_reg[4] (\pl_ltssm_state_q_reg[4] ),
        .qpllpd_reg(\cplllock_reg1_reg[3] ),
        .qpllpd_reg_0(\cplllock_reg1_reg[3]_0 ),
        .\resetovrd_disble.fsm_reg[1] (\pipe_lane[3].pipe_user_i_n_17 ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .\resetovrd_disble.reset_reg[4]_0 ({pipe_rxphaligndone[6:3],pipe_rxphaligndone[1:0]}),
        .rst_cpllpd(rst_cpllpd),
        .rst_gtreset(rst_gtreset),
        .rxcdrlock_reg1_reg(\pipe_lane[3].gt_wrapper_i_n_6 ),
        .rxphaligndone_s_reg1_reg(\pipe_lane[3].gt_wrapper_i_n_86 ),
        .rxsync_donem_reg2_reg(\pipe_lane[3].pipe_sync_i_n_18 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2] (\pipe_lane[3].pipe_sync_i_n_19 ),
        .rxvalid_reg1_reg(\pipe_lane[3].gt_wrapper_i_n_16 ),
        .sys_clk(sys_clk),
        .\txsync_fsm.fsm_tx_reg[2] (\pipe_lane[3].pipe_sync_i_n_15 ),
        .\txsync_fsm.fsm_tx_reg[4] (\pipe_lane[3].pipe_sync_i_n_17 ),
        .\txsync_fsm.fsm_tx_reg[4]_0 (\pipe_lane[3].pipe_sync_i_n_16 ),
        .\txsync_fsm.txdlyen_reg (\pipe_lane[3].pipe_sync_i_n_6 ),
        .userrdy_reg_rep__2(\pipe_reset.pipe_reset_i_n_20 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_42 \pipe_lane[3].pipe_drp.pipe_drp_i 
       (.DRPADDR({\pipe_lane[3].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[3].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[3].pipe_drp.pipe_drp_i_n_30 }),
        .DRP_DONE(p_259_out),
        .DRP_START(DRP_START082_out),
        .DRP_X16(DRP_X16084_out),
        .DRP_X16X20_MODE(DRP_X16X20_MODE086_out),
        .Q(\index_reg[1]_1 ),
        .RST_DCLK_RESET(rst_dclk_reset),
        .\cplllock_reg1_reg[3] (\pipe_lane[3].pipe_drp.pipe_drp_i_n_12 ),
        .\cplllock_reg1_reg[3]_0 (\pipe_lane[3].pipe_drp.pipe_drp_i_n_13 ),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr[35:27]),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi[63:48]),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[63:48]),
        .ext_ch_gt_drpen(ext_ch_gt_drpen[3]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[3]),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe[3]),
        .gt_ch_drp_rdy(gt_ch_drp_rdy[3]),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_gtreset(rst_gtreset));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_43 \pipe_lane[3].pipe_eq.pipe_eq_i 
       (.RST_CPLLRESET(p_0_in__0),
        .TXMAINCURSOR({\pipe_lane[3].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[3].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[3].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[3].pipe_eq.pipe_eq_i_n_4 }),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[3].pipe_eq.pipe_eq_i_n_17 ),
        .pclk_sel_reg(CLK_OOBCLK),
        .rate_gen3(rate_gen3[3]));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_44 \pipe_lane[3].pipe_rate.pipe_rate_i 
       (.DRP_START082_out(DRP_START082_out),
        .DRP_X16084_out(DRP_X16084_out),
        .DRP_X16X20_MODE086_out(DRP_X16X20_MODE086_out),
        .GT_TXPMARESET074_out(GT_TXPMARESET074_out),
        .Q(\sysclksel_reg[1]_1 ),
        .QRST_QPLLPD_IN(p_268_out),
        .QRST_QPLLRESET_IN(p_267_out),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[3]),
        .RATE_DRP_DONE(p_259_out),
        .RATE_PHYSTATUS(p_241_out),
        .RATE_RESETOVRD_DONE(\pipe_lane[3].pipe_user_i_n_18 ),
        .RATE_RXRATEDONE(\pipe_lane[3].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[3].gt_wrapper_i_n_20 ),
        .RATE_TXSYNC_DONE(p_262_out),
        .RST_CPLLRESET(p_0_in__0),
        .RST_DRP_START(rst_drp_start),
        .RST_DRP_X16(rst_drp_x16),
        .RST_DRP_X16X20_MODE(rst_drp_x16x20_mode),
        .RST_RATE_IDLE(rate_idle[3]),
        .RXRATE({\pipe_lane[3].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[3].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[3].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[3].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[3].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[3].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[3].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START080_out),
        .USER_PCLK_SEL(CLK_PCLK_SEL[3]),
        .USER_RATE_DONE(\pipe_lane[3].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[3].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[3].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXRESETDONE(\pipe_lane[3].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[3].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[3] (\pipe_lane[3].pipe_rate.pipe_rate_i_n_12 ),
        .\cplllock_reg1_reg[3]_0 (\pipe_lane[3].pipe_rate.pipe_rate_i_n_14 ),
        .out1({out[0],rst_txsync_start}),
        .p_0_in75_in(p_0_in75_in),
        .p_0_in77_in(p_0_in77_in),
        .p_0_in7_in(p_0_in7_in_7),
        .p_1_in8_in(p_1_in8_in_6),
        .pclk_sel_reg_0(CLK_OOBCLK),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .qpllpd_reg_0(QRST_QPLLLOCK[0]),
        .rate_gen3(rate_gen3[3]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_45 \pipe_lane[3].pipe_sync_i 
       (.Q(\txsync_fsm.txdlyen_reg_1 ),
        .RST_CPLLRESET(p_0_in__0),
        .RST_RATE_IDLE(rate_idle[3]),
        .RST_TXSYNC_DONE(p_262_out),
        .SYNC_GEN3(rate_gen3[3]),
        .SYNC_RXCDRLOCK(p_274_out),
        .SYNC_RXDLYEN(\pipe_lane[3].pipe_sync_i_n_14 ),
        .SYNC_RXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_90 ),
        .SYNC_RXSYNC_DONEM_IN(\pipe_lane[0].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[3].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_89 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START080_out),
        .\cplllock_reg1_reg[3] (\pipe_lane[3].pipe_sync_i_n_15 ),
        .\cplllock_reg1_reg[3]_0 (\pipe_lane[3].pipe_sync_i_n_16 ),
        .\cplllock_reg1_reg[3]_1 (\pipe_lane[3].pipe_sync_i_n_17 ),
        .\cplllock_reg1_reg[3]_2 (\pipe_lane[3].pipe_sync_i_n_18 ),
        .\cplllock_reg1_reg[3]_3 (\pipe_lane[3].pipe_sync_i_n_19 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[3]),
        .p_0_in7_in(p_0_in7_in_7),
        .p_1_in8_in(p_1_in8_in_6),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx[27:21]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK),
        .\resetovrd_disble.reset_reg[4]_0 (SYNC_RXPHALIGNDONE_M),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[3].gt_wrapper_i_n_86 ),
        .txelecidle_reg2_reg(\pipe_lane[4].pipe_user_i_n_0 ),
        .\txsync_fsm.txdlyen_reg_0 (\pipe_lane[3].pipe_sync_i_n_6 ),
        .txsyncallin(txsyncallin));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_46 \pipe_lane[3].pipe_user_i 
       (.CLK_PCLK_SEL(CLK_PCLK_SEL[3]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[3]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[3]),
        .Q({\pipe_lane[3].pipe_user_i_n_7 ,\pipe_lane[3].pipe_user_i_n_8 ,\pipe_lane[3].pipe_user_i_n_9 ,\pipe_lane[3].pipe_user_i_n_10 ,\pipe_lane[3].pipe_user_i_n_11 ,\pipe_lane[3].pipe_user_i_n_12 ,\cplllock_reg1_reg[3]_1 }),
        .RST_CPLLRESET(p_0_in__0),
        .RST_PHYSTATUS(p_241_out),
        .RST_RATE_IDLE(rate_idle[3]),
        .RST_RESETDONE(p_276_out),
        .RST_RXCDRLOCK(p_274_out),
        .RST_RXUSRCLK_RESET(rst_rxusrclk_reset),
        .USER_OOBCLK(\pipe_lane[3].pipe_user_i_n_6 ),
        .USER_RATE_DONE(\pipe_lane[3].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[3].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[3].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[3].pipe_eq.pipe_eq_i_n_17 ),
        .USER_RXRESETDONE(\pipe_lane[3].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[3].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[3] (\pipe_lane[3].pipe_user_i_n_17 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[3]),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[3]),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_2),
        .gt_rxvalid_q_reg_0(gt_rxvalid_q_reg_10),
        .out1(out[0]),
        .p_0_in7_in(p_0_in7_in_7),
        .p_1_in8_in(p_1_in8_in_6),
        .p_2_in(p_2_in_8),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_rxstatus(pipe_rxstatus[11]),
        .pipe_txphaligndone({pipe_txphaligndone[2],pipe_txphaligndone[0]}),
        .rate_gen3(rate_gen3[3]),
        .\resetovrd_disble.reset_reg[4]_0 (\pipe_lane[3].gt_wrapper_i_n_16 ),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[3].gt_wrapper_i_n_6 ),
        .resetovrd_done_reg1_reg(\pipe_lane[3].pipe_user_i_n_18 ),
        .txcompliance_reg2_reg_0(\pipe_lane[1].pipe_user_i_n_3 ),
        .txelecidle_reg2_reg_0({user_active_lane[2],user_active_lane[0]}),
        .txphaligndone_reg1_reg(\pipe_lane[3].pipe_user_i_n_0 ),
        .user_active_lane(user_active_lane[3]),
        .user_rx_converge(p_269_out));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_47 \pipe_lane[4].gt_wrapper_i 
       (.DRPADDR({\pipe_lane[4].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[4].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_30 }),
        .GT_RXPMARESET061_out(GT_RXPMARESET061_out),
        .GT_RX_CONVERGE0(\pipe_lane[6].pipe_user_i_n_3 ),
        .GT_TXPMARESET064_out(GT_TXPMARESET064_out),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[9:8]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[4]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[4]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[4]),
        .PIPE_TXDATA(PIPE_TXDATA[79:64]),
        .PIPE_TXDATAK(PIPE_TXDATAK[9:8]),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH[2]),
        .PIPE_TXDETECTRX(PIPE_TXDETECTRX),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[4]),
        .PIPE_TXMARGIN(PIPE_TXMARGIN),
        .Q(Q),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[4]),
        .RATE_PHYSTATUS(p_184_out),
        .RATE_RXRATEDONE(\pipe_lane[4].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[4].gt_wrapper_i_n_20 ),
        .RST_CPLLRESET(p_0_in__0),
        .RXCHBONDO(\gt_rxchbondo[1]_0 ),
        .RXRATE({\pipe_lane[4].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[4].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[4].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[4].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[4].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[4].pipe_sync_i_n_14 ),
        .TXMAINCURSOR({\pipe_lane[4].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[4].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[4].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_4 }),
        .USER_EYESCANRESET(\pipe_lane[4].pipe_user_i_n_9 ),
        .USER_OOBCLK(\pipe_lane[4].pipe_user_i_n_6 ),
        .USER_RXBUFRESET(\pipe_lane[4].pipe_user_i_n_7 ),
        .USER_RXCDRFREQRESET(\pipe_lane[4].pipe_user_i_n_11 ),
        .USER_RXCDRRESET(\pipe_lane[4].pipe_user_i_n_12 ),
        .USER_RXDFELPMRESET(\pipe_lane[4].pipe_user_i_n_10 ),
        .USER_RXPCSRESET(\pipe_lane[4].pipe_user_i_n_8 ),
        .USER_RXRESETDONE(\pipe_lane[4].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[4].gt_wrapper_i_n_21 ),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[79:64]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[4]),
        .\fsm_reg[0] (\pipe_lane[4].pipe_drp.pipe_drp_i_n_13 ),
        .\fsm_reg[2] (\pipe_lane[4].pipe_drp.pipe_drp_i_n_12 ),
        .gen3_reg(\pipe_lane[4].pipe_rate.pipe_rate_i_n_14 ),
        .gen3_reg_0(\pipe_lane[4].pipe_rate.pipe_rate_i_n_12 ),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[4]),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_2 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_2 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_2 ),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_11),
        .p_0_in65_in(p_0_in65_in),
        .p_0_in67_in(p_0_in67_in),
        .pci_exp_rxn(pci_exp_rxn[4]),
        .pci_exp_rxp(pci_exp_rxp[4]),
        .pci_exp_txn(pci_exp_txn[4]),
        .pci_exp_txp(pci_exp_txp[4]),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_dmonitorout(pipe_dmonitorout[39:32]),
        .pipe_eyescandataerror(pipe_eyescandataerror[4]),
        .pipe_rxbufstatus(pipe_rxbufstatus[14:12]),
        .pipe_rxcommadet(pipe_rxcommadet[4]),
        .pipe_rxdisperr(pipe_rxdisperr[39:32]),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone[4]),
        .pipe_rxnotintable(pipe_rxnotintable[39:32]),
        .pipe_rxoutclk_out(pipe_rxoutclk_out[4]),
        .pipe_rxphaligndone(pipe_rxphaligndone[3]),
        .pipe_rxprbserr(pipe_rxprbserr[4]),
        .pipe_rxstatus(pipe_rxstatus[14:12]),
        .pipe_txdlysresetdone(pipe_txdlysresetdone[4]),
        .pipe_txinhibit(pipe_txinhibit[4]),
        .pipe_txphaligndone(pipe_txphaligndone[4]),
        .pipe_txphinitdone(pipe_txphinitdone[4]),
        .\pl_ltssm_state_q_reg[4] (\pl_ltssm_state_q_reg[4] ),
        .qpllpd_reg(\cplllock_reg1_reg[7] ),
        .qpllpd_reg_0(\cplllock_reg1_reg[7]_0 ),
        .\resetovrd_disble.fsm_reg[1] (\pipe_lane[4].pipe_user_i_n_17 ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_cpllpd(rst_cpllpd),
        .rst_gtreset(rst_gtreset),
        .rxcdrlock_reg1_reg(\pipe_lane[4].gt_wrapper_i_n_6 ),
        .rxsync_donem_reg2_reg(\pipe_lane[4].pipe_sync_i_n_18 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2] (\pipe_lane[4].pipe_sync_i_n_19 ),
        .rxvalid_reg1_reg(\pipe_lane[4].gt_wrapper_i_n_16 ),
        .sys_clk(sys_clk),
        .\txsync_fsm.fsm_tx_reg[2] (\pipe_lane[4].pipe_sync_i_n_15 ),
        .\txsync_fsm.fsm_tx_reg[4] (\pipe_lane[4].pipe_sync_i_n_17 ),
        .\txsync_fsm.fsm_tx_reg[4]_0 (\pipe_lane[4].pipe_sync_i_n_16 ),
        .\txsync_fsm.txdlyen_reg (\pipe_lane[4].pipe_sync_i_n_6 ),
        .userrdy_reg_rep__1(\pipe_reset.pipe_reset_i_n_19 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_48 \pipe_lane[4].pipe_drp.pipe_drp_i 
       (.DRPADDR({\pipe_lane[4].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[4].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[4].pipe_drp.pipe_drp_i_n_30 }),
        .DRP_DONE(p_206_out),
        .DRP_START(DRP_START0130_out),
        .DRP_X16(DRP_X160132_out),
        .DRP_X16X20_MODE(DRP_X16X20_MODE0134_out),
        .Q(\index_reg[1]_2 ),
        .RST_DCLK_RESET(rst_dclk_reset),
        .\cplllock_reg1_reg[4] (\pipe_lane[4].pipe_drp.pipe_drp_i_n_12 ),
        .\cplllock_reg1_reg[4]_0 (\pipe_lane[4].pipe_drp.pipe_drp_i_n_13 ),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr[44:36]),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi[79:64]),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[79:64]),
        .ext_ch_gt_drpen(ext_ch_gt_drpen[4]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[4]),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe[4]),
        .gt_ch_drp_rdy(gt_ch_drp_rdy[4]),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_gtreset(rst_gtreset));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_49 \pipe_lane[4].pipe_eq.pipe_eq_i 
       (.RST_CPLLRESET(p_0_in__0),
        .TXMAINCURSOR({\pipe_lane[4].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[4].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[4].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[4].pipe_eq.pipe_eq_i_n_4 }),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[4].pipe_eq.pipe_eq_i_n_17 ),
        .pclk_sel_reg(CLK_OOBCLK),
        .rate_gen3(rate_gen3[4]));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_common_50 \pipe_lane[4].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i 
       (.DRP_DONE(p_196_out),
        .DRP_GEN3(\pipe_lane[6].pipe_rate.pipe_rate_i_n_14 ),
        .DRP_OVRD(qrst_ovrd),
        .DRP_START(\qpll_reset.qpll_reset_i_n_4 ),
        .RATE_QPLLLOCK(QRST_QPLLLOCK[1]),
        .RST_DCLK_RESET(rst_dclk_reset),
        .\cplllock_reg1_reg[7] (\cplllock_reg1_reg[7] ),
        .\cplllock_reg1_reg[7]_0 (\cplllock_reg1_reg[7]_0 ),
        .qpllpd(qpllpd),
        .qrst_qpllreset(qrst_qpllreset),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .sys_clk(sys_clk));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_51 \pipe_lane[4].pipe_rate.pipe_rate_i 
       (.DRP_START0130_out(DRP_START0130_out),
        .DRP_X160132_out(DRP_X160132_out),
        .DRP_X16X20_MODE0134_out(DRP_X16X20_MODE0134_out),
        .GT_TXPMARESET064_out(GT_TXPMARESET064_out),
        .Q(\sysclksel_reg[1]_2 ),
        .QRST_QPLLPD_IN(p_215_out),
        .QRST_QPLLRESET_IN(p_214_out),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[4]),
        .RATE_DRP_DONE(p_206_out),
        .RATE_PHYSTATUS(p_184_out),
        .RATE_QPLLLOCK(QRST_QPLLLOCK[1]),
        .RATE_RESETOVRD_DONE(\pipe_lane[4].pipe_user_i_n_18 ),
        .RATE_RXRATEDONE(\pipe_lane[4].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[4].gt_wrapper_i_n_20 ),
        .RATE_TXSYNC_DONE(p_209_out),
        .RST_CPLLRESET(p_0_in__0),
        .RST_DRP_START(rst_drp_start),
        .RST_DRP_X16(rst_drp_x16),
        .RST_DRP_X16X20_MODE(rst_drp_x16x20_mode),
        .RST_RATE_IDLE(rate_idle[4]),
        .RXRATE({\pipe_lane[4].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[4].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[4].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[4].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[4].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[4].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[4].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START0128_out),
        .USER_PCLK_SEL(CLK_PCLK_SEL[4]),
        .USER_RATE_DONE(\pipe_lane[4].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[4].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[4].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXRESETDONE(\pipe_lane[4].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[4].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[4] (\pipe_lane[4].pipe_rate.pipe_rate_i_n_12 ),
        .\cplllock_reg1_reg[4]_0 (\pipe_lane[4].pipe_rate.pipe_rate_i_n_14 ),
        .out1({out[0],rst_txsync_start}),
        .p_0_in65_in(p_0_in65_in),
        .p_0_in67_in(p_0_in67_in),
        .p_0_in7_in(p_0_in7_in_11),
        .p_1_in8_in(p_1_in8_in_10),
        .pclk_sel_reg_0(CLK_OOBCLK),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .rate_gen3(rate_gen3[4]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_52 \pipe_lane[4].pipe_sync_i 
       (.Q(\txsync_fsm.txdlyen_reg_2 ),
        .RST_CPLLRESET(p_0_in__0),
        .RST_RATE_IDLE(rate_idle[4]),
        .RST_TXSYNC_DONE(p_209_out),
        .SYNC_GEN3(rate_gen3[4]),
        .SYNC_RXCDRLOCK(p_221_out),
        .SYNC_RXDLYEN(\pipe_lane[4].pipe_sync_i_n_14 ),
        .SYNC_RXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_90 ),
        .SYNC_RXSYNC_START(\pipe_lane[4].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_89 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START0128_out),
        .\cplllock_reg1_reg[4] (\pipe_lane[4].pipe_sync_i_n_15 ),
        .\cplllock_reg1_reg[4]_0 (\pipe_lane[4].pipe_sync_i_n_16 ),
        .\cplllock_reg1_reg[4]_1 (\pipe_lane[4].pipe_sync_i_n_17 ),
        .\cplllock_reg1_reg[4]_2 (\pipe_lane[4].pipe_sync_i_n_18 ),
        .\cplllock_reg1_reg[4]_3 (\pipe_lane[4].pipe_sync_i_n_19 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[4]),
        .p_0_in7_in(p_0_in7_in_11),
        .p_1_in8_in(p_1_in8_in_10),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx[34:28]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK),
        .\resetovrd_disble.reset_reg[4]_0 (SYNC_RXPHALIGNDONE_M),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[3].gt_wrapper_i_n_86 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2]_0 (\pipe_lane[0].pipe_sync_i_n_14 ),
        .txelecidle_reg2_reg(\pipe_lane[4].pipe_user_i_n_0 ),
        .\txsync_fsm.txdlyen_reg_0 (\pipe_lane[4].pipe_sync_i_n_6 ),
        .txsyncallin(txsyncallin));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_53 \pipe_lane[4].pipe_user_i 
       (.CLK_PCLK_SEL(CLK_PCLK_SEL[4]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[4]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[4]),
        .Q({\pipe_lane[4].pipe_user_i_n_7 ,\pipe_lane[4].pipe_user_i_n_8 ,\pipe_lane[4].pipe_user_i_n_9 ,\pipe_lane[4].pipe_user_i_n_10 ,\pipe_lane[4].pipe_user_i_n_11 ,\pipe_lane[4].pipe_user_i_n_12 ,\cplllock_reg1_reg[4] }),
        .RST_CPLLRESET(p_0_in__0),
        .RST_PHYSTATUS(p_184_out),
        .RST_RATE_IDLE(rate_idle[4]),
        .RST_RESETDONE(p_223_out),
        .RST_RXCDRLOCK(p_221_out),
        .RST_RXUSRCLK_RESET(rst_rxusrclk_reset),
        .USER_OOBCLK(\pipe_lane[4].pipe_user_i_n_6 ),
        .USER_RATE_DONE(\pipe_lane[4].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[4].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[4].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[4].pipe_eq.pipe_eq_i_n_17 ),
        .USER_RXRESETDONE(\pipe_lane[4].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[4].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[4] (\pipe_lane[4].pipe_user_i_n_17 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[4]),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[4]),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_3),
        .gt_rxvalid_q_reg_0(gt_rxvalid_q_reg_11),
        .out1(out[0]),
        .p_0_in7_in(p_0_in7_in_11),
        .p_0_in7_in_1(p_0_in7_in_13),
        .p_1_in8_in(p_1_in8_in_10),
        .p_1_in8_in_0(p_1_in8_in_12),
        .p_216_out(p_216_out),
        .p_2_in(p_2_in_9),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_rxstatus(pipe_rxstatus[14]),
        .pipe_txphaligndone(pipe_txphaligndone[5:4]),
        .pipe_txphinitdone({pipe_txphinitdone[5:4],pipe_txphinitdone[0]}),
        .rate_gen3(rate_gen3[4]),
        .\resetovrd_disble.reset_reg[4]_0 (\pipe_lane[4].gt_wrapper_i_n_16 ),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[4].gt_wrapper_i_n_6 ),
        .resetovrd_done_reg1_reg(\pipe_lane[4].pipe_user_i_n_18 ),
        .txcompliance_reg2_reg_0(\pipe_lane[2].pipe_user_i_n_3 ),
        .txelecidle_reg2_reg_0(\pipe_lane[7].pipe_user_i_n_0 ),
        .txelecidle_reg2_reg_1(\pipe_lane[0].pipe_user_i_n_0 ),
        .txphaligndone_reg1_reg(\pipe_lane[4].pipe_user_i_n_3 ),
        .txphinitdone_reg1_reg(\pipe_lane[4].pipe_user_i_n_0 ),
        .user_active_lane(user_active_lane[5]));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_54 \pipe_lane[5].gt_wrapper_i 
       (.DRPADDR({\pipe_lane[5].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[5].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_30 }),
        .GT_RXPMARESET043_out(GT_RXPMARESET043_out),
        .GT_TXPMARESET046_out(GT_TXPMARESET046_out),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[11:10]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[5]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[5]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[5]),
        .PIPE_TXDATA(PIPE_TXDATA[95:80]),
        .PIPE_TXDATAK(PIPE_TXDATAK[11:10]),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH[2]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[5]),
        .Q(Q),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[5]),
        .RATE_PHYSTATUS(p_131_out),
        .RATE_RXRATEDONE(\pipe_lane[5].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[5].gt_wrapper_i_n_20 ),
        .RST_CPLLRESET(p_0_in__0),
        .RXCHBONDO(\gt_rxchbondo[1]_0 ),
        .RXRATE({\pipe_lane[5].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[5].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[5].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[5].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[5].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[5].pipe_sync_i_n_14 ),
        .TXMAINCURSOR({\pipe_lane[5].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[5].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[5].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_4 }),
        .USER_EYESCANRESET(\pipe_lane[5].pipe_user_i_n_7 ),
        .USER_OOBCLK(\pipe_lane[5].pipe_user_i_n_4 ),
        .USER_RXBUFRESET(\pipe_lane[5].pipe_user_i_n_5 ),
        .USER_RXCDRFREQRESET(\pipe_lane[5].pipe_user_i_n_9 ),
        .USER_RXCDRRESET(\pipe_lane[5].pipe_user_i_n_10 ),
        .USER_RXDFELPMRESET(\pipe_lane[5].pipe_user_i_n_8 ),
        .USER_RXPCSRESET(\pipe_lane[5].pipe_user_i_n_6 ),
        .USER_RXRESETDONE(\pipe_lane[5].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[5].gt_wrapper_i_n_21 ),
        .converge_gen3_reg(\pipe_lane[6].pipe_user_i_n_6 ),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[95:80]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[5]),
        .\fsm_reg[0] (\pipe_lane[5].pipe_drp.pipe_drp_i_n_13 ),
        .\fsm_reg[2] (\pipe_lane[5].pipe_drp.pipe_drp_i_n_12 ),
        .gen3_reg(\pipe_lane[5].pipe_rate.pipe_rate_i_n_14 ),
        .gen3_reg_0(\pipe_lane[5].pipe_rate.pipe_rate_i_n_12 ),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[5]),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_1 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_3 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_3 ),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_12),
        .p_0_in47_in(p_0_in47_in),
        .p_0_in49_in(p_0_in49_in),
        .pci_exp_rxn(pci_exp_rxn[5]),
        .pci_exp_rxp(pci_exp_rxp[5]),
        .pci_exp_txn(pci_exp_txn[5]),
        .pci_exp_txp(pci_exp_txp[5]),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_dmonitorout(pipe_dmonitorout[47:40]),
        .pipe_eyescandataerror(pipe_eyescandataerror[5]),
        .pipe_rxbufstatus(pipe_rxbufstatus[17:15]),
        .pipe_rxcommadet(pipe_rxcommadet[5]),
        .pipe_rxdisperr(pipe_rxdisperr[47:40]),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone[5]),
        .pipe_rxnotintable(pipe_rxnotintable[47:40]),
        .pipe_rxoutclk_out(pipe_rxoutclk_out[5]),
        .pipe_rxphaligndone(pipe_rxphaligndone[4]),
        .pipe_rxprbserr(pipe_rxprbserr[5]),
        .pipe_rxstatus(pipe_rxstatus[17:15]),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2] (\pipe_stages_1.pipe_tx_margin_q_reg[2] ),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det),
        .pipe_txdlysresetdone(pipe_txdlysresetdone[5]),
        .pipe_txinhibit(pipe_txinhibit[5]),
        .pipe_txphaligndone(pipe_txphaligndone[5]),
        .pipe_txphinitdone(pipe_txphinitdone[5]),
        .\pl_ltssm_state_q_reg[4] (\pl_ltssm_state_q_reg[4] ),
        .qpllpd_reg(\cplllock_reg1_reg[7] ),
        .qpllpd_reg_0(\cplllock_reg1_reg[7]_0 ),
        .\resetovrd_disble.fsm_reg[1] (\pipe_lane[5].pipe_user_i_n_15 ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_cpllpd(rst_cpllpd),
        .rst_gtreset(rst_gtreset),
        .rxcdrlock_reg1_reg(\pipe_lane[5].gt_wrapper_i_n_6 ),
        .rxsync_donem_reg2_reg(\pipe_lane[5].pipe_sync_i_n_18 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2] (\pipe_lane[5].pipe_sync_i_n_19 ),
        .rxvalid_reg1_reg(\pipe_lane[5].gt_wrapper_i_n_16 ),
        .sys_clk(sys_clk),
        .\txsync_fsm.fsm_tx_reg[2] (\pipe_lane[5].pipe_sync_i_n_15 ),
        .\txsync_fsm.fsm_tx_reg[4] (\pipe_lane[5].pipe_sync_i_n_17 ),
        .\txsync_fsm.fsm_tx_reg[4]_0 (\pipe_lane[5].pipe_sync_i_n_16 ),
        .\txsync_fsm.txdlyen_reg (\pipe_lane[5].pipe_sync_i_n_6 ),
        .userrdy_reg_rep__0(\pipe_reset.pipe_reset_i_n_18 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_55 \pipe_lane[5].pipe_drp.pipe_drp_i 
       (.DRPADDR({\pipe_lane[5].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[5].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[5].pipe_drp.pipe_drp_i_n_30 }),
        .DRP_DONE(p_149_out),
        .DRP_START(DRP_START054_out),
        .DRP_X16(DRP_X16056_out),
        .DRP_X16X20_MODE(DRP_X16X20_MODE058_out),
        .Q(\index_reg[1]_3 ),
        .RST_DCLK_RESET(rst_dclk_reset),
        .\cplllock_reg1_reg[5] (\pipe_lane[5].pipe_drp.pipe_drp_i_n_12 ),
        .\cplllock_reg1_reg[5]_0 (\pipe_lane[5].pipe_drp.pipe_drp_i_n_13 ),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr[53:45]),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi[95:80]),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[95:80]),
        .ext_ch_gt_drpen(ext_ch_gt_drpen[5]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[5]),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe[5]),
        .gt_ch_drp_rdy(gt_ch_drp_rdy[5]),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_gtreset(rst_gtreset));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_56 \pipe_lane[5].pipe_eq.pipe_eq_i 
       (.RST_CPLLRESET(p_0_in__0),
        .TXMAINCURSOR({\pipe_lane[5].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[5].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[5].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[5].pipe_eq.pipe_eq_i_n_4 }),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[5].pipe_eq.pipe_eq_i_n_17 ),
        .pclk_sel_reg(CLK_OOBCLK),
        .rate_gen3(rate_gen3[5]));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_57 \pipe_lane[5].pipe_rate.pipe_rate_i 
       (.DRP_START054_out(DRP_START054_out),
        .DRP_X16056_out(DRP_X16056_out),
        .DRP_X16X20_MODE058_out(DRP_X16X20_MODE058_out),
        .GT_TXPMARESET046_out(GT_TXPMARESET046_out),
        .Q(\sysclksel_reg[1]_3 ),
        .QRST_QPLLPD_IN(p_158_out),
        .QRST_QPLLRESET_IN(p_157_out),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[5]),
        .RATE_DRP_DONE(p_149_out),
        .RATE_PHYSTATUS(p_131_out),
        .RATE_QPLLLOCK(QRST_QPLLLOCK[1]),
        .RATE_RESETOVRD_DONE(\pipe_lane[5].pipe_user_i_n_16 ),
        .RATE_RXRATEDONE(\pipe_lane[5].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[5].gt_wrapper_i_n_20 ),
        .RATE_TXSYNC_DONE(p_152_out),
        .RST_CPLLRESET(p_0_in__0),
        .RST_DRP_START(rst_drp_start),
        .RST_DRP_X16(rst_drp_x16),
        .RST_DRP_X16X20_MODE(rst_drp_x16x20_mode),
        .RST_RATE_IDLE(rate_idle[5]),
        .RXRATE({\pipe_lane[5].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[5].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[5].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[5].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[5].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[5].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[5].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START052_out),
        .USER_PCLK_SEL(CLK_PCLK_SEL[5]),
        .USER_RATE_DONE(\pipe_lane[5].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[5].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[5].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXRESETDONE(\pipe_lane[5].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[5].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[5] (\pipe_lane[5].pipe_rate.pipe_rate_i_n_12 ),
        .\cplllock_reg1_reg[5]_0 (\pipe_lane[5].pipe_rate.pipe_rate_i_n_14 ),
        .out1({out[0],rst_txsync_start}),
        .p_0_in47_in(p_0_in47_in),
        .p_0_in49_in(p_0_in49_in),
        .p_0_in7_in(p_0_in7_in_13),
        .p_1_in8_in(p_1_in8_in_12),
        .pclk_sel_reg_0(CLK_OOBCLK),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .rate_gen3(rate_gen3[5]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_58 \pipe_lane[5].pipe_sync_i 
       (.Q(\txsync_fsm.txdlyen_reg_3 ),
        .RST_CPLLRESET(p_0_in__0),
        .RST_RATE_IDLE(rate_idle[5]),
        .RST_TXSYNC_DONE(p_152_out),
        .SYNC_GEN3(rate_gen3[5]),
        .SYNC_RXCDRLOCK(p_164_out),
        .SYNC_RXDLYEN(\pipe_lane[5].pipe_sync_i_n_14 ),
        .SYNC_RXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_90 ),
        .SYNC_RXSYNC_START(\pipe_lane[5].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_89 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START052_out),
        .\cplllock_reg1_reg[5] (\pipe_lane[5].pipe_sync_i_n_15 ),
        .\cplllock_reg1_reg[5]_0 (\pipe_lane[5].pipe_sync_i_n_16 ),
        .\cplllock_reg1_reg[5]_1 (\pipe_lane[5].pipe_sync_i_n_17 ),
        .\cplllock_reg1_reg[5]_2 (\pipe_lane[5].pipe_sync_i_n_18 ),
        .\cplllock_reg1_reg[5]_3 (\pipe_lane[5].pipe_sync_i_n_19 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[5]),
        .p_0_in7_in(p_0_in7_in_13),
        .p_1_in8_in(p_1_in8_in_12),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx[41:35]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK),
        .\resetovrd_disble.reset_reg[4]_0 (SYNC_RXPHALIGNDONE_M),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[3].gt_wrapper_i_n_86 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2]_0 (\pipe_lane[0].pipe_sync_i_n_14 ),
        .txelecidle_reg2_reg(\pipe_lane[4].pipe_user_i_n_0 ),
        .\txsync_fsm.txdlyen_reg_0 (\pipe_lane[5].pipe_sync_i_n_6 ),
        .txsyncallin(txsyncallin));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_59 \pipe_lane[5].pipe_user_i 
       (.CLK_PCLK_SEL(CLK_PCLK_SEL[5]),
        .D(D),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[5]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[5]),
        .Q({\pipe_lane[5].pipe_user_i_n_5 ,\pipe_lane[5].pipe_user_i_n_6 ,\pipe_lane[5].pipe_user_i_n_7 ,\pipe_lane[5].pipe_user_i_n_8 ,\pipe_lane[5].pipe_user_i_n_9 ,\pipe_lane[5].pipe_user_i_n_10 ,\cplllock_reg1_reg[5] }),
        .RST_CPLLRESET(p_0_in__0),
        .RST_PHYSTATUS(p_131_out),
        .RST_RATE_IDLE(rate_idle[5]),
        .RST_RESETDONE(p_166_out),
        .RST_RXCDRLOCK(p_164_out),
        .RST_RXUSRCLK_RESET(rst_rxusrclk_reset),
        .USER_OOBCLK(\pipe_lane[5].pipe_user_i_n_4 ),
        .USER_RATE_DONE(\pipe_lane[5].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[5].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[5].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[5].pipe_eq.pipe_eq_i_n_17 ),
        .USER_RXRESETDONE(\pipe_lane[5].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[5].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[5] (\pipe_lane[5].pipe_user_i_n_15 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[5]),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[5]),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_4),
        .gt_rxvalid_q_reg_0(gt_rxvalid_q_reg_12),
        .out1(out[0]),
        .p_0_in7_in(p_0_in7_in_13),
        .p_159_out(p_159_out),
        .p_1_in8_in(p_1_in8_in_12),
        .p_2_in(p_2_in_9),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_rxstatus(pipe_rxstatus[17]),
        .rate_gen3(rate_gen3[5]),
        .\resetovrd_disble.reset_reg[4]_0 (\pipe_lane[5].gt_wrapper_i_n_16 ),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[5].gt_wrapper_i_n_6 ),
        .resetovrd_done_reg1_reg(\pipe_lane[5].pipe_user_i_n_16 ),
        .rst_idle_reg2_reg_0(\pipe_lane[7].pipe_user_i_n_5 ),
        .user_active_lane(user_active_lane[5]));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_60 \pipe_lane[6].gt_wrapper_i 
       (.DRPADDR({\pipe_lane[6].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[6].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_30 }),
        .GT_RXPMARESET032_out(GT_RXPMARESET032_out),
        .GT_RX_CONVERGE0(\pipe_lane[6].pipe_user_i_n_3 ),
        .GT_TXPMARESET035_out(GT_TXPMARESET035_out),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[13:12]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[6]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[6]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[6]),
        .PIPE_TXDATA(PIPE_TXDATA[111:96]),
        .PIPE_TXDATAK(PIPE_TXDATAK[13:12]),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH[3]),
        .PIPE_TXDETECTRX(PIPE_TXDETECTRX),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[6]),
        .PIPE_TXMARGIN(PIPE_TXMARGIN),
        .Q(Q),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[6]),
        .RATE_PHYSTATUS(p_78_out),
        .RATE_RXRATEDONE(\pipe_lane[6].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[6].gt_wrapper_i_n_20 ),
        .RST_CPLLRESET(p_0_in__0),
        .RXCHBONDO(\gt_rxchbondo[1]_0 ),
        .RXRATE({\pipe_lane[6].pipe_rate.pipe_rate_i_n_18 ,\pipe_lane[6].pipe_rate.pipe_rate_i_n_19 ,\pipe_lane[6].pipe_rate.pipe_rate_i_n_20 }),
        .RXSYSCLKSEL({\pipe_lane[6].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[6].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_90 ),
        .SYNC_RXSYNC_DONE(\pipe_lane[6].pipe_sync_i_n_14 ),
        .SYNC_TXDLYSRESETDONE0(\pipe_lane[6].gt_wrapper_i_n_89 ),
        .TXMAINCURSOR({\pipe_lane[6].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[6].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[6].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_4 }),
        .USER_EYESCANRESET(\pipe_lane[6].pipe_user_i_n_12 ),
        .USER_OOBCLK(\pipe_lane[6].pipe_user_i_n_9 ),
        .USER_RXBUFRESET(\pipe_lane[6].pipe_user_i_n_10 ),
        .USER_RXCDRFREQRESET(\pipe_lane[6].pipe_user_i_n_14 ),
        .USER_RXCDRRESET(\pipe_lane[6].pipe_user_i_n_15 ),
        .USER_RXDFELPMRESET(\pipe_lane[6].pipe_user_i_n_13 ),
        .USER_RXPCSRESET(\pipe_lane[6].pipe_user_i_n_11 ),
        .USER_RXRESETDONE(\pipe_lane[6].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[6].gt_wrapper_i_n_21 ),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[111:96]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[6]),
        .\fsm_reg[0] (\pipe_lane[6].pipe_drp.pipe_drp_i_n_13 ),
        .\fsm_reg[2] (\pipe_lane[6].pipe_drp.pipe_drp_i_n_12 ),
        .gen3_reg(\pipe_lane[6].pipe_rate.pipe_rate_i_n_15 ),
        .gen3_reg_0(\pipe_lane[6].pipe_rate.pipe_rate_i_n_12 ),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[6]),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2]_0 ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_4 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_4 ),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_13),
        .p_0_in36_in(p_0_in36_in),
        .p_0_in38_in(p_0_in38_in),
        .pci_exp_rxn(pci_exp_rxn[6]),
        .pci_exp_rxp(pci_exp_rxp[6]),
        .pci_exp_txn(pci_exp_txn[6]),
        .pci_exp_txp(pci_exp_txp[6]),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_dmonitorout(pipe_dmonitorout[55:48]),
        .pipe_eyescandataerror(pipe_eyescandataerror[6]),
        .pipe_rxbufstatus(pipe_rxbufstatus[20:18]),
        .pipe_rxcommadet(pipe_rxcommadet[6]),
        .pipe_rxdisperr(pipe_rxdisperr[55:48]),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone[6]),
        .pipe_rxnotintable(pipe_rxnotintable[55:48]),
        .pipe_rxoutclk_out(pipe_rxoutclk_out[6]),
        .pipe_rxphaligndone(pipe_rxphaligndone[5]),
        .pipe_rxprbserr(pipe_rxprbserr[6]),
        .pipe_rxstatus(pipe_rxstatus[20:18]),
        .pipe_txdlysresetdone(pipe_txdlysresetdone[6]),
        .pipe_txinhibit(pipe_txinhibit[6]),
        .pipe_txphaligndone(pipe_txphaligndone[6]),
        .pipe_txphinitdone(pipe_txphinitdone[6]),
        .\pl_ltssm_state_q_reg[4] (\pl_ltssm_state_q_reg[4] ),
        .qpllpd_reg(\cplllock_reg1_reg[7] ),
        .qpllpd_reg_0(\cplllock_reg1_reg[7]_0 ),
        .\resetovrd_disble.fsm_reg[1] (\pipe_lane[6].pipe_user_i_n_19 ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .\resetovrd_disble.reset_reg[4]_0 ({pipe_txdlysresetdone[7],pipe_txdlysresetdone[5:0]}),
        .\resetovrd_disble.reset_reg[4]_1 ({pipe_rxdlysresetdone[7],pipe_rxdlysresetdone[5:0]}),
        .rst_cpllpd(rst_cpllpd),
        .rst_gtreset(rst_gtreset),
        .rxcdrlock_reg1_reg(\pipe_lane[6].gt_wrapper_i_n_6 ),
        .rxsync_donem_reg2_reg(\pipe_lane[6].pipe_sync_i_n_18 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2] (\pipe_lane[6].pipe_sync_i_n_19 ),
        .rxvalid_reg1_reg(\pipe_lane[6].gt_wrapper_i_n_16 ),
        .sys_clk(sys_clk),
        .\txsync_fsm.fsm_tx_reg[2] (\pipe_lane[6].pipe_sync_i_n_15 ),
        .\txsync_fsm.fsm_tx_reg[4] (\pipe_lane[6].pipe_sync_i_n_17 ),
        .\txsync_fsm.fsm_tx_reg[4]_0 (\pipe_lane[6].pipe_sync_i_n_16 ),
        .\txsync_fsm.txdlyen_reg (\pipe_lane[6].pipe_sync_i_n_6 ),
        .userrdy_reg_rep(\pipe_reset.pipe_reset_i_n_17 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_61 \pipe_lane[6].pipe_drp.pipe_drp_i 
       (.DRPADDR({\pipe_lane[6].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[6].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[6].pipe_drp.pipe_drp_i_n_30 }),
        .DRP_DONE(p_96_out),
        .DRP_START(DRP_START025_out),
        .DRP_X16(DRP_X16027_out),
        .DRP_X16X20_MODE(DRP_X16X20_MODE029_out),
        .Q(\index_reg[1]_4 ),
        .RST_DCLK_RESET(rst_dclk_reset),
        .\cplllock_reg1_reg[6] (\pipe_lane[6].pipe_drp.pipe_drp_i_n_12 ),
        .\cplllock_reg1_reg[6]_0 (\pipe_lane[6].pipe_drp.pipe_drp_i_n_13 ),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr[62:54]),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi[111:96]),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[111:96]),
        .ext_ch_gt_drpen(ext_ch_gt_drpen[6]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[6]),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe[6]),
        .gt_ch_drp_rdy(gt_ch_drp_rdy[6]),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_gtreset(rst_gtreset));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_62 \pipe_lane[6].pipe_eq.pipe_eq_i 
       (.RST_CPLLRESET(p_0_in__0),
        .TXMAINCURSOR({\pipe_lane[6].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[6].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[6].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[6].pipe_eq.pipe_eq_i_n_4 }),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[6].pipe_eq.pipe_eq_i_n_17 ),
        .pclk_sel_reg(CLK_OOBCLK),
        .rate_gen3(rate_gen3[6]));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_63 \pipe_lane[6].pipe_rate.pipe_rate_i 
       (.DRP_START025_out(DRP_START025_out),
        .DRP_X16027_out(DRP_X16027_out),
        .DRP_X16X20_MODE029_out(DRP_X16X20_MODE029_out),
        .GT_TXPMARESET035_out(GT_TXPMARESET035_out),
        .Q(\sysclksel_reg[1]_4 ),
        .QRST_QPLLPD_IN(p_105_out),
        .QRST_QPLLRESET_IN(p_104_out),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[6]),
        .RATE_DRP_DONE(p_96_out),
        .RATE_PHYSTATUS(p_78_out),
        .RATE_QPLLLOCK(QRST_QPLLLOCK[1]),
        .RATE_RESETOVRD_DONE(\pipe_lane[6].pipe_user_i_n_20 ),
        .RATE_RXRATEDONE(\pipe_lane[6].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[6].gt_wrapper_i_n_20 ),
        .RATE_TXSYNC_DONE(p_99_out),
        .RST_CPLLRESET(p_0_in__0),
        .RST_DRP_START(rst_drp_start),
        .RST_DRP_X16(rst_drp_x16),
        .RST_DRP_X16X20_MODE(rst_drp_x16x20_mode),
        .RST_RATE_IDLE({rate_idle[7],rate_idle[5:0]}),
        .RXRATE({\pipe_lane[6].pipe_rate.pipe_rate_i_n_18 ,\pipe_lane[6].pipe_rate.pipe_rate_i_n_19 ,\pipe_lane[6].pipe_rate.pipe_rate_i_n_20 }),
        .RXSYSCLKSEL({\pipe_lane[6].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[6].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[6].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[6].pipe_rate.pipe_rate_i_n_23 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START023_out),
        .USER_PCLK_SEL(CLK_PCLK_SEL[6]),
        .USER_RATE_DONE(\pipe_lane[6].pipe_rate.pipe_rate_i_n_21 ),
        .USER_RATE_RXSYNC(\pipe_lane[6].pipe_rate.pipe_rate_i_n_22 ),
        .USER_RESETOVRD_START(\pipe_lane[6].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXRESETDONE(\pipe_lane[6].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[6].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[6] (\pipe_lane[6].pipe_rate.pipe_rate_i_n_12 ),
        .\cplllock_reg1_reg[6]_0 (\pipe_lane[6].pipe_rate.pipe_rate_i_n_15 ),
        .gen3_reg1_reg(\pipe_lane[6].pipe_rate.pipe_rate_i_n_14 ),
        .gen3_reg_0({rate_gen3[7],rate_gen3[5:1]}),
        .gen3_reg_1(EQ_GEN3),
        .out1({out[0],rst_txsync_start}),
        .p_0_in36_in(p_0_in36_in),
        .p_0_in38_in(p_0_in38_in),
        .p_0_in7_in(p_0_in7_in_15),
        .p_1_in8_in(p_1_in8_in_14),
        .pclk_sel_reg_0(CLK_OOBCLK),
        .pipe_rate_idle(pipe_rate_idle),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .rate_gen3(rate_gen3[6]),
        .\rate_idle_reg1_reg[6] (rate_idle[6]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_64 \pipe_lane[6].pipe_sync_i 
       (.Q(\txsync_fsm.txdlyen_reg_4 ),
        .RST_CPLLRESET(p_0_in__0),
        .RST_TXSYNC_DONE(p_99_out),
        .SYNC_GEN3(rate_gen3[6]),
        .SYNC_RATE_IDLE(rate_idle[6]),
        .SYNC_RXCDRLOCK(p_111_out),
        .SYNC_RXDLYEN(\pipe_lane[6].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[6].pipe_rate.pipe_rate_i_n_23 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START023_out),
        .\cplllock_reg1_reg[6] (\pipe_lane[6].pipe_sync_i_n_15 ),
        .\cplllock_reg1_reg[6]_0 (\pipe_lane[6].pipe_sync_i_n_16 ),
        .\cplllock_reg1_reg[6]_1 (\pipe_lane[6].pipe_sync_i_n_17 ),
        .\cplllock_reg1_reg[6]_2 (\pipe_lane[6].pipe_sync_i_n_18 ),
        .\cplllock_reg1_reg[6]_3 (\pipe_lane[6].pipe_sync_i_n_19 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[6]),
        .p_0_in7_in(p_0_in7_in_15),
        .p_1_in8_in(p_1_in8_in_14),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx[48:42]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK),
        .\resetovrd_disble.reset_reg[4]_0 (\pipe_lane[6].gt_wrapper_i_n_89 ),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[6].gt_wrapper_i_n_90 ),
        .\resetovrd_disble.reset_reg[4]_2 (SYNC_RXPHALIGNDONE_M),
        .\resetovrd_disble.reset_reg[4]_3 (\pipe_lane[3].gt_wrapper_i_n_86 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2]_0 (\pipe_lane[0].pipe_sync_i_n_14 ),
        .txelecidle_reg2_reg(\pipe_lane[4].pipe_user_i_n_0 ),
        .\txsync_fsm.txdlyen_reg_0 (\pipe_lane[6].pipe_sync_i_n_6 ),
        .txsyncallin(txsyncallin));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_65 \pipe_lane[6].pipe_user_i 
       (.CLK_PCLK_SEL(CLK_PCLK_SEL[6]),
        .GT_RX_CONVERGE0(\pipe_lane[6].pipe_user_i_n_3 ),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[6]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[6]),
        .Q({\pipe_lane[6].pipe_user_i_n_10 ,\pipe_lane[6].pipe_user_i_n_11 ,\pipe_lane[6].pipe_user_i_n_12 ,\pipe_lane[6].pipe_user_i_n_13 ,\pipe_lane[6].pipe_user_i_n_14 ,\pipe_lane[6].pipe_user_i_n_15 ,\cplllock_reg1_reg[6] }),
        .RST_CPLLRESET(p_0_in__0),
        .RST_PHYSTATUS(p_78_out),
        .RST_RESETDONE(p_113_out),
        .RST_RXCDRLOCK(p_111_out),
        .RST_RXUSRCLK_RESET(rst_rxusrclk_reset),
        .USER_OOBCLK(\pipe_lane[6].pipe_user_i_n_9 ),
        .USER_RATE_DONE(\pipe_lane[6].pipe_rate.pipe_rate_i_n_21 ),
        .USER_RATE_GEN3(rate_gen3[6]),
        .USER_RATE_IDLE(rate_idle[6]),
        .USER_RATE_RXSYNC(\pipe_lane[6].pipe_rate.pipe_rate_i_n_22 ),
        .USER_RESETOVRD_START(\pipe_lane[6].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[6].pipe_eq.pipe_eq_i_n_17 ),
        .USER_RXRESETDONE(\pipe_lane[6].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[6].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[2] (\pipe_lane[6].pipe_user_i_n_4 ),
        .\cplllock_reg1_reg[3] (\pipe_lane[6].pipe_user_i_n_5 ),
        .\cplllock_reg1_reg[6] (\pipe_lane[6].pipe_user_i_n_19 ),
        .\cplllock_reg1_reg[7] (\pipe_lane[6].pipe_user_i_n_6 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[6]),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[6]),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_5),
        .gt_rxvalid_q_reg_0(gt_rxvalid_q_reg_13),
        .out1(out[0]),
        .p_0_in7_in(p_0_in7_in_15),
        .p_159_out(p_159_out),
        .p_1_in8_in(p_1_in8_in_14),
        .p_216_out(p_216_out),
        .p_2_in(p_2_in_16),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_rxstatus(pipe_rxstatus[20]),
        .pipe_txphaligndone(pipe_txphaligndone[6]),
        .\resetovrd_disble.reset_reg[4]_0 (\pipe_lane[6].gt_wrapper_i_n_16 ),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[6].gt_wrapper_i_n_6 ),
        .resetovrd_done_reg1_reg(\pipe_lane[6].pipe_user_i_n_20 ),
        .txcompliance_reg2_reg_0(\pipe_lane[7].pipe_user_i_n_3 ),
        .txelecidle_reg2_reg_0(\pipe_lane[1].pipe_user_i_n_0 ),
        .txelecidle_reg2_reg_1(\pipe_lane[4].pipe_user_i_n_3 ),
        .txelecidle_reg2_reg_2(\pipe_lane[3].pipe_user_i_n_0 ),
        .txsyncallin(txsyncallin),
        .user_rx_converge({p_53_out,p_269_out,p_322_out,p_375_out,p_431_out}));
  PCIeGen1x8If64_PCIeGen1x8If64_gt_wrapper_66 \pipe_lane[7].gt_wrapper_i 
       (.DRPADDR({\pipe_lane[7].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[7].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_30 }),
        .GT_RXPMARESET014_out(GT_RXPMARESET014_out),
        .GT_TXPMARESET017_out(GT_TXPMARESET017_out),
        .PIPE_POWERDOWN(PIPE_POWERDOWN[15:14]),
        .PIPE_RXCHANISALIGNED(PIPE_RXCHANISALIGNED[7]),
        .PIPE_RXPOLARITY(PIPE_RXPOLARITY[7]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[7]),
        .PIPE_TXDATA(PIPE_TXDATA[127:112]),
        .PIPE_TXDATAK(PIPE_TXDATAK[15:14]),
        .PIPE_TXDEEMPH(PIPE_TXDEEMPH[3]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[7]),
        .Q(Q),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[7]),
        .RATE_PHYSTATUS(p_25_out),
        .RATE_RXRATEDONE(\pipe_lane[7].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[7].gt_wrapper_i_n_20 ),
        .RST_CPLLRESET(p_0_in__0),
        .RXCHBONDO(\gt_rxchbondo[1]_0 ),
        .RXRATE({\pipe_lane[7].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[7].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[7].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[7].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[7].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RXSYNC_DONE(\pipe_lane[7].pipe_sync_i_n_14 ),
        .TXMAINCURSOR({\pipe_lane[7].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[7].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[7].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_4 }),
        .USER_EYESCANRESET(\pipe_lane[7].pipe_user_i_n_9 ),
        .USER_OOBCLK(\pipe_lane[7].pipe_user_i_n_6 ),
        .USER_RXBUFRESET(\pipe_lane[7].pipe_user_i_n_7 ),
        .USER_RXCDRFREQRESET(\pipe_lane[7].pipe_user_i_n_11 ),
        .USER_RXCDRRESET(\pipe_lane[7].pipe_user_i_n_12 ),
        .USER_RXDFELPMRESET(\pipe_lane[7].pipe_user_i_n_10 ),
        .USER_RXPCSRESET(\pipe_lane[7].pipe_user_i_n_8 ),
        .USER_RXRESETDONE(\pipe_lane[7].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[7].gt_wrapper_i_n_21 ),
        .converge_gen3_reg(\pipe_lane[6].pipe_user_i_n_6 ),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[127:112]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[7]),
        .\fsm_reg[0] (\pipe_lane[7].pipe_drp.pipe_drp_i_n_13 ),
        .\fsm_reg[2] (\pipe_lane[7].pipe_drp.pipe_drp_i_n_12 ),
        .gen3_reg(\pipe_lane[7].pipe_rate.pipe_rate_i_n_14 ),
        .gen3_reg_0(\pipe_lane[7].pipe_rate.pipe_rate_i_n_12 ),
        .gt_cpllpdrefclk(gt_cpllpdrefclk),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[7]),
        .\gt_rx_status_q_reg[2] (\gt_rx_status_q_reg[2] ),
        .\gt_rxcharisk_q_reg[1] (\gt_rxcharisk_q_reg[1]_5 ),
        .\gt_rxdata_q_reg[15] (\gt_rxdata_q_reg[15]_5 ),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_14),
        .p_0_in18_in(p_0_in18_in),
        .p_0_in20_in(p_0_in20_in),
        .pci_exp_rxn(pci_exp_rxn[7]),
        .pci_exp_rxp(pci_exp_rxp[7]),
        .pci_exp_txn(pci_exp_txn[7]),
        .pci_exp_txp(pci_exp_txp[7]),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_dmonitorout(pipe_dmonitorout[63:56]),
        .pipe_eyescandataerror(pipe_eyescandataerror[7]),
        .pipe_rxbufstatus(pipe_rxbufstatus[23:21]),
        .pipe_rxcommadet(pipe_rxcommadet[7]),
        .pipe_rxdisperr(pipe_rxdisperr[63:56]),
        .pipe_rxdlysresetdone(pipe_rxdlysresetdone[7]),
        .pipe_rxnotintable(pipe_rxnotintable[63:56]),
        .pipe_rxoutclk_out(pipe_rxoutclk_out[7]),
        .pipe_rxphaligndone(pipe_rxphaligndone[6]),
        .pipe_rxprbserr(pipe_rxprbserr[7]),
        .pipe_rxstatus(pipe_rxstatus[23:21]),
        .\pipe_stages_1.pipe_tx_margin_q_reg[2] (\pipe_stages_1.pipe_tx_margin_q_reg[2] ),
        .pipe_tx_rcvr_det(pipe_tx_rcvr_det),
        .pipe_txdlysresetdone(pipe_txdlysresetdone[7]),
        .pipe_txinhibit(pipe_txinhibit[7]),
        .pipe_txphaligndone(pipe_txphaligndone[7]),
        .pipe_txphinitdone(pipe_txphinitdone[7]),
        .\pl_ltssm_state_q_reg[4] (\pl_ltssm_state_q_reg[4] ),
        .qpllpd_reg(\cplllock_reg1_reg[7] ),
        .qpllpd_reg_0(\cplllock_reg1_reg[7]_0 ),
        .\resetovrd_disble.fsm_reg[1] (\pipe_lane[7].pipe_user_i_n_17 ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_cpllpd(rst_cpllpd),
        .rst_gtreset(rst_gtreset),
        .rst_userrdy(rst_userrdy),
        .rxcdrlock_reg1_reg(\pipe_lane[7].gt_wrapper_i_n_6 ),
        .rxsync_donem_reg2_reg(\pipe_lane[7].pipe_sync_i_n_18 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2] (\pipe_lane[7].pipe_sync_i_n_19 ),
        .rxvalid_reg1_reg(\pipe_lane[7].gt_wrapper_i_n_16 ),
        .sys_clk(sys_clk),
        .\txsync_fsm.fsm_tx_reg[2] (\pipe_lane[7].pipe_sync_i_n_15 ),
        .\txsync_fsm.fsm_tx_reg[4] (\pipe_lane[7].pipe_sync_i_n_17 ),
        .\txsync_fsm.fsm_tx_reg[4]_0 (\pipe_lane[7].pipe_sync_i_n_16 ),
        .\txsync_fsm.txdlyen_reg (\pipe_lane[7].pipe_sync_i_n_6 ));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_drp_67 \pipe_lane[7].pipe_drp.pipe_drp_i 
       (.DRPADDR({\pipe_lane[7].pipe_drp.pipe_drp_i_n_3 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_4 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_5 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_6 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_7 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_8 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_9 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_10 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_11 }),
        .DRPDI({\pipe_lane[7].pipe_drp.pipe_drp_i_n_15 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_16 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_17 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_18 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_19 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_20 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_21 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_22 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_23 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_24 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_25 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_26 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_27 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_28 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_29 ,\pipe_lane[7].pipe_drp.pipe_drp_i_n_30 }),
        .DRP_DONE(p_43_out),
        .DRP_START(DRP_START08_out),
        .DRP_X16(DRP_X16010_out),
        .DRP_X16X20_MODE(DRP_X16X20_MODE0136_out),
        .Q(\index_reg[1]_5 ),
        .RST_DCLK_RESET(rst_dclk_reset),
        .\cplllock_reg1_reg[7] (\pipe_lane[7].pipe_drp.pipe_drp_i_n_12 ),
        .\cplllock_reg1_reg[7]_0 (\pipe_lane[7].pipe_drp.pipe_drp_i_n_13 ),
        .ext_ch_gt_drpaddr(ext_ch_gt_drpaddr[71:63]),
        .ext_ch_gt_drpdi(ext_ch_gt_drpdi[127:112]),
        .ext_ch_gt_drpdo(ext_ch_gt_drpdo[127:112]),
        .ext_ch_gt_drpen(ext_ch_gt_drpen[7]),
        .ext_ch_gt_drprdy(ext_ch_gt_drprdy[7]),
        .ext_ch_gt_drpwe(ext_ch_gt_drpwe[7]),
        .gt_ch_drp_rdy(gt_ch_drp_rdy[7]),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .\resetovrd_disble.reset_reg[4] (CLK_DCLK),
        .rst_gtreset(rst_gtreset));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_eq_68 \pipe_lane[7].pipe_eq.pipe_eq_i 
       (.RST_CPLLRESET(p_0_in__0),
        .TXMAINCURSOR({\pipe_lane[7].pipe_eq.pipe_eq_i_n_5 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_6 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_7 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_8 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_9 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_10 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_11 }),
        .TXPOSTCURSOR({\pipe_lane[7].pipe_eq.pipe_eq_i_n_12 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_13 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_14 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_15 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_16 }),
        .TXPRECURSOR({\pipe_lane[7].pipe_eq.pipe_eq_i_n_0 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_1 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_2 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_3 ,\pipe_lane[7].pipe_eq.pipe_eq_i_n_4 }),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[7].pipe_eq.pipe_eq_i_n_17 ),
        .gen3_reg(rate_gen3[7]),
        .pclk_sel_reg(CLK_OOBCLK));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_rate_69 \pipe_lane[7].pipe_rate.pipe_rate_i 
       (.DRP_START08_out(DRP_START08_out),
        .DRP_X16010_out(DRP_X16010_out),
        .DRP_X16X20_MODE0136_out(DRP_X16X20_MODE0136_out),
        .GT_TXPMARESET017_out(GT_TXPMARESET017_out),
        .Q(\sysclksel_reg[1]_5 ),
        .QRST_QPLLPD_IN(p_52_out),
        .QRST_QPLLRESET_IN(p_51_out),
        .RATE_CPLLLOCK(QRST_CPLLLOCK[7]),
        .RATE_DRP_DONE(p_43_out),
        .RATE_PHYSTATUS(p_25_out),
        .RATE_RESETOVRD_DONE(\pipe_lane[7].pipe_user_i_n_18 ),
        .RATE_RXRATEDONE(\pipe_lane[7].gt_wrapper_i_n_14 ),
        .RATE_TXRATEDONE(\pipe_lane[7].gt_wrapper_i_n_20 ),
        .RATE_TXSYNC_DONE(p_46_out),
        .RST_CPLLRESET(p_0_in__0),
        .RST_DRP_START(rst_drp_start),
        .RST_DRP_X16(rst_drp_x16),
        .RST_DRP_X16X20_MODE(rst_drp_x16x20_mode),
        .RXRATE({\pipe_lane[7].pipe_rate.pipe_rate_i_n_15 ,\pipe_lane[7].pipe_rate.pipe_rate_i_n_16 ,\pipe_lane[7].pipe_rate.pipe_rate_i_n_17 }),
        .RXSYSCLKSEL({\pipe_lane[7].pipe_rate.pipe_rate_i_n_6 ,\pipe_lane[7].pipe_rate.pipe_rate_i_n_7 }),
        .SYNC_RATE_IDLE(rate_idle[7]),
        .SYNC_RXSYNC_DONE(\pipe_lane[7].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[7].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START0),
        .USER_PCLK_SEL(CLK_PCLK_SEL[7]),
        .USER_RATE_DONE(\pipe_lane[7].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_RXSYNC(\pipe_lane[7].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[7].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXRESETDONE(\pipe_lane[7].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[7].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[7] (\pipe_lane[7].pipe_rate.pipe_rate_i_n_12 ),
        .\cplllock_reg1_reg[7]_0 (\pipe_lane[7].pipe_rate.pipe_rate_i_n_14 ),
        .out1({out[0],rst_txsync_start}),
        .p_0_in18_in(p_0_in18_in),
        .p_0_in20_in(p_0_in20_in),
        .p_0_in7_in(p_0_in7_in_17),
        .p_1_in8_in(p_1_in8_in_18),
        .pclk_sel_reg_0(CLK_OOBCLK),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .qpllpd_reg_0(QRST_QPLLLOCK[1]),
        .rate_gen3_reg1_reg(rate_gen3[7]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_sync_70 \pipe_lane[7].pipe_sync_i 
       (.Q(\txsync_fsm.txdlyen_reg_5 ),
        .RST_CPLLRESET(p_0_in__0),
        .RST_TXSYNC_DONE(p_46_out),
        .SYNC_GEN3(rate_gen3[7]),
        .SYNC_RATE_IDLE(rate_idle[7]),
        .SYNC_RXCDRLOCK(p_58_out),
        .SYNC_RXDLYEN(\pipe_lane[7].pipe_sync_i_n_14 ),
        .SYNC_RXSYNC_START(\pipe_lane[7].pipe_rate.pipe_rate_i_n_20 ),
        .SYNC_TXSYNC_START(SYNC_TXSYNC_START0),
        .\cplllock_reg1_reg[7] (\pipe_lane[7].pipe_sync_i_n_15 ),
        .\cplllock_reg1_reg[7]_0 (\pipe_lane[7].pipe_sync_i_n_16 ),
        .\cplllock_reg1_reg[7]_1 (\pipe_lane[7].pipe_sync_i_n_17 ),
        .\cplllock_reg1_reg[7]_2 (\pipe_lane[7].pipe_sync_i_n_18 ),
        .\cplllock_reg1_reg[7]_3 (\pipe_lane[7].pipe_sync_i_n_19 ),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[7]),
        .p_0_in7_in(p_0_in7_in_17),
        .p_1_in8_in(p_1_in8_in_18),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_sync_fsm_rx(pipe_sync_fsm_rx[55:49]),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK),
        .\resetovrd_disble.reset_reg[4]_0 (\pipe_lane[6].gt_wrapper_i_n_89 ),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[6].gt_wrapper_i_n_90 ),
        .\resetovrd_disble.reset_reg[4]_2 (SYNC_RXPHALIGNDONE_M),
        .\resetovrd_disble.reset_reg[4]_3 (\pipe_lane[3].gt_wrapper_i_n_86 ),
        .\rxsync_fsm_disable.fsm_rx_reg[2]_0 (\pipe_lane[0].pipe_sync_i_n_14 ),
        .txelecidle_reg2_reg(\pipe_lane[4].pipe_user_i_n_0 ),
        .\txsync_fsm.txdlyen_reg_0 (\pipe_lane[7].pipe_sync_i_n_6 ),
        .txsyncallin(txsyncallin));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_user_71 \pipe_lane[7].pipe_user_i 
       (.CLK_PCLK_SEL(CLK_PCLK_SEL[7]),
        .PIPE_TXCOMPLIANCE(PIPE_TXCOMPLIANCE[7]),
        .PIPE_TXELECIDLE(PIPE_TXELECIDLE[7]),
        .Q({\pipe_lane[7].pipe_user_i_n_7 ,\pipe_lane[7].pipe_user_i_n_8 ,\pipe_lane[7].pipe_user_i_n_9 ,\pipe_lane[7].pipe_user_i_n_10 ,\pipe_lane[7].pipe_user_i_n_11 ,\pipe_lane[7].pipe_user_i_n_12 ,\cplllock_reg1_reg[7]_1 }),
        .RST_CPLLRESET(p_0_in__0),
        .RST_PHYSTATUS(p_25_out),
        .RST_RESETDONE(p_60_out),
        .RST_RXCDRLOCK(p_58_out),
        .RST_RXUSRCLK_RESET(rst_rxusrclk_reset),
        .USER_OOBCLK(\pipe_lane[7].pipe_user_i_n_6 ),
        .USER_RATE_DONE(\pipe_lane[7].pipe_rate.pipe_rate_i_n_18 ),
        .USER_RATE_IDLE(rate_idle[7]),
        .USER_RATE_RXSYNC(\pipe_lane[7].pipe_rate.pipe_rate_i_n_19 ),
        .USER_RESETOVRD_START(\pipe_lane[7].pipe_rate.pipe_rate_i_n_5 ),
        .USER_RXEQ_ADAPT_DONE(\pipe_lane[7].pipe_eq.pipe_eq_i_n_17 ),
        .USER_RXRESETDONE(\pipe_lane[7].gt_wrapper_i_n_15 ),
        .USER_TXRESETDONE(\pipe_lane[7].gt_wrapper_i_n_21 ),
        .\cplllock_reg1_reg[7] (\pipe_lane[7].pipe_user_i_n_17 ),
        .gen3_reg(rate_gen3[7]),
        .gt_rx_elec_idle_wire_filter(gt_rx_elec_idle_wire_filter[7]),
        .gt_rx_phy_status_wire_filter(gt_rx_phy_status_wire_filter[7]),
        .gt_rxvalid_q_reg(gt_rxvalid_q_reg_6),
        .gt_rxvalid_q_reg_0(gt_rxvalid_q_reg_14),
        .out1(out[0]),
        .p_0_in7_in(p_0_in7_in_17),
        .p_0_in7_in_0(p_0_in7_in_15),
        .p_1_in8_in(p_1_in8_in_18),
        .p_1_in8_in_1(p_1_in8_in_14),
        .p_2_in(p_2_in_16),
        .p_2_in_2(p_2_in_8),
        .p_2_in_3(p_2_in_3),
        .p_2_in_4(p_2_in_0),
        .p_2_in_5(p_2_in),
        .pclk_sel_reg(CLK_OOBCLK),
        .phy_rdy_n_int_reg(\pipe_lane[7].pipe_user_i_n_5 ),
        .pipe_rxstatus(pipe_rxstatus[23]),
        .pipe_txphaligndone(pipe_txphaligndone[7]),
        .pipe_txphinitdone(pipe_txphinitdone[7:6]),
        .\resetovrd_disble.reset_reg[4]_0 (\pipe_lane[7].gt_wrapper_i_n_16 ),
        .\resetovrd_disble.reset_reg[4]_1 (\pipe_lane[7].gt_wrapper_i_n_6 ),
        .resetovrd_done_reg1_reg(\pipe_lane[7].pipe_user_i_n_18 ),
        .txphaligndone_reg1_reg(\pipe_lane[7].pipe_user_i_n_3 ),
        .txphinitdone_reg1_reg(\pipe_lane[7].pipe_user_i_n_0 ),
        .user_rx_converge(p_53_out));
  PCIeGen1x8If64_PCIeGen1x8If64_pipe_reset \pipe_reset.pipe_reset_i 
       (.D({p_60_out,p_113_out,p_166_out,p_223_out,p_276_out,p_329_out,p_382_out,p_438_out}),
        .RST_CPLLRESET(p_0_in__0),
        .RST_DCLK_RESET(rst_dclk_reset),
        .RST_DRP_START(rst_drp_start),
        .RST_DRP_X16(rst_drp_x16),
        .RST_DRP_X16X20_MODE(rst_drp_x16x20_mode),
        .RST_RXUSRCLK_RESET(rst_rxusrclk_reset),
        .\cfg_wait_cnt_reg[5]_0 (\pipe_reset.pipe_reset_i_n_4 ),
        .done_reg({p_43_out,p_96_out,p_149_out,p_206_out,p_259_out,p_312_out,p_365_out,p_422_out}),
        .out({out[1],rst_txsync_start,out[0]}),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_qrst_idle(pipe_qrst_idle),
        .pipe_rst_fsm(pipe_rst_fsm),
        .rate_idle(rate_idle),
        .reset_n_reg2_reg(reset_n_reg2),
        .\resetovrd_disble.reset_reg[4] (CLK_MMCM_LOCK),
        .\resetovrd_disble.reset_reg[4]_0 (QRST_CPLLLOCK),
        .\resetovrd_disble.reset_reg[4]_1 ({p_25_out,p_78_out,p_131_out,p_184_out,p_241_out,p_294_out,p_347_out,p_400_out}),
        .\resetovrd_disble.reset_reg[4]_2 (CLK_DCLK),
        .rst_cpllpd(rst_cpllpd),
        .rst_gtreset(rst_gtreset),
        .rst_userrdy(rst_userrdy),
        .\rxcdrlock_cnt_reg[3] ({p_58_out,p_111_out,p_164_out,p_221_out,p_274_out,p_327_out,p_380_out,p_436_out}),
        .\txsync_fsm.txsync_done_reg ({p_46_out,p_99_out,p_152_out,p_209_out,p_262_out,p_315_out,p_368_out,p_425_out}),
        .userrdy_reg_rep_0(\pipe_reset.pipe_reset_i_n_17 ),
        .userrdy_reg_rep__0_0(\pipe_reset.pipe_reset_i_n_18 ),
        .userrdy_reg_rep__1_0(\pipe_reset.pipe_reset_i_n_19 ),
        .userrdy_reg_rep__2_0(\pipe_reset.pipe_reset_i_n_20 ),
        .userrdy_reg_rep__3_0(\pipe_reset.pipe_reset_i_n_21 ),
        .userrdy_reg_rep__4_0(\pipe_reset.pipe_reset_i_n_22 ),
        .userrdy_reg_rep__5_0(\pipe_reset.pipe_reset_i_n_23 ));
  PCIeGen1x8If64_PCIeGen1x8If64_qpll_reset \qpll_reset.qpll_reset_i 
       (.D({p_52_out,p_105_out,p_158_out,p_215_out,p_268_out,p_321_out,p_374_out,p_430_out}),
        .done_reg({p_196_out,p_412_out}),
        .pclk_sel_reg(CLK_OOBCLK),
        .pipe_qrst_fsm(pipe_qrst_fsm),
        .pipe_qrst_idle(pipe_qrst_idle),
        .\pipe_stages_1.pipe_tx_rate_q_reg (\pipe_stages_1.pipe_tx_rate_q_reg ),
        .qpllpd(qpllpd),
        .qpllpd_reg_0(QRST_QPLLLOCK[1]),
        .qpllpd_reg_1(QRST_QPLLLOCK[0]),
        .qpllreset_reg_0({p_51_out,p_104_out,p_157_out,p_214_out,p_267_out,p_320_out,p_373_out,p_429_out}),
        .qrst_ovrd(qrst_ovrd),
        .qrst_qpllreset(qrst_qpllreset),
        .reset_n_reg2_reg(\pipe_reset.pipe_reset_i_n_4 ),
        .\resetovrd_disble.reset_reg[4] (QRST_CPLLLOCK),
        .\resetovrd_disble.reset_reg[4]_0 (CLK_MMCM_LOCK),
        .start_reg1_reg(\qpll_reset.qpll_reset_i_n_4 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDCE reset_n_reg1_reg
       (.C(CLK_OOBCLK),
        .CE(1'b1),
        .CLR(reset_n_reg2_reg_0),
        .D(1'b1),
        .Q(reset_n_reg1));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDCE reset_n_reg2_reg
       (.C(CLK_OOBCLK),
        .CE(1'b1),
        .CLR(reset_n_reg2_reg_0),
        .D(reset_n_reg1),
        .Q(reset_n_reg2));
  LUT1 #(
    .INIT(2'h1)) 
    user_lnk_up_int_i_1
       (.I0(sys_rst_n),
        .O(reset_n_reg2_reg_0));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_qpll_drp" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp
   (QPLL_QPLLRESET0,
    DRP_ADDR,
    DRP_DI,
    DRP_DONE,
    qpll_drp_en,
    qpll_drp_we,
    qrst_qpllreset,
    RST_DCLK_RESET,
    DRP_START,
    \resetovrd_disble.reset_reg[4] ,
    DRP_RDY,
    RATE_QPLLLOCK,
    DRP_DO,
    DRP_GEN3,
    DRP_OVRD);
  output QPLL_QPLLRESET0;
  output [7:0]DRP_ADDR;
  output [15:0]DRP_DI;
  output DRP_DONE;
  output qpll_drp_en;
  output qpll_drp_we;
  input qrst_qpllreset;
  input RST_DCLK_RESET;
  input DRP_START;
  input \resetovrd_disble.reset_reg[4] ;
  input DRP_RDY;
  input RATE_QPLLLOCK;
  input [15:0]DRP_DO;
  input DRP_GEN3;
  input DRP_OVRD;

  wire [7:0]DRP_ADDR;
  wire [15:0]DRP_DI;
  wire [15:0]DRP_DO;
  wire DRP_DONE;
  wire DRP_GEN3;
  wire DRP_OVRD;
  wire DRP_RDY;
  wire DRP_START;
  wire QPLL_QPLLRESET0;
  wire RATE_QPLLLOCK;
  wire RST_DCLK_RESET;
  wire [7:0]addr;
  wire \crscode[0]_i_1__0_n_0 ;
  wire \crscode[1]_i_1__0_n_0 ;
  wire \crscode[2]_i_1__0_n_0 ;
  wire \crscode[3]_i_1__0_n_0 ;
  wire \crscode[4]_i_1__0_n_0 ;
  wire \crscode[5]_i_1__0_n_0 ;
  wire \crscode[5]_i_2__0_n_0 ;
  wire \crscode_reg_n_0_[0] ;
  wire \crscode_reg_n_0_[1] ;
  wire \crscode_reg_n_0_[2] ;
  wire \crscode_reg_n_0_[3] ;
  wire \crscode_reg_n_0_[4] ;
  wire \crscode_reg_n_0_[5] ;
  wire [15:0]di;
  wire \di[11]_i_2__0_n_0 ;
  wire \di[12]_i_2__0_n_0 ;
  wire \di[13]_i_2__0_n_0 ;
  wire \di[14]_i_2__0_n_0 ;
  wire \di[15]_i_2__0_n_0 ;
  wire [15:0]do_reg1;
  wire [15:0]do_reg2;
  wire done;
  wire done_i_2__0_n_0;
  wire done_i_3__0_n_0;
  wire [8:0]fsm;
  wire fsm1;
  wire \fsm[0]_i_2__8_n_0 ;
  wire \fsm[1]_i_2__0_n_0 ;
  wire \fsm[8]_i_2__0_n_0 ;
  wire \fsm[8]_i_3__0_n_0 ;
  wire \fsm[8]_i_4__0_n_0 ;
  wire \fsm[8]_i_5__0_n_0 ;
  wire \fsm[8]_i_6__0_n_0 ;
  wire \fsm_reg_n_0_[0] ;
  wire \fsm_reg_n_0_[1] ;
  wire \fsm_reg_n_0_[2] ;
  wire \fsm_reg_n_0_[3] ;
  wire \fsm_reg_n_0_[4] ;
  wire \fsm_reg_n_0_[5] ;
  wire \fsm_reg_n_0_[6] ;
  wire \fsm_reg_n_0_[7] ;
  wire \fsm_reg_n_0_[8] ;
  wire gen3_reg1;
  wire gen3_reg2;
  wire \gtx_common.gtxe2_common_i_i_4__0_n_0 ;
  wire \gtx_common.gtxe2_common_i_i_5__0_n_0 ;
  wire \gtx_common.gtxe2_common_i_i_6__0_n_0 ;
  wire \gtx_common.gtxe2_common_i_i_7__0_n_0 ;
  wire \gtx_common.gtxe2_common_i_i_8__0_n_0 ;
  wire \index[0]_i_1__0_n_0 ;
  wire \index[0]_i_2__0_n_0 ;
  wire \index[0]_i_3__0_n_0 ;
  wire \index[0]_i_4__0_n_0 ;
  wire \index[0]_i_5__0_n_0 ;
  wire \index[1]_i_1__0_n_0 ;
  wire \index[1]_i_2__0_n_0 ;
  wire \index[1]_i_3__0_n_0 ;
  wire \index[2]_i_1__0_n_0 ;
  wire \index[2]_i_2__0_n_0 ;
  wire \index[2]_i_3__0_n_0 ;
  wire \index[2]_i_4__0_n_0 ;
  wire \index[2]_i_5__0_n_0 ;
  wire \index[2]_i_6__0_n_0 ;
  wire \index_reg_n_0_[0] ;
  wire \index_reg_n_0_[1] ;
  wire \index_reg_n_0_[2] ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1__5_n_0 ;
  wire \load_cnt[1]_i_1__0_n_0 ;
  wire \load_cnt[1]_i_2__0_n_0 ;
  wire \load_cnt[1]_i_3__0_n_0 ;
  wire mode_i_1__8_n_0;
  wire mode_i_2__8_n_0;
  wire mode_i_3__0_n_0;
  wire mode_i_4__0_n_0;
  wire mode_i_5__0_n_0;
  wire mode_i_6__0_n_0;
  wire mode_i_7__0_n_0;
  wire mode_i_8__0_n_0;
  wire mode_i_9__0_n_0;
  wire mode_reg_n_0;
  wire ovrd_reg1;
  wire ovrd_reg2;
  wire qpll_drp_en;
  wire qpll_drp_we;
  wire qplllock_reg1;
  wire qplllock_reg2;
  wire qrst_qpllreset;
  wire rdy_reg1;
  wire rdy_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire start_reg1;
  wire start_reg2;

  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \addr[0]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .O(addr[0]));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT3 #(
    .INIT(8'h0D)) 
    \addr[1]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[1] ),
        .O(addr[1]));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT3 #(
    .INIT(8'h2B)) 
    \addr[2]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .O(addr[2]));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \addr[3]_i_1__0 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .O(addr[3]));
  LUT2 #(
    .INIT(4'h7)) 
    \addr[4]_i_1__0 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .O(addr[4]));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \addr[5]_i_1__0 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .O(addr[5]));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \addr[7]_i_1__0 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .O(addr[7]));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[0]),
        .Q(DRP_ADDR[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[1]),
        .Q(DRP_ADDR[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[2]),
        .Q(DRP_ADDR[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[3]),
        .Q(DRP_ADDR[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[4]),
        .Q(DRP_ADDR[4]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[5]),
        .Q(DRP_ADDR[5]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(DRP_ADDR[6]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[7]),
        .Q(DRP_ADDR[7]),
        .R(RST_DCLK_RESET));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[0]_i_1__0 
       (.I0(do_reg2[1]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[0]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[1]_i_1__0 
       (.I0(do_reg2[2]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[1]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[2]_i_1__0 
       (.I0(do_reg2[3]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[2]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[3]_i_1__0 
       (.I0(do_reg2[4]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[3]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[4]_i_1__0 
       (.I0(do_reg2[5]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[4]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hA800)) 
    \crscode[5]_i_1__0 
       (.I0(\index_reg_n_0_[0] ),
        .I1(\index_reg_n_0_[2] ),
        .I2(ovrd_reg2),
        .I3(\index_reg_n_0_[1] ),
        .O(\crscode[5]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[5]_i_2__0 
       (.I0(do_reg2[6]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[5]_i_2__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1__0_n_0 ),
        .D(\crscode[0]_i_1__0_n_0 ),
        .Q(\crscode_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1__0_n_0 ),
        .D(\crscode[1]_i_1__0_n_0 ),
        .Q(\crscode_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1__0_n_0 ),
        .D(\crscode[2]_i_1__0_n_0 ),
        .Q(\crscode_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1__0_n_0 ),
        .D(\crscode[3]_i_1__0_n_0 ),
        .Q(\crscode_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1__0_n_0 ),
        .D(\crscode[4]_i_1__0_n_0 ),
        .Q(\crscode_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1__0_n_0 ),
        .D(\crscode[5]_i_2__0_n_0 ),
        .Q(\crscode_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[0]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[0]),
        .O(di[0]));
  LUT5 #(
    .INIT(32'h5FBF0010)) 
    \di[10]_i_1__0 
       (.I0(\index_reg_n_0_[0] ),
        .I1(\crscode_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\index_reg_n_0_[1] ),
        .I4(do_reg2[10]),
        .O(di[10]));
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \di[11]_i_1__0 
       (.I0(\di[11]_i_2__0_n_0 ),
        .I1(\index_reg_n_0_[2] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(\index_reg_n_0_[1] ),
        .I4(do_reg2[11]),
        .O(di[11]));
  LUT5 #(
    .INIT(32'h0000F909)) 
    \di[11]_i_2__0 
       (.I0(\crscode_reg_n_0_[1] ),
        .I1(\crscode_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(ovrd_reg2),
        .I4(\index_reg_n_0_[1] ),
        .O(\di[11]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0F00FF9F00000090)) 
    \di[12]_i_1__0 
       (.I0(\crscode_reg_n_0_[2] ),
        .I1(\di[12]_i_2__0_n_0 ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\index_reg_n_0_[0] ),
        .I4(\index_reg_n_0_[1] ),
        .I5(do_reg2[12]),
        .O(di[12]));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \di[12]_i_2__0 
       (.I0(\crscode_reg_n_0_[0] ),
        .I1(\crscode_reg_n_0_[1] ),
        .O(\di[12]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h3FBB0388)) 
    \di[13]_i_1__0 
       (.I0(\di[13]_i_2__0_n_0 ),
        .I1(\index_reg_n_0_[2] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(\index_reg_n_0_[1] ),
        .I4(do_reg2[13]),
        .O(di[13]));
  LUT6 #(
    .INIT(64'hBBBBBBB88888888B)) 
    \di[13]_i_2__0 
       (.I0(do_reg2[13]),
        .I1(\index_reg_n_0_[0] ),
        .I2(\crscode_reg_n_0_[2] ),
        .I3(\crscode_reg_n_0_[0] ),
        .I4(\crscode_reg_n_0_[1] ),
        .I5(\crscode_reg_n_0_[3] ),
        .O(\di[13]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h3FFB0308)) 
    \di[14]_i_1__0 
       (.I0(\di[14]_i_2__0_n_0 ),
        .I1(\index_reg_n_0_[2] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(\index_reg_n_0_[1] ),
        .I4(do_reg2[14]),
        .O(di[14]));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \di[14]_i_2__0 
       (.I0(\crscode_reg_n_0_[1] ),
        .I1(\crscode_reg_n_0_[0] ),
        .I2(\crscode_reg_n_0_[2] ),
        .I3(\crscode_reg_n_0_[3] ),
        .I4(\crscode_reg_n_0_[4] ),
        .O(\di[14]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h5FEF0040)) 
    \di[15]_i_1__0 
       (.I0(\index_reg_n_0_[0] ),
        .I1(\di[15]_i_2__0_n_0 ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\index_reg_n_0_[1] ),
        .I4(do_reg2[15]),
        .O(di[15]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \di[15]_i_2__0 
       (.I0(\crscode_reg_n_0_[5] ),
        .I1(\crscode_reg_n_0_[1] ),
        .I2(\crscode_reg_n_0_[0] ),
        .I3(\crscode_reg_n_0_[3] ),
        .I4(\crscode_reg_n_0_[2] ),
        .I5(\crscode_reg_n_0_[4] ),
        .O(\di[15]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[1]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[1]),
        .O(di[1]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[2]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[2]),
        .O(di[2]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[3]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[3]),
        .O(di[3]));
  LUT6 #(
    .INIT(64'h70E070E070F170E0)) 
    \di[4]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(do_reg2[4]),
        .I3(\index_reg_n_0_[0] ),
        .I4(mode_reg_n_0),
        .I5(gen3_reg2),
        .O(di[4]));
  LUT4 #(
    .INIT(16'h70F1)) 
    \di[5]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(do_reg2[5]),
        .I3(\index_reg_n_0_[0] ),
        .O(di[5]));
  LUT6 #(
    .INIT(64'h4DC84DCD4DC84DC8)) 
    \di[6]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(do_reg2[6]),
        .I2(\index_reg_n_0_[1] ),
        .I3(\index_reg_n_0_[0] ),
        .I4(gen3_reg2),
        .I5(mode_reg_n_0),
        .O(di[6]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[7]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[7]),
        .O(di[7]));
  LUT4 #(
    .INIT(16'h70F1)) 
    \di[8]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(do_reg2[8]),
        .I3(\index_reg_n_0_[0] ),
        .O(di[8]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[9]_i_1__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[9]),
        .O(di[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[0]),
        .Q(DRP_DI[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[10]),
        .Q(DRP_DI[10]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[11]),
        .Q(DRP_DI[11]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[12]),
        .Q(DRP_DI[12]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[13]),
        .Q(DRP_DI[13]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[14]),
        .Q(DRP_DI[14]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[15]),
        .Q(DRP_DI[15]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[1]),
        .Q(DRP_DI[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[2]),
        .Q(DRP_DI[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[3]),
        .Q(DRP_DI[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[4]),
        .Q(DRP_DI[4]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[5]),
        .Q(DRP_DI[5]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[6]),
        .Q(DRP_DI[6]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[7]),
        .Q(DRP_DI[7]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[8]),
        .Q(DRP_DI[8]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[9]),
        .Q(DRP_DI[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[0]),
        .Q(do_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[10]),
        .Q(do_reg1[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[11]),
        .Q(do_reg1[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[12]),
        .Q(do_reg1[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[13]),
        .Q(do_reg1[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[14]),
        .Q(do_reg1[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[15]),
        .Q(do_reg1[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[1]),
        .Q(do_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[2]),
        .Q(do_reg1[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[3]),
        .Q(do_reg1[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[4]),
        .Q(do_reg1[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[5]),
        .Q(do_reg1[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[6]),
        .Q(do_reg1[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[7]),
        .Q(do_reg1[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[8]),
        .Q(do_reg1[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[9]),
        .Q(do_reg1[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT4 #(
    .INIT(16'h8088)) 
    done_i_1__8
       (.I0(done_i_2__0_n_0),
        .I1(done_i_3__0_n_0),
        .I2(\fsm_reg_n_0_[4] ),
        .I3(\fsm_reg_n_0_[3] ),
        .O(done));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    done_i_2__0
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[8] ),
        .I3(start_reg2),
        .I4(\fsm_reg_n_0_[7] ),
        .I5(\fsm_reg_n_0_[4] ),
        .O(done_i_2__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT5 #(
    .INIT(32'h0E0E000E)) 
    done_i_3__0
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(\fsm_reg_n_0_[7] ),
        .O(done_i_3__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(done),
        .Q(DRP_DONE),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'hF8F8FFF8FFFFFFFF)) 
    \fsm[0]_i_1__16 
       (.I0(qplllock_reg2),
        .I1(\fsm_reg_n_0_[8] ),
        .I2(\fsm[0]_i_2__8_n_0 ),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(start_reg2),
        .I5(\fsm[8]_i_2__0_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \fsm[0]_i_2__8 
       (.I0(\index_reg_n_0_[0] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(mode_reg_n_0),
        .O(\fsm[0]_i_2__8_n_0 ));
  LUT4 #(
    .INIT(16'hAA08)) 
    \fsm[1]_i_1__8 
       (.I0(\fsm[8]_i_2__0_n_0 ),
        .I1(\fsm_reg_n_0_[6] ),
        .I2(fsm1),
        .I3(\fsm[1]_i_2__0_n_0 ),
        .O(fsm[1]));
  LUT5 #(
    .INIT(32'h8FFF8888)) 
    \fsm[1]_i_2__0 
       (.I0(start_reg2),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(load_cnt[0]),
        .I3(load_cnt[1]),
        .I4(\fsm_reg_n_0_[1] ),
        .O(\fsm[1]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[2]_i_1__16 
       (.I0(\fsm[8]_i_2__0_n_0 ),
        .I1(load_cnt[0]),
        .I2(load_cnt[1]),
        .I3(\fsm_reg_n_0_[1] ),
        .O(fsm[2]));
  LUT4 #(
    .INIT(16'hAA08)) 
    \fsm[3]_i_1__8 
       (.I0(\fsm[8]_i_2__0_n_0 ),
        .I1(\fsm_reg_n_0_[3] ),
        .I2(rdy_reg2),
        .I3(\fsm_reg_n_0_[2] ),
        .O(fsm[3]));
  LUT3 #(
    .INIT(8'h80)) 
    \fsm[4]_i_1__0 
       (.I0(\fsm[8]_i_2__0_n_0 ),
        .I1(rdy_reg2),
        .I2(\fsm_reg_n_0_[3] ),
        .O(fsm[4]));
  LUT4 #(
    .INIT(16'hAA08)) 
    \fsm[5]_i_1__0 
       (.I0(\fsm[8]_i_2__0_n_0 ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(rdy_reg2),
        .I3(\fsm_reg_n_0_[4] ),
        .O(fsm[5]));
  LUT3 #(
    .INIT(8'h80)) 
    \fsm[6]_i_1__0 
       (.I0(\fsm[8]_i_2__0_n_0 ),
        .I1(rdy_reg2),
        .I2(\fsm_reg_n_0_[5] ),
        .O(fsm[6]));
  LUT6 #(
    .INIT(64'hAA80808080808080)) 
    \fsm[7]_i_1__0 
       (.I0(\fsm[8]_i_2__0_n_0 ),
        .I1(\fsm_reg_n_0_[7] ),
        .I2(qplllock_reg2),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(fsm1),
        .I5(mode_reg_n_0),
        .O(fsm[7]));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT4 #(
    .INIT(16'h00E0)) 
    \fsm[7]_i_2__0 
       (.I0(\index_reg_n_0_[2] ),
        .I1(mode_reg_n_0),
        .I2(\index_reg_n_0_[1] ),
        .I3(\index_reg_n_0_[0] ),
        .O(fsm1));
  LUT4 #(
    .INIT(16'h0A08)) 
    \fsm[8]_i_1__0 
       (.I0(\fsm[8]_i_2__0_n_0 ),
        .I1(\fsm_reg_n_0_[8] ),
        .I2(qplllock_reg2),
        .I3(\fsm_reg_n_0_[7] ),
        .O(fsm[8]));
  LUT4 #(
    .INIT(16'h0012)) 
    \fsm[8]_i_2__0 
       (.I0(\fsm[8]_i_3__0_n_0 ),
        .I1(\fsm[8]_i_4__0_n_0 ),
        .I2(\fsm[8]_i_5__0_n_0 ),
        .I3(\fsm[8]_i_6__0_n_0 ),
        .O(\fsm[8]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \fsm[8]_i_3__0 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[3] ),
        .O(\fsm[8]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT4 #(
    .INIT(16'hFEE8)) 
    \fsm[8]_i_4__0 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[3] ),
        .O(\fsm[8]_i_4__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT5 #(
    .INIT(32'h00010116)) 
    \fsm[8]_i_5__0 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[6] ),
        .I3(\fsm_reg_n_0_[7] ),
        .I4(\fsm_reg_n_0_[8] ),
        .O(\fsm[8]_i_5__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT5 #(
    .INIT(32'hFFFEFEE8)) 
    \fsm[8]_i_6__0 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[6] ),
        .I3(\fsm_reg_n_0_[7] ),
        .I4(\fsm_reg_n_0_[8] ),
        .O(\fsm[8]_i_6__0_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \fsm_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(\fsm_reg_n_0_[0] ),
        .S(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(\fsm_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(\fsm_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[3]),
        .Q(\fsm_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[4]),
        .Q(\fsm_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[5]),
        .Q(\fsm_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[6]),
        .Q(\fsm_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[7]),
        .Q(\fsm_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[8]),
        .Q(\fsm_reg_n_0_[8] ),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_GEN3),
        .Q(gen3_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0000000000010100)) 
    \gtx_common.gtxe2_common_i_i_1__0 
       (.I0(\gtx_common.gtxe2_common_i_i_4__0_n_0 ),
        .I1(\gtx_common.gtxe2_common_i_i_5__0_n_0 ),
        .I2(\gtx_common.gtxe2_common_i_i_6__0_n_0 ),
        .I3(\fsm_reg_n_0_[4] ),
        .I4(\fsm_reg_n_0_[2] ),
        .I5(\fsm_reg_n_0_[1] ),
        .O(qpll_drp_en));
  LUT4 #(
    .INIT(16'h1000)) 
    \gtx_common.gtxe2_common_i_i_2__0 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[4] ),
        .I3(\gtx_common.gtxe2_common_i_i_7__0_n_0 ),
        .O(qpll_drp_we));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000010)) 
    \gtx_common.gtxe2_common_i_i_3__0 
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\gtx_common.gtxe2_common_i_i_8__0_n_0 ),
        .I3(\fsm_reg_n_0_[5] ),
        .I4(\fsm_reg_n_0_[8] ),
        .I5(qrst_qpllreset),
        .O(QPLL_QPLLRESET0));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_common.gtxe2_common_i_i_4__0 
       (.I0(\fsm_reg_n_0_[6] ),
        .I1(\fsm_reg_n_0_[7] ),
        .O(\gtx_common.gtxe2_common_i_i_4__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_common.gtxe2_common_i_i_5__0 
       (.I0(\fsm_reg_n_0_[8] ),
        .I1(\fsm_reg_n_0_[5] ),
        .O(\gtx_common.gtxe2_common_i_i_5__0_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_common.gtxe2_common_i_i_6__0 
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[0] ),
        .O(\gtx_common.gtxe2_common_i_i_6__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \gtx_common.gtxe2_common_i_i_7__0 
       (.I0(\fsm_reg_n_0_[6] ),
        .I1(\fsm_reg_n_0_[7] ),
        .I2(\fsm_reg_n_0_[8] ),
        .I3(\fsm_reg_n_0_[5] ),
        .I4(\fsm_reg_n_0_[0] ),
        .I5(\fsm_reg_n_0_[3] ),
        .O(\gtx_common.gtxe2_common_i_i_7__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    \gtx_common.gtxe2_common_i_i_8__0 
       (.I0(\fsm_reg_n_0_[7] ),
        .I1(\fsm_reg_n_0_[4] ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(\fsm_reg_n_0_[2] ),
        .O(\gtx_common.gtxe2_common_i_i_8__0_n_0 ));
  LUT6 #(
    .INIT(64'h0200FFFF02000000)) 
    \index[0]_i_1__0 
       (.I0(\index[0]_i_2__0_n_0 ),
        .I1(\index[0]_i_3__0_n_0 ),
        .I2(\index[0]_i_4__0_n_0 ),
        .I3(\index[0]_i_5__0_n_0 ),
        .I4(\index[2]_i_4__0_n_0 ),
        .I5(\index_reg_n_0_[0] ),
        .O(\index[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \index[0]_i_2__0 
       (.I0(\fsm_reg_n_0_[7] ),
        .I1(\fsm_reg_n_0_[8] ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[2] ),
        .I4(\index_reg_n_0_[0] ),
        .I5(fsm1),
        .O(\index[0]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \index[0]_i_3__0 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .O(\index[0]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \index[0]_i_4__0 
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .O(\index[0]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F2F200F2)) 
    \index[0]_i_5__0 
       (.I0(\fsm_reg_n_0_[6] ),
        .I1(\fsm_reg_n_0_[7] ),
        .I2(\fsm_reg_n_0_[8] ),
        .I3(\fsm_reg_n_0_[3] ),
        .I4(\fsm_reg_n_0_[4] ),
        .I5(\fsm_reg_n_0_[5] ),
        .O(\index[0]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'h0080FFFF80000000)) 
    \index[1]_i_1__0 
       (.I0(\index[1]_i_2__0_n_0 ),
        .I1(\index[1]_i_3__0_n_0 ),
        .I2(\index[2]_i_3__0_n_0 ),
        .I3(\index_reg_n_0_[0] ),
        .I4(\index[2]_i_4__0_n_0 ),
        .I5(\index_reg_n_0_[1] ),
        .O(\index[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \index[1]_i_2__0 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(fsm1),
        .I4(\fsm_reg_n_0_[7] ),
        .I5(\fsm_reg_n_0_[8] ),
        .O(\index[1]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \index[1]_i_3__0 
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[4] ),
        .O(\index[1]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h2A00FFFF80000000)) 
    \index[2]_i_1__0 
       (.I0(\index[2]_i_2__0_n_0 ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[1] ),
        .I3(\index[2]_i_3__0_n_0 ),
        .I4(\index[2]_i_4__0_n_0 ),
        .I5(\index_reg_n_0_[2] ),
        .O(\index[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \index[2]_i_2__0 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[3] ),
        .I3(\index[2]_i_5__0_n_0 ),
        .O(\index[2]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \index[2]_i_3__0 
       (.I0(\fsm_reg_n_0_[8] ),
        .I1(\fsm_reg_n_0_[7] ),
        .I2(\fsm_reg_n_0_[6] ),
        .O(\index[2]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \index[2]_i_4__0 
       (.I0(\index[2]_i_6__0_n_0 ),
        .I1(\fsm_reg_n_0_[7] ),
        .I2(\fsm_reg_n_0_[8] ),
        .I3(\fsm_reg_n_0_[6] ),
        .O(\index[2]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \index[2]_i_5__0 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(fsm1),
        .I4(\fsm_reg_n_0_[7] ),
        .I5(\fsm_reg_n_0_[8] ),
        .O(\index[2]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFEE9)) 
    \index[2]_i_6__0 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[3] ),
        .I3(\fsm_reg_n_0_[2] ),
        .I4(\fsm_reg_n_0_[1] ),
        .I5(\fsm_reg_n_0_[0] ),
        .O(\index[2]_i_6__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\index[0]_i_1__0_n_0 ),
        .Q(\index_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\index[1]_i_1__0_n_0 ),
        .Q(\index_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\index[2]_i_1__0_n_0 ),
        .Q(\index_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0020000000200020)) 
    \load_cnt[0]_i_1__5 
       (.I0(\load_cnt[1]_i_2__0_n_0 ),
        .I1(\load_cnt[1]_i_3__0_n_0 ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[2] ),
        .I4(load_cnt[1]),
        .I5(load_cnt[0]),
        .O(\load_cnt[0]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h0020002000200000)) 
    \load_cnt[1]_i_1__0 
       (.I0(\load_cnt[1]_i_2__0_n_0 ),
        .I1(\load_cnt[1]_i_3__0_n_0 ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[2] ),
        .I4(load_cnt[1]),
        .I5(load_cnt[0]),
        .O(\load_cnt[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \load_cnt[1]_i_2__0 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[3] ),
        .I2(\fsm_reg_n_0_[4] ),
        .O(\load_cnt[1]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \load_cnt[1]_i_3__0 
       (.I0(\fsm_reg_n_0_[7] ),
        .I1(\fsm_reg_n_0_[6] ),
        .I2(\fsm_reg_n_0_[5] ),
        .I3(\fsm_reg_n_0_[8] ),
        .O(\load_cnt[1]_i_3__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__5_n_0 ),
        .Q(load_cnt[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[1]_i_1__0_n_0 ),
        .Q(load_cnt[1]),
        .R(RST_DCLK_RESET));
  LUT5 #(
    .INIT(32'h00200A2A)) 
    mode_i_1__8
       (.I0(mode_reg_n_0),
        .I1(mode_i_2__8_n_0),
        .I2(\fsm_reg_n_0_[8] ),
        .I3(\fsm_reg_n_0_[7] ),
        .I4(mode_i_3__0_n_0),
        .O(mode_i_1__8_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF5D5DFF5D)) 
    mode_i_2__8
       (.I0(\fsm_reg_n_0_[8] ),
        .I1(\fsm_reg_n_0_[6] ),
        .I2(\fsm_reg_n_0_[7] ),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(\fsm_reg_n_0_[1] ),
        .I5(mode_i_4__0_n_0),
        .O(mode_i_2__8_n_0));
  LUT5 #(
    .INIT(32'hF4FFF400)) 
    mode_i_3__0
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(mode_i_5__0_n_0),
        .I3(\fsm_reg_n_0_[7] ),
        .I4(mode_i_6__0_n_0),
        .O(mode_i_3__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    mode_i_4__0
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[4] ),
        .I2(\fsm_reg_n_0_[5] ),
        .I3(\fsm_reg_n_0_[1] ),
        .I4(\fsm_reg_n_0_[2] ),
        .O(mode_i_4__0_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    mode_i_5__0
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[4] ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[5] ),
        .I4(\fsm_reg_n_0_[6] ),
        .I5(\fsm_reg_n_0_[1] ),
        .O(mode_i_5__0_n_0));
  LUT4 #(
    .INIT(16'h8B88)) 
    mode_i_6__0
       (.I0(mode_i_7__0_n_0),
        .I1(\fsm_reg_n_0_[6] ),
        .I2(mode_i_8__0_n_0),
        .I3(mode_i_9__0_n_0),
        .O(mode_i_6__0_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    mode_i_7__0
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[5] ),
        .I4(\fsm_reg_n_0_[4] ),
        .I5(\fsm_reg_n_0_[3] ),
        .O(mode_i_7__0_n_0));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    mode_i_8__0
       (.I0(\fsm_reg_n_0_[5] ),
        .I1(\fsm_reg_n_0_[4] ),
        .I2(\fsm_reg_n_0_[3] ),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(\fsm_reg_n_0_[1] ),
        .I5(\fsm_reg_n_0_[2] ),
        .O(mode_i_8__0_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFFFEED)) 
    mode_i_9__0
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[4] ),
        .I4(\fsm_reg_n_0_[5] ),
        .I5(\fsm_reg_n_0_[3] ),
        .O(mode_i_9__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mode_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(mode_i_1__8_n_0),
        .Q(mode_reg_n_0),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE ovrd_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_OVRD),
        .Q(ovrd_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE ovrd_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ovrd_reg1),
        .Q(ovrd_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(RATE_QPLLLOCK),
        .Q(qplllock_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_RDY),
        .Q(rdy_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_START),
        .Q(start_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(RST_DCLK_RESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_qpll_drp" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_qpll_drp_84
   (QPLL_QPLLRESET0126_out,
    DRP_ADDR,
    DRP_DI,
    DRP_DONE,
    qpll_drp_en,
    qpll_drp_we,
    qrst_qpllreset,
    RST_DCLK_RESET,
    DRP_START,
    \resetovrd_disble.reset_reg[4] ,
    DRP_RDY,
    RATE_QPLLLOCK,
    DRP_DO,
    O1687,
    DRP_OVRD);
  output QPLL_QPLLRESET0126_out;
  output [7:0]DRP_ADDR;
  output [15:0]DRP_DI;
  output DRP_DONE;
  output qpll_drp_en;
  output qpll_drp_we;
  input qrst_qpllreset;
  input RST_DCLK_RESET;
  input DRP_START;
  input \resetovrd_disble.reset_reg[4] ;
  input DRP_RDY;
  input RATE_QPLLLOCK;
  input [15:0]DRP_DO;
  input O1687;
  input DRP_OVRD;

  wire [7:0]DRP_ADDR;
  wire [15:0]DRP_DI;
  wire [15:0]DRP_DO;
  wire DRP_DONE;
  wire DRP_OVRD;
  wire DRP_RDY;
  wire DRP_START;
  wire O1687;
  wire QPLL_QPLLRESET0126_out;
  wire RATE_QPLLLOCK;
  wire RST_DCLK_RESET;
  wire [7:0]addr;
  wire \crscode[0]_i_1_n_0 ;
  wire \crscode[1]_i_1_n_0 ;
  wire \crscode[2]_i_1_n_0 ;
  wire \crscode[3]_i_1_n_0 ;
  wire \crscode[4]_i_1_n_0 ;
  wire \crscode[5]_i_1_n_0 ;
  wire \crscode[5]_i_2_n_0 ;
  wire \crscode_reg_n_0_[0] ;
  wire \crscode_reg_n_0_[1] ;
  wire \crscode_reg_n_0_[2] ;
  wire \crscode_reg_n_0_[3] ;
  wire \crscode_reg_n_0_[4] ;
  wire \crscode_reg_n_0_[5] ;
  wire [15:0]di;
  wire \di[11]_i_2_n_0 ;
  wire \di[12]_i_2_n_0 ;
  wire \di[13]_i_2_n_0 ;
  wire \di[14]_i_2_n_0 ;
  wire \di[15]_i_2_n_0 ;
  wire [15:0]do_reg1;
  wire [15:0]do_reg2;
  wire done;
  wire done_i_2_n_0;
  wire done_i_3_n_0;
  wire [8:0]fsm;
  wire fsm1;
  wire \fsm[0]_i_2__7_n_0 ;
  wire \fsm[1]_i_2_n_0 ;
  wire \fsm[8]_i_2_n_0 ;
  wire \fsm[8]_i_3_n_0 ;
  wire \fsm[8]_i_4_n_0 ;
  wire \fsm[8]_i_5_n_0 ;
  wire \fsm[8]_i_6_n_0 ;
  wire \fsm_reg_n_0_[0] ;
  wire \fsm_reg_n_0_[1] ;
  wire \fsm_reg_n_0_[2] ;
  wire \fsm_reg_n_0_[3] ;
  wire \fsm_reg_n_0_[4] ;
  wire \fsm_reg_n_0_[5] ;
  wire \fsm_reg_n_0_[6] ;
  wire \fsm_reg_n_0_[7] ;
  wire \fsm_reg_n_0_[8] ;
  wire gen3_reg1;
  wire gen3_reg2;
  wire \gtx_common.gtxe2_common_i_i_4_n_0 ;
  wire \gtx_common.gtxe2_common_i_i_5_n_0 ;
  wire \gtx_common.gtxe2_common_i_i_6_n_0 ;
  wire \gtx_common.gtxe2_common_i_i_7_n_0 ;
  wire \gtx_common.gtxe2_common_i_i_8_n_0 ;
  wire \index[0]_i_1_n_0 ;
  wire \index[0]_i_2_n_0 ;
  wire \index[0]_i_3_n_0 ;
  wire \index[0]_i_4_n_0 ;
  wire \index[0]_i_5_n_0 ;
  wire \index[1]_i_1_n_0 ;
  wire \index[1]_i_2_n_0 ;
  wire \index[1]_i_3_n_0 ;
  wire \index[2]_i_1_n_0 ;
  wire \index[2]_i_2_n_0 ;
  wire \index[2]_i_3_n_0 ;
  wire \index[2]_i_4_n_0 ;
  wire \index[2]_i_5_n_0 ;
  wire \index[2]_i_6_n_0 ;
  wire \index_reg_n_0_[0] ;
  wire \index_reg_n_0_[1] ;
  wire \index_reg_n_0_[2] ;
  wire [1:0]load_cnt;
  wire \load_cnt[0]_i_1__0_n_0 ;
  wire \load_cnt[1]_i_1_n_0 ;
  wire \load_cnt[1]_i_2_n_0 ;
  wire \load_cnt[1]_i_3_n_0 ;
  wire mode_i_1__7_n_0;
  wire mode_i_2__7_n_0;
  wire mode_i_3_n_0;
  wire mode_i_4_n_0;
  wire mode_i_5_n_0;
  wire mode_i_6_n_0;
  wire mode_i_7_n_0;
  wire mode_i_8_n_0;
  wire mode_i_9_n_0;
  wire mode_reg_n_0;
  wire ovrd_reg1;
  wire ovrd_reg2;
  wire qpll_drp_en;
  wire qpll_drp_we;
  wire qplllock_reg1;
  wire qplllock_reg2;
  wire qrst_qpllreset;
  wire rdy_reg1;
  wire rdy_reg2;
  wire \resetovrd_disble.reset_reg[4] ;
  wire start_reg1;
  wire start_reg2;

  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \addr[0]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .O(addr[0]));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'h0D)) 
    \addr[1]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[1] ),
        .O(addr[1]));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'h2B)) 
    \addr[2]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .O(addr[2]));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \addr[3]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .O(addr[3]));
  LUT2 #(
    .INIT(4'h7)) 
    \addr[4]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .O(addr[4]));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \addr[5]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .O(addr[5]));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \addr[7]_i_1 
       (.I0(\index_reg_n_0_[1] ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .O(addr[7]));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[0]),
        .Q(DRP_ADDR[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[1]),
        .Q(DRP_ADDR[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[2]),
        .Q(DRP_ADDR[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[3]),
        .Q(DRP_ADDR[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[4]),
        .Q(DRP_ADDR[4]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[5]),
        .Q(DRP_ADDR[5]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(1'b0),
        .Q(DRP_ADDR[6]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \addr_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(addr[7]),
        .Q(DRP_ADDR[7]),
        .R(RST_DCLK_RESET));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[0]_i_1 
       (.I0(do_reg2[1]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[1]_i_1 
       (.I0(do_reg2[2]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[1]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[2]_i_1 
       (.I0(do_reg2[3]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[3]_i_1 
       (.I0(do_reg2[4]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[4]_i_1 
       (.I0(do_reg2[5]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hA800)) 
    \crscode[5]_i_1 
       (.I0(\index_reg_n_0_[0] ),
        .I1(\index_reg_n_0_[2] ),
        .I2(ovrd_reg2),
        .I3(\index_reg_n_0_[1] ),
        .O(\crscode[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \crscode[5]_i_2 
       (.I0(do_reg2[6]),
        .I1(\index_reg_n_0_[2] ),
        .O(\crscode[5]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1_n_0 ),
        .D(\crscode[0]_i_1_n_0 ),
        .Q(\crscode_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1_n_0 ),
        .D(\crscode[1]_i_1_n_0 ),
        .Q(\crscode_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1_n_0 ),
        .D(\crscode[2]_i_1_n_0 ),
        .Q(\crscode_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1_n_0 ),
        .D(\crscode[3]_i_1_n_0 ),
        .Q(\crscode_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1_n_0 ),
        .D(\crscode[4]_i_1_n_0 ),
        .Q(\crscode_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \crscode_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(\crscode[5]_i_1_n_0 ),
        .D(\crscode[5]_i_2_n_0 ),
        .Q(\crscode_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[0]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[0]),
        .O(di[0]));
  LUT5 #(
    .INIT(32'h5FBF0010)) 
    \di[10]_i_1 
       (.I0(\index_reg_n_0_[0] ),
        .I1(\crscode_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\index_reg_n_0_[1] ),
        .I4(do_reg2[10]),
        .O(di[10]));
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \di[11]_i_1 
       (.I0(\di[11]_i_2_n_0 ),
        .I1(\index_reg_n_0_[2] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(\index_reg_n_0_[1] ),
        .I4(do_reg2[11]),
        .O(di[11]));
  LUT5 #(
    .INIT(32'h0000F909)) 
    \di[11]_i_2 
       (.I0(\crscode_reg_n_0_[1] ),
        .I1(\crscode_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(ovrd_reg2),
        .I4(\index_reg_n_0_[1] ),
        .O(\di[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0F00FF9F00000090)) 
    \di[12]_i_1 
       (.I0(\crscode_reg_n_0_[2] ),
        .I1(\di[12]_i_2_n_0 ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\index_reg_n_0_[0] ),
        .I4(\index_reg_n_0_[1] ),
        .I5(do_reg2[12]),
        .O(di[12]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \di[12]_i_2 
       (.I0(\crscode_reg_n_0_[0] ),
        .I1(\crscode_reg_n_0_[1] ),
        .O(\di[12]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h3FBB0388)) 
    \di[13]_i_1 
       (.I0(\di[13]_i_2_n_0 ),
        .I1(\index_reg_n_0_[2] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(\index_reg_n_0_[1] ),
        .I4(do_reg2[13]),
        .O(di[13]));
  LUT6 #(
    .INIT(64'hBBBBBBB88888888B)) 
    \di[13]_i_2 
       (.I0(do_reg2[13]),
        .I1(\index_reg_n_0_[0] ),
        .I2(\crscode_reg_n_0_[2] ),
        .I3(\crscode_reg_n_0_[0] ),
        .I4(\crscode_reg_n_0_[1] ),
        .I5(\crscode_reg_n_0_[3] ),
        .O(\di[13]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h3FFB0308)) 
    \di[14]_i_1 
       (.I0(\di[14]_i_2_n_0 ),
        .I1(\index_reg_n_0_[2] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(\index_reg_n_0_[1] ),
        .I4(do_reg2[14]),
        .O(di[14]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \di[14]_i_2 
       (.I0(\crscode_reg_n_0_[1] ),
        .I1(\crscode_reg_n_0_[0] ),
        .I2(\crscode_reg_n_0_[2] ),
        .I3(\crscode_reg_n_0_[3] ),
        .I4(\crscode_reg_n_0_[4] ),
        .O(\di[14]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h5FEF0040)) 
    \di[15]_i_1 
       (.I0(\index_reg_n_0_[0] ),
        .I1(\di[15]_i_2_n_0 ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\index_reg_n_0_[1] ),
        .I4(do_reg2[15]),
        .O(di[15]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \di[15]_i_2 
       (.I0(\crscode_reg_n_0_[5] ),
        .I1(\crscode_reg_n_0_[1] ),
        .I2(\crscode_reg_n_0_[0] ),
        .I3(\crscode_reg_n_0_[3] ),
        .I4(\crscode_reg_n_0_[2] ),
        .I5(\crscode_reg_n_0_[4] ),
        .O(\di[15]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[1]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[1]),
        .O(di[1]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[2]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[2]),
        .O(di[2]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[3]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[3]),
        .O(di[3]));
  LUT6 #(
    .INIT(64'h70E070E070F170E0)) 
    \di[4]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(do_reg2[4]),
        .I3(\index_reg_n_0_[0] ),
        .I4(mode_reg_n_0),
        .I5(gen3_reg2),
        .O(di[4]));
  LUT4 #(
    .INIT(16'h70F1)) 
    \di[5]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(do_reg2[5]),
        .I3(\index_reg_n_0_[0] ),
        .O(di[5]));
  LUT6 #(
    .INIT(64'h4DC84DCD4DC84DC8)) 
    \di[6]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(do_reg2[6]),
        .I2(\index_reg_n_0_[1] ),
        .I3(\index_reg_n_0_[0] ),
        .I4(gen3_reg2),
        .I5(mode_reg_n_0),
        .O(di[6]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[7]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[7]),
        .O(di[7]));
  LUT4 #(
    .INIT(16'h70F1)) 
    \di[8]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(do_reg2[8]),
        .I3(\index_reg_n_0_[0] ),
        .O(di[8]));
  LUT4 #(
    .INIT(16'h7E00)) 
    \di[9]_i_1 
       (.I0(\index_reg_n_0_[2] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[0] ),
        .I3(do_reg2[9]),
        .O(di[9]));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[0]),
        .Q(DRP_DI[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[10]),
        .Q(DRP_DI[10]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[11]),
        .Q(DRP_DI[11]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[12]),
        .Q(DRP_DI[12]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[13]),
        .Q(DRP_DI[13]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[14]),
        .Q(DRP_DI[14]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[15]),
        .Q(DRP_DI[15]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[1]),
        .Q(DRP_DI[1]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[2]),
        .Q(DRP_DI[2]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[3]),
        .Q(DRP_DI[3]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[4]),
        .Q(DRP_DI[4]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[5]),
        .Q(DRP_DI[5]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[6]),
        .Q(DRP_DI[6]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[7]),
        .Q(DRP_DI[7]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[8]),
        .Q(DRP_DI[8]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \di_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(di[9]),
        .Q(DRP_DI[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[0]),
        .Q(do_reg1[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[10]),
        .Q(do_reg1[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[11]),
        .Q(do_reg1[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[12]),
        .Q(do_reg1[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[13]),
        .Q(do_reg1[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[14]),
        .Q(do_reg1[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[15]),
        .Q(do_reg1[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[1]),
        .Q(do_reg1[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[2]),
        .Q(do_reg1[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[3]),
        .Q(do_reg1[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[4]),
        .Q(do_reg1[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[5]),
        .Q(do_reg1[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[6]),
        .Q(do_reg1[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[7]),
        .Q(do_reg1[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[8]),
        .Q(do_reg1[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg1_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_DO[9]),
        .Q(do_reg1[9]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[0]),
        .Q(do_reg2[0]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[10] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[10]),
        .Q(do_reg2[10]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[11] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[11]),
        .Q(do_reg2[11]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[12] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[12]),
        .Q(do_reg2[12]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[13] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[13]),
        .Q(do_reg2[13]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[14] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[14]),
        .Q(do_reg2[14]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[15] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[15]),
        .Q(do_reg2[15]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[1]),
        .Q(do_reg2[1]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[2]),
        .Q(do_reg2[2]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[3]),
        .Q(do_reg2[3]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[4]),
        .Q(do_reg2[4]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[5]),
        .Q(do_reg2[5]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[6]),
        .Q(do_reg2[6]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[7]),
        .Q(do_reg2[7]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[8]),
        .Q(do_reg2[8]),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \do_reg2_reg[9] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(do_reg1[9]),
        .Q(do_reg2[9]),
        .R(RST_DCLK_RESET));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'h8088)) 
    done_i_1__7
       (.I0(done_i_2_n_0),
        .I1(done_i_3_n_0),
        .I2(\fsm_reg_n_0_[4] ),
        .I3(\fsm_reg_n_0_[3] ),
        .O(done));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    done_i_2
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[8] ),
        .I3(start_reg2),
        .I4(\fsm_reg_n_0_[7] ),
        .I5(\fsm_reg_n_0_[4] ),
        .O(done_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT5 #(
    .INIT(32'h0E0E000E)) 
    done_i_3
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(\fsm_reg_n_0_[7] ),
        .O(done_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    done_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(done),
        .Q(DRP_DONE),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'hF8F8FFF8FFFFFFFF)) 
    \fsm[0]_i_1__15 
       (.I0(qplllock_reg2),
        .I1(\fsm_reg_n_0_[8] ),
        .I2(\fsm[0]_i_2__7_n_0 ),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(start_reg2),
        .I5(\fsm[8]_i_2_n_0 ),
        .O(fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \fsm[0]_i_2__7 
       (.I0(\index_reg_n_0_[0] ),
        .I1(\index_reg_n_0_[1] ),
        .I2(\index_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(mode_reg_n_0),
        .O(\fsm[0]_i_2__7_n_0 ));
  LUT4 #(
    .INIT(16'hAA08)) 
    \fsm[1]_i_1__7 
       (.I0(\fsm[8]_i_2_n_0 ),
        .I1(\fsm_reg_n_0_[6] ),
        .I2(fsm1),
        .I3(\fsm[1]_i_2_n_0 ),
        .O(fsm[1]));
  LUT5 #(
    .INIT(32'h8FFF8888)) 
    \fsm[1]_i_2 
       (.I0(start_reg2),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(load_cnt[0]),
        .I3(load_cnt[1]),
        .I4(\fsm_reg_n_0_[1] ),
        .O(\fsm[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \fsm[2]_i_1__15 
       (.I0(\fsm[8]_i_2_n_0 ),
        .I1(load_cnt[0]),
        .I2(load_cnt[1]),
        .I3(\fsm_reg_n_0_[1] ),
        .O(fsm[2]));
  LUT4 #(
    .INIT(16'hAA08)) 
    \fsm[3]_i_1__7 
       (.I0(\fsm[8]_i_2_n_0 ),
        .I1(\fsm_reg_n_0_[3] ),
        .I2(rdy_reg2),
        .I3(\fsm_reg_n_0_[2] ),
        .O(fsm[3]));
  LUT3 #(
    .INIT(8'h80)) 
    \fsm[4]_i_1 
       (.I0(\fsm[8]_i_2_n_0 ),
        .I1(rdy_reg2),
        .I2(\fsm_reg_n_0_[3] ),
        .O(fsm[4]));
  LUT4 #(
    .INIT(16'hAA08)) 
    \fsm[5]_i_1 
       (.I0(\fsm[8]_i_2_n_0 ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(rdy_reg2),
        .I3(\fsm_reg_n_0_[4] ),
        .O(fsm[5]));
  LUT3 #(
    .INIT(8'h80)) 
    \fsm[6]_i_1 
       (.I0(\fsm[8]_i_2_n_0 ),
        .I1(rdy_reg2),
        .I2(\fsm_reg_n_0_[5] ),
        .O(fsm[6]));
  LUT6 #(
    .INIT(64'hAA80808080808080)) 
    \fsm[7]_i_1 
       (.I0(\fsm[8]_i_2_n_0 ),
        .I1(\fsm_reg_n_0_[7] ),
        .I2(qplllock_reg2),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(fsm1),
        .I5(mode_reg_n_0),
        .O(fsm[7]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT4 #(
    .INIT(16'h00E0)) 
    \fsm[7]_i_2 
       (.I0(\index_reg_n_0_[2] ),
        .I1(mode_reg_n_0),
        .I2(\index_reg_n_0_[1] ),
        .I3(\index_reg_n_0_[0] ),
        .O(fsm1));
  LUT4 #(
    .INIT(16'h0A08)) 
    \fsm[8]_i_1 
       (.I0(\fsm[8]_i_2_n_0 ),
        .I1(\fsm_reg_n_0_[8] ),
        .I2(qplllock_reg2),
        .I3(\fsm_reg_n_0_[7] ),
        .O(fsm[8]));
  LUT4 #(
    .INIT(16'h0012)) 
    \fsm[8]_i_2 
       (.I0(\fsm[8]_i_3_n_0 ),
        .I1(\fsm[8]_i_4_n_0 ),
        .I2(\fsm[8]_i_5_n_0 ),
        .I3(\fsm[8]_i_6_n_0 ),
        .O(\fsm[8]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \fsm[8]_i_3 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[3] ),
        .O(\fsm[8]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT4 #(
    .INIT(16'hFEE8)) 
    \fsm[8]_i_4 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[3] ),
        .O(\fsm[8]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'h00010116)) 
    \fsm[8]_i_5 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[6] ),
        .I3(\fsm_reg_n_0_[7] ),
        .I4(\fsm_reg_n_0_[8] ),
        .O(\fsm[8]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'hFFFEFEE8)) 
    \fsm[8]_i_6 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[6] ),
        .I3(\fsm_reg_n_0_[7] ),
        .I4(\fsm_reg_n_0_[8] ),
        .O(\fsm[8]_i_6_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \fsm_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[0]),
        .Q(\fsm_reg_n_0_[0] ),
        .S(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[1]),
        .Q(\fsm_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[2]),
        .Q(\fsm_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[3] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[3]),
        .Q(\fsm_reg_n_0_[3] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[4] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[4]),
        .Q(\fsm_reg_n_0_[4] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[5] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[5]),
        .Q(\fsm_reg_n_0_[5] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[6] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[6]),
        .Q(\fsm_reg_n_0_[6] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[7] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[7]),
        .Q(\fsm_reg_n_0_[7] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \fsm_reg[8] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(fsm[8]),
        .Q(\fsm_reg_n_0_[8] ),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(O1687),
        .Q(gen3_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE gen3_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(gen3_reg1),
        .Q(gen3_reg2),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0000000000010100)) 
    \gtx_common.gtxe2_common_i_i_1 
       (.I0(\gtx_common.gtxe2_common_i_i_4_n_0 ),
        .I1(\gtx_common.gtxe2_common_i_i_5_n_0 ),
        .I2(\gtx_common.gtxe2_common_i_i_6_n_0 ),
        .I3(\fsm_reg_n_0_[4] ),
        .I4(\fsm_reg_n_0_[2] ),
        .I5(\fsm_reg_n_0_[1] ),
        .O(qpll_drp_en));
  LUT4 #(
    .INIT(16'h1000)) 
    \gtx_common.gtxe2_common_i_i_2 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[4] ),
        .I3(\gtx_common.gtxe2_common_i_i_7_n_0 ),
        .O(qpll_drp_we));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000010)) 
    \gtx_common.gtxe2_common_i_i_3 
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\gtx_common.gtxe2_common_i_i_8_n_0 ),
        .I3(\fsm_reg_n_0_[5] ),
        .I4(\fsm_reg_n_0_[8] ),
        .I5(qrst_qpllreset),
        .O(QPLL_QPLLRESET0126_out));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_common.gtxe2_common_i_i_4 
       (.I0(\fsm_reg_n_0_[6] ),
        .I1(\fsm_reg_n_0_[7] ),
        .O(\gtx_common.gtxe2_common_i_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_common.gtxe2_common_i_i_5 
       (.I0(\fsm_reg_n_0_[8] ),
        .I1(\fsm_reg_n_0_[5] ),
        .O(\gtx_common.gtxe2_common_i_i_5_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \gtx_common.gtxe2_common_i_i_6 
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[0] ),
        .O(\gtx_common.gtxe2_common_i_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \gtx_common.gtxe2_common_i_i_7 
       (.I0(\fsm_reg_n_0_[6] ),
        .I1(\fsm_reg_n_0_[7] ),
        .I2(\fsm_reg_n_0_[8] ),
        .I3(\fsm_reg_n_0_[5] ),
        .I4(\fsm_reg_n_0_[0] ),
        .I5(\fsm_reg_n_0_[3] ),
        .O(\gtx_common.gtxe2_common_i_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    \gtx_common.gtxe2_common_i_i_8 
       (.I0(\fsm_reg_n_0_[7] ),
        .I1(\fsm_reg_n_0_[4] ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[6] ),
        .I4(\fsm_reg_n_0_[2] ),
        .O(\gtx_common.gtxe2_common_i_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0200FFFF02000000)) 
    \index[0]_i_1 
       (.I0(\index[0]_i_2_n_0 ),
        .I1(\index[0]_i_3_n_0 ),
        .I2(\index[0]_i_4_n_0 ),
        .I3(\index[0]_i_5_n_0 ),
        .I4(\index[2]_i_4_n_0 ),
        .I5(\index_reg_n_0_[0] ),
        .O(\index[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \index[0]_i_2 
       (.I0(\fsm_reg_n_0_[7] ),
        .I1(\fsm_reg_n_0_[8] ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[2] ),
        .I4(\index_reg_n_0_[0] ),
        .I5(fsm1),
        .O(\index[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \index[0]_i_3 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .O(\index[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \index[0]_i_4 
       (.I0(\fsm_reg_n_0_[2] ),
        .I1(\fsm_reg_n_0_[1] ),
        .I2(\fsm_reg_n_0_[0] ),
        .O(\index[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F2F200F2)) 
    \index[0]_i_5 
       (.I0(\fsm_reg_n_0_[6] ),
        .I1(\fsm_reg_n_0_[7] ),
        .I2(\fsm_reg_n_0_[8] ),
        .I3(\fsm_reg_n_0_[3] ),
        .I4(\fsm_reg_n_0_[4] ),
        .I5(\fsm_reg_n_0_[5] ),
        .O(\index[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0080FFFF80000000)) 
    \index[1]_i_1 
       (.I0(\index[1]_i_2_n_0 ),
        .I1(\index[1]_i_3_n_0 ),
        .I2(\index[2]_i_3_n_0 ),
        .I3(\index_reg_n_0_[0] ),
        .I4(\index[2]_i_4_n_0 ),
        .I5(\index_reg_n_0_[1] ),
        .O(\index[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \index[1]_i_2 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(fsm1),
        .I4(\fsm_reg_n_0_[7] ),
        .I5(\fsm_reg_n_0_[8] ),
        .O(\index[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \index[1]_i_3 
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[4] ),
        .O(\index[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h2A00FFFF80000000)) 
    \index[2]_i_1 
       (.I0(\index[2]_i_2_n_0 ),
        .I1(\index_reg_n_0_[0] ),
        .I2(\index_reg_n_0_[1] ),
        .I3(\index[2]_i_3_n_0 ),
        .I4(\index[2]_i_4_n_0 ),
        .I5(\index_reg_n_0_[2] ),
        .O(\index[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \index[2]_i_2 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[3] ),
        .I3(\index[2]_i_5_n_0 ),
        .O(\index[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \index[2]_i_3 
       (.I0(\fsm_reg_n_0_[8] ),
        .I1(\fsm_reg_n_0_[7] ),
        .I2(\fsm_reg_n_0_[6] ),
        .O(\index[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \index[2]_i_4 
       (.I0(\index[2]_i_6_n_0 ),
        .I1(\fsm_reg_n_0_[7] ),
        .I2(\fsm_reg_n_0_[8] ),
        .I3(\fsm_reg_n_0_[6] ),
        .O(\index[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \index[2]_i_5 
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[0] ),
        .I3(fsm1),
        .I4(\fsm_reg_n_0_[7] ),
        .I5(\fsm_reg_n_0_[8] ),
        .O(\index[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFEE9)) 
    \index[2]_i_6 
       (.I0(\fsm_reg_n_0_[4] ),
        .I1(\fsm_reg_n_0_[5] ),
        .I2(\fsm_reg_n_0_[3] ),
        .I3(\fsm_reg_n_0_[2] ),
        .I4(\fsm_reg_n_0_[1] ),
        .I5(\fsm_reg_n_0_[0] ),
        .O(\index[2]_i_6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\index[0]_i_1_n_0 ),
        .Q(\index_reg_n_0_[0] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\index[1]_i_1_n_0 ),
        .Q(\index_reg_n_0_[1] ),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \index_reg[2] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\index[2]_i_1_n_0 ),
        .Q(\index_reg_n_0_[2] ),
        .R(RST_DCLK_RESET));
  LUT6 #(
    .INIT(64'h0020000000200020)) 
    \load_cnt[0]_i_1__0 
       (.I0(\load_cnt[1]_i_2_n_0 ),
        .I1(\load_cnt[1]_i_3_n_0 ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[2] ),
        .I4(load_cnt[1]),
        .I5(load_cnt[0]),
        .O(\load_cnt[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0020002000200000)) 
    \load_cnt[1]_i_1 
       (.I0(\load_cnt[1]_i_2_n_0 ),
        .I1(\load_cnt[1]_i_3_n_0 ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[2] ),
        .I4(load_cnt[1]),
        .I5(load_cnt[0]),
        .O(\load_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \load_cnt[1]_i_2 
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[3] ),
        .I2(\fsm_reg_n_0_[4] ),
        .O(\load_cnt[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \load_cnt[1]_i_3 
       (.I0(\fsm_reg_n_0_[7] ),
        .I1(\fsm_reg_n_0_[6] ),
        .I2(\fsm_reg_n_0_[5] ),
        .I3(\fsm_reg_n_0_[8] ),
        .O(\load_cnt[1]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[0] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[0]_i_1__0_n_0 ),
        .Q(load_cnt[0]),
        .R(RST_DCLK_RESET));
  FDRE #(
    .INIT(1'b0)) 
    \load_cnt_reg[1] 
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(\load_cnt[1]_i_1_n_0 ),
        .Q(load_cnt[1]),
        .R(RST_DCLK_RESET));
  LUT5 #(
    .INIT(32'h00200A2A)) 
    mode_i_1__7
       (.I0(mode_reg_n_0),
        .I1(mode_i_2__7_n_0),
        .I2(\fsm_reg_n_0_[8] ),
        .I3(\fsm_reg_n_0_[7] ),
        .I4(mode_i_3_n_0),
        .O(mode_i_1__7_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF5D5DFF5D)) 
    mode_i_2__7
       (.I0(\fsm_reg_n_0_[8] ),
        .I1(\fsm_reg_n_0_[6] ),
        .I2(\fsm_reg_n_0_[7] ),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(\fsm_reg_n_0_[1] ),
        .I5(mode_i_4_n_0),
        .O(mode_i_2__7_n_0));
  LUT5 #(
    .INIT(32'hF4FFF400)) 
    mode_i_3
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(mode_i_5_n_0),
        .I3(\fsm_reg_n_0_[7] ),
        .I4(mode_i_6_n_0),
        .O(mode_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    mode_i_4
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[4] ),
        .I2(\fsm_reg_n_0_[5] ),
        .I3(\fsm_reg_n_0_[1] ),
        .I4(\fsm_reg_n_0_[2] ),
        .O(mode_i_4_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    mode_i_5
       (.I0(\fsm_reg_n_0_[3] ),
        .I1(\fsm_reg_n_0_[4] ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[5] ),
        .I4(\fsm_reg_n_0_[6] ),
        .I5(\fsm_reg_n_0_[1] ),
        .O(mode_i_5_n_0));
  LUT4 #(
    .INIT(16'h8B88)) 
    mode_i_6
       (.I0(mode_i_7_n_0),
        .I1(\fsm_reg_n_0_[6] ),
        .I2(mode_i_8_n_0),
        .I3(mode_i_9_n_0),
        .O(mode_i_6_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    mode_i_7
       (.I0(\fsm_reg_n_0_[0] ),
        .I1(\fsm_reg_n_0_[2] ),
        .I2(\fsm_reg_n_0_[1] ),
        .I3(\fsm_reg_n_0_[5] ),
        .I4(\fsm_reg_n_0_[4] ),
        .I5(\fsm_reg_n_0_[3] ),
        .O(mode_i_7_n_0));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    mode_i_8
       (.I0(\fsm_reg_n_0_[5] ),
        .I1(\fsm_reg_n_0_[4] ),
        .I2(\fsm_reg_n_0_[3] ),
        .I3(\fsm_reg_n_0_[0] ),
        .I4(\fsm_reg_n_0_[1] ),
        .I5(\fsm_reg_n_0_[2] ),
        .O(mode_i_8_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFFFEED)) 
    mode_i_9
       (.I0(\fsm_reg_n_0_[1] ),
        .I1(\fsm_reg_n_0_[0] ),
        .I2(\fsm_reg_n_0_[2] ),
        .I3(\fsm_reg_n_0_[4] ),
        .I4(\fsm_reg_n_0_[5] ),
        .I5(\fsm_reg_n_0_[3] ),
        .O(mode_i_9_n_0));
  FDRE #(
    .INIT(1'b0)) 
    mode_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(mode_i_1__7_n_0),
        .Q(mode_reg_n_0),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE ovrd_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_OVRD),
        .Q(ovrd_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE ovrd_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(ovrd_reg1),
        .Q(ovrd_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(RATE_QPLLLOCK),
        .Q(qplllock_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE qplllock_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(qplllock_reg1),
        .Q(qplllock_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_RDY),
        .Q(rdy_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE rdy_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(rdy_reg1),
        .Q(rdy_reg2),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg1_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(DRP_START),
        .Q(start_reg1),
        .R(RST_DCLK_RESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE start_reg2_reg
       (.C(\resetovrd_disble.reset_reg[4] ),
        .CE(1'b1),
        .D(start_reg1),
        .Q(start_reg2),
        .R(RST_DCLK_RESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_qpll_reset" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_qpll_reset
   (pipe_qrst_fsm,
    start_reg1_reg,
    pipe_qrst_idle,
    qpllpd,
    qrst_qpllreset,
    qrst_ovrd,
    reset_n_reg2_reg,
    pclk_sel_reg,
    D,
    \pipe_stages_1.pipe_tx_rate_q_reg ,
    done_reg,
    qpllreset_reg_0,
    qpllpd_reg_0,
    qpllpd_reg_1,
    \resetovrd_disble.reset_reg[4] ,
    \resetovrd_disble.reset_reg[4]_0 );
  output [3:0]pipe_qrst_fsm;
  output start_reg1_reg;
  output pipe_qrst_idle;
  output qpllpd;
  output qrst_qpllreset;
  output qrst_ovrd;
  input reset_n_reg2_reg;
  input pclk_sel_reg;
  input [7:0]D;
  input [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  input [1:0]done_reg;
  input [7:0]qpllreset_reg_0;
  input qpllpd_reg_0;
  input qpllpd_reg_1;
  input [7:0]\resetovrd_disble.reset_reg[4] ;
  input \resetovrd_disble.reset_reg[4]_0 ;

  wire [7:0]D;
  wire \FSM_sequential_fsm[0]_i_1_n_0 ;
  wire \FSM_sequential_fsm[0]_i_2_n_0 ;
  wire \FSM_sequential_fsm[0]_i_3_n_0 ;
  wire \FSM_sequential_fsm[0]_i_4_n_0 ;
  wire \FSM_sequential_fsm[0]_i_5_n_0 ;
  wire \FSM_sequential_fsm[1]_i_1_n_0 ;
  wire \FSM_sequential_fsm[1]_i_2_n_0 ;
  wire \FSM_sequential_fsm[1]_i_3_n_0 ;
  wire \FSM_sequential_fsm[2]_i_1_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_sequential_fsm_reg_n_0_[2] ;
  wire [7:0]cplllock_reg1;
  wire [7:0]cplllock_reg2;
  wire [1:0]done_reg;
  wire [1:0]drp_done_reg1;
  wire [1:0]drp_done_reg2;
  wire mmcm_lock_reg1;
  wire mmcm_lock_reg2;
  wire pclk_sel_reg;
  wire [3:0]pipe_qrst_fsm;
  wire pipe_qrst_idle;
  wire [0:0]\pipe_stages_1.pipe_tx_rate_q_reg ;
  wire [1:0]qplllock_reg1;
  wire [1:0]qplllock_reg2;
  wire qpllpd;
  wire qpllpd_i_1_n_0;
  wire qpllpd_i_2_n_0;
  wire qpllpd_i_3_n_0;
  wire [7:0]qpllpd_in_reg1;
  wire [7:0]qpllpd_in_reg2;
  wire qpllpd_reg_0;
  wire qpllpd_reg_1;
  wire qpllreset_i_1_n_0;
  wire qpllreset_i_2_n_0;
  wire qpllreset_i_3_n_0;
  wire qpllreset_i_4_n_0;
  wire [7:0]qpllreset_in_reg1;
  wire [7:0]qpllreset_in_reg2;
  wire [7:0]qpllreset_reg_0;
  wire qrst_ovrd;
  wire qrst_qpllreset;
  wire [1:0]rate_reg1;
  wire [1:0]rate_reg2;
  wire reset_n_reg2_reg;
  wire [7:0]\resetovrd_disble.reset_reg[4] ;
  wire \resetovrd_disble.reset_reg[4]_0 ;
  wire start_reg1_reg;

  LUT4 #(
    .INIT(16'hBABB)) 
    \FSM_sequential_fsm[0]_i_1 
       (.I0(\FSM_sequential_fsm[0]_i_2_n_0 ),
        .I1(\FSM_sequential_fsm[0]_i_3_n_0 ),
        .I2(\FSM_sequential_fsm[1]_i_2_n_0 ),
        .I3(pipe_qrst_fsm[0]),
        .O(\FSM_sequential_fsm[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAA2A02)) 
    \FSM_sequential_fsm[0]_i_2 
       (.I0(\FSM_sequential_fsm_reg_n_0_[1] ),
        .I1(drp_done_reg2[1]),
        .I2(drp_done_reg2[0]),
        .I3(pipe_qrst_fsm[0]),
        .I4(\FSM_sequential_fsm_reg_n_0_[2] ),
        .O(\FSM_sequential_fsm[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h77FF77F0)) 
    \FSM_sequential_fsm[0]_i_3 
       (.I0(qplllock_reg2[0]),
        .I1(qplllock_reg2[1]),
        .I2(\FSM_sequential_fsm[0]_i_4_n_0 ),
        .I3(\FSM_sequential_fsm_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555551)) 
    \FSM_sequential_fsm[0]_i_4 
       (.I0(pipe_qrst_fsm[0]),
        .I1(\FSM_sequential_fsm[0]_i_5_n_0 ),
        .I2(qplllock_reg2[1]),
        .I3(qplllock_reg2[0]),
        .I4(cplllock_reg2[3]),
        .I5(cplllock_reg2[1]),
        .O(\FSM_sequential_fsm[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \FSM_sequential_fsm[0]_i_5 
       (.I0(cplllock_reg2[0]),
        .I1(cplllock_reg2[7]),
        .I2(cplllock_reg2[6]),
        .I3(cplllock_reg2[4]),
        .I4(cplllock_reg2[5]),
        .I5(cplllock_reg2[2]),
        .O(\FSM_sequential_fsm[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF1FFF44444444)) 
    \FSM_sequential_fsm[1]_i_1 
       (.I0(\FSM_sequential_fsm[1]_i_2_n_0 ),
        .I1(pipe_qrst_fsm[0]),
        .I2(drp_done_reg2[1]),
        .I3(drp_done_reg2[0]),
        .I4(\FSM_sequential_fsm_reg_n_0_[2] ),
        .I5(\FSM_sequential_fsm_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0111111111111111)) 
    \FSM_sequential_fsm[1]_i_2 
       (.I0(\FSM_sequential_fsm_reg_n_0_[1] ),
        .I1(\FSM_sequential_fsm_reg_n_0_[2] ),
        .I2(\FSM_sequential_fsm[1]_i_3_n_0 ),
        .I3(cplllock_reg2[1]),
        .I4(cplllock_reg2[7]),
        .I5(cplllock_reg2[3]),
        .O(\FSM_sequential_fsm[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \FSM_sequential_fsm[1]_i_3 
       (.I0(cplllock_reg2[5]),
        .I1(cplllock_reg2[0]),
        .I2(mmcm_lock_reg2),
        .I3(cplllock_reg2[4]),
        .I4(cplllock_reg2[2]),
        .I5(cplllock_reg2[6]),
        .O(\FSM_sequential_fsm[1]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hEAAAAAAA)) 
    \FSM_sequential_fsm[2]_i_1 
       (.I0(\FSM_sequential_fsm_reg_n_0_[2] ),
        .I1(pipe_qrst_fsm[0]),
        .I2(drp_done_reg2[1]),
        .I3(drp_done_reg2[0]),
        .I4(\FSM_sequential_fsm_reg_n_0_[1] ),
        .O(\FSM_sequential_fsm[2]_i_1_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_sequential_fsm[0]_i_1_n_0 ),
        .Q(pipe_qrst_fsm[0]),
        .R(reset_n_reg2_reg));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_sequential_fsm[1]_i_1_n_0 ),
        .Q(\FSM_sequential_fsm_reg_n_0_[1] ),
        .R(reset_n_reg2_reg));
  (* KEEP = "yes" *) 
  FDRE \FSM_sequential_fsm_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_sequential_fsm[2]_i_1_n_0 ),
        .Q(\FSM_sequential_fsm_reg_n_0_[2] ),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] [0]),
        .Q(cplllock_reg1[0]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] [1]),
        .Q(cplllock_reg1[1]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] [2]),
        .Q(cplllock_reg1[2]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] [3]),
        .Q(cplllock_reg1[3]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] [4]),
        .Q(cplllock_reg1[4]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] [5]),
        .Q(cplllock_reg1[5]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] [6]),
        .Q(cplllock_reg1[6]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4] [7]),
        .Q(cplllock_reg1[7]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[0]),
        .Q(cplllock_reg2[0]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[1]),
        .Q(cplllock_reg2[1]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[2]),
        .Q(cplllock_reg2[2]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[3]),
        .Q(cplllock_reg2[3]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[4]),
        .Q(cplllock_reg2[4]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[5]),
        .Q(cplllock_reg2[5]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[6]),
        .Q(cplllock_reg2[6]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \cplllock_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(cplllock_reg1[7]),
        .Q(cplllock_reg2[7]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(done_reg[0]),
        .Q(drp_done_reg1[0]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(done_reg[1]),
        .Q(drp_done_reg1[1]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(drp_done_reg1[0]),
        .Q(drp_done_reg2[0]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \drp_done_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(drp_done_reg1[1]),
        .Q(drp_done_reg2[1]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\resetovrd_disble.reset_reg[4]_0 ),
        .Q(mmcm_lock_reg1),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE mmcm_lock_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(mmcm_lock_reg1),
        .Q(mmcm_lock_reg2),
        .R(reset_n_reg2_reg));
  FDRE #(
    .INIT(1'b0)) 
    ovrd_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qrst_ovrd),
        .Q(qrst_ovrd),
        .R(reset_n_reg2_reg));
  LUT1 #(
    .INIT(2'h1)) 
    \pipe_qrst_fsm[1]_INST_0 
       (.I0(\FSM_sequential_fsm_reg_n_0_[1] ),
        .O(pipe_qrst_fsm[1]));
  LUT3 #(
    .INIT(8'h5C)) 
    \pipe_qrst_fsm[2]_INST_0 
       (.I0(pipe_qrst_fsm[0]),
        .I1(\FSM_sequential_fsm_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_reg_n_0_[2] ),
        .O(pipe_qrst_fsm[2]));
  LUT3 #(
    .INIT(8'h60)) 
    \pipe_qrst_fsm[3]_INST_0 
       (.I0(pipe_qrst_fsm[0]),
        .I1(\FSM_sequential_fsm_reg_n_0_[1] ),
        .I2(\FSM_sequential_fsm_reg_n_0_[2] ),
        .O(pipe_qrst_fsm[3]));
  LUT3 #(
    .INIT(8'h80)) 
    pipe_qrst_idle_INST_0
       (.I0(\FSM_sequential_fsm_reg_n_0_[1] ),
        .I1(pipe_qrst_fsm[0]),
        .I2(\FSM_sequential_fsm_reg_n_0_[2] ),
        .O(pipe_qrst_idle));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qplllock_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_reg_1),
        .Q(qplllock_reg1[0]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qplllock_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_reg_0),
        .Q(qplllock_reg1[1]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qplllock_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qplllock_reg1[0]),
        .Q(qplllock_reg2[0]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qplllock_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qplllock_reg1[1]),
        .Q(qplllock_reg2[1]),
        .R(reset_n_reg2_reg));
  LUT6 #(
    .INIT(64'hB8FFFFFFB8000000)) 
    qpllpd_i_1
       (.I0(qpllpd_i_2_n_0),
        .I1(pipe_qrst_fsm[0]),
        .I2(qpllreset_i_2_n_0),
        .I3(\FSM_sequential_fsm_reg_n_0_[2] ),
        .I4(\FSM_sequential_fsm_reg_n_0_[1] ),
        .I5(qpllpd),
        .O(qpllpd_i_1_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    qpllpd_i_2
       (.I0(qpllpd_i_3_n_0),
        .I1(qpllpd_in_reg2[4]),
        .I2(qpllpd_in_reg2[5]),
        .O(qpllpd_i_2_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    qpllpd_i_3
       (.I0(qpllpd_in_reg2[6]),
        .I1(qpllpd_in_reg2[7]),
        .I2(qpllpd_in_reg2[1]),
        .I3(qpllpd_in_reg2[0]),
        .I4(qpllpd_in_reg2[3]),
        .I5(qpllpd_in_reg2[2]),
        .O(qpllpd_i_3_n_0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[0]),
        .Q(qpllpd_in_reg1[0]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[1]),
        .Q(qpllpd_in_reg1[1]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[2]),
        .Q(qpllpd_in_reg1[2]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[3]),
        .Q(qpllpd_in_reg1[3]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[4]),
        .Q(qpllpd_in_reg1[4]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[5]),
        .Q(qpllpd_in_reg1[5]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[6]),
        .Q(qpllpd_in_reg1[6]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(D[7]),
        .Q(qpllpd_in_reg1[7]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_in_reg1[0]),
        .Q(qpllpd_in_reg2[0]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_in_reg1[1]),
        .Q(qpllpd_in_reg2[1]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_in_reg1[2]),
        .Q(qpllpd_in_reg2[2]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_in_reg1[3]),
        .Q(qpllpd_in_reg2[3]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_in_reg1[4]),
        .Q(qpllpd_in_reg2[4]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_in_reg1[5]),
        .Q(qpllpd_in_reg2[5]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_in_reg1[6]),
        .Q(qpllpd_in_reg2[6]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \qpllpd_in_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_in_reg1[7]),
        .Q(qpllpd_in_reg2[7]),
        .R(reset_n_reg2_reg));
  FDRE #(
    .INIT(1'b0)) 
    qpllpd_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllpd_i_1_n_0),
        .Q(qpllpd),
        .R(reset_n_reg2_reg));
  LUT6 #(
    .INIT(64'hCAF0FFFFCA000000)) 
    qpllreset_i_1
       (.I0(qpllreset_i_2_n_0),
        .I1(qpllreset_i_3_n_0),
        .I2(\FSM_sequential_fsm_reg_n_0_[1] ),
        .I3(pipe_qrst_fsm[0]),
        .I4(\FSM_sequential_fsm_reg_n_0_[2] ),
        .I5(qrst_qpllreset),
        .O(qpllreset_i_1_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    qpllreset_i_2
       (.I0(rate_reg2[0]),
        .I1(rate_reg2[1]),
        .O(qpllreset_i_2_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    qpllreset_i_3
       (.I0(qpllreset_i_4_n_0),
        .I1(qpllreset_in_reg2[4]),
        .I2(qpllreset_in_reg2[5]),
        .O(qpllreset_i_3_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    qpllreset_i_4
       (.I0(qpllreset_in_reg2[6]),
        .I1(qpllreset_in_reg2[7]),
        .I2(qpllreset_in_reg2[1]),
        .I3(qpllreset_in_reg2[0]),
        .I4(qpllreset_in_reg2[3]),
        .I5(qpllreset_in_reg2[2]),
        .O(qpllreset_i_4_n_0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_reg_0[0]),
        .Q(qpllreset_in_reg1[0]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_reg_0[1]),
        .Q(qpllreset_in_reg1[1]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_reg_0[2]),
        .Q(qpllreset_in_reg1[2]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_reg_0[3]),
        .Q(qpllreset_in_reg1[3]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_reg_0[4]),
        .Q(qpllreset_in_reg1[4]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_reg_0[5]),
        .Q(qpllreset_in_reg1[5]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_reg_0[6]),
        .Q(qpllreset_in_reg1[6]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_reg_0[7]),
        .Q(qpllreset_in_reg1[7]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_in_reg1[0]),
        .Q(qpllreset_in_reg2[0]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_in_reg1[1]),
        .Q(qpllreset_in_reg2[1]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_in_reg1[2]),
        .Q(qpllreset_in_reg2[2]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_in_reg1[3]),
        .Q(qpllreset_in_reg2[3]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_in_reg1[4]),
        .Q(qpllreset_in_reg2[4]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_in_reg1[5]),
        .Q(qpllreset_in_reg2[5]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_in_reg1[6]),
        .Q(qpllreset_in_reg2[6]),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDSE \qpllreset_in_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_in_reg1[7]),
        .Q(qpllreset_in_reg2[7]),
        .S(reset_n_reg2_reg));
  FDSE #(
    .INIT(1'b1)) 
    qpllreset_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(qpllreset_i_1_n_0),
        .Q(qrst_qpllreset),
        .S(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\pipe_stages_1.pipe_tx_rate_q_reg ),
        .Q(rate_reg1[0]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(rate_reg1[1]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_reg1[0]),
        .Q(rate_reg2[0]),
        .R(reset_n_reg2_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \rate_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rate_reg1[1]),
        .Q(rate_reg2[1]),
        .R(reset_n_reg2_reg));
  LUT3 #(
    .INIT(8'h04)) 
    start_reg1_i_1__7
       (.I0(\FSM_sequential_fsm_reg_n_0_[2] ),
        .I1(\FSM_sequential_fsm_reg_n_0_[1] ),
        .I2(pipe_qrst_fsm[0]),
        .O(start_reg1_reg));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_qpll_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper
   (qpll_drp_rdy,
    RATE_QPLLLOCK,
    \cplllock_reg1_reg[7] ,
    \cplllock_reg1_reg[7]_0 ,
    DRP_DO,
    \resetovrd_disble.reset_reg[4] ,
    qpll_drp_en,
    qpll_drp_we,
    sys_clk,
    qpllpd,
    QPLL_QPLLRESET0,
    DRP_DI,
    DRP_ADDR);
  output qpll_drp_rdy;
  output RATE_QPLLLOCK;
  output \cplllock_reg1_reg[7] ;
  output \cplllock_reg1_reg[7]_0 ;
  output [15:0]DRP_DO;
  input \resetovrd_disble.reset_reg[4] ;
  input qpll_drp_en;
  input qpll_drp_we;
  input sys_clk;
  input qpllpd;
  input QPLL_QPLLRESET0;
  input [15:0]DRP_DI;
  input [7:0]DRP_ADDR;

  wire [7:0]DRP_ADDR;
  wire [15:0]DRP_DI;
  wire [15:0]DRP_DO;
  wire QPLL_QPLLRESET0;
  wire RATE_QPLLLOCK;
  wire \cplllock_reg1_reg[7] ;
  wire \cplllock_reg1_reg[7]_0 ;
  wire qpll_drp_en;
  wire qpll_drp_rdy;
  wire qpll_drp_we;
  wire qpllpd;
  wire \resetovrd_disble.reset_reg[4] ;
  wire sys_clk;
  wire \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED ;
  wire [7:0]\NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  GTXE2_COMMON #(
    .BIAS_CFG(64'h0000040000001000),
    .COMMON_CFG(32'h00000000),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_QPLLLOCKDETCLK_INVERTED(1'b0),
    .QPLL_CFG(27'h06801C1),
    .QPLL_CLKOUT_CFG(4'b0000),
    .QPLL_COARSE_FREQ_OVRD(6'b010000),
    .QPLL_COARSE_FREQ_OVRD_EN(1'b0),
    .QPLL_CP(10'b0000011111),
    .QPLL_CP_MONITOR_EN(1'b0),
    .QPLL_DMONITOR_SEL(1'b0),
    .QPLL_FBDIV(10'b0100100000),
    .QPLL_FBDIV_MONITOR_EN(1'b0),
    .QPLL_FBDIV_RATIO(1'b1),
    .QPLL_INIT_CFG(24'h000006),
    .QPLL_LOCK_CFG(16'h21E8),
    .QPLL_LPF(4'b1101),
    .QPLL_REFCLK_DIV(1),
    .SIM_QPLLREFCLK_SEL(3'b001),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_VERSION("3.0")) 
    \gtx_common.gtxe2_common_i 
       (.BGBYPASSB(1'b1),
        .BGMONITORENB(1'b1),
        .BGPDB(1'b1),
        .BGRCALOVRD({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DRPADDR(DRP_ADDR),
        .DRPCLK(\resetovrd_disble.reset_reg[4] ),
        .DRPDI(DRP_DI),
        .DRPDO(DRP_DO),
        .DRPEN(qpll_drp_en),
        .DRPRDY(qpll_drp_rdy),
        .DRPWE(qpll_drp_we),
        .GTGREFCLK(1'b0),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .PMARSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLDMONITOR(\NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED [7:0]),
        .QPLLFBCLKLOST(\NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED ),
        .QPLLLOCK(RATE_QPLLLOCK),
        .QPLLLOCKDETCLK(1'b0),
        .QPLLLOCKEN(1'b1),
        .QPLLOUTCLK(\cplllock_reg1_reg[7] ),
        .QPLLOUTREFCLK(\cplllock_reg1_reg[7]_0 ),
        .QPLLOUTRESET(1'b0),
        .QPLLPD(qpllpd),
        .QPLLREFCLKLOST(\NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED ),
        .QPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .QPLLRESET(QPLL_QPLLRESET0),
        .QPLLRSVD1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLRSVD2({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .RCALENB(1'b1),
        .REFCLKOUTMONITOR(\NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_qpll_wrapper" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_qpll_wrapper_85
   (qpll_drp_rdy,
    RATE_QPLLLOCK,
    \cplllock_reg1_reg[3] ,
    \cplllock_reg1_reg[3]_0 ,
    DRP_DO,
    \resetovrd_disble.reset_reg[4] ,
    qpll_drp_en,
    qpll_drp_we,
    sys_clk,
    qpllpd,
    QPLL_QPLLRESET0126_out,
    DRP_DI,
    DRP_ADDR);
  output qpll_drp_rdy;
  output RATE_QPLLLOCK;
  output \cplllock_reg1_reg[3] ;
  output \cplllock_reg1_reg[3]_0 ;
  output [15:0]DRP_DO;
  input \resetovrd_disble.reset_reg[4] ;
  input qpll_drp_en;
  input qpll_drp_we;
  input sys_clk;
  input qpllpd;
  input QPLL_QPLLRESET0126_out;
  input [15:0]DRP_DI;
  input [7:0]DRP_ADDR;

  wire [7:0]DRP_ADDR;
  wire [15:0]DRP_DI;
  wire [15:0]DRP_DO;
  wire QPLL_QPLLRESET0126_out;
  wire RATE_QPLLLOCK;
  wire \cplllock_reg1_reg[3] ;
  wire \cplllock_reg1_reg[3]_0 ;
  wire qpll_drp_en;
  wire qpll_drp_rdy;
  wire qpll_drp_we;
  wire qpllpd;
  wire \resetovrd_disble.reset_reg[4] ;
  wire sys_clk;
  wire \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED ;
  wire \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED ;
  wire [7:0]\NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  GTXE2_COMMON #(
    .BIAS_CFG(64'h0000040000001000),
    .COMMON_CFG(32'h00000000),
    .IS_DRPCLK_INVERTED(1'b0),
    .IS_GTGREFCLK_INVERTED(1'b0),
    .IS_QPLLLOCKDETCLK_INVERTED(1'b0),
    .QPLL_CFG(27'h06801C1),
    .QPLL_CLKOUT_CFG(4'b0000),
    .QPLL_COARSE_FREQ_OVRD(6'b010000),
    .QPLL_COARSE_FREQ_OVRD_EN(1'b0),
    .QPLL_CP(10'b0000011111),
    .QPLL_CP_MONITOR_EN(1'b0),
    .QPLL_DMONITOR_SEL(1'b0),
    .QPLL_FBDIV(10'b0100100000),
    .QPLL_FBDIV_MONITOR_EN(1'b0),
    .QPLL_FBDIV_RATIO(1'b1),
    .QPLL_INIT_CFG(24'h000006),
    .QPLL_LOCK_CFG(16'h21E8),
    .QPLL_LPF(4'b1101),
    .QPLL_REFCLK_DIV(1),
    .SIM_QPLLREFCLK_SEL(3'b001),
    .SIM_RESET_SPEEDUP("FALSE"),
    .SIM_VERSION("3.0")) 
    \gtx_common.gtxe2_common_i 
       (.BGBYPASSB(1'b1),
        .BGMONITORENB(1'b1),
        .BGPDB(1'b1),
        .BGRCALOVRD({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DRPADDR(DRP_ADDR),
        .DRPCLK(\resetovrd_disble.reset_reg[4] ),
        .DRPDI(DRP_DI),
        .DRPDO(DRP_DO),
        .DRPEN(qpll_drp_en),
        .DRPRDY(qpll_drp_rdy),
        .DRPWE(qpll_drp_we),
        .GTGREFCLK(1'b0),
        .GTNORTHREFCLK0(1'b0),
        .GTNORTHREFCLK1(1'b0),
        .GTREFCLK0(sys_clk),
        .GTREFCLK1(1'b0),
        .GTSOUTHREFCLK0(1'b0),
        .GTSOUTHREFCLK1(1'b0),
        .PMARSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLDMONITOR(\NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED [7:0]),
        .QPLLFBCLKLOST(\NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED ),
        .QPLLLOCK(RATE_QPLLLOCK),
        .QPLLLOCKDETCLK(1'b0),
        .QPLLLOCKEN(1'b1),
        .QPLLOUTCLK(\cplllock_reg1_reg[3] ),
        .QPLLOUTREFCLK(\cplllock_reg1_reg[3]_0 ),
        .QPLLOUTRESET(1'b0),
        .QPLLPD(qpllpd),
        .QPLLREFCLKLOST(\NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED ),
        .QPLLREFCLKSEL({1'b0,1'b0,1'b1}),
        .QPLLRESET(QPLL_QPLLRESET0126_out),
        .QPLLRSVD1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .QPLLRSVD2({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .RCALENB(1'b1),
        .REFCLKOUTMONITOR(\NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_rxeq_scan" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan
   (D,
    rxeq_new_txcoeff_req_reg,
    rxeq_adapt_done_reg,
    rxeq_adapt_done_reg_reg,
    RST_CPLLRESET,
    rxeq_new_txcoeff_req_reg_0,
    pclk_sel_reg,
    rxeq_preset_valid_reg,
    out,
    \FSM_sequential_fsm_rx_reg[0] ,
    \rxeq_cnt_reg[1] ,
    \FSM_sequential_fsm_rx_reg[2] ,
    \rxeq_cnt_reg[1]_0 ,
    \rxeq_control_reg2_reg[0] ,
    rxeq_adapt_done_reg_reg_0,
    USER_RXEQ_ADAPT_DONE,
    \rxeq_preset_reg[2] ,
    Q,
    \rxeq_txcoeff_reg[17] ,
    \rxeq_fs_reg[5] ,
    \rxeq_lf_reg[5] );
  output [2:0]D;
  output rxeq_new_txcoeff_req_reg;
  output rxeq_adapt_done_reg;
  output rxeq_adapt_done_reg_reg;
  input RST_CPLLRESET;
  input rxeq_new_txcoeff_req_reg_0;
  input pclk_sel_reg;
  input rxeq_preset_valid_reg;
  input [1:0]out;
  input \FSM_sequential_fsm_rx_reg[0] ;
  input \rxeq_cnt_reg[1] ;
  input [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  input \rxeq_cnt_reg[1]_0 ;
  input \rxeq_control_reg2_reg[0] ;
  input rxeq_adapt_done_reg_reg_0;
  input USER_RXEQ_ADAPT_DONE;
  input [2:0]\rxeq_preset_reg[2] ;
  input [3:0]Q;
  input [17:0]\rxeq_txcoeff_reg[17] ;
  input [5:0]\rxeq_fs_reg[5] ;
  input [5:0]\rxeq_lf_reg[5] ;

  wire [2:0]D;
  wire \FSM_onehot_fsm[1]_i_1__7_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__7_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__7_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2__7_n_0 ;
  wire \FSM_onehot_fsm[3]_i_3__7_n_0 ;
  wire \FSM_onehot_fsm[3]_i_4__7_n_0 ;
  wire \FSM_onehot_fsm[3]_i_5__6_n_0 ;
  wire \FSM_onehot_fsm[3]_i_7__6_n_0 ;
  wire \FSM_onehot_fsm[3]_i_8__6_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__7_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2__6_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3__7_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4__6_n_0 ;
  wire \FSM_onehot_fsm[4]_i_5__6_n_0 ;
  wire \FSM_onehot_fsm[4]_i_6__6_n_0 ;
  wire \FSM_onehot_fsm[4]_i_7__6_n_0 ;
  wire \FSM_onehot_fsm[4]_i_8__6_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[4] ;
  wire \FSM_sequential_fsm_rx_reg[0] ;
  wire [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  wire [3:0]Q;
  wire RST_CPLLRESET;
  wire USER_RXEQ_ADAPT_DONE;
  wire adapt_done;
  wire adapt_done_cnt;
  wire adapt_done_cnt_i_1__6_n_0;
  wire adapt_done_cnt_reg_n_0;
  wire [21:0]converge_cnt;
  wire [21:0]converge_cnt0;
  wire \converge_cnt[11]_i_3__6_n_0 ;
  wire \converge_cnt[11]_i_4__6_n_0 ;
  wire \converge_cnt[11]_i_5__6_n_0 ;
  wire \converge_cnt[11]_i_6__6_n_0 ;
  wire \converge_cnt[15]_i_3__6_n_0 ;
  wire \converge_cnt[15]_i_4__6_n_0 ;
  wire \converge_cnt[15]_i_5__6_n_0 ;
  wire \converge_cnt[15]_i_6__6_n_0 ;
  wire \converge_cnt[19]_i_3__6_n_0 ;
  wire \converge_cnt[19]_i_4__6_n_0 ;
  wire \converge_cnt[19]_i_5__6_n_0 ;
  wire \converge_cnt[19]_i_6__6_n_0 ;
  wire \converge_cnt[21]_i_3__6_n_0 ;
  wire \converge_cnt[21]_i_4__6_n_0 ;
  wire \converge_cnt[3]_i_3__6_n_0 ;
  wire \converge_cnt[3]_i_4__6_n_0 ;
  wire \converge_cnt[3]_i_5__6_n_0 ;
  wire \converge_cnt[3]_i_6__6_n_0 ;
  wire \converge_cnt[7]_i_3__6_n_0 ;
  wire \converge_cnt[7]_i_4__6_n_0 ;
  wire \converge_cnt[7]_i_5__6_n_0 ;
  wire \converge_cnt[7]_i_6__6_n_0 ;
  wire \converge_cnt_reg[11]_i_2__6_n_0 ;
  wire \converge_cnt_reg[11]_i_2__6_n_1 ;
  wire \converge_cnt_reg[11]_i_2__6_n_2 ;
  wire \converge_cnt_reg[11]_i_2__6_n_3 ;
  wire \converge_cnt_reg[15]_i_2__6_n_0 ;
  wire \converge_cnt_reg[15]_i_2__6_n_1 ;
  wire \converge_cnt_reg[15]_i_2__6_n_2 ;
  wire \converge_cnt_reg[15]_i_2__6_n_3 ;
  wire \converge_cnt_reg[19]_i_2__6_n_0 ;
  wire \converge_cnt_reg[19]_i_2__6_n_1 ;
  wire \converge_cnt_reg[19]_i_2__6_n_2 ;
  wire \converge_cnt_reg[19]_i_2__6_n_3 ;
  wire \converge_cnt_reg[21]_i_2__6_n_3 ;
  wire \converge_cnt_reg[3]_i_2__6_n_0 ;
  wire \converge_cnt_reg[3]_i_2__6_n_1 ;
  wire \converge_cnt_reg[3]_i_2__6_n_2 ;
  wire \converge_cnt_reg[3]_i_2__6_n_3 ;
  wire \converge_cnt_reg[7]_i_2__6_n_0 ;
  wire \converge_cnt_reg[7]_i_2__6_n_1 ;
  wire \converge_cnt_reg[7]_i_2__6_n_2 ;
  wire \converge_cnt_reg[7]_i_2__6_n_3 ;
  wire \converge_cnt_reg_n_0_[0] ;
  wire \converge_cnt_reg_n_0_[10] ;
  wire \converge_cnt_reg_n_0_[11] ;
  wire \converge_cnt_reg_n_0_[12] ;
  wire \converge_cnt_reg_n_0_[13] ;
  wire \converge_cnt_reg_n_0_[14] ;
  wire \converge_cnt_reg_n_0_[15] ;
  wire \converge_cnt_reg_n_0_[16] ;
  wire \converge_cnt_reg_n_0_[17] ;
  wire \converge_cnt_reg_n_0_[18] ;
  wire \converge_cnt_reg_n_0_[19] ;
  wire \converge_cnt_reg_n_0_[1] ;
  wire \converge_cnt_reg_n_0_[20] ;
  wire \converge_cnt_reg_n_0_[21] ;
  wire \converge_cnt_reg_n_0_[2] ;
  wire \converge_cnt_reg_n_0_[3] ;
  wire \converge_cnt_reg_n_0_[4] ;
  wire \converge_cnt_reg_n_0_[5] ;
  wire \converge_cnt_reg_n_0_[6] ;
  wire \converge_cnt_reg_n_0_[7] ;
  wire \converge_cnt_reg_n_0_[8] ;
  wire \converge_cnt_reg_n_0_[9] ;
  wire [5:0]fs_reg1;
  wire [5:0]fs_reg2;
  wire fsm1;
  wire [5:0]lf_reg1;
  wire [5:0]lf_reg2;
  wire new_txcoeff_done;
  wire new_txcoeff_req_reg1;
  wire new_txcoeff_req_reg2;
  wire [1:0]out;
  wire pclk_sel_reg;
  wire preset_done;
  wire [2:0]preset_reg1;
  wire [2:0]preset_reg2;
  wire preset_valid_reg1;
  wire preset_valid_reg2;
  wire rxeq_adapt_done_reg;
  wire rxeq_adapt_done_reg0;
  wire rxeq_adapt_done_reg_i_2__6_n_0;
  wire rxeq_adapt_done_reg_reg;
  wire rxeq_adapt_done_reg_reg_0;
  wire \rxeq_cnt_reg[1] ;
  wire \rxeq_cnt_reg[1]_0 ;
  wire \rxeq_control_reg2_reg[0] ;
  wire [5:0]\rxeq_fs_reg[5] ;
  wire [5:0]\rxeq_lf_reg[5] ;
  wire rxeq_new_txcoeff_req_reg;
  wire rxeq_new_txcoeff_req_reg_0;
  wire [2:0]\rxeq_preset_reg[2] ;
  wire rxeq_preset_valid_reg;
  wire [17:0]\rxeq_txcoeff_reg[17] ;
  wire rxeqscan_adapt_done;
  wire rxeqscan_new_txcoeff_done;
  wire rxeqscan_preset_done;
  wire [17:0]txcoeff_reg1;
  wire [17:0]txcoeff_reg2;
  wire [3:0]txpreset_reg1;
  wire [3:0]txpreset_reg2;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__6_CO_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__6_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h000000073333FF07)) 
    \FSM_onehot_fsm[1]_i_1__7 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(preset_valid_reg2),
        .O(\FSM_onehot_fsm[1]_i_1__7_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \FSM_onehot_fsm[2]_i_1__7 
       (.I0(preset_valid_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[2]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA8A8AA)) 
    \FSM_onehot_fsm[3]_i_1__7 
       (.I0(\FSM_onehot_fsm[3]_i_2__7_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_3__7_n_0 ),
        .I2(\FSM_onehot_fsm[3]_i_4__7_n_0 ),
        .I3(\converge_cnt_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm[3]_i_5__6_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'h2020202020202F20)) 
    \FSM_onehot_fsm[3]_i_2__7 
       (.I0(new_txcoeff_req_reg2),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(fsm1),
        .I5(\FSM_onehot_fsm_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm[3]_i_2__7_n_0 ));
  LUT6 #(
    .INIT(64'hFFF6FFFFFFFF6FFF)) 
    \FSM_onehot_fsm[3]_i_3__7 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .I1(\converge_cnt_reg_n_0_[2] ),
        .I2(\converge_cnt_reg_n_0_[10] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[20] ),
        .O(\FSM_onehot_fsm[3]_i_3__7_n_0 ));
  LUT6 #(
    .INIT(64'hFF7E7EFFFF7EFF7E)) 
    \FSM_onehot_fsm[3]_i_4__7 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[8] ),
        .I3(\converge_cnt_reg_n_0_[21] ),
        .I4(out[0]),
        .I5(out[1]),
        .O(\FSM_onehot_fsm[3]_i_4__7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF9)) 
    \FSM_onehot_fsm[3]_i_5__6 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .I1(\converge_cnt_reg_n_0_[21] ),
        .I2(\converge_cnt_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[7] ),
        .I4(\FSM_onehot_fsm[3]_i_7__6_n_0 ),
        .I5(\FSM_onehot_fsm[3]_i_8__6_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_5__6_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_onehot_fsm[3]_i_6__6 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .O(fsm1));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[3]_i_7__6 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[16] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[3]_i_7__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFDFF)) 
    \FSM_onehot_fsm[3]_i_8__6 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .I1(\converge_cnt_reg_n_0_[4] ),
        .I2(\converge_cnt_reg_n_0_[12] ),
        .I3(\converge_cnt_reg_n_0_[9] ),
        .I4(\converge_cnt_reg_n_0_[5] ),
        .I5(\converge_cnt_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm[3]_i_8__6_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \FSM_onehot_fsm[4]_i_1__7 
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm[4]_i_2__6_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \FSM_onehot_fsm[4]_i_2__6 
       (.I0(\FSM_onehot_fsm[4]_i_3__7_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_4__6_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_5__6_n_0 ),
        .I3(\FSM_onehot_fsm[4]_i_6__6_n_0 ),
        .I4(\FSM_onehot_fsm[4]_i_7__6_n_0 ),
        .I5(\FSM_onehot_fsm[4]_i_8__6_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'h02020202FF000000)) 
    \FSM_onehot_fsm[4]_i_3__7 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_3__7_n_0 ));
  LUT6 #(
    .INIT(64'h00004B00004B0000)) 
    \FSM_onehot_fsm[4]_i_4__6 
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\converge_cnt_reg_n_0_[21] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[10] ),
        .O(\FSM_onehot_fsm[4]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'h0000810000810000)) 
    \FSM_onehot_fsm[4]_i_5__6 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[8] ),
        .I2(\converge_cnt_reg_n_0_[3] ),
        .I3(\converge_cnt_reg_n_0_[20] ),
        .I4(\converge_cnt_reg_n_0_[21] ),
        .I5(\converge_cnt_reg_n_0_[14] ),
        .O(\FSM_onehot_fsm[4]_i_5__6_n_0 ));
  LUT5 #(
    .INIT(32'h00000024)) 
    \FSM_onehot_fsm[4]_i_6__6 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[0] ),
        .I3(\converge_cnt_reg_n_0_[5] ),
        .I4(\converge_cnt_reg_n_0_[4] ),
        .O(\FSM_onehot_fsm[4]_i_6__6_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \FSM_onehot_fsm[4]_i_7__6 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\converge_cnt_reg_n_0_[11] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[9] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[4]_i_7__6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \FSM_onehot_fsm[4]_i_8__6 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .I1(\converge_cnt_reg_n_0_[6] ),
        .I2(\converge_cnt_reg_n_0_[16] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[19] ),
        .I5(\converge_cnt_reg_n_0_[7] ),
        .O(\FSM_onehot_fsm[4]_i_8__6_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__7_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__7_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__7_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__7_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hEFEEEEEE)) 
    \FSM_sequential_fsm_rx[0]_i_1__6 
       (.I0(\FSM_sequential_fsm_rx_reg[0] ),
        .I1(\rxeq_cnt_reg[1] ),
        .I2(rxeqscan_new_txcoeff_done),
        .I3(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h0CAF0CA0FF000F00)) 
    \FSM_sequential_fsm_rx[1]_i_1__6 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(\rxeq_cnt_reg[1]_0 ),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\rxeq_control_reg2_reg[0] ),
        .I5(\FSM_sequential_fsm_rx_reg[2] [0]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h3F083FC8330833C8)) 
    \FSM_sequential_fsm_rx[2]_i_1__6 
       (.I0(rxeqscan_preset_done),
        .I1(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I4(\rxeq_cnt_reg[1]_0 ),
        .I5(\rxeq_control_reg2_reg[0] ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'h00FF2A00)) 
    adapt_done_cnt_i_1__6
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(out[0]),
        .I2(out[1]),
        .I3(adapt_done_cnt),
        .I4(adapt_done_cnt_reg_n_0),
        .O(adapt_done_cnt_i_1__6_n_0));
  LUT6 #(
    .INIT(64'hFFFF444744444447)) 
    adapt_done_cnt_i_2__6
       (.I0(new_txcoeff_req_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I5(fsm1),
        .O(adapt_done_cnt));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_cnt_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done_cnt_i_1__6_n_0),
        .Q(adapt_done_cnt_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hA8880000)) 
    adapt_done_i_1__6
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[1]),
        .I3(out[0]),
        .I4(new_txcoeff_req_reg2),
        .O(adapt_done));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done),
        .Q(rxeqscan_adapt_done),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[0]_i_1__14 
       (.I0(converge_cnt0[0]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[0]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[10]_i_1__6 
       (.I0(converge_cnt0[10]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[10]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[11]_i_1__6 
       (.I0(converge_cnt0[11]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[11]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_3__6 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .O(\converge_cnt[11]_i_3__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_4__6 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .O(\converge_cnt[11]_i_4__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_5__6 
       (.I0(\converge_cnt_reg_n_0_[9] ),
        .O(\converge_cnt[11]_i_5__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_6__6 
       (.I0(\converge_cnt_reg_n_0_[8] ),
        .O(\converge_cnt[11]_i_6__6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[12]_i_1__6 
       (.I0(converge_cnt0[12]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[12]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[13]_i_1__6 
       (.I0(converge_cnt0[13]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[13]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[14]_i_1__6 
       (.I0(converge_cnt0[14]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[14]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[15]_i_1__6 
       (.I0(converge_cnt0[15]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[15]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_3__6 
       (.I0(\converge_cnt_reg_n_0_[15] ),
        .O(\converge_cnt[15]_i_3__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_4__6 
       (.I0(\converge_cnt_reg_n_0_[14] ),
        .O(\converge_cnt[15]_i_4__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_5__6 
       (.I0(\converge_cnt_reg_n_0_[13] ),
        .O(\converge_cnt[15]_i_5__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_6__6 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .O(\converge_cnt[15]_i_6__6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[16]_i_1__6 
       (.I0(converge_cnt0[16]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[16]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[17]_i_1__6 
       (.I0(converge_cnt0[17]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[17]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[18]_i_1__6 
       (.I0(converge_cnt0[18]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[18]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[19]_i_1__6 
       (.I0(converge_cnt0[19]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[19]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_3__6 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .O(\converge_cnt[19]_i_3__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_4__6 
       (.I0(\converge_cnt_reg_n_0_[18] ),
        .O(\converge_cnt[19]_i_4__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_5__6 
       (.I0(\converge_cnt_reg_n_0_[17] ),
        .O(\converge_cnt[19]_i_5__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_6__6 
       (.I0(\converge_cnt_reg_n_0_[16] ),
        .O(\converge_cnt[19]_i_6__6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[1]_i_1__6 
       (.I0(converge_cnt0[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[1]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[20]_i_1__6 
       (.I0(converge_cnt0[20]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[20]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[21]_i_1__6 
       (.I0(converge_cnt0[21]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[21]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_3__6 
       (.I0(\converge_cnt_reg_n_0_[21] ),
        .O(\converge_cnt[21]_i_3__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_4__6 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .O(\converge_cnt[21]_i_4__6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[2]_i_1__6 
       (.I0(converge_cnt0[2]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[2]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[3]_i_1__6 
       (.I0(converge_cnt0[3]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[3]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_3__6 
       (.I0(\converge_cnt_reg_n_0_[3] ),
        .O(\converge_cnt[3]_i_3__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_4__6 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .O(\converge_cnt[3]_i_4__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_5__6 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .O(\converge_cnt[3]_i_5__6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[3]_i_6__6 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .O(\converge_cnt[3]_i_6__6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[4]_i_1__6 
       (.I0(converge_cnt0[4]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[4]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[5]_i_1__6 
       (.I0(converge_cnt0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[5]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[6]_i_1__6 
       (.I0(converge_cnt0[6]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[6]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[7]_i_1__6 
       (.I0(converge_cnt0[7]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[7]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_3__6 
       (.I0(\converge_cnt_reg_n_0_[7] ),
        .O(\converge_cnt[7]_i_3__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_4__6 
       (.I0(\converge_cnt_reg_n_0_[6] ),
        .O(\converge_cnt[7]_i_4__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_5__6 
       (.I0(\converge_cnt_reg_n_0_[5] ),
        .O(\converge_cnt[7]_i_5__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_6__6 
       (.I0(\converge_cnt_reg_n_0_[4] ),
        .O(\converge_cnt[7]_i_6__6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[8]_i_1__6 
       (.I0(converge_cnt0[8]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[8]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[9]_i_1__6 
       (.I0(converge_cnt0[9]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[9]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[0]),
        .Q(\converge_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[10]),
        .Q(\converge_cnt_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[11]),
        .Q(\converge_cnt_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[11]_i_2__6 
       (.CI(\converge_cnt_reg[7]_i_2__6_n_0 ),
        .CO({\converge_cnt_reg[11]_i_2__6_n_0 ,\converge_cnt_reg[11]_i_2__6_n_1 ,\converge_cnt_reg[11]_i_2__6_n_2 ,\converge_cnt_reg[11]_i_2__6_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[11:8]),
        .S({\converge_cnt[11]_i_3__6_n_0 ,\converge_cnt[11]_i_4__6_n_0 ,\converge_cnt[11]_i_5__6_n_0 ,\converge_cnt[11]_i_6__6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[12]),
        .Q(\converge_cnt_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[13]),
        .Q(\converge_cnt_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[14]),
        .Q(\converge_cnt_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[15]),
        .Q(\converge_cnt_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[15]_i_2__6 
       (.CI(\converge_cnt_reg[11]_i_2__6_n_0 ),
        .CO({\converge_cnt_reg[15]_i_2__6_n_0 ,\converge_cnt_reg[15]_i_2__6_n_1 ,\converge_cnt_reg[15]_i_2__6_n_2 ,\converge_cnt_reg[15]_i_2__6_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[15:12]),
        .S({\converge_cnt[15]_i_3__6_n_0 ,\converge_cnt[15]_i_4__6_n_0 ,\converge_cnt[15]_i_5__6_n_0 ,\converge_cnt[15]_i_6__6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[16]),
        .Q(\converge_cnt_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[17]),
        .Q(\converge_cnt_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[18]),
        .Q(\converge_cnt_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[19]),
        .Q(\converge_cnt_reg_n_0_[19] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[19]_i_2__6 
       (.CI(\converge_cnt_reg[15]_i_2__6_n_0 ),
        .CO({\converge_cnt_reg[19]_i_2__6_n_0 ,\converge_cnt_reg[19]_i_2__6_n_1 ,\converge_cnt_reg[19]_i_2__6_n_2 ,\converge_cnt_reg[19]_i_2__6_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[19:16]),
        .S({\converge_cnt[19]_i_3__6_n_0 ,\converge_cnt[19]_i_4__6_n_0 ,\converge_cnt[19]_i_5__6_n_0 ,\converge_cnt[19]_i_6__6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[1]),
        .Q(\converge_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[20]),
        .Q(\converge_cnt_reg_n_0_[20] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[21]),
        .Q(\converge_cnt_reg_n_0_[21] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[21]_i_2__6 
       (.CI(\converge_cnt_reg[19]_i_2__6_n_0 ),
        .CO({\NLW_converge_cnt_reg[21]_i_2__6_CO_UNCONNECTED [3:1],\converge_cnt_reg[21]_i_2__6_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__6_O_UNCONNECTED [3:2],converge_cnt0[21:20]}),
        .S({1'b0,1'b0,\converge_cnt[21]_i_3__6_n_0 ,\converge_cnt[21]_i_4__6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[2]),
        .Q(\converge_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[3]),
        .Q(\converge_cnt_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[3]_i_2__6 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[3]_i_2__6_n_0 ,\converge_cnt_reg[3]_i_2__6_n_1 ,\converge_cnt_reg[3]_i_2__6_n_2 ,\converge_cnt_reg[3]_i_2__6_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\converge_cnt_reg_n_0_[0] }),
        .O(converge_cnt0[3:0]),
        .S({\converge_cnt[3]_i_3__6_n_0 ,\converge_cnt[3]_i_4__6_n_0 ,\converge_cnt[3]_i_5__6_n_0 ,\converge_cnt[3]_i_6__6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[4]),
        .Q(\converge_cnt_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[5]),
        .Q(\converge_cnt_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[6]),
        .Q(\converge_cnt_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[7]),
        .Q(\converge_cnt_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[7]_i_2__6 
       (.CI(\converge_cnt_reg[3]_i_2__6_n_0 ),
        .CO({\converge_cnt_reg[7]_i_2__6_n_0 ,\converge_cnt_reg[7]_i_2__6_n_1 ,\converge_cnt_reg[7]_i_2__6_n_2 ,\converge_cnt_reg[7]_i_2__6_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[7:4]),
        .S({\converge_cnt[7]_i_3__6_n_0 ,\converge_cnt[7]_i_4__6_n_0 ,\converge_cnt[7]_i_5__6_n_0 ,\converge_cnt[7]_i_6__6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[8]),
        .Q(\converge_cnt_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[9]),
        .Q(\converge_cnt_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [0]),
        .Q(fs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [1]),
        .Q(fs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [2]),
        .Q(fs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [3]),
        .Q(fs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [4]),
        .Q(fs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [5]),
        .Q(fs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[0]),
        .Q(fs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[1]),
        .Q(fs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[2]),
        .Q(fs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[3]),
        .Q(fs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[4]),
        .Q(fs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[5]),
        .Q(fs_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [0]),
        .Q(lf_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [1]),
        .Q(lf_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [2]),
        .Q(lf_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [3]),
        .Q(lf_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [4]),
        .Q(lf_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [5]),
        .Q(lf_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[0]),
        .Q(lf_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[1]),
        .Q(lf_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[2]),
        .Q(lf_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[3]),
        .Q(lf_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[4]),
        .Q(lf_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[5]),
        .Q(lf_reg2[5]),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    new_txcoeff_done_i_1__6
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .O(new_txcoeff_done));
  FDRE #(
    .INIT(1'b0)) 
    new_txcoeff_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_done),
        .Q(rxeqscan_new_txcoeff_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_new_txcoeff_req_reg_0),
        .Q(new_txcoeff_req_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1),
        .Q(new_txcoeff_req_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hEA)) 
    preset_done_i_1__6
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(preset_done));
  FDRE #(
    .INIT(1'b0)) 
    preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_done),
        .Q(rxeqscan_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [0]),
        .Q(preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [1]),
        .Q(preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [2]),
        .Q(preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[0]),
        .Q(preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[1]),
        .Q(preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[2]),
        .Q(preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid_reg),
        .Q(preset_valid_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_valid_reg1),
        .Q(preset_valid_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0080F00000800000)) 
    rxeq_adapt_done_i_1__6
       (.I0(rxeq_adapt_done_reg0),
        .I1(rxeqscan_new_txcoeff_done),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I5(USER_RXEQ_ADAPT_DONE),
        .O(rxeq_adapt_done_reg));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rxeq_adapt_done_i_2__6
       (.I0(rxeqscan_adapt_done),
        .I1(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg0));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT5 #(
    .INIT(32'h44FF4000)) 
    rxeq_adapt_done_reg_i_1__6
       (.I0(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(rxeqscan_adapt_done),
        .I3(rxeq_adapt_done_reg_i_2__6_n_0),
        .I4(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg_reg));
  LUT6 #(
    .INIT(64'hF0F0002FF000002F)) 
    rxeq_adapt_done_reg_i_2__6
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I5(rxeqscan_new_txcoeff_done),
        .O(rxeq_adapt_done_reg_i_2__6_n_0));
  LUT4 #(
    .INIT(16'h0008)) 
    rxeq_new_txcoeff_req_i_1__6
       (.I0(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I3(rxeqscan_new_txcoeff_done),
        .O(rxeq_new_txcoeff_req_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [0]),
        .Q(txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [10]),
        .Q(txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [11]),
        .Q(txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [12]),
        .Q(txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [13]),
        .Q(txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [14]),
        .Q(txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [15]),
        .Q(txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [16]),
        .Q(txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [17]),
        .Q(txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [1]),
        .Q(txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [2]),
        .Q(txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [3]),
        .Q(txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [4]),
        .Q(txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [5]),
        .Q(txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [6]),
        .Q(txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [7]),
        .Q(txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [8]),
        .Q(txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [9]),
        .Q(txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[0]),
        .Q(txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[10]),
        .Q(txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[11]),
        .Q(txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[12]),
        .Q(txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[13]),
        .Q(txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[14]),
        .Q(txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[15]),
        .Q(txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[16]),
        .Q(txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[17]),
        .Q(txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[1]),
        .Q(txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[2]),
        .Q(txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[3]),
        .Q(txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[4]),
        .Q(txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[5]),
        .Q(txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[6]),
        .Q(txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[7]),
        .Q(txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[8]),
        .Q(txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[9]),
        .Q(txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[0]),
        .Q(txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[1]),
        .Q(txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[2]),
        .Q(txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[3]),
        .Q(txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[0]),
        .Q(txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[1]),
        .Q(txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[2]),
        .Q(txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[3]),
        .Q(txpreset_reg2[3]),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_rxeq_scan" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_72
   (D,
    rxeq_new_txcoeff_req_reg,
    rxeq_adapt_done_reg,
    rxeq_adapt_done_reg_reg,
    RST_CPLLRESET,
    rxeq_new_txcoeff_req_reg_0,
    pclk_sel_reg,
    rxeq_preset_valid_reg,
    out,
    \FSM_sequential_fsm_rx_reg[0] ,
    \rxeq_cnt_reg[1] ,
    \FSM_sequential_fsm_rx_reg[2] ,
    \rxeq_cnt_reg[1]_0 ,
    \rxeq_control_reg2_reg[0] ,
    rxeq_adapt_done_reg_reg_0,
    USER_RXEQ_ADAPT_DONE,
    \rxeq_preset_reg[2] ,
    Q,
    \rxeq_txcoeff_reg[17] ,
    \rxeq_fs_reg[5] ,
    \rxeq_lf_reg[5] );
  output [2:0]D;
  output rxeq_new_txcoeff_req_reg;
  output rxeq_adapt_done_reg;
  output rxeq_adapt_done_reg_reg;
  input RST_CPLLRESET;
  input rxeq_new_txcoeff_req_reg_0;
  input pclk_sel_reg;
  input rxeq_preset_valid_reg;
  input [1:0]out;
  input \FSM_sequential_fsm_rx_reg[0] ;
  input \rxeq_cnt_reg[1] ;
  input [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  input \rxeq_cnt_reg[1]_0 ;
  input \rxeq_control_reg2_reg[0] ;
  input rxeq_adapt_done_reg_reg_0;
  input USER_RXEQ_ADAPT_DONE;
  input [2:0]\rxeq_preset_reg[2] ;
  input [3:0]Q;
  input [17:0]\rxeq_txcoeff_reg[17] ;
  input [5:0]\rxeq_fs_reg[5] ;
  input [5:0]\rxeq_lf_reg[5] ;

  wire [2:0]D;
  wire \FSM_onehot_fsm[1]_i_1__6_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__6_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__6_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2__6_n_0 ;
  wire \FSM_onehot_fsm[3]_i_3__6_n_0 ;
  wire \FSM_onehot_fsm[3]_i_4__6_n_0 ;
  wire \FSM_onehot_fsm[3]_i_5__5_n_0 ;
  wire \FSM_onehot_fsm[3]_i_7__5_n_0 ;
  wire \FSM_onehot_fsm[3]_i_8__5_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__6_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2__5_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3__6_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4__5_n_0 ;
  wire \FSM_onehot_fsm[4]_i_5__5_n_0 ;
  wire \FSM_onehot_fsm[4]_i_6__5_n_0 ;
  wire \FSM_onehot_fsm[4]_i_7__5_n_0 ;
  wire \FSM_onehot_fsm[4]_i_8__5_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[4] ;
  wire \FSM_sequential_fsm_rx_reg[0] ;
  wire [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  wire [3:0]Q;
  wire RST_CPLLRESET;
  wire USER_RXEQ_ADAPT_DONE;
  wire adapt_done;
  wire adapt_done_cnt;
  wire adapt_done_cnt_i_1__5_n_0;
  wire adapt_done_cnt_reg_n_0;
  wire [21:0]converge_cnt;
  wire [21:0]converge_cnt0;
  wire \converge_cnt[11]_i_3__5_n_0 ;
  wire \converge_cnt[11]_i_4__5_n_0 ;
  wire \converge_cnt[11]_i_5__5_n_0 ;
  wire \converge_cnt[11]_i_6__5_n_0 ;
  wire \converge_cnt[15]_i_3__5_n_0 ;
  wire \converge_cnt[15]_i_4__5_n_0 ;
  wire \converge_cnt[15]_i_5__5_n_0 ;
  wire \converge_cnt[15]_i_6__5_n_0 ;
  wire \converge_cnt[19]_i_3__5_n_0 ;
  wire \converge_cnt[19]_i_4__5_n_0 ;
  wire \converge_cnt[19]_i_5__5_n_0 ;
  wire \converge_cnt[19]_i_6__5_n_0 ;
  wire \converge_cnt[21]_i_3__5_n_0 ;
  wire \converge_cnt[21]_i_4__5_n_0 ;
  wire \converge_cnt[3]_i_3__5_n_0 ;
  wire \converge_cnt[3]_i_4__5_n_0 ;
  wire \converge_cnt[3]_i_5__5_n_0 ;
  wire \converge_cnt[3]_i_6__5_n_0 ;
  wire \converge_cnt[7]_i_3__5_n_0 ;
  wire \converge_cnt[7]_i_4__5_n_0 ;
  wire \converge_cnt[7]_i_5__5_n_0 ;
  wire \converge_cnt[7]_i_6__5_n_0 ;
  wire \converge_cnt_reg[11]_i_2__5_n_0 ;
  wire \converge_cnt_reg[11]_i_2__5_n_1 ;
  wire \converge_cnt_reg[11]_i_2__5_n_2 ;
  wire \converge_cnt_reg[11]_i_2__5_n_3 ;
  wire \converge_cnt_reg[15]_i_2__5_n_0 ;
  wire \converge_cnt_reg[15]_i_2__5_n_1 ;
  wire \converge_cnt_reg[15]_i_2__5_n_2 ;
  wire \converge_cnt_reg[15]_i_2__5_n_3 ;
  wire \converge_cnt_reg[19]_i_2__5_n_0 ;
  wire \converge_cnt_reg[19]_i_2__5_n_1 ;
  wire \converge_cnt_reg[19]_i_2__5_n_2 ;
  wire \converge_cnt_reg[19]_i_2__5_n_3 ;
  wire \converge_cnt_reg[21]_i_2__5_n_3 ;
  wire \converge_cnt_reg[3]_i_2__5_n_0 ;
  wire \converge_cnt_reg[3]_i_2__5_n_1 ;
  wire \converge_cnt_reg[3]_i_2__5_n_2 ;
  wire \converge_cnt_reg[3]_i_2__5_n_3 ;
  wire \converge_cnt_reg[7]_i_2__5_n_0 ;
  wire \converge_cnt_reg[7]_i_2__5_n_1 ;
  wire \converge_cnt_reg[7]_i_2__5_n_2 ;
  wire \converge_cnt_reg[7]_i_2__5_n_3 ;
  wire \converge_cnt_reg_n_0_[0] ;
  wire \converge_cnt_reg_n_0_[10] ;
  wire \converge_cnt_reg_n_0_[11] ;
  wire \converge_cnt_reg_n_0_[12] ;
  wire \converge_cnt_reg_n_0_[13] ;
  wire \converge_cnt_reg_n_0_[14] ;
  wire \converge_cnt_reg_n_0_[15] ;
  wire \converge_cnt_reg_n_0_[16] ;
  wire \converge_cnt_reg_n_0_[17] ;
  wire \converge_cnt_reg_n_0_[18] ;
  wire \converge_cnt_reg_n_0_[19] ;
  wire \converge_cnt_reg_n_0_[1] ;
  wire \converge_cnt_reg_n_0_[20] ;
  wire \converge_cnt_reg_n_0_[21] ;
  wire \converge_cnt_reg_n_0_[2] ;
  wire \converge_cnt_reg_n_0_[3] ;
  wire \converge_cnt_reg_n_0_[4] ;
  wire \converge_cnt_reg_n_0_[5] ;
  wire \converge_cnt_reg_n_0_[6] ;
  wire \converge_cnt_reg_n_0_[7] ;
  wire \converge_cnt_reg_n_0_[8] ;
  wire \converge_cnt_reg_n_0_[9] ;
  wire [5:0]fs_reg1;
  wire [5:0]fs_reg2;
  wire fsm1;
  wire [5:0]lf_reg1;
  wire [5:0]lf_reg2;
  wire new_txcoeff_done;
  wire new_txcoeff_req_reg1;
  wire new_txcoeff_req_reg2;
  wire [1:0]out;
  wire pclk_sel_reg;
  wire preset_done;
  wire [2:0]preset_reg1;
  wire [2:0]preset_reg2;
  wire preset_valid_reg1;
  wire preset_valid_reg2;
  wire rxeq_adapt_done_reg;
  wire rxeq_adapt_done_reg0;
  wire rxeq_adapt_done_reg_i_2__5_n_0;
  wire rxeq_adapt_done_reg_reg;
  wire rxeq_adapt_done_reg_reg_0;
  wire \rxeq_cnt_reg[1] ;
  wire \rxeq_cnt_reg[1]_0 ;
  wire \rxeq_control_reg2_reg[0] ;
  wire [5:0]\rxeq_fs_reg[5] ;
  wire [5:0]\rxeq_lf_reg[5] ;
  wire rxeq_new_txcoeff_req_reg;
  wire rxeq_new_txcoeff_req_reg_0;
  wire [2:0]\rxeq_preset_reg[2] ;
  wire rxeq_preset_valid_reg;
  wire [17:0]\rxeq_txcoeff_reg[17] ;
  wire rxeqscan_adapt_done;
  wire rxeqscan_new_txcoeff_done;
  wire rxeqscan_preset_done;
  wire [17:0]txcoeff_reg1;
  wire [17:0]txcoeff_reg2;
  wire [3:0]txpreset_reg1;
  wire [3:0]txpreset_reg2;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__5_CO_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__5_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h000000073333FF07)) 
    \FSM_onehot_fsm[1]_i_1__6 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(preset_valid_reg2),
        .O(\FSM_onehot_fsm[1]_i_1__6_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \FSM_onehot_fsm[2]_i_1__6 
       (.I0(preset_valid_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[2]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA8A8AA)) 
    \FSM_onehot_fsm[3]_i_1__6 
       (.I0(\FSM_onehot_fsm[3]_i_2__6_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_3__6_n_0 ),
        .I2(\FSM_onehot_fsm[3]_i_4__6_n_0 ),
        .I3(\converge_cnt_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm[3]_i_5__5_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h2020202020202F20)) 
    \FSM_onehot_fsm[3]_i_2__6 
       (.I0(new_txcoeff_req_reg2),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(fsm1),
        .I5(\FSM_onehot_fsm_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm[3]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFF6FFFFFFFF6FFF)) 
    \FSM_onehot_fsm[3]_i_3__6 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .I1(\converge_cnt_reg_n_0_[2] ),
        .I2(\converge_cnt_reg_n_0_[10] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[20] ),
        .O(\FSM_onehot_fsm[3]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'hFF7E7EFFFF7EFF7E)) 
    \FSM_onehot_fsm[3]_i_4__6 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[8] ),
        .I3(\converge_cnt_reg_n_0_[21] ),
        .I4(out[0]),
        .I5(out[1]),
        .O(\FSM_onehot_fsm[3]_i_4__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF9)) 
    \FSM_onehot_fsm[3]_i_5__5 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .I1(\converge_cnt_reg_n_0_[21] ),
        .I2(\converge_cnt_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[7] ),
        .I4(\FSM_onehot_fsm[3]_i_7__5_n_0 ),
        .I5(\FSM_onehot_fsm[3]_i_8__5_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_5__5_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_onehot_fsm[3]_i_6__5 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .O(fsm1));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[3]_i_7__5 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[16] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[3]_i_7__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFDFF)) 
    \FSM_onehot_fsm[3]_i_8__5 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .I1(\converge_cnt_reg_n_0_[4] ),
        .I2(\converge_cnt_reg_n_0_[12] ),
        .I3(\converge_cnt_reg_n_0_[9] ),
        .I4(\converge_cnt_reg_n_0_[5] ),
        .I5(\converge_cnt_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm[3]_i_8__5_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \FSM_onehot_fsm[4]_i_1__6 
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm[4]_i_2__5_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \FSM_onehot_fsm[4]_i_2__5 
       (.I0(\FSM_onehot_fsm[4]_i_3__6_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_4__5_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_5__5_n_0 ),
        .I3(\FSM_onehot_fsm[4]_i_6__5_n_0 ),
        .I4(\FSM_onehot_fsm[4]_i_7__5_n_0 ),
        .I5(\FSM_onehot_fsm[4]_i_8__5_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'h02020202FF000000)) 
    \FSM_onehot_fsm[4]_i_3__6 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_3__6_n_0 ));
  LUT6 #(
    .INIT(64'h00004B00004B0000)) 
    \FSM_onehot_fsm[4]_i_4__5 
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\converge_cnt_reg_n_0_[21] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[10] ),
        .O(\FSM_onehot_fsm[4]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'h0000810000810000)) 
    \FSM_onehot_fsm[4]_i_5__5 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[8] ),
        .I2(\converge_cnt_reg_n_0_[3] ),
        .I3(\converge_cnt_reg_n_0_[20] ),
        .I4(\converge_cnt_reg_n_0_[21] ),
        .I5(\converge_cnt_reg_n_0_[14] ),
        .O(\FSM_onehot_fsm[4]_i_5__5_n_0 ));
  LUT5 #(
    .INIT(32'h00000024)) 
    \FSM_onehot_fsm[4]_i_6__5 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[0] ),
        .I3(\converge_cnt_reg_n_0_[5] ),
        .I4(\converge_cnt_reg_n_0_[4] ),
        .O(\FSM_onehot_fsm[4]_i_6__5_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \FSM_onehot_fsm[4]_i_7__5 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\converge_cnt_reg_n_0_[11] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[9] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[4]_i_7__5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \FSM_onehot_fsm[4]_i_8__5 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .I1(\converge_cnt_reg_n_0_[6] ),
        .I2(\converge_cnt_reg_n_0_[16] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[19] ),
        .I5(\converge_cnt_reg_n_0_[7] ),
        .O(\FSM_onehot_fsm[4]_i_8__5_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__6_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__6_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__6_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__6_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hEFEEEEEE)) 
    \FSM_sequential_fsm_rx[0]_i_1__5 
       (.I0(\FSM_sequential_fsm_rx_reg[0] ),
        .I1(\rxeq_cnt_reg[1] ),
        .I2(rxeqscan_new_txcoeff_done),
        .I3(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h0CAF0CA0FF000F00)) 
    \FSM_sequential_fsm_rx[1]_i_1__5 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(\rxeq_cnt_reg[1]_0 ),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\rxeq_control_reg2_reg[0] ),
        .I5(\FSM_sequential_fsm_rx_reg[2] [0]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h3F083FC8330833C8)) 
    \FSM_sequential_fsm_rx[2]_i_1__5 
       (.I0(rxeqscan_preset_done),
        .I1(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I4(\rxeq_cnt_reg[1]_0 ),
        .I5(\rxeq_control_reg2_reg[0] ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'h00FF2A00)) 
    adapt_done_cnt_i_1__5
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(out[0]),
        .I2(out[1]),
        .I3(adapt_done_cnt),
        .I4(adapt_done_cnt_reg_n_0),
        .O(adapt_done_cnt_i_1__5_n_0));
  LUT6 #(
    .INIT(64'hFFFF444744444447)) 
    adapt_done_cnt_i_2__5
       (.I0(new_txcoeff_req_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I5(fsm1),
        .O(adapt_done_cnt));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_cnt_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done_cnt_i_1__5_n_0),
        .Q(adapt_done_cnt_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hA8880000)) 
    adapt_done_i_1__5
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[1]),
        .I3(out[0]),
        .I4(new_txcoeff_req_reg2),
        .O(adapt_done));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done),
        .Q(rxeqscan_adapt_done),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[0]_i_1__13 
       (.I0(converge_cnt0[0]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[0]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[10]_i_1__5 
       (.I0(converge_cnt0[10]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[10]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[11]_i_1__5 
       (.I0(converge_cnt0[11]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[11]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_3__5 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .O(\converge_cnt[11]_i_3__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_4__5 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .O(\converge_cnt[11]_i_4__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_5__5 
       (.I0(\converge_cnt_reg_n_0_[9] ),
        .O(\converge_cnt[11]_i_5__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_6__5 
       (.I0(\converge_cnt_reg_n_0_[8] ),
        .O(\converge_cnt[11]_i_6__5_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[12]_i_1__5 
       (.I0(converge_cnt0[12]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[12]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[13]_i_1__5 
       (.I0(converge_cnt0[13]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[13]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[14]_i_1__5 
       (.I0(converge_cnt0[14]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[14]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[15]_i_1__5 
       (.I0(converge_cnt0[15]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[15]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_3__5 
       (.I0(\converge_cnt_reg_n_0_[15] ),
        .O(\converge_cnt[15]_i_3__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_4__5 
       (.I0(\converge_cnt_reg_n_0_[14] ),
        .O(\converge_cnt[15]_i_4__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_5__5 
       (.I0(\converge_cnt_reg_n_0_[13] ),
        .O(\converge_cnt[15]_i_5__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_6__5 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .O(\converge_cnt[15]_i_6__5_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[16]_i_1__5 
       (.I0(converge_cnt0[16]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[16]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[17]_i_1__5 
       (.I0(converge_cnt0[17]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[17]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[18]_i_1__5 
       (.I0(converge_cnt0[18]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[18]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[19]_i_1__5 
       (.I0(converge_cnt0[19]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[19]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_3__5 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .O(\converge_cnt[19]_i_3__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_4__5 
       (.I0(\converge_cnt_reg_n_0_[18] ),
        .O(\converge_cnt[19]_i_4__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_5__5 
       (.I0(\converge_cnt_reg_n_0_[17] ),
        .O(\converge_cnt[19]_i_5__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_6__5 
       (.I0(\converge_cnt_reg_n_0_[16] ),
        .O(\converge_cnt[19]_i_6__5_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[1]_i_1__5 
       (.I0(converge_cnt0[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[1]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[20]_i_1__5 
       (.I0(converge_cnt0[20]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[20]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[21]_i_1__5 
       (.I0(converge_cnt0[21]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[21]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_3__5 
       (.I0(\converge_cnt_reg_n_0_[21] ),
        .O(\converge_cnt[21]_i_3__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_4__5 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .O(\converge_cnt[21]_i_4__5_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[2]_i_1__5 
       (.I0(converge_cnt0[2]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[2]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[3]_i_1__5 
       (.I0(converge_cnt0[3]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[3]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_3__5 
       (.I0(\converge_cnt_reg_n_0_[3] ),
        .O(\converge_cnt[3]_i_3__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_4__5 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .O(\converge_cnt[3]_i_4__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_5__5 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .O(\converge_cnt[3]_i_5__5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[3]_i_6__5 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .O(\converge_cnt[3]_i_6__5_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[4]_i_1__5 
       (.I0(converge_cnt0[4]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[4]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[5]_i_1__5 
       (.I0(converge_cnt0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[5]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[6]_i_1__5 
       (.I0(converge_cnt0[6]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[6]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[7]_i_1__5 
       (.I0(converge_cnt0[7]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[7]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_3__5 
       (.I0(\converge_cnt_reg_n_0_[7] ),
        .O(\converge_cnt[7]_i_3__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_4__5 
       (.I0(\converge_cnt_reg_n_0_[6] ),
        .O(\converge_cnt[7]_i_4__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_5__5 
       (.I0(\converge_cnt_reg_n_0_[5] ),
        .O(\converge_cnt[7]_i_5__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_6__5 
       (.I0(\converge_cnt_reg_n_0_[4] ),
        .O(\converge_cnt[7]_i_6__5_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[8]_i_1__5 
       (.I0(converge_cnt0[8]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[8]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[9]_i_1__5 
       (.I0(converge_cnt0[9]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[9]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[0]),
        .Q(\converge_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[10]),
        .Q(\converge_cnt_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[11]),
        .Q(\converge_cnt_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[11]_i_2__5 
       (.CI(\converge_cnt_reg[7]_i_2__5_n_0 ),
        .CO({\converge_cnt_reg[11]_i_2__5_n_0 ,\converge_cnt_reg[11]_i_2__5_n_1 ,\converge_cnt_reg[11]_i_2__5_n_2 ,\converge_cnt_reg[11]_i_2__5_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[11:8]),
        .S({\converge_cnt[11]_i_3__5_n_0 ,\converge_cnt[11]_i_4__5_n_0 ,\converge_cnt[11]_i_5__5_n_0 ,\converge_cnt[11]_i_6__5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[12]),
        .Q(\converge_cnt_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[13]),
        .Q(\converge_cnt_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[14]),
        .Q(\converge_cnt_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[15]),
        .Q(\converge_cnt_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[15]_i_2__5 
       (.CI(\converge_cnt_reg[11]_i_2__5_n_0 ),
        .CO({\converge_cnt_reg[15]_i_2__5_n_0 ,\converge_cnt_reg[15]_i_2__5_n_1 ,\converge_cnt_reg[15]_i_2__5_n_2 ,\converge_cnt_reg[15]_i_2__5_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[15:12]),
        .S({\converge_cnt[15]_i_3__5_n_0 ,\converge_cnt[15]_i_4__5_n_0 ,\converge_cnt[15]_i_5__5_n_0 ,\converge_cnt[15]_i_6__5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[16]),
        .Q(\converge_cnt_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[17]),
        .Q(\converge_cnt_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[18]),
        .Q(\converge_cnt_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[19]),
        .Q(\converge_cnt_reg_n_0_[19] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[19]_i_2__5 
       (.CI(\converge_cnt_reg[15]_i_2__5_n_0 ),
        .CO({\converge_cnt_reg[19]_i_2__5_n_0 ,\converge_cnt_reg[19]_i_2__5_n_1 ,\converge_cnt_reg[19]_i_2__5_n_2 ,\converge_cnt_reg[19]_i_2__5_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[19:16]),
        .S({\converge_cnt[19]_i_3__5_n_0 ,\converge_cnt[19]_i_4__5_n_0 ,\converge_cnt[19]_i_5__5_n_0 ,\converge_cnt[19]_i_6__5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[1]),
        .Q(\converge_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[20]),
        .Q(\converge_cnt_reg_n_0_[20] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[21]),
        .Q(\converge_cnt_reg_n_0_[21] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[21]_i_2__5 
       (.CI(\converge_cnt_reg[19]_i_2__5_n_0 ),
        .CO({\NLW_converge_cnt_reg[21]_i_2__5_CO_UNCONNECTED [3:1],\converge_cnt_reg[21]_i_2__5_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__5_O_UNCONNECTED [3:2],converge_cnt0[21:20]}),
        .S({1'b0,1'b0,\converge_cnt[21]_i_3__5_n_0 ,\converge_cnt[21]_i_4__5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[2]),
        .Q(\converge_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[3]),
        .Q(\converge_cnt_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[3]_i_2__5 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[3]_i_2__5_n_0 ,\converge_cnt_reg[3]_i_2__5_n_1 ,\converge_cnt_reg[3]_i_2__5_n_2 ,\converge_cnt_reg[3]_i_2__5_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\converge_cnt_reg_n_0_[0] }),
        .O(converge_cnt0[3:0]),
        .S({\converge_cnt[3]_i_3__5_n_0 ,\converge_cnt[3]_i_4__5_n_0 ,\converge_cnt[3]_i_5__5_n_0 ,\converge_cnt[3]_i_6__5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[4]),
        .Q(\converge_cnt_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[5]),
        .Q(\converge_cnt_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[6]),
        .Q(\converge_cnt_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[7]),
        .Q(\converge_cnt_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[7]_i_2__5 
       (.CI(\converge_cnt_reg[3]_i_2__5_n_0 ),
        .CO({\converge_cnt_reg[7]_i_2__5_n_0 ,\converge_cnt_reg[7]_i_2__5_n_1 ,\converge_cnt_reg[7]_i_2__5_n_2 ,\converge_cnt_reg[7]_i_2__5_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[7:4]),
        .S({\converge_cnt[7]_i_3__5_n_0 ,\converge_cnt[7]_i_4__5_n_0 ,\converge_cnt[7]_i_5__5_n_0 ,\converge_cnt[7]_i_6__5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[8]),
        .Q(\converge_cnt_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[9]),
        .Q(\converge_cnt_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [0]),
        .Q(fs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [1]),
        .Q(fs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [2]),
        .Q(fs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [3]),
        .Q(fs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [4]),
        .Q(fs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [5]),
        .Q(fs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[0]),
        .Q(fs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[1]),
        .Q(fs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[2]),
        .Q(fs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[3]),
        .Q(fs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[4]),
        .Q(fs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[5]),
        .Q(fs_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [0]),
        .Q(lf_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [1]),
        .Q(lf_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [2]),
        .Q(lf_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [3]),
        .Q(lf_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [4]),
        .Q(lf_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [5]),
        .Q(lf_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[0]),
        .Q(lf_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[1]),
        .Q(lf_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[2]),
        .Q(lf_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[3]),
        .Q(lf_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[4]),
        .Q(lf_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[5]),
        .Q(lf_reg2[5]),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    new_txcoeff_done_i_1__5
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .O(new_txcoeff_done));
  FDRE #(
    .INIT(1'b0)) 
    new_txcoeff_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_done),
        .Q(rxeqscan_new_txcoeff_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_new_txcoeff_req_reg_0),
        .Q(new_txcoeff_req_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1),
        .Q(new_txcoeff_req_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hEA)) 
    preset_done_i_1__5
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(preset_done));
  FDRE #(
    .INIT(1'b0)) 
    preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_done),
        .Q(rxeqscan_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [0]),
        .Q(preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [1]),
        .Q(preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [2]),
        .Q(preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[0]),
        .Q(preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[1]),
        .Q(preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[2]),
        .Q(preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid_reg),
        .Q(preset_valid_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_valid_reg1),
        .Q(preset_valid_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0080F00000800000)) 
    rxeq_adapt_done_i_1__5
       (.I0(rxeq_adapt_done_reg0),
        .I1(rxeqscan_new_txcoeff_done),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I5(USER_RXEQ_ADAPT_DONE),
        .O(rxeq_adapt_done_reg));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rxeq_adapt_done_i_2__5
       (.I0(rxeqscan_adapt_done),
        .I1(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg0));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT5 #(
    .INIT(32'h44FF4000)) 
    rxeq_adapt_done_reg_i_1__5
       (.I0(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(rxeqscan_adapt_done),
        .I3(rxeq_adapt_done_reg_i_2__5_n_0),
        .I4(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg_reg));
  LUT6 #(
    .INIT(64'hF0F0002FF000002F)) 
    rxeq_adapt_done_reg_i_2__5
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I5(rxeqscan_new_txcoeff_done),
        .O(rxeq_adapt_done_reg_i_2__5_n_0));
  LUT4 #(
    .INIT(16'h0008)) 
    rxeq_new_txcoeff_req_i_1__5
       (.I0(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I3(rxeqscan_new_txcoeff_done),
        .O(rxeq_new_txcoeff_req_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [0]),
        .Q(txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [10]),
        .Q(txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [11]),
        .Q(txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [12]),
        .Q(txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [13]),
        .Q(txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [14]),
        .Q(txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [15]),
        .Q(txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [16]),
        .Q(txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [17]),
        .Q(txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [1]),
        .Q(txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [2]),
        .Q(txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [3]),
        .Q(txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [4]),
        .Q(txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [5]),
        .Q(txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [6]),
        .Q(txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [7]),
        .Q(txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [8]),
        .Q(txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [9]),
        .Q(txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[0]),
        .Q(txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[10]),
        .Q(txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[11]),
        .Q(txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[12]),
        .Q(txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[13]),
        .Q(txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[14]),
        .Q(txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[15]),
        .Q(txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[16]),
        .Q(txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[17]),
        .Q(txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[1]),
        .Q(txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[2]),
        .Q(txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[3]),
        .Q(txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[4]),
        .Q(txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[5]),
        .Q(txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[6]),
        .Q(txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[7]),
        .Q(txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[8]),
        .Q(txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[9]),
        .Q(txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[0]),
        .Q(txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[1]),
        .Q(txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[2]),
        .Q(txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[3]),
        .Q(txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[0]),
        .Q(txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[1]),
        .Q(txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[2]),
        .Q(txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[3]),
        .Q(txpreset_reg2[3]),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_rxeq_scan" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_74
   (D,
    rxeq_new_txcoeff_req_reg,
    rxeq_adapt_done_reg,
    rxeq_adapt_done_reg_reg,
    RST_CPLLRESET,
    rxeq_new_txcoeff_req_reg_0,
    pclk_sel_reg,
    rxeq_preset_valid_reg,
    out,
    \FSM_sequential_fsm_rx_reg[0] ,
    \rxeq_cnt_reg[1] ,
    \FSM_sequential_fsm_rx_reg[2] ,
    \rxeq_cnt_reg[1]_0 ,
    \rxeq_control_reg2_reg[0] ,
    rxeq_adapt_done_reg_reg_0,
    USER_RXEQ_ADAPT_DONE,
    \rxeq_preset_reg[2] ,
    Q,
    \rxeq_txcoeff_reg[17] ,
    \rxeq_fs_reg[5] ,
    \rxeq_lf_reg[5] );
  output [2:0]D;
  output rxeq_new_txcoeff_req_reg;
  output rxeq_adapt_done_reg;
  output rxeq_adapt_done_reg_reg;
  input RST_CPLLRESET;
  input rxeq_new_txcoeff_req_reg_0;
  input pclk_sel_reg;
  input rxeq_preset_valid_reg;
  input [1:0]out;
  input \FSM_sequential_fsm_rx_reg[0] ;
  input \rxeq_cnt_reg[1] ;
  input [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  input \rxeq_cnt_reg[1]_0 ;
  input \rxeq_control_reg2_reg[0] ;
  input rxeq_adapt_done_reg_reg_0;
  input USER_RXEQ_ADAPT_DONE;
  input [2:0]\rxeq_preset_reg[2] ;
  input [3:0]Q;
  input [17:0]\rxeq_txcoeff_reg[17] ;
  input [5:0]\rxeq_fs_reg[5] ;
  input [5:0]\rxeq_lf_reg[5] ;

  wire [2:0]D;
  wire \FSM_onehot_fsm[1]_i_1__5_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__5_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__5_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2__5_n_0 ;
  wire \FSM_onehot_fsm[3]_i_3__5_n_0 ;
  wire \FSM_onehot_fsm[3]_i_4__5_n_0 ;
  wire \FSM_onehot_fsm[3]_i_5__4_n_0 ;
  wire \FSM_onehot_fsm[3]_i_7__4_n_0 ;
  wire \FSM_onehot_fsm[3]_i_8__4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__5_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2__4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3__5_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4__4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_5__4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_6__4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_7__4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_8__4_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[4] ;
  wire \FSM_sequential_fsm_rx_reg[0] ;
  wire [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  wire [3:0]Q;
  wire RST_CPLLRESET;
  wire USER_RXEQ_ADAPT_DONE;
  wire adapt_done;
  wire adapt_done_cnt;
  wire adapt_done_cnt_i_1__4_n_0;
  wire adapt_done_cnt_reg_n_0;
  wire [21:0]converge_cnt;
  wire [21:0]converge_cnt0;
  wire \converge_cnt[11]_i_3__4_n_0 ;
  wire \converge_cnt[11]_i_4__4_n_0 ;
  wire \converge_cnt[11]_i_5__4_n_0 ;
  wire \converge_cnt[11]_i_6__4_n_0 ;
  wire \converge_cnt[15]_i_3__4_n_0 ;
  wire \converge_cnt[15]_i_4__4_n_0 ;
  wire \converge_cnt[15]_i_5__4_n_0 ;
  wire \converge_cnt[15]_i_6__4_n_0 ;
  wire \converge_cnt[19]_i_3__4_n_0 ;
  wire \converge_cnt[19]_i_4__4_n_0 ;
  wire \converge_cnt[19]_i_5__4_n_0 ;
  wire \converge_cnt[19]_i_6__4_n_0 ;
  wire \converge_cnt[21]_i_3__4_n_0 ;
  wire \converge_cnt[21]_i_4__4_n_0 ;
  wire \converge_cnt[3]_i_3__4_n_0 ;
  wire \converge_cnt[3]_i_4__4_n_0 ;
  wire \converge_cnt[3]_i_5__4_n_0 ;
  wire \converge_cnt[3]_i_6__4_n_0 ;
  wire \converge_cnt[7]_i_3__4_n_0 ;
  wire \converge_cnt[7]_i_4__4_n_0 ;
  wire \converge_cnt[7]_i_5__4_n_0 ;
  wire \converge_cnt[7]_i_6__4_n_0 ;
  wire \converge_cnt_reg[11]_i_2__4_n_0 ;
  wire \converge_cnt_reg[11]_i_2__4_n_1 ;
  wire \converge_cnt_reg[11]_i_2__4_n_2 ;
  wire \converge_cnt_reg[11]_i_2__4_n_3 ;
  wire \converge_cnt_reg[15]_i_2__4_n_0 ;
  wire \converge_cnt_reg[15]_i_2__4_n_1 ;
  wire \converge_cnt_reg[15]_i_2__4_n_2 ;
  wire \converge_cnt_reg[15]_i_2__4_n_3 ;
  wire \converge_cnt_reg[19]_i_2__4_n_0 ;
  wire \converge_cnt_reg[19]_i_2__4_n_1 ;
  wire \converge_cnt_reg[19]_i_2__4_n_2 ;
  wire \converge_cnt_reg[19]_i_2__4_n_3 ;
  wire \converge_cnt_reg[21]_i_2__4_n_3 ;
  wire \converge_cnt_reg[3]_i_2__4_n_0 ;
  wire \converge_cnt_reg[3]_i_2__4_n_1 ;
  wire \converge_cnt_reg[3]_i_2__4_n_2 ;
  wire \converge_cnt_reg[3]_i_2__4_n_3 ;
  wire \converge_cnt_reg[7]_i_2__4_n_0 ;
  wire \converge_cnt_reg[7]_i_2__4_n_1 ;
  wire \converge_cnt_reg[7]_i_2__4_n_2 ;
  wire \converge_cnt_reg[7]_i_2__4_n_3 ;
  wire \converge_cnt_reg_n_0_[0] ;
  wire \converge_cnt_reg_n_0_[10] ;
  wire \converge_cnt_reg_n_0_[11] ;
  wire \converge_cnt_reg_n_0_[12] ;
  wire \converge_cnt_reg_n_0_[13] ;
  wire \converge_cnt_reg_n_0_[14] ;
  wire \converge_cnt_reg_n_0_[15] ;
  wire \converge_cnt_reg_n_0_[16] ;
  wire \converge_cnt_reg_n_0_[17] ;
  wire \converge_cnt_reg_n_0_[18] ;
  wire \converge_cnt_reg_n_0_[19] ;
  wire \converge_cnt_reg_n_0_[1] ;
  wire \converge_cnt_reg_n_0_[20] ;
  wire \converge_cnt_reg_n_0_[21] ;
  wire \converge_cnt_reg_n_0_[2] ;
  wire \converge_cnt_reg_n_0_[3] ;
  wire \converge_cnt_reg_n_0_[4] ;
  wire \converge_cnt_reg_n_0_[5] ;
  wire \converge_cnt_reg_n_0_[6] ;
  wire \converge_cnt_reg_n_0_[7] ;
  wire \converge_cnt_reg_n_0_[8] ;
  wire \converge_cnt_reg_n_0_[9] ;
  wire [5:0]fs_reg1;
  wire [5:0]fs_reg2;
  wire fsm1;
  wire [5:0]lf_reg1;
  wire [5:0]lf_reg2;
  wire new_txcoeff_done;
  wire new_txcoeff_req_reg1;
  wire new_txcoeff_req_reg2;
  wire [1:0]out;
  wire pclk_sel_reg;
  wire preset_done;
  wire [2:0]preset_reg1;
  wire [2:0]preset_reg2;
  wire preset_valid_reg1;
  wire preset_valid_reg2;
  wire rxeq_adapt_done_reg;
  wire rxeq_adapt_done_reg0;
  wire rxeq_adapt_done_reg_i_2__4_n_0;
  wire rxeq_adapt_done_reg_reg;
  wire rxeq_adapt_done_reg_reg_0;
  wire \rxeq_cnt_reg[1] ;
  wire \rxeq_cnt_reg[1]_0 ;
  wire \rxeq_control_reg2_reg[0] ;
  wire [5:0]\rxeq_fs_reg[5] ;
  wire [5:0]\rxeq_lf_reg[5] ;
  wire rxeq_new_txcoeff_req_reg;
  wire rxeq_new_txcoeff_req_reg_0;
  wire [2:0]\rxeq_preset_reg[2] ;
  wire rxeq_preset_valid_reg;
  wire [17:0]\rxeq_txcoeff_reg[17] ;
  wire rxeqscan_adapt_done;
  wire rxeqscan_new_txcoeff_done;
  wire rxeqscan_preset_done;
  wire [17:0]txcoeff_reg1;
  wire [17:0]txcoeff_reg2;
  wire [3:0]txpreset_reg1;
  wire [3:0]txpreset_reg2;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__4_CO_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__4_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h000000073333FF07)) 
    \FSM_onehot_fsm[1]_i_1__5 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(preset_valid_reg2),
        .O(\FSM_onehot_fsm[1]_i_1__5_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \FSM_onehot_fsm[2]_i_1__5 
       (.I0(preset_valid_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[2]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA8A8AA)) 
    \FSM_onehot_fsm[3]_i_1__5 
       (.I0(\FSM_onehot_fsm[3]_i_2__5_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_3__5_n_0 ),
        .I2(\FSM_onehot_fsm[3]_i_4__5_n_0 ),
        .I3(\converge_cnt_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm[3]_i_5__4_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h2020202020202F20)) 
    \FSM_onehot_fsm[3]_i_2__5 
       (.I0(new_txcoeff_req_reg2),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(fsm1),
        .I5(\FSM_onehot_fsm_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm[3]_i_2__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFF6FFFFFFFF6FFF)) 
    \FSM_onehot_fsm[3]_i_3__5 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .I1(\converge_cnt_reg_n_0_[2] ),
        .I2(\converge_cnt_reg_n_0_[10] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[20] ),
        .O(\FSM_onehot_fsm[3]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'hFF7E7EFFFF7EFF7E)) 
    \FSM_onehot_fsm[3]_i_4__5 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[8] ),
        .I3(\converge_cnt_reg_n_0_[21] ),
        .I4(out[0]),
        .I5(out[1]),
        .O(\FSM_onehot_fsm[3]_i_4__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF9)) 
    \FSM_onehot_fsm[3]_i_5__4 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .I1(\converge_cnt_reg_n_0_[21] ),
        .I2(\converge_cnt_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[7] ),
        .I4(\FSM_onehot_fsm[3]_i_7__4_n_0 ),
        .I5(\FSM_onehot_fsm[3]_i_8__4_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_5__4_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_onehot_fsm[3]_i_6__4 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .O(fsm1));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[3]_i_7__4 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[16] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[3]_i_7__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFDFF)) 
    \FSM_onehot_fsm[3]_i_8__4 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .I1(\converge_cnt_reg_n_0_[4] ),
        .I2(\converge_cnt_reg_n_0_[12] ),
        .I3(\converge_cnt_reg_n_0_[9] ),
        .I4(\converge_cnt_reg_n_0_[5] ),
        .I5(\converge_cnt_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm[3]_i_8__4_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \FSM_onehot_fsm[4]_i_1__5 
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm[4]_i_2__4_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \FSM_onehot_fsm[4]_i_2__4 
       (.I0(\FSM_onehot_fsm[4]_i_3__5_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_4__4_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_5__4_n_0 ),
        .I3(\FSM_onehot_fsm[4]_i_6__4_n_0 ),
        .I4(\FSM_onehot_fsm[4]_i_7__4_n_0 ),
        .I5(\FSM_onehot_fsm[4]_i_8__4_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'h02020202FF000000)) 
    \FSM_onehot_fsm[4]_i_3__5 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_3__5_n_0 ));
  LUT6 #(
    .INIT(64'h00004B00004B0000)) 
    \FSM_onehot_fsm[4]_i_4__4 
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\converge_cnt_reg_n_0_[21] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[10] ),
        .O(\FSM_onehot_fsm[4]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'h0000810000810000)) 
    \FSM_onehot_fsm[4]_i_5__4 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[8] ),
        .I2(\converge_cnt_reg_n_0_[3] ),
        .I3(\converge_cnt_reg_n_0_[20] ),
        .I4(\converge_cnt_reg_n_0_[21] ),
        .I5(\converge_cnt_reg_n_0_[14] ),
        .O(\FSM_onehot_fsm[4]_i_5__4_n_0 ));
  LUT5 #(
    .INIT(32'h00000024)) 
    \FSM_onehot_fsm[4]_i_6__4 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[0] ),
        .I3(\converge_cnt_reg_n_0_[5] ),
        .I4(\converge_cnt_reg_n_0_[4] ),
        .O(\FSM_onehot_fsm[4]_i_6__4_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \FSM_onehot_fsm[4]_i_7__4 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\converge_cnt_reg_n_0_[11] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[9] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[4]_i_7__4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \FSM_onehot_fsm[4]_i_8__4 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .I1(\converge_cnt_reg_n_0_[6] ),
        .I2(\converge_cnt_reg_n_0_[16] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[19] ),
        .I5(\converge_cnt_reg_n_0_[7] ),
        .O(\FSM_onehot_fsm[4]_i_8__4_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__5_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__5_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__5_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__5_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hEFEEEEEE)) 
    \FSM_sequential_fsm_rx[0]_i_1__4 
       (.I0(\FSM_sequential_fsm_rx_reg[0] ),
        .I1(\rxeq_cnt_reg[1] ),
        .I2(rxeqscan_new_txcoeff_done),
        .I3(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h0CAF0CA0FF000F00)) 
    \FSM_sequential_fsm_rx[1]_i_1__4 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(\rxeq_cnt_reg[1]_0 ),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\rxeq_control_reg2_reg[0] ),
        .I5(\FSM_sequential_fsm_rx_reg[2] [0]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h3F083FC8330833C8)) 
    \FSM_sequential_fsm_rx[2]_i_1__4 
       (.I0(rxeqscan_preset_done),
        .I1(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I4(\rxeq_cnt_reg[1]_0 ),
        .I5(\rxeq_control_reg2_reg[0] ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'h00FF2A00)) 
    adapt_done_cnt_i_1__4
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(out[0]),
        .I2(out[1]),
        .I3(adapt_done_cnt),
        .I4(adapt_done_cnt_reg_n_0),
        .O(adapt_done_cnt_i_1__4_n_0));
  LUT6 #(
    .INIT(64'hFFFF444744444447)) 
    adapt_done_cnt_i_2__4
       (.I0(new_txcoeff_req_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I5(fsm1),
        .O(adapt_done_cnt));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_cnt_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done_cnt_i_1__4_n_0),
        .Q(adapt_done_cnt_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hA8880000)) 
    adapt_done_i_1__4
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[1]),
        .I3(out[0]),
        .I4(new_txcoeff_req_reg2),
        .O(adapt_done));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done),
        .Q(rxeqscan_adapt_done),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[0]_i_1__12 
       (.I0(converge_cnt0[0]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[0]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[10]_i_1__4 
       (.I0(converge_cnt0[10]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[10]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[11]_i_1__4 
       (.I0(converge_cnt0[11]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[11]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_3__4 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .O(\converge_cnt[11]_i_3__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_4__4 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .O(\converge_cnt[11]_i_4__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_5__4 
       (.I0(\converge_cnt_reg_n_0_[9] ),
        .O(\converge_cnt[11]_i_5__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_6__4 
       (.I0(\converge_cnt_reg_n_0_[8] ),
        .O(\converge_cnt[11]_i_6__4_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[12]_i_1__4 
       (.I0(converge_cnt0[12]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[12]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[13]_i_1__4 
       (.I0(converge_cnt0[13]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[13]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[14]_i_1__4 
       (.I0(converge_cnt0[14]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[14]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[15]_i_1__4 
       (.I0(converge_cnt0[15]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[15]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_3__4 
       (.I0(\converge_cnt_reg_n_0_[15] ),
        .O(\converge_cnt[15]_i_3__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_4__4 
       (.I0(\converge_cnt_reg_n_0_[14] ),
        .O(\converge_cnt[15]_i_4__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_5__4 
       (.I0(\converge_cnt_reg_n_0_[13] ),
        .O(\converge_cnt[15]_i_5__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_6__4 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .O(\converge_cnt[15]_i_6__4_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[16]_i_1__4 
       (.I0(converge_cnt0[16]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[16]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[17]_i_1__4 
       (.I0(converge_cnt0[17]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[17]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[18]_i_1__4 
       (.I0(converge_cnt0[18]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[18]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[19]_i_1__4 
       (.I0(converge_cnt0[19]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[19]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_3__4 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .O(\converge_cnt[19]_i_3__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_4__4 
       (.I0(\converge_cnt_reg_n_0_[18] ),
        .O(\converge_cnt[19]_i_4__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_5__4 
       (.I0(\converge_cnt_reg_n_0_[17] ),
        .O(\converge_cnt[19]_i_5__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_6__4 
       (.I0(\converge_cnt_reg_n_0_[16] ),
        .O(\converge_cnt[19]_i_6__4_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[1]_i_1__4 
       (.I0(converge_cnt0[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[1]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[20]_i_1__4 
       (.I0(converge_cnt0[20]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[20]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[21]_i_1__4 
       (.I0(converge_cnt0[21]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[21]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_3__4 
       (.I0(\converge_cnt_reg_n_0_[21] ),
        .O(\converge_cnt[21]_i_3__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_4__4 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .O(\converge_cnt[21]_i_4__4_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[2]_i_1__4 
       (.I0(converge_cnt0[2]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[2]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[3]_i_1__4 
       (.I0(converge_cnt0[3]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[3]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_3__4 
       (.I0(\converge_cnt_reg_n_0_[3] ),
        .O(\converge_cnt[3]_i_3__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_4__4 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .O(\converge_cnt[3]_i_4__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_5__4 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .O(\converge_cnt[3]_i_5__4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[3]_i_6__4 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .O(\converge_cnt[3]_i_6__4_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[4]_i_1__4 
       (.I0(converge_cnt0[4]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[4]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[5]_i_1__4 
       (.I0(converge_cnt0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[5]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[6]_i_1__4 
       (.I0(converge_cnt0[6]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[6]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[7]_i_1__4 
       (.I0(converge_cnt0[7]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[7]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_3__4 
       (.I0(\converge_cnt_reg_n_0_[7] ),
        .O(\converge_cnt[7]_i_3__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_4__4 
       (.I0(\converge_cnt_reg_n_0_[6] ),
        .O(\converge_cnt[7]_i_4__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_5__4 
       (.I0(\converge_cnt_reg_n_0_[5] ),
        .O(\converge_cnt[7]_i_5__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_6__4 
       (.I0(\converge_cnt_reg_n_0_[4] ),
        .O(\converge_cnt[7]_i_6__4_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[8]_i_1__4 
       (.I0(converge_cnt0[8]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[8]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[9]_i_1__4 
       (.I0(converge_cnt0[9]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[9]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[0]),
        .Q(\converge_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[10]),
        .Q(\converge_cnt_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[11]),
        .Q(\converge_cnt_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[11]_i_2__4 
       (.CI(\converge_cnt_reg[7]_i_2__4_n_0 ),
        .CO({\converge_cnt_reg[11]_i_2__4_n_0 ,\converge_cnt_reg[11]_i_2__4_n_1 ,\converge_cnt_reg[11]_i_2__4_n_2 ,\converge_cnt_reg[11]_i_2__4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[11:8]),
        .S({\converge_cnt[11]_i_3__4_n_0 ,\converge_cnt[11]_i_4__4_n_0 ,\converge_cnt[11]_i_5__4_n_0 ,\converge_cnt[11]_i_6__4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[12]),
        .Q(\converge_cnt_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[13]),
        .Q(\converge_cnt_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[14]),
        .Q(\converge_cnt_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[15]),
        .Q(\converge_cnt_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[15]_i_2__4 
       (.CI(\converge_cnt_reg[11]_i_2__4_n_0 ),
        .CO({\converge_cnt_reg[15]_i_2__4_n_0 ,\converge_cnt_reg[15]_i_2__4_n_1 ,\converge_cnt_reg[15]_i_2__4_n_2 ,\converge_cnt_reg[15]_i_2__4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[15:12]),
        .S({\converge_cnt[15]_i_3__4_n_0 ,\converge_cnt[15]_i_4__4_n_0 ,\converge_cnt[15]_i_5__4_n_0 ,\converge_cnt[15]_i_6__4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[16]),
        .Q(\converge_cnt_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[17]),
        .Q(\converge_cnt_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[18]),
        .Q(\converge_cnt_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[19]),
        .Q(\converge_cnt_reg_n_0_[19] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[19]_i_2__4 
       (.CI(\converge_cnt_reg[15]_i_2__4_n_0 ),
        .CO({\converge_cnt_reg[19]_i_2__4_n_0 ,\converge_cnt_reg[19]_i_2__4_n_1 ,\converge_cnt_reg[19]_i_2__4_n_2 ,\converge_cnt_reg[19]_i_2__4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[19:16]),
        .S({\converge_cnt[19]_i_3__4_n_0 ,\converge_cnt[19]_i_4__4_n_0 ,\converge_cnt[19]_i_5__4_n_0 ,\converge_cnt[19]_i_6__4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[1]),
        .Q(\converge_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[20]),
        .Q(\converge_cnt_reg_n_0_[20] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[21]),
        .Q(\converge_cnt_reg_n_0_[21] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[21]_i_2__4 
       (.CI(\converge_cnt_reg[19]_i_2__4_n_0 ),
        .CO({\NLW_converge_cnt_reg[21]_i_2__4_CO_UNCONNECTED [3:1],\converge_cnt_reg[21]_i_2__4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__4_O_UNCONNECTED [3:2],converge_cnt0[21:20]}),
        .S({1'b0,1'b0,\converge_cnt[21]_i_3__4_n_0 ,\converge_cnt[21]_i_4__4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[2]),
        .Q(\converge_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[3]),
        .Q(\converge_cnt_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[3]_i_2__4 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[3]_i_2__4_n_0 ,\converge_cnt_reg[3]_i_2__4_n_1 ,\converge_cnt_reg[3]_i_2__4_n_2 ,\converge_cnt_reg[3]_i_2__4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\converge_cnt_reg_n_0_[0] }),
        .O(converge_cnt0[3:0]),
        .S({\converge_cnt[3]_i_3__4_n_0 ,\converge_cnt[3]_i_4__4_n_0 ,\converge_cnt[3]_i_5__4_n_0 ,\converge_cnt[3]_i_6__4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[4]),
        .Q(\converge_cnt_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[5]),
        .Q(\converge_cnt_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[6]),
        .Q(\converge_cnt_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[7]),
        .Q(\converge_cnt_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[7]_i_2__4 
       (.CI(\converge_cnt_reg[3]_i_2__4_n_0 ),
        .CO({\converge_cnt_reg[7]_i_2__4_n_0 ,\converge_cnt_reg[7]_i_2__4_n_1 ,\converge_cnt_reg[7]_i_2__4_n_2 ,\converge_cnt_reg[7]_i_2__4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[7:4]),
        .S({\converge_cnt[7]_i_3__4_n_0 ,\converge_cnt[7]_i_4__4_n_0 ,\converge_cnt[7]_i_5__4_n_0 ,\converge_cnt[7]_i_6__4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[8]),
        .Q(\converge_cnt_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[9]),
        .Q(\converge_cnt_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [0]),
        .Q(fs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [1]),
        .Q(fs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [2]),
        .Q(fs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [3]),
        .Q(fs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [4]),
        .Q(fs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [5]),
        .Q(fs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[0]),
        .Q(fs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[1]),
        .Q(fs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[2]),
        .Q(fs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[3]),
        .Q(fs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[4]),
        .Q(fs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[5]),
        .Q(fs_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [0]),
        .Q(lf_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [1]),
        .Q(lf_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [2]),
        .Q(lf_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [3]),
        .Q(lf_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [4]),
        .Q(lf_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [5]),
        .Q(lf_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[0]),
        .Q(lf_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[1]),
        .Q(lf_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[2]),
        .Q(lf_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[3]),
        .Q(lf_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[4]),
        .Q(lf_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[5]),
        .Q(lf_reg2[5]),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    new_txcoeff_done_i_1__4
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .O(new_txcoeff_done));
  FDRE #(
    .INIT(1'b0)) 
    new_txcoeff_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_done),
        .Q(rxeqscan_new_txcoeff_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_new_txcoeff_req_reg_0),
        .Q(new_txcoeff_req_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1),
        .Q(new_txcoeff_req_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hEA)) 
    preset_done_i_1__4
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(preset_done));
  FDRE #(
    .INIT(1'b0)) 
    preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_done),
        .Q(rxeqscan_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [0]),
        .Q(preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [1]),
        .Q(preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [2]),
        .Q(preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[0]),
        .Q(preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[1]),
        .Q(preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[2]),
        .Q(preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid_reg),
        .Q(preset_valid_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_valid_reg1),
        .Q(preset_valid_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0080F00000800000)) 
    rxeq_adapt_done_i_1__4
       (.I0(rxeq_adapt_done_reg0),
        .I1(rxeqscan_new_txcoeff_done),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I5(USER_RXEQ_ADAPT_DONE),
        .O(rxeq_adapt_done_reg));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rxeq_adapt_done_i_2__4
       (.I0(rxeqscan_adapt_done),
        .I1(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg0));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT5 #(
    .INIT(32'h44FF4000)) 
    rxeq_adapt_done_reg_i_1__4
       (.I0(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(rxeqscan_adapt_done),
        .I3(rxeq_adapt_done_reg_i_2__4_n_0),
        .I4(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg_reg));
  LUT6 #(
    .INIT(64'hF0F0002FF000002F)) 
    rxeq_adapt_done_reg_i_2__4
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I5(rxeqscan_new_txcoeff_done),
        .O(rxeq_adapt_done_reg_i_2__4_n_0));
  LUT4 #(
    .INIT(16'h0008)) 
    rxeq_new_txcoeff_req_i_1__4
       (.I0(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I3(rxeqscan_new_txcoeff_done),
        .O(rxeq_new_txcoeff_req_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [0]),
        .Q(txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [10]),
        .Q(txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [11]),
        .Q(txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [12]),
        .Q(txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [13]),
        .Q(txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [14]),
        .Q(txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [15]),
        .Q(txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [16]),
        .Q(txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [17]),
        .Q(txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [1]),
        .Q(txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [2]),
        .Q(txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [3]),
        .Q(txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [4]),
        .Q(txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [5]),
        .Q(txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [6]),
        .Q(txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [7]),
        .Q(txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [8]),
        .Q(txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [9]),
        .Q(txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[0]),
        .Q(txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[10]),
        .Q(txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[11]),
        .Q(txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[12]),
        .Q(txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[13]),
        .Q(txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[14]),
        .Q(txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[15]),
        .Q(txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[16]),
        .Q(txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[17]),
        .Q(txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[1]),
        .Q(txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[2]),
        .Q(txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[3]),
        .Q(txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[4]),
        .Q(txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[5]),
        .Q(txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[6]),
        .Q(txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[7]),
        .Q(txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[8]),
        .Q(txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[9]),
        .Q(txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[0]),
        .Q(txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[1]),
        .Q(txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[2]),
        .Q(txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[3]),
        .Q(txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[0]),
        .Q(txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[1]),
        .Q(txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[2]),
        .Q(txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[3]),
        .Q(txpreset_reg2[3]),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_rxeq_scan" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_76
   (D,
    rxeq_new_txcoeff_req_reg,
    rxeq_adapt_done_reg,
    rxeq_adapt_done_reg_reg,
    RST_CPLLRESET,
    rxeq_new_txcoeff_req_reg_0,
    pclk_sel_reg,
    rxeq_preset_valid_reg,
    out,
    \FSM_sequential_fsm_rx_reg[0] ,
    \rxeq_cnt_reg[1] ,
    \FSM_sequential_fsm_rx_reg[2] ,
    \rxeq_cnt_reg[1]_0 ,
    \rxeq_control_reg2_reg[0] ,
    rxeq_adapt_done_reg_reg_0,
    USER_RXEQ_ADAPT_DONE,
    \rxeq_preset_reg[2] ,
    Q,
    \rxeq_txcoeff_reg[17] ,
    \rxeq_fs_reg[5] ,
    \rxeq_lf_reg[5] );
  output [2:0]D;
  output rxeq_new_txcoeff_req_reg;
  output rxeq_adapt_done_reg;
  output rxeq_adapt_done_reg_reg;
  input RST_CPLLRESET;
  input rxeq_new_txcoeff_req_reg_0;
  input pclk_sel_reg;
  input rxeq_preset_valid_reg;
  input [1:0]out;
  input \FSM_sequential_fsm_rx_reg[0] ;
  input \rxeq_cnt_reg[1] ;
  input [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  input \rxeq_cnt_reg[1]_0 ;
  input \rxeq_control_reg2_reg[0] ;
  input rxeq_adapt_done_reg_reg_0;
  input USER_RXEQ_ADAPT_DONE;
  input [2:0]\rxeq_preset_reg[2] ;
  input [3:0]Q;
  input [17:0]\rxeq_txcoeff_reg[17] ;
  input [5:0]\rxeq_fs_reg[5] ;
  input [5:0]\rxeq_lf_reg[5] ;

  wire [2:0]D;
  wire \FSM_onehot_fsm[1]_i_1__4_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__4_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__4_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2__4_n_0 ;
  wire \FSM_onehot_fsm[3]_i_3__4_n_0 ;
  wire \FSM_onehot_fsm[3]_i_4__4_n_0 ;
  wire \FSM_onehot_fsm[3]_i_5__3_n_0 ;
  wire \FSM_onehot_fsm[3]_i_7__3_n_0 ;
  wire \FSM_onehot_fsm[3]_i_8__3_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2__3_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3__4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4__3_n_0 ;
  wire \FSM_onehot_fsm[4]_i_5__3_n_0 ;
  wire \FSM_onehot_fsm[4]_i_6__3_n_0 ;
  wire \FSM_onehot_fsm[4]_i_7__3_n_0 ;
  wire \FSM_onehot_fsm[4]_i_8__3_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[4] ;
  wire \FSM_sequential_fsm_rx_reg[0] ;
  wire [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  wire [3:0]Q;
  wire RST_CPLLRESET;
  wire USER_RXEQ_ADAPT_DONE;
  wire adapt_done;
  wire adapt_done_cnt;
  wire adapt_done_cnt_i_1__3_n_0;
  wire adapt_done_cnt_reg_n_0;
  wire [21:0]converge_cnt;
  wire [21:0]converge_cnt0;
  wire \converge_cnt[11]_i_3__3_n_0 ;
  wire \converge_cnt[11]_i_4__3_n_0 ;
  wire \converge_cnt[11]_i_5__3_n_0 ;
  wire \converge_cnt[11]_i_6__3_n_0 ;
  wire \converge_cnt[15]_i_3__3_n_0 ;
  wire \converge_cnt[15]_i_4__3_n_0 ;
  wire \converge_cnt[15]_i_5__3_n_0 ;
  wire \converge_cnt[15]_i_6__3_n_0 ;
  wire \converge_cnt[19]_i_3__3_n_0 ;
  wire \converge_cnt[19]_i_4__3_n_0 ;
  wire \converge_cnt[19]_i_5__3_n_0 ;
  wire \converge_cnt[19]_i_6__3_n_0 ;
  wire \converge_cnt[21]_i_3__3_n_0 ;
  wire \converge_cnt[21]_i_4__3_n_0 ;
  wire \converge_cnt[3]_i_3__3_n_0 ;
  wire \converge_cnt[3]_i_4__3_n_0 ;
  wire \converge_cnt[3]_i_5__3_n_0 ;
  wire \converge_cnt[3]_i_6__3_n_0 ;
  wire \converge_cnt[7]_i_3__3_n_0 ;
  wire \converge_cnt[7]_i_4__3_n_0 ;
  wire \converge_cnt[7]_i_5__3_n_0 ;
  wire \converge_cnt[7]_i_6__3_n_0 ;
  wire \converge_cnt_reg[11]_i_2__3_n_0 ;
  wire \converge_cnt_reg[11]_i_2__3_n_1 ;
  wire \converge_cnt_reg[11]_i_2__3_n_2 ;
  wire \converge_cnt_reg[11]_i_2__3_n_3 ;
  wire \converge_cnt_reg[15]_i_2__3_n_0 ;
  wire \converge_cnt_reg[15]_i_2__3_n_1 ;
  wire \converge_cnt_reg[15]_i_2__3_n_2 ;
  wire \converge_cnt_reg[15]_i_2__3_n_3 ;
  wire \converge_cnt_reg[19]_i_2__3_n_0 ;
  wire \converge_cnt_reg[19]_i_2__3_n_1 ;
  wire \converge_cnt_reg[19]_i_2__3_n_2 ;
  wire \converge_cnt_reg[19]_i_2__3_n_3 ;
  wire \converge_cnt_reg[21]_i_2__3_n_3 ;
  wire \converge_cnt_reg[3]_i_2__3_n_0 ;
  wire \converge_cnt_reg[3]_i_2__3_n_1 ;
  wire \converge_cnt_reg[3]_i_2__3_n_2 ;
  wire \converge_cnt_reg[3]_i_2__3_n_3 ;
  wire \converge_cnt_reg[7]_i_2__3_n_0 ;
  wire \converge_cnt_reg[7]_i_2__3_n_1 ;
  wire \converge_cnt_reg[7]_i_2__3_n_2 ;
  wire \converge_cnt_reg[7]_i_2__3_n_3 ;
  wire \converge_cnt_reg_n_0_[0] ;
  wire \converge_cnt_reg_n_0_[10] ;
  wire \converge_cnt_reg_n_0_[11] ;
  wire \converge_cnt_reg_n_0_[12] ;
  wire \converge_cnt_reg_n_0_[13] ;
  wire \converge_cnt_reg_n_0_[14] ;
  wire \converge_cnt_reg_n_0_[15] ;
  wire \converge_cnt_reg_n_0_[16] ;
  wire \converge_cnt_reg_n_0_[17] ;
  wire \converge_cnt_reg_n_0_[18] ;
  wire \converge_cnt_reg_n_0_[19] ;
  wire \converge_cnt_reg_n_0_[1] ;
  wire \converge_cnt_reg_n_0_[20] ;
  wire \converge_cnt_reg_n_0_[21] ;
  wire \converge_cnt_reg_n_0_[2] ;
  wire \converge_cnt_reg_n_0_[3] ;
  wire \converge_cnt_reg_n_0_[4] ;
  wire \converge_cnt_reg_n_0_[5] ;
  wire \converge_cnt_reg_n_0_[6] ;
  wire \converge_cnt_reg_n_0_[7] ;
  wire \converge_cnt_reg_n_0_[8] ;
  wire \converge_cnt_reg_n_0_[9] ;
  wire [5:0]fs_reg1;
  wire [5:0]fs_reg2;
  wire fsm1;
  wire [5:0]lf_reg1;
  wire [5:0]lf_reg2;
  wire new_txcoeff_done;
  wire new_txcoeff_req_reg1;
  wire new_txcoeff_req_reg2;
  wire [1:0]out;
  wire pclk_sel_reg;
  wire preset_done;
  wire [2:0]preset_reg1;
  wire [2:0]preset_reg2;
  wire preset_valid_reg1;
  wire preset_valid_reg2;
  wire rxeq_adapt_done_reg;
  wire rxeq_adapt_done_reg0;
  wire rxeq_adapt_done_reg_i_2__3_n_0;
  wire rxeq_adapt_done_reg_reg;
  wire rxeq_adapt_done_reg_reg_0;
  wire \rxeq_cnt_reg[1] ;
  wire \rxeq_cnt_reg[1]_0 ;
  wire \rxeq_control_reg2_reg[0] ;
  wire [5:0]\rxeq_fs_reg[5] ;
  wire [5:0]\rxeq_lf_reg[5] ;
  wire rxeq_new_txcoeff_req_reg;
  wire rxeq_new_txcoeff_req_reg_0;
  wire [2:0]\rxeq_preset_reg[2] ;
  wire rxeq_preset_valid_reg;
  wire [17:0]\rxeq_txcoeff_reg[17] ;
  wire rxeqscan_adapt_done;
  wire rxeqscan_new_txcoeff_done;
  wire rxeqscan_preset_done;
  wire [17:0]txcoeff_reg1;
  wire [17:0]txcoeff_reg2;
  wire [3:0]txpreset_reg1;
  wire [3:0]txpreset_reg2;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__3_CO_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__3_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h000000073333FF07)) 
    \FSM_onehot_fsm[1]_i_1__4 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(preset_valid_reg2),
        .O(\FSM_onehot_fsm[1]_i_1__4_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \FSM_onehot_fsm[2]_i_1__4 
       (.I0(preset_valid_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[2]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA8A8AA)) 
    \FSM_onehot_fsm[3]_i_1__4 
       (.I0(\FSM_onehot_fsm[3]_i_2__4_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_3__4_n_0 ),
        .I2(\FSM_onehot_fsm[3]_i_4__4_n_0 ),
        .I3(\converge_cnt_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm[3]_i_5__3_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h2020202020202F20)) 
    \FSM_onehot_fsm[3]_i_2__4 
       (.I0(new_txcoeff_req_reg2),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(fsm1),
        .I5(\FSM_onehot_fsm_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm[3]_i_2__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFF6FFFFFFFF6FFF)) 
    \FSM_onehot_fsm[3]_i_3__4 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .I1(\converge_cnt_reg_n_0_[2] ),
        .I2(\converge_cnt_reg_n_0_[10] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[20] ),
        .O(\FSM_onehot_fsm[3]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'hFF7E7EFFFF7EFF7E)) 
    \FSM_onehot_fsm[3]_i_4__4 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[8] ),
        .I3(\converge_cnt_reg_n_0_[21] ),
        .I4(out[0]),
        .I5(out[1]),
        .O(\FSM_onehot_fsm[3]_i_4__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF9)) 
    \FSM_onehot_fsm[3]_i_5__3 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .I1(\converge_cnt_reg_n_0_[21] ),
        .I2(\converge_cnt_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[7] ),
        .I4(\FSM_onehot_fsm[3]_i_7__3_n_0 ),
        .I5(\FSM_onehot_fsm[3]_i_8__3_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_5__3_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_onehot_fsm[3]_i_6__3 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .O(fsm1));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[3]_i_7__3 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[16] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[3]_i_7__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFDFF)) 
    \FSM_onehot_fsm[3]_i_8__3 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .I1(\converge_cnt_reg_n_0_[4] ),
        .I2(\converge_cnt_reg_n_0_[12] ),
        .I3(\converge_cnt_reg_n_0_[9] ),
        .I4(\converge_cnt_reg_n_0_[5] ),
        .I5(\converge_cnt_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm[3]_i_8__3_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \FSM_onehot_fsm[4]_i_1__4 
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm[4]_i_2__3_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \FSM_onehot_fsm[4]_i_2__3 
       (.I0(\FSM_onehot_fsm[4]_i_3__4_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_4__3_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_5__3_n_0 ),
        .I3(\FSM_onehot_fsm[4]_i_6__3_n_0 ),
        .I4(\FSM_onehot_fsm[4]_i_7__3_n_0 ),
        .I5(\FSM_onehot_fsm[4]_i_8__3_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'h02020202FF000000)) 
    \FSM_onehot_fsm[4]_i_3__4 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_3__4_n_0 ));
  LUT6 #(
    .INIT(64'h00004B00004B0000)) 
    \FSM_onehot_fsm[4]_i_4__3 
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\converge_cnt_reg_n_0_[21] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[10] ),
        .O(\FSM_onehot_fsm[4]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'h0000810000810000)) 
    \FSM_onehot_fsm[4]_i_5__3 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[8] ),
        .I2(\converge_cnt_reg_n_0_[3] ),
        .I3(\converge_cnt_reg_n_0_[20] ),
        .I4(\converge_cnt_reg_n_0_[21] ),
        .I5(\converge_cnt_reg_n_0_[14] ),
        .O(\FSM_onehot_fsm[4]_i_5__3_n_0 ));
  LUT5 #(
    .INIT(32'h00000024)) 
    \FSM_onehot_fsm[4]_i_6__3 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[0] ),
        .I3(\converge_cnt_reg_n_0_[5] ),
        .I4(\converge_cnt_reg_n_0_[4] ),
        .O(\FSM_onehot_fsm[4]_i_6__3_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \FSM_onehot_fsm[4]_i_7__3 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\converge_cnt_reg_n_0_[11] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[9] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[4]_i_7__3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \FSM_onehot_fsm[4]_i_8__3 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .I1(\converge_cnt_reg_n_0_[6] ),
        .I2(\converge_cnt_reg_n_0_[16] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[19] ),
        .I5(\converge_cnt_reg_n_0_[7] ),
        .O(\FSM_onehot_fsm[4]_i_8__3_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__4_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__4_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__4_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__4_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hEFEEEEEE)) 
    \FSM_sequential_fsm_rx[0]_i_1__3 
       (.I0(\FSM_sequential_fsm_rx_reg[0] ),
        .I1(\rxeq_cnt_reg[1] ),
        .I2(rxeqscan_new_txcoeff_done),
        .I3(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h0CAF0CA0FF000F00)) 
    \FSM_sequential_fsm_rx[1]_i_1__3 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(\rxeq_cnt_reg[1]_0 ),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\rxeq_control_reg2_reg[0] ),
        .I5(\FSM_sequential_fsm_rx_reg[2] [0]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h3F083FC8330833C8)) 
    \FSM_sequential_fsm_rx[2]_i_1__3 
       (.I0(rxeqscan_preset_done),
        .I1(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I4(\rxeq_cnt_reg[1]_0 ),
        .I5(\rxeq_control_reg2_reg[0] ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'h00FF2A00)) 
    adapt_done_cnt_i_1__3
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(out[0]),
        .I2(out[1]),
        .I3(adapt_done_cnt),
        .I4(adapt_done_cnt_reg_n_0),
        .O(adapt_done_cnt_i_1__3_n_0));
  LUT6 #(
    .INIT(64'hFFFF444744444447)) 
    adapt_done_cnt_i_2__3
       (.I0(new_txcoeff_req_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I5(fsm1),
        .O(adapt_done_cnt));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_cnt_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done_cnt_i_1__3_n_0),
        .Q(adapt_done_cnt_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hA8880000)) 
    adapt_done_i_1__3
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[1]),
        .I3(out[0]),
        .I4(new_txcoeff_req_reg2),
        .O(adapt_done));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done),
        .Q(rxeqscan_adapt_done),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[0]_i_1__11 
       (.I0(converge_cnt0[0]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[0]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[10]_i_1__3 
       (.I0(converge_cnt0[10]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[10]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[11]_i_1__3 
       (.I0(converge_cnt0[11]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[11]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_3__3 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .O(\converge_cnt[11]_i_3__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_4__3 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .O(\converge_cnt[11]_i_4__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_5__3 
       (.I0(\converge_cnt_reg_n_0_[9] ),
        .O(\converge_cnt[11]_i_5__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_6__3 
       (.I0(\converge_cnt_reg_n_0_[8] ),
        .O(\converge_cnt[11]_i_6__3_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[12]_i_1__3 
       (.I0(converge_cnt0[12]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[12]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[13]_i_1__3 
       (.I0(converge_cnt0[13]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[13]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[14]_i_1__3 
       (.I0(converge_cnt0[14]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[14]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[15]_i_1__3 
       (.I0(converge_cnt0[15]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[15]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_3__3 
       (.I0(\converge_cnt_reg_n_0_[15] ),
        .O(\converge_cnt[15]_i_3__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_4__3 
       (.I0(\converge_cnt_reg_n_0_[14] ),
        .O(\converge_cnt[15]_i_4__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_5__3 
       (.I0(\converge_cnt_reg_n_0_[13] ),
        .O(\converge_cnt[15]_i_5__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_6__3 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .O(\converge_cnt[15]_i_6__3_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[16]_i_1__3 
       (.I0(converge_cnt0[16]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[16]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[17]_i_1__3 
       (.I0(converge_cnt0[17]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[17]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[18]_i_1__3 
       (.I0(converge_cnt0[18]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[18]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[19]_i_1__3 
       (.I0(converge_cnt0[19]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[19]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_3__3 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .O(\converge_cnt[19]_i_3__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_4__3 
       (.I0(\converge_cnt_reg_n_0_[18] ),
        .O(\converge_cnt[19]_i_4__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_5__3 
       (.I0(\converge_cnt_reg_n_0_[17] ),
        .O(\converge_cnt[19]_i_5__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_6__3 
       (.I0(\converge_cnt_reg_n_0_[16] ),
        .O(\converge_cnt[19]_i_6__3_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[1]_i_1__3 
       (.I0(converge_cnt0[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[1]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[20]_i_1__3 
       (.I0(converge_cnt0[20]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[20]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[21]_i_1__3 
       (.I0(converge_cnt0[21]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[21]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_3__3 
       (.I0(\converge_cnt_reg_n_0_[21] ),
        .O(\converge_cnt[21]_i_3__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_4__3 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .O(\converge_cnt[21]_i_4__3_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[2]_i_1__3 
       (.I0(converge_cnt0[2]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[2]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[3]_i_1__3 
       (.I0(converge_cnt0[3]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[3]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_3__3 
       (.I0(\converge_cnt_reg_n_0_[3] ),
        .O(\converge_cnt[3]_i_3__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_4__3 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .O(\converge_cnt[3]_i_4__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_5__3 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .O(\converge_cnt[3]_i_5__3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[3]_i_6__3 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .O(\converge_cnt[3]_i_6__3_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[4]_i_1__3 
       (.I0(converge_cnt0[4]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[4]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[5]_i_1__3 
       (.I0(converge_cnt0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[5]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[6]_i_1__3 
       (.I0(converge_cnt0[6]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[6]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[7]_i_1__3 
       (.I0(converge_cnt0[7]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[7]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_3__3 
       (.I0(\converge_cnt_reg_n_0_[7] ),
        .O(\converge_cnt[7]_i_3__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_4__3 
       (.I0(\converge_cnt_reg_n_0_[6] ),
        .O(\converge_cnt[7]_i_4__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_5__3 
       (.I0(\converge_cnt_reg_n_0_[5] ),
        .O(\converge_cnt[7]_i_5__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_6__3 
       (.I0(\converge_cnt_reg_n_0_[4] ),
        .O(\converge_cnt[7]_i_6__3_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[8]_i_1__3 
       (.I0(converge_cnt0[8]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[8]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[9]_i_1__3 
       (.I0(converge_cnt0[9]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[9]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[0]),
        .Q(\converge_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[10]),
        .Q(\converge_cnt_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[11]),
        .Q(\converge_cnt_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[11]_i_2__3 
       (.CI(\converge_cnt_reg[7]_i_2__3_n_0 ),
        .CO({\converge_cnt_reg[11]_i_2__3_n_0 ,\converge_cnt_reg[11]_i_2__3_n_1 ,\converge_cnt_reg[11]_i_2__3_n_2 ,\converge_cnt_reg[11]_i_2__3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[11:8]),
        .S({\converge_cnt[11]_i_3__3_n_0 ,\converge_cnt[11]_i_4__3_n_0 ,\converge_cnt[11]_i_5__3_n_0 ,\converge_cnt[11]_i_6__3_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[12]),
        .Q(\converge_cnt_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[13]),
        .Q(\converge_cnt_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[14]),
        .Q(\converge_cnt_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[15]),
        .Q(\converge_cnt_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[15]_i_2__3 
       (.CI(\converge_cnt_reg[11]_i_2__3_n_0 ),
        .CO({\converge_cnt_reg[15]_i_2__3_n_0 ,\converge_cnt_reg[15]_i_2__3_n_1 ,\converge_cnt_reg[15]_i_2__3_n_2 ,\converge_cnt_reg[15]_i_2__3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[15:12]),
        .S({\converge_cnt[15]_i_3__3_n_0 ,\converge_cnt[15]_i_4__3_n_0 ,\converge_cnt[15]_i_5__3_n_0 ,\converge_cnt[15]_i_6__3_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[16]),
        .Q(\converge_cnt_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[17]),
        .Q(\converge_cnt_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[18]),
        .Q(\converge_cnt_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[19]),
        .Q(\converge_cnt_reg_n_0_[19] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[19]_i_2__3 
       (.CI(\converge_cnt_reg[15]_i_2__3_n_0 ),
        .CO({\converge_cnt_reg[19]_i_2__3_n_0 ,\converge_cnt_reg[19]_i_2__3_n_1 ,\converge_cnt_reg[19]_i_2__3_n_2 ,\converge_cnt_reg[19]_i_2__3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[19:16]),
        .S({\converge_cnt[19]_i_3__3_n_0 ,\converge_cnt[19]_i_4__3_n_0 ,\converge_cnt[19]_i_5__3_n_0 ,\converge_cnt[19]_i_6__3_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[1]),
        .Q(\converge_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[20]),
        .Q(\converge_cnt_reg_n_0_[20] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[21]),
        .Q(\converge_cnt_reg_n_0_[21] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[21]_i_2__3 
       (.CI(\converge_cnt_reg[19]_i_2__3_n_0 ),
        .CO({\NLW_converge_cnt_reg[21]_i_2__3_CO_UNCONNECTED [3:1],\converge_cnt_reg[21]_i_2__3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__3_O_UNCONNECTED [3:2],converge_cnt0[21:20]}),
        .S({1'b0,1'b0,\converge_cnt[21]_i_3__3_n_0 ,\converge_cnt[21]_i_4__3_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[2]),
        .Q(\converge_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[3]),
        .Q(\converge_cnt_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[3]_i_2__3 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[3]_i_2__3_n_0 ,\converge_cnt_reg[3]_i_2__3_n_1 ,\converge_cnt_reg[3]_i_2__3_n_2 ,\converge_cnt_reg[3]_i_2__3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\converge_cnt_reg_n_0_[0] }),
        .O(converge_cnt0[3:0]),
        .S({\converge_cnt[3]_i_3__3_n_0 ,\converge_cnt[3]_i_4__3_n_0 ,\converge_cnt[3]_i_5__3_n_0 ,\converge_cnt[3]_i_6__3_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[4]),
        .Q(\converge_cnt_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[5]),
        .Q(\converge_cnt_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[6]),
        .Q(\converge_cnt_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[7]),
        .Q(\converge_cnt_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[7]_i_2__3 
       (.CI(\converge_cnt_reg[3]_i_2__3_n_0 ),
        .CO({\converge_cnt_reg[7]_i_2__3_n_0 ,\converge_cnt_reg[7]_i_2__3_n_1 ,\converge_cnt_reg[7]_i_2__3_n_2 ,\converge_cnt_reg[7]_i_2__3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[7:4]),
        .S({\converge_cnt[7]_i_3__3_n_0 ,\converge_cnt[7]_i_4__3_n_0 ,\converge_cnt[7]_i_5__3_n_0 ,\converge_cnt[7]_i_6__3_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[8]),
        .Q(\converge_cnt_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[9]),
        .Q(\converge_cnt_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [0]),
        .Q(fs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [1]),
        .Q(fs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [2]),
        .Q(fs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [3]),
        .Q(fs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [4]),
        .Q(fs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [5]),
        .Q(fs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[0]),
        .Q(fs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[1]),
        .Q(fs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[2]),
        .Q(fs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[3]),
        .Q(fs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[4]),
        .Q(fs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[5]),
        .Q(fs_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [0]),
        .Q(lf_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [1]),
        .Q(lf_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [2]),
        .Q(lf_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [3]),
        .Q(lf_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [4]),
        .Q(lf_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [5]),
        .Q(lf_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[0]),
        .Q(lf_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[1]),
        .Q(lf_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[2]),
        .Q(lf_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[3]),
        .Q(lf_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[4]),
        .Q(lf_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[5]),
        .Q(lf_reg2[5]),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    new_txcoeff_done_i_1__3
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .O(new_txcoeff_done));
  FDRE #(
    .INIT(1'b0)) 
    new_txcoeff_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_done),
        .Q(rxeqscan_new_txcoeff_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_new_txcoeff_req_reg_0),
        .Q(new_txcoeff_req_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1),
        .Q(new_txcoeff_req_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hEA)) 
    preset_done_i_1__3
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(preset_done));
  FDRE #(
    .INIT(1'b0)) 
    preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_done),
        .Q(rxeqscan_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [0]),
        .Q(preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [1]),
        .Q(preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [2]),
        .Q(preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[0]),
        .Q(preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[1]),
        .Q(preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[2]),
        .Q(preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid_reg),
        .Q(preset_valid_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_valid_reg1),
        .Q(preset_valid_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0080F00000800000)) 
    rxeq_adapt_done_i_1__3
       (.I0(rxeq_adapt_done_reg0),
        .I1(rxeqscan_new_txcoeff_done),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I5(USER_RXEQ_ADAPT_DONE),
        .O(rxeq_adapt_done_reg));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rxeq_adapt_done_i_2__3
       (.I0(rxeqscan_adapt_done),
        .I1(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg0));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT5 #(
    .INIT(32'h44FF4000)) 
    rxeq_adapt_done_reg_i_1__3
       (.I0(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(rxeqscan_adapt_done),
        .I3(rxeq_adapt_done_reg_i_2__3_n_0),
        .I4(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg_reg));
  LUT6 #(
    .INIT(64'hF0F0002FF000002F)) 
    rxeq_adapt_done_reg_i_2__3
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I5(rxeqscan_new_txcoeff_done),
        .O(rxeq_adapt_done_reg_i_2__3_n_0));
  LUT4 #(
    .INIT(16'h0008)) 
    rxeq_new_txcoeff_req_i_1__3
       (.I0(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I3(rxeqscan_new_txcoeff_done),
        .O(rxeq_new_txcoeff_req_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [0]),
        .Q(txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [10]),
        .Q(txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [11]),
        .Q(txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [12]),
        .Q(txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [13]),
        .Q(txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [14]),
        .Q(txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [15]),
        .Q(txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [16]),
        .Q(txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [17]),
        .Q(txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [1]),
        .Q(txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [2]),
        .Q(txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [3]),
        .Q(txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [4]),
        .Q(txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [5]),
        .Q(txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [6]),
        .Q(txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [7]),
        .Q(txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [8]),
        .Q(txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [9]),
        .Q(txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[0]),
        .Q(txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[10]),
        .Q(txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[11]),
        .Q(txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[12]),
        .Q(txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[13]),
        .Q(txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[14]),
        .Q(txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[15]),
        .Q(txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[16]),
        .Q(txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[17]),
        .Q(txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[1]),
        .Q(txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[2]),
        .Q(txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[3]),
        .Q(txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[4]),
        .Q(txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[5]),
        .Q(txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[6]),
        .Q(txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[7]),
        .Q(txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[8]),
        .Q(txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[9]),
        .Q(txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[0]),
        .Q(txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[1]),
        .Q(txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[2]),
        .Q(txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[3]),
        .Q(txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[0]),
        .Q(txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[1]),
        .Q(txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[2]),
        .Q(txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[3]),
        .Q(txpreset_reg2[3]),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_rxeq_scan" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_78
   (D,
    rxeq_new_txcoeff_req_reg,
    rxeq_adapt_done_reg,
    rxeq_adapt_done_reg_reg,
    RST_CPLLRESET,
    rxeq_new_txcoeff_req_reg_0,
    pclk_sel_reg,
    rxeq_preset_valid_reg,
    out,
    \FSM_sequential_fsm_rx_reg[0] ,
    \rxeq_cnt_reg[1] ,
    \FSM_sequential_fsm_rx_reg[2] ,
    \rxeq_cnt_reg[1]_0 ,
    \rxeq_control_reg2_reg[0] ,
    rxeq_adapt_done_reg_reg_0,
    USER_RXEQ_ADAPT_DONE,
    \rxeq_preset_reg[2] ,
    Q,
    \rxeq_txcoeff_reg[17] ,
    \rxeq_fs_reg[5] ,
    \rxeq_lf_reg[5] );
  output [2:0]D;
  output rxeq_new_txcoeff_req_reg;
  output rxeq_adapt_done_reg;
  output rxeq_adapt_done_reg_reg;
  input RST_CPLLRESET;
  input rxeq_new_txcoeff_req_reg_0;
  input pclk_sel_reg;
  input rxeq_preset_valid_reg;
  input [1:0]out;
  input \FSM_sequential_fsm_rx_reg[0] ;
  input \rxeq_cnt_reg[1] ;
  input [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  input \rxeq_cnt_reg[1]_0 ;
  input \rxeq_control_reg2_reg[0] ;
  input rxeq_adapt_done_reg_reg_0;
  input USER_RXEQ_ADAPT_DONE;
  input [2:0]\rxeq_preset_reg[2] ;
  input [3:0]Q;
  input [17:0]\rxeq_txcoeff_reg[17] ;
  input [5:0]\rxeq_fs_reg[5] ;
  input [5:0]\rxeq_lf_reg[5] ;

  wire [2:0]D;
  wire \FSM_onehot_fsm[1]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2__3_n_0 ;
  wire \FSM_onehot_fsm[3]_i_3__3_n_0 ;
  wire \FSM_onehot_fsm[3]_i_4__3_n_0 ;
  wire \FSM_onehot_fsm[3]_i_5__2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_7__2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_8__2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__3_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2__2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3__3_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4__2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_5__2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_6__2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_7__2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_8__2_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[4] ;
  wire \FSM_sequential_fsm_rx_reg[0] ;
  wire [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  wire [3:0]Q;
  wire RST_CPLLRESET;
  wire USER_RXEQ_ADAPT_DONE;
  wire adapt_done;
  wire adapt_done_cnt;
  wire adapt_done_cnt_i_1__2_n_0;
  wire adapt_done_cnt_reg_n_0;
  wire [21:0]converge_cnt;
  wire [21:0]converge_cnt0;
  wire \converge_cnt[11]_i_3__2_n_0 ;
  wire \converge_cnt[11]_i_4__2_n_0 ;
  wire \converge_cnt[11]_i_5__2_n_0 ;
  wire \converge_cnt[11]_i_6__2_n_0 ;
  wire \converge_cnt[15]_i_3__2_n_0 ;
  wire \converge_cnt[15]_i_4__2_n_0 ;
  wire \converge_cnt[15]_i_5__2_n_0 ;
  wire \converge_cnt[15]_i_6__2_n_0 ;
  wire \converge_cnt[19]_i_3__2_n_0 ;
  wire \converge_cnt[19]_i_4__2_n_0 ;
  wire \converge_cnt[19]_i_5__2_n_0 ;
  wire \converge_cnt[19]_i_6__2_n_0 ;
  wire \converge_cnt[21]_i_3__2_n_0 ;
  wire \converge_cnt[21]_i_4__2_n_0 ;
  wire \converge_cnt[3]_i_3__2_n_0 ;
  wire \converge_cnt[3]_i_4__2_n_0 ;
  wire \converge_cnt[3]_i_5__2_n_0 ;
  wire \converge_cnt[3]_i_6__2_n_0 ;
  wire \converge_cnt[7]_i_3__2_n_0 ;
  wire \converge_cnt[7]_i_4__2_n_0 ;
  wire \converge_cnt[7]_i_5__2_n_0 ;
  wire \converge_cnt[7]_i_6__2_n_0 ;
  wire \converge_cnt_reg[11]_i_2__2_n_0 ;
  wire \converge_cnt_reg[11]_i_2__2_n_1 ;
  wire \converge_cnt_reg[11]_i_2__2_n_2 ;
  wire \converge_cnt_reg[11]_i_2__2_n_3 ;
  wire \converge_cnt_reg[15]_i_2__2_n_0 ;
  wire \converge_cnt_reg[15]_i_2__2_n_1 ;
  wire \converge_cnt_reg[15]_i_2__2_n_2 ;
  wire \converge_cnt_reg[15]_i_2__2_n_3 ;
  wire \converge_cnt_reg[19]_i_2__2_n_0 ;
  wire \converge_cnt_reg[19]_i_2__2_n_1 ;
  wire \converge_cnt_reg[19]_i_2__2_n_2 ;
  wire \converge_cnt_reg[19]_i_2__2_n_3 ;
  wire \converge_cnt_reg[21]_i_2__2_n_3 ;
  wire \converge_cnt_reg[3]_i_2__2_n_0 ;
  wire \converge_cnt_reg[3]_i_2__2_n_1 ;
  wire \converge_cnt_reg[3]_i_2__2_n_2 ;
  wire \converge_cnt_reg[3]_i_2__2_n_3 ;
  wire \converge_cnt_reg[7]_i_2__2_n_0 ;
  wire \converge_cnt_reg[7]_i_2__2_n_1 ;
  wire \converge_cnt_reg[7]_i_2__2_n_2 ;
  wire \converge_cnt_reg[7]_i_2__2_n_3 ;
  wire \converge_cnt_reg_n_0_[0] ;
  wire \converge_cnt_reg_n_0_[10] ;
  wire \converge_cnt_reg_n_0_[11] ;
  wire \converge_cnt_reg_n_0_[12] ;
  wire \converge_cnt_reg_n_0_[13] ;
  wire \converge_cnt_reg_n_0_[14] ;
  wire \converge_cnt_reg_n_0_[15] ;
  wire \converge_cnt_reg_n_0_[16] ;
  wire \converge_cnt_reg_n_0_[17] ;
  wire \converge_cnt_reg_n_0_[18] ;
  wire \converge_cnt_reg_n_0_[19] ;
  wire \converge_cnt_reg_n_0_[1] ;
  wire \converge_cnt_reg_n_0_[20] ;
  wire \converge_cnt_reg_n_0_[21] ;
  wire \converge_cnt_reg_n_0_[2] ;
  wire \converge_cnt_reg_n_0_[3] ;
  wire \converge_cnt_reg_n_0_[4] ;
  wire \converge_cnt_reg_n_0_[5] ;
  wire \converge_cnt_reg_n_0_[6] ;
  wire \converge_cnt_reg_n_0_[7] ;
  wire \converge_cnt_reg_n_0_[8] ;
  wire \converge_cnt_reg_n_0_[9] ;
  wire [5:0]fs_reg1;
  wire [5:0]fs_reg2;
  wire fsm1;
  wire [5:0]lf_reg1;
  wire [5:0]lf_reg2;
  wire new_txcoeff_done;
  wire new_txcoeff_req_reg1;
  wire new_txcoeff_req_reg2;
  wire [1:0]out;
  wire pclk_sel_reg;
  wire preset_done;
  wire [2:0]preset_reg1;
  wire [2:0]preset_reg2;
  wire preset_valid_reg1;
  wire preset_valid_reg2;
  wire rxeq_adapt_done_reg;
  wire rxeq_adapt_done_reg0;
  wire rxeq_adapt_done_reg_i_2__2_n_0;
  wire rxeq_adapt_done_reg_reg;
  wire rxeq_adapt_done_reg_reg_0;
  wire \rxeq_cnt_reg[1] ;
  wire \rxeq_cnt_reg[1]_0 ;
  wire \rxeq_control_reg2_reg[0] ;
  wire [5:0]\rxeq_fs_reg[5] ;
  wire [5:0]\rxeq_lf_reg[5] ;
  wire rxeq_new_txcoeff_req_reg;
  wire rxeq_new_txcoeff_req_reg_0;
  wire [2:0]\rxeq_preset_reg[2] ;
  wire rxeq_preset_valid_reg;
  wire [17:0]\rxeq_txcoeff_reg[17] ;
  wire rxeqscan_adapt_done;
  wire rxeqscan_new_txcoeff_done;
  wire rxeqscan_preset_done;
  wire [17:0]txcoeff_reg1;
  wire [17:0]txcoeff_reg2;
  wire [3:0]txpreset_reg1;
  wire [3:0]txpreset_reg2;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__2_CO_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__2_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h000000073333FF07)) 
    \FSM_onehot_fsm[1]_i_1__3 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(preset_valid_reg2),
        .O(\FSM_onehot_fsm[1]_i_1__3_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \FSM_onehot_fsm[2]_i_1__3 
       (.I0(preset_valid_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[2]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA8A8AA)) 
    \FSM_onehot_fsm[3]_i_1__3 
       (.I0(\FSM_onehot_fsm[3]_i_2__3_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_3__3_n_0 ),
        .I2(\FSM_onehot_fsm[3]_i_4__3_n_0 ),
        .I3(\converge_cnt_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm[3]_i_5__2_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h2020202020202F20)) 
    \FSM_onehot_fsm[3]_i_2__3 
       (.I0(new_txcoeff_req_reg2),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(fsm1),
        .I5(\FSM_onehot_fsm_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm[3]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF6FFFFFFFF6FFF)) 
    \FSM_onehot_fsm[3]_i_3__3 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .I1(\converge_cnt_reg_n_0_[2] ),
        .I2(\converge_cnt_reg_n_0_[10] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[20] ),
        .O(\FSM_onehot_fsm[3]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'hFF7E7EFFFF7EFF7E)) 
    \FSM_onehot_fsm[3]_i_4__3 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[8] ),
        .I3(\converge_cnt_reg_n_0_[21] ),
        .I4(out[0]),
        .I5(out[1]),
        .O(\FSM_onehot_fsm[3]_i_4__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF9)) 
    \FSM_onehot_fsm[3]_i_5__2 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .I1(\converge_cnt_reg_n_0_[21] ),
        .I2(\converge_cnt_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[7] ),
        .I4(\FSM_onehot_fsm[3]_i_7__2_n_0 ),
        .I5(\FSM_onehot_fsm[3]_i_8__2_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_5__2_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_onehot_fsm[3]_i_6__2 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .O(fsm1));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[3]_i_7__2 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[16] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[3]_i_7__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFDFF)) 
    \FSM_onehot_fsm[3]_i_8__2 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .I1(\converge_cnt_reg_n_0_[4] ),
        .I2(\converge_cnt_reg_n_0_[12] ),
        .I3(\converge_cnt_reg_n_0_[9] ),
        .I4(\converge_cnt_reg_n_0_[5] ),
        .I5(\converge_cnt_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm[3]_i_8__2_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \FSM_onehot_fsm[4]_i_1__3 
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm[4]_i_2__2_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \FSM_onehot_fsm[4]_i_2__2 
       (.I0(\FSM_onehot_fsm[4]_i_3__3_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_4__2_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_5__2_n_0 ),
        .I3(\FSM_onehot_fsm[4]_i_6__2_n_0 ),
        .I4(\FSM_onehot_fsm[4]_i_7__2_n_0 ),
        .I5(\FSM_onehot_fsm[4]_i_8__2_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h02020202FF000000)) 
    \FSM_onehot_fsm[4]_i_3__3 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_3__3_n_0 ));
  LUT6 #(
    .INIT(64'h00004B00004B0000)) 
    \FSM_onehot_fsm[4]_i_4__2 
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\converge_cnt_reg_n_0_[21] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[10] ),
        .O(\FSM_onehot_fsm[4]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000810000810000)) 
    \FSM_onehot_fsm[4]_i_5__2 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[8] ),
        .I2(\converge_cnt_reg_n_0_[3] ),
        .I3(\converge_cnt_reg_n_0_[20] ),
        .I4(\converge_cnt_reg_n_0_[21] ),
        .I5(\converge_cnt_reg_n_0_[14] ),
        .O(\FSM_onehot_fsm[4]_i_5__2_n_0 ));
  LUT5 #(
    .INIT(32'h00000024)) 
    \FSM_onehot_fsm[4]_i_6__2 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[0] ),
        .I3(\converge_cnt_reg_n_0_[5] ),
        .I4(\converge_cnt_reg_n_0_[4] ),
        .O(\FSM_onehot_fsm[4]_i_6__2_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \FSM_onehot_fsm[4]_i_7__2 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\converge_cnt_reg_n_0_[11] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[9] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[4]_i_7__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \FSM_onehot_fsm[4]_i_8__2 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .I1(\converge_cnt_reg_n_0_[6] ),
        .I2(\converge_cnt_reg_n_0_[16] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[19] ),
        .I5(\converge_cnt_reg_n_0_[7] ),
        .O(\FSM_onehot_fsm[4]_i_8__2_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__3_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hEFEEEEEE)) 
    \FSM_sequential_fsm_rx[0]_i_1__2 
       (.I0(\FSM_sequential_fsm_rx_reg[0] ),
        .I1(\rxeq_cnt_reg[1] ),
        .I2(rxeqscan_new_txcoeff_done),
        .I3(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h0CAF0CA0FF000F00)) 
    \FSM_sequential_fsm_rx[1]_i_1__2 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(\rxeq_cnt_reg[1]_0 ),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\rxeq_control_reg2_reg[0] ),
        .I5(\FSM_sequential_fsm_rx_reg[2] [0]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h3F083FC8330833C8)) 
    \FSM_sequential_fsm_rx[2]_i_1__2 
       (.I0(rxeqscan_preset_done),
        .I1(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I4(\rxeq_cnt_reg[1]_0 ),
        .I5(\rxeq_control_reg2_reg[0] ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'h00FF2A00)) 
    adapt_done_cnt_i_1__2
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(out[0]),
        .I2(out[1]),
        .I3(adapt_done_cnt),
        .I4(adapt_done_cnt_reg_n_0),
        .O(adapt_done_cnt_i_1__2_n_0));
  LUT6 #(
    .INIT(64'hFFFF444744444447)) 
    adapt_done_cnt_i_2__2
       (.I0(new_txcoeff_req_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I5(fsm1),
        .O(adapt_done_cnt));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_cnt_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done_cnt_i_1__2_n_0),
        .Q(adapt_done_cnt_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hA8880000)) 
    adapt_done_i_1__2
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[1]),
        .I3(out[0]),
        .I4(new_txcoeff_req_reg2),
        .O(adapt_done));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done),
        .Q(rxeqscan_adapt_done),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[0]_i_1__10 
       (.I0(converge_cnt0[0]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[0]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[10]_i_1__2 
       (.I0(converge_cnt0[10]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[10]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[11]_i_1__2 
       (.I0(converge_cnt0[11]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[11]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_3__2 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .O(\converge_cnt[11]_i_3__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_4__2 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .O(\converge_cnt[11]_i_4__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_5__2 
       (.I0(\converge_cnt_reg_n_0_[9] ),
        .O(\converge_cnt[11]_i_5__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_6__2 
       (.I0(\converge_cnt_reg_n_0_[8] ),
        .O(\converge_cnt[11]_i_6__2_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[12]_i_1__2 
       (.I0(converge_cnt0[12]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[12]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[13]_i_1__2 
       (.I0(converge_cnt0[13]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[13]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[14]_i_1__2 
       (.I0(converge_cnt0[14]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[14]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[15]_i_1__2 
       (.I0(converge_cnt0[15]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[15]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_3__2 
       (.I0(\converge_cnt_reg_n_0_[15] ),
        .O(\converge_cnt[15]_i_3__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_4__2 
       (.I0(\converge_cnt_reg_n_0_[14] ),
        .O(\converge_cnt[15]_i_4__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_5__2 
       (.I0(\converge_cnt_reg_n_0_[13] ),
        .O(\converge_cnt[15]_i_5__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_6__2 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .O(\converge_cnt[15]_i_6__2_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[16]_i_1__2 
       (.I0(converge_cnt0[16]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[16]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[17]_i_1__2 
       (.I0(converge_cnt0[17]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[17]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[18]_i_1__2 
       (.I0(converge_cnt0[18]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[18]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[19]_i_1__2 
       (.I0(converge_cnt0[19]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[19]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_3__2 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .O(\converge_cnt[19]_i_3__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_4__2 
       (.I0(\converge_cnt_reg_n_0_[18] ),
        .O(\converge_cnt[19]_i_4__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_5__2 
       (.I0(\converge_cnt_reg_n_0_[17] ),
        .O(\converge_cnt[19]_i_5__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_6__2 
       (.I0(\converge_cnt_reg_n_0_[16] ),
        .O(\converge_cnt[19]_i_6__2_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[1]_i_1__2 
       (.I0(converge_cnt0[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[1]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[20]_i_1__2 
       (.I0(converge_cnt0[20]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[20]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[21]_i_1__2 
       (.I0(converge_cnt0[21]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[21]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_3__2 
       (.I0(\converge_cnt_reg_n_0_[21] ),
        .O(\converge_cnt[21]_i_3__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_4__2 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .O(\converge_cnt[21]_i_4__2_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[2]_i_1__2 
       (.I0(converge_cnt0[2]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[2]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[3]_i_1__2 
       (.I0(converge_cnt0[3]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[3]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_3__2 
       (.I0(\converge_cnt_reg_n_0_[3] ),
        .O(\converge_cnt[3]_i_3__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_4__2 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .O(\converge_cnt[3]_i_4__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_5__2 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .O(\converge_cnt[3]_i_5__2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[3]_i_6__2 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .O(\converge_cnt[3]_i_6__2_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[4]_i_1__2 
       (.I0(converge_cnt0[4]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[4]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[5]_i_1__2 
       (.I0(converge_cnt0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[5]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[6]_i_1__2 
       (.I0(converge_cnt0[6]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[6]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[7]_i_1__2 
       (.I0(converge_cnt0[7]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[7]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_3__2 
       (.I0(\converge_cnt_reg_n_0_[7] ),
        .O(\converge_cnt[7]_i_3__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_4__2 
       (.I0(\converge_cnt_reg_n_0_[6] ),
        .O(\converge_cnt[7]_i_4__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_5__2 
       (.I0(\converge_cnt_reg_n_0_[5] ),
        .O(\converge_cnt[7]_i_5__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_6__2 
       (.I0(\converge_cnt_reg_n_0_[4] ),
        .O(\converge_cnt[7]_i_6__2_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[8]_i_1__2 
       (.I0(converge_cnt0[8]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[8]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[9]_i_1__2 
       (.I0(converge_cnt0[9]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[9]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[0]),
        .Q(\converge_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[10]),
        .Q(\converge_cnt_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[11]),
        .Q(\converge_cnt_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[11]_i_2__2 
       (.CI(\converge_cnt_reg[7]_i_2__2_n_0 ),
        .CO({\converge_cnt_reg[11]_i_2__2_n_0 ,\converge_cnt_reg[11]_i_2__2_n_1 ,\converge_cnt_reg[11]_i_2__2_n_2 ,\converge_cnt_reg[11]_i_2__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[11:8]),
        .S({\converge_cnt[11]_i_3__2_n_0 ,\converge_cnt[11]_i_4__2_n_0 ,\converge_cnt[11]_i_5__2_n_0 ,\converge_cnt[11]_i_6__2_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[12]),
        .Q(\converge_cnt_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[13]),
        .Q(\converge_cnt_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[14]),
        .Q(\converge_cnt_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[15]),
        .Q(\converge_cnt_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[15]_i_2__2 
       (.CI(\converge_cnt_reg[11]_i_2__2_n_0 ),
        .CO({\converge_cnt_reg[15]_i_2__2_n_0 ,\converge_cnt_reg[15]_i_2__2_n_1 ,\converge_cnt_reg[15]_i_2__2_n_2 ,\converge_cnt_reg[15]_i_2__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[15:12]),
        .S({\converge_cnt[15]_i_3__2_n_0 ,\converge_cnt[15]_i_4__2_n_0 ,\converge_cnt[15]_i_5__2_n_0 ,\converge_cnt[15]_i_6__2_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[16]),
        .Q(\converge_cnt_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[17]),
        .Q(\converge_cnt_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[18]),
        .Q(\converge_cnt_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[19]),
        .Q(\converge_cnt_reg_n_0_[19] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[19]_i_2__2 
       (.CI(\converge_cnt_reg[15]_i_2__2_n_0 ),
        .CO({\converge_cnt_reg[19]_i_2__2_n_0 ,\converge_cnt_reg[19]_i_2__2_n_1 ,\converge_cnt_reg[19]_i_2__2_n_2 ,\converge_cnt_reg[19]_i_2__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[19:16]),
        .S({\converge_cnt[19]_i_3__2_n_0 ,\converge_cnt[19]_i_4__2_n_0 ,\converge_cnt[19]_i_5__2_n_0 ,\converge_cnt[19]_i_6__2_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[1]),
        .Q(\converge_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[20]),
        .Q(\converge_cnt_reg_n_0_[20] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[21]),
        .Q(\converge_cnt_reg_n_0_[21] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[21]_i_2__2 
       (.CI(\converge_cnt_reg[19]_i_2__2_n_0 ),
        .CO({\NLW_converge_cnt_reg[21]_i_2__2_CO_UNCONNECTED [3:1],\converge_cnt_reg[21]_i_2__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__2_O_UNCONNECTED [3:2],converge_cnt0[21:20]}),
        .S({1'b0,1'b0,\converge_cnt[21]_i_3__2_n_0 ,\converge_cnt[21]_i_4__2_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[2]),
        .Q(\converge_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[3]),
        .Q(\converge_cnt_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[3]_i_2__2 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[3]_i_2__2_n_0 ,\converge_cnt_reg[3]_i_2__2_n_1 ,\converge_cnt_reg[3]_i_2__2_n_2 ,\converge_cnt_reg[3]_i_2__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\converge_cnt_reg_n_0_[0] }),
        .O(converge_cnt0[3:0]),
        .S({\converge_cnt[3]_i_3__2_n_0 ,\converge_cnt[3]_i_4__2_n_0 ,\converge_cnt[3]_i_5__2_n_0 ,\converge_cnt[3]_i_6__2_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[4]),
        .Q(\converge_cnt_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[5]),
        .Q(\converge_cnt_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[6]),
        .Q(\converge_cnt_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[7]),
        .Q(\converge_cnt_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[7]_i_2__2 
       (.CI(\converge_cnt_reg[3]_i_2__2_n_0 ),
        .CO({\converge_cnt_reg[7]_i_2__2_n_0 ,\converge_cnt_reg[7]_i_2__2_n_1 ,\converge_cnt_reg[7]_i_2__2_n_2 ,\converge_cnt_reg[7]_i_2__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[7:4]),
        .S({\converge_cnt[7]_i_3__2_n_0 ,\converge_cnt[7]_i_4__2_n_0 ,\converge_cnt[7]_i_5__2_n_0 ,\converge_cnt[7]_i_6__2_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[8]),
        .Q(\converge_cnt_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[9]),
        .Q(\converge_cnt_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [0]),
        .Q(fs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [1]),
        .Q(fs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [2]),
        .Q(fs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [3]),
        .Q(fs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [4]),
        .Q(fs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [5]),
        .Q(fs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[0]),
        .Q(fs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[1]),
        .Q(fs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[2]),
        .Q(fs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[3]),
        .Q(fs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[4]),
        .Q(fs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[5]),
        .Q(fs_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [0]),
        .Q(lf_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [1]),
        .Q(lf_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [2]),
        .Q(lf_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [3]),
        .Q(lf_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [4]),
        .Q(lf_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [5]),
        .Q(lf_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[0]),
        .Q(lf_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[1]),
        .Q(lf_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[2]),
        .Q(lf_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[3]),
        .Q(lf_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[4]),
        .Q(lf_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[5]),
        .Q(lf_reg2[5]),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    new_txcoeff_done_i_1__2
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .O(new_txcoeff_done));
  FDRE #(
    .INIT(1'b0)) 
    new_txcoeff_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_done),
        .Q(rxeqscan_new_txcoeff_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_new_txcoeff_req_reg_0),
        .Q(new_txcoeff_req_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1),
        .Q(new_txcoeff_req_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hEA)) 
    preset_done_i_1__2
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(preset_done));
  FDRE #(
    .INIT(1'b0)) 
    preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_done),
        .Q(rxeqscan_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [0]),
        .Q(preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [1]),
        .Q(preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [2]),
        .Q(preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[0]),
        .Q(preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[1]),
        .Q(preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[2]),
        .Q(preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid_reg),
        .Q(preset_valid_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_valid_reg1),
        .Q(preset_valid_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0080F00000800000)) 
    rxeq_adapt_done_i_1__2
       (.I0(rxeq_adapt_done_reg0),
        .I1(rxeqscan_new_txcoeff_done),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I5(USER_RXEQ_ADAPT_DONE),
        .O(rxeq_adapt_done_reg));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rxeq_adapt_done_i_2__2
       (.I0(rxeqscan_adapt_done),
        .I1(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg0));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT5 #(
    .INIT(32'h44FF4000)) 
    rxeq_adapt_done_reg_i_1__2
       (.I0(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(rxeqscan_adapt_done),
        .I3(rxeq_adapt_done_reg_i_2__2_n_0),
        .I4(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg_reg));
  LUT6 #(
    .INIT(64'hF0F0002FF000002F)) 
    rxeq_adapt_done_reg_i_2__2
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I5(rxeqscan_new_txcoeff_done),
        .O(rxeq_adapt_done_reg_i_2__2_n_0));
  LUT4 #(
    .INIT(16'h0008)) 
    rxeq_new_txcoeff_req_i_1__2
       (.I0(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I3(rxeqscan_new_txcoeff_done),
        .O(rxeq_new_txcoeff_req_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [0]),
        .Q(txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [10]),
        .Q(txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [11]),
        .Q(txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [12]),
        .Q(txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [13]),
        .Q(txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [14]),
        .Q(txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [15]),
        .Q(txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [16]),
        .Q(txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [17]),
        .Q(txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [1]),
        .Q(txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [2]),
        .Q(txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [3]),
        .Q(txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [4]),
        .Q(txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [5]),
        .Q(txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [6]),
        .Q(txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [7]),
        .Q(txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [8]),
        .Q(txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [9]),
        .Q(txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[0]),
        .Q(txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[10]),
        .Q(txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[11]),
        .Q(txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[12]),
        .Q(txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[13]),
        .Q(txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[14]),
        .Q(txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[15]),
        .Q(txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[16]),
        .Q(txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[17]),
        .Q(txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[1]),
        .Q(txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[2]),
        .Q(txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[3]),
        .Q(txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[4]),
        .Q(txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[5]),
        .Q(txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[6]),
        .Q(txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[7]),
        .Q(txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[8]),
        .Q(txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[9]),
        .Q(txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[0]),
        .Q(txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[1]),
        .Q(txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[2]),
        .Q(txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[3]),
        .Q(txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[0]),
        .Q(txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[1]),
        .Q(txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[2]),
        .Q(txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[3]),
        .Q(txpreset_reg2[3]),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_rxeq_scan" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_80
   (D,
    rxeq_new_txcoeff_req_reg,
    rxeq_adapt_done_reg,
    rxeq_adapt_done_reg_reg,
    RST_CPLLRESET,
    rxeq_new_txcoeff_req_reg_0,
    pclk_sel_reg,
    rxeq_preset_valid_reg,
    out,
    \FSM_sequential_fsm_rx_reg[0] ,
    \rxeq_cnt_reg[1] ,
    \FSM_sequential_fsm_rx_reg[2] ,
    \rxeq_cnt_reg[1]_0 ,
    \rxeq_control_reg2_reg[0] ,
    rxeq_adapt_done_reg_reg_0,
    USER_RXEQ_ADAPT_DONE,
    \rxeq_preset_reg[2] ,
    Q,
    \rxeq_txcoeff_reg[17] ,
    \rxeq_fs_reg[5] ,
    \rxeq_lf_reg[5] );
  output [2:0]D;
  output rxeq_new_txcoeff_req_reg;
  output rxeq_adapt_done_reg;
  output rxeq_adapt_done_reg_reg;
  input RST_CPLLRESET;
  input rxeq_new_txcoeff_req_reg_0;
  input pclk_sel_reg;
  input rxeq_preset_valid_reg;
  input [1:0]out;
  input \FSM_sequential_fsm_rx_reg[0] ;
  input \rxeq_cnt_reg[1] ;
  input [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  input \rxeq_cnt_reg[1]_0 ;
  input \rxeq_control_reg2_reg[0] ;
  input rxeq_adapt_done_reg_reg_0;
  input USER_RXEQ_ADAPT_DONE;
  input [2:0]\rxeq_preset_reg[2] ;
  input [3:0]Q;
  input [17:0]\rxeq_txcoeff_reg[17] ;
  input [5:0]\rxeq_fs_reg[5] ;
  input [5:0]\rxeq_lf_reg[5] ;

  wire [2:0]D;
  wire \FSM_onehot_fsm[1]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2__2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_3__2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_4__2_n_0 ;
  wire \FSM_onehot_fsm[3]_i_5__1_n_0 ;
  wire \FSM_onehot_fsm[3]_i_7__1_n_0 ;
  wire \FSM_onehot_fsm[3]_i_8__1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2__1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3__2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4__1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_5__1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_6__1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_7__1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_8__1_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[4] ;
  wire \FSM_sequential_fsm_rx_reg[0] ;
  wire [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  wire [3:0]Q;
  wire RST_CPLLRESET;
  wire USER_RXEQ_ADAPT_DONE;
  wire adapt_done;
  wire adapt_done_cnt;
  wire adapt_done_cnt_i_1__1_n_0;
  wire adapt_done_cnt_reg_n_0;
  wire [21:0]converge_cnt;
  wire [21:0]converge_cnt0;
  wire \converge_cnt[11]_i_3__1_n_0 ;
  wire \converge_cnt[11]_i_4__1_n_0 ;
  wire \converge_cnt[11]_i_5__1_n_0 ;
  wire \converge_cnt[11]_i_6__1_n_0 ;
  wire \converge_cnt[15]_i_3__1_n_0 ;
  wire \converge_cnt[15]_i_4__1_n_0 ;
  wire \converge_cnt[15]_i_5__1_n_0 ;
  wire \converge_cnt[15]_i_6__1_n_0 ;
  wire \converge_cnt[19]_i_3__1_n_0 ;
  wire \converge_cnt[19]_i_4__1_n_0 ;
  wire \converge_cnt[19]_i_5__1_n_0 ;
  wire \converge_cnt[19]_i_6__1_n_0 ;
  wire \converge_cnt[21]_i_3__1_n_0 ;
  wire \converge_cnt[21]_i_4__1_n_0 ;
  wire \converge_cnt[3]_i_3__1_n_0 ;
  wire \converge_cnt[3]_i_4__1_n_0 ;
  wire \converge_cnt[3]_i_5__1_n_0 ;
  wire \converge_cnt[3]_i_6__1_n_0 ;
  wire \converge_cnt[7]_i_3__1_n_0 ;
  wire \converge_cnt[7]_i_4__1_n_0 ;
  wire \converge_cnt[7]_i_5__1_n_0 ;
  wire \converge_cnt[7]_i_6__1_n_0 ;
  wire \converge_cnt_reg[11]_i_2__1_n_0 ;
  wire \converge_cnt_reg[11]_i_2__1_n_1 ;
  wire \converge_cnt_reg[11]_i_2__1_n_2 ;
  wire \converge_cnt_reg[11]_i_2__1_n_3 ;
  wire \converge_cnt_reg[15]_i_2__1_n_0 ;
  wire \converge_cnt_reg[15]_i_2__1_n_1 ;
  wire \converge_cnt_reg[15]_i_2__1_n_2 ;
  wire \converge_cnt_reg[15]_i_2__1_n_3 ;
  wire \converge_cnt_reg[19]_i_2__1_n_0 ;
  wire \converge_cnt_reg[19]_i_2__1_n_1 ;
  wire \converge_cnt_reg[19]_i_2__1_n_2 ;
  wire \converge_cnt_reg[19]_i_2__1_n_3 ;
  wire \converge_cnt_reg[21]_i_2__1_n_3 ;
  wire \converge_cnt_reg[3]_i_2__1_n_0 ;
  wire \converge_cnt_reg[3]_i_2__1_n_1 ;
  wire \converge_cnt_reg[3]_i_2__1_n_2 ;
  wire \converge_cnt_reg[3]_i_2__1_n_3 ;
  wire \converge_cnt_reg[7]_i_2__1_n_0 ;
  wire \converge_cnt_reg[7]_i_2__1_n_1 ;
  wire \converge_cnt_reg[7]_i_2__1_n_2 ;
  wire \converge_cnt_reg[7]_i_2__1_n_3 ;
  wire \converge_cnt_reg_n_0_[0] ;
  wire \converge_cnt_reg_n_0_[10] ;
  wire \converge_cnt_reg_n_0_[11] ;
  wire \converge_cnt_reg_n_0_[12] ;
  wire \converge_cnt_reg_n_0_[13] ;
  wire \converge_cnt_reg_n_0_[14] ;
  wire \converge_cnt_reg_n_0_[15] ;
  wire \converge_cnt_reg_n_0_[16] ;
  wire \converge_cnt_reg_n_0_[17] ;
  wire \converge_cnt_reg_n_0_[18] ;
  wire \converge_cnt_reg_n_0_[19] ;
  wire \converge_cnt_reg_n_0_[1] ;
  wire \converge_cnt_reg_n_0_[20] ;
  wire \converge_cnt_reg_n_0_[21] ;
  wire \converge_cnt_reg_n_0_[2] ;
  wire \converge_cnt_reg_n_0_[3] ;
  wire \converge_cnt_reg_n_0_[4] ;
  wire \converge_cnt_reg_n_0_[5] ;
  wire \converge_cnt_reg_n_0_[6] ;
  wire \converge_cnt_reg_n_0_[7] ;
  wire \converge_cnt_reg_n_0_[8] ;
  wire \converge_cnt_reg_n_0_[9] ;
  wire [5:0]fs_reg1;
  wire [5:0]fs_reg2;
  wire fsm1;
  wire [5:0]lf_reg1;
  wire [5:0]lf_reg2;
  wire new_txcoeff_done;
  wire new_txcoeff_req_reg1;
  wire new_txcoeff_req_reg2;
  wire [1:0]out;
  wire pclk_sel_reg;
  wire preset_done;
  wire [2:0]preset_reg1;
  wire [2:0]preset_reg2;
  wire preset_valid_reg1;
  wire preset_valid_reg2;
  wire rxeq_adapt_done_reg;
  wire rxeq_adapt_done_reg0;
  wire rxeq_adapt_done_reg_i_2__1_n_0;
  wire rxeq_adapt_done_reg_reg;
  wire rxeq_adapt_done_reg_reg_0;
  wire \rxeq_cnt_reg[1] ;
  wire \rxeq_cnt_reg[1]_0 ;
  wire \rxeq_control_reg2_reg[0] ;
  wire [5:0]\rxeq_fs_reg[5] ;
  wire [5:0]\rxeq_lf_reg[5] ;
  wire rxeq_new_txcoeff_req_reg;
  wire rxeq_new_txcoeff_req_reg_0;
  wire [2:0]\rxeq_preset_reg[2] ;
  wire rxeq_preset_valid_reg;
  wire [17:0]\rxeq_txcoeff_reg[17] ;
  wire rxeqscan_adapt_done;
  wire rxeqscan_new_txcoeff_done;
  wire rxeqscan_preset_done;
  wire [17:0]txcoeff_reg1;
  wire [17:0]txcoeff_reg2;
  wire [3:0]txpreset_reg1;
  wire [3:0]txpreset_reg2;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__1_CO_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__1_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h000000073333FF07)) 
    \FSM_onehot_fsm[1]_i_1__2 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(preset_valid_reg2),
        .O(\FSM_onehot_fsm[1]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \FSM_onehot_fsm[2]_i_1__2 
       (.I0(preset_valid_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA8A8AA)) 
    \FSM_onehot_fsm[3]_i_1__2 
       (.I0(\FSM_onehot_fsm[3]_i_2__2_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_3__2_n_0 ),
        .I2(\FSM_onehot_fsm[3]_i_4__2_n_0 ),
        .I3(\converge_cnt_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm[3]_i_5__1_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h2020202020202F20)) 
    \FSM_onehot_fsm[3]_i_2__2 
       (.I0(new_txcoeff_req_reg2),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(fsm1),
        .I5(\FSM_onehot_fsm_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm[3]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFF6FFFFFFFF6FFF)) 
    \FSM_onehot_fsm[3]_i_3__2 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .I1(\converge_cnt_reg_n_0_[2] ),
        .I2(\converge_cnt_reg_n_0_[10] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[20] ),
        .O(\FSM_onehot_fsm[3]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hFF7E7EFFFF7EFF7E)) 
    \FSM_onehot_fsm[3]_i_4__2 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[8] ),
        .I3(\converge_cnt_reg_n_0_[21] ),
        .I4(out[0]),
        .I5(out[1]),
        .O(\FSM_onehot_fsm[3]_i_4__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF9)) 
    \FSM_onehot_fsm[3]_i_5__1 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .I1(\converge_cnt_reg_n_0_[21] ),
        .I2(\converge_cnt_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[7] ),
        .I4(\FSM_onehot_fsm[3]_i_7__1_n_0 ),
        .I5(\FSM_onehot_fsm[3]_i_8__1_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_5__1_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_onehot_fsm[3]_i_6__1 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .O(fsm1));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[3]_i_7__1 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[16] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[3]_i_7__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFDFF)) 
    \FSM_onehot_fsm[3]_i_8__1 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .I1(\converge_cnt_reg_n_0_[4] ),
        .I2(\converge_cnt_reg_n_0_[12] ),
        .I3(\converge_cnt_reg_n_0_[9] ),
        .I4(\converge_cnt_reg_n_0_[5] ),
        .I5(\converge_cnt_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm[3]_i_8__1_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \FSM_onehot_fsm[4]_i_1__2 
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm[4]_i_2__1_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \FSM_onehot_fsm[4]_i_2__1 
       (.I0(\FSM_onehot_fsm[4]_i_3__2_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_4__1_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_5__1_n_0 ),
        .I3(\FSM_onehot_fsm[4]_i_6__1_n_0 ),
        .I4(\FSM_onehot_fsm[4]_i_7__1_n_0 ),
        .I5(\FSM_onehot_fsm[4]_i_8__1_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h02020202FF000000)) 
    \FSM_onehot_fsm[4]_i_3__2 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'h00004B00004B0000)) 
    \FSM_onehot_fsm[4]_i_4__1 
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\converge_cnt_reg_n_0_[21] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[10] ),
        .O(\FSM_onehot_fsm[4]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000810000810000)) 
    \FSM_onehot_fsm[4]_i_5__1 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[8] ),
        .I2(\converge_cnt_reg_n_0_[3] ),
        .I3(\converge_cnt_reg_n_0_[20] ),
        .I4(\converge_cnt_reg_n_0_[21] ),
        .I5(\converge_cnt_reg_n_0_[14] ),
        .O(\FSM_onehot_fsm[4]_i_5__1_n_0 ));
  LUT5 #(
    .INIT(32'h00000024)) 
    \FSM_onehot_fsm[4]_i_6__1 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[0] ),
        .I3(\converge_cnt_reg_n_0_[5] ),
        .I4(\converge_cnt_reg_n_0_[4] ),
        .O(\FSM_onehot_fsm[4]_i_6__1_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \FSM_onehot_fsm[4]_i_7__1 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\converge_cnt_reg_n_0_[11] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[9] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[4]_i_7__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \FSM_onehot_fsm[4]_i_8__1 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .I1(\converge_cnt_reg_n_0_[6] ),
        .I2(\converge_cnt_reg_n_0_[16] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[19] ),
        .I5(\converge_cnt_reg_n_0_[7] ),
        .O(\FSM_onehot_fsm[4]_i_8__1_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__2_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hEFEEEEEE)) 
    \FSM_sequential_fsm_rx[0]_i_1__1 
       (.I0(\FSM_sequential_fsm_rx_reg[0] ),
        .I1(\rxeq_cnt_reg[1] ),
        .I2(rxeqscan_new_txcoeff_done),
        .I3(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h0CAF0CA0FF000F00)) 
    \FSM_sequential_fsm_rx[1]_i_1__1 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(\rxeq_cnt_reg[1]_0 ),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\rxeq_control_reg2_reg[0] ),
        .I5(\FSM_sequential_fsm_rx_reg[2] [0]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h3F083FC8330833C8)) 
    \FSM_sequential_fsm_rx[2]_i_1__1 
       (.I0(rxeqscan_preset_done),
        .I1(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I4(\rxeq_cnt_reg[1]_0 ),
        .I5(\rxeq_control_reg2_reg[0] ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'h00FF2A00)) 
    adapt_done_cnt_i_1__1
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(out[0]),
        .I2(out[1]),
        .I3(adapt_done_cnt),
        .I4(adapt_done_cnt_reg_n_0),
        .O(adapt_done_cnt_i_1__1_n_0));
  LUT6 #(
    .INIT(64'hFFFF444744444447)) 
    adapt_done_cnt_i_2__1
       (.I0(new_txcoeff_req_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I5(fsm1),
        .O(adapt_done_cnt));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_cnt_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done_cnt_i_1__1_n_0),
        .Q(adapt_done_cnt_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hA8880000)) 
    adapt_done_i_1__1
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[1]),
        .I3(out[0]),
        .I4(new_txcoeff_req_reg2),
        .O(adapt_done));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done),
        .Q(rxeqscan_adapt_done),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[0]_i_1__9 
       (.I0(converge_cnt0[0]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[0]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[10]_i_1__1 
       (.I0(converge_cnt0[10]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[10]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[11]_i_1__1 
       (.I0(converge_cnt0[11]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[11]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_3__1 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .O(\converge_cnt[11]_i_3__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_4__1 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .O(\converge_cnt[11]_i_4__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_5__1 
       (.I0(\converge_cnt_reg_n_0_[9] ),
        .O(\converge_cnt[11]_i_5__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_6__1 
       (.I0(\converge_cnt_reg_n_0_[8] ),
        .O(\converge_cnt[11]_i_6__1_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[12]_i_1__1 
       (.I0(converge_cnt0[12]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[12]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[13]_i_1__1 
       (.I0(converge_cnt0[13]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[13]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[14]_i_1__1 
       (.I0(converge_cnt0[14]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[14]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[15]_i_1__1 
       (.I0(converge_cnt0[15]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[15]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_3__1 
       (.I0(\converge_cnt_reg_n_0_[15] ),
        .O(\converge_cnt[15]_i_3__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_4__1 
       (.I0(\converge_cnt_reg_n_0_[14] ),
        .O(\converge_cnt[15]_i_4__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_5__1 
       (.I0(\converge_cnt_reg_n_0_[13] ),
        .O(\converge_cnt[15]_i_5__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_6__1 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .O(\converge_cnt[15]_i_6__1_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[16]_i_1__1 
       (.I0(converge_cnt0[16]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[16]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[17]_i_1__1 
       (.I0(converge_cnt0[17]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[17]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[18]_i_1__1 
       (.I0(converge_cnt0[18]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[18]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[19]_i_1__1 
       (.I0(converge_cnt0[19]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[19]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_3__1 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .O(\converge_cnt[19]_i_3__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_4__1 
       (.I0(\converge_cnt_reg_n_0_[18] ),
        .O(\converge_cnt[19]_i_4__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_5__1 
       (.I0(\converge_cnt_reg_n_0_[17] ),
        .O(\converge_cnt[19]_i_5__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_6__1 
       (.I0(\converge_cnt_reg_n_0_[16] ),
        .O(\converge_cnt[19]_i_6__1_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[1]_i_1__1 
       (.I0(converge_cnt0[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[1]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[20]_i_1__1 
       (.I0(converge_cnt0[20]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[20]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[21]_i_1__1 
       (.I0(converge_cnt0[21]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[21]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_3__1 
       (.I0(\converge_cnt_reg_n_0_[21] ),
        .O(\converge_cnt[21]_i_3__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_4__1 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .O(\converge_cnt[21]_i_4__1_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[2]_i_1__1 
       (.I0(converge_cnt0[2]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[2]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[3]_i_1__1 
       (.I0(converge_cnt0[3]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[3]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_3__1 
       (.I0(\converge_cnt_reg_n_0_[3] ),
        .O(\converge_cnt[3]_i_3__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_4__1 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .O(\converge_cnt[3]_i_4__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_5__1 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .O(\converge_cnt[3]_i_5__1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[3]_i_6__1 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .O(\converge_cnt[3]_i_6__1_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[4]_i_1__1 
       (.I0(converge_cnt0[4]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[4]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[5]_i_1__1 
       (.I0(converge_cnt0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[5]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[6]_i_1__1 
       (.I0(converge_cnt0[6]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[6]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[7]_i_1__1 
       (.I0(converge_cnt0[7]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[7]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_3__1 
       (.I0(\converge_cnt_reg_n_0_[7] ),
        .O(\converge_cnt[7]_i_3__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_4__1 
       (.I0(\converge_cnt_reg_n_0_[6] ),
        .O(\converge_cnt[7]_i_4__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_5__1 
       (.I0(\converge_cnt_reg_n_0_[5] ),
        .O(\converge_cnt[7]_i_5__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_6__1 
       (.I0(\converge_cnt_reg_n_0_[4] ),
        .O(\converge_cnt[7]_i_6__1_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[8]_i_1__1 
       (.I0(converge_cnt0[8]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[8]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[9]_i_1__1 
       (.I0(converge_cnt0[9]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[9]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[0]),
        .Q(\converge_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[10]),
        .Q(\converge_cnt_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[11]),
        .Q(\converge_cnt_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[11]_i_2__1 
       (.CI(\converge_cnt_reg[7]_i_2__1_n_0 ),
        .CO({\converge_cnt_reg[11]_i_2__1_n_0 ,\converge_cnt_reg[11]_i_2__1_n_1 ,\converge_cnt_reg[11]_i_2__1_n_2 ,\converge_cnt_reg[11]_i_2__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[11:8]),
        .S({\converge_cnt[11]_i_3__1_n_0 ,\converge_cnt[11]_i_4__1_n_0 ,\converge_cnt[11]_i_5__1_n_0 ,\converge_cnt[11]_i_6__1_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[12]),
        .Q(\converge_cnt_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[13]),
        .Q(\converge_cnt_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[14]),
        .Q(\converge_cnt_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[15]),
        .Q(\converge_cnt_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[15]_i_2__1 
       (.CI(\converge_cnt_reg[11]_i_2__1_n_0 ),
        .CO({\converge_cnt_reg[15]_i_2__1_n_0 ,\converge_cnt_reg[15]_i_2__1_n_1 ,\converge_cnt_reg[15]_i_2__1_n_2 ,\converge_cnt_reg[15]_i_2__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[15:12]),
        .S({\converge_cnt[15]_i_3__1_n_0 ,\converge_cnt[15]_i_4__1_n_0 ,\converge_cnt[15]_i_5__1_n_0 ,\converge_cnt[15]_i_6__1_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[16]),
        .Q(\converge_cnt_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[17]),
        .Q(\converge_cnt_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[18]),
        .Q(\converge_cnt_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[19]),
        .Q(\converge_cnt_reg_n_0_[19] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[19]_i_2__1 
       (.CI(\converge_cnt_reg[15]_i_2__1_n_0 ),
        .CO({\converge_cnt_reg[19]_i_2__1_n_0 ,\converge_cnt_reg[19]_i_2__1_n_1 ,\converge_cnt_reg[19]_i_2__1_n_2 ,\converge_cnt_reg[19]_i_2__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[19:16]),
        .S({\converge_cnt[19]_i_3__1_n_0 ,\converge_cnt[19]_i_4__1_n_0 ,\converge_cnt[19]_i_5__1_n_0 ,\converge_cnt[19]_i_6__1_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[1]),
        .Q(\converge_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[20]),
        .Q(\converge_cnt_reg_n_0_[20] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[21]),
        .Q(\converge_cnt_reg_n_0_[21] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[21]_i_2__1 
       (.CI(\converge_cnt_reg[19]_i_2__1_n_0 ),
        .CO({\NLW_converge_cnt_reg[21]_i_2__1_CO_UNCONNECTED [3:1],\converge_cnt_reg[21]_i_2__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__1_O_UNCONNECTED [3:2],converge_cnt0[21:20]}),
        .S({1'b0,1'b0,\converge_cnt[21]_i_3__1_n_0 ,\converge_cnt[21]_i_4__1_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[2]),
        .Q(\converge_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[3]),
        .Q(\converge_cnt_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[3]_i_2__1 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[3]_i_2__1_n_0 ,\converge_cnt_reg[3]_i_2__1_n_1 ,\converge_cnt_reg[3]_i_2__1_n_2 ,\converge_cnt_reg[3]_i_2__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\converge_cnt_reg_n_0_[0] }),
        .O(converge_cnt0[3:0]),
        .S({\converge_cnt[3]_i_3__1_n_0 ,\converge_cnt[3]_i_4__1_n_0 ,\converge_cnt[3]_i_5__1_n_0 ,\converge_cnt[3]_i_6__1_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[4]),
        .Q(\converge_cnt_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[5]),
        .Q(\converge_cnt_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[6]),
        .Q(\converge_cnt_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[7]),
        .Q(\converge_cnt_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[7]_i_2__1 
       (.CI(\converge_cnt_reg[3]_i_2__1_n_0 ),
        .CO({\converge_cnt_reg[7]_i_2__1_n_0 ,\converge_cnt_reg[7]_i_2__1_n_1 ,\converge_cnt_reg[7]_i_2__1_n_2 ,\converge_cnt_reg[7]_i_2__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[7:4]),
        .S({\converge_cnt[7]_i_3__1_n_0 ,\converge_cnt[7]_i_4__1_n_0 ,\converge_cnt[7]_i_5__1_n_0 ,\converge_cnt[7]_i_6__1_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[8]),
        .Q(\converge_cnt_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[9]),
        .Q(\converge_cnt_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [0]),
        .Q(fs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [1]),
        .Q(fs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [2]),
        .Q(fs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [3]),
        .Q(fs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [4]),
        .Q(fs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [5]),
        .Q(fs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[0]),
        .Q(fs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[1]),
        .Q(fs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[2]),
        .Q(fs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[3]),
        .Q(fs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[4]),
        .Q(fs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[5]),
        .Q(fs_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [0]),
        .Q(lf_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [1]),
        .Q(lf_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [2]),
        .Q(lf_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [3]),
        .Q(lf_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [4]),
        .Q(lf_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [5]),
        .Q(lf_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[0]),
        .Q(lf_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[1]),
        .Q(lf_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[2]),
        .Q(lf_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[3]),
        .Q(lf_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[4]),
        .Q(lf_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[5]),
        .Q(lf_reg2[5]),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    new_txcoeff_done_i_1__1
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .O(new_txcoeff_done));
  FDRE #(
    .INIT(1'b0)) 
    new_txcoeff_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_done),
        .Q(rxeqscan_new_txcoeff_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_new_txcoeff_req_reg_0),
        .Q(new_txcoeff_req_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1),
        .Q(new_txcoeff_req_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hEA)) 
    preset_done_i_1__1
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(preset_done));
  FDRE #(
    .INIT(1'b0)) 
    preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_done),
        .Q(rxeqscan_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [0]),
        .Q(preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [1]),
        .Q(preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [2]),
        .Q(preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[0]),
        .Q(preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[1]),
        .Q(preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[2]),
        .Q(preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid_reg),
        .Q(preset_valid_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_valid_reg1),
        .Q(preset_valid_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0080F00000800000)) 
    rxeq_adapt_done_i_1__1
       (.I0(rxeq_adapt_done_reg0),
        .I1(rxeqscan_new_txcoeff_done),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I5(USER_RXEQ_ADAPT_DONE),
        .O(rxeq_adapt_done_reg));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rxeq_adapt_done_i_2__1
       (.I0(rxeqscan_adapt_done),
        .I1(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg0));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT5 #(
    .INIT(32'h44FF4000)) 
    rxeq_adapt_done_reg_i_1__1
       (.I0(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(rxeqscan_adapt_done),
        .I3(rxeq_adapt_done_reg_i_2__1_n_0),
        .I4(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg_reg));
  LUT6 #(
    .INIT(64'hF0F0002FF000002F)) 
    rxeq_adapt_done_reg_i_2__1
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I5(rxeqscan_new_txcoeff_done),
        .O(rxeq_adapt_done_reg_i_2__1_n_0));
  LUT4 #(
    .INIT(16'h0008)) 
    rxeq_new_txcoeff_req_i_1__1
       (.I0(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I3(rxeqscan_new_txcoeff_done),
        .O(rxeq_new_txcoeff_req_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [0]),
        .Q(txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [10]),
        .Q(txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [11]),
        .Q(txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [12]),
        .Q(txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [13]),
        .Q(txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [14]),
        .Q(txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [15]),
        .Q(txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [16]),
        .Q(txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [17]),
        .Q(txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [1]),
        .Q(txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [2]),
        .Q(txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [3]),
        .Q(txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [4]),
        .Q(txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [5]),
        .Q(txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [6]),
        .Q(txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [7]),
        .Q(txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [8]),
        .Q(txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [9]),
        .Q(txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[0]),
        .Q(txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[10]),
        .Q(txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[11]),
        .Q(txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[12]),
        .Q(txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[13]),
        .Q(txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[14]),
        .Q(txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[15]),
        .Q(txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[16]),
        .Q(txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[17]),
        .Q(txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[1]),
        .Q(txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[2]),
        .Q(txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[3]),
        .Q(txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[4]),
        .Q(txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[5]),
        .Q(txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[6]),
        .Q(txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[7]),
        .Q(txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[8]),
        .Q(txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[9]),
        .Q(txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[0]),
        .Q(txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[1]),
        .Q(txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[2]),
        .Q(txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[3]),
        .Q(txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[0]),
        .Q(txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[1]),
        .Q(txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[2]),
        .Q(txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[3]),
        .Q(txpreset_reg2[3]),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_rxeq_scan" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_82
   (D,
    rxeq_new_txcoeff_req_reg,
    rxeq_adapt_done_reg,
    rxeq_adapt_done_reg_reg,
    RST_CPLLRESET,
    rxeq_new_txcoeff_req_reg_0,
    pclk_sel_reg,
    rxeq_preset_valid_reg,
    out,
    \FSM_sequential_fsm_rx_reg[0] ,
    \rxeq_cnt_reg[1] ,
    \FSM_sequential_fsm_rx_reg[2] ,
    \rxeq_cnt_reg[1]_0 ,
    \rxeq_control_reg2_reg[0] ,
    rxeq_adapt_done_reg_reg_0,
    USER_RXEQ_ADAPT_DONE,
    \rxeq_preset_reg[2] ,
    Q,
    \rxeq_txcoeff_reg[17] ,
    \rxeq_fs_reg[5] ,
    \rxeq_lf_reg[5] );
  output [2:0]D;
  output rxeq_new_txcoeff_req_reg;
  output rxeq_adapt_done_reg;
  output rxeq_adapt_done_reg_reg;
  input RST_CPLLRESET;
  input rxeq_new_txcoeff_req_reg_0;
  input pclk_sel_reg;
  input rxeq_preset_valid_reg;
  input [1:0]out;
  input \FSM_sequential_fsm_rx_reg[0] ;
  input \rxeq_cnt_reg[1] ;
  input [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  input \rxeq_cnt_reg[1]_0 ;
  input \rxeq_control_reg2_reg[0] ;
  input rxeq_adapt_done_reg_reg_0;
  input USER_RXEQ_ADAPT_DONE;
  input [2:0]\rxeq_preset_reg[2] ;
  input [3:0]Q;
  input [17:0]\rxeq_txcoeff_reg[17] ;
  input [5:0]\rxeq_fs_reg[5] ;
  input [5:0]\rxeq_lf_reg[5] ;

  wire [2:0]D;
  wire \FSM_onehot_fsm[1]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2__1_n_0 ;
  wire \FSM_onehot_fsm[3]_i_3__1_n_0 ;
  wire \FSM_onehot_fsm[3]_i_4__1_n_0 ;
  wire \FSM_onehot_fsm[3]_i_5__0_n_0 ;
  wire \FSM_onehot_fsm[3]_i_7__0_n_0 ;
  wire \FSM_onehot_fsm[3]_i_8__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3__1_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_5__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_6__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_7__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_8__0_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[4] ;
  wire \FSM_sequential_fsm_rx_reg[0] ;
  wire [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  wire [3:0]Q;
  wire RST_CPLLRESET;
  wire USER_RXEQ_ADAPT_DONE;
  wire adapt_done;
  wire adapt_done_cnt;
  wire adapt_done_cnt_i_1__0_n_0;
  wire adapt_done_cnt_reg_n_0;
  wire [21:0]converge_cnt;
  wire [21:0]converge_cnt0;
  wire \converge_cnt[11]_i_3__0_n_0 ;
  wire \converge_cnt[11]_i_4__0_n_0 ;
  wire \converge_cnt[11]_i_5__0_n_0 ;
  wire \converge_cnt[11]_i_6__0_n_0 ;
  wire \converge_cnt[15]_i_3__0_n_0 ;
  wire \converge_cnt[15]_i_4__0_n_0 ;
  wire \converge_cnt[15]_i_5__0_n_0 ;
  wire \converge_cnt[15]_i_6__0_n_0 ;
  wire \converge_cnt[19]_i_3__0_n_0 ;
  wire \converge_cnt[19]_i_4__0_n_0 ;
  wire \converge_cnt[19]_i_5__0_n_0 ;
  wire \converge_cnt[19]_i_6__0_n_0 ;
  wire \converge_cnt[21]_i_3__0_n_0 ;
  wire \converge_cnt[21]_i_4__0_n_0 ;
  wire \converge_cnt[3]_i_3__0_n_0 ;
  wire \converge_cnt[3]_i_4__0_n_0 ;
  wire \converge_cnt[3]_i_5__0_n_0 ;
  wire \converge_cnt[3]_i_6__0_n_0 ;
  wire \converge_cnt[7]_i_3__0_n_0 ;
  wire \converge_cnt[7]_i_4__0_n_0 ;
  wire \converge_cnt[7]_i_5__0_n_0 ;
  wire \converge_cnt[7]_i_6__0_n_0 ;
  wire \converge_cnt_reg[11]_i_2__0_n_0 ;
  wire \converge_cnt_reg[11]_i_2__0_n_1 ;
  wire \converge_cnt_reg[11]_i_2__0_n_2 ;
  wire \converge_cnt_reg[11]_i_2__0_n_3 ;
  wire \converge_cnt_reg[15]_i_2__0_n_0 ;
  wire \converge_cnt_reg[15]_i_2__0_n_1 ;
  wire \converge_cnt_reg[15]_i_2__0_n_2 ;
  wire \converge_cnt_reg[15]_i_2__0_n_3 ;
  wire \converge_cnt_reg[19]_i_2__0_n_0 ;
  wire \converge_cnt_reg[19]_i_2__0_n_1 ;
  wire \converge_cnt_reg[19]_i_2__0_n_2 ;
  wire \converge_cnt_reg[19]_i_2__0_n_3 ;
  wire \converge_cnt_reg[21]_i_2__0_n_3 ;
  wire \converge_cnt_reg[3]_i_2__0_n_0 ;
  wire \converge_cnt_reg[3]_i_2__0_n_1 ;
  wire \converge_cnt_reg[3]_i_2__0_n_2 ;
  wire \converge_cnt_reg[3]_i_2__0_n_3 ;
  wire \converge_cnt_reg[7]_i_2__0_n_0 ;
  wire \converge_cnt_reg[7]_i_2__0_n_1 ;
  wire \converge_cnt_reg[7]_i_2__0_n_2 ;
  wire \converge_cnt_reg[7]_i_2__0_n_3 ;
  wire \converge_cnt_reg_n_0_[0] ;
  wire \converge_cnt_reg_n_0_[10] ;
  wire \converge_cnt_reg_n_0_[11] ;
  wire \converge_cnt_reg_n_0_[12] ;
  wire \converge_cnt_reg_n_0_[13] ;
  wire \converge_cnt_reg_n_0_[14] ;
  wire \converge_cnt_reg_n_0_[15] ;
  wire \converge_cnt_reg_n_0_[16] ;
  wire \converge_cnt_reg_n_0_[17] ;
  wire \converge_cnt_reg_n_0_[18] ;
  wire \converge_cnt_reg_n_0_[19] ;
  wire \converge_cnt_reg_n_0_[1] ;
  wire \converge_cnt_reg_n_0_[20] ;
  wire \converge_cnt_reg_n_0_[21] ;
  wire \converge_cnt_reg_n_0_[2] ;
  wire \converge_cnt_reg_n_0_[3] ;
  wire \converge_cnt_reg_n_0_[4] ;
  wire \converge_cnt_reg_n_0_[5] ;
  wire \converge_cnt_reg_n_0_[6] ;
  wire \converge_cnt_reg_n_0_[7] ;
  wire \converge_cnt_reg_n_0_[8] ;
  wire \converge_cnt_reg_n_0_[9] ;
  wire [5:0]fs_reg1;
  wire [5:0]fs_reg2;
  wire fsm1;
  wire [5:0]lf_reg1;
  wire [5:0]lf_reg2;
  wire new_txcoeff_done;
  wire new_txcoeff_req_reg1;
  wire new_txcoeff_req_reg2;
  wire [1:0]out;
  wire pclk_sel_reg;
  wire preset_done;
  wire [2:0]preset_reg1;
  wire [2:0]preset_reg2;
  wire preset_valid_reg1;
  wire preset_valid_reg2;
  wire rxeq_adapt_done_reg;
  wire rxeq_adapt_done_reg0;
  wire rxeq_adapt_done_reg_i_2__0_n_0;
  wire rxeq_adapt_done_reg_reg;
  wire rxeq_adapt_done_reg_reg_0;
  wire \rxeq_cnt_reg[1] ;
  wire \rxeq_cnt_reg[1]_0 ;
  wire \rxeq_control_reg2_reg[0] ;
  wire [5:0]\rxeq_fs_reg[5] ;
  wire [5:0]\rxeq_lf_reg[5] ;
  wire rxeq_new_txcoeff_req_reg;
  wire rxeq_new_txcoeff_req_reg_0;
  wire [2:0]\rxeq_preset_reg[2] ;
  wire rxeq_preset_valid_reg;
  wire [17:0]\rxeq_txcoeff_reg[17] ;
  wire rxeqscan_adapt_done;
  wire rxeqscan_new_txcoeff_done;
  wire rxeqscan_preset_done;
  wire [17:0]txcoeff_reg1;
  wire [17:0]txcoeff_reg2;
  wire [3:0]txpreset_reg1;
  wire [3:0]txpreset_reg2;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h000000073333FF07)) 
    \FSM_onehot_fsm[1]_i_1__1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(preset_valid_reg2),
        .O(\FSM_onehot_fsm[1]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \FSM_onehot_fsm[2]_i_1__1 
       (.I0(preset_valid_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA8A8AA)) 
    \FSM_onehot_fsm[3]_i_1__1 
       (.I0(\FSM_onehot_fsm[3]_i_2__1_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_3__1_n_0 ),
        .I2(\FSM_onehot_fsm[3]_i_4__1_n_0 ),
        .I3(\converge_cnt_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm[3]_i_5__0_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h2020202020202F20)) 
    \FSM_onehot_fsm[3]_i_2__1 
       (.I0(new_txcoeff_req_reg2),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(fsm1),
        .I5(\FSM_onehot_fsm_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm[3]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF6FFFFFFFF6FFF)) 
    \FSM_onehot_fsm[3]_i_3__1 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .I1(\converge_cnt_reg_n_0_[2] ),
        .I2(\converge_cnt_reg_n_0_[10] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[20] ),
        .O(\FSM_onehot_fsm[3]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFF7E7EFFFF7EFF7E)) 
    \FSM_onehot_fsm[3]_i_4__1 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[8] ),
        .I3(\converge_cnt_reg_n_0_[21] ),
        .I4(out[0]),
        .I5(out[1]),
        .O(\FSM_onehot_fsm[3]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF9)) 
    \FSM_onehot_fsm[3]_i_5__0 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .I1(\converge_cnt_reg_n_0_[21] ),
        .I2(\converge_cnt_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[7] ),
        .I4(\FSM_onehot_fsm[3]_i_7__0_n_0 ),
        .I5(\FSM_onehot_fsm[3]_i_8__0_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_5__0_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_onehot_fsm[3]_i_6__0 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .O(fsm1));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[3]_i_7__0 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[16] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[3]_i_7__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFDFF)) 
    \FSM_onehot_fsm[3]_i_8__0 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .I1(\converge_cnt_reg_n_0_[4] ),
        .I2(\converge_cnt_reg_n_0_[12] ),
        .I3(\converge_cnt_reg_n_0_[9] ),
        .I4(\converge_cnt_reg_n_0_[5] ),
        .I5(\converge_cnt_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm[3]_i_8__0_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \FSM_onehot_fsm[4]_i_1__1 
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm[4]_i_2__0_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \FSM_onehot_fsm[4]_i_2__0 
       (.I0(\FSM_onehot_fsm[4]_i_3__1_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_4__0_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_5__0_n_0 ),
        .I3(\FSM_onehot_fsm[4]_i_6__0_n_0 ),
        .I4(\FSM_onehot_fsm[4]_i_7__0_n_0 ),
        .I5(\FSM_onehot_fsm[4]_i_8__0_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h02020202FF000000)) 
    \FSM_onehot_fsm[4]_i_3__1 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'h00004B00004B0000)) 
    \FSM_onehot_fsm[4]_i_4__0 
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\converge_cnt_reg_n_0_[21] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[10] ),
        .O(\FSM_onehot_fsm[4]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000810000810000)) 
    \FSM_onehot_fsm[4]_i_5__0 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[8] ),
        .I2(\converge_cnt_reg_n_0_[3] ),
        .I3(\converge_cnt_reg_n_0_[20] ),
        .I4(\converge_cnt_reg_n_0_[21] ),
        .I5(\converge_cnt_reg_n_0_[14] ),
        .O(\FSM_onehot_fsm[4]_i_5__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000024)) 
    \FSM_onehot_fsm[4]_i_6__0 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[0] ),
        .I3(\converge_cnt_reg_n_0_[5] ),
        .I4(\converge_cnt_reg_n_0_[4] ),
        .O(\FSM_onehot_fsm[4]_i_6__0_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \FSM_onehot_fsm[4]_i_7__0 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\converge_cnt_reg_n_0_[11] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[9] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[4]_i_7__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \FSM_onehot_fsm[4]_i_8__0 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .I1(\converge_cnt_reg_n_0_[6] ),
        .I2(\converge_cnt_reg_n_0_[16] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[19] ),
        .I5(\converge_cnt_reg_n_0_[7] ),
        .O(\FSM_onehot_fsm[4]_i_8__0_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__1_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hEFEEEEEE)) 
    \FSM_sequential_fsm_rx[0]_i_1__0 
       (.I0(\FSM_sequential_fsm_rx_reg[0] ),
        .I1(\rxeq_cnt_reg[1] ),
        .I2(rxeqscan_new_txcoeff_done),
        .I3(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h0CAF0CA0FF000F00)) 
    \FSM_sequential_fsm_rx[1]_i_1__0 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(\rxeq_cnt_reg[1]_0 ),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\rxeq_control_reg2_reg[0] ),
        .I5(\FSM_sequential_fsm_rx_reg[2] [0]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h3F083FC8330833C8)) 
    \FSM_sequential_fsm_rx[2]_i_1__0 
       (.I0(rxeqscan_preset_done),
        .I1(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I4(\rxeq_cnt_reg[1]_0 ),
        .I5(\rxeq_control_reg2_reg[0] ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'h00FF2A00)) 
    adapt_done_cnt_i_1__0
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(out[0]),
        .I2(out[1]),
        .I3(adapt_done_cnt),
        .I4(adapt_done_cnt_reg_n_0),
        .O(adapt_done_cnt_i_1__0_n_0));
  LUT6 #(
    .INIT(64'hFFFF444744444447)) 
    adapt_done_cnt_i_2__0
       (.I0(new_txcoeff_req_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I5(fsm1),
        .O(adapt_done_cnt));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_cnt_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done_cnt_i_1__0_n_0),
        .Q(adapt_done_cnt_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hA8880000)) 
    adapt_done_i_1__0
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[1]),
        .I3(out[0]),
        .I4(new_txcoeff_req_reg2),
        .O(adapt_done));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(adapt_done),
        .Q(rxeqscan_adapt_done),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[0]_i_1__8 
       (.I0(converge_cnt0[0]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[0]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[10]_i_1__0 
       (.I0(converge_cnt0[10]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[10]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[11]_i_1__0 
       (.I0(converge_cnt0[11]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[11]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_3__0 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .O(\converge_cnt[11]_i_3__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_4__0 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .O(\converge_cnt[11]_i_4__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_5__0 
       (.I0(\converge_cnt_reg_n_0_[9] ),
        .O(\converge_cnt[11]_i_5__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_6__0 
       (.I0(\converge_cnt_reg_n_0_[8] ),
        .O(\converge_cnt[11]_i_6__0_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[12]_i_1__0 
       (.I0(converge_cnt0[12]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[12]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[13]_i_1__0 
       (.I0(converge_cnt0[13]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[13]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[14]_i_1__0 
       (.I0(converge_cnt0[14]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[14]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[15]_i_1__0 
       (.I0(converge_cnt0[15]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[15]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_3__0 
       (.I0(\converge_cnt_reg_n_0_[15] ),
        .O(\converge_cnt[15]_i_3__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_4__0 
       (.I0(\converge_cnt_reg_n_0_[14] ),
        .O(\converge_cnt[15]_i_4__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_5__0 
       (.I0(\converge_cnt_reg_n_0_[13] ),
        .O(\converge_cnt[15]_i_5__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_6__0 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .O(\converge_cnt[15]_i_6__0_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[16]_i_1__0 
       (.I0(converge_cnt0[16]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[16]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[17]_i_1__0 
       (.I0(converge_cnt0[17]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[17]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[18]_i_1__0 
       (.I0(converge_cnt0[18]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[18]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[19]_i_1__0 
       (.I0(converge_cnt0[19]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[19]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_3__0 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .O(\converge_cnt[19]_i_3__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_4__0 
       (.I0(\converge_cnt_reg_n_0_[18] ),
        .O(\converge_cnt[19]_i_4__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_5__0 
       (.I0(\converge_cnt_reg_n_0_[17] ),
        .O(\converge_cnt[19]_i_5__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_6__0 
       (.I0(\converge_cnt_reg_n_0_[16] ),
        .O(\converge_cnt[19]_i_6__0_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[1]_i_1__0 
       (.I0(converge_cnt0[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[1]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[20]_i_1__0 
       (.I0(converge_cnt0[20]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[20]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[21]_i_1__0 
       (.I0(converge_cnt0[21]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[21]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_3__0 
       (.I0(\converge_cnt_reg_n_0_[21] ),
        .O(\converge_cnt[21]_i_3__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_4__0 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .O(\converge_cnt[21]_i_4__0_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[2]_i_1__0 
       (.I0(converge_cnt0[2]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[2]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[3]_i_1__0 
       (.I0(converge_cnt0[3]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[3]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_3__0 
       (.I0(\converge_cnt_reg_n_0_[3] ),
        .O(\converge_cnt[3]_i_3__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_4__0 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .O(\converge_cnt[3]_i_4__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_5__0 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .O(\converge_cnt[3]_i_5__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[3]_i_6__0 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .O(\converge_cnt[3]_i_6__0_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[4]_i_1__0 
       (.I0(converge_cnt0[4]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[4]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[5]_i_1__0 
       (.I0(converge_cnt0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[5]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[6]_i_1__0 
       (.I0(converge_cnt0[6]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[6]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[7]_i_1__0 
       (.I0(converge_cnt0[7]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[7]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_3__0 
       (.I0(\converge_cnt_reg_n_0_[7] ),
        .O(\converge_cnt[7]_i_3__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_4__0 
       (.I0(\converge_cnt_reg_n_0_[6] ),
        .O(\converge_cnt[7]_i_4__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_5__0 
       (.I0(\converge_cnt_reg_n_0_[5] ),
        .O(\converge_cnt[7]_i_5__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_6__0 
       (.I0(\converge_cnt_reg_n_0_[4] ),
        .O(\converge_cnt[7]_i_6__0_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[8]_i_1__0 
       (.I0(converge_cnt0[8]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[8]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[9]_i_1__0 
       (.I0(converge_cnt0[9]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[9]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[0]),
        .Q(\converge_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[10]),
        .Q(\converge_cnt_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[11]),
        .Q(\converge_cnt_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[11]_i_2__0 
       (.CI(\converge_cnt_reg[7]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[11]_i_2__0_n_0 ,\converge_cnt_reg[11]_i_2__0_n_1 ,\converge_cnt_reg[11]_i_2__0_n_2 ,\converge_cnt_reg[11]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[11:8]),
        .S({\converge_cnt[11]_i_3__0_n_0 ,\converge_cnt[11]_i_4__0_n_0 ,\converge_cnt[11]_i_5__0_n_0 ,\converge_cnt[11]_i_6__0_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[12]),
        .Q(\converge_cnt_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[13]),
        .Q(\converge_cnt_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[14]),
        .Q(\converge_cnt_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[15]),
        .Q(\converge_cnt_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[15]_i_2__0 
       (.CI(\converge_cnt_reg[11]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[15]_i_2__0_n_0 ,\converge_cnt_reg[15]_i_2__0_n_1 ,\converge_cnt_reg[15]_i_2__0_n_2 ,\converge_cnt_reg[15]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[15:12]),
        .S({\converge_cnt[15]_i_3__0_n_0 ,\converge_cnt[15]_i_4__0_n_0 ,\converge_cnt[15]_i_5__0_n_0 ,\converge_cnt[15]_i_6__0_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[16]),
        .Q(\converge_cnt_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[17]),
        .Q(\converge_cnt_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[18]),
        .Q(\converge_cnt_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[19]),
        .Q(\converge_cnt_reg_n_0_[19] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[19]_i_2__0 
       (.CI(\converge_cnt_reg[15]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[19]_i_2__0_n_0 ,\converge_cnt_reg[19]_i_2__0_n_1 ,\converge_cnt_reg[19]_i_2__0_n_2 ,\converge_cnt_reg[19]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[19:16]),
        .S({\converge_cnt[19]_i_3__0_n_0 ,\converge_cnt[19]_i_4__0_n_0 ,\converge_cnt[19]_i_5__0_n_0 ,\converge_cnt[19]_i_6__0_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[1]),
        .Q(\converge_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[20]),
        .Q(\converge_cnt_reg_n_0_[20] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[21]),
        .Q(\converge_cnt_reg_n_0_[21] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[21]_i_2__0 
       (.CI(\converge_cnt_reg[19]_i_2__0_n_0 ),
        .CO({\NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED [3:1],\converge_cnt_reg[21]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED [3:2],converge_cnt0[21:20]}),
        .S({1'b0,1'b0,\converge_cnt[21]_i_3__0_n_0 ,\converge_cnt[21]_i_4__0_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[2]),
        .Q(\converge_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[3]),
        .Q(\converge_cnt_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[3]_i_2__0 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[3]_i_2__0_n_0 ,\converge_cnt_reg[3]_i_2__0_n_1 ,\converge_cnt_reg[3]_i_2__0_n_2 ,\converge_cnt_reg[3]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\converge_cnt_reg_n_0_[0] }),
        .O(converge_cnt0[3:0]),
        .S({\converge_cnt[3]_i_3__0_n_0 ,\converge_cnt[3]_i_4__0_n_0 ,\converge_cnt[3]_i_5__0_n_0 ,\converge_cnt[3]_i_6__0_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[4]),
        .Q(\converge_cnt_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[5]),
        .Q(\converge_cnt_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[6]),
        .Q(\converge_cnt_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[7]),
        .Q(\converge_cnt_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[7]_i_2__0 
       (.CI(\converge_cnt_reg[3]_i_2__0_n_0 ),
        .CO({\converge_cnt_reg[7]_i_2__0_n_0 ,\converge_cnt_reg[7]_i_2__0_n_1 ,\converge_cnt_reg[7]_i_2__0_n_2 ,\converge_cnt_reg[7]_i_2__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[7:4]),
        .S({\converge_cnt[7]_i_3__0_n_0 ,\converge_cnt[7]_i_4__0_n_0 ,\converge_cnt[7]_i_5__0_n_0 ,\converge_cnt[7]_i_6__0_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[8]),
        .Q(\converge_cnt_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(converge_cnt[9]),
        .Q(\converge_cnt_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [0]),
        .Q(fs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [1]),
        .Q(fs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [2]),
        .Q(fs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [3]),
        .Q(fs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [4]),
        .Q(fs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [5]),
        .Q(fs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[0]),
        .Q(fs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[1]),
        .Q(fs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[2]),
        .Q(fs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[3]),
        .Q(fs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[4]),
        .Q(fs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(fs_reg1[5]),
        .Q(fs_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [0]),
        .Q(lf_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [1]),
        .Q(lf_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [2]),
        .Q(lf_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [3]),
        .Q(lf_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [4]),
        .Q(lf_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [5]),
        .Q(lf_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[0]),
        .Q(lf_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[1]),
        .Q(lf_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[2]),
        .Q(lf_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[3]),
        .Q(lf_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[4]),
        .Q(lf_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(lf_reg1[5]),
        .Q(lf_reg2[5]),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    new_txcoeff_done_i_1__0
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .O(new_txcoeff_done));
  FDRE #(
    .INIT(1'b0)) 
    new_txcoeff_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_done),
        .Q(rxeqscan_new_txcoeff_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_new_txcoeff_req_reg_0),
        .Q(new_txcoeff_req_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1),
        .Q(new_txcoeff_req_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hEA)) 
    preset_done_i_1__0
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(preset_done));
  FDRE #(
    .INIT(1'b0)) 
    preset_done_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_done),
        .Q(rxeqscan_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [0]),
        .Q(preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [1]),
        .Q(preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [2]),
        .Q(preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[0]),
        .Q(preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[1]),
        .Q(preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_reg1[2]),
        .Q(preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg1_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(rxeq_preset_valid_reg),
        .Q(preset_valid_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg2_reg
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(preset_valid_reg1),
        .Q(preset_valid_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0080F00000800000)) 
    rxeq_adapt_done_i_1__0
       (.I0(rxeq_adapt_done_reg0),
        .I1(rxeqscan_new_txcoeff_done),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I5(USER_RXEQ_ADAPT_DONE),
        .O(rxeq_adapt_done_reg));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rxeq_adapt_done_i_2__0
       (.I0(rxeqscan_adapt_done),
        .I1(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg0));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT5 #(
    .INIT(32'h44FF4000)) 
    rxeq_adapt_done_reg_i_1__0
       (.I0(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(rxeqscan_adapt_done),
        .I3(rxeq_adapt_done_reg_i_2__0_n_0),
        .I4(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg_reg));
  LUT6 #(
    .INIT(64'hF0F0002FF000002F)) 
    rxeq_adapt_done_reg_i_2__0
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I5(rxeqscan_new_txcoeff_done),
        .O(rxeq_adapt_done_reg_i_2__0_n_0));
  LUT4 #(
    .INIT(16'h0008)) 
    rxeq_new_txcoeff_req_i_1__0
       (.I0(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I3(rxeqscan_new_txcoeff_done),
        .O(rxeq_new_txcoeff_req_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [0]),
        .Q(txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [10]),
        .Q(txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [11]),
        .Q(txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [12]),
        .Q(txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [13]),
        .Q(txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [14]),
        .Q(txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [15]),
        .Q(txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [16]),
        .Q(txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [17]),
        .Q(txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [1]),
        .Q(txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [2]),
        .Q(txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [3]),
        .Q(txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [4]),
        .Q(txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [5]),
        .Q(txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [6]),
        .Q(txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [7]),
        .Q(txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [8]),
        .Q(txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [9]),
        .Q(txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[0]),
        .Q(txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[10] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[10]),
        .Q(txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[11] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[11]),
        .Q(txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[12] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[12]),
        .Q(txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[13] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[13]),
        .Q(txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[14] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[14]),
        .Q(txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[15] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[15]),
        .Q(txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[16] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[16]),
        .Q(txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[17] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[17]),
        .Q(txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[1]),
        .Q(txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[2]),
        .Q(txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[3]),
        .Q(txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[4] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[4]),
        .Q(txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[5] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[5]),
        .Q(txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[6] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[6]),
        .Q(txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[7] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[7]),
        .Q(txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[8] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[8]),
        .Q(txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[9] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txcoeff_reg1[9]),
        .Q(txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[0]),
        .Q(txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[1]),
        .Q(txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[2]),
        .Q(txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(Q[3]),
        .Q(txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[0] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[0]),
        .Q(txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[1] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[1]),
        .Q(txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[2] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[2]),
        .Q(txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[3] 
       (.C(pclk_sel_reg),
        .CE(1'b1),
        .D(txpreset_reg1[3]),
        .Q(txpreset_reg2[3]),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "PCIeGen1x8If64_rxeq_scan" *) 
module PCIeGen1x8If64_PCIeGen1x8If64_rxeq_scan_86
   (D,
    rxeq_new_txcoeff_req_reg,
    rxeq_adapt_done_reg,
    rxeq_adapt_done_reg_reg,
    RST_CPLLRESET,
    rxeq_new_txcoeff_req_reg_0,
    CLK,
    rxeq_preset_valid_reg,
    out,
    \FSM_sequential_fsm_rx_reg[0] ,
    \rxeq_cnt_reg[1] ,
    \FSM_sequential_fsm_rx_reg[2] ,
    \rxeq_cnt_reg[1]_0 ,
    \rxeq_control_reg2_reg[0] ,
    rxeq_adapt_done_reg_reg_0,
    USER_RXEQ_ADAPT_DONE,
    \rxeq_preset_reg[2] ,
    Q,
    \rxeq_txcoeff_reg[17] ,
    \rxeq_fs_reg[5] ,
    \rxeq_lf_reg[5] );
  output [2:0]D;
  output rxeq_new_txcoeff_req_reg;
  output rxeq_adapt_done_reg;
  output rxeq_adapt_done_reg_reg;
  input RST_CPLLRESET;
  input rxeq_new_txcoeff_req_reg_0;
  input CLK;
  input rxeq_preset_valid_reg;
  input [1:0]out;
  input \FSM_sequential_fsm_rx_reg[0] ;
  input \rxeq_cnt_reg[1] ;
  input [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  input \rxeq_cnt_reg[1]_0 ;
  input \rxeq_control_reg2_reg[0] ;
  input rxeq_adapt_done_reg_reg_0;
  input USER_RXEQ_ADAPT_DONE;
  input [2:0]\rxeq_preset_reg[2] ;
  input [3:0]Q;
  input [17:0]\rxeq_txcoeff_reg[17] ;
  input [5:0]\rxeq_fs_reg[5] ;
  input [5:0]\rxeq_lf_reg[5] ;

  wire CLK;
  wire [2:0]D;
  wire \FSM_onehot_fsm[1]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[2]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[3]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[3]_i_2__0_n_0 ;
  wire \FSM_onehot_fsm[3]_i_3__0_n_0 ;
  wire \FSM_onehot_fsm[3]_i_4__0_n_0 ;
  wire \FSM_onehot_fsm[3]_i_5_n_0 ;
  wire \FSM_onehot_fsm[3]_i_7_n_0 ;
  wire \FSM_onehot_fsm[3]_i_8_n_0 ;
  wire \FSM_onehot_fsm[4]_i_1__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_2_n_0 ;
  wire \FSM_onehot_fsm[4]_i_3__0_n_0 ;
  wire \FSM_onehot_fsm[4]_i_4_n_0 ;
  wire \FSM_onehot_fsm[4]_i_5_n_0 ;
  wire \FSM_onehot_fsm[4]_i_6_n_0 ;
  wire \FSM_onehot_fsm[4]_i_7_n_0 ;
  wire \FSM_onehot_fsm[4]_i_8_n_0 ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[0] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[1] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[2] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[3] ;
  (* RTL_KEEP = "yes" *) wire \FSM_onehot_fsm_reg_n_0_[4] ;
  wire \FSM_sequential_fsm_rx_reg[0] ;
  wire [2:0]\FSM_sequential_fsm_rx_reg[2] ;
  wire [3:0]Q;
  wire RST_CPLLRESET;
  wire USER_RXEQ_ADAPT_DONE;
  wire adapt_done;
  wire adapt_done_cnt;
  wire adapt_done_cnt_i_1_n_0;
  wire adapt_done_cnt_reg_n_0;
  wire [21:0]converge_cnt;
  wire [21:0]converge_cnt0;
  wire \converge_cnt[11]_i_3_n_0 ;
  wire \converge_cnt[11]_i_4_n_0 ;
  wire \converge_cnt[11]_i_5_n_0 ;
  wire \converge_cnt[11]_i_6_n_0 ;
  wire \converge_cnt[15]_i_3_n_0 ;
  wire \converge_cnt[15]_i_4_n_0 ;
  wire \converge_cnt[15]_i_5_n_0 ;
  wire \converge_cnt[15]_i_6_n_0 ;
  wire \converge_cnt[19]_i_3_n_0 ;
  wire \converge_cnt[19]_i_4_n_0 ;
  wire \converge_cnt[19]_i_5_n_0 ;
  wire \converge_cnt[19]_i_6_n_0 ;
  wire \converge_cnt[21]_i_3_n_0 ;
  wire \converge_cnt[21]_i_4_n_0 ;
  wire \converge_cnt[3]_i_3_n_0 ;
  wire \converge_cnt[3]_i_4_n_0 ;
  wire \converge_cnt[3]_i_5_n_0 ;
  wire \converge_cnt[3]_i_6_n_0 ;
  wire \converge_cnt[7]_i_3_n_0 ;
  wire \converge_cnt[7]_i_4_n_0 ;
  wire \converge_cnt[7]_i_5_n_0 ;
  wire \converge_cnt[7]_i_6_n_0 ;
  wire \converge_cnt_reg[11]_i_2_n_0 ;
  wire \converge_cnt_reg[11]_i_2_n_1 ;
  wire \converge_cnt_reg[11]_i_2_n_2 ;
  wire \converge_cnt_reg[11]_i_2_n_3 ;
  wire \converge_cnt_reg[15]_i_2_n_0 ;
  wire \converge_cnt_reg[15]_i_2_n_1 ;
  wire \converge_cnt_reg[15]_i_2_n_2 ;
  wire \converge_cnt_reg[15]_i_2_n_3 ;
  wire \converge_cnt_reg[19]_i_2_n_0 ;
  wire \converge_cnt_reg[19]_i_2_n_1 ;
  wire \converge_cnt_reg[19]_i_2_n_2 ;
  wire \converge_cnt_reg[19]_i_2_n_3 ;
  wire \converge_cnt_reg[21]_i_2_n_3 ;
  wire \converge_cnt_reg[3]_i_2_n_0 ;
  wire \converge_cnt_reg[3]_i_2_n_1 ;
  wire \converge_cnt_reg[3]_i_2_n_2 ;
  wire \converge_cnt_reg[3]_i_2_n_3 ;
  wire \converge_cnt_reg[7]_i_2_n_0 ;
  wire \converge_cnt_reg[7]_i_2_n_1 ;
  wire \converge_cnt_reg[7]_i_2_n_2 ;
  wire \converge_cnt_reg[7]_i_2_n_3 ;
  wire \converge_cnt_reg_n_0_[0] ;
  wire \converge_cnt_reg_n_0_[10] ;
  wire \converge_cnt_reg_n_0_[11] ;
  wire \converge_cnt_reg_n_0_[12] ;
  wire \converge_cnt_reg_n_0_[13] ;
  wire \converge_cnt_reg_n_0_[14] ;
  wire \converge_cnt_reg_n_0_[15] ;
  wire \converge_cnt_reg_n_0_[16] ;
  wire \converge_cnt_reg_n_0_[17] ;
  wire \converge_cnt_reg_n_0_[18] ;
  wire \converge_cnt_reg_n_0_[19] ;
  wire \converge_cnt_reg_n_0_[1] ;
  wire \converge_cnt_reg_n_0_[20] ;
  wire \converge_cnt_reg_n_0_[21] ;
  wire \converge_cnt_reg_n_0_[2] ;
  wire \converge_cnt_reg_n_0_[3] ;
  wire \converge_cnt_reg_n_0_[4] ;
  wire \converge_cnt_reg_n_0_[5] ;
  wire \converge_cnt_reg_n_0_[6] ;
  wire \converge_cnt_reg_n_0_[7] ;
  wire \converge_cnt_reg_n_0_[8] ;
  wire \converge_cnt_reg_n_0_[9] ;
  wire [5:0]fs_reg1;
  wire [5:0]fs_reg2;
  wire fsm1;
  wire [5:0]lf_reg1;
  wire [5:0]lf_reg2;
  wire new_txcoeff_done;
  wire new_txcoeff_req_reg1;
  wire new_txcoeff_req_reg2;
  wire [1:0]out;
  wire preset_done;
  wire [2:0]preset_reg1;
  wire [2:0]preset_reg2;
  wire preset_valid_reg1;
  wire preset_valid_reg2;
  wire rxeq_adapt_done_reg;
  wire rxeq_adapt_done_reg0;
  wire rxeq_adapt_done_reg_i_2_n_0;
  wire rxeq_adapt_done_reg_reg;
  wire rxeq_adapt_done_reg_reg_0;
  wire \rxeq_cnt_reg[1] ;
  wire \rxeq_cnt_reg[1]_0 ;
  wire \rxeq_control_reg2_reg[0] ;
  wire [5:0]\rxeq_fs_reg[5] ;
  wire [5:0]\rxeq_lf_reg[5] ;
  wire rxeq_new_txcoeff_req_reg;
  wire rxeq_new_txcoeff_req_reg_0;
  wire [2:0]\rxeq_preset_reg[2] ;
  wire rxeq_preset_valid_reg;
  wire [17:0]\rxeq_txcoeff_reg[17] ;
  wire rxeqscan_adapt_done;
  wire rxeqscan_new_txcoeff_done;
  wire rxeqscan_preset_done;
  wire [17:0]txcoeff_reg1;
  wire [17:0]txcoeff_reg2;
  wire [3:0]txpreset_reg1;
  wire [3:0]txpreset_reg2;
  wire [3:1]\NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED ;
  wire [3:2]\NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h000000073333FF07)) 
    \FSM_onehot_fsm[1]_i_1__0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I5(preset_valid_reg2),
        .O(\FSM_onehot_fsm[1]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \FSM_onehot_fsm[2]_i_1__0 
       (.I0(preset_valid_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(\FSM_onehot_fsm[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA8A8AA)) 
    \FSM_onehot_fsm[3]_i_1__0 
       (.I0(\FSM_onehot_fsm[3]_i_2__0_n_0 ),
        .I1(\FSM_onehot_fsm[3]_i_3__0_n_0 ),
        .I2(\FSM_onehot_fsm[3]_i_4__0_n_0 ),
        .I3(\converge_cnt_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_fsm[3]_i_5_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h2020202020202F20)) 
    \FSM_onehot_fsm[3]_i_2__0 
       (.I0(new_txcoeff_req_reg2),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(fsm1),
        .I5(\FSM_onehot_fsm_reg_n_0_[2] ),
        .O(\FSM_onehot_fsm[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF6FFFFFFFF6FFF)) 
    \FSM_onehot_fsm[3]_i_3__0 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .I1(\converge_cnt_reg_n_0_[2] ),
        .I2(\converge_cnt_reg_n_0_[10] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[20] ),
        .O(\FSM_onehot_fsm[3]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFF7E7EFFFF7EFF7E)) 
    \FSM_onehot_fsm[3]_i_4__0 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[8] ),
        .I3(\converge_cnt_reg_n_0_[21] ),
        .I4(out[0]),
        .I5(out[1]),
        .O(\FSM_onehot_fsm[3]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF9)) 
    \FSM_onehot_fsm[3]_i_5 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .I1(\converge_cnt_reg_n_0_[21] ),
        .I2(\converge_cnt_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[7] ),
        .I4(\FSM_onehot_fsm[3]_i_7_n_0 ),
        .I5(\FSM_onehot_fsm[3]_i_8_n_0 ),
        .O(\FSM_onehot_fsm[3]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_onehot_fsm[3]_i_6 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .O(fsm1));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \FSM_onehot_fsm[3]_i_7 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[16] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFDFF)) 
    \FSM_onehot_fsm[3]_i_8 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .I1(\converge_cnt_reg_n_0_[4] ),
        .I2(\converge_cnt_reg_n_0_[12] ),
        .I3(\converge_cnt_reg_n_0_[9] ),
        .I4(\converge_cnt_reg_n_0_[5] ),
        .I5(\converge_cnt_reg_n_0_[6] ),
        .O(\FSM_onehot_fsm[3]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \FSM_onehot_fsm[4]_i_1__0 
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I2(\FSM_onehot_fsm[4]_i_2_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \FSM_onehot_fsm[4]_i_2 
       (.I0(\FSM_onehot_fsm[4]_i_3__0_n_0 ),
        .I1(\FSM_onehot_fsm[4]_i_4_n_0 ),
        .I2(\FSM_onehot_fsm[4]_i_5_n_0 ),
        .I3(\FSM_onehot_fsm[4]_i_6_n_0 ),
        .I4(\FSM_onehot_fsm[4]_i_7_n_0 ),
        .I5(\FSM_onehot_fsm[4]_i_8_n_0 ),
        .O(\FSM_onehot_fsm[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h02020202FF000000)) 
    \FSM_onehot_fsm[4]_i_3__0 
       (.I0(out[1]),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[0]),
        .I3(new_txcoeff_req_reg2),
        .I4(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I5(\FSM_onehot_fsm_reg_n_0_[3] ),
        .O(\FSM_onehot_fsm[4]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h00004B00004B0000)) 
    \FSM_onehot_fsm[4]_i_4 
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\converge_cnt_reg_n_0_[21] ),
        .I3(\converge_cnt_reg_n_0_[13] ),
        .I4(\converge_cnt_reg_n_0_[14] ),
        .I5(\converge_cnt_reg_n_0_[10] ),
        .O(\FSM_onehot_fsm[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000810000810000)) 
    \FSM_onehot_fsm[4]_i_5 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .I1(\converge_cnt_reg_n_0_[8] ),
        .I2(\converge_cnt_reg_n_0_[3] ),
        .I3(\converge_cnt_reg_n_0_[20] ),
        .I4(\converge_cnt_reg_n_0_[21] ),
        .I5(\converge_cnt_reg_n_0_[14] ),
        .O(\FSM_onehot_fsm[4]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h00000024)) 
    \FSM_onehot_fsm[4]_i_6 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .I1(\converge_cnt_reg_n_0_[3] ),
        .I2(\converge_cnt_reg_n_0_[0] ),
        .I3(\converge_cnt_reg_n_0_[5] ),
        .I4(\converge_cnt_reg_n_0_[4] ),
        .O(\FSM_onehot_fsm[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \FSM_onehot_fsm[4]_i_7 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .I1(\converge_cnt_reg_n_0_[18] ),
        .I2(\converge_cnt_reg_n_0_[11] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I4(\converge_cnt_reg_n_0_[9] ),
        .I5(\converge_cnt_reg_n_0_[15] ),
        .O(\FSM_onehot_fsm[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \FSM_onehot_fsm[4]_i_8 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .I1(\converge_cnt_reg_n_0_[6] ),
        .I2(\converge_cnt_reg_n_0_[16] ),
        .I3(\converge_cnt_reg_n_0_[17] ),
        .I4(\converge_cnt_reg_n_0_[19] ),
        .I5(\converge_cnt_reg_n_0_[7] ),
        .O(\FSM_onehot_fsm[4]_i_8_n_0 ));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \FSM_onehot_fsm_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .Q(\FSM_onehot_fsm_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDSE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[1]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[1] ),
        .S(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[2]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[3]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_fsm_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\FSM_onehot_fsm[4]_i_1__0_n_0 ),
        .Q(\FSM_onehot_fsm_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hEFEEEEEE)) 
    \FSM_sequential_fsm_rx[0]_i_1 
       (.I0(\FSM_sequential_fsm_rx_reg[0] ),
        .I1(\rxeq_cnt_reg[1] ),
        .I2(rxeqscan_new_txcoeff_done),
        .I3(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h0CAF0CA0FF000F00)) 
    \FSM_sequential_fsm_rx[1]_i_1 
       (.I0(rxeqscan_new_txcoeff_done),
        .I1(\rxeq_cnt_reg[1]_0 ),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\rxeq_control_reg2_reg[0] ),
        .I5(\FSM_sequential_fsm_rx_reg[2] [0]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h3F083FC8330833C8)) 
    \FSM_sequential_fsm_rx[2]_i_1 
       (.I0(rxeqscan_preset_done),
        .I1(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I4(\rxeq_cnt_reg[1]_0 ),
        .I5(\rxeq_control_reg2_reg[0] ),
        .O(D[2]));
  LUT5 #(
    .INIT(32'h00FF2A00)) 
    adapt_done_cnt_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(out[0]),
        .I2(out[1]),
        .I3(adapt_done_cnt),
        .I4(adapt_done_cnt_reg_n_0),
        .O(adapt_done_cnt_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFF444744444447)) 
    adapt_done_cnt_i_2
       (.I0(new_txcoeff_req_reg2),
        .I1(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .I3(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I4(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I5(fsm1),
        .O(adapt_done_cnt));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_cnt_reg
       (.C(CLK),
        .CE(1'b1),
        .D(adapt_done_cnt_i_1_n_0),
        .Q(adapt_done_cnt_reg_n_0),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'hA8880000)) 
    adapt_done_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(adapt_done_cnt_reg_n_0),
        .I2(out[1]),
        .I3(out[0]),
        .I4(new_txcoeff_req_reg2),
        .O(adapt_done));
  FDRE #(
    .INIT(1'b0)) 
    adapt_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(adapt_done),
        .Q(rxeqscan_adapt_done),
        .R(RST_CPLLRESET));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[0]_i_1__7 
       (.I0(converge_cnt0[0]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[0]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[10]_i_1 
       (.I0(converge_cnt0[10]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[10]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[11]_i_1 
       (.I0(converge_cnt0[11]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[11]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_3 
       (.I0(\converge_cnt_reg_n_0_[11] ),
        .O(\converge_cnt[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_4 
       (.I0(\converge_cnt_reg_n_0_[10] ),
        .O(\converge_cnt[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_5 
       (.I0(\converge_cnt_reg_n_0_[9] ),
        .O(\converge_cnt[11]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[11]_i_6 
       (.I0(\converge_cnt_reg_n_0_[8] ),
        .O(\converge_cnt[11]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[12]_i_1 
       (.I0(converge_cnt0[12]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[12]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[13]_i_1 
       (.I0(converge_cnt0[13]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[13]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[14]_i_1 
       (.I0(converge_cnt0[14]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[14]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[15]_i_1 
       (.I0(converge_cnt0[15]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[15]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_3 
       (.I0(\converge_cnt_reg_n_0_[15] ),
        .O(\converge_cnt[15]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_4 
       (.I0(\converge_cnt_reg_n_0_[14] ),
        .O(\converge_cnt[15]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_5 
       (.I0(\converge_cnt_reg_n_0_[13] ),
        .O(\converge_cnt[15]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[15]_i_6 
       (.I0(\converge_cnt_reg_n_0_[12] ),
        .O(\converge_cnt[15]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[16]_i_1 
       (.I0(converge_cnt0[16]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[16]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[17]_i_1 
       (.I0(converge_cnt0[17]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[17]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[18]_i_1 
       (.I0(converge_cnt0[18]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[18]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[19]_i_1 
       (.I0(converge_cnt0[19]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[19]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_3 
       (.I0(\converge_cnt_reg_n_0_[19] ),
        .O(\converge_cnt[19]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_4 
       (.I0(\converge_cnt_reg_n_0_[18] ),
        .O(\converge_cnt[19]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_5 
       (.I0(\converge_cnt_reg_n_0_[17] ),
        .O(\converge_cnt[19]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[19]_i_6 
       (.I0(\converge_cnt_reg_n_0_[16] ),
        .O(\converge_cnt[19]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[1]_i_1 
       (.I0(converge_cnt0[1]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[1]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[20]_i_1 
       (.I0(converge_cnt0[20]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[20]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[21]_i_1 
       (.I0(converge_cnt0[21]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[21]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_3 
       (.I0(\converge_cnt_reg_n_0_[21] ),
        .O(\converge_cnt[21]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[21]_i_4 
       (.I0(\converge_cnt_reg_n_0_[20] ),
        .O(\converge_cnt[21]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[2]_i_1 
       (.I0(converge_cnt0[2]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[2]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[3]_i_1 
       (.I0(converge_cnt0[3]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[3]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_3 
       (.I0(\converge_cnt_reg_n_0_[3] ),
        .O(\converge_cnt[3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_4 
       (.I0(\converge_cnt_reg_n_0_[2] ),
        .O(\converge_cnt[3]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[3]_i_5 
       (.I0(\converge_cnt_reg_n_0_[1] ),
        .O(\converge_cnt[3]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \converge_cnt[3]_i_6 
       (.I0(\converge_cnt_reg_n_0_[0] ),
        .O(\converge_cnt[3]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[4]_i_1 
       (.I0(converge_cnt0[4]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[4]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[5]_i_1 
       (.I0(converge_cnt0[5]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[5]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[6]_i_1 
       (.I0(converge_cnt0[6]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[6]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[7]_i_1 
       (.I0(converge_cnt0[7]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[7]));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_3 
       (.I0(\converge_cnt_reg_n_0_[7] ),
        .O(\converge_cnt[7]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_4 
       (.I0(\converge_cnt_reg_n_0_[6] ),
        .O(\converge_cnt[7]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_5 
       (.I0(\converge_cnt_reg_n_0_[5] ),
        .O(\converge_cnt[7]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \converge_cnt[7]_i_6 
       (.I0(\converge_cnt_reg_n_0_[4] ),
        .O(\converge_cnt[7]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[8]_i_1 
       (.I0(converge_cnt0[8]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[8]));
  LUT5 #(
    .INIT(32'h88888808)) 
    \converge_cnt[9]_i_1 
       (.I0(converge_cnt0[9]),
        .I1(\FSM_onehot_fsm_reg_n_0_[3] ),
        .I2(out[1]),
        .I3(adapt_done_cnt_reg_n_0),
        .I4(out[0]),
        .O(converge_cnt[9]));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[0]),
        .Q(\converge_cnt_reg_n_0_[0] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[10]),
        .Q(\converge_cnt_reg_n_0_[10] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[11]),
        .Q(\converge_cnt_reg_n_0_[11] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[11]_i_2 
       (.CI(\converge_cnt_reg[7]_i_2_n_0 ),
        .CO({\converge_cnt_reg[11]_i_2_n_0 ,\converge_cnt_reg[11]_i_2_n_1 ,\converge_cnt_reg[11]_i_2_n_2 ,\converge_cnt_reg[11]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[11:8]),
        .S({\converge_cnt[11]_i_3_n_0 ,\converge_cnt[11]_i_4_n_0 ,\converge_cnt[11]_i_5_n_0 ,\converge_cnt[11]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[12]),
        .Q(\converge_cnt_reg_n_0_[12] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[13]),
        .Q(\converge_cnt_reg_n_0_[13] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[14]),
        .Q(\converge_cnt_reg_n_0_[14] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[15]),
        .Q(\converge_cnt_reg_n_0_[15] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[15]_i_2 
       (.CI(\converge_cnt_reg[11]_i_2_n_0 ),
        .CO({\converge_cnt_reg[15]_i_2_n_0 ,\converge_cnt_reg[15]_i_2_n_1 ,\converge_cnt_reg[15]_i_2_n_2 ,\converge_cnt_reg[15]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[15:12]),
        .S({\converge_cnt[15]_i_3_n_0 ,\converge_cnt[15]_i_4_n_0 ,\converge_cnt[15]_i_5_n_0 ,\converge_cnt[15]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[16]),
        .Q(\converge_cnt_reg_n_0_[16] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[17]),
        .Q(\converge_cnt_reg_n_0_[17] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[18]),
        .Q(\converge_cnt_reg_n_0_[18] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[19]),
        .Q(\converge_cnt_reg_n_0_[19] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[19]_i_2 
       (.CI(\converge_cnt_reg[15]_i_2_n_0 ),
        .CO({\converge_cnt_reg[19]_i_2_n_0 ,\converge_cnt_reg[19]_i_2_n_1 ,\converge_cnt_reg[19]_i_2_n_2 ,\converge_cnt_reg[19]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[19:16]),
        .S({\converge_cnt[19]_i_3_n_0 ,\converge_cnt[19]_i_4_n_0 ,\converge_cnt[19]_i_5_n_0 ,\converge_cnt[19]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[1]),
        .Q(\converge_cnt_reg_n_0_[1] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[20]),
        .Q(\converge_cnt_reg_n_0_[20] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[21]),
        .Q(\converge_cnt_reg_n_0_[21] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[21]_i_2 
       (.CI(\converge_cnt_reg[19]_i_2_n_0 ),
        .CO({\NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED [3:1],\converge_cnt_reg[21]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED [3:2],converge_cnt0[21:20]}),
        .S({1'b0,1'b0,\converge_cnt[21]_i_3_n_0 ,\converge_cnt[21]_i_4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[2]),
        .Q(\converge_cnt_reg_n_0_[2] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[3]),
        .Q(\converge_cnt_reg_n_0_[3] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[3]_i_2 
       (.CI(1'b0),
        .CO({\converge_cnt_reg[3]_i_2_n_0 ,\converge_cnt_reg[3]_i_2_n_1 ,\converge_cnt_reg[3]_i_2_n_2 ,\converge_cnt_reg[3]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\converge_cnt_reg_n_0_[0] }),
        .O(converge_cnt0[3:0]),
        .S({\converge_cnt[3]_i_3_n_0 ,\converge_cnt[3]_i_4_n_0 ,\converge_cnt[3]_i_5_n_0 ,\converge_cnt[3]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[4]),
        .Q(\converge_cnt_reg_n_0_[4] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[5]),
        .Q(\converge_cnt_reg_n_0_[5] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[6]),
        .Q(\converge_cnt_reg_n_0_[6] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[7]),
        .Q(\converge_cnt_reg_n_0_[7] ),
        .R(RST_CPLLRESET));
  CARRY4 \converge_cnt_reg[7]_i_2 
       (.CI(\converge_cnt_reg[3]_i_2_n_0 ),
        .CO({\converge_cnt_reg[7]_i_2_n_0 ,\converge_cnt_reg[7]_i_2_n_1 ,\converge_cnt_reg[7]_i_2_n_2 ,\converge_cnt_reg[7]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(converge_cnt0[7:4]),
        .S({\converge_cnt[7]_i_3_n_0 ,\converge_cnt[7]_i_4_n_0 ,\converge_cnt[7]_i_5_n_0 ,\converge_cnt[7]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[8]),
        .Q(\converge_cnt_reg_n_0_[8] ),
        .R(RST_CPLLRESET));
  FDRE #(
    .INIT(1'b0)) 
    \converge_cnt_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(converge_cnt[9]),
        .Q(\converge_cnt_reg_n_0_[9] ),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [0]),
        .Q(fs_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [1]),
        .Q(fs_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [2]),
        .Q(fs_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [3]),
        .Q(fs_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [4]),
        .Q(fs_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_fs_reg[5] [5]),
        .Q(fs_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(fs_reg1[0]),
        .Q(fs_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(fs_reg1[1]),
        .Q(fs_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(fs_reg1[2]),
        .Q(fs_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(fs_reg1[3]),
        .Q(fs_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(fs_reg1[4]),
        .Q(fs_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \fs_reg2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(fs_reg1[5]),
        .Q(fs_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [0]),
        .Q(lf_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [1]),
        .Q(lf_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [2]),
        .Q(lf_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [3]),
        .Q(lf_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [4]),
        .Q(lf_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_lf_reg[5] [5]),
        .Q(lf_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(lf_reg1[0]),
        .Q(lf_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(lf_reg1[1]),
        .Q(lf_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(lf_reg1[2]),
        .Q(lf_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(lf_reg1[3]),
        .Q(lf_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(lf_reg1[4]),
        .Q(lf_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \lf_reg2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(lf_reg1[5]),
        .Q(lf_reg2[5]),
        .R(RST_CPLLRESET));
  LUT2 #(
    .INIT(4'h8)) 
    new_txcoeff_done_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[4] ),
        .I1(new_txcoeff_req_reg2),
        .O(new_txcoeff_done));
  FDRE #(
    .INIT(1'b0)) 
    new_txcoeff_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(new_txcoeff_done),
        .Q(rxeqscan_new_txcoeff_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_new_txcoeff_req_reg_0),
        .Q(new_txcoeff_req_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE new_txcoeff_req_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(new_txcoeff_req_reg1),
        .Q(new_txcoeff_req_reg2),
        .R(RST_CPLLRESET));
  LUT3 #(
    .INIT(8'hEA)) 
    preset_done_i_1
       (.I0(\FSM_onehot_fsm_reg_n_0_[2] ),
        .I1(preset_valid_reg2),
        .I2(\FSM_onehot_fsm_reg_n_0_[1] ),
        .O(preset_done));
  FDRE #(
    .INIT(1'b0)) 
    preset_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(preset_done),
        .Q(rxeqscan_preset_done),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [0]),
        .Q(preset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [1]),
        .Q(preset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_preset_reg[2] [2]),
        .Q(preset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(preset_reg1[0]),
        .Q(preset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(preset_reg1[1]),
        .Q(preset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \preset_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(preset_reg1[2]),
        .Q(preset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rxeq_preset_valid_reg),
        .Q(preset_valid_reg1),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE preset_valid_reg2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(preset_valid_reg1),
        .Q(preset_valid_reg2),
        .R(RST_CPLLRESET));
  LUT6 #(
    .INIT(64'h0080F00000800000)) 
    rxeq_adapt_done_i_1
       (.I0(rxeq_adapt_done_reg0),
        .I1(rxeqscan_new_txcoeff_done),
        .I2(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I5(USER_RXEQ_ADAPT_DONE),
        .O(rxeq_adapt_done_reg));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rxeq_adapt_done_i_2
       (.I0(rxeqscan_adapt_done),
        .I1(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg0));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT5 #(
    .INIT(32'h44FF4000)) 
    rxeq_adapt_done_reg_i_1
       (.I0(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(rxeqscan_adapt_done),
        .I3(rxeq_adapt_done_reg_i_2_n_0),
        .I4(rxeq_adapt_done_reg_reg_0),
        .O(rxeq_adapt_done_reg_reg));
  LUT6 #(
    .INIT(64'hF0F0002FF000002F)) 
    rxeq_adapt_done_reg_i_2
       (.I0(out[0]),
        .I1(out[1]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I3(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I4(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I5(rxeqscan_new_txcoeff_done),
        .O(rxeq_adapt_done_reg_i_2_n_0));
  LUT4 #(
    .INIT(16'h0008)) 
    rxeq_new_txcoeff_req_i_1
       (.I0(\FSM_sequential_fsm_rx_reg[2] [0]),
        .I1(\FSM_sequential_fsm_rx_reg[2] [2]),
        .I2(\FSM_sequential_fsm_rx_reg[2] [1]),
        .I3(rxeqscan_new_txcoeff_done),
        .O(rxeq_new_txcoeff_req_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [0]),
        .Q(txcoeff_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [10]),
        .Q(txcoeff_reg1[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [11]),
        .Q(txcoeff_reg1[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [12]),
        .Q(txcoeff_reg1[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [13]),
        .Q(txcoeff_reg1[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [14]),
        .Q(txcoeff_reg1[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [15]),
        .Q(txcoeff_reg1[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [16]),
        .Q(txcoeff_reg1[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [17]),
        .Q(txcoeff_reg1[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [1]),
        .Q(txcoeff_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [2]),
        .Q(txcoeff_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [3]),
        .Q(txcoeff_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [4]),
        .Q(txcoeff_reg1[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [5]),
        .Q(txcoeff_reg1[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [6]),
        .Q(txcoeff_reg1[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [7]),
        .Q(txcoeff_reg1[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [8]),
        .Q(txcoeff_reg1[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg1_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rxeq_txcoeff_reg[17] [9]),
        .Q(txcoeff_reg1[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[0]),
        .Q(txcoeff_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[10]),
        .Q(txcoeff_reg2[10]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[11]),
        .Q(txcoeff_reg2[11]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[12]),
        .Q(txcoeff_reg2[12]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[13]),
        .Q(txcoeff_reg2[13]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[14]),
        .Q(txcoeff_reg2[14]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[15]),
        .Q(txcoeff_reg2[15]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[16]),
        .Q(txcoeff_reg2[16]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[17]),
        .Q(txcoeff_reg2[17]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[1]),
        .Q(txcoeff_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[2]),
        .Q(txcoeff_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[3]),
        .Q(txcoeff_reg2[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[4]),
        .Q(txcoeff_reg2[4]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[5]),
        .Q(txcoeff_reg2[5]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[6]),
        .Q(txcoeff_reg2[6]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[7]),
        .Q(txcoeff_reg2[7]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[8]),
        .Q(txcoeff_reg2[8]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txcoeff_reg2_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(txcoeff_reg1[9]),
        .Q(txcoeff_reg2[9]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(Q[0]),
        .Q(txpreset_reg1[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(Q[1]),
        .Q(txpreset_reg1[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(Q[2]),
        .Q(txpreset_reg1[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(Q[3]),
        .Q(txpreset_reg1[3]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(txpreset_reg1[0]),
        .Q(txpreset_reg2[0]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(txpreset_reg1[1]),
        .Q(txpreset_reg2[1]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(txpreset_reg1[2]),
        .Q(txpreset_reg2[2]),
        .R(RST_CPLLRESET));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \txpreset_reg2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(txpreset_reg1[3]),
        .Q(txpreset_reg2[3]),
        .R(RST_CPLLRESET));
endmodule

(* ORIG_REF_NAME = "unimacro_BRAM_TDP_MACRO" *) 
module PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO
   (rdata,
    mim_tx_wen,
    user_clk,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [14:0]rdata;
  input mim_tx_wen;
  input user_clk;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [14:0]wdata;

  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_35 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_52 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_53 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_71 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_74 ;
  wire [14:0]rdata;
  wire user_clk;
  wire [14:0]wdata;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \ramb_bl.ramb36_dp_bl.ram36_bl 
       (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(user_clk),
        .CLKBWRCLK(user_clk),
        .DBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,wdata[14:9],wdata[7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,1'b0,wdata[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_35 }),
        .DOBDO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_n_52 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_53 ,rdata[14:9],rdata[7:0]}),
        .DOPADOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_71 }),
        .DOPBDOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_n_74 ,rdata[8]}),
        .ECCPARITY(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_tx_wen),
        .ENBWREN(mim_tx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "unimacro_BRAM_TDP_MACRO" *) 
module PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_11
   (rdata,
    mim_tx_wen,
    user_clk,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input mim_tx_wen;
  input user_clk;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_35 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_71 ;
  wire [17:0]rdata;
  wire user_clk;
  wire [17:0]wdata;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \ramb_bl.ramb36_dp_bl.ram36_bl 
       (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(user_clk),
        .CLKBWRCLK(user_clk),
        .DBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,wdata[16:9],wdata[7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,wdata[17],wdata[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_35 }),
        .DOBDO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED [31:16],rdata[16:9],rdata[7:0]}),
        .DOPADOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_71 }),
        .DOPBDOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED [3:2],rdata[17],rdata[8]}),
        .ECCPARITY(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_tx_wen),
        .ENBWREN(mim_tx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "unimacro_BRAM_TDP_MACRO" *) 
module PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_12
   (rdata,
    mim_tx_wen,
    user_clk,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input mim_tx_wen;
  input user_clk;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_35 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_71 ;
  wire [17:0]rdata;
  wire user_clk;
  wire [17:0]wdata;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \ramb_bl.ramb36_dp_bl.ram36_bl 
       (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(user_clk),
        .CLKBWRCLK(user_clk),
        .DBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,wdata[16:9],wdata[7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,wdata[17],wdata[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_35 }),
        .DOBDO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED [31:16],rdata[16:9],rdata[7:0]}),
        .DOPADOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_71 }),
        .DOPBDOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED [3:2],rdata[17],rdata[8]}),
        .ECCPARITY(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_tx_wen),
        .ENBWREN(mim_tx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "unimacro_BRAM_TDP_MACRO" *) 
module PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_13
   (rdata,
    mim_tx_wen,
    user_clk,
    mim_tx_ren,
    MIMTXWADDR,
    MIMTXRADDR,
    wdata);
  output [17:0]rdata;
  input mim_tx_wen;
  input user_clk;
  input mim_tx_ren;
  input [10:0]MIMTXWADDR;
  input [10:0]MIMTXRADDR;
  input [17:0]wdata;

  wire [10:0]MIMTXRADDR;
  wire [10:0]MIMTXWADDR;
  wire mim_tx_ren;
  wire mim_tx_wen;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_35 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_71 ;
  wire [17:0]rdata;
  wire user_clk;
  wire [17:0]wdata;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \ramb_bl.ramb36_dp_bl.ram36_bl 
       (.ADDRARDADDR({1'b1,MIMTXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMTXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(user_clk),
        .CLKBWRCLK(user_clk),
        .DBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,wdata[16:9],wdata[7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,wdata[17],wdata[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_35 }),
        .DOBDO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED [31:16],rdata[16:9],rdata[7:0]}),
        .DOPADOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_71 }),
        .DOPBDOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED [3:2],rdata[17],rdata[8]}),
        .ECCPARITY(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_tx_wen),
        .ENBWREN(mim_tx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "unimacro_BRAM_TDP_MACRO" *) 
module PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_18
   (\ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    mim_rx_wen,
    user_clk,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg );
  output [13:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  input mim_rx_wen;
  input user_clk;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [13:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;

  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire [13:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [13:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_35 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_52 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_53 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_54 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_71 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_74 ;
  wire user_clk;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \ramb_bl.ramb36_dp_bl.ram36_bl 
       (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(user_clk),
        .CLKBWRCLK(user_clk),
        .DBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\pipe_stages_1.pipe_rx_chanisaligned_q_reg [13:9],\pipe_stages_1.pipe_rx_chanisaligned_q_reg [7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,1'b0,\pipe_stages_1.pipe_rx_chanisaligned_q_reg [8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_35 }),
        .DOBDO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_n_52 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_53 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_54 ,\ramb_bl.ramb36_dp_bl.ram36_bl_0 [13:9],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7:0]}),
        .DOPADOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_71 }),
        .DOPBDOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_n_74 ,\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]}),
        .ECCPARITY(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_rx_wen),
        .ENBWREN(mim_rx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "unimacro_BRAM_TDP_MACRO" *) 
module PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_19
   (\ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    mim_rx_wen,
    user_clk,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg );
  output [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  input mim_rx_wen;
  input user_clk;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;

  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_35 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_71 ;
  wire user_clk;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \ramb_bl.ramb36_dp_bl.ram36_bl 
       (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(user_clk),
        .CLKBWRCLK(user_clk),
        .DBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\pipe_stages_1.pipe_rx_chanisaligned_q_reg [16:9],\pipe_stages_1.pipe_rx_chanisaligned_q_reg [7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,\pipe_stages_1.pipe_rx_chanisaligned_q_reg [17],\pipe_stages_1.pipe_rx_chanisaligned_q_reg [8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_35 }),
        .DOBDO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [16:9],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7:0]}),
        .DOPADOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_71 }),
        .DOPBDOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [17],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]}),
        .ECCPARITY(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_rx_wen),
        .ENBWREN(mim_rx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "unimacro_BRAM_TDP_MACRO" *) 
module PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_20
   (\ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    mim_rx_wen,
    user_clk,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg );
  output [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  input mim_rx_wen;
  input user_clk;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;

  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_35 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_71 ;
  wire user_clk;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \ramb_bl.ramb36_dp_bl.ram36_bl 
       (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(user_clk),
        .CLKBWRCLK(user_clk),
        .DBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\pipe_stages_1.pipe_rx_chanisaligned_q_reg [16:9],\pipe_stages_1.pipe_rx_chanisaligned_q_reg [7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,\pipe_stages_1.pipe_rx_chanisaligned_q_reg [17],\pipe_stages_1.pipe_rx_chanisaligned_q_reg [8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_35 }),
        .DOBDO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [16:9],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7:0]}),
        .DOPADOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_71 }),
        .DOPBDOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [17],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]}),
        .ECCPARITY(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_rx_wen),
        .ENBWREN(mim_rx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "unimacro_BRAM_TDP_MACRO" *) 
module PCIeGen1x8If64_unimacro_BRAM_TDP_MACRO_21
   (\ramb_bl.ramb36_dp_bl.ram36_bl_0 ,
    mim_rx_wen,
    user_clk,
    mim_rx_ren,
    MIMRXWADDR,
    MIMRXRADDR,
    \pipe_stages_1.pipe_rx_chanisaligned_q_reg );
  output [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  input mim_rx_wen;
  input user_clk;
  input mim_rx_ren;
  input [10:0]MIMRXWADDR;
  input [10:0]MIMRXRADDR;
  input [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;

  wire [10:0]MIMRXRADDR;
  wire [10:0]MIMRXWADDR;
  wire mim_rx_ren;
  wire mim_rx_wen;
  wire [17:0]\pipe_stages_1.pipe_rx_chanisaligned_q_reg ;
  wire [17:0]\ramb_bl.ramb36_dp_bl.ram36_bl_0 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_35 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ;
  wire \ramb_bl.ramb36_dp_bl.ram36_bl_n_71 ;
  wire user_clk;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ;
  wire \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED ;
  wire [31:16]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED ;
  wire [3:2]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED ;
  wire [7:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(0),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(18),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("NO_CHANGE"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(18)) 
    \ramb_bl.ramb36_dp_bl.ram36_bl 
       (.ADDRARDADDR({1'b1,MIMRXWADDR,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,MIMRXRADDR,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(user_clk),
        .CLKBWRCLK(user_clk),
        .DBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED ),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\pipe_stages_1.pipe_rx_chanisaligned_q_reg [16:9],\pipe_stages_1.pipe_rx_chanisaligned_q_reg [7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,\pipe_stages_1.pipe_rx_chanisaligned_q_reg [17],\pipe_stages_1.pipe_rx_chanisaligned_q_reg [8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_n_20 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_21 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_22 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_23 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_24 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_25 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_26 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_27 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_28 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_29 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_30 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_31 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_32 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_33 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_34 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_35 }),
        .DOBDO({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED [31:16],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [16:9],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [7:0]}),
        .DOPADOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_n_70 ,\ramb_bl.ramb36_dp_bl.ram36_bl_n_71 }),
        .DOPBDOP({\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED [3:2],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [17],\ramb_bl.ramb36_dp_bl.ram36_bl_0 [8]}),
        .ECCPARITY(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(mim_rx_wen),
        .ENBWREN(mim_rx_ren),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
