
use work.AdOCNet_2DMesh_pkg.all;

----------------------------------------------------------------------------------------------------
-- Actual File Name      = Router.vhd
-- Title & purpose       =  - 
-- Author                = Automaticaly generated by YANGO netlist generator - made by Matthieu PAYET (ADACSYS) - matthieu.payet@adacsys.com
-- Creation Date         = 2016-11-01 14:18
-- Version               = 0.1
-- Simple Description    = 
-- Specific issues       = 
-- Speed                 = 
-- Area estimates        = 
-- Tools (version)       = 
-- HDL standard followed = VHDL 2001 standard
-- Revisions & ECOs      = 
----------------------------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
-- ENTITY: Router_2DMesh 
--------------------------------------------------------------------------------
entity Router_2DMesh is 
	generic(
		FlitWidth      : natural := 16;
		NbInputs       : natural := 5;
		NbOutputs      : natural := 5;
		X_Local        : natural := 0;
		Y_Local        : natural := 0;
		InputFifoDepth : natural := 1024);
	port(
		HS_Rx      : IN  std_logic_vector(NbInputs-1 downto 0);
		HS_DataIn  : IN  FLITS(NbInputs-1 downto 0);
		HS_AckTx   : IN  std_logic_vector(NbOutputs-1 downto 0);
		HS_AckRx   : OUT std_logic_vector(NbInputs-1 downto 0);
		HS_Tx      : OUT std_logic_vector(NbOutputs-1 downto 0);
		HS_DataOut : OUT FLITS(NbOutputs-1 downto 0);
		clock      : IN  std_logic;
		reset      : IN  std_logic
	);
end entity Router_2DMesh;

--------------------------------------------------------------------------------
-- ARCHITECTURE: RTL - 
--------------------------------------------------------------------------------
architecture RTL of Router_2DMesh is

	signal Arbiter_RequestTable : std_logic_vector(NbInputs-1 downto 0);
	signal Arbiter_selectedport : natural;
	signal Crossbar_Input_AckTx : std_logic_vector(NbInputs-1 downto 0);
	signal Crossbar_Input_DataOut : FLITS(NbInputs-1 downto 0);
	signal Crossbar_Input_Tx : std_logic_vector(NbInputs-1 downto 0);
	signal Crossbar_inputconnections : NATURALS(NbInputs-1 downto 0);
	signal Crossbar_outputconnections : NATURALS(NbOutputs-1 downto 0);
	signal FIFO_IN_i0_DataIn : std_logic_vector(FlitWidth-1 downto 0);
	signal FIFO_IN_i0_DataOut : std_logic_vector(FlitWidth-1 downto 0);
	signal FIFO_IN_i0_IsEmpty : std_logic;
	signal FIFO_IN_i0_IsFull : std_logic;
	signal FIFO_IN_i0_Read : std_logic;
	signal FIFO_IN_i0_Write : std_logic;
	signal FIFO_IN_i1_DataIn : std_logic_vector(FlitWidth-1 downto 0);
	signal FIFO_IN_i1_DataOut : std_logic_vector(FlitWidth-1 downto 0);
	signal FIFO_IN_i1_IsEmpty : std_logic;
	signal FIFO_IN_i1_IsFull : std_logic;
	signal FIFO_IN_i1_Read : std_logic;
	signal FIFO_IN_i1_Write : std_logic;
	signal FIFO_IN_i2_DataIn : std_logic_vector(FlitWidth-1 downto 0);
	signal FIFO_IN_i2_DataOut : std_logic_vector(FlitWidth-1 downto 0);
	signal FIFO_IN_i2_IsEmpty : std_logic;
	signal FIFO_IN_i2_IsFull : std_logic;
	signal FIFO_IN_i2_Read : std_logic;
	signal FIFO_IN_i2_Write : std_logic;
	signal FIFO_IN_i3_DataIn : std_logic_vector(FlitWidth-1 downto 0);
	signal FIFO_IN_i3_DataOut : std_logic_vector(FlitWidth-1 downto 0);
	signal FIFO_IN_i3_IsEmpty : std_logic;
	signal FIFO_IN_i3_IsFull : std_logic;
	signal FIFO_IN_i3_Read : std_logic;
	signal FIFO_IN_i3_Write : std_logic;
	signal FIFO_IN_i4_DataIn : std_logic_vector(FlitWidth-1 downto 0);
	signal FIFO_IN_i4_DataOut : std_logic_vector(FlitWidth-1 downto 0);
	signal FIFO_IN_i4_IsEmpty : std_logic;
	signal FIFO_IN_i4_IsFull : std_logic;
	signal FIFO_IN_i4_Read : std_logic;
	signal FIFO_IN_i4_Write : std_logic;
	signal RoutingTable_Connected : std_logic_vector(NbInputs-1 downto 0);
	signal RoutingTable_RoutingReady : std_logic;
	signal RoutingTable_outputport : natural;

begin

	Arbiter: entity work.Arbiter(RTL)
		generic map(
			NbInputs => NbInputs
			)
		port map(
			Rst             => reset,
			Clk             => clock,
			RequestTable    => Arbiter_RequestTable,
			SelectedPort    => Arbiter_selectedport,
			ConnectionTable => RoutingTable_Connected
			);
	-----------------------------------------------------------------
	Crossbar: entity work.Crossbar(RTL)
		generic map(
			FlitWidth => FlitWidth,
			NbInputs  => NbInputs,
			NbOutputs => NbOutputs
			)
		port map(
			Input_DataOut     => Crossbar_Input_DataOut,
			Input_Tx          => Crossbar_Input_Tx,
			Input_AckTx       => Crossbar_Input_AckTx,
			Output_DataOut    => HS_DataOut,
			Output_Tx         => HS_Tx,
			Output_AckTx      => HS_AckTx,
			outputconnections => Crossbar_outputconnections,
			inputconnections  => Crossbar_inputconnections
			);
	-----------------------------------------------------------------
	FIFO_IN_i0: entity work.fifo(RTL)
		generic map(
			largeur    => FlitWidth,
			profondeur => InputFifoDepth
			)
		port map(
			reset     => reset,
			clock_in  => clock,
			clock_out => clock,
			data_in   => FIFO_IN_i0_DataIn,
			wr        => FIFO_IN_i0_Write,
			IsFull    => FIFO_IN_i0_IsFull,
			data_out  => FIFO_IN_i0_DataOut,
			rd        => FIFO_IN_i0_Read,
			IsEmpty   => FIFO_IN_i0_IsEmpty
			);
	-----------------------------------------------------------------
	FIFO_IN_i1: entity work.fifo(RTL)
		generic map(
			largeur    => FlitWidth,
			profondeur => InputFifoDepth
			)
		port map(
			reset     => reset,
			clock_in  => clock,
			clock_out => clock,
			data_in   => FIFO_IN_i1_DataIn,
			wr        => FIFO_IN_i1_Write,
			IsFull    => FIFO_IN_i1_IsFull,
			data_out  => FIFO_IN_i1_DataOut,
			rd        => FIFO_IN_i1_Read,
			IsEmpty   => FIFO_IN_i1_IsEmpty
			);
	-----------------------------------------------------------------
	FIFO_IN_i2: entity work.fifo(RTL)
		generic map(
			largeur    => FlitWidth,
			profondeur => InputFifoDepth
			)
		port map(
			reset     => reset,
			clock_in  => clock,
			clock_out => clock,
			data_in   => FIFO_IN_i2_DataIn,
			wr        => FIFO_IN_i2_Write,
			IsFull    => FIFO_IN_i2_IsFull,
			data_out  => FIFO_IN_i2_DataOut,
			rd        => FIFO_IN_i2_Read,
			IsEmpty   => FIFO_IN_i2_IsEmpty
			);
	-----------------------------------------------------------------
	FIFO_IN_i3: entity work.fifo(RTL)
		generic map(
			largeur    => FlitWidth,
			profondeur => InputFifoDepth
			)
		port map(
			reset     => reset,
			clock_in  => clock,
			clock_out => clock,
			data_in   => FIFO_IN_i3_DataIn,
			wr        => FIFO_IN_i3_Write,
			IsFull    => FIFO_IN_i3_IsFull,
			data_out  => FIFO_IN_i3_DataOut,
			rd        => FIFO_IN_i3_Read,
			IsEmpty   => FIFO_IN_i3_IsEmpty
			);
	-----------------------------------------------------------------
	FIFO_IN_i4: entity work.fifo(RTL)
		generic map(
			largeur    => FlitWidth,
			profondeur => InputFifoDepth
			)
		port map(
			reset     => reset,
			clock_in  => clock,
			clock_out => clock,
			data_in   => FIFO_IN_i4_DataIn,
			wr        => FIFO_IN_i4_Write,
			IsFull    => FIFO_IN_i4_IsFull,
			data_out  => FIFO_IN_i4_DataOut,
			rd        => FIFO_IN_i4_Read,
			IsEmpty   => FIFO_IN_i4_IsEmpty
			);
	-----------------------------------------------------------------
	HandShakeToFifo_i0: entity work.HandShakeToFifo(RTL)
		generic map(
			FlitWidth => FlitWidth
			)
		port map(
			rst         => reset,
			clk         => clock,
			fifo_write  => FIFO_IN_i0_Write,
			fifo_isfull => FIFO_IN_i0_IsFull,
			fifo_datain => FIFO_IN_i0_DataIn,
			hs_rx       => HS_Rx(0),
			hs_ackrx    => HS_AckRx(0),
			hs_datain   => HS_DataIn(0)
			);
	-----------------------------------------------------------------
	HandShakeToFifo_i1: entity work.HandShakeToFifo(RTL)
		generic map(
			FlitWidth => FlitWidth
			)
		port map(
			rst         => reset,
			clk         => clock,
			fifo_write  => FIFO_IN_i1_Write,
			fifo_isfull => FIFO_IN_i1_IsFull,
			fifo_datain => FIFO_IN_i1_DataIn,
			hs_rx       => HS_Rx(1),
			hs_ackrx    => HS_AckRx(1),
			hs_datain   => HS_DataIn(1)
			);
	-----------------------------------------------------------------
	HandShakeToFifo_i2: entity work.HandShakeToFifo(RTL)
		generic map(
			FlitWidth => FlitWidth
			)
		port map(
			rst         => reset,
			clk         => clock,
			fifo_write  => FIFO_IN_i2_Write,
			fifo_isfull => FIFO_IN_i2_IsFull,
			fifo_datain => FIFO_IN_i2_DataIn,
			hs_rx       => HS_Rx(2),
			hs_ackrx    => HS_AckRx(2),
			hs_datain   => HS_DataIn(2)
			);
	-----------------------------------------------------------------
	HandShakeToFifo_i3: entity work.HandShakeToFifo(RTL)
		generic map(
			FlitWidth => FlitWidth
			)
		port map(
			rst         => reset,
			clk         => clock,
			fifo_write  => FIFO_IN_i3_Write,
			fifo_isfull => FIFO_IN_i3_IsFull,
			fifo_datain => FIFO_IN_i3_DataIn,
			hs_rx       => HS_Rx(3),
			hs_ackrx    => HS_AckRx(3),
			hs_datain   => HS_DataIn(3)
			);
	-----------------------------------------------------------------
	HandShakeToFifo_i4: entity work.HandShakeToFifo(RTL)
		generic map(
			FlitWidth => FlitWidth
			)
		port map(
			rst         => reset,
			clk         => clock,
			fifo_write  => FIFO_IN_i4_Write,
			fifo_isfull => FIFO_IN_i4_IsFull,
			fifo_datain => FIFO_IN_i4_DataIn,
			hs_rx       => HS_Rx(4),
			hs_ackrx    => HS_AckRx(4),
			hs_datain   => HS_DataIn(4)
			);
	-----------------------------------------------------------------
	RoutingControl: entity work.routingcontrol(RTL)
		generic map(
			Y_Local   => Y_Local,
			X_Local   => X_Local,
			NbInputs  => NbInputs,
			FlitWidth => FlitWidth
			)
		port map(
			outputport        => RoutingTable_outputport,
			fifo_dataout_list => Crossbar_Input_DataOut,
			selectedinput     => Arbiter_selectedport,
			StartRouting      => Arbiter_RequestTable,
			RoutingReady      => RoutingTable_RoutingReady
			);
	-----------------------------------------------------------------
	RoutingTable: entity work.routingtable(RTL)
		generic map(
			NbInputs  => NbInputs,
			NbOutputs => NbOutputs
			)
		port map(
			Clk               => clock,
			RoutingReady      => RoutingTable_RoutingReady,
			Requests          => Arbiter_RequestTable,
			Connected         => RoutingTable_Connected,
			outputconnections => Crossbar_outputconnections,
			inputconnections  => Crossbar_inputconnections,
			outputport        => RoutingTable_outputport,
			selectedinput     => Arbiter_selectedport
			);
	-----------------------------------------------------------------
	-- Router Transfert Controller
	TransfertController_i0: entity work.TransfertControl(RTL)
		generic map(
			FlitWidth => FlitWidth
			)
		port map(
			rst            => reset,
			clk            => clock,
			HS_DataOut     => Crossbar_Input_DataOut(0),
			HS_Tx          => Crossbar_Input_Tx(0),
			HS_AckTx       => Crossbar_Input_AckTx(0),
			fifoin_isempty => FIFO_IN_i0_IsEmpty,
			fifoin_dataout => FIFO_IN_i0_DataOut,
			fifoin_read    => FIFO_IN_i0_Read,
			InputRequests  => Arbiter_RequestTable(0),
			InputConnected => RoutingTable_Connected(0)
			);
	-----------------------------------------------------------------
	-- Router Transfert Controller
	TransfertController_i1: entity work.TransfertControl(RTL)
		generic map(
			FlitWidth => FlitWidth
			)
		port map(
			rst            => reset,
			clk            => clock,
			HS_DataOut     => Crossbar_Input_DataOut(1),
			HS_Tx          => Crossbar_Input_Tx(1),
			HS_AckTx       => Crossbar_Input_AckTx(1),
			fifoin_isempty => FIFO_IN_i1_IsEmpty,
			fifoin_dataout => FIFO_IN_i1_DataOut,
			fifoin_read    => FIFO_IN_i1_Read,
			InputRequests  => Arbiter_RequestTable(1),
			InputConnected => RoutingTable_Connected(1)
			);
	-----------------------------------------------------------------
	-- Router Transfert Controller
	TransfertController_i2: entity work.TransfertControl(RTL)
		generic map(
			FlitWidth => FlitWidth
			)
		port map(
			rst            => reset,
			clk            => clock,
			HS_DataOut     => Crossbar_Input_DataOut(2),
			HS_Tx          => Crossbar_Input_Tx(2),
			HS_AckTx       => Crossbar_Input_AckTx(2),
			fifoin_isempty => FIFO_IN_i2_IsEmpty,
			fifoin_dataout => FIFO_IN_i2_DataOut,
			fifoin_read    => FIFO_IN_i2_Read,
			InputRequests  => Arbiter_RequestTable(2),
			InputConnected => RoutingTable_Connected(2)
			);
	-----------------------------------------------------------------
	-- Router Transfert Controller
	TransfertController_i3: entity work.TransfertControl(RTL)
		generic map(
			FlitWidth => FlitWidth
			)
		port map(
			rst            => reset,
			clk            => clock,
			HS_DataOut     => Crossbar_Input_DataOut(3),
			HS_Tx          => Crossbar_Input_Tx(3),
			HS_AckTx       => Crossbar_Input_AckTx(3),
			fifoin_isempty => FIFO_IN_i3_IsEmpty,
			fifoin_dataout => FIFO_IN_i3_DataOut,
			fifoin_read    => FIFO_IN_i3_Read,
			InputRequests  => Arbiter_RequestTable(3),
			InputConnected => RoutingTable_Connected(3)
			);
	-----------------------------------------------------------------
	-- Router Transfert Controller
	TransfertController_i4: entity work.TransfertControl(RTL)
		generic map(
			FlitWidth => FlitWidth
			)
		port map(
			rst            => reset,
			clk            => clock,
			HS_DataOut     => Crossbar_Input_DataOut(4),
			HS_Tx          => Crossbar_Input_Tx(4),
			HS_AckTx       => Crossbar_Input_AckTx(4),
			fifoin_isempty => FIFO_IN_i4_IsEmpty,
			fifoin_dataout => FIFO_IN_i4_DataOut,
			fifoin_read    => FIFO_IN_i4_Read,
			InputRequests  => Arbiter_RequestTable(4),
			InputConnected => RoutingTable_Connected(4)
			);
	-----------------------------------------------------------------

end architecture RTL;

