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-- Actual File Name      = BOPM_computation_unit_8_47_VC707.vhd
-- Title & purpose       = VC707 wrapper for BOPM_computation_unit_8_47. - Add clock management for BOPM_computation_unit_8_47 instanciation on VC707.
-- Author                = Automaticaly generated by YANGO netlist generator - made by Matthieu PAYET (ADACSYS) - matthieu.payet@adacsys.com
-- Creation Date         = 2016-03-25 11:16
-- Version               = 0.1
-- Simple Description    = 
-- Specific issues       = 
-- Speed                 = 
-- Area estimates        = 
-- Tools (version)       = 
-- HDL standard followed = VHDL 2001 standard
-- Revisions & ECOs      = 
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library IEEE;
use IEEE.std_logic_1164.all;
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-- ENTITY: BOPM_computation_unit_8_47_VC707 - Add clock management for BOPM_computation_unit_8_47 instanciation on VC707.
--------------------------------------------------------------------------------
entity BOPM_computation_unit is 
	generic(
		DataWidth : natural := 64
		);

	port (
		--control signals    
		CLK               : in  std_logic;
		RST               : in  std_logic;
		--tree values (k and k-1 values from t+1)
		Stim1             : in  std_logic_vector(DataWidth-1 downto 0);
		Stim2             : in  std_logic_vector(DataWidth-1 downto 0);
		--outputs
		Trace1            : out std_logic_vector(DataWidth-1 downto 0)
		-- valid_out         : out std_logic -- output is valid at the next clock cycle (1 cycle delay)
	);
end entity BOPM_computation_unit;

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-- ARCHITECTURE: RTL - 
--------------------------------------------------------------------------------
architecture RTL of BOPM_computation_unit is

	signal Traces : std_logic_vector(3*56-1 downto 0);
--	signal Stim1, Stim2, Trace1 : std_logic_vector(3*55-1 downto 0);
begin
		

	-- BOPM_computation_unit_8_47
	BOPM_computation_unit_8_47_0: entity work.BOPM_computation_unit_8_47(RTL)
		port map(
			RST => RST,
			Cmd => '1',
			CLK => CLK,
			Enable => '1',
			
			d_stim => Stim1(55 downto 0),
			K_min_stim => Stim1(55 downto 0),
			rp_stim => Stim1(55 downto 0),
			rp_min_stim => Stim1(55 downto 0),
			
			S_k_stim => Stim1(55 downto 0),
			
			V_k_min_call_stim => Stim1(55 downto 0),
			V_k_min_put_stim  => Stim1(55 downto 0),
			
			V_k_put_stim  => Stim2(55 downto 0),
			V_k_call_stim => Stim2(55 downto 0),
			
			S_k_trace => Traces(3*56-1 downto 2*56),
			
			V_k_call_trace => Traces(2*56-1 downto 56),
			V_k_put_trace => Traces(56-1 downto 0)
			);
	-----------------------------------------------------------------
	
	Trace1(55 downto 0) <= Traces(3*56-1 downto 2*56) when Stim1(1 downto 0)="00" else
	                       Traces(2*56-1 downto 1*56) when Stim1(1 downto 0)="01" else
	                       Traces(1*56-1 downto 0*56) when Stim1(1 downto 0)="10" else
	                       (others=>'1') ;
	
	Trace1(DataWidth-1 downto 56) <= (others=>'0'); 
	
end architecture RTL;

