aag 147 6 35 1 106
2
4
6
8
10
12
14 16
18 20
22 24
26 28
30 32
34 36
38 40
42 44
46 48
50 52
54 56
58 60
62 64
66 68
70 72
74 76
78 80
82 1
16 213
24 219
28 223
36 229
40 233
44 237
60 241
64 245
76 251
20 257
32 265
48 269
52 273
56 283
68 287
72 291
80 295
84
84 83 206
86 12 5
88 13 19
90 4 13
92 90 75
94 9 52
96 95 13
98 96 75
100 95 7
102 100 23
104 8 13
106 9 71
108 12 9
110 108 35
112 7 9
114 11 13
116 112 114
118 78 117
120 119 27
122 6 8
124 6 10
126 6 12
128 8 10
130 8 12
132 10 12
134 123 125
136 127 129
138 131 133
140 134 136
142 140 138
144 117 143
146 38 117
148 14 7
150 9 11
152 148 150
154 152 13
156 78 3
158 156 5
160 159 43
162 3 5
164 2 4
166 163 165
168 58 167
170 62 163
172 161 169
174 171 32
176 172 174
178 99 103
180 105 107
182 111 48
184 121 145
186 147 155
188 56 177
190 178 180
192 182 184
194 186 188
196 190 192
198 196 194
200 87 89
202 93 68
204 200 202
206 204 199
208 83 0
210 82 38
212 209 211
214 7 23
216 82 215
218 209 217
220 82 121
222 209 221
224 9 35
226 82 225
228 209 227
230 82 117
232 209 231
234 82 161
236 209 235
238 82 162
240 209 239
242 82 58
244 209 243
246 13 75
248 82 247
250 209 249
252 83 1
254 82 200
256 253 255
258 169 171
260 258 32
262 82 260
264 253 263
266 82 182
268 253 267
270 82 94
272 253 271
274 145 147
276 155 56
278 274 276
280 82 278
282 253 281
284 82 202
286 253 285
288 82 180
290 253 289
292 82 0
294 253 293
i0 controllable_skip
i1 controllable_ship
i2 i_regaddr
i3 i_open
i4 i_reqc
i5 i_pay
l0 latch_x_var1
l1 latch_x_var1_prime
l2 latch_x_var2
l3 latch_x_var2_prime
l4 latch_x_var3
l5 latch_x_var3_prime
l6 latch_x_var4
l7 latch_x_var4_prime
l8 latch_x_var5
l9 latch_x_var5_prime
l10 latch_x_var6
l11 latch_x_var6_prime
l12 latch_x_var7
l13 latch_x_var7_prime
l14 latch_x_var8
l15 latch_x_var8_prime
l16 latch_x_var9
l17 latch_x_var9_prime
l18 latch_x_var10
l19 latch_x_var10_prime
l20 latch_x_var11
l21 latch_x_var11_prime
l22 latch_x_var12
l23 latch_x_var12_prime
l24 latch_x_var13
l25 latch_x_var13_prime
l26 latch_x_var14
l27 latch_x_var14_prime
l28 latch_x_var15
l29 latch_x_var15_prime
l30 latch_x_var16
l31 latch_x_var16_prime
l32 latch_x_var17
l33 latch_x_var17_prime
l34 latch_init
o0 F(X)
c

---state var:
x_var1: (before (before (or regaddr open reqc pay)))
x_var2: (weakbefore (triggers pay (or (not pay) ship)))
x_var3: (before (since PropositionalTrue(Logic.PLTL) regaddr))
x_var4: (before (since PropositionalTrue(Logic.PLTL) (and (weakbefore false) (or regaddr open reqc pay))))
x_var5: (weakbefore (triggers false (and (or (not (before (and (not skip) (not ship)))) (and (or skip ship) (not (and skip ship)))) (or (not (before (before (and (not skip) (not ship))))) (and (not skip) (not ship))))))
x_var6: (before (since PropositionalTrue(Logic.PLTL) open))
x_var7: (before (or regaddr open reqc pay))
x_var8: (before (since PropositionalTrue(Logic.PLTL) (and (weakbefore false) (not skip) (not ship))))
x_var9: (weakbefore (triggers false (or (not pay) (since PropositionalTrue(Logic.PLTL) open))))
x_var10: (weakbefore (triggers false (not open)))
x_var11: (weakbefore (triggers false (and (or (not (or regaddr open reqc pay)) (and (not (and regaddr open)) (not (and regaddr reqc)) (not (and regaddr pay)) (not (and open reqc)) (not (and open pay)) (not (and reqc pay)))) (or (not (before (or regaddr open reqc pay))) (and (not regaddr) (not open) (not reqc) (not pay))) (or (not (before (before (or regaddr open reqc pay)))) regaddr open reqc pay))))
x_var12: (before (and (not skip) (not ship)))
x_var13: (before (before (and (not skip) (not ship))))
x_var14: (weakbefore (triggers false (or (not ship) (since PropositionalTrue(Logic.PLTL) pay))))
x_var15: (weakbefore (triggers open (or (not open) pay)))
x_var16: (before (since PropositionalTrue(Logic.PLTL) pay))
x_var17: (weakbefore false)

---
initial state:
(and (not x_var1) (not x_var3) (not x_var4) (not x_var6) (not x_var7) (not x_var8) (not x_var12) (not x_var13) (not x_var16) x_var2 x_var5 x_var9 x_var10 x_var11 x_var14 x_var15 x_var17) 
---
transition relation:
x_var1_prime iff x_var7
x_var3_prime iff (or regaddr (and PropositionalTrue(Logic.PLTL) x_var3))
x_var4_prime iff (or (and x_var17 (or regaddr open reqc pay)) (and PropositionalTrue(Logic.PLTL) x_var4))
x_var6_prime iff (or open (and PropositionalTrue(Logic.PLTL) x_var6))
x_var7_prime iff (or regaddr open reqc pay)
x_var8_prime iff (or (and x_var17 (not skip) (not ship)) (and PropositionalTrue(Logic.PLTL) x_var8))
x_var12_prime iff (and (not skip) (not ship))
x_var13_prime iff x_var12
x_var16_prime iff (or pay (and PropositionalTrue(Logic.PLTL) x_var16))
x_var2_prime iff (and (or (not pay) ship) (or pay x_var2))
x_var5_prime iff (and (or (not x_var12) (and (or skip ship) (not (and skip ship)))) (or (not x_var13) (and (not skip) (not ship))) (or false x_var5))
x_var9_prime iff (and (or (not pay) open (and PropositionalTrue(Logic.PLTL) x_var6)) (or false x_var9))
x_var10_prime iff (and (not open) (or false x_var10))
x_var11_prime iff (and (or (not (or regaddr open reqc pay)) (and (not (and regaddr open)) (not (and regaddr reqc)) (not (and regaddr pay)) (not (and open reqc)) (not (and open pay)) (not (and reqc pay)))) (or (not x_var7) (and (not regaddr) (not open) (not reqc) (not pay))) (or (not x_var1) regaddr open reqc pay) (or false x_var11))
x_var14_prime iff (and (or (not ship) pay (and PropositionalTrue(Logic.PLTL) x_var16)) (or false x_var14))
x_var15_prime iff (and (or (not open) pay) (or open x_var15))
x_var17_prime iff false
---
final state: 
(and (or (not pay) ship) (or pay x_var2) (or (not ship) pay (and PropositionalTrue(Logic.PLTL) x_var16)) (or false x_var14) (or (not (and (or (and (not open) (or false x_var10)) pay (and PropositionalTrue(Logic.PLTL) x_var16)) (or (and (not open) (or false x_var10)) regaddr (and PropositionalTrue(Logic.PLTL) x_var3)) (or (not open) pay) (or open x_var15) (or (not pay) open (and PropositionalTrue(Logic.PLTL) x_var6)) (or false x_var9) (or (and x_var17 (or regaddr open reqc pay)) (and PropositionalTrue(Logic.PLTL) x_var4)) (or (not (or regaddr open reqc pay)) (and (not (and regaddr open)) (not (and regaddr reqc)) (not (and regaddr pay)) (not (and open reqc)) (not (and open pay)) (not (and reqc pay)))) (or (not x_var7) (and (not regaddr) (not open) (not reqc) (not pay))) (or (not x_var1) regaddr open reqc pay) (or false x_var11))) (and (or (and x_var17 (not skip) (not ship)) (and PropositionalTrue(Logic.PLTL) x_var8)) (or (not x_var12) (and (or skip ship) (not (and skip ship)))) (or (not x_var13) (and (not skip) (not ship))) (or false x_var5))))
