.gitignore
.gitmodules
LICENSE
README.md
pyproject.toml
.github/workflows/verilog.yml
docs/chisel.md
docs/pyrtl.md
docs/systemc.md
docs/verilog.md
docs/paper/Makefile
docs/paper/custom.sty
docs/paper/ssti.pdf
docs/paper/ssti.tex
docs/paper/diagrams/comm.png
docs/paper/diagrams/comm.xml
docs/paper/diagrams/data_flow.png
docs/paper/diagrams/data_flow.xml
docs/paper/diagrams/fsm.png
docs/paper/diagrams/fsm.xml
docs/paper/diagrams/intersection.png
docs/paper/diagrams/intersection.xml
docs/paper/diagrams/intersection_comp.png
docs/paper/diagrams/intersection_comp.xml
docs/paper/diagrams/sst.png
docs/paper/diagrams/sst.xml
docs/paper/diagrams/sst_before_after.png
docs/paper/diagrams/sst_int.png
docs/paper/diagrams/sst_int.xml
src/py.typed
src/sit/__init__.py
src/sit/exceptions.py
src/sit/exceptions.pyi
src/sit/pyrtl.py
src/sit/pyrtl.pyi
src/sit/sit.py
src/sit/sit.pyi
src/sit/systemc.py
src/sit/systemc.pyi
src/sit/verilog.py
src/sit/verilog.pyi
src/sit/cpp/CMakeLists.txt
src/sit/cpp/cmake/SITConfig.cmake.in
src/sit/cpp/libsit/sigutils.hpp
src/sit/cpp/libsit/sit.hpp
src/sit/cpp/libsit/socksigs.hpp
src/sit/cpp/libsit/zmqsigs.hpp
src/sit/template/verilog/Makefile.config
src/sit/template/verilog/comp
src/sit/template/verilog/driver
src/sit/util/__init__.py
src/sit/util/libmgmt.py
src/sit/util/libmgmt.pyi
src/sst_it.egg-info/PKG-INFO
src/sst_it.egg-info/SOURCES.txt
src/sst_it.egg-info/dependency_links.txt
src/sst_it.egg-info/requires.txt
src/sst_it.egg-info/top_level.txt
tests/CMakeLists.txt
tests/read_mem.py
tests/test_params.py
tests/unit.cpp
tests/verilog/generate_bbox.py
tests/verilog/common/ram.v
tests/verilog/sock/CMakeLists.txt
tests/verilog/sock/run.py
tests/verilog/zmq/CMakeLists.txt
tests/verilog/zmq/run.py