# Example EDIF Netlists

This directory contains the examples used for testing and documentation.

Name | Description | Size
-----|----------|----|


**4bitadder** - a four bit adder
**8051**
**adder**
**aes_128_noBRAM**
**b13**
**basic_clock_crossing**
**basic_synchronizer**
**bram**
**carrychain**
**counters128**
**flappy_nexys**
**float_demo**
**fourBitCounter**
**fourBitCounterWithAnd**
**hierarchical_luts**
**inverter** - a LUT1 that acts as an inverter
**lc2**
**lc3**
**leon3mp_hierarchical_flat**
**leon3mp_hierarchical**
**leon3mp**
**lfsr_kc705**
**lfsr_zybo**
**multi_port**
**n_bit_counter**
**namespace**
**netlist_with_large_integer**
**one_counter**
**osfbm**
**passthrough_test**
**port_test**
**ports_diff_modules**
**register_file**
**riscv_multi_core**
**sha3_core**
**shift_reg**
**SID**
**synchronizer_test**
**synth_th1_slaac**
**testCountMult**
**three_layer_hierarchy**
**three_stage_synchronizer**
**three_stage_synchronizer2**
**TMR_hierarchy**
**toggle** - a very simple design with a single flip flop and a LUT2. Oscillates between 1 and 0.
**unique_challenge**
**unique_different_modules**
**unused_blackbox**
**zpu4**