; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevmac -verify-machineinstrs -global-isel=1 < %s \
; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL

define i32 @mulsRN(i32 %a, i32 %b) {
; CHECK-LABEL: mulsRN:
; CHECK:       # %bb.0:
; CHECK-NEXT:    slli a0, a0, 16
; CHECK-NEXT:    slli a1, a1, 16
; CHECK-GISEL-NEXT:    seal5.cv.mulhhsrn a0, a0, a1, 5
; CHECK-NEXT:    ret
  %1 = shl i32 %a, 16
  %2 = ashr i32 %1, 16
  %3 = shl i32 %b, 16
  %4 = ashr i32 %3, 16
  %5 = mul i32 %2, %4
  %6 = add i32 %5, 16
  %7 = ashr i32 %6, 5
  ret i32 %7
}
