# RISC-V Vector Development Suite

A set of tools for developing RISC-V Vector IP includes Random Test Generator (RTG), Assembler, and Simulator.

> **This project is not yet complete**.
>
> However, since my teammate needs it for testing the RTL design, I have decided to publish it anyway.

## Changelog

| Version | Description             | Owner                                              |
| ------- | ----------------------- | -------------------------------------------------- |
| 0.0.1   | Initial version         | [Nguyen Binh Khiem](https://github.com/khiemnb153) |
| 0.0.2   | Fix SRA operator of ICB | [Nguyen Binh Khiem](https://github.com/khiemnb153) |

## Supported features

## Configurations

## APIs
