
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.4.1
// timestamp : Wed Dec 16 03:37:04 2020 GMT
// usage     : riscv_ctg \
//                  -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv32ic.cgf') \
//                  -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lui instruction of the RISC-V C extension for the clui covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IC")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*C.*);def TEST_CASE_1=True;",clui)

RVTEST_SIGBASE( x2,signature_x2_1)

inst_0:
// rd==x12, rs1_val > 0 and imm_val > 32, imm_val == 42
// opcode:c.lui; op1:x12; dest:x12 op1val:0x80; immval:0xfffea
TEST_CI_OP( c.lui, x12, 0xfffea000, 0x80, 0xfffea, x2, 0, x13)

inst_1:
// rd==x21, rs1_val > 0 and imm_val < 32 and imm_val !=0 , 
// opcode:c.lui; op1:x21; dest:x21 op1val:0x20; immval:0xc
TEST_CI_OP( c.lui, x21, 0xc000, 0x20, 0xc, x2, 4, x13)

inst_2:
// rd==x27, rs1_val < 0 and imm_val > 32, 
// opcode:c.lui; op1:x27; dest:x27 op1val:-0x11; immval:0xfffff
TEST_CI_OP( c.lui, x27, 0xfffff000, -0x11, 0xfffff, x2, 8, x13)

inst_3:
// rd==x23, rs1_val < 0 and imm_val < 32 and imm_val !=0 , 
// opcode:c.lui; op1:x23; dest:x23 op1val:-0x2; immval:0xf
TEST_CI_OP( c.lui, x23, 0xf000, -0x2, 0xf, x2, 12, x13)

inst_4:
// rd==x19, imm_val == 1, 
// opcode:c.lui; op1:x19; dest:x19 op1val:-0x8000001; immval:0x1
TEST_CI_OP( c.lui, x19, 0x1000, -0x8000001, 0x1, x2, 16, x13)

inst_5:
// rd==x20, imm_val == 2, 
// opcode:c.lui; op1:x20; dest:x20 op1val:-0x10001; immval:0x2
TEST_CI_OP( c.lui, x20, 0x2000, -0x10001, 0x2, x2, 20, x13)

inst_6:
// rd==x8, imm_val == 4, 
// opcode:c.lui; op1:x8; dest:x8 op1val:0x1000; immval:0x4
TEST_CI_OP( c.lui, x8, 0x4000, 0x1000, 0x4, x2, 24, x13)

inst_7:
// rd==x29, imm_val == 8, 
// opcode:c.lui; op1:x29; dest:x29 op1val:0x7fffffff; immval:0x8
TEST_CI_OP( c.lui, x29, 0x8000, 0x7fffffff, 0x8, x2, 28, x13)

inst_8:
// rd==x31, imm_val == 16, 
// opcode:c.lui; op1:x31; dest:x31 op1val:-0x5; immval:0x10
TEST_CI_OP( c.lui, x31, 0x10000, -0x5, 0x10, x2, 32, x13)

inst_9:
// rd==x14, imm_val == 32, 
// opcode:c.lui; op1:x14; dest:x14 op1val:0x400000; immval:0xfffe0
TEST_CI_OP( c.lui, x14, 0xfffe0000, 0x400000, 0xfffe0, x2, 36, x13)

inst_10:
// rd==x3, imm_val == 21, 
// opcode:c.lui; op1:x3; dest:x3 op1val:-0x2000001; immval:0x15
TEST_CI_OP( c.lui, x3, 0x15000, -0x2000001, 0x15, x2, 40, x13)

inst_11:
// rd==x4, imm_val == 62, 
// opcode:c.lui; op1:x4; dest:x4 op1val:-0x7; immval:0xffffe
TEST_CI_OP( c.lui, x4, 0xffffe000, -0x7, 0xffffe, x2, 44, x13)

inst_12:
// rd==x17, imm_val == 61, 
// opcode:c.lui; op1:x17; dest:x17 op1val:0x4000; immval:0xffffd
TEST_CI_OP( c.lui, x17, 0xffffd000, 0x4000, 0xffffd, x2, 48, x13)

inst_13:
// rd==x10, imm_val == 59, 
// opcode:c.lui; op1:x10; dest:x10 op1val:0x40000; immval:0xffffb
TEST_CI_OP( c.lui, x10, 0xffffb000, 0x40000, 0xffffb, x2, 52, x13)

inst_14:
// rd==x7, imm_val == 55, 
// opcode:c.lui; op1:x7; dest:x7 op1val:-0x201; immval:0xffff7
TEST_CI_OP( c.lui, x7, 0xffff7000, -0x201, 0xffff7, x2, 56, x13)

inst_15:
// rd==x22, imm_val == 47, 
// opcode:c.lui; op1:x22; dest:x22 op1val:0x5; immval:0xfffef
TEST_CI_OP( c.lui, x22, 0xfffef000, 0x5, 0xfffef, x2, 60, x13)

inst_16:
// rd==x5, imm_val == 31, 
// opcode:c.lui; op1:x5; dest:x5 op1val:0x20; immval:0x1f
TEST_CI_OP( c.lui, x5, 0x1f000, 0x20, 0x1f, x2, 64, x13)

inst_17:
// rd==x25, 
// opcode:c.lui; op1:x25; dest:x25 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x25, 0x1000, -0x80000000, 0x1, x2, 68, x13)

inst_18:
// rd==x28, 
// opcode:c.lui; op1:x28; dest:x28 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x28, 0x1000, -0x80000000, 0x1, x2, 72, x13)

inst_19:
// rd==x0, 
// opcode:c.lui; op1:x0; dest:x0 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x0, 0, -0x80000000, 0x1, x2, 76, x13)

inst_20:
// rd==x11, 
// opcode:c.lui; op1:x11; dest:x11 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x11, 0x1000, -0x80000000, 0x1, x2, 80, x13)

inst_21:
// rd==x1, 
// opcode:c.lui; op1:x1; dest:x1 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x1, 0x1000, -0x80000000, 0x1, x2, 84, x13)

inst_22:
// rd==x18, 
// opcode:c.lui; op1:x18; dest:x18 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x18, 0x1000, -0x80000000, 0x1, x2, 88, x13)

inst_23:
// rd==x9, 
// opcode:c.lui; op1:x9; dest:x9 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x9, 0x1000, -0x80000000, 0x1, x2, 92, x13)

inst_24:
// rd==x26, 
// opcode:c.lui; op1:x26; dest:x26 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x26, 0x1000, -0x80000000, 0x1, x2, 96, x13)

inst_25:
// rd==x30, 
// opcode:c.lui; op1:x30; dest:x30 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x30, 0x1000, -0x80000000, 0x1, x2, 100, x13)

inst_26:
// rd==x16, 
// opcode:c.lui; op1:x16; dest:x16 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x16, 0x1000, -0x80000000, 0x1, x2, 104, x13)

inst_27:
// rd==x6, 
// opcode:c.lui; op1:x6; dest:x6 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x6, 0x1000, -0x80000000, 0x1, x2, 108, x13)

inst_28:
// rd==x15, 
// opcode:c.lui; op1:x15; dest:x15 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x15, 0x1000, -0x80000000, 0x1, x2, 112, x3)
RVTEST_SIGBASE( x1,signature_x1_0)

inst_29:
// rd==x24, 
// opcode:c.lui; op1:x24; dest:x24 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x24, 0x1000, -0x80000000, 0x1, x1, 0, x3)

inst_30:
// rd==x13, 
// opcode:c.lui; op1:x13; dest:x13 op1val:-0x80000000; immval:0x1
TEST_CI_OP( c.lui, x13, 0x1000, -0x80000000, 0x1, x1, 4, x3)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x2_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x2_1:
    .fill 29*(XLEN/32),4,0xdeadbeef


signature_x1_0:
    .fill 2*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END
