// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.5.0
// timestamp : Thu Jun 24 11:43:22 2021 GMT
// usage     : riscv_ctg \
//                  --cgf /home/sharder/git/incoresemi/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/sharder/git/incoresemi/riscv-ctg/sample_cgfs/rv32i_priv.cgf \
//                  --base-isa rv32i \
//                  --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the jalr instruction of the RISC-V I extension for the misalign1-jalr covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",misalign1-jalr)

RVTEST_SIGBASE( x1,signature_x1_1)

inst_0:
// imm_val%2 == 0 and ea_align == 1, 
// opcode: jalr; op1:x10; dest:x11; immval:0x4; align:1 
TEST_JALR_OP(x2, x11, x10, 0x4, x1, 0,1)

inst_1:
// imm_val%2 == 1 and ea_align == 1, 
// opcode: jalr; op1:x10; dest:x11; immval:-0x101; align:1 
TEST_JALR_OP(x2, x11, x10, -0x101, x1, 4,1)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 2*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END
