
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.4.1
// timestamp : Wed Dec 16 08:50:23 2020 GMT
// usage     : riscv_ctg \
//                  -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv64i_priv.cgf') \
//                  -- xlen 64 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the sd instruction of the RISC-V I extension for the misalign-sd covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True; def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",misalign-sd)

RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",misalign-sd)

RVTEST_SIGBASE( x1,signature_x1_1)

inst_0:
// ea_align == 1, 
// opcode: sd; op1:x10; op2:x11; op2val:-0x400000001; immval:0x2; align:1
TEST_STORE(x1,x2,0,x10,x11,-0x400000001,0x2,0,sd,1)

inst_1:
// ea_align == 2, 
// opcode: sd; op1:x10; op2:x11; op2val:0x100000000000; immval:0x80; align:2
TEST_STORE(x1,x2,0,x10,x11,0x100000000000,0x80,8,sd,2)

inst_2:
// ea_align == 3, 
// opcode: sd; op1:x10; op2:x11; op2val:0x80000000; immval:-0x401; align:3
TEST_STORE(x1,x2,0,x10,x11,0x80000000,-0x401,16,sd,3)

inst_3:
// ea_align == 4, 
// opcode: sd; op1:x10; op2:x11; op2val:0x5555555555555555; immval:0x40; align:4
TEST_STORE(x1,x2,0,x10,x11,0x5555555555555555,0x40,24,sd,4)

inst_4:
// ea_align == 5, 
// opcode: sd; op1:x10; op2:x11; op2val:-0x101; immval:-0x800; align:5
TEST_STORE(x1,x2,0,x10,x11,-0x101,-0x800,32,sd,5)

inst_5:
// ea_align == 6, 
// opcode: sd; op1:x10; op2:x11; op2val:-0x3; immval:-0x2; align:6
TEST_STORE(x1,x2,0,x10,x11,-0x3,-0x2,40,sd,6)

inst_6:
// ea_align == 7, 
// opcode: sd; op1:x10; op2:x11; op2val:0x4; immval:0x10; align:7
TEST_STORE(x1,x2,0,x10,x11,0x4,0x10,48,sd,7)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 7*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END
