
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.4.1
// timestamp : Wed Dec 16 03:37:04 2020 GMT
// usage     : riscv_ctg \
//                  -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv32ic.cgf') \
//                  -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jr instruction of the RISC-V C extension for the cjr covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IC")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*C.*);def TEST_CASE_1=True;",cjr)

RVTEST_SIGBASE( x2,signature_x2_1)

inst_0:
// rs1==x21, 
// opcode: c.jr; op1:x21
TEST_CJR_OP(x6, x21, x2, 0)

inst_1:
// rs1==x30, 
// opcode: c.jr; op1:x30
TEST_CJR_OP(x6, x30, x2, 4)

inst_2:
// rs1==x20, 
// opcode: c.jr; op1:x20
TEST_CJR_OP(x6, x20, x2, 8)

inst_3:
// rs1==x11, 
// opcode: c.jr; op1:x11
TEST_CJR_OP(x6, x11, x2, 12)

inst_4:
// rs1==x19, 
// opcode: c.jr; op1:x19
TEST_CJR_OP(x6, x19, x2, 16)

inst_5:
// rs1==x27, 
// opcode: c.jr; op1:x27
TEST_CJR_OP(x6, x27, x2, 20)

inst_6:
// rs1==x1, 
// opcode: c.jr; op1:x1
TEST_CJR_OP(x6, x1, x2, 24)

inst_7:
// rs1==x9, 
// opcode: c.jr; op1:x9
TEST_CJR_OP(x6, x9, x2, 28)

inst_8:
// rs1==x22, 
// opcode: c.jr; op1:x22
TEST_CJR_OP(x6, x22, x2, 32)

inst_9:
// rs1==x3, 
// opcode: c.jr; op1:x3
TEST_CJR_OP(x6, x3, x2, 36)

inst_10:
// rs1==x5, 
// opcode: c.jr; op1:x5
TEST_CJR_OP(x6, x5, x2, 40)

inst_11:
// rs1==x18, 
// opcode: c.jr; op1:x18
TEST_CJR_OP(x6, x18, x2, 44)

inst_12:
// rs1==x24, 
// opcode: c.jr; op1:x24
TEST_CJR_OP(x6, x24, x2, 48)

inst_13:
// rs1==x25, 
// opcode: c.jr; op1:x25
TEST_CJR_OP(x6, x25, x2, 52)

inst_14:
// rs1==x8, 
// opcode: c.jr; op1:x8
TEST_CJR_OP(x6, x8, x2, 56)

inst_15:
// rs1==x28, 
// opcode: c.jr; op1:x28
TEST_CJR_OP(x6, x28, x2, 60)

inst_16:
// rs1==x14, 
// opcode: c.jr; op1:x14
TEST_CJR_OP(x6, x14, x2, 64)

inst_17:
// rs1==x4, 
// opcode: c.jr; op1:x4
TEST_CJR_OP(x6, x4, x2, 68)

inst_18:
// rs1==x15, 
// opcode: c.jr; op1:x15
TEST_CJR_OP(x6, x15, x2, 72)

inst_19:
// rs1==x12, 
// opcode: c.jr; op1:x12
TEST_CJR_OP(x6, x12, x2, 76)

inst_20:
// rs1==x29, 
// opcode: c.jr; op1:x29
TEST_CJR_OP(x6, x29, x2, 80)

inst_21:
// rs1==x23, 
// opcode: c.jr; op1:x23
TEST_CJR_OP(x6, x23, x2, 84)

inst_22:
// rs1==x31, 
// opcode: c.jr; op1:x31
TEST_CJR_OP(x6, x31, x2, 88)

inst_23:
// rs1==x26, 
// opcode: c.jr; op1:x26
TEST_CJR_OP(x6, x26, x2, 92)

inst_24:
// rs1==x7, 
// opcode: c.jr; op1:x7
TEST_CJR_OP(x6, x7, x2, 96)

inst_25:
// rs1==x13, 
// opcode: c.jr; op1:x13
TEST_CJR_OP(x6, x13, x2, 100)

inst_26:
// rs1==x17, 
// opcode: c.jr; op1:x17
TEST_CJR_OP(x3, x17, x2, 104)
RVTEST_SIGBASE( x1,signature_x1_0)

inst_27:
// rs1==x2, 
// opcode: c.jr; op1:x2
TEST_CJR_OP(x3, x2, x1, 0)

inst_28:
// rs1==x6, 
// opcode: c.jr; op1:x6
TEST_CJR_OP(x3, x6, x1, 4)

inst_29:
// rs1==x16, 
// opcode: c.jr; op1:x16
TEST_CJR_OP(x3, x16, x1, 8)

inst_30:
// rs1==x10, 
// opcode: c.jr; op1:x10
TEST_CJR_OP(x3, x10, x1, 12)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x2_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x2_1:
    .fill 27*(XLEN/32),4,0xdeadbeef


signature_x1_0:
    .fill 4*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END
