# RISC-V Compliance Test SLL-01
#
#
# Copyright (c) 2019 Imperas Software Ltd., www.imperas.com
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#   http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
# either express or implied.
#
# See the License for the specific language governing permissions and
# limitations under the License.
#
#
#
# Specification: RV32I Base Integer Instruction Set, Version 2.1
# Description: Testing instruction 'SLL'.

#include "compliance_test.h"
#include "compliance_model.h"

RVTEST_ISA("RV32I")

RVMODEL_BOOT
RVTEST_CODE_BEGIN


	RVMODEL_IO_INIT
	RVMODEL_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
	RVMODEL_IO_WRITE_STR(x31, "Test Begin\n")

#ifdef TEST_CASE_1
  RVTEST_CASE(1,"// check ISA:=regex(.*32.*); check ISA:=regex(.*I.*); def TEST_CASE_1=True", sll)

	# ---------------------------------------------------------------------------------------------

	RVMODEL_IO_WRITE_STR(x31, "# Test number 1\n")


    # address for test results
	la	x5, test_1_res

	TEST_RR_OP(sll, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6)   # Testcase 0
	TEST_RR_OP(sll, x1, x30, x15, 0x1, 0x1, 0x0, x5, 4, x6)   # Testcase 1
	TEST_RR_OP(sll, x2, x29, x14, 0x0, 0x0, -0x1, x5, 8, x6)   # Testcase 2
	TEST_RR_OP(sll, x3, x28, x13, 0x7ff0, 0x7ff, 0x4, x5, 12, x6)   # Testcase 3
	TEST_RR_OP(sll, x4, x27, x12, 0x0, 0x0, 0x8, x5, 16, x6)   # Testcase 4


	# ---------------------------------------------------------------------------------------------
	RVMODEL_IO_WRITE_STR(x31, "# Test number 2\n")


    # address for test results
	la	x1, test_2_res

	TEST_RR_OP(sll, x5, x26, x11, 0x0, 0x800, 0x1f, x1, 0, x2)   # Testcase 5
	TEST_RR_OP(sll, x6, x25, x10, 0x43210000, 0x7654321, 0x10, x1, 4, x2)   # Testcase 6
	TEST_RR_OP(sll, x7, x24, x9, 0x80000000, 0x7fffffff, -0x1, x1, 8, x2)   # Testcase 7
	TEST_RR_OP(sll, x8, x23, x8, 0x1, 0x1, 0x0, x1, 12, x2)   # Testcase 8
	TEST_RR_OP(sll, x9, x22, x7, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2)   # Testcase 9


	# ---------------------------------------------------------------------------------------------
	RVMODEL_IO_WRITE_STR(x31, "# Test number 3\n")


    # address for test results
	la	x1, test_3_res

	TEST_RR_OP(sll, x10, x21, x6, 0x0, 0x1234, -0x1, x1, 0, x7)   # Testcase 10
	TEST_RR_OP(sll, x11, x20, x5, 0x0, 0x80000000, 0x4, x1, 4, x7)   # Testcase 11
	TEST_RR_OP(sll, x12, x19, x4, 0xffedcc00, -0x1234, 0x8, x1, 8, x7)   # Testcase 12
	TEST_RR_OP(sll, x13, x18, x3, 0x80000000, -0x1, 0x1f, x1, 12, x7)   # Testcase 13
	TEST_RR_OP(sll, x14, x17, x2, 0xf8010000, -0x7ff, 0x10, x1, 16, x7)   # Testcase 14


	# ---------------------------------------------------------------------------------------------
	RVMODEL_IO_WRITE_STR(x31, "# Test number 4\n")


    # address for test results
	la	x2, test_4_res

	TEST_RR_OP(sll, x15, x16, x1, 0x0, 0x0, -0x1, x2, 0, x3)   # Testcase 15
	TEST_RR_OP(sll, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3)   # Testcase 16
	TEST_RR_OP(sll, x17, x14, x31, 0x1, 0x1, 0x0, x2, 8, x3)   # Testcase 17
	TEST_RR_OP(sll, x18, x13, x30, 0x0, 0x0, -0x1, x2, 12, x3)   # Testcase 18
	TEST_RR_OP(sll, x19, x12, x29, 0x7ff0, 0x7ff, 0x4, x2, 16, x3)   # Testcase 19


	# ---------------------------------------------------------------------------------------------
	RVMODEL_IO_WRITE_STR(x31, "# Test number 5\n")


    # address for test results
	la	x1, test_5_res

	TEST_RR_OP(sll, x20, x11, x28, 0x0, 0x0, 0x8, x1, 0, x2)   # Testcase 20
	TEST_RR_OP(sll, x21, x10, x27, 0x0, 0x800, 0x1f, x1, 4, x2)   # Testcase 21
	TEST_RR_OP(sll, x22, x9, x26, 0x43210000, 0x7654321, 0x10, x1, 8, x2)   # Testcase 22
	TEST_RR_OP(sll, x23, x8, x25, 0x80000000, 0x7fffffff, -0x1, x1, 12, x2)   # Testcase 23
	TEST_RR_OP(sll, x24, x7, x24, 0x1, 0x1, 0x0, x1, 16, x2)   # Testcase 24


	# ---------------------------------------------------------------------------------------------
	RVMODEL_IO_WRITE_STR(x31, "# Test number 6\n")


    # address for test results
	la	x1, test_6_res

	TEST_RR_OP(sll, x25, x6, x23, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7)   # Testcase 25
	TEST_RR_OP(sll, x26, x5, x22, 0x0, 0x1234, -0x1, x1, 4, x7)   # Testcase 26
	TEST_RR_OP(sll, x27, x4, x21, 0x0, 0x80000000, 0x4, x1, 8, x7)   # Testcase 27
	TEST_RR_OP(sll, x28, x3, x20, 0xffedcc00, -0x1234, 0x8, x1, 12, x7)   # Testcase 28
	TEST_RR_OP(sll, x29, x2, x19, 0x80000000, -0x1, 0x1f, x1, 16, x7)   # Testcase 29


	# ---------------------------------------------------------------------------------------------
	RVMODEL_IO_WRITE_STR(x31, "# Test number 7\n")


    # address for test results
	la	x2, test_7_res

	TEST_RR_OP(sll, x30, x1, x18, 0xf8010000, -0x7ff, 0x10, x2, 0, x3)   # Testcase 30
	TEST_RR_OP(sll, x31, x0, x17, 0x0, 0x0, -0x1, x2, 4, x3)   # Testcase 31


	# ---------------------------------------------------------------------------------------------
	
	RVMODEL_IO_WRITE_STR(x31, "Test End\n")

#endif

	# ---------------------------------------------------------------------------------------------

	RVMODEL_HALT

RVTEST_CODE_END

# Input data section.
	.data

# Output data section.
RVMODEL_DATA_BEGIN

test_1_res:
	.fill 5, 4, -1
test_2_res:
	.fill 5, 4, -1
test_3_res:
	.fill 5, 4, -1
test_4_res:
	.fill 5, 4, -1
test_5_res:
	.fill 5, 4, -1
test_6_res:
	.fill 5, 4, -1
test_7_res:
	.fill 5, 4, -1

RVMODEL_DATA_END

