// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `rdl2ot`

`include "prim_assert.sv"

module lc_ctrl_regs_reg_top (
  input clk_i,
  input rst_ni,
  input  tlul_pkg::tl_h2d_t tl_i,
  output tlul_pkg::tl_d2h_t tl_o,
  // To HW
  output lc_ctrl_reg_pkg::lc_ctrl_regs_reg2hw_t reg2hw, // Write
  input  lc_ctrl_reg_pkg::lc_ctrl_regs_hw2reg_t hw2reg, // Read

  // Integrity check errors
  output logic intg_err_o
);

  import lc_ctrl_reg_pkg::* ;

  localparam int AW = 8;
  localparam int DW = 32;
  localparam int DBW = DW/8;                    // Byte Width

  // register signals
  logic           reg_we;
  logic           reg_re;
  logic [AW-1:0]  reg_addr;
  logic [DW-1:0]  reg_wdata;
  logic [DBW-1:0] reg_be;
  logic [DW-1:0]  reg_rdata;
  logic           reg_error;

  logic          addrmiss, wr_err;

  logic [DW-1:0] reg_rdata_next;
  logic reg_busy;

  tlul_pkg::tl_h2d_t tl_reg_h2d;
  tlul_pkg::tl_d2h_t tl_reg_d2h;


  // incoming payload check
  logic intg_err;
  tlul_cmd_intg_chk u_chk (
    .tl_i(tl_i),
    .err_o(intg_err)
  );

  // also check for spurious write enables
  logic reg_we_err;
  logic [34:0] reg_we_check;
  prim_reg_we_check #(
    .OneHotWidth(35)
  ) u_prim_reg_we_check (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .oh_i  (reg_we_check),
    .en_i  (reg_we && !addrmiss),
    .err_o (reg_we_err)
  );

  logic err_q;
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      err_q <= '0;
    end else if (intg_err || reg_we_err) begin
      err_q <= 1'b1;
    end
  end

  // integrity error output is permanent and should be used for alert generation
  // register errors are transactional
  assign intg_err_o = err_q | intg_err | reg_we_err;

  // outgoing integrity generation
  tlul_pkg::tl_d2h_t tl_o_pre;
  tlul_rsp_intg_gen #(
    .EnableRspIntgGen(1),
    .EnableDataIntgGen(1)
  ) u_rsp_intg_gen (
    .tl_i(tl_o_pre),
    .tl_o(tl_o)
  );

  assign tl_reg_h2d = tl_i;
  assign tl_o_pre   = tl_reg_d2h;

  tlul_adapter_reg #(
    .RegAw(AW),
    .RegDw(DW),
    .EnableDataIntgGen(0)
  ) u_reg_if (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),

    .tl_i (tl_reg_h2d),
    .tl_o (tl_reg_d2h),

    .en_ifetch_i(prim_mubi_pkg::MuBi4False),
    .intg_error_o(),

    .we_o    (reg_we),
    .re_o    (reg_re),
    .addr_o  (reg_addr),
    .wdata_o (reg_wdata),
    .be_o    (reg_be),
    .busy_i  (reg_busy),
    .rdata_i (reg_rdata),
    .error_i (reg_error)
  );

  // cdc oversampling signals

  assign reg_rdata = reg_rdata_next ;
  assign reg_error = addrmiss | wr_err | intg_err;

  // Define SW related signals
  // Format: <reg>_<field>_{wd|we|qs}
  //        or <reg>_{wd|we|qs} if field == 1 or 0
  logic alert_test_we;
  logic alert_test_fatal_prog_error_wd;
  logic alert_test_fatal_state_error_wd;
  logic alert_test_fatal_bus_integ_error_wd;
  logic status_re;
  logic status_initialized_qs;
  logic status_ready_qs;
  logic status_ext_clock_switched_qs;
  logic status_transition_successful_qs;
  logic status_transition_count_error_qs;
  logic status_transition_error_qs;
  logic status_token_error_qs;
  logic status_flash_rma_error_qs;
  logic status_otp_error_qs;
  logic status_state_error_qs;
  logic status_bus_integ_error_qs;
  logic status_otp_partition_error_qs;
  logic claim_transition_if_regwen_we;
  logic claim_transition_if_regwen_qs;
  logic claim_transition_if_regwen_wd;
  logic claim_transition_if_re;
  logic claim_transition_if_we;
  logic [7:0] claim_transition_if_qs;
  logic [7:0] claim_transition_if_wd;
  logic transition_regwen_re;
  logic transition_regwen_qs;
  logic transition_cmd_we;
  logic transition_cmd_wd;
  logic transition_ctrl_re;
  logic transition_ctrl_we;
  logic transition_ctrl_ext_clock_en_qs;
  logic transition_ctrl_ext_clock_en_wd;
  logic transition_ctrl_volatile_raw_unlock_qs;
  logic transition_ctrl_volatile_raw_unlock_wd;
  logic transition_token_0_re;
  logic transition_token_0_we;
  logic [31:0] transition_token_0_qs;
  logic [31:0] transition_token_0_wd;
  logic transition_token_1_re;
  logic transition_token_1_we;
  logic [31:0] transition_token_1_qs;
  logic [31:0] transition_token_1_wd;
  logic transition_token_2_re;
  logic transition_token_2_we;
  logic [31:0] transition_token_2_qs;
  logic [31:0] transition_token_2_wd;
  logic transition_token_3_re;
  logic transition_token_3_we;
  logic [31:0] transition_token_3_qs;
  logic [31:0] transition_token_3_wd;
  logic transition_target_re;
  logic transition_target_we;
  logic [29:0] transition_target_qs;
  logic [29:0] transition_target_wd;
  logic otp_vendor_test_ctrl_re;
  logic otp_vendor_test_ctrl_we;
  logic [31:0] otp_vendor_test_ctrl_qs;
  logic [31:0] otp_vendor_test_ctrl_wd;
  logic otp_vendor_test_status_re;
  logic [31:0] otp_vendor_test_status_qs;
  logic lc_state_re;
  logic [29:0] lc_state_qs;
  logic lc_transition_cnt_re;
  logic [4:0] lc_transition_cnt_qs;
  logic lc_id_state_re;
  logic [31:0] lc_id_state_qs;
  logic hw_revision0_re;
  logic [15:0] hw_revision0_product_id_qs;
  logic [15:0] hw_revision0_silicon_creator_id_qs;
  logic hw_revision1_re;
  logic [7:0] hw_revision1_revision_id_qs;
  logic [23:0] hw_revision1_reserved_qs;
  logic device_id_0_re;
  logic [31:0] device_id_0_qs;
  logic device_id_1_re;
  logic [31:0] device_id_1_qs;
  logic device_id_2_re;
  logic [31:0] device_id_2_qs;
  logic device_id_3_re;
  logic [31:0] device_id_3_qs;
  logic device_id_4_re;
  logic [31:0] device_id_4_qs;
  logic device_id_5_re;
  logic [31:0] device_id_5_qs;
  logic device_id_6_re;
  logic [31:0] device_id_6_qs;
  logic device_id_7_re;
  logic [31:0] device_id_7_qs;
  logic manuf_state_0_re;
  logic [31:0] manuf_state_0_qs;
  logic manuf_state_1_re;
  logic [31:0] manuf_state_1_qs;
  logic manuf_state_2_re;
  logic [31:0] manuf_state_2_qs;
  logic manuf_state_3_re;
  logic [31:0] manuf_state_3_qs;
  logic manuf_state_4_re;
  logic [31:0] manuf_state_4_qs;
  logic manuf_state_5_re;
  logic [31:0] manuf_state_5_qs;
  logic manuf_state_6_re;
  logic [31:0] manuf_state_6_qs;
  logic manuf_state_7_re;
  logic [31:0] manuf_state_7_qs;
  // Register instances
  // R[alert_test]: V(True)
  logic alert_test_qe;
  logic [2:0] alert_test_flds_we;
  assign alert_test_qe = &alert_test_flds_we;
  //   F[fatal_prog_error]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_alert_test_fatal_prog_error (
    .re     (1'b0),
    .we     (alert_test_we),
    .wd     (alert_test_fatal_prog_error_wd),
    .d      ('0),
    .qre    (),
    .qe     (alert_test_flds_we[0]),
    .q      (reg2hw.alert_test.fatal_prog_error.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.alert_test.fatal_prog_error.qe = alert_test_qe;

  //   F[fatal_state_error]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_alert_test_fatal_state_error (
    .re     (1'b0),
    .we     (alert_test_we),
    .wd     (alert_test_fatal_state_error_wd),
    .d      ('0),
    .qre    (),
    .qe     (alert_test_flds_we[1]),
    .q      (reg2hw.alert_test.fatal_state_error.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.alert_test.fatal_state_error.qe = alert_test_qe;

  //   F[fatal_bus_integ_error]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_alert_test_fatal_bus_integ_error (
    .re     (1'b0),
    .we     (alert_test_we),
    .wd     (alert_test_fatal_bus_integ_error_wd),
    .d      ('0),
    .qre    (),
    .qe     (alert_test_flds_we[2]),
    .q      (reg2hw.alert_test.fatal_bus_integ_error.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.alert_test.fatal_bus_integ_error.qe = alert_test_qe;


  // R[status]: V(True)
  //   F[initialized]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_initialized (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.initialized.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_initialized_qs)
  );

  //   F[ready]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_ready (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.ready.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_ready_qs)
  );

  //   F[ext_clock_switched]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_ext_clock_switched (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.ext_clock_switched.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_ext_clock_switched_qs)
  );

  //   F[transition_successful]: 3:3
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_transition_successful (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.transition_successful.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_transition_successful_qs)
  );

  //   F[transition_count_error]: 4:4
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_transition_count_error (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.transition_count_error.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_transition_count_error_qs)
  );

  //   F[transition_error]: 5:5
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_transition_error (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.transition_error.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_transition_error_qs)
  );

  //   F[token_error]: 6:6
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_token_error (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.token_error.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_token_error_qs)
  );

  //   F[flash_rma_error]: 7:7
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_flash_rma_error (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.flash_rma_error.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_flash_rma_error_qs)
  );

  //   F[otp_error]: 8:8
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_otp_error (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.otp_error.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_otp_error_qs)
  );

  //   F[state_error]: 9:9
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_state_error (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.state_error.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_state_error_qs)
  );

  //   F[bus_integ_error]: 10:10
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_bus_integ_error (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.bus_integ_error.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_bus_integ_error_qs)
  );

  //   F[otp_partition_error]: 11:11
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_otp_partition_error (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.otp_partition_error.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_otp_partition_error_qs)
  );


  // R[claim_transition_if_regwen]: V(False)
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW0C),
    .RESVAL  (1'h1),
    .Mubi    (1'b0)
  ) u_claim_transition_if_regwen (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (claim_transition_if_regwen_we),
    .wd     (claim_transition_if_regwen_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (claim_transition_if_regwen_qs)
  );


  // R[claim_transition_if]: V(True)
  logic claim_transition_if_qe;
  logic [0:0] claim_transition_if_flds_we;
  assign claim_transition_if_qe = &claim_transition_if_flds_we;
  // Create REGWEN-gated WE signal
  logic claim_transition_if_gated_we;
  assign claim_transition_if_gated_we = claim_transition_if_we & claim_transition_if_regwen_qs;
  prim_subreg_ext #(
    .DW    (8)
  ) u_claim_transition_if (
    .re     (claim_transition_if_re),
    .we     (claim_transition_if_gated_we),
    .wd     (claim_transition_if_wd),
    .d      (hw2reg.claim_transition_if.d),
    .qre    (),
    .qe     (claim_transition_if_flds_we[0]),
    .q      (reg2hw.claim_transition_if.q),
    .ds     (),
    .qs     (claim_transition_if_qs)
  );
  assign reg2hw.claim_transition_if.qe = claim_transition_if_qe;


  // R[transition_regwen]: V(True)
  prim_subreg_ext #(
    .DW    (1)
  ) u_transition_regwen (
    .re     (transition_regwen_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.transition_regwen.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (transition_regwen_qs)
  );


  // R[transition_cmd]: V(True)
  logic transition_cmd_qe;
  logic [0:0] transition_cmd_flds_we;
  assign transition_cmd_qe = &transition_cmd_flds_we;
  // Create REGWEN-gated WE signal
  logic transition_cmd_gated_we;
  assign transition_cmd_gated_we = transition_cmd_we & transition_regwen_qs;
  prim_subreg_ext #(
    .DW    (1)
  ) u_transition_cmd (
    .re     (1'b0),
    .we     (transition_cmd_gated_we),
    .wd     (transition_cmd_wd),
    .d      ('0),
    .qre    (),
    .qe     (transition_cmd_flds_we[0]),
    .q      (reg2hw.transition_cmd.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.transition_cmd.qe = transition_cmd_qe;


  // R[transition_ctrl]: V(True)
  logic transition_ctrl_qe;
  logic [1:0] transition_ctrl_flds_we;
  assign transition_ctrl_qe = &transition_ctrl_flds_we;
  // Create REGWEN-gated WE signal
  logic transition_ctrl_gated_we;
  assign transition_ctrl_gated_we = transition_ctrl_we & transition_regwen_qs;
  //   F[ext_clock_en]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_transition_ctrl_ext_clock_en (
    .re     (transition_ctrl_re),
    .we     (transition_ctrl_gated_we),
    .wd     (transition_ctrl_ext_clock_en_wd),
    .d      (hw2reg.transition_ctrl.ext_clock_en.d),
    .qre    (),
    .qe     (transition_ctrl_flds_we[0]),
    .q      (reg2hw.transition_ctrl.ext_clock_en.q),
    .ds     (),
    .qs     (transition_ctrl_ext_clock_en_qs)
  );
  assign reg2hw.transition_ctrl.ext_clock_en.qe = transition_ctrl_qe;

  //   F[volatile_raw_unlock]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_transition_ctrl_volatile_raw_unlock (
    .re     (transition_ctrl_re),
    .we     (transition_ctrl_gated_we),
    .wd     (transition_ctrl_volatile_raw_unlock_wd),
    .d      (hw2reg.transition_ctrl.volatile_raw_unlock.d),
    .qre    (),
    .qe     (transition_ctrl_flds_we[1]),
    .q      (reg2hw.transition_ctrl.volatile_raw_unlock.q),
    .ds     (),
    .qs     (transition_ctrl_volatile_raw_unlock_qs)
  );
  assign reg2hw.transition_ctrl.volatile_raw_unlock.qe = transition_ctrl_qe;


  // Subregister 0 of Multireg transition_token
  // R[transition_token_0]: V(True)
  logic transition_token_0_qe;
  logic [0:0] transition_token_0_flds_we;
  assign transition_token_0_qe = &transition_token_0_flds_we;
  // Create REGWEN-gated WE signal
  logic transition_token_0_gated_we;
  assign transition_token_0_gated_we = transition_token_0_we & transition_regwen_qs;
  prim_subreg_ext #(
    .DW    (32)
  ) u_transition_token_0 (
    .re     (transition_token_0_re),
    .we     (transition_token_0_gated_we),
    .wd     (transition_token_0_wd),
    .d      (hw2reg.transition_token[0].d),
    .qre    (),
    .qe     (transition_token_0_flds_we[0]),
    .q      (reg2hw.transition_token[0].q),
    .ds     (),
    .qs     (transition_token_0_qs)
  );
  assign reg2hw.transition_token[0].qe = transition_token_0_qe;


  // Subregister 1 of Multireg transition_token
  // R[transition_token_1]: V(True)
  logic transition_token_1_qe;
  logic [0:0] transition_token_1_flds_we;
  assign transition_token_1_qe = &transition_token_1_flds_we;
  // Create REGWEN-gated WE signal
  logic transition_token_1_gated_we;
  assign transition_token_1_gated_we = transition_token_1_we & transition_regwen_qs;
  prim_subreg_ext #(
    .DW    (32)
  ) u_transition_token_1 (
    .re     (transition_token_1_re),
    .we     (transition_token_1_gated_we),
    .wd     (transition_token_1_wd),
    .d      (hw2reg.transition_token[1].d),
    .qre    (),
    .qe     (transition_token_1_flds_we[0]),
    .q      (reg2hw.transition_token[1].q),
    .ds     (),
    .qs     (transition_token_1_qs)
  );
  assign reg2hw.transition_token[1].qe = transition_token_1_qe;


  // Subregister 2 of Multireg transition_token
  // R[transition_token_2]: V(True)
  logic transition_token_2_qe;
  logic [0:0] transition_token_2_flds_we;
  assign transition_token_2_qe = &transition_token_2_flds_we;
  // Create REGWEN-gated WE signal
  logic transition_token_2_gated_we;
  assign transition_token_2_gated_we = transition_token_2_we & transition_regwen_qs;
  prim_subreg_ext #(
    .DW    (32)
  ) u_transition_token_2 (
    .re     (transition_token_2_re),
    .we     (transition_token_2_gated_we),
    .wd     (transition_token_2_wd),
    .d      (hw2reg.transition_token[2].d),
    .qre    (),
    .qe     (transition_token_2_flds_we[0]),
    .q      (reg2hw.transition_token[2].q),
    .ds     (),
    .qs     (transition_token_2_qs)
  );
  assign reg2hw.transition_token[2].qe = transition_token_2_qe;


  // Subregister 3 of Multireg transition_token
  // R[transition_token_3]: V(True)
  logic transition_token_3_qe;
  logic [0:0] transition_token_3_flds_we;
  assign transition_token_3_qe = &transition_token_3_flds_we;
  // Create REGWEN-gated WE signal
  logic transition_token_3_gated_we;
  assign transition_token_3_gated_we = transition_token_3_we & transition_regwen_qs;
  prim_subreg_ext #(
    .DW    (32)
  ) u_transition_token_3 (
    .re     (transition_token_3_re),
    .we     (transition_token_3_gated_we),
    .wd     (transition_token_3_wd),
    .d      (hw2reg.transition_token[3].d),
    .qre    (),
    .qe     (transition_token_3_flds_we[0]),
    .q      (reg2hw.transition_token[3].q),
    .ds     (),
    .qs     (transition_token_3_qs)
  );
  assign reg2hw.transition_token[3].qe = transition_token_3_qe;


  // R[transition_target]: V(True)
  logic transition_target_qe;
  logic [0:0] transition_target_flds_we;
  assign transition_target_qe = &transition_target_flds_we;
  // Create REGWEN-gated WE signal
  logic transition_target_gated_we;
  assign transition_target_gated_we = transition_target_we & transition_regwen_qs;
  prim_subreg_ext #(
    .DW    (30)
  ) u_transition_target (
    .re     (transition_target_re),
    .we     (transition_target_gated_we),
    .wd     (transition_target_wd),
    .d      (hw2reg.transition_target.d),
    .qre    (),
    .qe     (transition_target_flds_we[0]),
    .q      (reg2hw.transition_target.q),
    .ds     (),
    .qs     (transition_target_qs)
  );
  assign reg2hw.transition_target.qe = transition_target_qe;


  // R[otp_vendor_test_ctrl]: V(True)
  logic otp_vendor_test_ctrl_qe;
  logic [0:0] otp_vendor_test_ctrl_flds_we;
  assign otp_vendor_test_ctrl_qe = &otp_vendor_test_ctrl_flds_we;
  // Create REGWEN-gated WE signal
  logic otp_vendor_test_ctrl_gated_we;
  assign otp_vendor_test_ctrl_gated_we = otp_vendor_test_ctrl_we & transition_regwen_qs;
  prim_subreg_ext #(
    .DW    (32)
  ) u_otp_vendor_test_ctrl (
    .re     (otp_vendor_test_ctrl_re),
    .we     (otp_vendor_test_ctrl_gated_we),
    .wd     (otp_vendor_test_ctrl_wd),
    .d      (hw2reg.otp_vendor_test_ctrl.d),
    .qre    (),
    .qe     (otp_vendor_test_ctrl_flds_we[0]),
    .q      (reg2hw.otp_vendor_test_ctrl.q),
    .ds     (),
    .qs     (otp_vendor_test_ctrl_qs)
  );
  assign reg2hw.otp_vendor_test_ctrl.qe = otp_vendor_test_ctrl_qe;


  // R[otp_vendor_test_status]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_otp_vendor_test_status (
    .re     (otp_vendor_test_status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.otp_vendor_test_status.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (otp_vendor_test_status_qs)
  );


  // R[lc_state]: V(True)
  prim_subreg_ext #(
    .DW    (30)
  ) u_lc_state (
    .re     (lc_state_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.lc_state.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (lc_state_qs)
  );


  // R[lc_transition_cnt]: V(True)
  prim_subreg_ext #(
    .DW    (5)
  ) u_lc_transition_cnt (
    .re     (lc_transition_cnt_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.lc_transition_cnt.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (lc_transition_cnt_qs)
  );


  // R[lc_id_state]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_lc_id_state (
    .re     (lc_id_state_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.lc_id_state.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (lc_id_state_qs)
  );


  // R[hw_revision0]: V(True)
  //   F[product_id]: 15:0
  prim_subreg_ext #(
    .DW    (16)
  ) u_hw_revision0_product_id (
    .re     (hw_revision0_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.hw_revision0.product_id.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (hw_revision0_product_id_qs)
  );

  //   F[silicon_creator_id]: 31:16
  prim_subreg_ext #(
    .DW    (16)
  ) u_hw_revision0_silicon_creator_id (
    .re     (hw_revision0_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.hw_revision0.silicon_creator_id.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (hw_revision0_silicon_creator_id_qs)
  );


  // R[hw_revision1]: V(True)
  //   F[revision_id]: 7:0
  prim_subreg_ext #(
    .DW    (8)
  ) u_hw_revision1_revision_id (
    .re     (hw_revision1_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.hw_revision1.revision_id.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (hw_revision1_revision_id_qs)
  );

  //   F[reserved]: 31:8
  prim_subreg_ext #(
    .DW    (24)
  ) u_hw_revision1_reserved (
    .re     (hw_revision1_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.hw_revision1.reserved.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (hw_revision1_reserved_qs)
  );


  // Subregister 0 of Multireg device_id
  // R[device_id_0]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_device_id_0 (
    .re     (device_id_0_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.device_id[0].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (device_id_0_qs)
  );


  // Subregister 1 of Multireg device_id
  // R[device_id_1]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_device_id_1 (
    .re     (device_id_1_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.device_id[1].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (device_id_1_qs)
  );


  // Subregister 2 of Multireg device_id
  // R[device_id_2]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_device_id_2 (
    .re     (device_id_2_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.device_id[2].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (device_id_2_qs)
  );


  // Subregister 3 of Multireg device_id
  // R[device_id_3]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_device_id_3 (
    .re     (device_id_3_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.device_id[3].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (device_id_3_qs)
  );


  // Subregister 4 of Multireg device_id
  // R[device_id_4]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_device_id_4 (
    .re     (device_id_4_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.device_id[4].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (device_id_4_qs)
  );


  // Subregister 5 of Multireg device_id
  // R[device_id_5]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_device_id_5 (
    .re     (device_id_5_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.device_id[5].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (device_id_5_qs)
  );


  // Subregister 6 of Multireg device_id
  // R[device_id_6]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_device_id_6 (
    .re     (device_id_6_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.device_id[6].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (device_id_6_qs)
  );


  // Subregister 7 of Multireg device_id
  // R[device_id_7]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_device_id_7 (
    .re     (device_id_7_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.device_id[7].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (device_id_7_qs)
  );


  // Subregister 0 of Multireg manuf_state
  // R[manuf_state_0]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_manuf_state_0 (
    .re     (manuf_state_0_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.manuf_state[0].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (manuf_state_0_qs)
  );


  // Subregister 1 of Multireg manuf_state
  // R[manuf_state_1]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_manuf_state_1 (
    .re     (manuf_state_1_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.manuf_state[1].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (manuf_state_1_qs)
  );


  // Subregister 2 of Multireg manuf_state
  // R[manuf_state_2]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_manuf_state_2 (
    .re     (manuf_state_2_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.manuf_state[2].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (manuf_state_2_qs)
  );


  // Subregister 3 of Multireg manuf_state
  // R[manuf_state_3]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_manuf_state_3 (
    .re     (manuf_state_3_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.manuf_state[3].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (manuf_state_3_qs)
  );


  // Subregister 4 of Multireg manuf_state
  // R[manuf_state_4]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_manuf_state_4 (
    .re     (manuf_state_4_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.manuf_state[4].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (manuf_state_4_qs)
  );


  // Subregister 5 of Multireg manuf_state
  // R[manuf_state_5]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_manuf_state_5 (
    .re     (manuf_state_5_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.manuf_state[5].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (manuf_state_5_qs)
  );


  // Subregister 6 of Multireg manuf_state
  // R[manuf_state_6]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_manuf_state_6 (
    .re     (manuf_state_6_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.manuf_state[6].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (manuf_state_6_qs)
  );


  // Subregister 7 of Multireg manuf_state
  // R[manuf_state_7]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_manuf_state_7 (
    .re     (manuf_state_7_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.manuf_state[7].d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (manuf_state_7_qs)
  );



  logic [34:0] addr_hit;
  always_comb begin
    addr_hit[ 0] = (reg_addr == LC_CTRL_ALERT_TEST_OFFSET);
    addr_hit[ 1] = (reg_addr == LC_CTRL_STATUS_OFFSET);
    addr_hit[ 2] = (reg_addr == LC_CTRL_CLAIM_TRANSITION_IF_REGWEN_OFFSET);
    addr_hit[ 3] = (reg_addr == LC_CTRL_CLAIM_TRANSITION_IF_OFFSET);
    addr_hit[ 4] = (reg_addr == LC_CTRL_TRANSITION_REGWEN_OFFSET);
    addr_hit[ 5] = (reg_addr == LC_CTRL_TRANSITION_CMD_OFFSET);
    addr_hit[ 6] = (reg_addr == LC_CTRL_TRANSITION_CTRL_OFFSET);
    addr_hit[ 7] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_0_OFFSET);
    addr_hit[ 8] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_1_OFFSET);
    addr_hit[ 9] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_2_OFFSET);
    addr_hit[10] = (reg_addr == LC_CTRL_TRANSITION_TOKEN_3_OFFSET);
    addr_hit[11] = (reg_addr == LC_CTRL_TRANSITION_TARGET_OFFSET);
    addr_hit[12] = (reg_addr == LC_CTRL_OTP_VENDOR_TEST_CTRL_OFFSET);
    addr_hit[13] = (reg_addr == LC_CTRL_OTP_VENDOR_TEST_STATUS_OFFSET);
    addr_hit[14] = (reg_addr == LC_CTRL_LC_STATE_OFFSET);
    addr_hit[15] = (reg_addr == LC_CTRL_LC_TRANSITION_CNT_OFFSET);
    addr_hit[16] = (reg_addr == LC_CTRL_LC_ID_STATE_OFFSET);
    addr_hit[17] = (reg_addr == LC_CTRL_HW_REVISION0_OFFSET);
    addr_hit[18] = (reg_addr == LC_CTRL_HW_REVISION1_OFFSET);
    addr_hit[19] = (reg_addr == LC_CTRL_DEVICE_ID_0_OFFSET);
    addr_hit[20] = (reg_addr == LC_CTRL_DEVICE_ID_1_OFFSET);
    addr_hit[21] = (reg_addr == LC_CTRL_DEVICE_ID_2_OFFSET);
    addr_hit[22] = (reg_addr == LC_CTRL_DEVICE_ID_3_OFFSET);
    addr_hit[23] = (reg_addr == LC_CTRL_DEVICE_ID_4_OFFSET);
    addr_hit[24] = (reg_addr == LC_CTRL_DEVICE_ID_5_OFFSET);
    addr_hit[25] = (reg_addr == LC_CTRL_DEVICE_ID_6_OFFSET);
    addr_hit[26] = (reg_addr == LC_CTRL_DEVICE_ID_7_OFFSET);
    addr_hit[27] = (reg_addr == LC_CTRL_MANUF_STATE_0_OFFSET);
    addr_hit[28] = (reg_addr == LC_CTRL_MANUF_STATE_1_OFFSET);
    addr_hit[29] = (reg_addr == LC_CTRL_MANUF_STATE_2_OFFSET);
    addr_hit[30] = (reg_addr == LC_CTRL_MANUF_STATE_3_OFFSET);
    addr_hit[31] = (reg_addr == LC_CTRL_MANUF_STATE_4_OFFSET);
    addr_hit[32] = (reg_addr == LC_CTRL_MANUF_STATE_5_OFFSET);
    addr_hit[33] = (reg_addr == LC_CTRL_MANUF_STATE_6_OFFSET);
    addr_hit[34] = (reg_addr == LC_CTRL_MANUF_STATE_7_OFFSET);
  end

  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;

  // Check sub-word write is permitted
  always_comb begin
    wr_err = (reg_we &
              ((addr_hit[ 0] & (|(LC_CTRL_REGS_PERMIT[ 0] & ~reg_be))) |
               (addr_hit[ 1] & (|(LC_CTRL_REGS_PERMIT[ 1] & ~reg_be))) |
               (addr_hit[ 2] & (|(LC_CTRL_REGS_PERMIT[ 2] & ~reg_be))) |
               (addr_hit[ 3] & (|(LC_CTRL_REGS_PERMIT[ 3] & ~reg_be))) |
               (addr_hit[ 4] & (|(LC_CTRL_REGS_PERMIT[ 4] & ~reg_be))) |
               (addr_hit[ 5] & (|(LC_CTRL_REGS_PERMIT[ 5] & ~reg_be))) |
               (addr_hit[ 6] & (|(LC_CTRL_REGS_PERMIT[ 6] & ~reg_be))) |
               (addr_hit[ 7] & (|(LC_CTRL_REGS_PERMIT[ 7] & ~reg_be))) |
               (addr_hit[ 8] & (|(LC_CTRL_REGS_PERMIT[ 8] & ~reg_be))) |
               (addr_hit[ 9] & (|(LC_CTRL_REGS_PERMIT[ 9] & ~reg_be))) |
               (addr_hit[10] & (|(LC_CTRL_REGS_PERMIT[10] & ~reg_be))) |
               (addr_hit[11] & (|(LC_CTRL_REGS_PERMIT[11] & ~reg_be))) |
               (addr_hit[12] & (|(LC_CTRL_REGS_PERMIT[12] & ~reg_be))) |
               (addr_hit[13] & (|(LC_CTRL_REGS_PERMIT[13] & ~reg_be))) |
               (addr_hit[14] & (|(LC_CTRL_REGS_PERMIT[14] & ~reg_be))) |
               (addr_hit[15] & (|(LC_CTRL_REGS_PERMIT[15] & ~reg_be))) |
               (addr_hit[16] & (|(LC_CTRL_REGS_PERMIT[16] & ~reg_be))) |
               (addr_hit[17] & (|(LC_CTRL_REGS_PERMIT[17] & ~reg_be))) |
               (addr_hit[18] & (|(LC_CTRL_REGS_PERMIT[18] & ~reg_be))) |
               (addr_hit[19] & (|(LC_CTRL_REGS_PERMIT[19] & ~reg_be))) |
               (addr_hit[20] & (|(LC_CTRL_REGS_PERMIT[20] & ~reg_be))) |
               (addr_hit[21] & (|(LC_CTRL_REGS_PERMIT[21] & ~reg_be))) |
               (addr_hit[22] & (|(LC_CTRL_REGS_PERMIT[22] & ~reg_be))) |
               (addr_hit[23] & (|(LC_CTRL_REGS_PERMIT[23] & ~reg_be))) |
               (addr_hit[24] & (|(LC_CTRL_REGS_PERMIT[24] & ~reg_be))) |
               (addr_hit[25] & (|(LC_CTRL_REGS_PERMIT[25] & ~reg_be))) |
               (addr_hit[26] & (|(LC_CTRL_REGS_PERMIT[26] & ~reg_be))) |
               (addr_hit[27] & (|(LC_CTRL_REGS_PERMIT[27] & ~reg_be))) |
               (addr_hit[28] & (|(LC_CTRL_REGS_PERMIT[28] & ~reg_be))) |
               (addr_hit[29] & (|(LC_CTRL_REGS_PERMIT[29] & ~reg_be))) |
               (addr_hit[30] & (|(LC_CTRL_REGS_PERMIT[30] & ~reg_be))) |
               (addr_hit[31] & (|(LC_CTRL_REGS_PERMIT[31] & ~reg_be))) |
               (addr_hit[32] & (|(LC_CTRL_REGS_PERMIT[32] & ~reg_be))) |
               (addr_hit[33] & (|(LC_CTRL_REGS_PERMIT[33] & ~reg_be))) |
               (addr_hit[34] & (|(LC_CTRL_REGS_PERMIT[34] & ~reg_be)))));
  end

  // Generate write-enables
  assign alert_test_we = addr_hit[0] & reg_we & !reg_error;

  assign alert_test_fatal_prog_error_wd = reg_wdata[0];

  assign alert_test_fatal_state_error_wd = reg_wdata[1];

  assign alert_test_fatal_bus_integ_error_wd = reg_wdata[2];

  assign status_re = addr_hit[1] & reg_re & !reg_error;
  assign claim_transition_if_regwen_we = addr_hit[2] & reg_we & !reg_error;

  assign claim_transition_if_regwen_wd = reg_wdata[0];

  assign claim_transition_if_re = addr_hit[3] & reg_re & !reg_error;
  assign claim_transition_if_we = addr_hit[3] & reg_we & !reg_error;

  assign claim_transition_if_wd = reg_wdata[7:0];

  assign transition_regwen_re = addr_hit[4] & reg_re & !reg_error;
  assign transition_cmd_we = addr_hit[5] & reg_we & !reg_error;

  assign transition_cmd_wd = reg_wdata[0];

  assign transition_ctrl_re = addr_hit[6] & reg_re & !reg_error;
  assign transition_ctrl_we = addr_hit[6] & reg_we & !reg_error;

  assign transition_ctrl_ext_clock_en_wd = reg_wdata[0];

  assign transition_ctrl_volatile_raw_unlock_wd = reg_wdata[1];

  assign transition_token_0_re = addr_hit[7] & reg_re & !reg_error;
  assign transition_token_0_we = addr_hit[7] & reg_we & !reg_error;

  assign transition_token_0_wd = reg_wdata[31:0];

  assign transition_token_1_re = addr_hit[8] & reg_re & !reg_error;
  assign transition_token_1_we = addr_hit[8] & reg_we & !reg_error;

  assign transition_token_1_wd = reg_wdata[31:0];

  assign transition_token_2_re = addr_hit[9] & reg_re & !reg_error;
  assign transition_token_2_we = addr_hit[9] & reg_we & !reg_error;

  assign transition_token_2_wd = reg_wdata[31:0];

  assign transition_token_3_re = addr_hit[10] & reg_re & !reg_error;
  assign transition_token_3_we = addr_hit[10] & reg_we & !reg_error;

  assign transition_token_3_wd = reg_wdata[31:0];

  assign transition_target_re = addr_hit[11] & reg_re & !reg_error;
  assign transition_target_we = addr_hit[11] & reg_we & !reg_error;

  assign transition_target_wd = reg_wdata[29:0];

  assign otp_vendor_test_ctrl_re = addr_hit[12] & reg_re & !reg_error;
  assign otp_vendor_test_ctrl_we = addr_hit[12] & reg_we & !reg_error;

  assign otp_vendor_test_ctrl_wd = reg_wdata[31:0];

  assign otp_vendor_test_status_re = addr_hit[13] & reg_re & !reg_error;
  assign lc_state_re = addr_hit[14] & reg_re & !reg_error;
  assign lc_transition_cnt_re = addr_hit[15] & reg_re & !reg_error;
  assign lc_id_state_re = addr_hit[16] & reg_re & !reg_error;
  assign hw_revision0_re = addr_hit[17] & reg_re & !reg_error;
  assign hw_revision1_re = addr_hit[18] & reg_re & !reg_error;
  assign device_id_0_re = addr_hit[19] & reg_re & !reg_error;
  assign device_id_1_re = addr_hit[20] & reg_re & !reg_error;
  assign device_id_2_re = addr_hit[21] & reg_re & !reg_error;
  assign device_id_3_re = addr_hit[22] & reg_re & !reg_error;
  assign device_id_4_re = addr_hit[23] & reg_re & !reg_error;
  assign device_id_5_re = addr_hit[24] & reg_re & !reg_error;
  assign device_id_6_re = addr_hit[25] & reg_re & !reg_error;
  assign device_id_7_re = addr_hit[26] & reg_re & !reg_error;
  assign manuf_state_0_re = addr_hit[27] & reg_re & !reg_error;
  assign manuf_state_1_re = addr_hit[28] & reg_re & !reg_error;
  assign manuf_state_2_re = addr_hit[29] & reg_re & !reg_error;
  assign manuf_state_3_re = addr_hit[30] & reg_re & !reg_error;
  assign manuf_state_4_re = addr_hit[31] & reg_re & !reg_error;
  assign manuf_state_5_re = addr_hit[32] & reg_re & !reg_error;
  assign manuf_state_6_re = addr_hit[33] & reg_re & !reg_error;
  assign manuf_state_7_re = addr_hit[34] & reg_re & !reg_error;

  // Assign write-enables to checker logic vector.
  always_comb begin
    reg_we_check[0] = alert_test_we;
    reg_we_check[1] = 1'b0;
    reg_we_check[2] = claim_transition_if_regwen_we;
    reg_we_check[3] = claim_transition_if_gated_we;
    reg_we_check[4] = 1'b0;
    reg_we_check[5] = transition_cmd_gated_we;
    reg_we_check[6] = transition_ctrl_gated_we;
    reg_we_check[7] = transition_token_0_gated_we;
    reg_we_check[8] = transition_token_1_gated_we;
    reg_we_check[9] = transition_token_2_gated_we;
    reg_we_check[10] = transition_token_3_gated_we;
    reg_we_check[11] = transition_target_gated_we;
    reg_we_check[12] = otp_vendor_test_ctrl_gated_we;
    reg_we_check[13] = 1'b0;
    reg_we_check[14] = 1'b0;
    reg_we_check[15] = 1'b0;
    reg_we_check[16] = 1'b0;
    reg_we_check[17] = 1'b0;
    reg_we_check[18] = 1'b0;
    reg_we_check[19] = 1'b0;
    reg_we_check[20] = 1'b0;
    reg_we_check[21] = 1'b0;
    reg_we_check[22] = 1'b0;
    reg_we_check[23] = 1'b0;
    reg_we_check[24] = 1'b0;
    reg_we_check[25] = 1'b0;
    reg_we_check[26] = 1'b0;
    reg_we_check[27] = 1'b0;
    reg_we_check[28] = 1'b0;
    reg_we_check[29] = 1'b0;
    reg_we_check[30] = 1'b0;
    reg_we_check[31] = 1'b0;
    reg_we_check[32] = 1'b0;
    reg_we_check[33] = 1'b0;
    reg_we_check[34] = 1'b0;
  end

  // Read data return
  always_comb begin
    reg_rdata_next = '0;
    unique case (1'b1)
      addr_hit[0]: begin
        reg_rdata_next[0] = '0;
        reg_rdata_next[1] = '0;
        reg_rdata_next[2] = '0;
      end

      addr_hit[1]: begin
        reg_rdata_next[0] = status_initialized_qs;
        reg_rdata_next[1] = status_ready_qs;
        reg_rdata_next[2] = status_ext_clock_switched_qs;
        reg_rdata_next[3] = status_transition_successful_qs;
        reg_rdata_next[4] = status_transition_count_error_qs;
        reg_rdata_next[5] = status_transition_error_qs;
        reg_rdata_next[6] = status_token_error_qs;
        reg_rdata_next[7] = status_flash_rma_error_qs;
        reg_rdata_next[8] = status_otp_error_qs;
        reg_rdata_next[9] = status_state_error_qs;
        reg_rdata_next[10] = status_bus_integ_error_qs;
        reg_rdata_next[11] = status_otp_partition_error_qs;
      end

      addr_hit[2]: begin
        reg_rdata_next[0] = claim_transition_if_regwen_qs;
      end

      addr_hit[3]: begin
        reg_rdata_next[7:0] = claim_transition_if_qs;
      end

      addr_hit[4]: begin
        reg_rdata_next[0] = transition_regwen_qs;
      end

      addr_hit[5]: begin
        reg_rdata_next[0] = '0;
      end

      addr_hit[6]: begin
        reg_rdata_next[0] = transition_ctrl_ext_clock_en_qs;
        reg_rdata_next[1] = transition_ctrl_volatile_raw_unlock_qs;
      end

      addr_hit[7]: begin
        reg_rdata_next[31:0] = transition_token_0_qs;
      end

      addr_hit[8]: begin
        reg_rdata_next[31:0] = transition_token_1_qs;
      end

      addr_hit[9]: begin
        reg_rdata_next[31:0] = transition_token_2_qs;
      end

      addr_hit[10]: begin
        reg_rdata_next[31:0] = transition_token_3_qs;
      end

      addr_hit[11]: begin
        reg_rdata_next[29:0] = transition_target_qs;
      end

      addr_hit[12]: begin
        reg_rdata_next[31:0] = otp_vendor_test_ctrl_qs;
      end

      addr_hit[13]: begin
        reg_rdata_next[31:0] = otp_vendor_test_status_qs;
      end

      addr_hit[14]: begin
        reg_rdata_next[29:0] = lc_state_qs;
      end

      addr_hit[15]: begin
        reg_rdata_next[4:0] = lc_transition_cnt_qs;
      end

      addr_hit[16]: begin
        reg_rdata_next[31:0] = lc_id_state_qs;
      end

      addr_hit[17]: begin
        reg_rdata_next[15:0] = hw_revision0_product_id_qs;
        reg_rdata_next[31:16] = hw_revision0_silicon_creator_id_qs;
      end

      addr_hit[18]: begin
        reg_rdata_next[7:0] = hw_revision1_revision_id_qs;
        reg_rdata_next[31:8] = hw_revision1_reserved_qs;
      end

      addr_hit[19]: begin
        reg_rdata_next[31:0] = device_id_0_qs;
      end

      addr_hit[20]: begin
        reg_rdata_next[31:0] = device_id_1_qs;
      end

      addr_hit[21]: begin
        reg_rdata_next[31:0] = device_id_2_qs;
      end

      addr_hit[22]: begin
        reg_rdata_next[31:0] = device_id_3_qs;
      end

      addr_hit[23]: begin
        reg_rdata_next[31:0] = device_id_4_qs;
      end

      addr_hit[24]: begin
        reg_rdata_next[31:0] = device_id_5_qs;
      end

      addr_hit[25]: begin
        reg_rdata_next[31:0] = device_id_6_qs;
      end

      addr_hit[26]: begin
        reg_rdata_next[31:0] = device_id_7_qs;
      end

      addr_hit[27]: begin
        reg_rdata_next[31:0] = manuf_state_0_qs;
      end

      addr_hit[28]: begin
        reg_rdata_next[31:0] = manuf_state_1_qs;
      end

      addr_hit[29]: begin
        reg_rdata_next[31:0] = manuf_state_2_qs;
      end

      addr_hit[30]: begin
        reg_rdata_next[31:0] = manuf_state_3_qs;
      end

      addr_hit[31]: begin
        reg_rdata_next[31:0] = manuf_state_4_qs;
      end

      addr_hit[32]: begin
        reg_rdata_next[31:0] = manuf_state_5_qs;
      end

      addr_hit[33]: begin
        reg_rdata_next[31:0] = manuf_state_6_qs;
      end

      addr_hit[34]: begin
        reg_rdata_next[31:0] = manuf_state_7_qs;
      end

      default: begin
        reg_rdata_next = '1;
      end
    endcase
  end

  // shadow busy
  logic shadow_busy;
  assign shadow_busy = 1'b0;

  // register busy
  assign reg_busy = shadow_busy;

  // Unused signal tieoff

  // wdata / byte enable are not always fully used
  // add a blanket unused statement to handle lint waivers
  logic unused_wdata;
  logic unused_be;
  assign unused_wdata = ^reg_wdata;
  assign unused_be = ^reg_be;

  // Assertions for Register Interface
  `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
  `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)

  `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)

  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)

  // this is formulated as an assumption such that the FPV testbenches do disprove this
  // property by mistake
  //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)

endmodule
