// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `rdl2ot`

`include "prim_assert.sv"

module spi_device_reg_top
  # (
    parameter bit          EnableRacl           = 1'b0,
    parameter bit          RaclErrorRsp         = 1'b1,
    parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[spi_device_reg_pkg::NumRegs] =
      '{spi_device_reg_pkg::NumRegs{0}}
  ) (
  input clk_i,
  input rst_ni,
  input  tlul_pkg::tl_h2d_t tl_i,
  output tlul_pkg::tl_d2h_t tl_o,

  // Output port for window
  output tlul_pkg::tl_h2d_t tl_win_o  [2],
  input  tlul_pkg::tl_d2h_t tl_win_i  [2],
  // To HW
  output spi_device_reg_pkg::spi_device_reg2hw_t reg2hw, // Write
  input  spi_device_reg_pkg::spi_device_hw2reg_t hw2reg, // Read

  // RACL interface
  input  top_racl_pkg::racl_policy_vec_t racl_policies_i,
  output top_racl_pkg::racl_error_log_t  racl_error_o,

  // Integrity check errors
  output logic intg_err_o
);

  import spi_device_reg_pkg::* ;

  localparam int AW = 13;
  localparam int DW = 32;
  localparam int DBW = DW/8;                    // Byte Width

  // register signals
  logic           reg_we;
  logic           reg_re;
  logic [AW-1:0]  reg_addr;
  logic [DW-1:0]  reg_wdata;
  logic [DBW-1:0] reg_be;
  logic [DW-1:0]  reg_rdata;
  logic           reg_error;

  logic          addrmiss, wr_err;

  logic [DW-1:0] reg_rdata_next;
  logic reg_busy;

  tlul_pkg::tl_h2d_t tl_reg_h2d;
  tlul_pkg::tl_d2h_t tl_reg_d2h;


  // incoming payload check
  logic intg_err;
  tlul_cmd_intg_chk u_chk (
    .tl_i(tl_i),
    .err_o(intg_err)
  );

  // also check for spurious write enables
  logic reg_we_err;
  logic [72:0] reg_we_check;
  prim_reg_we_check #(
    .OneHotWidth(73)
  ) u_prim_reg_we_check (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .oh_i  (reg_we_check),
    .en_i  (reg_we && !addrmiss),
    .err_o (reg_we_err)
  );

  logic err_q;
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      err_q <= '0;
    end else if (intg_err || reg_we_err) begin
      err_q <= 1'b1;
    end
  end

  // integrity error output is permanent and should be used for alert generation
  // register errors are transactional
  assign intg_err_o = err_q | intg_err | reg_we_err;

  // outgoing integrity generation
  tlul_pkg::tl_d2h_t tl_o_pre;
  tlul_rsp_intg_gen #(
    .EnableRspIntgGen(1),
    .EnableDataIntgGen(1)
  ) u_rsp_intg_gen (
    .tl_i(tl_o_pre),
    .tl_o(tl_o)
  );

  tlul_pkg::tl_h2d_t tl_socket_h2d [3];
  tlul_pkg::tl_d2h_t tl_socket_d2h [3];

  logic [1:0] reg_steer;

  // socket_1n connection
  assign tl_reg_h2d = tl_socket_h2d[2];
  assign tl_socket_d2h[2] = tl_reg_d2h;

  assign tl_win_o[0] = tl_socket_h2d[0];
  assign tl_socket_d2h[0] = tl_win_i[0];
  assign tl_win_o[1] = tl_socket_h2d[1];
  assign tl_socket_d2h[1] = tl_win_i[1];

  // Create Socket_1n
  tlul_socket_1n #(
    .N            (3),
    .HReqPass     (1'b1),
    .HRspPass     (1'b1),
    .DReqPass     ({3{1'b1}}),
    .DRspPass     ({3{1'b1}}),
    .HReqDepth    (4'h0),
    .HRspDepth    (4'h0),
    .DReqDepth    ({3{4'h0}}),
    .DRspDepth    ({3{4'h0}}),
    .ExplicitErrs (1'b0)
  ) u_socket (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),
    .tl_h_i (tl_i),
    .tl_h_o (tl_o_pre),
    .tl_d_o (tl_socket_h2d),
    .tl_d_i (tl_socket_d2h),
    .dev_select_i (reg_steer)
  );

  // Create steering logic
  always_comb begin
    reg_steer =
        tl_i.a_address[AW-1:0] inside {[4096:7487]} ? 2'd0 :
        tl_i.a_address[AW-1:0] inside {[7680:8127]} ? 2'd1 :
        // Default set to register
        2'd2;

    // Override this in case of an integrity error
    if (intg_err) begin
      reg_steer = 2'd2;
    end
  end

  tlul_adapter_reg #(
    .RegAw(AW),
    .RegDw(DW),
    .EnableDataIntgGen(0)
  ) u_reg_if (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),

    .tl_i (tl_reg_h2d),
    .tl_o (tl_reg_d2h),

    .en_ifetch_i(prim_mubi_pkg::MuBi4False),
    .intg_error_o(),

    .we_o    (reg_we),
    .re_o    (reg_re),
    .addr_o  (reg_addr),
    .wdata_o (reg_wdata),
    .be_o    (reg_be),
    .busy_i  (reg_busy),
    .rdata_i (reg_rdata),
    // Translate RACL error to TLUL error if enabled
    .error_i (reg_error | (RaclErrorRsp & racl_error_o.valid))
  );

  // cdc oversampling signals

  assign reg_rdata = reg_rdata_next ;
  assign reg_error = addrmiss | wr_err | intg_err;

  // Define SW related signals
  // Format: <reg>_<field>_{wd|we|qs}
  //        or <reg>_{wd|we|qs} if field == 1 or 0
  logic intr_state_we;
  logic intr_state_upload_cmdfifo_not_empty_qs;
  logic intr_state_upload_cmdfifo_not_empty_wd;
  logic intr_state_upload_payload_not_empty_qs;
  logic intr_state_upload_payload_not_empty_wd;
  logic intr_state_upload_payload_overflow_qs;
  logic intr_state_upload_payload_overflow_wd;
  logic intr_state_readbuf_watermark_qs;
  logic intr_state_readbuf_watermark_wd;
  logic intr_state_readbuf_flip_qs;
  logic intr_state_readbuf_flip_wd;
  logic intr_state_tpm_header_not_empty_qs;
  logic intr_state_tpm_rdfifo_cmd_end_qs;
  logic intr_state_tpm_rdfifo_cmd_end_wd;
  logic intr_state_tpm_rdfifo_drop_qs;
  logic intr_state_tpm_rdfifo_drop_wd;
  logic intr_enable_we;
  logic intr_enable_upload_cmdfifo_not_empty_qs;
  logic intr_enable_upload_cmdfifo_not_empty_wd;
  logic intr_enable_upload_payload_not_empty_qs;
  logic intr_enable_upload_payload_not_empty_wd;
  logic intr_enable_upload_payload_overflow_qs;
  logic intr_enable_upload_payload_overflow_wd;
  logic intr_enable_readbuf_watermark_qs;
  logic intr_enable_readbuf_watermark_wd;
  logic intr_enable_readbuf_flip_qs;
  logic intr_enable_readbuf_flip_wd;
  logic intr_enable_tpm_header_not_empty_qs;
  logic intr_enable_tpm_header_not_empty_wd;
  logic intr_enable_tpm_rdfifo_cmd_end_qs;
  logic intr_enable_tpm_rdfifo_cmd_end_wd;
  logic intr_enable_tpm_rdfifo_drop_qs;
  logic intr_enable_tpm_rdfifo_drop_wd;
  logic intr_test_we;
  logic intr_test_upload_cmdfifo_not_empty_wd;
  logic intr_test_upload_payload_not_empty_wd;
  logic intr_test_upload_payload_overflow_wd;
  logic intr_test_readbuf_watermark_wd;
  logic intr_test_readbuf_flip_wd;
  logic intr_test_tpm_header_not_empty_wd;
  logic intr_test_tpm_rdfifo_cmd_end_wd;
  logic intr_test_tpm_rdfifo_drop_wd;
  logic alert_test_we;
  logic alert_test_wd;
  logic control_we;
  logic control_flash_status_fifo_clr_qs;
  logic control_flash_status_fifo_clr_wd;
  logic control_flash_read_buffer_clr_qs;
  logic control_flash_read_buffer_clr_wd;
  logic [1:0] control_mode_qs;
  logic [1:0] control_mode_wd;
  logic cfg_we;
  logic cfg_tx_order_qs;
  logic cfg_tx_order_wd;
  logic cfg_rx_order_qs;
  logic cfg_rx_order_wd;
  logic cfg_mailbox_en_qs;
  logic cfg_mailbox_en_wd;
  logic status_re;
  logic status_csb_qs;
  logic status_tpm_csb_qs;
  logic intercept_en_we;
  logic intercept_en_status_qs;
  logic intercept_en_status_wd;
  logic intercept_en_jedec_qs;
  logic intercept_en_jedec_wd;
  logic intercept_en_sfdp_qs;
  logic intercept_en_sfdp_wd;
  logic intercept_en_mbx_qs;
  logic intercept_en_mbx_wd;
  logic addr_mode_re;
  logic addr_mode_we;
  logic addr_mode_addr_4b_en_qs;
  logic addr_mode_addr_4b_en_wd;
  logic addr_mode_pending_qs;
  logic last_read_addr_re;
  logic [31:0] last_read_addr_qs;
  logic flash_status_re;
  logic flash_status_we;
  logic flash_status_busy_qs;
  logic flash_status_busy_wd;
  logic flash_status_wel_qs;
  logic flash_status_wel_wd;
  logic [21:0] flash_status_status_qs;
  logic [21:0] flash_status_status_wd;
  logic jedec_cc_we;
  logic [7:0] jedec_cc_cc_qs;
  logic [7:0] jedec_cc_cc_wd;
  logic [7:0] jedec_cc_num_cc_qs;
  logic [7:0] jedec_cc_num_cc_wd;
  logic jedec_id_we;
  logic [15:0] jedec_id_id_qs;
  logic [15:0] jedec_id_id_wd;
  logic [7:0] jedec_id_mf_qs;
  logic [7:0] jedec_id_mf_wd;
  logic read_threshold_we;
  logic [9:0] read_threshold_qs;
  logic [9:0] read_threshold_wd;
  logic mailbox_addr_we;
  logic [31:0] mailbox_addr_qs;
  logic [31:0] mailbox_addr_wd;
  logic [4:0] upload_status_cmdfifo_depth_qs;
  logic upload_status_cmdfifo_notempty_qs;
  logic [4:0] upload_status_addrfifo_depth_qs;
  logic upload_status_addrfifo_notempty_qs;
  logic [8:0] upload_status2_payload_depth_qs;
  logic [7:0] upload_status2_payload_start_idx_qs;
  logic upload_cmdfifo_re;
  logic [7:0] upload_cmdfifo_data_qs;
  logic upload_cmdfifo_busy_qs;
  logic upload_cmdfifo_wel_qs;
  logic upload_cmdfifo_addr4b_mode_qs;
  logic upload_addrfifo_re;
  logic [31:0] upload_addrfifo_qs;
  logic cmd_filter_0_we;
  logic cmd_filter_0_filter_0_qs;
  logic cmd_filter_0_filter_0_wd;
  logic cmd_filter_0_filter_1_qs;
  logic cmd_filter_0_filter_1_wd;
  logic cmd_filter_0_filter_2_qs;
  logic cmd_filter_0_filter_2_wd;
  logic cmd_filter_0_filter_3_qs;
  logic cmd_filter_0_filter_3_wd;
  logic cmd_filter_0_filter_4_qs;
  logic cmd_filter_0_filter_4_wd;
  logic cmd_filter_0_filter_5_qs;
  logic cmd_filter_0_filter_5_wd;
  logic cmd_filter_0_filter_6_qs;
  logic cmd_filter_0_filter_6_wd;
  logic cmd_filter_0_filter_7_qs;
  logic cmd_filter_0_filter_7_wd;
  logic cmd_filter_0_filter_8_qs;
  logic cmd_filter_0_filter_8_wd;
  logic cmd_filter_0_filter_9_qs;
  logic cmd_filter_0_filter_9_wd;
  logic cmd_filter_0_filter_10_qs;
  logic cmd_filter_0_filter_10_wd;
  logic cmd_filter_0_filter_11_qs;
  logic cmd_filter_0_filter_11_wd;
  logic cmd_filter_0_filter_12_qs;
  logic cmd_filter_0_filter_12_wd;
  logic cmd_filter_0_filter_13_qs;
  logic cmd_filter_0_filter_13_wd;
  logic cmd_filter_0_filter_14_qs;
  logic cmd_filter_0_filter_14_wd;
  logic cmd_filter_0_filter_15_qs;
  logic cmd_filter_0_filter_15_wd;
  logic cmd_filter_0_filter_16_qs;
  logic cmd_filter_0_filter_16_wd;
  logic cmd_filter_0_filter_17_qs;
  logic cmd_filter_0_filter_17_wd;
  logic cmd_filter_0_filter_18_qs;
  logic cmd_filter_0_filter_18_wd;
  logic cmd_filter_0_filter_19_qs;
  logic cmd_filter_0_filter_19_wd;
  logic cmd_filter_0_filter_20_qs;
  logic cmd_filter_0_filter_20_wd;
  logic cmd_filter_0_filter_21_qs;
  logic cmd_filter_0_filter_21_wd;
  logic cmd_filter_0_filter_22_qs;
  logic cmd_filter_0_filter_22_wd;
  logic cmd_filter_0_filter_23_qs;
  logic cmd_filter_0_filter_23_wd;
  logic cmd_filter_0_filter_24_qs;
  logic cmd_filter_0_filter_24_wd;
  logic cmd_filter_0_filter_25_qs;
  logic cmd_filter_0_filter_25_wd;
  logic cmd_filter_0_filter_26_qs;
  logic cmd_filter_0_filter_26_wd;
  logic cmd_filter_0_filter_27_qs;
  logic cmd_filter_0_filter_27_wd;
  logic cmd_filter_0_filter_28_qs;
  logic cmd_filter_0_filter_28_wd;
  logic cmd_filter_0_filter_29_qs;
  logic cmd_filter_0_filter_29_wd;
  logic cmd_filter_0_filter_30_qs;
  logic cmd_filter_0_filter_30_wd;
  logic cmd_filter_0_filter_31_qs;
  logic cmd_filter_0_filter_31_wd;
  logic cmd_filter_1_we;
  logic cmd_filter_1_filter_32_qs;
  logic cmd_filter_1_filter_32_wd;
  logic cmd_filter_1_filter_33_qs;
  logic cmd_filter_1_filter_33_wd;
  logic cmd_filter_1_filter_34_qs;
  logic cmd_filter_1_filter_34_wd;
  logic cmd_filter_1_filter_35_qs;
  logic cmd_filter_1_filter_35_wd;
  logic cmd_filter_1_filter_36_qs;
  logic cmd_filter_1_filter_36_wd;
  logic cmd_filter_1_filter_37_qs;
  logic cmd_filter_1_filter_37_wd;
  logic cmd_filter_1_filter_38_qs;
  logic cmd_filter_1_filter_38_wd;
  logic cmd_filter_1_filter_39_qs;
  logic cmd_filter_1_filter_39_wd;
  logic cmd_filter_1_filter_40_qs;
  logic cmd_filter_1_filter_40_wd;
  logic cmd_filter_1_filter_41_qs;
  logic cmd_filter_1_filter_41_wd;
  logic cmd_filter_1_filter_42_qs;
  logic cmd_filter_1_filter_42_wd;
  logic cmd_filter_1_filter_43_qs;
  logic cmd_filter_1_filter_43_wd;
  logic cmd_filter_1_filter_44_qs;
  logic cmd_filter_1_filter_44_wd;
  logic cmd_filter_1_filter_45_qs;
  logic cmd_filter_1_filter_45_wd;
  logic cmd_filter_1_filter_46_qs;
  logic cmd_filter_1_filter_46_wd;
  logic cmd_filter_1_filter_47_qs;
  logic cmd_filter_1_filter_47_wd;
  logic cmd_filter_1_filter_48_qs;
  logic cmd_filter_1_filter_48_wd;
  logic cmd_filter_1_filter_49_qs;
  logic cmd_filter_1_filter_49_wd;
  logic cmd_filter_1_filter_50_qs;
  logic cmd_filter_1_filter_50_wd;
  logic cmd_filter_1_filter_51_qs;
  logic cmd_filter_1_filter_51_wd;
  logic cmd_filter_1_filter_52_qs;
  logic cmd_filter_1_filter_52_wd;
  logic cmd_filter_1_filter_53_qs;
  logic cmd_filter_1_filter_53_wd;
  logic cmd_filter_1_filter_54_qs;
  logic cmd_filter_1_filter_54_wd;
  logic cmd_filter_1_filter_55_qs;
  logic cmd_filter_1_filter_55_wd;
  logic cmd_filter_1_filter_56_qs;
  logic cmd_filter_1_filter_56_wd;
  logic cmd_filter_1_filter_57_qs;
  logic cmd_filter_1_filter_57_wd;
  logic cmd_filter_1_filter_58_qs;
  logic cmd_filter_1_filter_58_wd;
  logic cmd_filter_1_filter_59_qs;
  logic cmd_filter_1_filter_59_wd;
  logic cmd_filter_1_filter_60_qs;
  logic cmd_filter_1_filter_60_wd;
  logic cmd_filter_1_filter_61_qs;
  logic cmd_filter_1_filter_61_wd;
  logic cmd_filter_1_filter_62_qs;
  logic cmd_filter_1_filter_62_wd;
  logic cmd_filter_1_filter_63_qs;
  logic cmd_filter_1_filter_63_wd;
  logic cmd_filter_2_we;
  logic cmd_filter_2_filter_64_qs;
  logic cmd_filter_2_filter_64_wd;
  logic cmd_filter_2_filter_65_qs;
  logic cmd_filter_2_filter_65_wd;
  logic cmd_filter_2_filter_66_qs;
  logic cmd_filter_2_filter_66_wd;
  logic cmd_filter_2_filter_67_qs;
  logic cmd_filter_2_filter_67_wd;
  logic cmd_filter_2_filter_68_qs;
  logic cmd_filter_2_filter_68_wd;
  logic cmd_filter_2_filter_69_qs;
  logic cmd_filter_2_filter_69_wd;
  logic cmd_filter_2_filter_70_qs;
  logic cmd_filter_2_filter_70_wd;
  logic cmd_filter_2_filter_71_qs;
  logic cmd_filter_2_filter_71_wd;
  logic cmd_filter_2_filter_72_qs;
  logic cmd_filter_2_filter_72_wd;
  logic cmd_filter_2_filter_73_qs;
  logic cmd_filter_2_filter_73_wd;
  logic cmd_filter_2_filter_74_qs;
  logic cmd_filter_2_filter_74_wd;
  logic cmd_filter_2_filter_75_qs;
  logic cmd_filter_2_filter_75_wd;
  logic cmd_filter_2_filter_76_qs;
  logic cmd_filter_2_filter_76_wd;
  logic cmd_filter_2_filter_77_qs;
  logic cmd_filter_2_filter_77_wd;
  logic cmd_filter_2_filter_78_qs;
  logic cmd_filter_2_filter_78_wd;
  logic cmd_filter_2_filter_79_qs;
  logic cmd_filter_2_filter_79_wd;
  logic cmd_filter_2_filter_80_qs;
  logic cmd_filter_2_filter_80_wd;
  logic cmd_filter_2_filter_81_qs;
  logic cmd_filter_2_filter_81_wd;
  logic cmd_filter_2_filter_82_qs;
  logic cmd_filter_2_filter_82_wd;
  logic cmd_filter_2_filter_83_qs;
  logic cmd_filter_2_filter_83_wd;
  logic cmd_filter_2_filter_84_qs;
  logic cmd_filter_2_filter_84_wd;
  logic cmd_filter_2_filter_85_qs;
  logic cmd_filter_2_filter_85_wd;
  logic cmd_filter_2_filter_86_qs;
  logic cmd_filter_2_filter_86_wd;
  logic cmd_filter_2_filter_87_qs;
  logic cmd_filter_2_filter_87_wd;
  logic cmd_filter_2_filter_88_qs;
  logic cmd_filter_2_filter_88_wd;
  logic cmd_filter_2_filter_89_qs;
  logic cmd_filter_2_filter_89_wd;
  logic cmd_filter_2_filter_90_qs;
  logic cmd_filter_2_filter_90_wd;
  logic cmd_filter_2_filter_91_qs;
  logic cmd_filter_2_filter_91_wd;
  logic cmd_filter_2_filter_92_qs;
  logic cmd_filter_2_filter_92_wd;
  logic cmd_filter_2_filter_93_qs;
  logic cmd_filter_2_filter_93_wd;
  logic cmd_filter_2_filter_94_qs;
  logic cmd_filter_2_filter_94_wd;
  logic cmd_filter_2_filter_95_qs;
  logic cmd_filter_2_filter_95_wd;
  logic cmd_filter_3_we;
  logic cmd_filter_3_filter_96_qs;
  logic cmd_filter_3_filter_96_wd;
  logic cmd_filter_3_filter_97_qs;
  logic cmd_filter_3_filter_97_wd;
  logic cmd_filter_3_filter_98_qs;
  logic cmd_filter_3_filter_98_wd;
  logic cmd_filter_3_filter_99_qs;
  logic cmd_filter_3_filter_99_wd;
  logic cmd_filter_3_filter_100_qs;
  logic cmd_filter_3_filter_100_wd;
  logic cmd_filter_3_filter_101_qs;
  logic cmd_filter_3_filter_101_wd;
  logic cmd_filter_3_filter_102_qs;
  logic cmd_filter_3_filter_102_wd;
  logic cmd_filter_3_filter_103_qs;
  logic cmd_filter_3_filter_103_wd;
  logic cmd_filter_3_filter_104_qs;
  logic cmd_filter_3_filter_104_wd;
  logic cmd_filter_3_filter_105_qs;
  logic cmd_filter_3_filter_105_wd;
  logic cmd_filter_3_filter_106_qs;
  logic cmd_filter_3_filter_106_wd;
  logic cmd_filter_3_filter_107_qs;
  logic cmd_filter_3_filter_107_wd;
  logic cmd_filter_3_filter_108_qs;
  logic cmd_filter_3_filter_108_wd;
  logic cmd_filter_3_filter_109_qs;
  logic cmd_filter_3_filter_109_wd;
  logic cmd_filter_3_filter_110_qs;
  logic cmd_filter_3_filter_110_wd;
  logic cmd_filter_3_filter_111_qs;
  logic cmd_filter_3_filter_111_wd;
  logic cmd_filter_3_filter_112_qs;
  logic cmd_filter_3_filter_112_wd;
  logic cmd_filter_3_filter_113_qs;
  logic cmd_filter_3_filter_113_wd;
  logic cmd_filter_3_filter_114_qs;
  logic cmd_filter_3_filter_114_wd;
  logic cmd_filter_3_filter_115_qs;
  logic cmd_filter_3_filter_115_wd;
  logic cmd_filter_3_filter_116_qs;
  logic cmd_filter_3_filter_116_wd;
  logic cmd_filter_3_filter_117_qs;
  logic cmd_filter_3_filter_117_wd;
  logic cmd_filter_3_filter_118_qs;
  logic cmd_filter_3_filter_118_wd;
  logic cmd_filter_3_filter_119_qs;
  logic cmd_filter_3_filter_119_wd;
  logic cmd_filter_3_filter_120_qs;
  logic cmd_filter_3_filter_120_wd;
  logic cmd_filter_3_filter_121_qs;
  logic cmd_filter_3_filter_121_wd;
  logic cmd_filter_3_filter_122_qs;
  logic cmd_filter_3_filter_122_wd;
  logic cmd_filter_3_filter_123_qs;
  logic cmd_filter_3_filter_123_wd;
  logic cmd_filter_3_filter_124_qs;
  logic cmd_filter_3_filter_124_wd;
  logic cmd_filter_3_filter_125_qs;
  logic cmd_filter_3_filter_125_wd;
  logic cmd_filter_3_filter_126_qs;
  logic cmd_filter_3_filter_126_wd;
  logic cmd_filter_3_filter_127_qs;
  logic cmd_filter_3_filter_127_wd;
  logic cmd_filter_4_we;
  logic cmd_filter_4_filter_128_qs;
  logic cmd_filter_4_filter_128_wd;
  logic cmd_filter_4_filter_129_qs;
  logic cmd_filter_4_filter_129_wd;
  logic cmd_filter_4_filter_130_qs;
  logic cmd_filter_4_filter_130_wd;
  logic cmd_filter_4_filter_131_qs;
  logic cmd_filter_4_filter_131_wd;
  logic cmd_filter_4_filter_132_qs;
  logic cmd_filter_4_filter_132_wd;
  logic cmd_filter_4_filter_133_qs;
  logic cmd_filter_4_filter_133_wd;
  logic cmd_filter_4_filter_134_qs;
  logic cmd_filter_4_filter_134_wd;
  logic cmd_filter_4_filter_135_qs;
  logic cmd_filter_4_filter_135_wd;
  logic cmd_filter_4_filter_136_qs;
  logic cmd_filter_4_filter_136_wd;
  logic cmd_filter_4_filter_137_qs;
  logic cmd_filter_4_filter_137_wd;
  logic cmd_filter_4_filter_138_qs;
  logic cmd_filter_4_filter_138_wd;
  logic cmd_filter_4_filter_139_qs;
  logic cmd_filter_4_filter_139_wd;
  logic cmd_filter_4_filter_140_qs;
  logic cmd_filter_4_filter_140_wd;
  logic cmd_filter_4_filter_141_qs;
  logic cmd_filter_4_filter_141_wd;
  logic cmd_filter_4_filter_142_qs;
  logic cmd_filter_4_filter_142_wd;
  logic cmd_filter_4_filter_143_qs;
  logic cmd_filter_4_filter_143_wd;
  logic cmd_filter_4_filter_144_qs;
  logic cmd_filter_4_filter_144_wd;
  logic cmd_filter_4_filter_145_qs;
  logic cmd_filter_4_filter_145_wd;
  logic cmd_filter_4_filter_146_qs;
  logic cmd_filter_4_filter_146_wd;
  logic cmd_filter_4_filter_147_qs;
  logic cmd_filter_4_filter_147_wd;
  logic cmd_filter_4_filter_148_qs;
  logic cmd_filter_4_filter_148_wd;
  logic cmd_filter_4_filter_149_qs;
  logic cmd_filter_4_filter_149_wd;
  logic cmd_filter_4_filter_150_qs;
  logic cmd_filter_4_filter_150_wd;
  logic cmd_filter_4_filter_151_qs;
  logic cmd_filter_4_filter_151_wd;
  logic cmd_filter_4_filter_152_qs;
  logic cmd_filter_4_filter_152_wd;
  logic cmd_filter_4_filter_153_qs;
  logic cmd_filter_4_filter_153_wd;
  logic cmd_filter_4_filter_154_qs;
  logic cmd_filter_4_filter_154_wd;
  logic cmd_filter_4_filter_155_qs;
  logic cmd_filter_4_filter_155_wd;
  logic cmd_filter_4_filter_156_qs;
  logic cmd_filter_4_filter_156_wd;
  logic cmd_filter_4_filter_157_qs;
  logic cmd_filter_4_filter_157_wd;
  logic cmd_filter_4_filter_158_qs;
  logic cmd_filter_4_filter_158_wd;
  logic cmd_filter_4_filter_159_qs;
  logic cmd_filter_4_filter_159_wd;
  logic cmd_filter_5_we;
  logic cmd_filter_5_filter_160_qs;
  logic cmd_filter_5_filter_160_wd;
  logic cmd_filter_5_filter_161_qs;
  logic cmd_filter_5_filter_161_wd;
  logic cmd_filter_5_filter_162_qs;
  logic cmd_filter_5_filter_162_wd;
  logic cmd_filter_5_filter_163_qs;
  logic cmd_filter_5_filter_163_wd;
  logic cmd_filter_5_filter_164_qs;
  logic cmd_filter_5_filter_164_wd;
  logic cmd_filter_5_filter_165_qs;
  logic cmd_filter_5_filter_165_wd;
  logic cmd_filter_5_filter_166_qs;
  logic cmd_filter_5_filter_166_wd;
  logic cmd_filter_5_filter_167_qs;
  logic cmd_filter_5_filter_167_wd;
  logic cmd_filter_5_filter_168_qs;
  logic cmd_filter_5_filter_168_wd;
  logic cmd_filter_5_filter_169_qs;
  logic cmd_filter_5_filter_169_wd;
  logic cmd_filter_5_filter_170_qs;
  logic cmd_filter_5_filter_170_wd;
  logic cmd_filter_5_filter_171_qs;
  logic cmd_filter_5_filter_171_wd;
  logic cmd_filter_5_filter_172_qs;
  logic cmd_filter_5_filter_172_wd;
  logic cmd_filter_5_filter_173_qs;
  logic cmd_filter_5_filter_173_wd;
  logic cmd_filter_5_filter_174_qs;
  logic cmd_filter_5_filter_174_wd;
  logic cmd_filter_5_filter_175_qs;
  logic cmd_filter_5_filter_175_wd;
  logic cmd_filter_5_filter_176_qs;
  logic cmd_filter_5_filter_176_wd;
  logic cmd_filter_5_filter_177_qs;
  logic cmd_filter_5_filter_177_wd;
  logic cmd_filter_5_filter_178_qs;
  logic cmd_filter_5_filter_178_wd;
  logic cmd_filter_5_filter_179_qs;
  logic cmd_filter_5_filter_179_wd;
  logic cmd_filter_5_filter_180_qs;
  logic cmd_filter_5_filter_180_wd;
  logic cmd_filter_5_filter_181_qs;
  logic cmd_filter_5_filter_181_wd;
  logic cmd_filter_5_filter_182_qs;
  logic cmd_filter_5_filter_182_wd;
  logic cmd_filter_5_filter_183_qs;
  logic cmd_filter_5_filter_183_wd;
  logic cmd_filter_5_filter_184_qs;
  logic cmd_filter_5_filter_184_wd;
  logic cmd_filter_5_filter_185_qs;
  logic cmd_filter_5_filter_185_wd;
  logic cmd_filter_5_filter_186_qs;
  logic cmd_filter_5_filter_186_wd;
  logic cmd_filter_5_filter_187_qs;
  logic cmd_filter_5_filter_187_wd;
  logic cmd_filter_5_filter_188_qs;
  logic cmd_filter_5_filter_188_wd;
  logic cmd_filter_5_filter_189_qs;
  logic cmd_filter_5_filter_189_wd;
  logic cmd_filter_5_filter_190_qs;
  logic cmd_filter_5_filter_190_wd;
  logic cmd_filter_5_filter_191_qs;
  logic cmd_filter_5_filter_191_wd;
  logic cmd_filter_6_we;
  logic cmd_filter_6_filter_192_qs;
  logic cmd_filter_6_filter_192_wd;
  logic cmd_filter_6_filter_193_qs;
  logic cmd_filter_6_filter_193_wd;
  logic cmd_filter_6_filter_194_qs;
  logic cmd_filter_6_filter_194_wd;
  logic cmd_filter_6_filter_195_qs;
  logic cmd_filter_6_filter_195_wd;
  logic cmd_filter_6_filter_196_qs;
  logic cmd_filter_6_filter_196_wd;
  logic cmd_filter_6_filter_197_qs;
  logic cmd_filter_6_filter_197_wd;
  logic cmd_filter_6_filter_198_qs;
  logic cmd_filter_6_filter_198_wd;
  logic cmd_filter_6_filter_199_qs;
  logic cmd_filter_6_filter_199_wd;
  logic cmd_filter_6_filter_200_qs;
  logic cmd_filter_6_filter_200_wd;
  logic cmd_filter_6_filter_201_qs;
  logic cmd_filter_6_filter_201_wd;
  logic cmd_filter_6_filter_202_qs;
  logic cmd_filter_6_filter_202_wd;
  logic cmd_filter_6_filter_203_qs;
  logic cmd_filter_6_filter_203_wd;
  logic cmd_filter_6_filter_204_qs;
  logic cmd_filter_6_filter_204_wd;
  logic cmd_filter_6_filter_205_qs;
  logic cmd_filter_6_filter_205_wd;
  logic cmd_filter_6_filter_206_qs;
  logic cmd_filter_6_filter_206_wd;
  logic cmd_filter_6_filter_207_qs;
  logic cmd_filter_6_filter_207_wd;
  logic cmd_filter_6_filter_208_qs;
  logic cmd_filter_6_filter_208_wd;
  logic cmd_filter_6_filter_209_qs;
  logic cmd_filter_6_filter_209_wd;
  logic cmd_filter_6_filter_210_qs;
  logic cmd_filter_6_filter_210_wd;
  logic cmd_filter_6_filter_211_qs;
  logic cmd_filter_6_filter_211_wd;
  logic cmd_filter_6_filter_212_qs;
  logic cmd_filter_6_filter_212_wd;
  logic cmd_filter_6_filter_213_qs;
  logic cmd_filter_6_filter_213_wd;
  logic cmd_filter_6_filter_214_qs;
  logic cmd_filter_6_filter_214_wd;
  logic cmd_filter_6_filter_215_qs;
  logic cmd_filter_6_filter_215_wd;
  logic cmd_filter_6_filter_216_qs;
  logic cmd_filter_6_filter_216_wd;
  logic cmd_filter_6_filter_217_qs;
  logic cmd_filter_6_filter_217_wd;
  logic cmd_filter_6_filter_218_qs;
  logic cmd_filter_6_filter_218_wd;
  logic cmd_filter_6_filter_219_qs;
  logic cmd_filter_6_filter_219_wd;
  logic cmd_filter_6_filter_220_qs;
  logic cmd_filter_6_filter_220_wd;
  logic cmd_filter_6_filter_221_qs;
  logic cmd_filter_6_filter_221_wd;
  logic cmd_filter_6_filter_222_qs;
  logic cmd_filter_6_filter_222_wd;
  logic cmd_filter_6_filter_223_qs;
  logic cmd_filter_6_filter_223_wd;
  logic cmd_filter_7_we;
  logic cmd_filter_7_filter_224_qs;
  logic cmd_filter_7_filter_224_wd;
  logic cmd_filter_7_filter_225_qs;
  logic cmd_filter_7_filter_225_wd;
  logic cmd_filter_7_filter_226_qs;
  logic cmd_filter_7_filter_226_wd;
  logic cmd_filter_7_filter_227_qs;
  logic cmd_filter_7_filter_227_wd;
  logic cmd_filter_7_filter_228_qs;
  logic cmd_filter_7_filter_228_wd;
  logic cmd_filter_7_filter_229_qs;
  logic cmd_filter_7_filter_229_wd;
  logic cmd_filter_7_filter_230_qs;
  logic cmd_filter_7_filter_230_wd;
  logic cmd_filter_7_filter_231_qs;
  logic cmd_filter_7_filter_231_wd;
  logic cmd_filter_7_filter_232_qs;
  logic cmd_filter_7_filter_232_wd;
  logic cmd_filter_7_filter_233_qs;
  logic cmd_filter_7_filter_233_wd;
  logic cmd_filter_7_filter_234_qs;
  logic cmd_filter_7_filter_234_wd;
  logic cmd_filter_7_filter_235_qs;
  logic cmd_filter_7_filter_235_wd;
  logic cmd_filter_7_filter_236_qs;
  logic cmd_filter_7_filter_236_wd;
  logic cmd_filter_7_filter_237_qs;
  logic cmd_filter_7_filter_237_wd;
  logic cmd_filter_7_filter_238_qs;
  logic cmd_filter_7_filter_238_wd;
  logic cmd_filter_7_filter_239_qs;
  logic cmd_filter_7_filter_239_wd;
  logic cmd_filter_7_filter_240_qs;
  logic cmd_filter_7_filter_240_wd;
  logic cmd_filter_7_filter_241_qs;
  logic cmd_filter_7_filter_241_wd;
  logic cmd_filter_7_filter_242_qs;
  logic cmd_filter_7_filter_242_wd;
  logic cmd_filter_7_filter_243_qs;
  logic cmd_filter_7_filter_243_wd;
  logic cmd_filter_7_filter_244_qs;
  logic cmd_filter_7_filter_244_wd;
  logic cmd_filter_7_filter_245_qs;
  logic cmd_filter_7_filter_245_wd;
  logic cmd_filter_7_filter_246_qs;
  logic cmd_filter_7_filter_246_wd;
  logic cmd_filter_7_filter_247_qs;
  logic cmd_filter_7_filter_247_wd;
  logic cmd_filter_7_filter_248_qs;
  logic cmd_filter_7_filter_248_wd;
  logic cmd_filter_7_filter_249_qs;
  logic cmd_filter_7_filter_249_wd;
  logic cmd_filter_7_filter_250_qs;
  logic cmd_filter_7_filter_250_wd;
  logic cmd_filter_7_filter_251_qs;
  logic cmd_filter_7_filter_251_wd;
  logic cmd_filter_7_filter_252_qs;
  logic cmd_filter_7_filter_252_wd;
  logic cmd_filter_7_filter_253_qs;
  logic cmd_filter_7_filter_253_wd;
  logic cmd_filter_7_filter_254_qs;
  logic cmd_filter_7_filter_254_wd;
  logic cmd_filter_7_filter_255_qs;
  logic cmd_filter_7_filter_255_wd;
  logic addr_swap_mask_we;
  logic [31:0] addr_swap_mask_qs;
  logic [31:0] addr_swap_mask_wd;
  logic addr_swap_data_we;
  logic [31:0] addr_swap_data_qs;
  logic [31:0] addr_swap_data_wd;
  logic payload_swap_mask_we;
  logic [31:0] payload_swap_mask_qs;
  logic [31:0] payload_swap_mask_wd;
  logic payload_swap_data_we;
  logic [31:0] payload_swap_data_qs;
  logic [31:0] payload_swap_data_wd;
  logic cmd_info_0_we;
  logic [7:0] cmd_info_0_opcode_0_qs;
  logic [7:0] cmd_info_0_opcode_0_wd;
  logic [1:0] cmd_info_0_addr_mode_0_qs;
  logic [1:0] cmd_info_0_addr_mode_0_wd;
  logic cmd_info_0_addr_swap_en_0_qs;
  logic cmd_info_0_addr_swap_en_0_wd;
  logic cmd_info_0_mbyte_en_0_qs;
  logic cmd_info_0_mbyte_en_0_wd;
  logic [2:0] cmd_info_0_dummy_size_0_qs;
  logic [2:0] cmd_info_0_dummy_size_0_wd;
  logic cmd_info_0_dummy_en_0_qs;
  logic cmd_info_0_dummy_en_0_wd;
  logic [3:0] cmd_info_0_payload_en_0_qs;
  logic [3:0] cmd_info_0_payload_en_0_wd;
  logic cmd_info_0_payload_dir_0_qs;
  logic cmd_info_0_payload_dir_0_wd;
  logic cmd_info_0_payload_swap_en_0_qs;
  logic cmd_info_0_payload_swap_en_0_wd;
  logic [1:0] cmd_info_0_read_pipeline_mode_0_qs;
  logic [1:0] cmd_info_0_read_pipeline_mode_0_wd;
  logic cmd_info_0_upload_0_qs;
  logic cmd_info_0_upload_0_wd;
  logic cmd_info_0_busy_0_qs;
  logic cmd_info_0_busy_0_wd;
  logic cmd_info_0_valid_0_qs;
  logic cmd_info_0_valid_0_wd;
  logic cmd_info_1_we;
  logic [7:0] cmd_info_1_opcode_1_qs;
  logic [7:0] cmd_info_1_opcode_1_wd;
  logic [1:0] cmd_info_1_addr_mode_1_qs;
  logic [1:0] cmd_info_1_addr_mode_1_wd;
  logic cmd_info_1_addr_swap_en_1_qs;
  logic cmd_info_1_addr_swap_en_1_wd;
  logic cmd_info_1_mbyte_en_1_qs;
  logic cmd_info_1_mbyte_en_1_wd;
  logic [2:0] cmd_info_1_dummy_size_1_qs;
  logic [2:0] cmd_info_1_dummy_size_1_wd;
  logic cmd_info_1_dummy_en_1_qs;
  logic cmd_info_1_dummy_en_1_wd;
  logic [3:0] cmd_info_1_payload_en_1_qs;
  logic [3:0] cmd_info_1_payload_en_1_wd;
  logic cmd_info_1_payload_dir_1_qs;
  logic cmd_info_1_payload_dir_1_wd;
  logic cmd_info_1_payload_swap_en_1_qs;
  logic cmd_info_1_payload_swap_en_1_wd;
  logic [1:0] cmd_info_1_read_pipeline_mode_1_qs;
  logic [1:0] cmd_info_1_read_pipeline_mode_1_wd;
  logic cmd_info_1_upload_1_qs;
  logic cmd_info_1_upload_1_wd;
  logic cmd_info_1_busy_1_qs;
  logic cmd_info_1_busy_1_wd;
  logic cmd_info_1_valid_1_qs;
  logic cmd_info_1_valid_1_wd;
  logic cmd_info_2_we;
  logic [7:0] cmd_info_2_opcode_2_qs;
  logic [7:0] cmd_info_2_opcode_2_wd;
  logic [1:0] cmd_info_2_addr_mode_2_qs;
  logic [1:0] cmd_info_2_addr_mode_2_wd;
  logic cmd_info_2_addr_swap_en_2_qs;
  logic cmd_info_2_addr_swap_en_2_wd;
  logic cmd_info_2_mbyte_en_2_qs;
  logic cmd_info_2_mbyte_en_2_wd;
  logic [2:0] cmd_info_2_dummy_size_2_qs;
  logic [2:0] cmd_info_2_dummy_size_2_wd;
  logic cmd_info_2_dummy_en_2_qs;
  logic cmd_info_2_dummy_en_2_wd;
  logic [3:0] cmd_info_2_payload_en_2_qs;
  logic [3:0] cmd_info_2_payload_en_2_wd;
  logic cmd_info_2_payload_dir_2_qs;
  logic cmd_info_2_payload_dir_2_wd;
  logic cmd_info_2_payload_swap_en_2_qs;
  logic cmd_info_2_payload_swap_en_2_wd;
  logic [1:0] cmd_info_2_read_pipeline_mode_2_qs;
  logic [1:0] cmd_info_2_read_pipeline_mode_2_wd;
  logic cmd_info_2_upload_2_qs;
  logic cmd_info_2_upload_2_wd;
  logic cmd_info_2_busy_2_qs;
  logic cmd_info_2_busy_2_wd;
  logic cmd_info_2_valid_2_qs;
  logic cmd_info_2_valid_2_wd;
  logic cmd_info_3_we;
  logic [7:0] cmd_info_3_opcode_3_qs;
  logic [7:0] cmd_info_3_opcode_3_wd;
  logic [1:0] cmd_info_3_addr_mode_3_qs;
  logic [1:0] cmd_info_3_addr_mode_3_wd;
  logic cmd_info_3_addr_swap_en_3_qs;
  logic cmd_info_3_addr_swap_en_3_wd;
  logic cmd_info_3_mbyte_en_3_qs;
  logic cmd_info_3_mbyte_en_3_wd;
  logic [2:0] cmd_info_3_dummy_size_3_qs;
  logic [2:0] cmd_info_3_dummy_size_3_wd;
  logic cmd_info_3_dummy_en_3_qs;
  logic cmd_info_3_dummy_en_3_wd;
  logic [3:0] cmd_info_3_payload_en_3_qs;
  logic [3:0] cmd_info_3_payload_en_3_wd;
  logic cmd_info_3_payload_dir_3_qs;
  logic cmd_info_3_payload_dir_3_wd;
  logic cmd_info_3_payload_swap_en_3_qs;
  logic cmd_info_3_payload_swap_en_3_wd;
  logic [1:0] cmd_info_3_read_pipeline_mode_3_qs;
  logic [1:0] cmd_info_3_read_pipeline_mode_3_wd;
  logic cmd_info_3_upload_3_qs;
  logic cmd_info_3_upload_3_wd;
  logic cmd_info_3_busy_3_qs;
  logic cmd_info_3_busy_3_wd;
  logic cmd_info_3_valid_3_qs;
  logic cmd_info_3_valid_3_wd;
  logic cmd_info_4_we;
  logic [7:0] cmd_info_4_opcode_4_qs;
  logic [7:0] cmd_info_4_opcode_4_wd;
  logic [1:0] cmd_info_4_addr_mode_4_qs;
  logic [1:0] cmd_info_4_addr_mode_4_wd;
  logic cmd_info_4_addr_swap_en_4_qs;
  logic cmd_info_4_addr_swap_en_4_wd;
  logic cmd_info_4_mbyte_en_4_qs;
  logic cmd_info_4_mbyte_en_4_wd;
  logic [2:0] cmd_info_4_dummy_size_4_qs;
  logic [2:0] cmd_info_4_dummy_size_4_wd;
  logic cmd_info_4_dummy_en_4_qs;
  logic cmd_info_4_dummy_en_4_wd;
  logic [3:0] cmd_info_4_payload_en_4_qs;
  logic [3:0] cmd_info_4_payload_en_4_wd;
  logic cmd_info_4_payload_dir_4_qs;
  logic cmd_info_4_payload_dir_4_wd;
  logic cmd_info_4_payload_swap_en_4_qs;
  logic cmd_info_4_payload_swap_en_4_wd;
  logic [1:0] cmd_info_4_read_pipeline_mode_4_qs;
  logic [1:0] cmd_info_4_read_pipeline_mode_4_wd;
  logic cmd_info_4_upload_4_qs;
  logic cmd_info_4_upload_4_wd;
  logic cmd_info_4_busy_4_qs;
  logic cmd_info_4_busy_4_wd;
  logic cmd_info_4_valid_4_qs;
  logic cmd_info_4_valid_4_wd;
  logic cmd_info_5_we;
  logic [7:0] cmd_info_5_opcode_5_qs;
  logic [7:0] cmd_info_5_opcode_5_wd;
  logic [1:0] cmd_info_5_addr_mode_5_qs;
  logic [1:0] cmd_info_5_addr_mode_5_wd;
  logic cmd_info_5_addr_swap_en_5_qs;
  logic cmd_info_5_addr_swap_en_5_wd;
  logic cmd_info_5_mbyte_en_5_qs;
  logic cmd_info_5_mbyte_en_5_wd;
  logic [2:0] cmd_info_5_dummy_size_5_qs;
  logic [2:0] cmd_info_5_dummy_size_5_wd;
  logic cmd_info_5_dummy_en_5_qs;
  logic cmd_info_5_dummy_en_5_wd;
  logic [3:0] cmd_info_5_payload_en_5_qs;
  logic [3:0] cmd_info_5_payload_en_5_wd;
  logic cmd_info_5_payload_dir_5_qs;
  logic cmd_info_5_payload_dir_5_wd;
  logic cmd_info_5_payload_swap_en_5_qs;
  logic cmd_info_5_payload_swap_en_5_wd;
  logic [1:0] cmd_info_5_read_pipeline_mode_5_qs;
  logic [1:0] cmd_info_5_read_pipeline_mode_5_wd;
  logic cmd_info_5_upload_5_qs;
  logic cmd_info_5_upload_5_wd;
  logic cmd_info_5_busy_5_qs;
  logic cmd_info_5_busy_5_wd;
  logic cmd_info_5_valid_5_qs;
  logic cmd_info_5_valid_5_wd;
  logic cmd_info_6_we;
  logic [7:0] cmd_info_6_opcode_6_qs;
  logic [7:0] cmd_info_6_opcode_6_wd;
  logic [1:0] cmd_info_6_addr_mode_6_qs;
  logic [1:0] cmd_info_6_addr_mode_6_wd;
  logic cmd_info_6_addr_swap_en_6_qs;
  logic cmd_info_6_addr_swap_en_6_wd;
  logic cmd_info_6_mbyte_en_6_qs;
  logic cmd_info_6_mbyte_en_6_wd;
  logic [2:0] cmd_info_6_dummy_size_6_qs;
  logic [2:0] cmd_info_6_dummy_size_6_wd;
  logic cmd_info_6_dummy_en_6_qs;
  logic cmd_info_6_dummy_en_6_wd;
  logic [3:0] cmd_info_6_payload_en_6_qs;
  logic [3:0] cmd_info_6_payload_en_6_wd;
  logic cmd_info_6_payload_dir_6_qs;
  logic cmd_info_6_payload_dir_6_wd;
  logic cmd_info_6_payload_swap_en_6_qs;
  logic cmd_info_6_payload_swap_en_6_wd;
  logic [1:0] cmd_info_6_read_pipeline_mode_6_qs;
  logic [1:0] cmd_info_6_read_pipeline_mode_6_wd;
  logic cmd_info_6_upload_6_qs;
  logic cmd_info_6_upload_6_wd;
  logic cmd_info_6_busy_6_qs;
  logic cmd_info_6_busy_6_wd;
  logic cmd_info_6_valid_6_qs;
  logic cmd_info_6_valid_6_wd;
  logic cmd_info_7_we;
  logic [7:0] cmd_info_7_opcode_7_qs;
  logic [7:0] cmd_info_7_opcode_7_wd;
  logic [1:0] cmd_info_7_addr_mode_7_qs;
  logic [1:0] cmd_info_7_addr_mode_7_wd;
  logic cmd_info_7_addr_swap_en_7_qs;
  logic cmd_info_7_addr_swap_en_7_wd;
  logic cmd_info_7_mbyte_en_7_qs;
  logic cmd_info_7_mbyte_en_7_wd;
  logic [2:0] cmd_info_7_dummy_size_7_qs;
  logic [2:0] cmd_info_7_dummy_size_7_wd;
  logic cmd_info_7_dummy_en_7_qs;
  logic cmd_info_7_dummy_en_7_wd;
  logic [3:0] cmd_info_7_payload_en_7_qs;
  logic [3:0] cmd_info_7_payload_en_7_wd;
  logic cmd_info_7_payload_dir_7_qs;
  logic cmd_info_7_payload_dir_7_wd;
  logic cmd_info_7_payload_swap_en_7_qs;
  logic cmd_info_7_payload_swap_en_7_wd;
  logic [1:0] cmd_info_7_read_pipeline_mode_7_qs;
  logic [1:0] cmd_info_7_read_pipeline_mode_7_wd;
  logic cmd_info_7_upload_7_qs;
  logic cmd_info_7_upload_7_wd;
  logic cmd_info_7_busy_7_qs;
  logic cmd_info_7_busy_7_wd;
  logic cmd_info_7_valid_7_qs;
  logic cmd_info_7_valid_7_wd;
  logic cmd_info_8_we;
  logic [7:0] cmd_info_8_opcode_8_qs;
  logic [7:0] cmd_info_8_opcode_8_wd;
  logic [1:0] cmd_info_8_addr_mode_8_qs;
  logic [1:0] cmd_info_8_addr_mode_8_wd;
  logic cmd_info_8_addr_swap_en_8_qs;
  logic cmd_info_8_addr_swap_en_8_wd;
  logic cmd_info_8_mbyte_en_8_qs;
  logic cmd_info_8_mbyte_en_8_wd;
  logic [2:0] cmd_info_8_dummy_size_8_qs;
  logic [2:0] cmd_info_8_dummy_size_8_wd;
  logic cmd_info_8_dummy_en_8_qs;
  logic cmd_info_8_dummy_en_8_wd;
  logic [3:0] cmd_info_8_payload_en_8_qs;
  logic [3:0] cmd_info_8_payload_en_8_wd;
  logic cmd_info_8_payload_dir_8_qs;
  logic cmd_info_8_payload_dir_8_wd;
  logic cmd_info_8_payload_swap_en_8_qs;
  logic cmd_info_8_payload_swap_en_8_wd;
  logic [1:0] cmd_info_8_read_pipeline_mode_8_qs;
  logic [1:0] cmd_info_8_read_pipeline_mode_8_wd;
  logic cmd_info_8_upload_8_qs;
  logic cmd_info_8_upload_8_wd;
  logic cmd_info_8_busy_8_qs;
  logic cmd_info_8_busy_8_wd;
  logic cmd_info_8_valid_8_qs;
  logic cmd_info_8_valid_8_wd;
  logic cmd_info_9_we;
  logic [7:0] cmd_info_9_opcode_9_qs;
  logic [7:0] cmd_info_9_opcode_9_wd;
  logic [1:0] cmd_info_9_addr_mode_9_qs;
  logic [1:0] cmd_info_9_addr_mode_9_wd;
  logic cmd_info_9_addr_swap_en_9_qs;
  logic cmd_info_9_addr_swap_en_9_wd;
  logic cmd_info_9_mbyte_en_9_qs;
  logic cmd_info_9_mbyte_en_9_wd;
  logic [2:0] cmd_info_9_dummy_size_9_qs;
  logic [2:0] cmd_info_9_dummy_size_9_wd;
  logic cmd_info_9_dummy_en_9_qs;
  logic cmd_info_9_dummy_en_9_wd;
  logic [3:0] cmd_info_9_payload_en_9_qs;
  logic [3:0] cmd_info_9_payload_en_9_wd;
  logic cmd_info_9_payload_dir_9_qs;
  logic cmd_info_9_payload_dir_9_wd;
  logic cmd_info_9_payload_swap_en_9_qs;
  logic cmd_info_9_payload_swap_en_9_wd;
  logic [1:0] cmd_info_9_read_pipeline_mode_9_qs;
  logic [1:0] cmd_info_9_read_pipeline_mode_9_wd;
  logic cmd_info_9_upload_9_qs;
  logic cmd_info_9_upload_9_wd;
  logic cmd_info_9_busy_9_qs;
  logic cmd_info_9_busy_9_wd;
  logic cmd_info_9_valid_9_qs;
  logic cmd_info_9_valid_9_wd;
  logic cmd_info_10_we;
  logic [7:0] cmd_info_10_opcode_10_qs;
  logic [7:0] cmd_info_10_opcode_10_wd;
  logic [1:0] cmd_info_10_addr_mode_10_qs;
  logic [1:0] cmd_info_10_addr_mode_10_wd;
  logic cmd_info_10_addr_swap_en_10_qs;
  logic cmd_info_10_addr_swap_en_10_wd;
  logic cmd_info_10_mbyte_en_10_qs;
  logic cmd_info_10_mbyte_en_10_wd;
  logic [2:0] cmd_info_10_dummy_size_10_qs;
  logic [2:0] cmd_info_10_dummy_size_10_wd;
  logic cmd_info_10_dummy_en_10_qs;
  logic cmd_info_10_dummy_en_10_wd;
  logic [3:0] cmd_info_10_payload_en_10_qs;
  logic [3:0] cmd_info_10_payload_en_10_wd;
  logic cmd_info_10_payload_dir_10_qs;
  logic cmd_info_10_payload_dir_10_wd;
  logic cmd_info_10_payload_swap_en_10_qs;
  logic cmd_info_10_payload_swap_en_10_wd;
  logic [1:0] cmd_info_10_read_pipeline_mode_10_qs;
  logic [1:0] cmd_info_10_read_pipeline_mode_10_wd;
  logic cmd_info_10_upload_10_qs;
  logic cmd_info_10_upload_10_wd;
  logic cmd_info_10_busy_10_qs;
  logic cmd_info_10_busy_10_wd;
  logic cmd_info_10_valid_10_qs;
  logic cmd_info_10_valid_10_wd;
  logic cmd_info_11_we;
  logic [7:0] cmd_info_11_opcode_11_qs;
  logic [7:0] cmd_info_11_opcode_11_wd;
  logic [1:0] cmd_info_11_addr_mode_11_qs;
  logic [1:0] cmd_info_11_addr_mode_11_wd;
  logic cmd_info_11_addr_swap_en_11_qs;
  logic cmd_info_11_addr_swap_en_11_wd;
  logic cmd_info_11_mbyte_en_11_qs;
  logic cmd_info_11_mbyte_en_11_wd;
  logic [2:0] cmd_info_11_dummy_size_11_qs;
  logic [2:0] cmd_info_11_dummy_size_11_wd;
  logic cmd_info_11_dummy_en_11_qs;
  logic cmd_info_11_dummy_en_11_wd;
  logic [3:0] cmd_info_11_payload_en_11_qs;
  logic [3:0] cmd_info_11_payload_en_11_wd;
  logic cmd_info_11_payload_dir_11_qs;
  logic cmd_info_11_payload_dir_11_wd;
  logic cmd_info_11_payload_swap_en_11_qs;
  logic cmd_info_11_payload_swap_en_11_wd;
  logic [1:0] cmd_info_11_read_pipeline_mode_11_qs;
  logic [1:0] cmd_info_11_read_pipeline_mode_11_wd;
  logic cmd_info_11_upload_11_qs;
  logic cmd_info_11_upload_11_wd;
  logic cmd_info_11_busy_11_qs;
  logic cmd_info_11_busy_11_wd;
  logic cmd_info_11_valid_11_qs;
  logic cmd_info_11_valid_11_wd;
  logic cmd_info_12_we;
  logic [7:0] cmd_info_12_opcode_12_qs;
  logic [7:0] cmd_info_12_opcode_12_wd;
  logic [1:0] cmd_info_12_addr_mode_12_qs;
  logic [1:0] cmd_info_12_addr_mode_12_wd;
  logic cmd_info_12_addr_swap_en_12_qs;
  logic cmd_info_12_addr_swap_en_12_wd;
  logic cmd_info_12_mbyte_en_12_qs;
  logic cmd_info_12_mbyte_en_12_wd;
  logic [2:0] cmd_info_12_dummy_size_12_qs;
  logic [2:0] cmd_info_12_dummy_size_12_wd;
  logic cmd_info_12_dummy_en_12_qs;
  logic cmd_info_12_dummy_en_12_wd;
  logic [3:0] cmd_info_12_payload_en_12_qs;
  logic [3:0] cmd_info_12_payload_en_12_wd;
  logic cmd_info_12_payload_dir_12_qs;
  logic cmd_info_12_payload_dir_12_wd;
  logic cmd_info_12_payload_swap_en_12_qs;
  logic cmd_info_12_payload_swap_en_12_wd;
  logic [1:0] cmd_info_12_read_pipeline_mode_12_qs;
  logic [1:0] cmd_info_12_read_pipeline_mode_12_wd;
  logic cmd_info_12_upload_12_qs;
  logic cmd_info_12_upload_12_wd;
  logic cmd_info_12_busy_12_qs;
  logic cmd_info_12_busy_12_wd;
  logic cmd_info_12_valid_12_qs;
  logic cmd_info_12_valid_12_wd;
  logic cmd_info_13_we;
  logic [7:0] cmd_info_13_opcode_13_qs;
  logic [7:0] cmd_info_13_opcode_13_wd;
  logic [1:0] cmd_info_13_addr_mode_13_qs;
  logic [1:0] cmd_info_13_addr_mode_13_wd;
  logic cmd_info_13_addr_swap_en_13_qs;
  logic cmd_info_13_addr_swap_en_13_wd;
  logic cmd_info_13_mbyte_en_13_qs;
  logic cmd_info_13_mbyte_en_13_wd;
  logic [2:0] cmd_info_13_dummy_size_13_qs;
  logic [2:0] cmd_info_13_dummy_size_13_wd;
  logic cmd_info_13_dummy_en_13_qs;
  logic cmd_info_13_dummy_en_13_wd;
  logic [3:0] cmd_info_13_payload_en_13_qs;
  logic [3:0] cmd_info_13_payload_en_13_wd;
  logic cmd_info_13_payload_dir_13_qs;
  logic cmd_info_13_payload_dir_13_wd;
  logic cmd_info_13_payload_swap_en_13_qs;
  logic cmd_info_13_payload_swap_en_13_wd;
  logic [1:0] cmd_info_13_read_pipeline_mode_13_qs;
  logic [1:0] cmd_info_13_read_pipeline_mode_13_wd;
  logic cmd_info_13_upload_13_qs;
  logic cmd_info_13_upload_13_wd;
  logic cmd_info_13_busy_13_qs;
  logic cmd_info_13_busy_13_wd;
  logic cmd_info_13_valid_13_qs;
  logic cmd_info_13_valid_13_wd;
  logic cmd_info_14_we;
  logic [7:0] cmd_info_14_opcode_14_qs;
  logic [7:0] cmd_info_14_opcode_14_wd;
  logic [1:0] cmd_info_14_addr_mode_14_qs;
  logic [1:0] cmd_info_14_addr_mode_14_wd;
  logic cmd_info_14_addr_swap_en_14_qs;
  logic cmd_info_14_addr_swap_en_14_wd;
  logic cmd_info_14_mbyte_en_14_qs;
  logic cmd_info_14_mbyte_en_14_wd;
  logic [2:0] cmd_info_14_dummy_size_14_qs;
  logic [2:0] cmd_info_14_dummy_size_14_wd;
  logic cmd_info_14_dummy_en_14_qs;
  logic cmd_info_14_dummy_en_14_wd;
  logic [3:0] cmd_info_14_payload_en_14_qs;
  logic [3:0] cmd_info_14_payload_en_14_wd;
  logic cmd_info_14_payload_dir_14_qs;
  logic cmd_info_14_payload_dir_14_wd;
  logic cmd_info_14_payload_swap_en_14_qs;
  logic cmd_info_14_payload_swap_en_14_wd;
  logic [1:0] cmd_info_14_read_pipeline_mode_14_qs;
  logic [1:0] cmd_info_14_read_pipeline_mode_14_wd;
  logic cmd_info_14_upload_14_qs;
  logic cmd_info_14_upload_14_wd;
  logic cmd_info_14_busy_14_qs;
  logic cmd_info_14_busy_14_wd;
  logic cmd_info_14_valid_14_qs;
  logic cmd_info_14_valid_14_wd;
  logic cmd_info_15_we;
  logic [7:0] cmd_info_15_opcode_15_qs;
  logic [7:0] cmd_info_15_opcode_15_wd;
  logic [1:0] cmd_info_15_addr_mode_15_qs;
  logic [1:0] cmd_info_15_addr_mode_15_wd;
  logic cmd_info_15_addr_swap_en_15_qs;
  logic cmd_info_15_addr_swap_en_15_wd;
  logic cmd_info_15_mbyte_en_15_qs;
  logic cmd_info_15_mbyte_en_15_wd;
  logic [2:0] cmd_info_15_dummy_size_15_qs;
  logic [2:0] cmd_info_15_dummy_size_15_wd;
  logic cmd_info_15_dummy_en_15_qs;
  logic cmd_info_15_dummy_en_15_wd;
  logic [3:0] cmd_info_15_payload_en_15_qs;
  logic [3:0] cmd_info_15_payload_en_15_wd;
  logic cmd_info_15_payload_dir_15_qs;
  logic cmd_info_15_payload_dir_15_wd;
  logic cmd_info_15_payload_swap_en_15_qs;
  logic cmd_info_15_payload_swap_en_15_wd;
  logic [1:0] cmd_info_15_read_pipeline_mode_15_qs;
  logic [1:0] cmd_info_15_read_pipeline_mode_15_wd;
  logic cmd_info_15_upload_15_qs;
  logic cmd_info_15_upload_15_wd;
  logic cmd_info_15_busy_15_qs;
  logic cmd_info_15_busy_15_wd;
  logic cmd_info_15_valid_15_qs;
  logic cmd_info_15_valid_15_wd;
  logic cmd_info_16_we;
  logic [7:0] cmd_info_16_opcode_16_qs;
  logic [7:0] cmd_info_16_opcode_16_wd;
  logic [1:0] cmd_info_16_addr_mode_16_qs;
  logic [1:0] cmd_info_16_addr_mode_16_wd;
  logic cmd_info_16_addr_swap_en_16_qs;
  logic cmd_info_16_addr_swap_en_16_wd;
  logic cmd_info_16_mbyte_en_16_qs;
  logic cmd_info_16_mbyte_en_16_wd;
  logic [2:0] cmd_info_16_dummy_size_16_qs;
  logic [2:0] cmd_info_16_dummy_size_16_wd;
  logic cmd_info_16_dummy_en_16_qs;
  logic cmd_info_16_dummy_en_16_wd;
  logic [3:0] cmd_info_16_payload_en_16_qs;
  logic [3:0] cmd_info_16_payload_en_16_wd;
  logic cmd_info_16_payload_dir_16_qs;
  logic cmd_info_16_payload_dir_16_wd;
  logic cmd_info_16_payload_swap_en_16_qs;
  logic cmd_info_16_payload_swap_en_16_wd;
  logic [1:0] cmd_info_16_read_pipeline_mode_16_qs;
  logic [1:0] cmd_info_16_read_pipeline_mode_16_wd;
  logic cmd_info_16_upload_16_qs;
  logic cmd_info_16_upload_16_wd;
  logic cmd_info_16_busy_16_qs;
  logic cmd_info_16_busy_16_wd;
  logic cmd_info_16_valid_16_qs;
  logic cmd_info_16_valid_16_wd;
  logic cmd_info_17_we;
  logic [7:0] cmd_info_17_opcode_17_qs;
  logic [7:0] cmd_info_17_opcode_17_wd;
  logic [1:0] cmd_info_17_addr_mode_17_qs;
  logic [1:0] cmd_info_17_addr_mode_17_wd;
  logic cmd_info_17_addr_swap_en_17_qs;
  logic cmd_info_17_addr_swap_en_17_wd;
  logic cmd_info_17_mbyte_en_17_qs;
  logic cmd_info_17_mbyte_en_17_wd;
  logic [2:0] cmd_info_17_dummy_size_17_qs;
  logic [2:0] cmd_info_17_dummy_size_17_wd;
  logic cmd_info_17_dummy_en_17_qs;
  logic cmd_info_17_dummy_en_17_wd;
  logic [3:0] cmd_info_17_payload_en_17_qs;
  logic [3:0] cmd_info_17_payload_en_17_wd;
  logic cmd_info_17_payload_dir_17_qs;
  logic cmd_info_17_payload_dir_17_wd;
  logic cmd_info_17_payload_swap_en_17_qs;
  logic cmd_info_17_payload_swap_en_17_wd;
  logic [1:0] cmd_info_17_read_pipeline_mode_17_qs;
  logic [1:0] cmd_info_17_read_pipeline_mode_17_wd;
  logic cmd_info_17_upload_17_qs;
  logic cmd_info_17_upload_17_wd;
  logic cmd_info_17_busy_17_qs;
  logic cmd_info_17_busy_17_wd;
  logic cmd_info_17_valid_17_qs;
  logic cmd_info_17_valid_17_wd;
  logic cmd_info_18_we;
  logic [7:0] cmd_info_18_opcode_18_qs;
  logic [7:0] cmd_info_18_opcode_18_wd;
  logic [1:0] cmd_info_18_addr_mode_18_qs;
  logic [1:0] cmd_info_18_addr_mode_18_wd;
  logic cmd_info_18_addr_swap_en_18_qs;
  logic cmd_info_18_addr_swap_en_18_wd;
  logic cmd_info_18_mbyte_en_18_qs;
  logic cmd_info_18_mbyte_en_18_wd;
  logic [2:0] cmd_info_18_dummy_size_18_qs;
  logic [2:0] cmd_info_18_dummy_size_18_wd;
  logic cmd_info_18_dummy_en_18_qs;
  logic cmd_info_18_dummy_en_18_wd;
  logic [3:0] cmd_info_18_payload_en_18_qs;
  logic [3:0] cmd_info_18_payload_en_18_wd;
  logic cmd_info_18_payload_dir_18_qs;
  logic cmd_info_18_payload_dir_18_wd;
  logic cmd_info_18_payload_swap_en_18_qs;
  logic cmd_info_18_payload_swap_en_18_wd;
  logic [1:0] cmd_info_18_read_pipeline_mode_18_qs;
  logic [1:0] cmd_info_18_read_pipeline_mode_18_wd;
  logic cmd_info_18_upload_18_qs;
  logic cmd_info_18_upload_18_wd;
  logic cmd_info_18_busy_18_qs;
  logic cmd_info_18_busy_18_wd;
  logic cmd_info_18_valid_18_qs;
  logic cmd_info_18_valid_18_wd;
  logic cmd_info_19_we;
  logic [7:0] cmd_info_19_opcode_19_qs;
  logic [7:0] cmd_info_19_opcode_19_wd;
  logic [1:0] cmd_info_19_addr_mode_19_qs;
  logic [1:0] cmd_info_19_addr_mode_19_wd;
  logic cmd_info_19_addr_swap_en_19_qs;
  logic cmd_info_19_addr_swap_en_19_wd;
  logic cmd_info_19_mbyte_en_19_qs;
  logic cmd_info_19_mbyte_en_19_wd;
  logic [2:0] cmd_info_19_dummy_size_19_qs;
  logic [2:0] cmd_info_19_dummy_size_19_wd;
  logic cmd_info_19_dummy_en_19_qs;
  logic cmd_info_19_dummy_en_19_wd;
  logic [3:0] cmd_info_19_payload_en_19_qs;
  logic [3:0] cmd_info_19_payload_en_19_wd;
  logic cmd_info_19_payload_dir_19_qs;
  logic cmd_info_19_payload_dir_19_wd;
  logic cmd_info_19_payload_swap_en_19_qs;
  logic cmd_info_19_payload_swap_en_19_wd;
  logic [1:0] cmd_info_19_read_pipeline_mode_19_qs;
  logic [1:0] cmd_info_19_read_pipeline_mode_19_wd;
  logic cmd_info_19_upload_19_qs;
  logic cmd_info_19_upload_19_wd;
  logic cmd_info_19_busy_19_qs;
  logic cmd_info_19_busy_19_wd;
  logic cmd_info_19_valid_19_qs;
  logic cmd_info_19_valid_19_wd;
  logic cmd_info_20_we;
  logic [7:0] cmd_info_20_opcode_20_qs;
  logic [7:0] cmd_info_20_opcode_20_wd;
  logic [1:0] cmd_info_20_addr_mode_20_qs;
  logic [1:0] cmd_info_20_addr_mode_20_wd;
  logic cmd_info_20_addr_swap_en_20_qs;
  logic cmd_info_20_addr_swap_en_20_wd;
  logic cmd_info_20_mbyte_en_20_qs;
  logic cmd_info_20_mbyte_en_20_wd;
  logic [2:0] cmd_info_20_dummy_size_20_qs;
  logic [2:0] cmd_info_20_dummy_size_20_wd;
  logic cmd_info_20_dummy_en_20_qs;
  logic cmd_info_20_dummy_en_20_wd;
  logic [3:0] cmd_info_20_payload_en_20_qs;
  logic [3:0] cmd_info_20_payload_en_20_wd;
  logic cmd_info_20_payload_dir_20_qs;
  logic cmd_info_20_payload_dir_20_wd;
  logic cmd_info_20_payload_swap_en_20_qs;
  logic cmd_info_20_payload_swap_en_20_wd;
  logic [1:0] cmd_info_20_read_pipeline_mode_20_qs;
  logic [1:0] cmd_info_20_read_pipeline_mode_20_wd;
  logic cmd_info_20_upload_20_qs;
  logic cmd_info_20_upload_20_wd;
  logic cmd_info_20_busy_20_qs;
  logic cmd_info_20_busy_20_wd;
  logic cmd_info_20_valid_20_qs;
  logic cmd_info_20_valid_20_wd;
  logic cmd_info_21_we;
  logic [7:0] cmd_info_21_opcode_21_qs;
  logic [7:0] cmd_info_21_opcode_21_wd;
  logic [1:0] cmd_info_21_addr_mode_21_qs;
  logic [1:0] cmd_info_21_addr_mode_21_wd;
  logic cmd_info_21_addr_swap_en_21_qs;
  logic cmd_info_21_addr_swap_en_21_wd;
  logic cmd_info_21_mbyte_en_21_qs;
  logic cmd_info_21_mbyte_en_21_wd;
  logic [2:0] cmd_info_21_dummy_size_21_qs;
  logic [2:0] cmd_info_21_dummy_size_21_wd;
  logic cmd_info_21_dummy_en_21_qs;
  logic cmd_info_21_dummy_en_21_wd;
  logic [3:0] cmd_info_21_payload_en_21_qs;
  logic [3:0] cmd_info_21_payload_en_21_wd;
  logic cmd_info_21_payload_dir_21_qs;
  logic cmd_info_21_payload_dir_21_wd;
  logic cmd_info_21_payload_swap_en_21_qs;
  logic cmd_info_21_payload_swap_en_21_wd;
  logic [1:0] cmd_info_21_read_pipeline_mode_21_qs;
  logic [1:0] cmd_info_21_read_pipeline_mode_21_wd;
  logic cmd_info_21_upload_21_qs;
  logic cmd_info_21_upload_21_wd;
  logic cmd_info_21_busy_21_qs;
  logic cmd_info_21_busy_21_wd;
  logic cmd_info_21_valid_21_qs;
  logic cmd_info_21_valid_21_wd;
  logic cmd_info_22_we;
  logic [7:0] cmd_info_22_opcode_22_qs;
  logic [7:0] cmd_info_22_opcode_22_wd;
  logic [1:0] cmd_info_22_addr_mode_22_qs;
  logic [1:0] cmd_info_22_addr_mode_22_wd;
  logic cmd_info_22_addr_swap_en_22_qs;
  logic cmd_info_22_addr_swap_en_22_wd;
  logic cmd_info_22_mbyte_en_22_qs;
  logic cmd_info_22_mbyte_en_22_wd;
  logic [2:0] cmd_info_22_dummy_size_22_qs;
  logic [2:0] cmd_info_22_dummy_size_22_wd;
  logic cmd_info_22_dummy_en_22_qs;
  logic cmd_info_22_dummy_en_22_wd;
  logic [3:0] cmd_info_22_payload_en_22_qs;
  logic [3:0] cmd_info_22_payload_en_22_wd;
  logic cmd_info_22_payload_dir_22_qs;
  logic cmd_info_22_payload_dir_22_wd;
  logic cmd_info_22_payload_swap_en_22_qs;
  logic cmd_info_22_payload_swap_en_22_wd;
  logic [1:0] cmd_info_22_read_pipeline_mode_22_qs;
  logic [1:0] cmd_info_22_read_pipeline_mode_22_wd;
  logic cmd_info_22_upload_22_qs;
  logic cmd_info_22_upload_22_wd;
  logic cmd_info_22_busy_22_qs;
  logic cmd_info_22_busy_22_wd;
  logic cmd_info_22_valid_22_qs;
  logic cmd_info_22_valid_22_wd;
  logic cmd_info_23_we;
  logic [7:0] cmd_info_23_opcode_23_qs;
  logic [7:0] cmd_info_23_opcode_23_wd;
  logic [1:0] cmd_info_23_addr_mode_23_qs;
  logic [1:0] cmd_info_23_addr_mode_23_wd;
  logic cmd_info_23_addr_swap_en_23_qs;
  logic cmd_info_23_addr_swap_en_23_wd;
  logic cmd_info_23_mbyte_en_23_qs;
  logic cmd_info_23_mbyte_en_23_wd;
  logic [2:0] cmd_info_23_dummy_size_23_qs;
  logic [2:0] cmd_info_23_dummy_size_23_wd;
  logic cmd_info_23_dummy_en_23_qs;
  logic cmd_info_23_dummy_en_23_wd;
  logic [3:0] cmd_info_23_payload_en_23_qs;
  logic [3:0] cmd_info_23_payload_en_23_wd;
  logic cmd_info_23_payload_dir_23_qs;
  logic cmd_info_23_payload_dir_23_wd;
  logic cmd_info_23_payload_swap_en_23_qs;
  logic cmd_info_23_payload_swap_en_23_wd;
  logic [1:0] cmd_info_23_read_pipeline_mode_23_qs;
  logic [1:0] cmd_info_23_read_pipeline_mode_23_wd;
  logic cmd_info_23_upload_23_qs;
  logic cmd_info_23_upload_23_wd;
  logic cmd_info_23_busy_23_qs;
  logic cmd_info_23_busy_23_wd;
  logic cmd_info_23_valid_23_qs;
  logic cmd_info_23_valid_23_wd;
  logic cmd_info_en4b_we;
  logic [7:0] cmd_info_en4b_opcode_qs;
  logic [7:0] cmd_info_en4b_opcode_wd;
  logic cmd_info_en4b_valid_qs;
  logic cmd_info_en4b_valid_wd;
  logic cmd_info_ex4b_we;
  logic [7:0] cmd_info_ex4b_opcode_qs;
  logic [7:0] cmd_info_ex4b_opcode_wd;
  logic cmd_info_ex4b_valid_qs;
  logic cmd_info_ex4b_valid_wd;
  logic cmd_info_wren_we;
  logic [7:0] cmd_info_wren_opcode_qs;
  logic [7:0] cmd_info_wren_opcode_wd;
  logic cmd_info_wren_valid_qs;
  logic cmd_info_wren_valid_wd;
  logic cmd_info_wrdi_we;
  logic [7:0] cmd_info_wrdi_opcode_qs;
  logic [7:0] cmd_info_wrdi_opcode_wd;
  logic cmd_info_wrdi_valid_qs;
  logic cmd_info_wrdi_valid_wd;
  logic [7:0] tpm_cap_rev_qs;
  logic tpm_cap_locality_qs;
  logic [2:0] tpm_cap_max_wr_size_qs;
  logic [2:0] tpm_cap_max_rd_size_qs;
  logic tpm_cfg_we;
  logic tpm_cfg_en_qs;
  logic tpm_cfg_en_wd;
  logic tpm_cfg_tpm_mode_qs;
  logic tpm_cfg_tpm_mode_wd;
  logic tpm_cfg_hw_reg_dis_qs;
  logic tpm_cfg_hw_reg_dis_wd;
  logic tpm_cfg_tpm_reg_chk_dis_qs;
  logic tpm_cfg_tpm_reg_chk_dis_wd;
  logic tpm_cfg_invalid_locality_qs;
  logic tpm_cfg_invalid_locality_wd;
  logic tpm_status_re;
  logic tpm_status_we;
  logic tpm_status_cmdaddr_notempty_qs;
  logic tpm_status_wrfifo_pending_qs;
  logic tpm_status_wrfifo_pending_wd;
  logic tpm_status_rdfifo_aborted_qs;
  logic tpm_access_0_we;
  logic [7:0] tpm_access_0_access_0_qs;
  logic [7:0] tpm_access_0_access_0_wd;
  logic [7:0] tpm_access_0_access_1_qs;
  logic [7:0] tpm_access_0_access_1_wd;
  logic [7:0] tpm_access_0_access_2_qs;
  logic [7:0] tpm_access_0_access_2_wd;
  logic [7:0] tpm_access_0_access_3_qs;
  logic [7:0] tpm_access_0_access_3_wd;
  logic tpm_access_1_we;
  logic [7:0] tpm_access_1_qs;
  logic [7:0] tpm_access_1_wd;
  logic tpm_sts_we;
  logic [31:0] tpm_sts_qs;
  logic [31:0] tpm_sts_wd;
  logic tpm_intf_capability_we;
  logic [31:0] tpm_intf_capability_qs;
  logic [31:0] tpm_intf_capability_wd;
  logic tpm_int_enable_we;
  logic [31:0] tpm_int_enable_qs;
  logic [31:0] tpm_int_enable_wd;
  logic tpm_int_vector_we;
  logic [7:0] tpm_int_vector_qs;
  logic [7:0] tpm_int_vector_wd;
  logic tpm_int_status_we;
  logic [31:0] tpm_int_status_qs;
  logic [31:0] tpm_int_status_wd;
  logic tpm_did_vid_we;
  logic [15:0] tpm_did_vid_vid_qs;
  logic [15:0] tpm_did_vid_vid_wd;
  logic [15:0] tpm_did_vid_did_qs;
  logic [15:0] tpm_did_vid_did_wd;
  logic tpm_rid_we;
  logic [7:0] tpm_rid_qs;
  logic [7:0] tpm_rid_wd;
  logic tpm_cmd_addr_re;
  logic [23:0] tpm_cmd_addr_addr_qs;
  logic [7:0] tpm_cmd_addr_cmd_qs;
  logic tpm_read_fifo_we;
  logic [31:0] tpm_read_fifo_wd;
  // Register instances
  // R[intr_state]: V(False)
  //   F[upload_cmdfifo_not_empty]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_state_upload_cmdfifo_not_empty (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_upload_cmdfifo_not_empty_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.upload_cmdfifo_not_empty.de),
    .d      (hw2reg.intr_state.upload_cmdfifo_not_empty.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.upload_cmdfifo_not_empty.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_upload_cmdfifo_not_empty_qs)
  );

  //   F[upload_payload_not_empty]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_state_upload_payload_not_empty (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_upload_payload_not_empty_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.upload_payload_not_empty.de),
    .d      (hw2reg.intr_state.upload_payload_not_empty.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.upload_payload_not_empty.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_upload_payload_not_empty_qs)
  );

  //   F[upload_payload_overflow]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_state_upload_payload_overflow (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_upload_payload_overflow_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.upload_payload_overflow.de),
    .d      (hw2reg.intr_state.upload_payload_overflow.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.upload_payload_overflow.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_upload_payload_overflow_qs)
  );

  //   F[readbuf_watermark]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_state_readbuf_watermark (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_readbuf_watermark_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.readbuf_watermark.de),
    .d      (hw2reg.intr_state.readbuf_watermark.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.readbuf_watermark.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_readbuf_watermark_qs)
  );

  //   F[readbuf_flip]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_state_readbuf_flip (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_readbuf_flip_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.readbuf_flip.de),
    .d      (hw2reg.intr_state.readbuf_flip.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.readbuf_flip.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_readbuf_flip_qs)
  );

  //   F[tpm_header_not_empty]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_state_tpm_header_not_empty (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.intr_state.tpm_header_not_empty.de),
    .d      (hw2reg.intr_state.tpm_header_not_empty.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.tpm_header_not_empty.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_tpm_header_not_empty_qs)
  );

  //   F[tpm_rdfifo_cmd_end]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_state_tpm_rdfifo_cmd_end (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_tpm_rdfifo_cmd_end_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.tpm_rdfifo_cmd_end.de),
    .d      (hw2reg.intr_state.tpm_rdfifo_cmd_end.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.tpm_rdfifo_cmd_end.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_tpm_rdfifo_cmd_end_qs)
  );

  //   F[tpm_rdfifo_drop]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_state_tpm_rdfifo_drop (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_tpm_rdfifo_drop_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.tpm_rdfifo_drop.de),
    .d      (hw2reg.intr_state.tpm_rdfifo_drop.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.tpm_rdfifo_drop.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_tpm_rdfifo_drop_qs)
  );


  // R[intr_enable]: V(False)
  //   F[upload_cmdfifo_not_empty]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_enable_upload_cmdfifo_not_empty (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_upload_cmdfifo_not_empty_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.upload_cmdfifo_not_empty.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_upload_cmdfifo_not_empty_qs)
  );

  //   F[upload_payload_not_empty]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_enable_upload_payload_not_empty (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_upload_payload_not_empty_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.upload_payload_not_empty.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_upload_payload_not_empty_qs)
  );

  //   F[upload_payload_overflow]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_enable_upload_payload_overflow (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_upload_payload_overflow_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.upload_payload_overflow.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_upload_payload_overflow_qs)
  );

  //   F[readbuf_watermark]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_enable_readbuf_watermark (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_readbuf_watermark_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.readbuf_watermark.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_readbuf_watermark_qs)
  );

  //   F[readbuf_flip]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_enable_readbuf_flip (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_readbuf_flip_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.readbuf_flip.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_readbuf_flip_qs)
  );

  //   F[tpm_header_not_empty]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_enable_tpm_header_not_empty (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_tpm_header_not_empty_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.tpm_header_not_empty.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_tpm_header_not_empty_qs)
  );

  //   F[tpm_rdfifo_cmd_end]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_enable_tpm_rdfifo_cmd_end (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_tpm_rdfifo_cmd_end_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.tpm_rdfifo_cmd_end.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_tpm_rdfifo_cmd_end_qs)
  );

  //   F[tpm_rdfifo_drop]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intr_enable_tpm_rdfifo_drop (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_tpm_rdfifo_drop_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.tpm_rdfifo_drop.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_tpm_rdfifo_drop_qs)
  );


  // R[intr_test]: V(True)
  logic intr_test_qe;
  logic [7:0] intr_test_flds_we;
  assign intr_test_qe = &intr_test_flds_we;
  //   F[upload_cmdfifo_not_empty]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_upload_cmdfifo_not_empty (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_upload_cmdfifo_not_empty_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[0]),
    .q      (reg2hw.intr_test.upload_cmdfifo_not_empty.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.upload_cmdfifo_not_empty.qe = intr_test_qe;

  //   F[upload_payload_not_empty]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_upload_payload_not_empty (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_upload_payload_not_empty_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[1]),
    .q      (reg2hw.intr_test.upload_payload_not_empty.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.upload_payload_not_empty.qe = intr_test_qe;

  //   F[upload_payload_overflow]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_upload_payload_overflow (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_upload_payload_overflow_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[2]),
    .q      (reg2hw.intr_test.upload_payload_overflow.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.upload_payload_overflow.qe = intr_test_qe;

  //   F[readbuf_watermark]: 3:3
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_readbuf_watermark (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_readbuf_watermark_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[3]),
    .q      (reg2hw.intr_test.readbuf_watermark.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.readbuf_watermark.qe = intr_test_qe;

  //   F[readbuf_flip]: 4:4
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_readbuf_flip (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_readbuf_flip_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[4]),
    .q      (reg2hw.intr_test.readbuf_flip.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.readbuf_flip.qe = intr_test_qe;

  //   F[tpm_header_not_empty]: 5:5
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_tpm_header_not_empty (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_tpm_header_not_empty_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[5]),
    .q      (reg2hw.intr_test.tpm_header_not_empty.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.tpm_header_not_empty.qe = intr_test_qe;

  //   F[tpm_rdfifo_cmd_end]: 6:6
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_tpm_rdfifo_cmd_end (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_tpm_rdfifo_cmd_end_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[6]),
    .q      (reg2hw.intr_test.tpm_rdfifo_cmd_end.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.tpm_rdfifo_cmd_end.qe = intr_test_qe;

  //   F[tpm_rdfifo_drop]: 7:7
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_tpm_rdfifo_drop (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_tpm_rdfifo_drop_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[7]),
    .q      (reg2hw.intr_test.tpm_rdfifo_drop.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.tpm_rdfifo_drop.qe = intr_test_qe;


  // R[alert_test]: V(True)
  logic alert_test_qe;
  logic [0:0] alert_test_flds_we;
  assign alert_test_qe = &alert_test_flds_we;
  prim_subreg_ext #(
    .DW    (1)
  ) u_alert_test (
    .re     (1'b0),
    .we     (alert_test_we),
    .wd     (alert_test_wd),
    .d      ('0),
    .qre    (),
    .qe     (alert_test_flds_we[0]),
    .q      (reg2hw.alert_test.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.alert_test.qe = alert_test_qe;


  // R[control]: V(False)
  //   F[flash_status_fifo_clr]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1S),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_control_flash_status_fifo_clr (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (control_we),
    .wd     (control_flash_status_fifo_clr_wd),

    // from internal hardware
    .de     (hw2reg.control.flash_status_fifo_clr.de),
    .d      (hw2reg.control.flash_status_fifo_clr.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.control.flash_status_fifo_clr.q),
    .ds     (),

    // to register interface (read)
    .qs     (control_flash_status_fifo_clr_qs)
  );

  //   F[flash_read_buffer_clr]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1S),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_control_flash_read_buffer_clr (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (control_we),
    .wd     (control_flash_read_buffer_clr_wd),

    // from internal hardware
    .de     (hw2reg.control.flash_read_buffer_clr.de),
    .d      (hw2reg.control.flash_read_buffer_clr.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.control.flash_read_buffer_clr.q),
    .ds     (),

    // to register interface (read)
    .qs     (control_flash_read_buffer_clr_qs)
  );

  //   F[mode]: 5:4
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h1),
    .Mubi    (1'b0)
  ) u_control_mode (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (control_we),
    .wd     (control_mode_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.control.mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (control_mode_qs)
  );


  // R[cfg]: V(False)
  //   F[tx_order]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cfg_tx_order (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cfg_we),
    .wd     (cfg_tx_order_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cfg.tx_order.q),
    .ds     (),

    // to register interface (read)
    .qs     (cfg_tx_order_qs)
  );

  //   F[rx_order]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cfg_rx_order (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cfg_we),
    .wd     (cfg_rx_order_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cfg.rx_order.q),
    .ds     (),

    // to register interface (read)
    .qs     (cfg_rx_order_qs)
  );

  //   F[mailbox_en]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cfg_mailbox_en (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cfg_we),
    .wd     (cfg_mailbox_en_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cfg.mailbox_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cfg_mailbox_en_qs)
  );


  // R[status]: V(True)
  //   F[csb]: 5:5
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_csb (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.csb.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_csb_qs)
  );

  //   F[tpm_csb]: 6:6
  prim_subreg_ext #(
    .DW    (1)
  ) u_status_tpm_csb (
    .re     (status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.status.tpm_csb.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (status_tpm_csb_qs)
  );


  // R[intercept_en]: V(False)
  //   F[status]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intercept_en_status (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intercept_en_we),
    .wd     (intercept_en_status_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intercept_en.status.q),
    .ds     (),

    // to register interface (read)
    .qs     (intercept_en_status_qs)
  );

  //   F[jedec]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intercept_en_jedec (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intercept_en_we),
    .wd     (intercept_en_jedec_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intercept_en.jedec.q),
    .ds     (),

    // to register interface (read)
    .qs     (intercept_en_jedec_qs)
  );

  //   F[sfdp]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intercept_en_sfdp (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intercept_en_we),
    .wd     (intercept_en_sfdp_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intercept_en.sfdp.q),
    .ds     (),

    // to register interface (read)
    .qs     (intercept_en_sfdp_qs)
  );

  //   F[mbx]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_intercept_en_mbx (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intercept_en_we),
    .wd     (intercept_en_mbx_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intercept_en.mbx.q),
    .ds     (),

    // to register interface (read)
    .qs     (intercept_en_mbx_qs)
  );


  // R[addr_mode]: V(True)
  logic addr_mode_qe;
  logic [1:0] addr_mode_flds_we;
  // This ignores QEs that are set to constant 0 due to read-only fields.
  logic unused_addr_mode_flds_we;
  assign unused_addr_mode_flds_we = ^(addr_mode_flds_we & 2'h2);
  assign addr_mode_qe = &(addr_mode_flds_we | 2'h2);
  //   F[addr_4b_en]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_addr_mode_addr_4b_en (
    .re     (addr_mode_re),
    .we     (addr_mode_we),
    .wd     (addr_mode_addr_4b_en_wd),
    .d      (hw2reg.addr_mode.addr_4b_en.d),
    .qre    (),
    .qe     (addr_mode_flds_we[0]),
    .q      (reg2hw.addr_mode.addr_4b_en.q),
    .ds     (),
    .qs     (addr_mode_addr_4b_en_qs)
  );
  assign reg2hw.addr_mode.addr_4b_en.qe = addr_mode_qe;

  //   F[pending]: 31:31
  prim_subreg_ext #(
    .DW    (1)
  ) u_addr_mode_pending (
    .re     (addr_mode_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.addr_mode.pending.d),
    .qre    (),
    .qe     (addr_mode_flds_we[1]),
    .q      (),
    .ds     (),
    .qs     (addr_mode_pending_qs)
  );


  // R[last_read_addr]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_last_read_addr (
    .re     (last_read_addr_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.last_read_addr.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (last_read_addr_qs)
  );


  // R[flash_status]: V(True)
  logic flash_status_qe;
  logic [2:0] flash_status_flds_we;
  assign flash_status_qe = &flash_status_flds_we;
  //   F[busy]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_flash_status_busy (
    .re     (flash_status_re),
    .we     (flash_status_we),
    .wd     (flash_status_busy_wd),
    .d      (hw2reg.flash_status.busy.d),
    .qre    (),
    .qe     (flash_status_flds_we[0]),
    .q      (reg2hw.flash_status.busy.q),
    .ds     (),
    .qs     (flash_status_busy_qs)
  );
  assign reg2hw.flash_status.busy.qe = flash_status_qe;

  //   F[wel]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_flash_status_wel (
    .re     (flash_status_re),
    .we     (flash_status_we),
    .wd     (flash_status_wel_wd),
    .d      (hw2reg.flash_status.wel.d),
    .qre    (),
    .qe     (flash_status_flds_we[1]),
    .q      (reg2hw.flash_status.wel.q),
    .ds     (),
    .qs     (flash_status_wel_qs)
  );
  assign reg2hw.flash_status.wel.qe = flash_status_qe;

  //   F[status]: 23:2
  prim_subreg_ext #(
    .DW    (22)
  ) u_flash_status_status (
    .re     (flash_status_re),
    .we     (flash_status_we),
    .wd     (flash_status_status_wd),
    .d      (hw2reg.flash_status.status.d),
    .qre    (),
    .qe     (flash_status_flds_we[2]),
    .q      (reg2hw.flash_status.status.q),
    .ds     (),
    .qs     (flash_status_status_qs)
  );
  assign reg2hw.flash_status.status.qe = flash_status_qe;


  // R[jedec_cc]: V(False)
  //   F[cc]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h7f),
    .Mubi    (1'b0)
  ) u_jedec_cc_cc (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (jedec_cc_we),
    .wd     (jedec_cc_cc_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.jedec_cc.cc.q),
    .ds     (),

    // to register interface (read)
    .qs     (jedec_cc_cc_qs)
  );

  //   F[num_cc]: 15:8
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_jedec_cc_num_cc (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (jedec_cc_we),
    .wd     (jedec_cc_num_cc_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.jedec_cc.num_cc.q),
    .ds     (),

    // to register interface (read)
    .qs     (jedec_cc_num_cc_qs)
  );


  // R[jedec_id]: V(False)
  //   F[id]: 15:0
  prim_subreg #(
    .DW      (16),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (16'h0),
    .Mubi    (1'b0)
  ) u_jedec_id_id (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (jedec_id_we),
    .wd     (jedec_id_id_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.jedec_id.id.q),
    .ds     (),

    // to register interface (read)
    .qs     (jedec_id_id_qs)
  );

  //   F[mf]: 23:16
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_jedec_id_mf (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (jedec_id_we),
    .wd     (jedec_id_mf_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.jedec_id.mf.q),
    .ds     (),

    // to register interface (read)
    .qs     (jedec_id_mf_qs)
  );


  // R[read_threshold]: V(False)
  prim_subreg #(
    .DW      (10),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (10'h0),
    .Mubi    (1'b0)
  ) u_read_threshold (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (read_threshold_we),
    .wd     (read_threshold_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.read_threshold.q),
    .ds     (),

    // to register interface (read)
    .qs     (read_threshold_qs)
  );


  // R[mailbox_addr]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_mailbox_addr (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (mailbox_addr_we),
    .wd     (mailbox_addr_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.mailbox_addr.q),
    .ds     (),

    // to register interface (read)
    .qs     (mailbox_addr_qs)
  );


  // R[upload_status]: V(False)
  //   F[cmdfifo_depth]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (5'h0),
    .Mubi    (1'b0)
  ) u_upload_status_cmdfifo_depth (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.upload_status.cmdfifo_depth.de),
    .d      (hw2reg.upload_status.cmdfifo_depth.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (upload_status_cmdfifo_depth_qs)
  );

  //   F[cmdfifo_notempty]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_upload_status_cmdfifo_notempty (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.upload_status.cmdfifo_notempty.de),
    .d      (hw2reg.upload_status.cmdfifo_notempty.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (upload_status_cmdfifo_notempty_qs)
  );

  //   F[addrfifo_depth]: 12:8
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (5'h0),
    .Mubi    (1'b0)
  ) u_upload_status_addrfifo_depth (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.upload_status.addrfifo_depth.de),
    .d      (hw2reg.upload_status.addrfifo_depth.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (upload_status_addrfifo_depth_qs)
  );

  //   F[addrfifo_notempty]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_upload_status_addrfifo_notempty (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.upload_status.addrfifo_notempty.de),
    .d      (hw2reg.upload_status.addrfifo_notempty.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (upload_status_addrfifo_notempty_qs)
  );


  // R[upload_status2]: V(False)
  //   F[payload_depth]: 8:0
  prim_subreg #(
    .DW      (9),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (9'h0),
    .Mubi    (1'b0)
  ) u_upload_status2_payload_depth (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.upload_status2.payload_depth.de),
    .d      (hw2reg.upload_status2.payload_depth.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (upload_status2_payload_depth_qs)
  );

  //   F[payload_start_idx]: 23:16
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_upload_status2_payload_start_idx (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.upload_status2.payload_start_idx.de),
    .d      (hw2reg.upload_status2.payload_start_idx.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (upload_status2_payload_start_idx_qs)
  );


  // R[upload_cmdfifo]: V(True)
  //   F[data]: 7:0
  prim_subreg_ext #(
    .DW    (8)
  ) u_upload_cmdfifo_data (
    .re     (upload_cmdfifo_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.upload_cmdfifo.data.d),
    .qre    (reg2hw.upload_cmdfifo.data.re),
    .qe     (),
    .q      (reg2hw.upload_cmdfifo.data.q),
    .ds     (),
    .qs     (upload_cmdfifo_data_qs)
  );

  //   F[busy]: 13:13
  prim_subreg_ext #(
    .DW    (1)
  ) u_upload_cmdfifo_busy (
    .re     (upload_cmdfifo_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.upload_cmdfifo.busy.d),
    .qre    (reg2hw.upload_cmdfifo.busy.re),
    .qe     (),
    .q      (reg2hw.upload_cmdfifo.busy.q),
    .ds     (),
    .qs     (upload_cmdfifo_busy_qs)
  );

  //   F[wel]: 14:14
  prim_subreg_ext #(
    .DW    (1)
  ) u_upload_cmdfifo_wel (
    .re     (upload_cmdfifo_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.upload_cmdfifo.wel.d),
    .qre    (reg2hw.upload_cmdfifo.wel.re),
    .qe     (),
    .q      (reg2hw.upload_cmdfifo.wel.q),
    .ds     (),
    .qs     (upload_cmdfifo_wel_qs)
  );

  //   F[addr4b_mode]: 15:15
  prim_subreg_ext #(
    .DW    (1)
  ) u_upload_cmdfifo_addr4b_mode (
    .re     (upload_cmdfifo_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.upload_cmdfifo.addr4b_mode.d),
    .qre    (reg2hw.upload_cmdfifo.addr4b_mode.re),
    .qe     (),
    .q      (reg2hw.upload_cmdfifo.addr4b_mode.q),
    .ds     (),
    .qs     (upload_cmdfifo_addr4b_mode_qs)
  );


  // R[upload_addrfifo]: V(True)
  prim_subreg_ext #(
    .DW    (32)
  ) u_upload_addrfifo (
    .re     (upload_addrfifo_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.upload_addrfifo.d),
    .qre    (reg2hw.upload_addrfifo.re),
    .qe     (),
    .q      (reg2hw.upload_addrfifo.q),
    .ds     (),
    .qs     (upload_addrfifo_qs)
  );


  // Subregister 0 of Multireg cmd_filter
  // R[cmd_filter_0]: V(False)
  //   F[filter_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_0_qs)
  );

  //   F[filter_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_1_qs)
  );

  //   F[filter_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_2_qs)
  );

  //   F[filter_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_3_qs)
  );

  //   F[filter_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_4_qs)
  );

  //   F[filter_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_5_qs)
  );

  //   F[filter_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_6_qs)
  );

  //   F[filter_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_7_qs)
  );

  //   F[filter_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_8_qs)
  );

  //   F[filter_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_9_qs)
  );

  //   F[filter_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_10_qs)
  );

  //   F[filter_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_11_qs)
  );

  //   F[filter_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[12].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_12_qs)
  );

  //   F[filter_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[13].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_13_qs)
  );

  //   F[filter_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[14].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_14_qs)
  );

  //   F[filter_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[15].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_15_qs)
  );

  //   F[filter_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[16].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_16_qs)
  );

  //   F[filter_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[17].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_17_qs)
  );

  //   F[filter_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[18].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_18_qs)
  );

  //   F[filter_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[19].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_19_qs)
  );

  //   F[filter_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[20].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_20_qs)
  );

  //   F[filter_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[21].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_21_qs)
  );

  //   F[filter_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[22].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_22_qs)
  );

  //   F[filter_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[23].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_23_qs)
  );

  //   F[filter_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_24 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_24_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[24].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_24_qs)
  );

  //   F[filter_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_25 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_25_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[25].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_25_qs)
  );

  //   F[filter_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_26 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_26_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[26].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_26_qs)
  );

  //   F[filter_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_27 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_27_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[27].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_27_qs)
  );

  //   F[filter_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_28 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_28_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[28].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_28_qs)
  );

  //   F[filter_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_29 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_29_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[29].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_29_qs)
  );

  //   F[filter_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_30 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_30_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[30].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_30_qs)
  );

  //   F[filter_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_0_filter_31 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_0_we),
    .wd     (cmd_filter_0_filter_31_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[31].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_0_filter_31_qs)
  );


  // Subregister 1 of Multireg cmd_filter
  // R[cmd_filter_1]: V(False)
  //   F[filter_32]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_32 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_32_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[32].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_32_qs)
  );

  //   F[filter_33]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_33 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_33_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[33].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_33_qs)
  );

  //   F[filter_34]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_34 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_34_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[34].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_34_qs)
  );

  //   F[filter_35]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_35 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_35_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[35].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_35_qs)
  );

  //   F[filter_36]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_36 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_36_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[36].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_36_qs)
  );

  //   F[filter_37]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_37 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_37_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[37].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_37_qs)
  );

  //   F[filter_38]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_38 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_38_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[38].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_38_qs)
  );

  //   F[filter_39]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_39 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_39_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[39].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_39_qs)
  );

  //   F[filter_40]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_40 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_40_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[40].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_40_qs)
  );

  //   F[filter_41]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_41 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_41_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[41].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_41_qs)
  );

  //   F[filter_42]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_42 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_42_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[42].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_42_qs)
  );

  //   F[filter_43]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_43 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_43_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[43].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_43_qs)
  );

  //   F[filter_44]: 12:12
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_44 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_44_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[44].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_44_qs)
  );

  //   F[filter_45]: 13:13
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_45 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_45_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[45].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_45_qs)
  );

  //   F[filter_46]: 14:14
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_46 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_46_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[46].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_46_qs)
  );

  //   F[filter_47]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_47 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_47_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[47].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_47_qs)
  );

  //   F[filter_48]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_48 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_48_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[48].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_48_qs)
  );

  //   F[filter_49]: 17:17
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_49 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_49_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[49].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_49_qs)
  );

  //   F[filter_50]: 18:18
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_50 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_50_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[50].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_50_qs)
  );

  //   F[filter_51]: 19:19
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_51 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_51_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[51].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_51_qs)
  );

  //   F[filter_52]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_52 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_52_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[52].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_52_qs)
  );

  //   F[filter_53]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_53 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_53_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[53].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_53_qs)
  );

  //   F[filter_54]: 22:22
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_54 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_54_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[54].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_54_qs)
  );

  //   F[filter_55]: 23:23
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_55 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_55_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[55].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_55_qs)
  );

  //   F[filter_56]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_56 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_56_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[56].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_56_qs)
  );

  //   F[filter_57]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_57 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_57_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[57].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_57_qs)
  );

  //   F[filter_58]: 26:26
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_58 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_58_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[58].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_58_qs)
  );

  //   F[filter_59]: 27:27
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_59 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_59_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[59].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_59_qs)
  );

  //   F[filter_60]: 28:28
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_60 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_60_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[60].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_60_qs)
  );

  //   F[filter_61]: 29:29
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_61 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_61_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[61].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_61_qs)
  );

  //   F[filter_62]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_62 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_62_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[62].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_62_qs)
  );

  //   F[filter_63]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_1_filter_63 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_1_we),
    .wd     (cmd_filter_1_filter_63_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[63].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_1_filter_63_qs)
  );


  // Subregister 2 of Multireg cmd_filter
  // R[cmd_filter_2]: V(False)
  //   F[filter_64]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_64 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_64_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[64].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_64_qs)
  );

  //   F[filter_65]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_65 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_65_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[65].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_65_qs)
  );

  //   F[filter_66]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_66 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_66_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[66].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_66_qs)
  );

  //   F[filter_67]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_67 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_67_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[67].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_67_qs)
  );

  //   F[filter_68]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_68 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_68_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[68].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_68_qs)
  );

  //   F[filter_69]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_69 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_69_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[69].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_69_qs)
  );

  //   F[filter_70]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_70 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_70_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[70].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_70_qs)
  );

  //   F[filter_71]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_71 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_71_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[71].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_71_qs)
  );

  //   F[filter_72]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_72 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_72_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[72].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_72_qs)
  );

  //   F[filter_73]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_73 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_73_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[73].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_73_qs)
  );

  //   F[filter_74]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_74 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_74_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[74].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_74_qs)
  );

  //   F[filter_75]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_75 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_75_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[75].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_75_qs)
  );

  //   F[filter_76]: 12:12
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_76 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_76_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[76].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_76_qs)
  );

  //   F[filter_77]: 13:13
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_77 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_77_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[77].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_77_qs)
  );

  //   F[filter_78]: 14:14
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_78 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_78_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[78].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_78_qs)
  );

  //   F[filter_79]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_79 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_79_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[79].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_79_qs)
  );

  //   F[filter_80]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_80 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_80_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[80].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_80_qs)
  );

  //   F[filter_81]: 17:17
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_81 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_81_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[81].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_81_qs)
  );

  //   F[filter_82]: 18:18
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_82 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_82_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[82].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_82_qs)
  );

  //   F[filter_83]: 19:19
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_83 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_83_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[83].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_83_qs)
  );

  //   F[filter_84]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_84 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_84_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[84].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_84_qs)
  );

  //   F[filter_85]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_85 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_85_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[85].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_85_qs)
  );

  //   F[filter_86]: 22:22
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_86 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_86_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[86].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_86_qs)
  );

  //   F[filter_87]: 23:23
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_87 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_87_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[87].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_87_qs)
  );

  //   F[filter_88]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_88 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_88_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[88].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_88_qs)
  );

  //   F[filter_89]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_89 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_89_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[89].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_89_qs)
  );

  //   F[filter_90]: 26:26
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_90 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_90_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[90].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_90_qs)
  );

  //   F[filter_91]: 27:27
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_91 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_91_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[91].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_91_qs)
  );

  //   F[filter_92]: 28:28
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_92 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_92_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[92].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_92_qs)
  );

  //   F[filter_93]: 29:29
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_93 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_93_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[93].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_93_qs)
  );

  //   F[filter_94]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_94 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_94_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[94].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_94_qs)
  );

  //   F[filter_95]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_2_filter_95 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_2_we),
    .wd     (cmd_filter_2_filter_95_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[95].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_2_filter_95_qs)
  );


  // Subregister 3 of Multireg cmd_filter
  // R[cmd_filter_3]: V(False)
  //   F[filter_96]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_96 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_96_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[96].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_96_qs)
  );

  //   F[filter_97]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_97 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_97_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[97].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_97_qs)
  );

  //   F[filter_98]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_98 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_98_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[98].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_98_qs)
  );

  //   F[filter_99]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_99 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_99_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[99].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_99_qs)
  );

  //   F[filter_100]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_100 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_100_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[100].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_100_qs)
  );

  //   F[filter_101]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_101 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_101_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[101].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_101_qs)
  );

  //   F[filter_102]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_102 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_102_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[102].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_102_qs)
  );

  //   F[filter_103]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_103 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_103_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[103].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_103_qs)
  );

  //   F[filter_104]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_104 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_104_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[104].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_104_qs)
  );

  //   F[filter_105]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_105 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_105_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[105].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_105_qs)
  );

  //   F[filter_106]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_106 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_106_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[106].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_106_qs)
  );

  //   F[filter_107]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_107 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_107_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[107].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_107_qs)
  );

  //   F[filter_108]: 12:12
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_108 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_108_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[108].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_108_qs)
  );

  //   F[filter_109]: 13:13
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_109 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_109_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[109].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_109_qs)
  );

  //   F[filter_110]: 14:14
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_110 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_110_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[110].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_110_qs)
  );

  //   F[filter_111]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_111 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_111_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[111].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_111_qs)
  );

  //   F[filter_112]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_112 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_112_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[112].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_112_qs)
  );

  //   F[filter_113]: 17:17
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_113 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_113_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[113].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_113_qs)
  );

  //   F[filter_114]: 18:18
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_114 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_114_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[114].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_114_qs)
  );

  //   F[filter_115]: 19:19
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_115 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_115_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[115].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_115_qs)
  );

  //   F[filter_116]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_116 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_116_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[116].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_116_qs)
  );

  //   F[filter_117]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_117 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_117_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[117].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_117_qs)
  );

  //   F[filter_118]: 22:22
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_118 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_118_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[118].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_118_qs)
  );

  //   F[filter_119]: 23:23
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_119 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_119_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[119].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_119_qs)
  );

  //   F[filter_120]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_120 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_120_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[120].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_120_qs)
  );

  //   F[filter_121]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_121 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_121_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[121].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_121_qs)
  );

  //   F[filter_122]: 26:26
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_122 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_122_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[122].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_122_qs)
  );

  //   F[filter_123]: 27:27
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_123 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_123_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[123].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_123_qs)
  );

  //   F[filter_124]: 28:28
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_124 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_124_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[124].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_124_qs)
  );

  //   F[filter_125]: 29:29
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_125 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_125_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[125].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_125_qs)
  );

  //   F[filter_126]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_126 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_126_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[126].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_126_qs)
  );

  //   F[filter_127]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_3_filter_127 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_3_we),
    .wd     (cmd_filter_3_filter_127_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[127].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_3_filter_127_qs)
  );


  // Subregister 4 of Multireg cmd_filter
  // R[cmd_filter_4]: V(False)
  //   F[filter_128]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_128 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_128_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[128].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_128_qs)
  );

  //   F[filter_129]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_129 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_129_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[129].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_129_qs)
  );

  //   F[filter_130]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_130 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_130_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[130].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_130_qs)
  );

  //   F[filter_131]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_131 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_131_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[131].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_131_qs)
  );

  //   F[filter_132]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_132 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_132_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[132].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_132_qs)
  );

  //   F[filter_133]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_133 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_133_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[133].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_133_qs)
  );

  //   F[filter_134]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_134 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_134_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[134].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_134_qs)
  );

  //   F[filter_135]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_135 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_135_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[135].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_135_qs)
  );

  //   F[filter_136]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_136 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_136_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[136].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_136_qs)
  );

  //   F[filter_137]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_137 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_137_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[137].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_137_qs)
  );

  //   F[filter_138]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_138 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_138_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[138].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_138_qs)
  );

  //   F[filter_139]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_139 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_139_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[139].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_139_qs)
  );

  //   F[filter_140]: 12:12
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_140 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_140_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[140].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_140_qs)
  );

  //   F[filter_141]: 13:13
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_141 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_141_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[141].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_141_qs)
  );

  //   F[filter_142]: 14:14
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_142 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_142_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[142].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_142_qs)
  );

  //   F[filter_143]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_143 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_143_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[143].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_143_qs)
  );

  //   F[filter_144]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_144 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_144_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[144].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_144_qs)
  );

  //   F[filter_145]: 17:17
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_145 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_145_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[145].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_145_qs)
  );

  //   F[filter_146]: 18:18
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_146 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_146_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[146].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_146_qs)
  );

  //   F[filter_147]: 19:19
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_147 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_147_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[147].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_147_qs)
  );

  //   F[filter_148]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_148 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_148_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[148].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_148_qs)
  );

  //   F[filter_149]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_149 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_149_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[149].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_149_qs)
  );

  //   F[filter_150]: 22:22
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_150 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_150_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[150].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_150_qs)
  );

  //   F[filter_151]: 23:23
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_151 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_151_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[151].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_151_qs)
  );

  //   F[filter_152]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_152 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_152_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[152].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_152_qs)
  );

  //   F[filter_153]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_153 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_153_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[153].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_153_qs)
  );

  //   F[filter_154]: 26:26
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_154 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_154_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[154].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_154_qs)
  );

  //   F[filter_155]: 27:27
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_155 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_155_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[155].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_155_qs)
  );

  //   F[filter_156]: 28:28
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_156 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_156_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[156].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_156_qs)
  );

  //   F[filter_157]: 29:29
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_157 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_157_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[157].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_157_qs)
  );

  //   F[filter_158]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_158 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_158_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[158].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_158_qs)
  );

  //   F[filter_159]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_4_filter_159 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_4_we),
    .wd     (cmd_filter_4_filter_159_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[159].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_4_filter_159_qs)
  );


  // Subregister 5 of Multireg cmd_filter
  // R[cmd_filter_5]: V(False)
  //   F[filter_160]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_160 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_160_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[160].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_160_qs)
  );

  //   F[filter_161]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_161 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_161_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[161].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_161_qs)
  );

  //   F[filter_162]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_162 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_162_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[162].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_162_qs)
  );

  //   F[filter_163]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_163 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_163_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[163].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_163_qs)
  );

  //   F[filter_164]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_164 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_164_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[164].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_164_qs)
  );

  //   F[filter_165]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_165 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_165_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[165].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_165_qs)
  );

  //   F[filter_166]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_166 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_166_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[166].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_166_qs)
  );

  //   F[filter_167]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_167 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_167_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[167].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_167_qs)
  );

  //   F[filter_168]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_168 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_168_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[168].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_168_qs)
  );

  //   F[filter_169]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_169 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_169_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[169].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_169_qs)
  );

  //   F[filter_170]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_170 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_170_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[170].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_170_qs)
  );

  //   F[filter_171]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_171 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_171_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[171].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_171_qs)
  );

  //   F[filter_172]: 12:12
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_172 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_172_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[172].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_172_qs)
  );

  //   F[filter_173]: 13:13
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_173 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_173_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[173].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_173_qs)
  );

  //   F[filter_174]: 14:14
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_174 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_174_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[174].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_174_qs)
  );

  //   F[filter_175]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_175 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_175_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[175].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_175_qs)
  );

  //   F[filter_176]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_176 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_176_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[176].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_176_qs)
  );

  //   F[filter_177]: 17:17
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_177 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_177_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[177].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_177_qs)
  );

  //   F[filter_178]: 18:18
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_178 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_178_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[178].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_178_qs)
  );

  //   F[filter_179]: 19:19
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_179 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_179_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[179].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_179_qs)
  );

  //   F[filter_180]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_180 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_180_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[180].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_180_qs)
  );

  //   F[filter_181]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_181 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_181_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[181].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_181_qs)
  );

  //   F[filter_182]: 22:22
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_182 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_182_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[182].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_182_qs)
  );

  //   F[filter_183]: 23:23
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_183 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_183_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[183].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_183_qs)
  );

  //   F[filter_184]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_184 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_184_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[184].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_184_qs)
  );

  //   F[filter_185]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_185 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_185_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[185].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_185_qs)
  );

  //   F[filter_186]: 26:26
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_186 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_186_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[186].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_186_qs)
  );

  //   F[filter_187]: 27:27
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_187 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_187_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[187].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_187_qs)
  );

  //   F[filter_188]: 28:28
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_188 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_188_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[188].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_188_qs)
  );

  //   F[filter_189]: 29:29
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_189 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_189_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[189].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_189_qs)
  );

  //   F[filter_190]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_190 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_190_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[190].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_190_qs)
  );

  //   F[filter_191]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_5_filter_191 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_5_we),
    .wd     (cmd_filter_5_filter_191_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[191].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_5_filter_191_qs)
  );


  // Subregister 6 of Multireg cmd_filter
  // R[cmd_filter_6]: V(False)
  //   F[filter_192]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_192 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_192_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[192].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_192_qs)
  );

  //   F[filter_193]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_193 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_193_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[193].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_193_qs)
  );

  //   F[filter_194]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_194 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_194_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[194].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_194_qs)
  );

  //   F[filter_195]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_195 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_195_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[195].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_195_qs)
  );

  //   F[filter_196]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_196 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_196_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[196].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_196_qs)
  );

  //   F[filter_197]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_197 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_197_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[197].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_197_qs)
  );

  //   F[filter_198]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_198 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_198_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[198].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_198_qs)
  );

  //   F[filter_199]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_199 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_199_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[199].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_199_qs)
  );

  //   F[filter_200]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_200 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_200_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[200].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_200_qs)
  );

  //   F[filter_201]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_201 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_201_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[201].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_201_qs)
  );

  //   F[filter_202]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_202 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_202_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[202].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_202_qs)
  );

  //   F[filter_203]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_203 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_203_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[203].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_203_qs)
  );

  //   F[filter_204]: 12:12
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_204 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_204_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[204].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_204_qs)
  );

  //   F[filter_205]: 13:13
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_205 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_205_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[205].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_205_qs)
  );

  //   F[filter_206]: 14:14
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_206 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_206_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[206].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_206_qs)
  );

  //   F[filter_207]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_207 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_207_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[207].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_207_qs)
  );

  //   F[filter_208]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_208 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_208_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[208].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_208_qs)
  );

  //   F[filter_209]: 17:17
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_209 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_209_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[209].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_209_qs)
  );

  //   F[filter_210]: 18:18
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_210 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_210_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[210].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_210_qs)
  );

  //   F[filter_211]: 19:19
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_211 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_211_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[211].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_211_qs)
  );

  //   F[filter_212]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_212 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_212_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[212].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_212_qs)
  );

  //   F[filter_213]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_213 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_213_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[213].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_213_qs)
  );

  //   F[filter_214]: 22:22
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_214 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_214_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[214].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_214_qs)
  );

  //   F[filter_215]: 23:23
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_215 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_215_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[215].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_215_qs)
  );

  //   F[filter_216]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_216 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_216_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[216].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_216_qs)
  );

  //   F[filter_217]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_217 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_217_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[217].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_217_qs)
  );

  //   F[filter_218]: 26:26
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_218 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_218_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[218].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_218_qs)
  );

  //   F[filter_219]: 27:27
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_219 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_219_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[219].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_219_qs)
  );

  //   F[filter_220]: 28:28
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_220 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_220_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[220].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_220_qs)
  );

  //   F[filter_221]: 29:29
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_221 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_221_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[221].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_221_qs)
  );

  //   F[filter_222]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_222 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_222_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[222].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_222_qs)
  );

  //   F[filter_223]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_6_filter_223 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_6_we),
    .wd     (cmd_filter_6_filter_223_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[223].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_6_filter_223_qs)
  );


  // Subregister 7 of Multireg cmd_filter
  // R[cmd_filter_7]: V(False)
  //   F[filter_224]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_224 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_224_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[224].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_224_qs)
  );

  //   F[filter_225]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_225 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_225_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[225].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_225_qs)
  );

  //   F[filter_226]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_226 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_226_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[226].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_226_qs)
  );

  //   F[filter_227]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_227 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_227_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[227].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_227_qs)
  );

  //   F[filter_228]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_228 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_228_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[228].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_228_qs)
  );

  //   F[filter_229]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_229 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_229_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[229].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_229_qs)
  );

  //   F[filter_230]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_230 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_230_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[230].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_230_qs)
  );

  //   F[filter_231]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_231 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_231_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[231].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_231_qs)
  );

  //   F[filter_232]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_232 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_232_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[232].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_232_qs)
  );

  //   F[filter_233]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_233 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_233_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[233].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_233_qs)
  );

  //   F[filter_234]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_234 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_234_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[234].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_234_qs)
  );

  //   F[filter_235]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_235 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_235_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[235].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_235_qs)
  );

  //   F[filter_236]: 12:12
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_236 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_236_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[236].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_236_qs)
  );

  //   F[filter_237]: 13:13
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_237 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_237_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[237].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_237_qs)
  );

  //   F[filter_238]: 14:14
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_238 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_238_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[238].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_238_qs)
  );

  //   F[filter_239]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_239 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_239_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[239].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_239_qs)
  );

  //   F[filter_240]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_240 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_240_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[240].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_240_qs)
  );

  //   F[filter_241]: 17:17
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_241 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_241_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[241].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_241_qs)
  );

  //   F[filter_242]: 18:18
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_242 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_242_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[242].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_242_qs)
  );

  //   F[filter_243]: 19:19
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_243 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_243_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[243].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_243_qs)
  );

  //   F[filter_244]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_244 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_244_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[244].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_244_qs)
  );

  //   F[filter_245]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_245 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_245_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[245].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_245_qs)
  );

  //   F[filter_246]: 22:22
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_246 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_246_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[246].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_246_qs)
  );

  //   F[filter_247]: 23:23
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_247 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_247_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[247].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_247_qs)
  );

  //   F[filter_248]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_248 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_248_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[248].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_248_qs)
  );

  //   F[filter_249]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_249 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_249_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[249].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_249_qs)
  );

  //   F[filter_250]: 26:26
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_250 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_250_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[250].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_250_qs)
  );

  //   F[filter_251]: 27:27
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_251 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_251_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[251].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_251_qs)
  );

  //   F[filter_252]: 28:28
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_252 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_252_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[252].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_252_qs)
  );

  //   F[filter_253]: 29:29
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_253 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_253_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[253].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_253_qs)
  );

  //   F[filter_254]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_254 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_254_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[254].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_254_qs)
  );

  //   F[filter_255]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_filter_7_filter_255 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_filter_7_we),
    .wd     (cmd_filter_7_filter_255_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_filter[255].q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_filter_7_filter_255_qs)
  );


  // R[addr_swap_mask]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_addr_swap_mask (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (addr_swap_mask_we),
    .wd     (addr_swap_mask_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.addr_swap_mask.q),
    .ds     (),

    // to register interface (read)
    .qs     (addr_swap_mask_qs)
  );


  // R[addr_swap_data]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_addr_swap_data (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (addr_swap_data_we),
    .wd     (addr_swap_data_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.addr_swap_data.q),
    .ds     (),

    // to register interface (read)
    .qs     (addr_swap_data_qs)
  );


  // R[payload_swap_mask]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_payload_swap_mask (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (payload_swap_mask_we),
    .wd     (payload_swap_mask_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.payload_swap_mask.q),
    .ds     (),

    // to register interface (read)
    .qs     (payload_swap_mask_qs)
  );


  // R[payload_swap_data]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_payload_swap_data (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (payload_swap_data_we),
    .wd     (payload_swap_data_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.payload_swap_data.q),
    .ds     (),

    // to register interface (read)
    .qs     (payload_swap_data_qs)
  );


  // Subregister 0 of Multireg cmd_info
  // R[cmd_info_0]: V(False)
  //   F[opcode_0]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_opcode_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_opcode_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_opcode_0_qs)
  );

  //   F[addr_mode_0]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_addr_mode_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_addr_mode_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_addr_mode_0_qs)
  );

  //   F[addr_swap_en_0]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_addr_swap_en_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_addr_swap_en_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_addr_swap_en_0_qs)
  );

  //   F[mbyte_en_0]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_mbyte_en_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_mbyte_en_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_mbyte_en_0_qs)
  );

  //   F[dummy_size_0]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_0_dummy_size_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_dummy_size_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_dummy_size_0_qs)
  );

  //   F[dummy_en_0]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_dummy_en_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_dummy_en_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_dummy_en_0_qs)
  );

  //   F[payload_en_0]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_payload_en_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_payload_en_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_payload_en_0_qs)
  );

  //   F[payload_dir_0]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_payload_dir_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_payload_dir_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_payload_dir_0_qs)
  );

  //   F[payload_swap_en_0]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_payload_swap_en_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_payload_swap_en_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_payload_swap_en_0_qs)
  );

  //   F[read_pipeline_mode_0]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_read_pipeline_mode_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_read_pipeline_mode_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_read_pipeline_mode_0_qs)
  );

  //   F[upload_0]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_upload_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_upload_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_upload_0_qs)
  );

  //   F[busy_0]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_busy_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_busy_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_busy_0_qs)
  );

  //   F[valid_0]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_0_valid_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_0_we),
    .wd     (cmd_info_0_valid_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[0].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_0_valid_0_qs)
  );


  // Subregister 1 of Multireg cmd_info
  // R[cmd_info_1]: V(False)
  //   F[opcode_1]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_opcode_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_opcode_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_opcode_1_qs)
  );

  //   F[addr_mode_1]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_addr_mode_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_addr_mode_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_addr_mode_1_qs)
  );

  //   F[addr_swap_en_1]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_addr_swap_en_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_addr_swap_en_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_addr_swap_en_1_qs)
  );

  //   F[mbyte_en_1]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_mbyte_en_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_mbyte_en_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_mbyte_en_1_qs)
  );

  //   F[dummy_size_1]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_1_dummy_size_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_dummy_size_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_dummy_size_1_qs)
  );

  //   F[dummy_en_1]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_dummy_en_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_dummy_en_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_dummy_en_1_qs)
  );

  //   F[payload_en_1]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_payload_en_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_payload_en_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_payload_en_1_qs)
  );

  //   F[payload_dir_1]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_payload_dir_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_payload_dir_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_payload_dir_1_qs)
  );

  //   F[payload_swap_en_1]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_payload_swap_en_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_payload_swap_en_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_payload_swap_en_1_qs)
  );

  //   F[read_pipeline_mode_1]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_read_pipeline_mode_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_read_pipeline_mode_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_read_pipeline_mode_1_qs)
  );

  //   F[upload_1]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_upload_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_upload_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_upload_1_qs)
  );

  //   F[busy_1]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_busy_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_busy_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_busy_1_qs)
  );

  //   F[valid_1]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_1_valid_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_1_we),
    .wd     (cmd_info_1_valid_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[1].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_1_valid_1_qs)
  );


  // Subregister 2 of Multireg cmd_info
  // R[cmd_info_2]: V(False)
  //   F[opcode_2]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_opcode_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_opcode_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_opcode_2_qs)
  );

  //   F[addr_mode_2]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_addr_mode_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_addr_mode_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_addr_mode_2_qs)
  );

  //   F[addr_swap_en_2]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_addr_swap_en_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_addr_swap_en_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_addr_swap_en_2_qs)
  );

  //   F[mbyte_en_2]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_mbyte_en_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_mbyte_en_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_mbyte_en_2_qs)
  );

  //   F[dummy_size_2]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_2_dummy_size_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_dummy_size_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_dummy_size_2_qs)
  );

  //   F[dummy_en_2]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_dummy_en_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_dummy_en_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_dummy_en_2_qs)
  );

  //   F[payload_en_2]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_payload_en_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_payload_en_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_payload_en_2_qs)
  );

  //   F[payload_dir_2]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_payload_dir_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_payload_dir_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_payload_dir_2_qs)
  );

  //   F[payload_swap_en_2]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_payload_swap_en_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_payload_swap_en_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_payload_swap_en_2_qs)
  );

  //   F[read_pipeline_mode_2]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_read_pipeline_mode_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_read_pipeline_mode_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_read_pipeline_mode_2_qs)
  );

  //   F[upload_2]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_upload_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_upload_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_upload_2_qs)
  );

  //   F[busy_2]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_busy_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_busy_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_busy_2_qs)
  );

  //   F[valid_2]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_2_valid_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_2_we),
    .wd     (cmd_info_2_valid_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[2].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_2_valid_2_qs)
  );


  // Subregister 3 of Multireg cmd_info
  // R[cmd_info_3]: V(False)
  //   F[opcode_3]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_opcode_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_opcode_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_opcode_3_qs)
  );

  //   F[addr_mode_3]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_addr_mode_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_addr_mode_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_addr_mode_3_qs)
  );

  //   F[addr_swap_en_3]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_addr_swap_en_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_addr_swap_en_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_addr_swap_en_3_qs)
  );

  //   F[mbyte_en_3]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_mbyte_en_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_mbyte_en_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_mbyte_en_3_qs)
  );

  //   F[dummy_size_3]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_3_dummy_size_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_dummy_size_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_dummy_size_3_qs)
  );

  //   F[dummy_en_3]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_dummy_en_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_dummy_en_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_dummy_en_3_qs)
  );

  //   F[payload_en_3]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_payload_en_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_payload_en_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_payload_en_3_qs)
  );

  //   F[payload_dir_3]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_payload_dir_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_payload_dir_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_payload_dir_3_qs)
  );

  //   F[payload_swap_en_3]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_payload_swap_en_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_payload_swap_en_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_payload_swap_en_3_qs)
  );

  //   F[read_pipeline_mode_3]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_read_pipeline_mode_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_read_pipeline_mode_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_read_pipeline_mode_3_qs)
  );

  //   F[upload_3]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_upload_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_upload_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_upload_3_qs)
  );

  //   F[busy_3]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_busy_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_busy_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_busy_3_qs)
  );

  //   F[valid_3]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_3_valid_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_3_we),
    .wd     (cmd_info_3_valid_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[3].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_3_valid_3_qs)
  );


  // Subregister 4 of Multireg cmd_info
  // R[cmd_info_4]: V(False)
  //   F[opcode_4]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_opcode_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_opcode_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_opcode_4_qs)
  );

  //   F[addr_mode_4]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_addr_mode_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_addr_mode_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_addr_mode_4_qs)
  );

  //   F[addr_swap_en_4]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_addr_swap_en_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_addr_swap_en_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_addr_swap_en_4_qs)
  );

  //   F[mbyte_en_4]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_mbyte_en_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_mbyte_en_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_mbyte_en_4_qs)
  );

  //   F[dummy_size_4]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_4_dummy_size_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_dummy_size_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_dummy_size_4_qs)
  );

  //   F[dummy_en_4]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_dummy_en_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_dummy_en_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_dummy_en_4_qs)
  );

  //   F[payload_en_4]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_payload_en_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_payload_en_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_payload_en_4_qs)
  );

  //   F[payload_dir_4]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_payload_dir_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_payload_dir_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_payload_dir_4_qs)
  );

  //   F[payload_swap_en_4]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_payload_swap_en_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_payload_swap_en_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_payload_swap_en_4_qs)
  );

  //   F[read_pipeline_mode_4]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_read_pipeline_mode_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_read_pipeline_mode_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_read_pipeline_mode_4_qs)
  );

  //   F[upload_4]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_upload_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_upload_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_upload_4_qs)
  );

  //   F[busy_4]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_busy_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_busy_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_busy_4_qs)
  );

  //   F[valid_4]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_4_valid_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_4_we),
    .wd     (cmd_info_4_valid_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[4].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_4_valid_4_qs)
  );


  // Subregister 5 of Multireg cmd_info
  // R[cmd_info_5]: V(False)
  //   F[opcode_5]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_opcode_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_opcode_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_opcode_5_qs)
  );

  //   F[addr_mode_5]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_addr_mode_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_addr_mode_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_addr_mode_5_qs)
  );

  //   F[addr_swap_en_5]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_addr_swap_en_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_addr_swap_en_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_addr_swap_en_5_qs)
  );

  //   F[mbyte_en_5]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_mbyte_en_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_mbyte_en_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_mbyte_en_5_qs)
  );

  //   F[dummy_size_5]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_5_dummy_size_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_dummy_size_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_dummy_size_5_qs)
  );

  //   F[dummy_en_5]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_dummy_en_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_dummy_en_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_dummy_en_5_qs)
  );

  //   F[payload_en_5]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_payload_en_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_payload_en_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_payload_en_5_qs)
  );

  //   F[payload_dir_5]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_payload_dir_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_payload_dir_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_payload_dir_5_qs)
  );

  //   F[payload_swap_en_5]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_payload_swap_en_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_payload_swap_en_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_payload_swap_en_5_qs)
  );

  //   F[read_pipeline_mode_5]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_read_pipeline_mode_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_read_pipeline_mode_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_read_pipeline_mode_5_qs)
  );

  //   F[upload_5]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_upload_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_upload_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_upload_5_qs)
  );

  //   F[busy_5]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_busy_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_busy_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_busy_5_qs)
  );

  //   F[valid_5]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_5_valid_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_5_we),
    .wd     (cmd_info_5_valid_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[5].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_5_valid_5_qs)
  );


  // Subregister 6 of Multireg cmd_info
  // R[cmd_info_6]: V(False)
  //   F[opcode_6]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_opcode_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_opcode_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_opcode_6_qs)
  );

  //   F[addr_mode_6]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_addr_mode_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_addr_mode_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_addr_mode_6_qs)
  );

  //   F[addr_swap_en_6]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_addr_swap_en_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_addr_swap_en_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_addr_swap_en_6_qs)
  );

  //   F[mbyte_en_6]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_mbyte_en_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_mbyte_en_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_mbyte_en_6_qs)
  );

  //   F[dummy_size_6]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_6_dummy_size_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_dummy_size_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_dummy_size_6_qs)
  );

  //   F[dummy_en_6]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_dummy_en_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_dummy_en_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_dummy_en_6_qs)
  );

  //   F[payload_en_6]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_payload_en_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_payload_en_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_payload_en_6_qs)
  );

  //   F[payload_dir_6]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_payload_dir_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_payload_dir_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_payload_dir_6_qs)
  );

  //   F[payload_swap_en_6]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_payload_swap_en_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_payload_swap_en_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_payload_swap_en_6_qs)
  );

  //   F[read_pipeline_mode_6]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_read_pipeline_mode_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_read_pipeline_mode_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_read_pipeline_mode_6_qs)
  );

  //   F[upload_6]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_upload_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_upload_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_upload_6_qs)
  );

  //   F[busy_6]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_busy_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_busy_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_busy_6_qs)
  );

  //   F[valid_6]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_6_valid_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_6_we),
    .wd     (cmd_info_6_valid_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[6].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_6_valid_6_qs)
  );


  // Subregister 7 of Multireg cmd_info
  // R[cmd_info_7]: V(False)
  //   F[opcode_7]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_opcode_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_opcode_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_opcode_7_qs)
  );

  //   F[addr_mode_7]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_addr_mode_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_addr_mode_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_addr_mode_7_qs)
  );

  //   F[addr_swap_en_7]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_addr_swap_en_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_addr_swap_en_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_addr_swap_en_7_qs)
  );

  //   F[mbyte_en_7]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_mbyte_en_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_mbyte_en_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_mbyte_en_7_qs)
  );

  //   F[dummy_size_7]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_7_dummy_size_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_dummy_size_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_dummy_size_7_qs)
  );

  //   F[dummy_en_7]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_dummy_en_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_dummy_en_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_dummy_en_7_qs)
  );

  //   F[payload_en_7]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_payload_en_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_payload_en_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_payload_en_7_qs)
  );

  //   F[payload_dir_7]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_payload_dir_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_payload_dir_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_payload_dir_7_qs)
  );

  //   F[payload_swap_en_7]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_payload_swap_en_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_payload_swap_en_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_payload_swap_en_7_qs)
  );

  //   F[read_pipeline_mode_7]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_read_pipeline_mode_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_read_pipeline_mode_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_read_pipeline_mode_7_qs)
  );

  //   F[upload_7]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_upload_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_upload_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_upload_7_qs)
  );

  //   F[busy_7]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_busy_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_busy_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_busy_7_qs)
  );

  //   F[valid_7]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_7_valid_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_7_we),
    .wd     (cmd_info_7_valid_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[7].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_7_valid_7_qs)
  );


  // Subregister 8 of Multireg cmd_info
  // R[cmd_info_8]: V(False)
  //   F[opcode_8]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_opcode_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_opcode_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_opcode_8_qs)
  );

  //   F[addr_mode_8]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_addr_mode_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_addr_mode_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_addr_mode_8_qs)
  );

  //   F[addr_swap_en_8]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_addr_swap_en_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_addr_swap_en_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_addr_swap_en_8_qs)
  );

  //   F[mbyte_en_8]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_mbyte_en_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_mbyte_en_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_mbyte_en_8_qs)
  );

  //   F[dummy_size_8]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_8_dummy_size_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_dummy_size_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_dummy_size_8_qs)
  );

  //   F[dummy_en_8]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_dummy_en_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_dummy_en_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_dummy_en_8_qs)
  );

  //   F[payload_en_8]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_payload_en_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_payload_en_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_payload_en_8_qs)
  );

  //   F[payload_dir_8]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_payload_dir_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_payload_dir_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_payload_dir_8_qs)
  );

  //   F[payload_swap_en_8]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_payload_swap_en_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_payload_swap_en_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_payload_swap_en_8_qs)
  );

  //   F[read_pipeline_mode_8]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_read_pipeline_mode_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_read_pipeline_mode_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_read_pipeline_mode_8_qs)
  );

  //   F[upload_8]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_upload_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_upload_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_upload_8_qs)
  );

  //   F[busy_8]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_busy_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_busy_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_busy_8_qs)
  );

  //   F[valid_8]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_8_valid_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_8_we),
    .wd     (cmd_info_8_valid_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[8].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_8_valid_8_qs)
  );


  // Subregister 9 of Multireg cmd_info
  // R[cmd_info_9]: V(False)
  //   F[opcode_9]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_opcode_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_opcode_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_opcode_9_qs)
  );

  //   F[addr_mode_9]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_addr_mode_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_addr_mode_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_addr_mode_9_qs)
  );

  //   F[addr_swap_en_9]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_addr_swap_en_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_addr_swap_en_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_addr_swap_en_9_qs)
  );

  //   F[mbyte_en_9]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_mbyte_en_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_mbyte_en_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_mbyte_en_9_qs)
  );

  //   F[dummy_size_9]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_9_dummy_size_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_dummy_size_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_dummy_size_9_qs)
  );

  //   F[dummy_en_9]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_dummy_en_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_dummy_en_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_dummy_en_9_qs)
  );

  //   F[payload_en_9]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_payload_en_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_payload_en_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_payload_en_9_qs)
  );

  //   F[payload_dir_9]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_payload_dir_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_payload_dir_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_payload_dir_9_qs)
  );

  //   F[payload_swap_en_9]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_payload_swap_en_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_payload_swap_en_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_payload_swap_en_9_qs)
  );

  //   F[read_pipeline_mode_9]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_read_pipeline_mode_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_read_pipeline_mode_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_read_pipeline_mode_9_qs)
  );

  //   F[upload_9]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_upload_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_upload_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_upload_9_qs)
  );

  //   F[busy_9]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_busy_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_busy_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_busy_9_qs)
  );

  //   F[valid_9]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_9_valid_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_9_we),
    .wd     (cmd_info_9_valid_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[9].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_9_valid_9_qs)
  );


  // Subregister 10 of Multireg cmd_info
  // R[cmd_info_10]: V(False)
  //   F[opcode_10]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_opcode_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_opcode_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_opcode_10_qs)
  );

  //   F[addr_mode_10]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_addr_mode_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_addr_mode_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_addr_mode_10_qs)
  );

  //   F[addr_swap_en_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_addr_swap_en_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_addr_swap_en_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_addr_swap_en_10_qs)
  );

  //   F[mbyte_en_10]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_mbyte_en_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_mbyte_en_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_mbyte_en_10_qs)
  );

  //   F[dummy_size_10]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_10_dummy_size_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_dummy_size_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_dummy_size_10_qs)
  );

  //   F[dummy_en_10]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_dummy_en_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_dummy_en_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_dummy_en_10_qs)
  );

  //   F[payload_en_10]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_payload_en_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_payload_en_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_payload_en_10_qs)
  );

  //   F[payload_dir_10]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_payload_dir_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_payload_dir_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_payload_dir_10_qs)
  );

  //   F[payload_swap_en_10]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_payload_swap_en_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_payload_swap_en_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_payload_swap_en_10_qs)
  );

  //   F[read_pipeline_mode_10]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_read_pipeline_mode_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_read_pipeline_mode_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_read_pipeline_mode_10_qs)
  );

  //   F[upload_10]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_upload_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_upload_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_upload_10_qs)
  );

  //   F[busy_10]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_busy_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_busy_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_busy_10_qs)
  );

  //   F[valid_10]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_10_valid_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_10_we),
    .wd     (cmd_info_10_valid_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[10].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_10_valid_10_qs)
  );


  // Subregister 11 of Multireg cmd_info
  // R[cmd_info_11]: V(False)
  //   F[opcode_11]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_opcode_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_opcode_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_opcode_11_qs)
  );

  //   F[addr_mode_11]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_addr_mode_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_addr_mode_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_addr_mode_11_qs)
  );

  //   F[addr_swap_en_11]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_addr_swap_en_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_addr_swap_en_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_addr_swap_en_11_qs)
  );

  //   F[mbyte_en_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_mbyte_en_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_mbyte_en_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_mbyte_en_11_qs)
  );

  //   F[dummy_size_11]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_11_dummy_size_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_dummy_size_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_dummy_size_11_qs)
  );

  //   F[dummy_en_11]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_dummy_en_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_dummy_en_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_dummy_en_11_qs)
  );

  //   F[payload_en_11]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_payload_en_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_payload_en_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_payload_en_11_qs)
  );

  //   F[payload_dir_11]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_payload_dir_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_payload_dir_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_payload_dir_11_qs)
  );

  //   F[payload_swap_en_11]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_payload_swap_en_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_payload_swap_en_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_payload_swap_en_11_qs)
  );

  //   F[read_pipeline_mode_11]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_read_pipeline_mode_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_read_pipeline_mode_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_read_pipeline_mode_11_qs)
  );

  //   F[upload_11]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_upload_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_upload_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_upload_11_qs)
  );

  //   F[busy_11]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_busy_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_busy_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_busy_11_qs)
  );

  //   F[valid_11]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_11_valid_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_11_we),
    .wd     (cmd_info_11_valid_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[11].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_11_valid_11_qs)
  );


  // Subregister 12 of Multireg cmd_info
  // R[cmd_info_12]: V(False)
  //   F[opcode_12]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_opcode_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_opcode_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_opcode_12_qs)
  );

  //   F[addr_mode_12]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_addr_mode_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_addr_mode_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_addr_mode_12_qs)
  );

  //   F[addr_swap_en_12]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_addr_swap_en_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_addr_swap_en_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_addr_swap_en_12_qs)
  );

  //   F[mbyte_en_12]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_mbyte_en_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_mbyte_en_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_mbyte_en_12_qs)
  );

  //   F[dummy_size_12]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_12_dummy_size_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_dummy_size_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_dummy_size_12_qs)
  );

  //   F[dummy_en_12]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_dummy_en_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_dummy_en_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_dummy_en_12_qs)
  );

  //   F[payload_en_12]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_payload_en_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_payload_en_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_payload_en_12_qs)
  );

  //   F[payload_dir_12]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_payload_dir_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_payload_dir_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_payload_dir_12_qs)
  );

  //   F[payload_swap_en_12]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_payload_swap_en_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_payload_swap_en_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_payload_swap_en_12_qs)
  );

  //   F[read_pipeline_mode_12]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_read_pipeline_mode_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_read_pipeline_mode_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_read_pipeline_mode_12_qs)
  );

  //   F[upload_12]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_upload_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_upload_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_upload_12_qs)
  );

  //   F[busy_12]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_busy_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_busy_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_busy_12_qs)
  );

  //   F[valid_12]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_12_valid_12 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_12_we),
    .wd     (cmd_info_12_valid_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[12].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_12_valid_12_qs)
  );


  // Subregister 13 of Multireg cmd_info
  // R[cmd_info_13]: V(False)
  //   F[opcode_13]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_opcode_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_opcode_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_opcode_13_qs)
  );

  //   F[addr_mode_13]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_addr_mode_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_addr_mode_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_addr_mode_13_qs)
  );

  //   F[addr_swap_en_13]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_addr_swap_en_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_addr_swap_en_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_addr_swap_en_13_qs)
  );

  //   F[mbyte_en_13]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_mbyte_en_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_mbyte_en_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_mbyte_en_13_qs)
  );

  //   F[dummy_size_13]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_13_dummy_size_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_dummy_size_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_dummy_size_13_qs)
  );

  //   F[dummy_en_13]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_dummy_en_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_dummy_en_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_dummy_en_13_qs)
  );

  //   F[payload_en_13]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_payload_en_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_payload_en_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_payload_en_13_qs)
  );

  //   F[payload_dir_13]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_payload_dir_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_payload_dir_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_payload_dir_13_qs)
  );

  //   F[payload_swap_en_13]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_payload_swap_en_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_payload_swap_en_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_payload_swap_en_13_qs)
  );

  //   F[read_pipeline_mode_13]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_read_pipeline_mode_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_read_pipeline_mode_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_read_pipeline_mode_13_qs)
  );

  //   F[upload_13]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_upload_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_upload_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_upload_13_qs)
  );

  //   F[busy_13]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_busy_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_busy_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_busy_13_qs)
  );

  //   F[valid_13]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_13_valid_13 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_13_we),
    .wd     (cmd_info_13_valid_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[13].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_13_valid_13_qs)
  );


  // Subregister 14 of Multireg cmd_info
  // R[cmd_info_14]: V(False)
  //   F[opcode_14]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_opcode_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_opcode_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_opcode_14_qs)
  );

  //   F[addr_mode_14]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_addr_mode_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_addr_mode_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_addr_mode_14_qs)
  );

  //   F[addr_swap_en_14]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_addr_swap_en_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_addr_swap_en_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_addr_swap_en_14_qs)
  );

  //   F[mbyte_en_14]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_mbyte_en_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_mbyte_en_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_mbyte_en_14_qs)
  );

  //   F[dummy_size_14]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_14_dummy_size_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_dummy_size_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_dummy_size_14_qs)
  );

  //   F[dummy_en_14]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_dummy_en_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_dummy_en_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_dummy_en_14_qs)
  );

  //   F[payload_en_14]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_payload_en_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_payload_en_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_payload_en_14_qs)
  );

  //   F[payload_dir_14]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_payload_dir_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_payload_dir_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_payload_dir_14_qs)
  );

  //   F[payload_swap_en_14]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_payload_swap_en_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_payload_swap_en_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_payload_swap_en_14_qs)
  );

  //   F[read_pipeline_mode_14]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_read_pipeline_mode_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_read_pipeline_mode_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_read_pipeline_mode_14_qs)
  );

  //   F[upload_14]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_upload_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_upload_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_upload_14_qs)
  );

  //   F[busy_14]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_busy_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_busy_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_busy_14_qs)
  );

  //   F[valid_14]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_14_valid_14 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_14_we),
    .wd     (cmd_info_14_valid_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[14].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_14_valid_14_qs)
  );


  // Subregister 15 of Multireg cmd_info
  // R[cmd_info_15]: V(False)
  //   F[opcode_15]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_opcode_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_opcode_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_opcode_15_qs)
  );

  //   F[addr_mode_15]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_addr_mode_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_addr_mode_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_addr_mode_15_qs)
  );

  //   F[addr_swap_en_15]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_addr_swap_en_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_addr_swap_en_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_addr_swap_en_15_qs)
  );

  //   F[mbyte_en_15]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_mbyte_en_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_mbyte_en_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_mbyte_en_15_qs)
  );

  //   F[dummy_size_15]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_15_dummy_size_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_dummy_size_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_dummy_size_15_qs)
  );

  //   F[dummy_en_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_dummy_en_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_dummy_en_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_dummy_en_15_qs)
  );

  //   F[payload_en_15]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_payload_en_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_payload_en_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_payload_en_15_qs)
  );

  //   F[payload_dir_15]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_payload_dir_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_payload_dir_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_payload_dir_15_qs)
  );

  //   F[payload_swap_en_15]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_payload_swap_en_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_payload_swap_en_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_payload_swap_en_15_qs)
  );

  //   F[read_pipeline_mode_15]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_read_pipeline_mode_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_read_pipeline_mode_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_read_pipeline_mode_15_qs)
  );

  //   F[upload_15]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_upload_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_upload_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_upload_15_qs)
  );

  //   F[busy_15]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_busy_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_busy_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_busy_15_qs)
  );

  //   F[valid_15]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_15_valid_15 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_15_we),
    .wd     (cmd_info_15_valid_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[15].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_15_valid_15_qs)
  );


  // Subregister 16 of Multireg cmd_info
  // R[cmd_info_16]: V(False)
  //   F[opcode_16]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_opcode_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_opcode_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_opcode_16_qs)
  );

  //   F[addr_mode_16]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_addr_mode_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_addr_mode_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_addr_mode_16_qs)
  );

  //   F[addr_swap_en_16]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_addr_swap_en_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_addr_swap_en_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_addr_swap_en_16_qs)
  );

  //   F[mbyte_en_16]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_mbyte_en_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_mbyte_en_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_mbyte_en_16_qs)
  );

  //   F[dummy_size_16]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_16_dummy_size_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_dummy_size_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_dummy_size_16_qs)
  );

  //   F[dummy_en_16]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_dummy_en_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_dummy_en_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_dummy_en_16_qs)
  );

  //   F[payload_en_16]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_payload_en_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_payload_en_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_payload_en_16_qs)
  );

  //   F[payload_dir_16]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_payload_dir_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_payload_dir_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_payload_dir_16_qs)
  );

  //   F[payload_swap_en_16]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_payload_swap_en_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_payload_swap_en_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_payload_swap_en_16_qs)
  );

  //   F[read_pipeline_mode_16]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_read_pipeline_mode_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_read_pipeline_mode_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_read_pipeline_mode_16_qs)
  );

  //   F[upload_16]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_upload_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_upload_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_upload_16_qs)
  );

  //   F[busy_16]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_busy_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_busy_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_busy_16_qs)
  );

  //   F[valid_16]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_16_valid_16 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_16_we),
    .wd     (cmd_info_16_valid_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[16].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_16_valid_16_qs)
  );


  // Subregister 17 of Multireg cmd_info
  // R[cmd_info_17]: V(False)
  //   F[opcode_17]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_opcode_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_opcode_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_opcode_17_qs)
  );

  //   F[addr_mode_17]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_addr_mode_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_addr_mode_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_addr_mode_17_qs)
  );

  //   F[addr_swap_en_17]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_addr_swap_en_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_addr_swap_en_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_addr_swap_en_17_qs)
  );

  //   F[mbyte_en_17]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_mbyte_en_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_mbyte_en_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_mbyte_en_17_qs)
  );

  //   F[dummy_size_17]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_17_dummy_size_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_dummy_size_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_dummy_size_17_qs)
  );

  //   F[dummy_en_17]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_dummy_en_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_dummy_en_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_dummy_en_17_qs)
  );

  //   F[payload_en_17]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_payload_en_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_payload_en_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_payload_en_17_qs)
  );

  //   F[payload_dir_17]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_payload_dir_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_payload_dir_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_payload_dir_17_qs)
  );

  //   F[payload_swap_en_17]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_payload_swap_en_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_payload_swap_en_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_payload_swap_en_17_qs)
  );

  //   F[read_pipeline_mode_17]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_read_pipeline_mode_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_read_pipeline_mode_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_read_pipeline_mode_17_qs)
  );

  //   F[upload_17]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_upload_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_upload_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_upload_17_qs)
  );

  //   F[busy_17]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_busy_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_busy_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_busy_17_qs)
  );

  //   F[valid_17]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_17_valid_17 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_17_we),
    .wd     (cmd_info_17_valid_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[17].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_17_valid_17_qs)
  );


  // Subregister 18 of Multireg cmd_info
  // R[cmd_info_18]: V(False)
  //   F[opcode_18]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_opcode_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_opcode_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_opcode_18_qs)
  );

  //   F[addr_mode_18]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_addr_mode_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_addr_mode_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_addr_mode_18_qs)
  );

  //   F[addr_swap_en_18]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_addr_swap_en_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_addr_swap_en_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_addr_swap_en_18_qs)
  );

  //   F[mbyte_en_18]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_mbyte_en_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_mbyte_en_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_mbyte_en_18_qs)
  );

  //   F[dummy_size_18]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_18_dummy_size_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_dummy_size_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_dummy_size_18_qs)
  );

  //   F[dummy_en_18]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_dummy_en_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_dummy_en_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_dummy_en_18_qs)
  );

  //   F[payload_en_18]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_payload_en_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_payload_en_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_payload_en_18_qs)
  );

  //   F[payload_dir_18]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_payload_dir_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_payload_dir_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_payload_dir_18_qs)
  );

  //   F[payload_swap_en_18]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_payload_swap_en_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_payload_swap_en_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_payload_swap_en_18_qs)
  );

  //   F[read_pipeline_mode_18]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_read_pipeline_mode_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_read_pipeline_mode_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_read_pipeline_mode_18_qs)
  );

  //   F[upload_18]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_upload_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_upload_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_upload_18_qs)
  );

  //   F[busy_18]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_busy_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_busy_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_busy_18_qs)
  );

  //   F[valid_18]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_18_valid_18 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_18_we),
    .wd     (cmd_info_18_valid_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[18].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_18_valid_18_qs)
  );


  // Subregister 19 of Multireg cmd_info
  // R[cmd_info_19]: V(False)
  //   F[opcode_19]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_opcode_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_opcode_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_opcode_19_qs)
  );

  //   F[addr_mode_19]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_addr_mode_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_addr_mode_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_addr_mode_19_qs)
  );

  //   F[addr_swap_en_19]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_addr_swap_en_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_addr_swap_en_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_addr_swap_en_19_qs)
  );

  //   F[mbyte_en_19]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_mbyte_en_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_mbyte_en_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_mbyte_en_19_qs)
  );

  //   F[dummy_size_19]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_19_dummy_size_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_dummy_size_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_dummy_size_19_qs)
  );

  //   F[dummy_en_19]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_dummy_en_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_dummy_en_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_dummy_en_19_qs)
  );

  //   F[payload_en_19]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_payload_en_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_payload_en_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_payload_en_19_qs)
  );

  //   F[payload_dir_19]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_payload_dir_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_payload_dir_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_payload_dir_19_qs)
  );

  //   F[payload_swap_en_19]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_payload_swap_en_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_payload_swap_en_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_payload_swap_en_19_qs)
  );

  //   F[read_pipeline_mode_19]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_read_pipeline_mode_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_read_pipeline_mode_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_read_pipeline_mode_19_qs)
  );

  //   F[upload_19]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_upload_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_upload_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_upload_19_qs)
  );

  //   F[busy_19]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_busy_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_busy_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_busy_19_qs)
  );

  //   F[valid_19]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_19_valid_19 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_19_we),
    .wd     (cmd_info_19_valid_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[19].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_19_valid_19_qs)
  );


  // Subregister 20 of Multireg cmd_info
  // R[cmd_info_20]: V(False)
  //   F[opcode_20]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_opcode_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_opcode_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_opcode_20_qs)
  );

  //   F[addr_mode_20]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_addr_mode_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_addr_mode_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_addr_mode_20_qs)
  );

  //   F[addr_swap_en_20]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_addr_swap_en_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_addr_swap_en_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_addr_swap_en_20_qs)
  );

  //   F[mbyte_en_20]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_mbyte_en_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_mbyte_en_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_mbyte_en_20_qs)
  );

  //   F[dummy_size_20]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_20_dummy_size_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_dummy_size_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_dummy_size_20_qs)
  );

  //   F[dummy_en_20]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_dummy_en_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_dummy_en_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_dummy_en_20_qs)
  );

  //   F[payload_en_20]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_payload_en_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_payload_en_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_payload_en_20_qs)
  );

  //   F[payload_dir_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_payload_dir_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_payload_dir_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_payload_dir_20_qs)
  );

  //   F[payload_swap_en_20]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_payload_swap_en_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_payload_swap_en_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_payload_swap_en_20_qs)
  );

  //   F[read_pipeline_mode_20]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_read_pipeline_mode_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_read_pipeline_mode_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_read_pipeline_mode_20_qs)
  );

  //   F[upload_20]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_upload_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_upload_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_upload_20_qs)
  );

  //   F[busy_20]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_busy_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_busy_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_busy_20_qs)
  );

  //   F[valid_20]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_20_valid_20 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_20_we),
    .wd     (cmd_info_20_valid_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[20].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_20_valid_20_qs)
  );


  // Subregister 21 of Multireg cmd_info
  // R[cmd_info_21]: V(False)
  //   F[opcode_21]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_opcode_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_opcode_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_opcode_21_qs)
  );

  //   F[addr_mode_21]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_addr_mode_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_addr_mode_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_addr_mode_21_qs)
  );

  //   F[addr_swap_en_21]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_addr_swap_en_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_addr_swap_en_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_addr_swap_en_21_qs)
  );

  //   F[mbyte_en_21]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_mbyte_en_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_mbyte_en_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_mbyte_en_21_qs)
  );

  //   F[dummy_size_21]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_21_dummy_size_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_dummy_size_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_dummy_size_21_qs)
  );

  //   F[dummy_en_21]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_dummy_en_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_dummy_en_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_dummy_en_21_qs)
  );

  //   F[payload_en_21]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_payload_en_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_payload_en_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_payload_en_21_qs)
  );

  //   F[payload_dir_21]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_payload_dir_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_payload_dir_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_payload_dir_21_qs)
  );

  //   F[payload_swap_en_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_payload_swap_en_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_payload_swap_en_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_payload_swap_en_21_qs)
  );

  //   F[read_pipeline_mode_21]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_read_pipeline_mode_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_read_pipeline_mode_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_read_pipeline_mode_21_qs)
  );

  //   F[upload_21]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_upload_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_upload_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_upload_21_qs)
  );

  //   F[busy_21]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_busy_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_busy_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_busy_21_qs)
  );

  //   F[valid_21]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_21_valid_21 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_21_we),
    .wd     (cmd_info_21_valid_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[21].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_21_valid_21_qs)
  );


  // Subregister 22 of Multireg cmd_info
  // R[cmd_info_22]: V(False)
  //   F[opcode_22]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_opcode_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_opcode_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_opcode_22_qs)
  );

  //   F[addr_mode_22]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_addr_mode_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_addr_mode_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_addr_mode_22_qs)
  );

  //   F[addr_swap_en_22]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_addr_swap_en_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_addr_swap_en_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_addr_swap_en_22_qs)
  );

  //   F[mbyte_en_22]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_mbyte_en_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_mbyte_en_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_mbyte_en_22_qs)
  );

  //   F[dummy_size_22]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_22_dummy_size_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_dummy_size_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_dummy_size_22_qs)
  );

  //   F[dummy_en_22]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_dummy_en_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_dummy_en_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_dummy_en_22_qs)
  );

  //   F[payload_en_22]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_payload_en_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_payload_en_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_payload_en_22_qs)
  );

  //   F[payload_dir_22]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_payload_dir_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_payload_dir_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_payload_dir_22_qs)
  );

  //   F[payload_swap_en_22]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_payload_swap_en_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_payload_swap_en_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_payload_swap_en_22_qs)
  );

  //   F[read_pipeline_mode_22]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_read_pipeline_mode_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_read_pipeline_mode_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_read_pipeline_mode_22_qs)
  );

  //   F[upload_22]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_upload_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_upload_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_upload_22_qs)
  );

  //   F[busy_22]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_busy_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_busy_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_busy_22_qs)
  );

  //   F[valid_22]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_22_valid_22 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_22_we),
    .wd     (cmd_info_22_valid_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[22].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_22_valid_22_qs)
  );


  // Subregister 23 of Multireg cmd_info
  // R[cmd_info_23]: V(False)
  //   F[opcode_23]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_opcode_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_opcode_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_opcode_23_qs)
  );

  //   F[addr_mode_23]: 9:8
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_addr_mode_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_addr_mode_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].addr_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_addr_mode_23_qs)
  );

  //   F[addr_swap_en_23]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_addr_swap_en_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_addr_swap_en_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].addr_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_addr_swap_en_23_qs)
  );

  //   F[mbyte_en_23]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_mbyte_en_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_mbyte_en_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].mbyte_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_mbyte_en_23_qs)
  );

  //   F[dummy_size_23]: 14:12
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (3'h7),
    .Mubi    (1'b0)
  ) u_cmd_info_23_dummy_size_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_dummy_size_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].dummy_size.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_dummy_size_23_qs)
  );

  //   F[dummy_en_23]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_dummy_en_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_dummy_en_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].dummy_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_dummy_en_23_qs)
  );

  //   F[payload_en_23]: 19:16
  prim_subreg #(
    .DW      (4),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (4'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_payload_en_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_payload_en_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].payload_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_payload_en_23_qs)
  );

  //   F[payload_dir_23]: 20:20
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_payload_dir_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_payload_dir_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].payload_dir.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_payload_dir_23_qs)
  );

  //   F[payload_swap_en_23]: 21:21
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_payload_swap_en_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_payload_swap_en_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].payload_swap_en.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_payload_swap_en_23_qs)
  );

  //   F[read_pipeline_mode_23]: 23:22
  prim_subreg #(
    .DW      (2),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (2'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_read_pipeline_mode_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_read_pipeline_mode_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].read_pipeline_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_read_pipeline_mode_23_qs)
  );

  //   F[upload_23]: 24:24
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_upload_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_upload_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].upload.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_upload_23_qs)
  );

  //   F[busy_23]: 25:25
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_busy_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_busy_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_busy_23_qs)
  );

  //   F[valid_23]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_23_valid_23 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_23_we),
    .wd     (cmd_info_23_valid_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info[23].valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_23_valid_23_qs)
  );


  // R[cmd_info_en4b]: V(False)
  //   F[opcode]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_en4b_opcode (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_en4b_we),
    .wd     (cmd_info_en4b_opcode_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info_en4b.opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_en4b_opcode_qs)
  );

  //   F[valid]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_en4b_valid (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_en4b_we),
    .wd     (cmd_info_en4b_valid_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info_en4b.valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_en4b_valid_qs)
  );


  // R[cmd_info_ex4b]: V(False)
  //   F[opcode]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_ex4b_opcode (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_ex4b_we),
    .wd     (cmd_info_ex4b_opcode_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info_ex4b.opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_ex4b_opcode_qs)
  );

  //   F[valid]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_ex4b_valid (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_ex4b_we),
    .wd     (cmd_info_ex4b_valid_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info_ex4b.valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_ex4b_valid_qs)
  );


  // R[cmd_info_wren]: V(False)
  //   F[opcode]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_wren_opcode (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_wren_we),
    .wd     (cmd_info_wren_opcode_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info_wren.opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_wren_opcode_qs)
  );

  //   F[valid]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_wren_valid (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_wren_we),
    .wd     (cmd_info_wren_valid_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info_wren.valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_wren_valid_qs)
  );


  // R[cmd_info_wrdi]: V(False)
  //   F[opcode]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_wrdi_opcode (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_wrdi_we),
    .wd     (cmd_info_wrdi_opcode_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info_wrdi.opcode.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_wrdi_opcode_qs)
  );

  //   F[valid]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_cmd_info_wrdi_valid (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (cmd_info_wrdi_we),
    .wd     (cmd_info_wrdi_valid_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cmd_info_wrdi.valid.q),
    .ds     (),

    // to register interface (read)
    .qs     (cmd_info_wrdi_valid_qs)
  );


  // R[tpm_cap]: V(False)
  //   F[rev]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_tpm_cap_rev (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.tpm_cap.rev.de),
    .d      (hw2reg.tpm_cap.rev.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_cap_rev_qs)
  );

  //   F[locality]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h1),
    .Mubi    (1'b0)
  ) u_tpm_cap_locality (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.tpm_cap.locality.de),
    .d      (hw2reg.tpm_cap.locality.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_cap_locality_qs)
  );

  //   F[max_wr_size]: 18:16
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (3'h6),
    .Mubi    (1'b0)
  ) u_tpm_cap_max_wr_size (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.tpm_cap.max_wr_size.de),
    .d      (hw2reg.tpm_cap.max_wr_size.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_cap_max_wr_size_qs)
  );

  //   F[max_rd_size]: 22:20
  prim_subreg #(
    .DW      (3),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (3'h6),
    .Mubi    (1'b0)
  ) u_tpm_cap_max_rd_size (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.tpm_cap.max_rd_size.de),
    .d      (hw2reg.tpm_cap.max_rd_size.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_cap_max_rd_size_qs)
  );


  // R[tpm_cfg]: V(False)
  //   F[en]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_tpm_cfg_en (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_cfg_we),
    .wd     (tpm_cfg_en_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_cfg.en.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_cfg_en_qs)
  );

  //   F[tpm_mode]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_tpm_cfg_tpm_mode (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_cfg_we),
    .wd     (tpm_cfg_tpm_mode_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_cfg.tpm_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_cfg_tpm_mode_qs)
  );

  //   F[hw_reg_dis]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_tpm_cfg_hw_reg_dis (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_cfg_we),
    .wd     (tpm_cfg_hw_reg_dis_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_cfg.hw_reg_dis.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_cfg_hw_reg_dis_qs)
  );

  //   F[tpm_reg_chk_dis]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_tpm_cfg_tpm_reg_chk_dis (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_cfg_we),
    .wd     (tpm_cfg_tpm_reg_chk_dis_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_cfg.tpm_reg_chk_dis.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_cfg_tpm_reg_chk_dis_qs)
  );

  //   F[invalid_locality]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_tpm_cfg_invalid_locality (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_cfg_we),
    .wd     (tpm_cfg_invalid_locality_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_cfg.invalid_locality.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_cfg_invalid_locality_qs)
  );


  // R[tpm_status]: V(True)
  logic tpm_status_qe;
  logic [2:0] tpm_status_flds_we;
  // This ignores QEs that are set to constant 0 due to read-only fields.
  logic unused_tpm_status_flds_we;
  assign unused_tpm_status_flds_we = ^(tpm_status_flds_we & 3'h5);
  assign tpm_status_qe = &(tpm_status_flds_we | 3'h5);
  //   F[cmdaddr_notempty]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_tpm_status_cmdaddr_notempty (
    .re     (tpm_status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.tpm_status.cmdaddr_notempty.d),
    .qre    (),
    .qe     (tpm_status_flds_we[0]),
    .q      (),
    .ds     (),
    .qs     (tpm_status_cmdaddr_notempty_qs)
  );

  //   F[wrfifo_pending]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_tpm_status_wrfifo_pending (
    .re     (tpm_status_re),
    .we     (tpm_status_we),
    .wd     (tpm_status_wrfifo_pending_wd),
    .d      (hw2reg.tpm_status.wrfifo_pending.d),
    .qre    (),
    .qe     (tpm_status_flds_we[1]),
    .q      (reg2hw.tpm_status.wrfifo_pending.q),
    .ds     (),
    .qs     (tpm_status_wrfifo_pending_qs)
  );
  assign reg2hw.tpm_status.wrfifo_pending.qe = tpm_status_qe;

  //   F[rdfifo_aborted]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_tpm_status_rdfifo_aborted (
    .re     (tpm_status_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.tpm_status.rdfifo_aborted.d),
    .qre    (),
    .qe     (tpm_status_flds_we[2]),
    .q      (),
    .ds     (),
    .qs     (tpm_status_rdfifo_aborted_qs)
  );


  // R[tpm_access_0]: V(False)
  //   F[access_0]: 7:0
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_tpm_access_0_access_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_access_0_we),
    .wd     (tpm_access_0_access_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_access_0[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_access_0_access_0_qs)
  );

  //   F[access_1]: 15:8
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_tpm_access_0_access_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_access_0_we),
    .wd     (tpm_access_0_access_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_access_0[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_access_0_access_1_qs)
  );

  //   F[access_2]: 23:16
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_tpm_access_0_access_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_access_0_we),
    .wd     (tpm_access_0_access_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_access_0[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_access_0_access_2_qs)
  );

  //   F[access_3]: 31:24
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_tpm_access_0_access_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_access_0_we),
    .wd     (tpm_access_0_access_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_access_0[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_access_0_access_3_qs)
  );


  // R[tpm_access_1]: V(False)
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_tpm_access_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_access_1_we),
    .wd     (tpm_access_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_access_1.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_access_1_qs)
  );


  // R[tpm_sts]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_tpm_sts (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_sts_we),
    .wd     (tpm_sts_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_sts.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_sts_qs)
  );


  // R[tpm_intf_capability]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_tpm_intf_capability (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_intf_capability_we),
    .wd     (tpm_intf_capability_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_intf_capability.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_intf_capability_qs)
  );


  // R[tpm_int_enable]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_tpm_int_enable (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_int_enable_we),
    .wd     (tpm_int_enable_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_int_enable.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_int_enable_qs)
  );


  // R[tpm_int_vector]: V(False)
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_tpm_int_vector (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_int_vector_we),
    .wd     (tpm_int_vector_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_int_vector.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_int_vector_qs)
  );


  // R[tpm_int_status]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_tpm_int_status (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_int_status_we),
    .wd     (tpm_int_status_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_int_status.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_int_status_qs)
  );


  // R[tpm_did_vid]: V(False)
  //   F[vid]: 15:0
  prim_subreg #(
    .DW      (16),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (16'h0),
    .Mubi    (1'b0)
  ) u_tpm_did_vid_vid (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_did_vid_we),
    .wd     (tpm_did_vid_vid_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_did_vid.vid.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_did_vid_vid_qs)
  );

  //   F[did]: 31:16
  prim_subreg #(
    .DW      (16),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (16'h0),
    .Mubi    (1'b0)
  ) u_tpm_did_vid_did (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_did_vid_we),
    .wd     (tpm_did_vid_did_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_did_vid.did.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_did_vid_did_qs)
  );


  // R[tpm_rid]: V(False)
  prim_subreg #(
    .DW      (8),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (8'h0),
    .Mubi    (1'b0)
  ) u_tpm_rid (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (tpm_rid_we),
    .wd     (tpm_rid_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.tpm_rid.q),
    .ds     (),

    // to register interface (read)
    .qs     (tpm_rid_qs)
  );


  // R[tpm_cmd_addr]: V(True)
  logic tpm_cmd_addr_qe;
  logic [1:0] tpm_cmd_addr_flds_we;
  // In case all fields are read-only the aggregated register QE will be zero as well.
  assign tpm_cmd_addr_qe = &tpm_cmd_addr_flds_we;
  //   F[addr]: 23:0
  prim_subreg_ext #(
    .DW    (24)
  ) u_tpm_cmd_addr_addr (
    .re     (tpm_cmd_addr_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.tpm_cmd_addr.addr.d),
    .qre    (reg2hw.tpm_cmd_addr.addr.re),
    .qe     (tpm_cmd_addr_flds_we[0]),
    .q      (reg2hw.tpm_cmd_addr.addr.q),
    .ds     (),
    .qs     (tpm_cmd_addr_addr_qs)
  );
  assign reg2hw.tpm_cmd_addr.addr.qe = tpm_cmd_addr_qe;

  //   F[cmd]: 31:24
  prim_subreg_ext #(
    .DW    (8)
  ) u_tpm_cmd_addr_cmd (
    .re     (tpm_cmd_addr_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.tpm_cmd_addr.cmd.d),
    .qre    (reg2hw.tpm_cmd_addr.cmd.re),
    .qe     (tpm_cmd_addr_flds_we[1]),
    .q      (reg2hw.tpm_cmd_addr.cmd.q),
    .ds     (),
    .qs     (tpm_cmd_addr_cmd_qs)
  );
  assign reg2hw.tpm_cmd_addr.cmd.qe = tpm_cmd_addr_qe;


  // R[tpm_read_fifo]: V(True)
  logic tpm_read_fifo_qe;
  logic [0:0] tpm_read_fifo_flds_we;
  assign tpm_read_fifo_qe = &tpm_read_fifo_flds_we;
  prim_subreg_ext #(
    .DW    (32)
  ) u_tpm_read_fifo (
    .re     (1'b0),
    .we     (tpm_read_fifo_we),
    .wd     (tpm_read_fifo_wd),
    .d      ('0),
    .qre    (),
    .qe     (tpm_read_fifo_flds_we[0]),
    .q      (reg2hw.tpm_read_fifo.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.tpm_read_fifo.qe = tpm_read_fifo_qe;



  logic [72:0] addr_hit;
  top_racl_pkg::racl_role_vec_t racl_role_vec;
  top_racl_pkg::racl_role_t racl_role;

  logic [72:0] racl_addr_hit_read;
  logic [72:0] racl_addr_hit_write;

  if (EnableRacl) begin : gen_racl_role_logic
    // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap
    assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd);

    prim_onehot_enc #(
      .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) )
    ) u_racl_role_encode (
      .in_i ( racl_role     ),
      .en_i ( 1'b1          ),
      .out_o( racl_role_vec )
    );
  end else begin : gen_no_racl_role_logic
    assign racl_role     = '0;
    assign racl_role_vec = '0;
  end
  always_comb begin
    racl_addr_hit_read  = '0;
    racl_addr_hit_write = '0;
    addr_hit[ 0] = (reg_addr == SPI_DEVICE_INTR_STATE_OFFSET);
    addr_hit[ 1] = (reg_addr == SPI_DEVICE_INTR_ENABLE_OFFSET);
    addr_hit[ 2] = (reg_addr == SPI_DEVICE_INTR_TEST_OFFSET);
    addr_hit[ 3] = (reg_addr == SPI_DEVICE_ALERT_TEST_OFFSET);
    addr_hit[ 4] = (reg_addr == SPI_DEVICE_CONTROL_OFFSET);
    addr_hit[ 5] = (reg_addr == SPI_DEVICE_CFG_OFFSET);
    addr_hit[ 6] = (reg_addr == SPI_DEVICE_STATUS_OFFSET);
    addr_hit[ 7] = (reg_addr == SPI_DEVICE_INTERCEPT_EN_OFFSET);
    addr_hit[ 8] = (reg_addr == SPI_DEVICE_ADDR_MODE_OFFSET);
    addr_hit[ 9] = (reg_addr == SPI_DEVICE_LAST_READ_ADDR_OFFSET);
    addr_hit[10] = (reg_addr == SPI_DEVICE_FLASH_STATUS_OFFSET);
    addr_hit[11] = (reg_addr == SPI_DEVICE_JEDEC_CC_OFFSET);
    addr_hit[12] = (reg_addr == SPI_DEVICE_JEDEC_ID_OFFSET);
    addr_hit[13] = (reg_addr == SPI_DEVICE_READ_THRESHOLD_OFFSET);
    addr_hit[14] = (reg_addr == SPI_DEVICE_MAILBOX_ADDR_OFFSET);
    addr_hit[15] = (reg_addr == SPI_DEVICE_UPLOAD_STATUS_OFFSET);
    addr_hit[16] = (reg_addr == SPI_DEVICE_UPLOAD_STATUS2_OFFSET);
    addr_hit[17] = (reg_addr == SPI_DEVICE_UPLOAD_CMDFIFO_OFFSET);
    addr_hit[18] = (reg_addr == SPI_DEVICE_UPLOAD_ADDRFIFO_OFFSET);
    addr_hit[19] = (reg_addr == SPI_DEVICE_CMD_FILTER_0_OFFSET);
    addr_hit[20] = (reg_addr == SPI_DEVICE_CMD_FILTER_1_OFFSET);
    addr_hit[21] = (reg_addr == SPI_DEVICE_CMD_FILTER_2_OFFSET);
    addr_hit[22] = (reg_addr == SPI_DEVICE_CMD_FILTER_3_OFFSET);
    addr_hit[23] = (reg_addr == SPI_DEVICE_CMD_FILTER_4_OFFSET);
    addr_hit[24] = (reg_addr == SPI_DEVICE_CMD_FILTER_5_OFFSET);
    addr_hit[25] = (reg_addr == SPI_DEVICE_CMD_FILTER_6_OFFSET);
    addr_hit[26] = (reg_addr == SPI_DEVICE_CMD_FILTER_7_OFFSET);
    addr_hit[27] = (reg_addr == SPI_DEVICE_ADDR_SWAP_MASK_OFFSET);
    addr_hit[28] = (reg_addr == SPI_DEVICE_ADDR_SWAP_DATA_OFFSET);
    addr_hit[29] = (reg_addr == SPI_DEVICE_PAYLOAD_SWAP_MASK_OFFSET);
    addr_hit[30] = (reg_addr == SPI_DEVICE_PAYLOAD_SWAP_DATA_OFFSET);
    addr_hit[31] = (reg_addr == SPI_DEVICE_CMD_INFO_0_OFFSET);
    addr_hit[32] = (reg_addr == SPI_DEVICE_CMD_INFO_1_OFFSET);
    addr_hit[33] = (reg_addr == SPI_DEVICE_CMD_INFO_2_OFFSET);
    addr_hit[34] = (reg_addr == SPI_DEVICE_CMD_INFO_3_OFFSET);
    addr_hit[35] = (reg_addr == SPI_DEVICE_CMD_INFO_4_OFFSET);
    addr_hit[36] = (reg_addr == SPI_DEVICE_CMD_INFO_5_OFFSET);
    addr_hit[37] = (reg_addr == SPI_DEVICE_CMD_INFO_6_OFFSET);
    addr_hit[38] = (reg_addr == SPI_DEVICE_CMD_INFO_7_OFFSET);
    addr_hit[39] = (reg_addr == SPI_DEVICE_CMD_INFO_8_OFFSET);
    addr_hit[40] = (reg_addr == SPI_DEVICE_CMD_INFO_9_OFFSET);
    addr_hit[41] = (reg_addr == SPI_DEVICE_CMD_INFO_10_OFFSET);
    addr_hit[42] = (reg_addr == SPI_DEVICE_CMD_INFO_11_OFFSET);
    addr_hit[43] = (reg_addr == SPI_DEVICE_CMD_INFO_12_OFFSET);
    addr_hit[44] = (reg_addr == SPI_DEVICE_CMD_INFO_13_OFFSET);
    addr_hit[45] = (reg_addr == SPI_DEVICE_CMD_INFO_14_OFFSET);
    addr_hit[46] = (reg_addr == SPI_DEVICE_CMD_INFO_15_OFFSET);
    addr_hit[47] = (reg_addr == SPI_DEVICE_CMD_INFO_16_OFFSET);
    addr_hit[48] = (reg_addr == SPI_DEVICE_CMD_INFO_17_OFFSET);
    addr_hit[49] = (reg_addr == SPI_DEVICE_CMD_INFO_18_OFFSET);
    addr_hit[50] = (reg_addr == SPI_DEVICE_CMD_INFO_19_OFFSET);
    addr_hit[51] = (reg_addr == SPI_DEVICE_CMD_INFO_20_OFFSET);
    addr_hit[52] = (reg_addr == SPI_DEVICE_CMD_INFO_21_OFFSET);
    addr_hit[53] = (reg_addr == SPI_DEVICE_CMD_INFO_22_OFFSET);
    addr_hit[54] = (reg_addr == SPI_DEVICE_CMD_INFO_23_OFFSET);
    addr_hit[55] = (reg_addr == SPI_DEVICE_CMD_INFO_EN4B_OFFSET);
    addr_hit[56] = (reg_addr == SPI_DEVICE_CMD_INFO_EX4B_OFFSET);
    addr_hit[57] = (reg_addr == SPI_DEVICE_CMD_INFO_WREN_OFFSET);
    addr_hit[58] = (reg_addr == SPI_DEVICE_CMD_INFO_WRDI_OFFSET);
    addr_hit[59] = (reg_addr == SPI_DEVICE_TPM_CAP_OFFSET);
    addr_hit[60] = (reg_addr == SPI_DEVICE_TPM_CFG_OFFSET);
    addr_hit[61] = (reg_addr == SPI_DEVICE_TPM_STATUS_OFFSET);
    addr_hit[62] = (reg_addr == SPI_DEVICE_TPM_ACCESS_0_OFFSET);
    addr_hit[63] = (reg_addr == SPI_DEVICE_TPM_ACCESS_1_OFFSET);
    addr_hit[64] = (reg_addr == SPI_DEVICE_TPM_STS_OFFSET);
    addr_hit[65] = (reg_addr == SPI_DEVICE_TPM_INTF_CAPABILITY_OFFSET);
    addr_hit[66] = (reg_addr == SPI_DEVICE_TPM_INT_ENABLE_OFFSET);
    addr_hit[67] = (reg_addr == SPI_DEVICE_TPM_INT_VECTOR_OFFSET);
    addr_hit[68] = (reg_addr == SPI_DEVICE_TPM_INT_STATUS_OFFSET);
    addr_hit[69] = (reg_addr == SPI_DEVICE_TPM_DID_VID_OFFSET);
    addr_hit[70] = (reg_addr == SPI_DEVICE_TPM_RID_OFFSET);
    addr_hit[71] = (reg_addr == SPI_DEVICE_TPM_CMD_ADDR_OFFSET);
    addr_hit[72] = (reg_addr == SPI_DEVICE_TPM_READ_FIFO_OFFSET);

    if (EnableRacl) begin : gen_racl_hit
      for (int unsigned slice_idx = 0; slice_idx < 73; slice_idx++) begin
        racl_addr_hit_read[slice_idx] =
            addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].read_perm
                                      & racl_role_vec));
        racl_addr_hit_write[slice_idx] =
            addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].write_perm
                                      & racl_role_vec));
      end
    end else begin : gen_no_racl
      racl_addr_hit_read  = addr_hit;
      racl_addr_hit_write = addr_hit;
    end
  end

  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
  // A valid address hit, access, but failed the RACL check
  assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) |
                                           (reg_we & ~|racl_addr_hit_write));
  assign racl_error_o.request_address = top_pkg::TL_AW'(reg_addr);
  assign racl_error_o.racl_role       = racl_role;
  assign racl_error_o.overflow        = 1'b0;

  if (EnableRacl) begin : gen_racl_log
    assign racl_error_o.ctn_uid     = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd);
    assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get;
  end else begin : gen_no_racl_log
    assign racl_error_o.ctn_uid     = '0;
    assign racl_error_o.read_access = 1'b0;
  end

  // Check sub-word write is permitted
  always_comb begin
    wr_err = (reg_we &
              ((racl_addr_hit_write[ 0] & (|(SPI_DEVICE_PERMIT[ 0] & ~reg_be))) |
               (racl_addr_hit_write[ 1] & (|(SPI_DEVICE_PERMIT[ 1] & ~reg_be))) |
               (racl_addr_hit_write[ 2] & (|(SPI_DEVICE_PERMIT[ 2] & ~reg_be))) |
               (racl_addr_hit_write[ 3] & (|(SPI_DEVICE_PERMIT[ 3] & ~reg_be))) |
               (racl_addr_hit_write[ 4] & (|(SPI_DEVICE_PERMIT[ 4] & ~reg_be))) |
               (racl_addr_hit_write[ 5] & (|(SPI_DEVICE_PERMIT[ 5] & ~reg_be))) |
               (racl_addr_hit_write[ 6] & (|(SPI_DEVICE_PERMIT[ 6] & ~reg_be))) |
               (racl_addr_hit_write[ 7] & (|(SPI_DEVICE_PERMIT[ 7] & ~reg_be))) |
               (racl_addr_hit_write[ 8] & (|(SPI_DEVICE_PERMIT[ 8] & ~reg_be))) |
               (racl_addr_hit_write[ 9] & (|(SPI_DEVICE_PERMIT[ 9] & ~reg_be))) |
               (racl_addr_hit_write[10] & (|(SPI_DEVICE_PERMIT[10] & ~reg_be))) |
               (racl_addr_hit_write[11] & (|(SPI_DEVICE_PERMIT[11] & ~reg_be))) |
               (racl_addr_hit_write[12] & (|(SPI_DEVICE_PERMIT[12] & ~reg_be))) |
               (racl_addr_hit_write[13] & (|(SPI_DEVICE_PERMIT[13] & ~reg_be))) |
               (racl_addr_hit_write[14] & (|(SPI_DEVICE_PERMIT[14] & ~reg_be))) |
               (racl_addr_hit_write[15] & (|(SPI_DEVICE_PERMIT[15] & ~reg_be))) |
               (racl_addr_hit_write[16] & (|(SPI_DEVICE_PERMIT[16] & ~reg_be))) |
               (racl_addr_hit_write[17] & (|(SPI_DEVICE_PERMIT[17] & ~reg_be))) |
               (racl_addr_hit_write[18] & (|(SPI_DEVICE_PERMIT[18] & ~reg_be))) |
               (racl_addr_hit_write[19] & (|(SPI_DEVICE_PERMIT[19] & ~reg_be))) |
               (racl_addr_hit_write[20] & (|(SPI_DEVICE_PERMIT[20] & ~reg_be))) |
               (racl_addr_hit_write[21] & (|(SPI_DEVICE_PERMIT[21] & ~reg_be))) |
               (racl_addr_hit_write[22] & (|(SPI_DEVICE_PERMIT[22] & ~reg_be))) |
               (racl_addr_hit_write[23] & (|(SPI_DEVICE_PERMIT[23] & ~reg_be))) |
               (racl_addr_hit_write[24] & (|(SPI_DEVICE_PERMIT[24] & ~reg_be))) |
               (racl_addr_hit_write[25] & (|(SPI_DEVICE_PERMIT[25] & ~reg_be))) |
               (racl_addr_hit_write[26] & (|(SPI_DEVICE_PERMIT[26] & ~reg_be))) |
               (racl_addr_hit_write[27] & (|(SPI_DEVICE_PERMIT[27] & ~reg_be))) |
               (racl_addr_hit_write[28] & (|(SPI_DEVICE_PERMIT[28] & ~reg_be))) |
               (racl_addr_hit_write[29] & (|(SPI_DEVICE_PERMIT[29] & ~reg_be))) |
               (racl_addr_hit_write[30] & (|(SPI_DEVICE_PERMIT[30] & ~reg_be))) |
               (racl_addr_hit_write[31] & (|(SPI_DEVICE_PERMIT[31] & ~reg_be))) |
               (racl_addr_hit_write[32] & (|(SPI_DEVICE_PERMIT[32] & ~reg_be))) |
               (racl_addr_hit_write[33] & (|(SPI_DEVICE_PERMIT[33] & ~reg_be))) |
               (racl_addr_hit_write[34] & (|(SPI_DEVICE_PERMIT[34] & ~reg_be))) |
               (racl_addr_hit_write[35] & (|(SPI_DEVICE_PERMIT[35] & ~reg_be))) |
               (racl_addr_hit_write[36] & (|(SPI_DEVICE_PERMIT[36] & ~reg_be))) |
               (racl_addr_hit_write[37] & (|(SPI_DEVICE_PERMIT[37] & ~reg_be))) |
               (racl_addr_hit_write[38] & (|(SPI_DEVICE_PERMIT[38] & ~reg_be))) |
               (racl_addr_hit_write[39] & (|(SPI_DEVICE_PERMIT[39] & ~reg_be))) |
               (racl_addr_hit_write[40] & (|(SPI_DEVICE_PERMIT[40] & ~reg_be))) |
               (racl_addr_hit_write[41] & (|(SPI_DEVICE_PERMIT[41] & ~reg_be))) |
               (racl_addr_hit_write[42] & (|(SPI_DEVICE_PERMIT[42] & ~reg_be))) |
               (racl_addr_hit_write[43] & (|(SPI_DEVICE_PERMIT[43] & ~reg_be))) |
               (racl_addr_hit_write[44] & (|(SPI_DEVICE_PERMIT[44] & ~reg_be))) |
               (racl_addr_hit_write[45] & (|(SPI_DEVICE_PERMIT[45] & ~reg_be))) |
               (racl_addr_hit_write[46] & (|(SPI_DEVICE_PERMIT[46] & ~reg_be))) |
               (racl_addr_hit_write[47] & (|(SPI_DEVICE_PERMIT[47] & ~reg_be))) |
               (racl_addr_hit_write[48] & (|(SPI_DEVICE_PERMIT[48] & ~reg_be))) |
               (racl_addr_hit_write[49] & (|(SPI_DEVICE_PERMIT[49] & ~reg_be))) |
               (racl_addr_hit_write[50] & (|(SPI_DEVICE_PERMIT[50] & ~reg_be))) |
               (racl_addr_hit_write[51] & (|(SPI_DEVICE_PERMIT[51] & ~reg_be))) |
               (racl_addr_hit_write[52] & (|(SPI_DEVICE_PERMIT[52] & ~reg_be))) |
               (racl_addr_hit_write[53] & (|(SPI_DEVICE_PERMIT[53] & ~reg_be))) |
               (racl_addr_hit_write[54] & (|(SPI_DEVICE_PERMIT[54] & ~reg_be))) |
               (racl_addr_hit_write[55] & (|(SPI_DEVICE_PERMIT[55] & ~reg_be))) |
               (racl_addr_hit_write[56] & (|(SPI_DEVICE_PERMIT[56] & ~reg_be))) |
               (racl_addr_hit_write[57] & (|(SPI_DEVICE_PERMIT[57] & ~reg_be))) |
               (racl_addr_hit_write[58] & (|(SPI_DEVICE_PERMIT[58] & ~reg_be))) |
               (racl_addr_hit_write[59] & (|(SPI_DEVICE_PERMIT[59] & ~reg_be))) |
               (racl_addr_hit_write[60] & (|(SPI_DEVICE_PERMIT[60] & ~reg_be))) |
               (racl_addr_hit_write[61] & (|(SPI_DEVICE_PERMIT[61] & ~reg_be))) |
               (racl_addr_hit_write[62] & (|(SPI_DEVICE_PERMIT[62] & ~reg_be))) |
               (racl_addr_hit_write[63] & (|(SPI_DEVICE_PERMIT[63] & ~reg_be))) |
               (racl_addr_hit_write[64] & (|(SPI_DEVICE_PERMIT[64] & ~reg_be))) |
               (racl_addr_hit_write[65] & (|(SPI_DEVICE_PERMIT[65] & ~reg_be))) |
               (racl_addr_hit_write[66] & (|(SPI_DEVICE_PERMIT[66] & ~reg_be))) |
               (racl_addr_hit_write[67] & (|(SPI_DEVICE_PERMIT[67] & ~reg_be))) |
               (racl_addr_hit_write[68] & (|(SPI_DEVICE_PERMIT[68] & ~reg_be))) |
               (racl_addr_hit_write[69] & (|(SPI_DEVICE_PERMIT[69] & ~reg_be))) |
               (racl_addr_hit_write[70] & (|(SPI_DEVICE_PERMIT[70] & ~reg_be))) |
               (racl_addr_hit_write[71] & (|(SPI_DEVICE_PERMIT[71] & ~reg_be))) |
               (racl_addr_hit_write[72] & (|(SPI_DEVICE_PERMIT[72] & ~reg_be)))));
  end

  // Generate write-enables
  assign intr_state_we = racl_addr_hit_write[0] & reg_we & !reg_error;

  assign intr_state_upload_cmdfifo_not_empty_wd = reg_wdata[0];

  assign intr_state_upload_payload_not_empty_wd = reg_wdata[1];

  assign intr_state_upload_payload_overflow_wd = reg_wdata[2];

  assign intr_state_readbuf_watermark_wd = reg_wdata[3];

  assign intr_state_readbuf_flip_wd = reg_wdata[4];

  assign intr_state_tpm_rdfifo_cmd_end_wd = reg_wdata[6];

  assign intr_state_tpm_rdfifo_drop_wd = reg_wdata[7];

  assign intr_enable_we = racl_addr_hit_write[1] & reg_we & !reg_error;

  assign intr_enable_upload_cmdfifo_not_empty_wd = reg_wdata[0];

  assign intr_enable_upload_payload_not_empty_wd = reg_wdata[1];

  assign intr_enable_upload_payload_overflow_wd = reg_wdata[2];

  assign intr_enable_readbuf_watermark_wd = reg_wdata[3];

  assign intr_enable_readbuf_flip_wd = reg_wdata[4];

  assign intr_enable_tpm_header_not_empty_wd = reg_wdata[5];

  assign intr_enable_tpm_rdfifo_cmd_end_wd = reg_wdata[6];

  assign intr_enable_tpm_rdfifo_drop_wd = reg_wdata[7];

  assign intr_test_we = racl_addr_hit_write[2] & reg_we & !reg_error;

  assign intr_test_upload_cmdfifo_not_empty_wd = reg_wdata[0];

  assign intr_test_upload_payload_not_empty_wd = reg_wdata[1];

  assign intr_test_upload_payload_overflow_wd = reg_wdata[2];

  assign intr_test_readbuf_watermark_wd = reg_wdata[3];

  assign intr_test_readbuf_flip_wd = reg_wdata[4];

  assign intr_test_tpm_header_not_empty_wd = reg_wdata[5];

  assign intr_test_tpm_rdfifo_cmd_end_wd = reg_wdata[6];

  assign intr_test_tpm_rdfifo_drop_wd = reg_wdata[7];

  assign alert_test_we = racl_addr_hit_write[3] & reg_we & !reg_error;

  assign alert_test_wd = reg_wdata[0];

  assign control_we = racl_addr_hit_write[4] & reg_we & !reg_error;

  assign control_flash_status_fifo_clr_wd = reg_wdata[0];

  assign control_flash_read_buffer_clr_wd = reg_wdata[1];

  assign control_mode_wd = reg_wdata[5:4];

  assign cfg_we = racl_addr_hit_write[5] & reg_we & !reg_error;

  assign cfg_tx_order_wd = reg_wdata[2];

  assign cfg_rx_order_wd = reg_wdata[3];

  assign cfg_mailbox_en_wd = reg_wdata[24];

  assign status_re = racl_addr_hit_read[6] & reg_re & !reg_error;
  assign intercept_en_we = racl_addr_hit_write[7] & reg_we & !reg_error;

  assign intercept_en_status_wd = reg_wdata[0];

  assign intercept_en_jedec_wd = reg_wdata[1];

  assign intercept_en_sfdp_wd = reg_wdata[2];

  assign intercept_en_mbx_wd = reg_wdata[3];

  assign addr_mode_re = racl_addr_hit_read[8] & reg_re & !reg_error;
  assign addr_mode_we = racl_addr_hit_write[8] & reg_we & !reg_error;

  assign addr_mode_addr_4b_en_wd = reg_wdata[0];

  assign last_read_addr_re = racl_addr_hit_read[9] & reg_re & !reg_error;
  assign flash_status_re = racl_addr_hit_read[10] & reg_re & !reg_error;
  assign flash_status_we = racl_addr_hit_write[10] & reg_we & !reg_error;

  assign flash_status_busy_wd = reg_wdata[0];

  assign flash_status_wel_wd = reg_wdata[1];

  assign flash_status_status_wd = reg_wdata[23:2];

  assign jedec_cc_we = racl_addr_hit_write[11] & reg_we & !reg_error;

  assign jedec_cc_cc_wd = reg_wdata[7:0];

  assign jedec_cc_num_cc_wd = reg_wdata[15:8];

  assign jedec_id_we = racl_addr_hit_write[12] & reg_we & !reg_error;

  assign jedec_id_id_wd = reg_wdata[15:0];

  assign jedec_id_mf_wd = reg_wdata[23:16];

  assign read_threshold_we = racl_addr_hit_write[13] & reg_we & !reg_error;

  assign read_threshold_wd = reg_wdata[9:0];

  assign mailbox_addr_we = racl_addr_hit_write[14] & reg_we & !reg_error;

  assign mailbox_addr_wd = reg_wdata[31:0];

  assign upload_cmdfifo_re = racl_addr_hit_read[17] & reg_re & !reg_error;
  assign upload_addrfifo_re = racl_addr_hit_read[18] & reg_re & !reg_error;
  assign cmd_filter_0_we = racl_addr_hit_write[19] & reg_we & !reg_error;

  assign cmd_filter_0_filter_0_wd = reg_wdata[0];

  assign cmd_filter_0_filter_1_wd = reg_wdata[1];

  assign cmd_filter_0_filter_2_wd = reg_wdata[2];

  assign cmd_filter_0_filter_3_wd = reg_wdata[3];

  assign cmd_filter_0_filter_4_wd = reg_wdata[4];

  assign cmd_filter_0_filter_5_wd = reg_wdata[5];

  assign cmd_filter_0_filter_6_wd = reg_wdata[6];

  assign cmd_filter_0_filter_7_wd = reg_wdata[7];

  assign cmd_filter_0_filter_8_wd = reg_wdata[8];

  assign cmd_filter_0_filter_9_wd = reg_wdata[9];

  assign cmd_filter_0_filter_10_wd = reg_wdata[10];

  assign cmd_filter_0_filter_11_wd = reg_wdata[11];

  assign cmd_filter_0_filter_12_wd = reg_wdata[12];

  assign cmd_filter_0_filter_13_wd = reg_wdata[13];

  assign cmd_filter_0_filter_14_wd = reg_wdata[14];

  assign cmd_filter_0_filter_15_wd = reg_wdata[15];

  assign cmd_filter_0_filter_16_wd = reg_wdata[16];

  assign cmd_filter_0_filter_17_wd = reg_wdata[17];

  assign cmd_filter_0_filter_18_wd = reg_wdata[18];

  assign cmd_filter_0_filter_19_wd = reg_wdata[19];

  assign cmd_filter_0_filter_20_wd = reg_wdata[20];

  assign cmd_filter_0_filter_21_wd = reg_wdata[21];

  assign cmd_filter_0_filter_22_wd = reg_wdata[22];

  assign cmd_filter_0_filter_23_wd = reg_wdata[23];

  assign cmd_filter_0_filter_24_wd = reg_wdata[24];

  assign cmd_filter_0_filter_25_wd = reg_wdata[25];

  assign cmd_filter_0_filter_26_wd = reg_wdata[26];

  assign cmd_filter_0_filter_27_wd = reg_wdata[27];

  assign cmd_filter_0_filter_28_wd = reg_wdata[28];

  assign cmd_filter_0_filter_29_wd = reg_wdata[29];

  assign cmd_filter_0_filter_30_wd = reg_wdata[30];

  assign cmd_filter_0_filter_31_wd = reg_wdata[31];

  assign cmd_filter_1_we = racl_addr_hit_write[20] & reg_we & !reg_error;

  assign cmd_filter_1_filter_32_wd = reg_wdata[0];

  assign cmd_filter_1_filter_33_wd = reg_wdata[1];

  assign cmd_filter_1_filter_34_wd = reg_wdata[2];

  assign cmd_filter_1_filter_35_wd = reg_wdata[3];

  assign cmd_filter_1_filter_36_wd = reg_wdata[4];

  assign cmd_filter_1_filter_37_wd = reg_wdata[5];

  assign cmd_filter_1_filter_38_wd = reg_wdata[6];

  assign cmd_filter_1_filter_39_wd = reg_wdata[7];

  assign cmd_filter_1_filter_40_wd = reg_wdata[8];

  assign cmd_filter_1_filter_41_wd = reg_wdata[9];

  assign cmd_filter_1_filter_42_wd = reg_wdata[10];

  assign cmd_filter_1_filter_43_wd = reg_wdata[11];

  assign cmd_filter_1_filter_44_wd = reg_wdata[12];

  assign cmd_filter_1_filter_45_wd = reg_wdata[13];

  assign cmd_filter_1_filter_46_wd = reg_wdata[14];

  assign cmd_filter_1_filter_47_wd = reg_wdata[15];

  assign cmd_filter_1_filter_48_wd = reg_wdata[16];

  assign cmd_filter_1_filter_49_wd = reg_wdata[17];

  assign cmd_filter_1_filter_50_wd = reg_wdata[18];

  assign cmd_filter_1_filter_51_wd = reg_wdata[19];

  assign cmd_filter_1_filter_52_wd = reg_wdata[20];

  assign cmd_filter_1_filter_53_wd = reg_wdata[21];

  assign cmd_filter_1_filter_54_wd = reg_wdata[22];

  assign cmd_filter_1_filter_55_wd = reg_wdata[23];

  assign cmd_filter_1_filter_56_wd = reg_wdata[24];

  assign cmd_filter_1_filter_57_wd = reg_wdata[25];

  assign cmd_filter_1_filter_58_wd = reg_wdata[26];

  assign cmd_filter_1_filter_59_wd = reg_wdata[27];

  assign cmd_filter_1_filter_60_wd = reg_wdata[28];

  assign cmd_filter_1_filter_61_wd = reg_wdata[29];

  assign cmd_filter_1_filter_62_wd = reg_wdata[30];

  assign cmd_filter_1_filter_63_wd = reg_wdata[31];

  assign cmd_filter_2_we = racl_addr_hit_write[21] & reg_we & !reg_error;

  assign cmd_filter_2_filter_64_wd = reg_wdata[0];

  assign cmd_filter_2_filter_65_wd = reg_wdata[1];

  assign cmd_filter_2_filter_66_wd = reg_wdata[2];

  assign cmd_filter_2_filter_67_wd = reg_wdata[3];

  assign cmd_filter_2_filter_68_wd = reg_wdata[4];

  assign cmd_filter_2_filter_69_wd = reg_wdata[5];

  assign cmd_filter_2_filter_70_wd = reg_wdata[6];

  assign cmd_filter_2_filter_71_wd = reg_wdata[7];

  assign cmd_filter_2_filter_72_wd = reg_wdata[8];

  assign cmd_filter_2_filter_73_wd = reg_wdata[9];

  assign cmd_filter_2_filter_74_wd = reg_wdata[10];

  assign cmd_filter_2_filter_75_wd = reg_wdata[11];

  assign cmd_filter_2_filter_76_wd = reg_wdata[12];

  assign cmd_filter_2_filter_77_wd = reg_wdata[13];

  assign cmd_filter_2_filter_78_wd = reg_wdata[14];

  assign cmd_filter_2_filter_79_wd = reg_wdata[15];

  assign cmd_filter_2_filter_80_wd = reg_wdata[16];

  assign cmd_filter_2_filter_81_wd = reg_wdata[17];

  assign cmd_filter_2_filter_82_wd = reg_wdata[18];

  assign cmd_filter_2_filter_83_wd = reg_wdata[19];

  assign cmd_filter_2_filter_84_wd = reg_wdata[20];

  assign cmd_filter_2_filter_85_wd = reg_wdata[21];

  assign cmd_filter_2_filter_86_wd = reg_wdata[22];

  assign cmd_filter_2_filter_87_wd = reg_wdata[23];

  assign cmd_filter_2_filter_88_wd = reg_wdata[24];

  assign cmd_filter_2_filter_89_wd = reg_wdata[25];

  assign cmd_filter_2_filter_90_wd = reg_wdata[26];

  assign cmd_filter_2_filter_91_wd = reg_wdata[27];

  assign cmd_filter_2_filter_92_wd = reg_wdata[28];

  assign cmd_filter_2_filter_93_wd = reg_wdata[29];

  assign cmd_filter_2_filter_94_wd = reg_wdata[30];

  assign cmd_filter_2_filter_95_wd = reg_wdata[31];

  assign cmd_filter_3_we = racl_addr_hit_write[22] & reg_we & !reg_error;

  assign cmd_filter_3_filter_96_wd = reg_wdata[0];

  assign cmd_filter_3_filter_97_wd = reg_wdata[1];

  assign cmd_filter_3_filter_98_wd = reg_wdata[2];

  assign cmd_filter_3_filter_99_wd = reg_wdata[3];

  assign cmd_filter_3_filter_100_wd = reg_wdata[4];

  assign cmd_filter_3_filter_101_wd = reg_wdata[5];

  assign cmd_filter_3_filter_102_wd = reg_wdata[6];

  assign cmd_filter_3_filter_103_wd = reg_wdata[7];

  assign cmd_filter_3_filter_104_wd = reg_wdata[8];

  assign cmd_filter_3_filter_105_wd = reg_wdata[9];

  assign cmd_filter_3_filter_106_wd = reg_wdata[10];

  assign cmd_filter_3_filter_107_wd = reg_wdata[11];

  assign cmd_filter_3_filter_108_wd = reg_wdata[12];

  assign cmd_filter_3_filter_109_wd = reg_wdata[13];

  assign cmd_filter_3_filter_110_wd = reg_wdata[14];

  assign cmd_filter_3_filter_111_wd = reg_wdata[15];

  assign cmd_filter_3_filter_112_wd = reg_wdata[16];

  assign cmd_filter_3_filter_113_wd = reg_wdata[17];

  assign cmd_filter_3_filter_114_wd = reg_wdata[18];

  assign cmd_filter_3_filter_115_wd = reg_wdata[19];

  assign cmd_filter_3_filter_116_wd = reg_wdata[20];

  assign cmd_filter_3_filter_117_wd = reg_wdata[21];

  assign cmd_filter_3_filter_118_wd = reg_wdata[22];

  assign cmd_filter_3_filter_119_wd = reg_wdata[23];

  assign cmd_filter_3_filter_120_wd = reg_wdata[24];

  assign cmd_filter_3_filter_121_wd = reg_wdata[25];

  assign cmd_filter_3_filter_122_wd = reg_wdata[26];

  assign cmd_filter_3_filter_123_wd = reg_wdata[27];

  assign cmd_filter_3_filter_124_wd = reg_wdata[28];

  assign cmd_filter_3_filter_125_wd = reg_wdata[29];

  assign cmd_filter_3_filter_126_wd = reg_wdata[30];

  assign cmd_filter_3_filter_127_wd = reg_wdata[31];

  assign cmd_filter_4_we = racl_addr_hit_write[23] & reg_we & !reg_error;

  assign cmd_filter_4_filter_128_wd = reg_wdata[0];

  assign cmd_filter_4_filter_129_wd = reg_wdata[1];

  assign cmd_filter_4_filter_130_wd = reg_wdata[2];

  assign cmd_filter_4_filter_131_wd = reg_wdata[3];

  assign cmd_filter_4_filter_132_wd = reg_wdata[4];

  assign cmd_filter_4_filter_133_wd = reg_wdata[5];

  assign cmd_filter_4_filter_134_wd = reg_wdata[6];

  assign cmd_filter_4_filter_135_wd = reg_wdata[7];

  assign cmd_filter_4_filter_136_wd = reg_wdata[8];

  assign cmd_filter_4_filter_137_wd = reg_wdata[9];

  assign cmd_filter_4_filter_138_wd = reg_wdata[10];

  assign cmd_filter_4_filter_139_wd = reg_wdata[11];

  assign cmd_filter_4_filter_140_wd = reg_wdata[12];

  assign cmd_filter_4_filter_141_wd = reg_wdata[13];

  assign cmd_filter_4_filter_142_wd = reg_wdata[14];

  assign cmd_filter_4_filter_143_wd = reg_wdata[15];

  assign cmd_filter_4_filter_144_wd = reg_wdata[16];

  assign cmd_filter_4_filter_145_wd = reg_wdata[17];

  assign cmd_filter_4_filter_146_wd = reg_wdata[18];

  assign cmd_filter_4_filter_147_wd = reg_wdata[19];

  assign cmd_filter_4_filter_148_wd = reg_wdata[20];

  assign cmd_filter_4_filter_149_wd = reg_wdata[21];

  assign cmd_filter_4_filter_150_wd = reg_wdata[22];

  assign cmd_filter_4_filter_151_wd = reg_wdata[23];

  assign cmd_filter_4_filter_152_wd = reg_wdata[24];

  assign cmd_filter_4_filter_153_wd = reg_wdata[25];

  assign cmd_filter_4_filter_154_wd = reg_wdata[26];

  assign cmd_filter_4_filter_155_wd = reg_wdata[27];

  assign cmd_filter_4_filter_156_wd = reg_wdata[28];

  assign cmd_filter_4_filter_157_wd = reg_wdata[29];

  assign cmd_filter_4_filter_158_wd = reg_wdata[30];

  assign cmd_filter_4_filter_159_wd = reg_wdata[31];

  assign cmd_filter_5_we = racl_addr_hit_write[24] & reg_we & !reg_error;

  assign cmd_filter_5_filter_160_wd = reg_wdata[0];

  assign cmd_filter_5_filter_161_wd = reg_wdata[1];

  assign cmd_filter_5_filter_162_wd = reg_wdata[2];

  assign cmd_filter_5_filter_163_wd = reg_wdata[3];

  assign cmd_filter_5_filter_164_wd = reg_wdata[4];

  assign cmd_filter_5_filter_165_wd = reg_wdata[5];

  assign cmd_filter_5_filter_166_wd = reg_wdata[6];

  assign cmd_filter_5_filter_167_wd = reg_wdata[7];

  assign cmd_filter_5_filter_168_wd = reg_wdata[8];

  assign cmd_filter_5_filter_169_wd = reg_wdata[9];

  assign cmd_filter_5_filter_170_wd = reg_wdata[10];

  assign cmd_filter_5_filter_171_wd = reg_wdata[11];

  assign cmd_filter_5_filter_172_wd = reg_wdata[12];

  assign cmd_filter_5_filter_173_wd = reg_wdata[13];

  assign cmd_filter_5_filter_174_wd = reg_wdata[14];

  assign cmd_filter_5_filter_175_wd = reg_wdata[15];

  assign cmd_filter_5_filter_176_wd = reg_wdata[16];

  assign cmd_filter_5_filter_177_wd = reg_wdata[17];

  assign cmd_filter_5_filter_178_wd = reg_wdata[18];

  assign cmd_filter_5_filter_179_wd = reg_wdata[19];

  assign cmd_filter_5_filter_180_wd = reg_wdata[20];

  assign cmd_filter_5_filter_181_wd = reg_wdata[21];

  assign cmd_filter_5_filter_182_wd = reg_wdata[22];

  assign cmd_filter_5_filter_183_wd = reg_wdata[23];

  assign cmd_filter_5_filter_184_wd = reg_wdata[24];

  assign cmd_filter_5_filter_185_wd = reg_wdata[25];

  assign cmd_filter_5_filter_186_wd = reg_wdata[26];

  assign cmd_filter_5_filter_187_wd = reg_wdata[27];

  assign cmd_filter_5_filter_188_wd = reg_wdata[28];

  assign cmd_filter_5_filter_189_wd = reg_wdata[29];

  assign cmd_filter_5_filter_190_wd = reg_wdata[30];

  assign cmd_filter_5_filter_191_wd = reg_wdata[31];

  assign cmd_filter_6_we = racl_addr_hit_write[25] & reg_we & !reg_error;

  assign cmd_filter_6_filter_192_wd = reg_wdata[0];

  assign cmd_filter_6_filter_193_wd = reg_wdata[1];

  assign cmd_filter_6_filter_194_wd = reg_wdata[2];

  assign cmd_filter_6_filter_195_wd = reg_wdata[3];

  assign cmd_filter_6_filter_196_wd = reg_wdata[4];

  assign cmd_filter_6_filter_197_wd = reg_wdata[5];

  assign cmd_filter_6_filter_198_wd = reg_wdata[6];

  assign cmd_filter_6_filter_199_wd = reg_wdata[7];

  assign cmd_filter_6_filter_200_wd = reg_wdata[8];

  assign cmd_filter_6_filter_201_wd = reg_wdata[9];

  assign cmd_filter_6_filter_202_wd = reg_wdata[10];

  assign cmd_filter_6_filter_203_wd = reg_wdata[11];

  assign cmd_filter_6_filter_204_wd = reg_wdata[12];

  assign cmd_filter_6_filter_205_wd = reg_wdata[13];

  assign cmd_filter_6_filter_206_wd = reg_wdata[14];

  assign cmd_filter_6_filter_207_wd = reg_wdata[15];

  assign cmd_filter_6_filter_208_wd = reg_wdata[16];

  assign cmd_filter_6_filter_209_wd = reg_wdata[17];

  assign cmd_filter_6_filter_210_wd = reg_wdata[18];

  assign cmd_filter_6_filter_211_wd = reg_wdata[19];

  assign cmd_filter_6_filter_212_wd = reg_wdata[20];

  assign cmd_filter_6_filter_213_wd = reg_wdata[21];

  assign cmd_filter_6_filter_214_wd = reg_wdata[22];

  assign cmd_filter_6_filter_215_wd = reg_wdata[23];

  assign cmd_filter_6_filter_216_wd = reg_wdata[24];

  assign cmd_filter_6_filter_217_wd = reg_wdata[25];

  assign cmd_filter_6_filter_218_wd = reg_wdata[26];

  assign cmd_filter_6_filter_219_wd = reg_wdata[27];

  assign cmd_filter_6_filter_220_wd = reg_wdata[28];

  assign cmd_filter_6_filter_221_wd = reg_wdata[29];

  assign cmd_filter_6_filter_222_wd = reg_wdata[30];

  assign cmd_filter_6_filter_223_wd = reg_wdata[31];

  assign cmd_filter_7_we = racl_addr_hit_write[26] & reg_we & !reg_error;

  assign cmd_filter_7_filter_224_wd = reg_wdata[0];

  assign cmd_filter_7_filter_225_wd = reg_wdata[1];

  assign cmd_filter_7_filter_226_wd = reg_wdata[2];

  assign cmd_filter_7_filter_227_wd = reg_wdata[3];

  assign cmd_filter_7_filter_228_wd = reg_wdata[4];

  assign cmd_filter_7_filter_229_wd = reg_wdata[5];

  assign cmd_filter_7_filter_230_wd = reg_wdata[6];

  assign cmd_filter_7_filter_231_wd = reg_wdata[7];

  assign cmd_filter_7_filter_232_wd = reg_wdata[8];

  assign cmd_filter_7_filter_233_wd = reg_wdata[9];

  assign cmd_filter_7_filter_234_wd = reg_wdata[10];

  assign cmd_filter_7_filter_235_wd = reg_wdata[11];

  assign cmd_filter_7_filter_236_wd = reg_wdata[12];

  assign cmd_filter_7_filter_237_wd = reg_wdata[13];

  assign cmd_filter_7_filter_238_wd = reg_wdata[14];

  assign cmd_filter_7_filter_239_wd = reg_wdata[15];

  assign cmd_filter_7_filter_240_wd = reg_wdata[16];

  assign cmd_filter_7_filter_241_wd = reg_wdata[17];

  assign cmd_filter_7_filter_242_wd = reg_wdata[18];

  assign cmd_filter_7_filter_243_wd = reg_wdata[19];

  assign cmd_filter_7_filter_244_wd = reg_wdata[20];

  assign cmd_filter_7_filter_245_wd = reg_wdata[21];

  assign cmd_filter_7_filter_246_wd = reg_wdata[22];

  assign cmd_filter_7_filter_247_wd = reg_wdata[23];

  assign cmd_filter_7_filter_248_wd = reg_wdata[24];

  assign cmd_filter_7_filter_249_wd = reg_wdata[25];

  assign cmd_filter_7_filter_250_wd = reg_wdata[26];

  assign cmd_filter_7_filter_251_wd = reg_wdata[27];

  assign cmd_filter_7_filter_252_wd = reg_wdata[28];

  assign cmd_filter_7_filter_253_wd = reg_wdata[29];

  assign cmd_filter_7_filter_254_wd = reg_wdata[30];

  assign cmd_filter_7_filter_255_wd = reg_wdata[31];

  assign addr_swap_mask_we = racl_addr_hit_write[27] & reg_we & !reg_error;

  assign addr_swap_mask_wd = reg_wdata[31:0];

  assign addr_swap_data_we = racl_addr_hit_write[28] & reg_we & !reg_error;

  assign addr_swap_data_wd = reg_wdata[31:0];

  assign payload_swap_mask_we = racl_addr_hit_write[29] & reg_we & !reg_error;

  assign payload_swap_mask_wd = reg_wdata[31:0];

  assign payload_swap_data_we = racl_addr_hit_write[30] & reg_we & !reg_error;

  assign payload_swap_data_wd = reg_wdata[31:0];

  assign cmd_info_0_we = racl_addr_hit_write[31] & reg_we & !reg_error;

  assign cmd_info_0_opcode_0_wd = reg_wdata[7:0];

  assign cmd_info_0_addr_mode_0_wd = reg_wdata[9:8];

  assign cmd_info_0_addr_swap_en_0_wd = reg_wdata[10];

  assign cmd_info_0_mbyte_en_0_wd = reg_wdata[11];

  assign cmd_info_0_dummy_size_0_wd = reg_wdata[14:12];

  assign cmd_info_0_dummy_en_0_wd = reg_wdata[15];

  assign cmd_info_0_payload_en_0_wd = reg_wdata[19:16];

  assign cmd_info_0_payload_dir_0_wd = reg_wdata[20];

  assign cmd_info_0_payload_swap_en_0_wd = reg_wdata[21];

  assign cmd_info_0_read_pipeline_mode_0_wd = reg_wdata[23:22];

  assign cmd_info_0_upload_0_wd = reg_wdata[24];

  assign cmd_info_0_busy_0_wd = reg_wdata[25];

  assign cmd_info_0_valid_0_wd = reg_wdata[31];

  assign cmd_info_1_we = racl_addr_hit_write[32] & reg_we & !reg_error;

  assign cmd_info_1_opcode_1_wd = reg_wdata[7:0];

  assign cmd_info_1_addr_mode_1_wd = reg_wdata[9:8];

  assign cmd_info_1_addr_swap_en_1_wd = reg_wdata[10];

  assign cmd_info_1_mbyte_en_1_wd = reg_wdata[11];

  assign cmd_info_1_dummy_size_1_wd = reg_wdata[14:12];

  assign cmd_info_1_dummy_en_1_wd = reg_wdata[15];

  assign cmd_info_1_payload_en_1_wd = reg_wdata[19:16];

  assign cmd_info_1_payload_dir_1_wd = reg_wdata[20];

  assign cmd_info_1_payload_swap_en_1_wd = reg_wdata[21];

  assign cmd_info_1_read_pipeline_mode_1_wd = reg_wdata[23:22];

  assign cmd_info_1_upload_1_wd = reg_wdata[24];

  assign cmd_info_1_busy_1_wd = reg_wdata[25];

  assign cmd_info_1_valid_1_wd = reg_wdata[31];

  assign cmd_info_2_we = racl_addr_hit_write[33] & reg_we & !reg_error;

  assign cmd_info_2_opcode_2_wd = reg_wdata[7:0];

  assign cmd_info_2_addr_mode_2_wd = reg_wdata[9:8];

  assign cmd_info_2_addr_swap_en_2_wd = reg_wdata[10];

  assign cmd_info_2_mbyte_en_2_wd = reg_wdata[11];

  assign cmd_info_2_dummy_size_2_wd = reg_wdata[14:12];

  assign cmd_info_2_dummy_en_2_wd = reg_wdata[15];

  assign cmd_info_2_payload_en_2_wd = reg_wdata[19:16];

  assign cmd_info_2_payload_dir_2_wd = reg_wdata[20];

  assign cmd_info_2_payload_swap_en_2_wd = reg_wdata[21];

  assign cmd_info_2_read_pipeline_mode_2_wd = reg_wdata[23:22];

  assign cmd_info_2_upload_2_wd = reg_wdata[24];

  assign cmd_info_2_busy_2_wd = reg_wdata[25];

  assign cmd_info_2_valid_2_wd = reg_wdata[31];

  assign cmd_info_3_we = racl_addr_hit_write[34] & reg_we & !reg_error;

  assign cmd_info_3_opcode_3_wd = reg_wdata[7:0];

  assign cmd_info_3_addr_mode_3_wd = reg_wdata[9:8];

  assign cmd_info_3_addr_swap_en_3_wd = reg_wdata[10];

  assign cmd_info_3_mbyte_en_3_wd = reg_wdata[11];

  assign cmd_info_3_dummy_size_3_wd = reg_wdata[14:12];

  assign cmd_info_3_dummy_en_3_wd = reg_wdata[15];

  assign cmd_info_3_payload_en_3_wd = reg_wdata[19:16];

  assign cmd_info_3_payload_dir_3_wd = reg_wdata[20];

  assign cmd_info_3_payload_swap_en_3_wd = reg_wdata[21];

  assign cmd_info_3_read_pipeline_mode_3_wd = reg_wdata[23:22];

  assign cmd_info_3_upload_3_wd = reg_wdata[24];

  assign cmd_info_3_busy_3_wd = reg_wdata[25];

  assign cmd_info_3_valid_3_wd = reg_wdata[31];

  assign cmd_info_4_we = racl_addr_hit_write[35] & reg_we & !reg_error;

  assign cmd_info_4_opcode_4_wd = reg_wdata[7:0];

  assign cmd_info_4_addr_mode_4_wd = reg_wdata[9:8];

  assign cmd_info_4_addr_swap_en_4_wd = reg_wdata[10];

  assign cmd_info_4_mbyte_en_4_wd = reg_wdata[11];

  assign cmd_info_4_dummy_size_4_wd = reg_wdata[14:12];

  assign cmd_info_4_dummy_en_4_wd = reg_wdata[15];

  assign cmd_info_4_payload_en_4_wd = reg_wdata[19:16];

  assign cmd_info_4_payload_dir_4_wd = reg_wdata[20];

  assign cmd_info_4_payload_swap_en_4_wd = reg_wdata[21];

  assign cmd_info_4_read_pipeline_mode_4_wd = reg_wdata[23:22];

  assign cmd_info_4_upload_4_wd = reg_wdata[24];

  assign cmd_info_4_busy_4_wd = reg_wdata[25];

  assign cmd_info_4_valid_4_wd = reg_wdata[31];

  assign cmd_info_5_we = racl_addr_hit_write[36] & reg_we & !reg_error;

  assign cmd_info_5_opcode_5_wd = reg_wdata[7:0];

  assign cmd_info_5_addr_mode_5_wd = reg_wdata[9:8];

  assign cmd_info_5_addr_swap_en_5_wd = reg_wdata[10];

  assign cmd_info_5_mbyte_en_5_wd = reg_wdata[11];

  assign cmd_info_5_dummy_size_5_wd = reg_wdata[14:12];

  assign cmd_info_5_dummy_en_5_wd = reg_wdata[15];

  assign cmd_info_5_payload_en_5_wd = reg_wdata[19:16];

  assign cmd_info_5_payload_dir_5_wd = reg_wdata[20];

  assign cmd_info_5_payload_swap_en_5_wd = reg_wdata[21];

  assign cmd_info_5_read_pipeline_mode_5_wd = reg_wdata[23:22];

  assign cmd_info_5_upload_5_wd = reg_wdata[24];

  assign cmd_info_5_busy_5_wd = reg_wdata[25];

  assign cmd_info_5_valid_5_wd = reg_wdata[31];

  assign cmd_info_6_we = racl_addr_hit_write[37] & reg_we & !reg_error;

  assign cmd_info_6_opcode_6_wd = reg_wdata[7:0];

  assign cmd_info_6_addr_mode_6_wd = reg_wdata[9:8];

  assign cmd_info_6_addr_swap_en_6_wd = reg_wdata[10];

  assign cmd_info_6_mbyte_en_6_wd = reg_wdata[11];

  assign cmd_info_6_dummy_size_6_wd = reg_wdata[14:12];

  assign cmd_info_6_dummy_en_6_wd = reg_wdata[15];

  assign cmd_info_6_payload_en_6_wd = reg_wdata[19:16];

  assign cmd_info_6_payload_dir_6_wd = reg_wdata[20];

  assign cmd_info_6_payload_swap_en_6_wd = reg_wdata[21];

  assign cmd_info_6_read_pipeline_mode_6_wd = reg_wdata[23:22];

  assign cmd_info_6_upload_6_wd = reg_wdata[24];

  assign cmd_info_6_busy_6_wd = reg_wdata[25];

  assign cmd_info_6_valid_6_wd = reg_wdata[31];

  assign cmd_info_7_we = racl_addr_hit_write[38] & reg_we & !reg_error;

  assign cmd_info_7_opcode_7_wd = reg_wdata[7:0];

  assign cmd_info_7_addr_mode_7_wd = reg_wdata[9:8];

  assign cmd_info_7_addr_swap_en_7_wd = reg_wdata[10];

  assign cmd_info_7_mbyte_en_7_wd = reg_wdata[11];

  assign cmd_info_7_dummy_size_7_wd = reg_wdata[14:12];

  assign cmd_info_7_dummy_en_7_wd = reg_wdata[15];

  assign cmd_info_7_payload_en_7_wd = reg_wdata[19:16];

  assign cmd_info_7_payload_dir_7_wd = reg_wdata[20];

  assign cmd_info_7_payload_swap_en_7_wd = reg_wdata[21];

  assign cmd_info_7_read_pipeline_mode_7_wd = reg_wdata[23:22];

  assign cmd_info_7_upload_7_wd = reg_wdata[24];

  assign cmd_info_7_busy_7_wd = reg_wdata[25];

  assign cmd_info_7_valid_7_wd = reg_wdata[31];

  assign cmd_info_8_we = racl_addr_hit_write[39] & reg_we & !reg_error;

  assign cmd_info_8_opcode_8_wd = reg_wdata[7:0];

  assign cmd_info_8_addr_mode_8_wd = reg_wdata[9:8];

  assign cmd_info_8_addr_swap_en_8_wd = reg_wdata[10];

  assign cmd_info_8_mbyte_en_8_wd = reg_wdata[11];

  assign cmd_info_8_dummy_size_8_wd = reg_wdata[14:12];

  assign cmd_info_8_dummy_en_8_wd = reg_wdata[15];

  assign cmd_info_8_payload_en_8_wd = reg_wdata[19:16];

  assign cmd_info_8_payload_dir_8_wd = reg_wdata[20];

  assign cmd_info_8_payload_swap_en_8_wd = reg_wdata[21];

  assign cmd_info_8_read_pipeline_mode_8_wd = reg_wdata[23:22];

  assign cmd_info_8_upload_8_wd = reg_wdata[24];

  assign cmd_info_8_busy_8_wd = reg_wdata[25];

  assign cmd_info_8_valid_8_wd = reg_wdata[31];

  assign cmd_info_9_we = racl_addr_hit_write[40] & reg_we & !reg_error;

  assign cmd_info_9_opcode_9_wd = reg_wdata[7:0];

  assign cmd_info_9_addr_mode_9_wd = reg_wdata[9:8];

  assign cmd_info_9_addr_swap_en_9_wd = reg_wdata[10];

  assign cmd_info_9_mbyte_en_9_wd = reg_wdata[11];

  assign cmd_info_9_dummy_size_9_wd = reg_wdata[14:12];

  assign cmd_info_9_dummy_en_9_wd = reg_wdata[15];

  assign cmd_info_9_payload_en_9_wd = reg_wdata[19:16];

  assign cmd_info_9_payload_dir_9_wd = reg_wdata[20];

  assign cmd_info_9_payload_swap_en_9_wd = reg_wdata[21];

  assign cmd_info_9_read_pipeline_mode_9_wd = reg_wdata[23:22];

  assign cmd_info_9_upload_9_wd = reg_wdata[24];

  assign cmd_info_9_busy_9_wd = reg_wdata[25];

  assign cmd_info_9_valid_9_wd = reg_wdata[31];

  assign cmd_info_10_we = racl_addr_hit_write[41] & reg_we & !reg_error;

  assign cmd_info_10_opcode_10_wd = reg_wdata[7:0];

  assign cmd_info_10_addr_mode_10_wd = reg_wdata[9:8];

  assign cmd_info_10_addr_swap_en_10_wd = reg_wdata[10];

  assign cmd_info_10_mbyte_en_10_wd = reg_wdata[11];

  assign cmd_info_10_dummy_size_10_wd = reg_wdata[14:12];

  assign cmd_info_10_dummy_en_10_wd = reg_wdata[15];

  assign cmd_info_10_payload_en_10_wd = reg_wdata[19:16];

  assign cmd_info_10_payload_dir_10_wd = reg_wdata[20];

  assign cmd_info_10_payload_swap_en_10_wd = reg_wdata[21];

  assign cmd_info_10_read_pipeline_mode_10_wd = reg_wdata[23:22];

  assign cmd_info_10_upload_10_wd = reg_wdata[24];

  assign cmd_info_10_busy_10_wd = reg_wdata[25];

  assign cmd_info_10_valid_10_wd = reg_wdata[31];

  assign cmd_info_11_we = racl_addr_hit_write[42] & reg_we & !reg_error;

  assign cmd_info_11_opcode_11_wd = reg_wdata[7:0];

  assign cmd_info_11_addr_mode_11_wd = reg_wdata[9:8];

  assign cmd_info_11_addr_swap_en_11_wd = reg_wdata[10];

  assign cmd_info_11_mbyte_en_11_wd = reg_wdata[11];

  assign cmd_info_11_dummy_size_11_wd = reg_wdata[14:12];

  assign cmd_info_11_dummy_en_11_wd = reg_wdata[15];

  assign cmd_info_11_payload_en_11_wd = reg_wdata[19:16];

  assign cmd_info_11_payload_dir_11_wd = reg_wdata[20];

  assign cmd_info_11_payload_swap_en_11_wd = reg_wdata[21];

  assign cmd_info_11_read_pipeline_mode_11_wd = reg_wdata[23:22];

  assign cmd_info_11_upload_11_wd = reg_wdata[24];

  assign cmd_info_11_busy_11_wd = reg_wdata[25];

  assign cmd_info_11_valid_11_wd = reg_wdata[31];

  assign cmd_info_12_we = racl_addr_hit_write[43] & reg_we & !reg_error;

  assign cmd_info_12_opcode_12_wd = reg_wdata[7:0];

  assign cmd_info_12_addr_mode_12_wd = reg_wdata[9:8];

  assign cmd_info_12_addr_swap_en_12_wd = reg_wdata[10];

  assign cmd_info_12_mbyte_en_12_wd = reg_wdata[11];

  assign cmd_info_12_dummy_size_12_wd = reg_wdata[14:12];

  assign cmd_info_12_dummy_en_12_wd = reg_wdata[15];

  assign cmd_info_12_payload_en_12_wd = reg_wdata[19:16];

  assign cmd_info_12_payload_dir_12_wd = reg_wdata[20];

  assign cmd_info_12_payload_swap_en_12_wd = reg_wdata[21];

  assign cmd_info_12_read_pipeline_mode_12_wd = reg_wdata[23:22];

  assign cmd_info_12_upload_12_wd = reg_wdata[24];

  assign cmd_info_12_busy_12_wd = reg_wdata[25];

  assign cmd_info_12_valid_12_wd = reg_wdata[31];

  assign cmd_info_13_we = racl_addr_hit_write[44] & reg_we & !reg_error;

  assign cmd_info_13_opcode_13_wd = reg_wdata[7:0];

  assign cmd_info_13_addr_mode_13_wd = reg_wdata[9:8];

  assign cmd_info_13_addr_swap_en_13_wd = reg_wdata[10];

  assign cmd_info_13_mbyte_en_13_wd = reg_wdata[11];

  assign cmd_info_13_dummy_size_13_wd = reg_wdata[14:12];

  assign cmd_info_13_dummy_en_13_wd = reg_wdata[15];

  assign cmd_info_13_payload_en_13_wd = reg_wdata[19:16];

  assign cmd_info_13_payload_dir_13_wd = reg_wdata[20];

  assign cmd_info_13_payload_swap_en_13_wd = reg_wdata[21];

  assign cmd_info_13_read_pipeline_mode_13_wd = reg_wdata[23:22];

  assign cmd_info_13_upload_13_wd = reg_wdata[24];

  assign cmd_info_13_busy_13_wd = reg_wdata[25];

  assign cmd_info_13_valid_13_wd = reg_wdata[31];

  assign cmd_info_14_we = racl_addr_hit_write[45] & reg_we & !reg_error;

  assign cmd_info_14_opcode_14_wd = reg_wdata[7:0];

  assign cmd_info_14_addr_mode_14_wd = reg_wdata[9:8];

  assign cmd_info_14_addr_swap_en_14_wd = reg_wdata[10];

  assign cmd_info_14_mbyte_en_14_wd = reg_wdata[11];

  assign cmd_info_14_dummy_size_14_wd = reg_wdata[14:12];

  assign cmd_info_14_dummy_en_14_wd = reg_wdata[15];

  assign cmd_info_14_payload_en_14_wd = reg_wdata[19:16];

  assign cmd_info_14_payload_dir_14_wd = reg_wdata[20];

  assign cmd_info_14_payload_swap_en_14_wd = reg_wdata[21];

  assign cmd_info_14_read_pipeline_mode_14_wd = reg_wdata[23:22];

  assign cmd_info_14_upload_14_wd = reg_wdata[24];

  assign cmd_info_14_busy_14_wd = reg_wdata[25];

  assign cmd_info_14_valid_14_wd = reg_wdata[31];

  assign cmd_info_15_we = racl_addr_hit_write[46] & reg_we & !reg_error;

  assign cmd_info_15_opcode_15_wd = reg_wdata[7:0];

  assign cmd_info_15_addr_mode_15_wd = reg_wdata[9:8];

  assign cmd_info_15_addr_swap_en_15_wd = reg_wdata[10];

  assign cmd_info_15_mbyte_en_15_wd = reg_wdata[11];

  assign cmd_info_15_dummy_size_15_wd = reg_wdata[14:12];

  assign cmd_info_15_dummy_en_15_wd = reg_wdata[15];

  assign cmd_info_15_payload_en_15_wd = reg_wdata[19:16];

  assign cmd_info_15_payload_dir_15_wd = reg_wdata[20];

  assign cmd_info_15_payload_swap_en_15_wd = reg_wdata[21];

  assign cmd_info_15_read_pipeline_mode_15_wd = reg_wdata[23:22];

  assign cmd_info_15_upload_15_wd = reg_wdata[24];

  assign cmd_info_15_busy_15_wd = reg_wdata[25];

  assign cmd_info_15_valid_15_wd = reg_wdata[31];

  assign cmd_info_16_we = racl_addr_hit_write[47] & reg_we & !reg_error;

  assign cmd_info_16_opcode_16_wd = reg_wdata[7:0];

  assign cmd_info_16_addr_mode_16_wd = reg_wdata[9:8];

  assign cmd_info_16_addr_swap_en_16_wd = reg_wdata[10];

  assign cmd_info_16_mbyte_en_16_wd = reg_wdata[11];

  assign cmd_info_16_dummy_size_16_wd = reg_wdata[14:12];

  assign cmd_info_16_dummy_en_16_wd = reg_wdata[15];

  assign cmd_info_16_payload_en_16_wd = reg_wdata[19:16];

  assign cmd_info_16_payload_dir_16_wd = reg_wdata[20];

  assign cmd_info_16_payload_swap_en_16_wd = reg_wdata[21];

  assign cmd_info_16_read_pipeline_mode_16_wd = reg_wdata[23:22];

  assign cmd_info_16_upload_16_wd = reg_wdata[24];

  assign cmd_info_16_busy_16_wd = reg_wdata[25];

  assign cmd_info_16_valid_16_wd = reg_wdata[31];

  assign cmd_info_17_we = racl_addr_hit_write[48] & reg_we & !reg_error;

  assign cmd_info_17_opcode_17_wd = reg_wdata[7:0];

  assign cmd_info_17_addr_mode_17_wd = reg_wdata[9:8];

  assign cmd_info_17_addr_swap_en_17_wd = reg_wdata[10];

  assign cmd_info_17_mbyte_en_17_wd = reg_wdata[11];

  assign cmd_info_17_dummy_size_17_wd = reg_wdata[14:12];

  assign cmd_info_17_dummy_en_17_wd = reg_wdata[15];

  assign cmd_info_17_payload_en_17_wd = reg_wdata[19:16];

  assign cmd_info_17_payload_dir_17_wd = reg_wdata[20];

  assign cmd_info_17_payload_swap_en_17_wd = reg_wdata[21];

  assign cmd_info_17_read_pipeline_mode_17_wd = reg_wdata[23:22];

  assign cmd_info_17_upload_17_wd = reg_wdata[24];

  assign cmd_info_17_busy_17_wd = reg_wdata[25];

  assign cmd_info_17_valid_17_wd = reg_wdata[31];

  assign cmd_info_18_we = racl_addr_hit_write[49] & reg_we & !reg_error;

  assign cmd_info_18_opcode_18_wd = reg_wdata[7:0];

  assign cmd_info_18_addr_mode_18_wd = reg_wdata[9:8];

  assign cmd_info_18_addr_swap_en_18_wd = reg_wdata[10];

  assign cmd_info_18_mbyte_en_18_wd = reg_wdata[11];

  assign cmd_info_18_dummy_size_18_wd = reg_wdata[14:12];

  assign cmd_info_18_dummy_en_18_wd = reg_wdata[15];

  assign cmd_info_18_payload_en_18_wd = reg_wdata[19:16];

  assign cmd_info_18_payload_dir_18_wd = reg_wdata[20];

  assign cmd_info_18_payload_swap_en_18_wd = reg_wdata[21];

  assign cmd_info_18_read_pipeline_mode_18_wd = reg_wdata[23:22];

  assign cmd_info_18_upload_18_wd = reg_wdata[24];

  assign cmd_info_18_busy_18_wd = reg_wdata[25];

  assign cmd_info_18_valid_18_wd = reg_wdata[31];

  assign cmd_info_19_we = racl_addr_hit_write[50] & reg_we & !reg_error;

  assign cmd_info_19_opcode_19_wd = reg_wdata[7:0];

  assign cmd_info_19_addr_mode_19_wd = reg_wdata[9:8];

  assign cmd_info_19_addr_swap_en_19_wd = reg_wdata[10];

  assign cmd_info_19_mbyte_en_19_wd = reg_wdata[11];

  assign cmd_info_19_dummy_size_19_wd = reg_wdata[14:12];

  assign cmd_info_19_dummy_en_19_wd = reg_wdata[15];

  assign cmd_info_19_payload_en_19_wd = reg_wdata[19:16];

  assign cmd_info_19_payload_dir_19_wd = reg_wdata[20];

  assign cmd_info_19_payload_swap_en_19_wd = reg_wdata[21];

  assign cmd_info_19_read_pipeline_mode_19_wd = reg_wdata[23:22];

  assign cmd_info_19_upload_19_wd = reg_wdata[24];

  assign cmd_info_19_busy_19_wd = reg_wdata[25];

  assign cmd_info_19_valid_19_wd = reg_wdata[31];

  assign cmd_info_20_we = racl_addr_hit_write[51] & reg_we & !reg_error;

  assign cmd_info_20_opcode_20_wd = reg_wdata[7:0];

  assign cmd_info_20_addr_mode_20_wd = reg_wdata[9:8];

  assign cmd_info_20_addr_swap_en_20_wd = reg_wdata[10];

  assign cmd_info_20_mbyte_en_20_wd = reg_wdata[11];

  assign cmd_info_20_dummy_size_20_wd = reg_wdata[14:12];

  assign cmd_info_20_dummy_en_20_wd = reg_wdata[15];

  assign cmd_info_20_payload_en_20_wd = reg_wdata[19:16];

  assign cmd_info_20_payload_dir_20_wd = reg_wdata[20];

  assign cmd_info_20_payload_swap_en_20_wd = reg_wdata[21];

  assign cmd_info_20_read_pipeline_mode_20_wd = reg_wdata[23:22];

  assign cmd_info_20_upload_20_wd = reg_wdata[24];

  assign cmd_info_20_busy_20_wd = reg_wdata[25];

  assign cmd_info_20_valid_20_wd = reg_wdata[31];

  assign cmd_info_21_we = racl_addr_hit_write[52] & reg_we & !reg_error;

  assign cmd_info_21_opcode_21_wd = reg_wdata[7:0];

  assign cmd_info_21_addr_mode_21_wd = reg_wdata[9:8];

  assign cmd_info_21_addr_swap_en_21_wd = reg_wdata[10];

  assign cmd_info_21_mbyte_en_21_wd = reg_wdata[11];

  assign cmd_info_21_dummy_size_21_wd = reg_wdata[14:12];

  assign cmd_info_21_dummy_en_21_wd = reg_wdata[15];

  assign cmd_info_21_payload_en_21_wd = reg_wdata[19:16];

  assign cmd_info_21_payload_dir_21_wd = reg_wdata[20];

  assign cmd_info_21_payload_swap_en_21_wd = reg_wdata[21];

  assign cmd_info_21_read_pipeline_mode_21_wd = reg_wdata[23:22];

  assign cmd_info_21_upload_21_wd = reg_wdata[24];

  assign cmd_info_21_busy_21_wd = reg_wdata[25];

  assign cmd_info_21_valid_21_wd = reg_wdata[31];

  assign cmd_info_22_we = racl_addr_hit_write[53] & reg_we & !reg_error;

  assign cmd_info_22_opcode_22_wd = reg_wdata[7:0];

  assign cmd_info_22_addr_mode_22_wd = reg_wdata[9:8];

  assign cmd_info_22_addr_swap_en_22_wd = reg_wdata[10];

  assign cmd_info_22_mbyte_en_22_wd = reg_wdata[11];

  assign cmd_info_22_dummy_size_22_wd = reg_wdata[14:12];

  assign cmd_info_22_dummy_en_22_wd = reg_wdata[15];

  assign cmd_info_22_payload_en_22_wd = reg_wdata[19:16];

  assign cmd_info_22_payload_dir_22_wd = reg_wdata[20];

  assign cmd_info_22_payload_swap_en_22_wd = reg_wdata[21];

  assign cmd_info_22_read_pipeline_mode_22_wd = reg_wdata[23:22];

  assign cmd_info_22_upload_22_wd = reg_wdata[24];

  assign cmd_info_22_busy_22_wd = reg_wdata[25];

  assign cmd_info_22_valid_22_wd = reg_wdata[31];

  assign cmd_info_23_we = racl_addr_hit_write[54] & reg_we & !reg_error;

  assign cmd_info_23_opcode_23_wd = reg_wdata[7:0];

  assign cmd_info_23_addr_mode_23_wd = reg_wdata[9:8];

  assign cmd_info_23_addr_swap_en_23_wd = reg_wdata[10];

  assign cmd_info_23_mbyte_en_23_wd = reg_wdata[11];

  assign cmd_info_23_dummy_size_23_wd = reg_wdata[14:12];

  assign cmd_info_23_dummy_en_23_wd = reg_wdata[15];

  assign cmd_info_23_payload_en_23_wd = reg_wdata[19:16];

  assign cmd_info_23_payload_dir_23_wd = reg_wdata[20];

  assign cmd_info_23_payload_swap_en_23_wd = reg_wdata[21];

  assign cmd_info_23_read_pipeline_mode_23_wd = reg_wdata[23:22];

  assign cmd_info_23_upload_23_wd = reg_wdata[24];

  assign cmd_info_23_busy_23_wd = reg_wdata[25];

  assign cmd_info_23_valid_23_wd = reg_wdata[31];

  assign cmd_info_en4b_we = racl_addr_hit_write[55] & reg_we & !reg_error;

  assign cmd_info_en4b_opcode_wd = reg_wdata[7:0];

  assign cmd_info_en4b_valid_wd = reg_wdata[31];

  assign cmd_info_ex4b_we = racl_addr_hit_write[56] & reg_we & !reg_error;

  assign cmd_info_ex4b_opcode_wd = reg_wdata[7:0];

  assign cmd_info_ex4b_valid_wd = reg_wdata[31];

  assign cmd_info_wren_we = racl_addr_hit_write[57] & reg_we & !reg_error;

  assign cmd_info_wren_opcode_wd = reg_wdata[7:0];

  assign cmd_info_wren_valid_wd = reg_wdata[31];

  assign cmd_info_wrdi_we = racl_addr_hit_write[58] & reg_we & !reg_error;

  assign cmd_info_wrdi_opcode_wd = reg_wdata[7:0];

  assign cmd_info_wrdi_valid_wd = reg_wdata[31];

  assign tpm_cfg_we = racl_addr_hit_write[60] & reg_we & !reg_error;

  assign tpm_cfg_en_wd = reg_wdata[0];

  assign tpm_cfg_tpm_mode_wd = reg_wdata[1];

  assign tpm_cfg_hw_reg_dis_wd = reg_wdata[2];

  assign tpm_cfg_tpm_reg_chk_dis_wd = reg_wdata[3];

  assign tpm_cfg_invalid_locality_wd = reg_wdata[4];

  assign tpm_status_re = racl_addr_hit_read[61] & reg_re & !reg_error;
  assign tpm_status_we = racl_addr_hit_write[61] & reg_we & !reg_error;

  assign tpm_status_wrfifo_pending_wd = reg_wdata[1];

  assign tpm_access_0_we = racl_addr_hit_write[62] & reg_we & !reg_error;

  assign tpm_access_0_access_0_wd = reg_wdata[7:0];

  assign tpm_access_0_access_1_wd = reg_wdata[15:8];

  assign tpm_access_0_access_2_wd = reg_wdata[23:16];

  assign tpm_access_0_access_3_wd = reg_wdata[31:24];

  assign tpm_access_1_we = racl_addr_hit_write[63] & reg_we & !reg_error;

  assign tpm_access_1_wd = reg_wdata[7:0];

  assign tpm_sts_we = racl_addr_hit_write[64] & reg_we & !reg_error;

  assign tpm_sts_wd = reg_wdata[31:0];

  assign tpm_intf_capability_we = racl_addr_hit_write[65] & reg_we & !reg_error;

  assign tpm_intf_capability_wd = reg_wdata[31:0];

  assign tpm_int_enable_we = racl_addr_hit_write[66] & reg_we & !reg_error;

  assign tpm_int_enable_wd = reg_wdata[31:0];

  assign tpm_int_vector_we = racl_addr_hit_write[67] & reg_we & !reg_error;

  assign tpm_int_vector_wd = reg_wdata[7:0];

  assign tpm_int_status_we = racl_addr_hit_write[68] & reg_we & !reg_error;

  assign tpm_int_status_wd = reg_wdata[31:0];

  assign tpm_did_vid_we = racl_addr_hit_write[69] & reg_we & !reg_error;

  assign tpm_did_vid_vid_wd = reg_wdata[15:0];

  assign tpm_did_vid_did_wd = reg_wdata[31:16];

  assign tpm_rid_we = racl_addr_hit_write[70] & reg_we & !reg_error;

  assign tpm_rid_wd = reg_wdata[7:0];

  assign tpm_cmd_addr_re = racl_addr_hit_read[71] & reg_re & !reg_error;
  assign tpm_read_fifo_we = racl_addr_hit_write[72] & reg_we & !reg_error;

  assign tpm_read_fifo_wd = reg_wdata[31:0];


  // Assign write-enables to checker logic vector.
  always_comb begin
    reg_we_check[0] = intr_state_we;
    reg_we_check[1] = intr_enable_we;
    reg_we_check[2] = intr_test_we;
    reg_we_check[3] = alert_test_we;
    reg_we_check[4] = control_we;
    reg_we_check[5] = cfg_we;
    reg_we_check[6] = 1'b0;
    reg_we_check[7] = intercept_en_we;
    reg_we_check[8] = addr_mode_we;
    reg_we_check[9] = 1'b0;
    reg_we_check[10] = flash_status_we;
    reg_we_check[11] = jedec_cc_we;
    reg_we_check[12] = jedec_id_we;
    reg_we_check[13] = read_threshold_we;
    reg_we_check[14] = mailbox_addr_we;
    reg_we_check[15] = 1'b0;
    reg_we_check[16] = 1'b0;
    reg_we_check[17] = 1'b0;
    reg_we_check[18] = 1'b0;
    reg_we_check[19] = cmd_filter_0_we;
    reg_we_check[20] = cmd_filter_1_we;
    reg_we_check[21] = cmd_filter_2_we;
    reg_we_check[22] = cmd_filter_3_we;
    reg_we_check[23] = cmd_filter_4_we;
    reg_we_check[24] = cmd_filter_5_we;
    reg_we_check[25] = cmd_filter_6_we;
    reg_we_check[26] = cmd_filter_7_we;
    reg_we_check[27] = addr_swap_mask_we;
    reg_we_check[28] = addr_swap_data_we;
    reg_we_check[29] = payload_swap_mask_we;
    reg_we_check[30] = payload_swap_data_we;
    reg_we_check[31] = cmd_info_0_we;
    reg_we_check[32] = cmd_info_1_we;
    reg_we_check[33] = cmd_info_2_we;
    reg_we_check[34] = cmd_info_3_we;
    reg_we_check[35] = cmd_info_4_we;
    reg_we_check[36] = cmd_info_5_we;
    reg_we_check[37] = cmd_info_6_we;
    reg_we_check[38] = cmd_info_7_we;
    reg_we_check[39] = cmd_info_8_we;
    reg_we_check[40] = cmd_info_9_we;
    reg_we_check[41] = cmd_info_10_we;
    reg_we_check[42] = cmd_info_11_we;
    reg_we_check[43] = cmd_info_12_we;
    reg_we_check[44] = cmd_info_13_we;
    reg_we_check[45] = cmd_info_14_we;
    reg_we_check[46] = cmd_info_15_we;
    reg_we_check[47] = cmd_info_16_we;
    reg_we_check[48] = cmd_info_17_we;
    reg_we_check[49] = cmd_info_18_we;
    reg_we_check[50] = cmd_info_19_we;
    reg_we_check[51] = cmd_info_20_we;
    reg_we_check[52] = cmd_info_21_we;
    reg_we_check[53] = cmd_info_22_we;
    reg_we_check[54] = cmd_info_23_we;
    reg_we_check[55] = cmd_info_en4b_we;
    reg_we_check[56] = cmd_info_ex4b_we;
    reg_we_check[57] = cmd_info_wren_we;
    reg_we_check[58] = cmd_info_wrdi_we;
    reg_we_check[59] = 1'b0;
    reg_we_check[60] = tpm_cfg_we;
    reg_we_check[61] = tpm_status_we;
    reg_we_check[62] = tpm_access_0_we;
    reg_we_check[63] = tpm_access_1_we;
    reg_we_check[64] = tpm_sts_we;
    reg_we_check[65] = tpm_intf_capability_we;
    reg_we_check[66] = tpm_int_enable_we;
    reg_we_check[67] = tpm_int_vector_we;
    reg_we_check[68] = tpm_int_status_we;
    reg_we_check[69] = tpm_did_vid_we;
    reg_we_check[70] = tpm_rid_we;
    reg_we_check[71] = 1'b0;
    reg_we_check[72] = tpm_read_fifo_we;
  end

  // Read data return
  always_comb begin
    reg_rdata_next = '0;
    unique case (1'b1)
      racl_addr_hit_read[0]: begin
        reg_rdata_next[0] = intr_state_upload_cmdfifo_not_empty_qs;
        reg_rdata_next[1] = intr_state_upload_payload_not_empty_qs;
        reg_rdata_next[2] = intr_state_upload_payload_overflow_qs;
        reg_rdata_next[3] = intr_state_readbuf_watermark_qs;
        reg_rdata_next[4] = intr_state_readbuf_flip_qs;
        reg_rdata_next[5] = intr_state_tpm_header_not_empty_qs;
        reg_rdata_next[6] = intr_state_tpm_rdfifo_cmd_end_qs;
        reg_rdata_next[7] = intr_state_tpm_rdfifo_drop_qs;
      end

      racl_addr_hit_read[1]: begin
        reg_rdata_next[0] = intr_enable_upload_cmdfifo_not_empty_qs;
        reg_rdata_next[1] = intr_enable_upload_payload_not_empty_qs;
        reg_rdata_next[2] = intr_enable_upload_payload_overflow_qs;
        reg_rdata_next[3] = intr_enable_readbuf_watermark_qs;
        reg_rdata_next[4] = intr_enable_readbuf_flip_qs;
        reg_rdata_next[5] = intr_enable_tpm_header_not_empty_qs;
        reg_rdata_next[6] = intr_enable_tpm_rdfifo_cmd_end_qs;
        reg_rdata_next[7] = intr_enable_tpm_rdfifo_drop_qs;
      end

      racl_addr_hit_read[2]: begin
        reg_rdata_next[0] = '0;
        reg_rdata_next[1] = '0;
        reg_rdata_next[2] = '0;
        reg_rdata_next[3] = '0;
        reg_rdata_next[4] = '0;
        reg_rdata_next[5] = '0;
        reg_rdata_next[6] = '0;
        reg_rdata_next[7] = '0;
      end

      racl_addr_hit_read[3]: begin
        reg_rdata_next[0] = '0;
      end

      racl_addr_hit_read[4]: begin
        reg_rdata_next[0] = control_flash_status_fifo_clr_qs;
        reg_rdata_next[1] = control_flash_read_buffer_clr_qs;
        reg_rdata_next[5:4] = control_mode_qs;
      end

      racl_addr_hit_read[5]: begin
        reg_rdata_next[2] = cfg_tx_order_qs;
        reg_rdata_next[3] = cfg_rx_order_qs;
        reg_rdata_next[24] = cfg_mailbox_en_qs;
      end

      racl_addr_hit_read[6]: begin
        reg_rdata_next[5] = status_csb_qs;
        reg_rdata_next[6] = status_tpm_csb_qs;
      end

      racl_addr_hit_read[7]: begin
        reg_rdata_next[0] = intercept_en_status_qs;
        reg_rdata_next[1] = intercept_en_jedec_qs;
        reg_rdata_next[2] = intercept_en_sfdp_qs;
        reg_rdata_next[3] = intercept_en_mbx_qs;
      end

      racl_addr_hit_read[8]: begin
        reg_rdata_next[0] = addr_mode_addr_4b_en_qs;
        reg_rdata_next[31] = addr_mode_pending_qs;
      end

      racl_addr_hit_read[9]: begin
        reg_rdata_next[31:0] = last_read_addr_qs;
      end

      racl_addr_hit_read[10]: begin
        reg_rdata_next[0] = flash_status_busy_qs;
        reg_rdata_next[1] = flash_status_wel_qs;
        reg_rdata_next[23:2] = flash_status_status_qs;
      end

      racl_addr_hit_read[11]: begin
        reg_rdata_next[7:0] = jedec_cc_cc_qs;
        reg_rdata_next[15:8] = jedec_cc_num_cc_qs;
      end

      racl_addr_hit_read[12]: begin
        reg_rdata_next[15:0] = jedec_id_id_qs;
        reg_rdata_next[23:16] = jedec_id_mf_qs;
      end

      racl_addr_hit_read[13]: begin
        reg_rdata_next[9:0] = read_threshold_qs;
      end

      racl_addr_hit_read[14]: begin
        reg_rdata_next[31:0] = mailbox_addr_qs;
      end

      racl_addr_hit_read[15]: begin
        reg_rdata_next[4:0] = upload_status_cmdfifo_depth_qs;
        reg_rdata_next[7] = upload_status_cmdfifo_notempty_qs;
        reg_rdata_next[12:8] = upload_status_addrfifo_depth_qs;
        reg_rdata_next[15] = upload_status_addrfifo_notempty_qs;
      end

      racl_addr_hit_read[16]: begin
        reg_rdata_next[8:0] = upload_status2_payload_depth_qs;
        reg_rdata_next[23:16] = upload_status2_payload_start_idx_qs;
      end

      racl_addr_hit_read[17]: begin
        reg_rdata_next[7:0] = upload_cmdfifo_data_qs;
        reg_rdata_next[13] = upload_cmdfifo_busy_qs;
        reg_rdata_next[14] = upload_cmdfifo_wel_qs;
        reg_rdata_next[15] = upload_cmdfifo_addr4b_mode_qs;
      end

      racl_addr_hit_read[18]: begin
        reg_rdata_next[31:0] = upload_addrfifo_qs;
      end

      racl_addr_hit_read[19]: begin
        reg_rdata_next[0] = cmd_filter_0_filter_0_qs;
        reg_rdata_next[1] = cmd_filter_0_filter_1_qs;
        reg_rdata_next[2] = cmd_filter_0_filter_2_qs;
        reg_rdata_next[3] = cmd_filter_0_filter_3_qs;
        reg_rdata_next[4] = cmd_filter_0_filter_4_qs;
        reg_rdata_next[5] = cmd_filter_0_filter_5_qs;
        reg_rdata_next[6] = cmd_filter_0_filter_6_qs;
        reg_rdata_next[7] = cmd_filter_0_filter_7_qs;
        reg_rdata_next[8] = cmd_filter_0_filter_8_qs;
        reg_rdata_next[9] = cmd_filter_0_filter_9_qs;
        reg_rdata_next[10] = cmd_filter_0_filter_10_qs;
        reg_rdata_next[11] = cmd_filter_0_filter_11_qs;
        reg_rdata_next[12] = cmd_filter_0_filter_12_qs;
        reg_rdata_next[13] = cmd_filter_0_filter_13_qs;
        reg_rdata_next[14] = cmd_filter_0_filter_14_qs;
        reg_rdata_next[15] = cmd_filter_0_filter_15_qs;
        reg_rdata_next[16] = cmd_filter_0_filter_16_qs;
        reg_rdata_next[17] = cmd_filter_0_filter_17_qs;
        reg_rdata_next[18] = cmd_filter_0_filter_18_qs;
        reg_rdata_next[19] = cmd_filter_0_filter_19_qs;
        reg_rdata_next[20] = cmd_filter_0_filter_20_qs;
        reg_rdata_next[21] = cmd_filter_0_filter_21_qs;
        reg_rdata_next[22] = cmd_filter_0_filter_22_qs;
        reg_rdata_next[23] = cmd_filter_0_filter_23_qs;
        reg_rdata_next[24] = cmd_filter_0_filter_24_qs;
        reg_rdata_next[25] = cmd_filter_0_filter_25_qs;
        reg_rdata_next[26] = cmd_filter_0_filter_26_qs;
        reg_rdata_next[27] = cmd_filter_0_filter_27_qs;
        reg_rdata_next[28] = cmd_filter_0_filter_28_qs;
        reg_rdata_next[29] = cmd_filter_0_filter_29_qs;
        reg_rdata_next[30] = cmd_filter_0_filter_30_qs;
        reg_rdata_next[31] = cmd_filter_0_filter_31_qs;
      end

      racl_addr_hit_read[20]: begin
        reg_rdata_next[0] = cmd_filter_1_filter_32_qs;
        reg_rdata_next[1] = cmd_filter_1_filter_33_qs;
        reg_rdata_next[2] = cmd_filter_1_filter_34_qs;
        reg_rdata_next[3] = cmd_filter_1_filter_35_qs;
        reg_rdata_next[4] = cmd_filter_1_filter_36_qs;
        reg_rdata_next[5] = cmd_filter_1_filter_37_qs;
        reg_rdata_next[6] = cmd_filter_1_filter_38_qs;
        reg_rdata_next[7] = cmd_filter_1_filter_39_qs;
        reg_rdata_next[8] = cmd_filter_1_filter_40_qs;
        reg_rdata_next[9] = cmd_filter_1_filter_41_qs;
        reg_rdata_next[10] = cmd_filter_1_filter_42_qs;
        reg_rdata_next[11] = cmd_filter_1_filter_43_qs;
        reg_rdata_next[12] = cmd_filter_1_filter_44_qs;
        reg_rdata_next[13] = cmd_filter_1_filter_45_qs;
        reg_rdata_next[14] = cmd_filter_1_filter_46_qs;
        reg_rdata_next[15] = cmd_filter_1_filter_47_qs;
        reg_rdata_next[16] = cmd_filter_1_filter_48_qs;
        reg_rdata_next[17] = cmd_filter_1_filter_49_qs;
        reg_rdata_next[18] = cmd_filter_1_filter_50_qs;
        reg_rdata_next[19] = cmd_filter_1_filter_51_qs;
        reg_rdata_next[20] = cmd_filter_1_filter_52_qs;
        reg_rdata_next[21] = cmd_filter_1_filter_53_qs;
        reg_rdata_next[22] = cmd_filter_1_filter_54_qs;
        reg_rdata_next[23] = cmd_filter_1_filter_55_qs;
        reg_rdata_next[24] = cmd_filter_1_filter_56_qs;
        reg_rdata_next[25] = cmd_filter_1_filter_57_qs;
        reg_rdata_next[26] = cmd_filter_1_filter_58_qs;
        reg_rdata_next[27] = cmd_filter_1_filter_59_qs;
        reg_rdata_next[28] = cmd_filter_1_filter_60_qs;
        reg_rdata_next[29] = cmd_filter_1_filter_61_qs;
        reg_rdata_next[30] = cmd_filter_1_filter_62_qs;
        reg_rdata_next[31] = cmd_filter_1_filter_63_qs;
      end

      racl_addr_hit_read[21]: begin
        reg_rdata_next[0] = cmd_filter_2_filter_64_qs;
        reg_rdata_next[1] = cmd_filter_2_filter_65_qs;
        reg_rdata_next[2] = cmd_filter_2_filter_66_qs;
        reg_rdata_next[3] = cmd_filter_2_filter_67_qs;
        reg_rdata_next[4] = cmd_filter_2_filter_68_qs;
        reg_rdata_next[5] = cmd_filter_2_filter_69_qs;
        reg_rdata_next[6] = cmd_filter_2_filter_70_qs;
        reg_rdata_next[7] = cmd_filter_2_filter_71_qs;
        reg_rdata_next[8] = cmd_filter_2_filter_72_qs;
        reg_rdata_next[9] = cmd_filter_2_filter_73_qs;
        reg_rdata_next[10] = cmd_filter_2_filter_74_qs;
        reg_rdata_next[11] = cmd_filter_2_filter_75_qs;
        reg_rdata_next[12] = cmd_filter_2_filter_76_qs;
        reg_rdata_next[13] = cmd_filter_2_filter_77_qs;
        reg_rdata_next[14] = cmd_filter_2_filter_78_qs;
        reg_rdata_next[15] = cmd_filter_2_filter_79_qs;
        reg_rdata_next[16] = cmd_filter_2_filter_80_qs;
        reg_rdata_next[17] = cmd_filter_2_filter_81_qs;
        reg_rdata_next[18] = cmd_filter_2_filter_82_qs;
        reg_rdata_next[19] = cmd_filter_2_filter_83_qs;
        reg_rdata_next[20] = cmd_filter_2_filter_84_qs;
        reg_rdata_next[21] = cmd_filter_2_filter_85_qs;
        reg_rdata_next[22] = cmd_filter_2_filter_86_qs;
        reg_rdata_next[23] = cmd_filter_2_filter_87_qs;
        reg_rdata_next[24] = cmd_filter_2_filter_88_qs;
        reg_rdata_next[25] = cmd_filter_2_filter_89_qs;
        reg_rdata_next[26] = cmd_filter_2_filter_90_qs;
        reg_rdata_next[27] = cmd_filter_2_filter_91_qs;
        reg_rdata_next[28] = cmd_filter_2_filter_92_qs;
        reg_rdata_next[29] = cmd_filter_2_filter_93_qs;
        reg_rdata_next[30] = cmd_filter_2_filter_94_qs;
        reg_rdata_next[31] = cmd_filter_2_filter_95_qs;
      end

      racl_addr_hit_read[22]: begin
        reg_rdata_next[0] = cmd_filter_3_filter_96_qs;
        reg_rdata_next[1] = cmd_filter_3_filter_97_qs;
        reg_rdata_next[2] = cmd_filter_3_filter_98_qs;
        reg_rdata_next[3] = cmd_filter_3_filter_99_qs;
        reg_rdata_next[4] = cmd_filter_3_filter_100_qs;
        reg_rdata_next[5] = cmd_filter_3_filter_101_qs;
        reg_rdata_next[6] = cmd_filter_3_filter_102_qs;
        reg_rdata_next[7] = cmd_filter_3_filter_103_qs;
        reg_rdata_next[8] = cmd_filter_3_filter_104_qs;
        reg_rdata_next[9] = cmd_filter_3_filter_105_qs;
        reg_rdata_next[10] = cmd_filter_3_filter_106_qs;
        reg_rdata_next[11] = cmd_filter_3_filter_107_qs;
        reg_rdata_next[12] = cmd_filter_3_filter_108_qs;
        reg_rdata_next[13] = cmd_filter_3_filter_109_qs;
        reg_rdata_next[14] = cmd_filter_3_filter_110_qs;
        reg_rdata_next[15] = cmd_filter_3_filter_111_qs;
        reg_rdata_next[16] = cmd_filter_3_filter_112_qs;
        reg_rdata_next[17] = cmd_filter_3_filter_113_qs;
        reg_rdata_next[18] = cmd_filter_3_filter_114_qs;
        reg_rdata_next[19] = cmd_filter_3_filter_115_qs;
        reg_rdata_next[20] = cmd_filter_3_filter_116_qs;
        reg_rdata_next[21] = cmd_filter_3_filter_117_qs;
        reg_rdata_next[22] = cmd_filter_3_filter_118_qs;
        reg_rdata_next[23] = cmd_filter_3_filter_119_qs;
        reg_rdata_next[24] = cmd_filter_3_filter_120_qs;
        reg_rdata_next[25] = cmd_filter_3_filter_121_qs;
        reg_rdata_next[26] = cmd_filter_3_filter_122_qs;
        reg_rdata_next[27] = cmd_filter_3_filter_123_qs;
        reg_rdata_next[28] = cmd_filter_3_filter_124_qs;
        reg_rdata_next[29] = cmd_filter_3_filter_125_qs;
        reg_rdata_next[30] = cmd_filter_3_filter_126_qs;
        reg_rdata_next[31] = cmd_filter_3_filter_127_qs;
      end

      racl_addr_hit_read[23]: begin
        reg_rdata_next[0] = cmd_filter_4_filter_128_qs;
        reg_rdata_next[1] = cmd_filter_4_filter_129_qs;
        reg_rdata_next[2] = cmd_filter_4_filter_130_qs;
        reg_rdata_next[3] = cmd_filter_4_filter_131_qs;
        reg_rdata_next[4] = cmd_filter_4_filter_132_qs;
        reg_rdata_next[5] = cmd_filter_4_filter_133_qs;
        reg_rdata_next[6] = cmd_filter_4_filter_134_qs;
        reg_rdata_next[7] = cmd_filter_4_filter_135_qs;
        reg_rdata_next[8] = cmd_filter_4_filter_136_qs;
        reg_rdata_next[9] = cmd_filter_4_filter_137_qs;
        reg_rdata_next[10] = cmd_filter_4_filter_138_qs;
        reg_rdata_next[11] = cmd_filter_4_filter_139_qs;
        reg_rdata_next[12] = cmd_filter_4_filter_140_qs;
        reg_rdata_next[13] = cmd_filter_4_filter_141_qs;
        reg_rdata_next[14] = cmd_filter_4_filter_142_qs;
        reg_rdata_next[15] = cmd_filter_4_filter_143_qs;
        reg_rdata_next[16] = cmd_filter_4_filter_144_qs;
        reg_rdata_next[17] = cmd_filter_4_filter_145_qs;
        reg_rdata_next[18] = cmd_filter_4_filter_146_qs;
        reg_rdata_next[19] = cmd_filter_4_filter_147_qs;
        reg_rdata_next[20] = cmd_filter_4_filter_148_qs;
        reg_rdata_next[21] = cmd_filter_4_filter_149_qs;
        reg_rdata_next[22] = cmd_filter_4_filter_150_qs;
        reg_rdata_next[23] = cmd_filter_4_filter_151_qs;
        reg_rdata_next[24] = cmd_filter_4_filter_152_qs;
        reg_rdata_next[25] = cmd_filter_4_filter_153_qs;
        reg_rdata_next[26] = cmd_filter_4_filter_154_qs;
        reg_rdata_next[27] = cmd_filter_4_filter_155_qs;
        reg_rdata_next[28] = cmd_filter_4_filter_156_qs;
        reg_rdata_next[29] = cmd_filter_4_filter_157_qs;
        reg_rdata_next[30] = cmd_filter_4_filter_158_qs;
        reg_rdata_next[31] = cmd_filter_4_filter_159_qs;
      end

      racl_addr_hit_read[24]: begin
        reg_rdata_next[0] = cmd_filter_5_filter_160_qs;
        reg_rdata_next[1] = cmd_filter_5_filter_161_qs;
        reg_rdata_next[2] = cmd_filter_5_filter_162_qs;
        reg_rdata_next[3] = cmd_filter_5_filter_163_qs;
        reg_rdata_next[4] = cmd_filter_5_filter_164_qs;
        reg_rdata_next[5] = cmd_filter_5_filter_165_qs;
        reg_rdata_next[6] = cmd_filter_5_filter_166_qs;
        reg_rdata_next[7] = cmd_filter_5_filter_167_qs;
        reg_rdata_next[8] = cmd_filter_5_filter_168_qs;
        reg_rdata_next[9] = cmd_filter_5_filter_169_qs;
        reg_rdata_next[10] = cmd_filter_5_filter_170_qs;
        reg_rdata_next[11] = cmd_filter_5_filter_171_qs;
        reg_rdata_next[12] = cmd_filter_5_filter_172_qs;
        reg_rdata_next[13] = cmd_filter_5_filter_173_qs;
        reg_rdata_next[14] = cmd_filter_5_filter_174_qs;
        reg_rdata_next[15] = cmd_filter_5_filter_175_qs;
        reg_rdata_next[16] = cmd_filter_5_filter_176_qs;
        reg_rdata_next[17] = cmd_filter_5_filter_177_qs;
        reg_rdata_next[18] = cmd_filter_5_filter_178_qs;
        reg_rdata_next[19] = cmd_filter_5_filter_179_qs;
        reg_rdata_next[20] = cmd_filter_5_filter_180_qs;
        reg_rdata_next[21] = cmd_filter_5_filter_181_qs;
        reg_rdata_next[22] = cmd_filter_5_filter_182_qs;
        reg_rdata_next[23] = cmd_filter_5_filter_183_qs;
        reg_rdata_next[24] = cmd_filter_5_filter_184_qs;
        reg_rdata_next[25] = cmd_filter_5_filter_185_qs;
        reg_rdata_next[26] = cmd_filter_5_filter_186_qs;
        reg_rdata_next[27] = cmd_filter_5_filter_187_qs;
        reg_rdata_next[28] = cmd_filter_5_filter_188_qs;
        reg_rdata_next[29] = cmd_filter_5_filter_189_qs;
        reg_rdata_next[30] = cmd_filter_5_filter_190_qs;
        reg_rdata_next[31] = cmd_filter_5_filter_191_qs;
      end

      racl_addr_hit_read[25]: begin
        reg_rdata_next[0] = cmd_filter_6_filter_192_qs;
        reg_rdata_next[1] = cmd_filter_6_filter_193_qs;
        reg_rdata_next[2] = cmd_filter_6_filter_194_qs;
        reg_rdata_next[3] = cmd_filter_6_filter_195_qs;
        reg_rdata_next[4] = cmd_filter_6_filter_196_qs;
        reg_rdata_next[5] = cmd_filter_6_filter_197_qs;
        reg_rdata_next[6] = cmd_filter_6_filter_198_qs;
        reg_rdata_next[7] = cmd_filter_6_filter_199_qs;
        reg_rdata_next[8] = cmd_filter_6_filter_200_qs;
        reg_rdata_next[9] = cmd_filter_6_filter_201_qs;
        reg_rdata_next[10] = cmd_filter_6_filter_202_qs;
        reg_rdata_next[11] = cmd_filter_6_filter_203_qs;
        reg_rdata_next[12] = cmd_filter_6_filter_204_qs;
        reg_rdata_next[13] = cmd_filter_6_filter_205_qs;
        reg_rdata_next[14] = cmd_filter_6_filter_206_qs;
        reg_rdata_next[15] = cmd_filter_6_filter_207_qs;
        reg_rdata_next[16] = cmd_filter_6_filter_208_qs;
        reg_rdata_next[17] = cmd_filter_6_filter_209_qs;
        reg_rdata_next[18] = cmd_filter_6_filter_210_qs;
        reg_rdata_next[19] = cmd_filter_6_filter_211_qs;
        reg_rdata_next[20] = cmd_filter_6_filter_212_qs;
        reg_rdata_next[21] = cmd_filter_6_filter_213_qs;
        reg_rdata_next[22] = cmd_filter_6_filter_214_qs;
        reg_rdata_next[23] = cmd_filter_6_filter_215_qs;
        reg_rdata_next[24] = cmd_filter_6_filter_216_qs;
        reg_rdata_next[25] = cmd_filter_6_filter_217_qs;
        reg_rdata_next[26] = cmd_filter_6_filter_218_qs;
        reg_rdata_next[27] = cmd_filter_6_filter_219_qs;
        reg_rdata_next[28] = cmd_filter_6_filter_220_qs;
        reg_rdata_next[29] = cmd_filter_6_filter_221_qs;
        reg_rdata_next[30] = cmd_filter_6_filter_222_qs;
        reg_rdata_next[31] = cmd_filter_6_filter_223_qs;
      end

      racl_addr_hit_read[26]: begin
        reg_rdata_next[0] = cmd_filter_7_filter_224_qs;
        reg_rdata_next[1] = cmd_filter_7_filter_225_qs;
        reg_rdata_next[2] = cmd_filter_7_filter_226_qs;
        reg_rdata_next[3] = cmd_filter_7_filter_227_qs;
        reg_rdata_next[4] = cmd_filter_7_filter_228_qs;
        reg_rdata_next[5] = cmd_filter_7_filter_229_qs;
        reg_rdata_next[6] = cmd_filter_7_filter_230_qs;
        reg_rdata_next[7] = cmd_filter_7_filter_231_qs;
        reg_rdata_next[8] = cmd_filter_7_filter_232_qs;
        reg_rdata_next[9] = cmd_filter_7_filter_233_qs;
        reg_rdata_next[10] = cmd_filter_7_filter_234_qs;
        reg_rdata_next[11] = cmd_filter_7_filter_235_qs;
        reg_rdata_next[12] = cmd_filter_7_filter_236_qs;
        reg_rdata_next[13] = cmd_filter_7_filter_237_qs;
        reg_rdata_next[14] = cmd_filter_7_filter_238_qs;
        reg_rdata_next[15] = cmd_filter_7_filter_239_qs;
        reg_rdata_next[16] = cmd_filter_7_filter_240_qs;
        reg_rdata_next[17] = cmd_filter_7_filter_241_qs;
        reg_rdata_next[18] = cmd_filter_7_filter_242_qs;
        reg_rdata_next[19] = cmd_filter_7_filter_243_qs;
        reg_rdata_next[20] = cmd_filter_7_filter_244_qs;
        reg_rdata_next[21] = cmd_filter_7_filter_245_qs;
        reg_rdata_next[22] = cmd_filter_7_filter_246_qs;
        reg_rdata_next[23] = cmd_filter_7_filter_247_qs;
        reg_rdata_next[24] = cmd_filter_7_filter_248_qs;
        reg_rdata_next[25] = cmd_filter_7_filter_249_qs;
        reg_rdata_next[26] = cmd_filter_7_filter_250_qs;
        reg_rdata_next[27] = cmd_filter_7_filter_251_qs;
        reg_rdata_next[28] = cmd_filter_7_filter_252_qs;
        reg_rdata_next[29] = cmd_filter_7_filter_253_qs;
        reg_rdata_next[30] = cmd_filter_7_filter_254_qs;
        reg_rdata_next[31] = cmd_filter_7_filter_255_qs;
      end

      racl_addr_hit_read[27]: begin
        reg_rdata_next[31:0] = addr_swap_mask_qs;
      end

      racl_addr_hit_read[28]: begin
        reg_rdata_next[31:0] = addr_swap_data_qs;
      end

      racl_addr_hit_read[29]: begin
        reg_rdata_next[31:0] = payload_swap_mask_qs;
      end

      racl_addr_hit_read[30]: begin
        reg_rdata_next[31:0] = payload_swap_data_qs;
      end

      racl_addr_hit_read[31]: begin
        reg_rdata_next[7:0] = cmd_info_0_opcode_0_qs;
        reg_rdata_next[9:8] = cmd_info_0_addr_mode_0_qs;
        reg_rdata_next[10] = cmd_info_0_addr_swap_en_0_qs;
        reg_rdata_next[11] = cmd_info_0_mbyte_en_0_qs;
        reg_rdata_next[14:12] = cmd_info_0_dummy_size_0_qs;
        reg_rdata_next[15] = cmd_info_0_dummy_en_0_qs;
        reg_rdata_next[19:16] = cmd_info_0_payload_en_0_qs;
        reg_rdata_next[20] = cmd_info_0_payload_dir_0_qs;
        reg_rdata_next[21] = cmd_info_0_payload_swap_en_0_qs;
        reg_rdata_next[23:22] = cmd_info_0_read_pipeline_mode_0_qs;
        reg_rdata_next[24] = cmd_info_0_upload_0_qs;
        reg_rdata_next[25] = cmd_info_0_busy_0_qs;
        reg_rdata_next[31] = cmd_info_0_valid_0_qs;
      end

      racl_addr_hit_read[32]: begin
        reg_rdata_next[7:0] = cmd_info_1_opcode_1_qs;
        reg_rdata_next[9:8] = cmd_info_1_addr_mode_1_qs;
        reg_rdata_next[10] = cmd_info_1_addr_swap_en_1_qs;
        reg_rdata_next[11] = cmd_info_1_mbyte_en_1_qs;
        reg_rdata_next[14:12] = cmd_info_1_dummy_size_1_qs;
        reg_rdata_next[15] = cmd_info_1_dummy_en_1_qs;
        reg_rdata_next[19:16] = cmd_info_1_payload_en_1_qs;
        reg_rdata_next[20] = cmd_info_1_payload_dir_1_qs;
        reg_rdata_next[21] = cmd_info_1_payload_swap_en_1_qs;
        reg_rdata_next[23:22] = cmd_info_1_read_pipeline_mode_1_qs;
        reg_rdata_next[24] = cmd_info_1_upload_1_qs;
        reg_rdata_next[25] = cmd_info_1_busy_1_qs;
        reg_rdata_next[31] = cmd_info_1_valid_1_qs;
      end

      racl_addr_hit_read[33]: begin
        reg_rdata_next[7:0] = cmd_info_2_opcode_2_qs;
        reg_rdata_next[9:8] = cmd_info_2_addr_mode_2_qs;
        reg_rdata_next[10] = cmd_info_2_addr_swap_en_2_qs;
        reg_rdata_next[11] = cmd_info_2_mbyte_en_2_qs;
        reg_rdata_next[14:12] = cmd_info_2_dummy_size_2_qs;
        reg_rdata_next[15] = cmd_info_2_dummy_en_2_qs;
        reg_rdata_next[19:16] = cmd_info_2_payload_en_2_qs;
        reg_rdata_next[20] = cmd_info_2_payload_dir_2_qs;
        reg_rdata_next[21] = cmd_info_2_payload_swap_en_2_qs;
        reg_rdata_next[23:22] = cmd_info_2_read_pipeline_mode_2_qs;
        reg_rdata_next[24] = cmd_info_2_upload_2_qs;
        reg_rdata_next[25] = cmd_info_2_busy_2_qs;
        reg_rdata_next[31] = cmd_info_2_valid_2_qs;
      end

      racl_addr_hit_read[34]: begin
        reg_rdata_next[7:0] = cmd_info_3_opcode_3_qs;
        reg_rdata_next[9:8] = cmd_info_3_addr_mode_3_qs;
        reg_rdata_next[10] = cmd_info_3_addr_swap_en_3_qs;
        reg_rdata_next[11] = cmd_info_3_mbyte_en_3_qs;
        reg_rdata_next[14:12] = cmd_info_3_dummy_size_3_qs;
        reg_rdata_next[15] = cmd_info_3_dummy_en_3_qs;
        reg_rdata_next[19:16] = cmd_info_3_payload_en_3_qs;
        reg_rdata_next[20] = cmd_info_3_payload_dir_3_qs;
        reg_rdata_next[21] = cmd_info_3_payload_swap_en_3_qs;
        reg_rdata_next[23:22] = cmd_info_3_read_pipeline_mode_3_qs;
        reg_rdata_next[24] = cmd_info_3_upload_3_qs;
        reg_rdata_next[25] = cmd_info_3_busy_3_qs;
        reg_rdata_next[31] = cmd_info_3_valid_3_qs;
      end

      racl_addr_hit_read[35]: begin
        reg_rdata_next[7:0] = cmd_info_4_opcode_4_qs;
        reg_rdata_next[9:8] = cmd_info_4_addr_mode_4_qs;
        reg_rdata_next[10] = cmd_info_4_addr_swap_en_4_qs;
        reg_rdata_next[11] = cmd_info_4_mbyte_en_4_qs;
        reg_rdata_next[14:12] = cmd_info_4_dummy_size_4_qs;
        reg_rdata_next[15] = cmd_info_4_dummy_en_4_qs;
        reg_rdata_next[19:16] = cmd_info_4_payload_en_4_qs;
        reg_rdata_next[20] = cmd_info_4_payload_dir_4_qs;
        reg_rdata_next[21] = cmd_info_4_payload_swap_en_4_qs;
        reg_rdata_next[23:22] = cmd_info_4_read_pipeline_mode_4_qs;
        reg_rdata_next[24] = cmd_info_4_upload_4_qs;
        reg_rdata_next[25] = cmd_info_4_busy_4_qs;
        reg_rdata_next[31] = cmd_info_4_valid_4_qs;
      end

      racl_addr_hit_read[36]: begin
        reg_rdata_next[7:0] = cmd_info_5_opcode_5_qs;
        reg_rdata_next[9:8] = cmd_info_5_addr_mode_5_qs;
        reg_rdata_next[10] = cmd_info_5_addr_swap_en_5_qs;
        reg_rdata_next[11] = cmd_info_5_mbyte_en_5_qs;
        reg_rdata_next[14:12] = cmd_info_5_dummy_size_5_qs;
        reg_rdata_next[15] = cmd_info_5_dummy_en_5_qs;
        reg_rdata_next[19:16] = cmd_info_5_payload_en_5_qs;
        reg_rdata_next[20] = cmd_info_5_payload_dir_5_qs;
        reg_rdata_next[21] = cmd_info_5_payload_swap_en_5_qs;
        reg_rdata_next[23:22] = cmd_info_5_read_pipeline_mode_5_qs;
        reg_rdata_next[24] = cmd_info_5_upload_5_qs;
        reg_rdata_next[25] = cmd_info_5_busy_5_qs;
        reg_rdata_next[31] = cmd_info_5_valid_5_qs;
      end

      racl_addr_hit_read[37]: begin
        reg_rdata_next[7:0] = cmd_info_6_opcode_6_qs;
        reg_rdata_next[9:8] = cmd_info_6_addr_mode_6_qs;
        reg_rdata_next[10] = cmd_info_6_addr_swap_en_6_qs;
        reg_rdata_next[11] = cmd_info_6_mbyte_en_6_qs;
        reg_rdata_next[14:12] = cmd_info_6_dummy_size_6_qs;
        reg_rdata_next[15] = cmd_info_6_dummy_en_6_qs;
        reg_rdata_next[19:16] = cmd_info_6_payload_en_6_qs;
        reg_rdata_next[20] = cmd_info_6_payload_dir_6_qs;
        reg_rdata_next[21] = cmd_info_6_payload_swap_en_6_qs;
        reg_rdata_next[23:22] = cmd_info_6_read_pipeline_mode_6_qs;
        reg_rdata_next[24] = cmd_info_6_upload_6_qs;
        reg_rdata_next[25] = cmd_info_6_busy_6_qs;
        reg_rdata_next[31] = cmd_info_6_valid_6_qs;
      end

      racl_addr_hit_read[38]: begin
        reg_rdata_next[7:0] = cmd_info_7_opcode_7_qs;
        reg_rdata_next[9:8] = cmd_info_7_addr_mode_7_qs;
        reg_rdata_next[10] = cmd_info_7_addr_swap_en_7_qs;
        reg_rdata_next[11] = cmd_info_7_mbyte_en_7_qs;
        reg_rdata_next[14:12] = cmd_info_7_dummy_size_7_qs;
        reg_rdata_next[15] = cmd_info_7_dummy_en_7_qs;
        reg_rdata_next[19:16] = cmd_info_7_payload_en_7_qs;
        reg_rdata_next[20] = cmd_info_7_payload_dir_7_qs;
        reg_rdata_next[21] = cmd_info_7_payload_swap_en_7_qs;
        reg_rdata_next[23:22] = cmd_info_7_read_pipeline_mode_7_qs;
        reg_rdata_next[24] = cmd_info_7_upload_7_qs;
        reg_rdata_next[25] = cmd_info_7_busy_7_qs;
        reg_rdata_next[31] = cmd_info_7_valid_7_qs;
      end

      racl_addr_hit_read[39]: begin
        reg_rdata_next[7:0] = cmd_info_8_opcode_8_qs;
        reg_rdata_next[9:8] = cmd_info_8_addr_mode_8_qs;
        reg_rdata_next[10] = cmd_info_8_addr_swap_en_8_qs;
        reg_rdata_next[11] = cmd_info_8_mbyte_en_8_qs;
        reg_rdata_next[14:12] = cmd_info_8_dummy_size_8_qs;
        reg_rdata_next[15] = cmd_info_8_dummy_en_8_qs;
        reg_rdata_next[19:16] = cmd_info_8_payload_en_8_qs;
        reg_rdata_next[20] = cmd_info_8_payload_dir_8_qs;
        reg_rdata_next[21] = cmd_info_8_payload_swap_en_8_qs;
        reg_rdata_next[23:22] = cmd_info_8_read_pipeline_mode_8_qs;
        reg_rdata_next[24] = cmd_info_8_upload_8_qs;
        reg_rdata_next[25] = cmd_info_8_busy_8_qs;
        reg_rdata_next[31] = cmd_info_8_valid_8_qs;
      end

      racl_addr_hit_read[40]: begin
        reg_rdata_next[7:0] = cmd_info_9_opcode_9_qs;
        reg_rdata_next[9:8] = cmd_info_9_addr_mode_9_qs;
        reg_rdata_next[10] = cmd_info_9_addr_swap_en_9_qs;
        reg_rdata_next[11] = cmd_info_9_mbyte_en_9_qs;
        reg_rdata_next[14:12] = cmd_info_9_dummy_size_9_qs;
        reg_rdata_next[15] = cmd_info_9_dummy_en_9_qs;
        reg_rdata_next[19:16] = cmd_info_9_payload_en_9_qs;
        reg_rdata_next[20] = cmd_info_9_payload_dir_9_qs;
        reg_rdata_next[21] = cmd_info_9_payload_swap_en_9_qs;
        reg_rdata_next[23:22] = cmd_info_9_read_pipeline_mode_9_qs;
        reg_rdata_next[24] = cmd_info_9_upload_9_qs;
        reg_rdata_next[25] = cmd_info_9_busy_9_qs;
        reg_rdata_next[31] = cmd_info_9_valid_9_qs;
      end

      racl_addr_hit_read[41]: begin
        reg_rdata_next[7:0] = cmd_info_10_opcode_10_qs;
        reg_rdata_next[9:8] = cmd_info_10_addr_mode_10_qs;
        reg_rdata_next[10] = cmd_info_10_addr_swap_en_10_qs;
        reg_rdata_next[11] = cmd_info_10_mbyte_en_10_qs;
        reg_rdata_next[14:12] = cmd_info_10_dummy_size_10_qs;
        reg_rdata_next[15] = cmd_info_10_dummy_en_10_qs;
        reg_rdata_next[19:16] = cmd_info_10_payload_en_10_qs;
        reg_rdata_next[20] = cmd_info_10_payload_dir_10_qs;
        reg_rdata_next[21] = cmd_info_10_payload_swap_en_10_qs;
        reg_rdata_next[23:22] = cmd_info_10_read_pipeline_mode_10_qs;
        reg_rdata_next[24] = cmd_info_10_upload_10_qs;
        reg_rdata_next[25] = cmd_info_10_busy_10_qs;
        reg_rdata_next[31] = cmd_info_10_valid_10_qs;
      end

      racl_addr_hit_read[42]: begin
        reg_rdata_next[7:0] = cmd_info_11_opcode_11_qs;
        reg_rdata_next[9:8] = cmd_info_11_addr_mode_11_qs;
        reg_rdata_next[10] = cmd_info_11_addr_swap_en_11_qs;
        reg_rdata_next[11] = cmd_info_11_mbyte_en_11_qs;
        reg_rdata_next[14:12] = cmd_info_11_dummy_size_11_qs;
        reg_rdata_next[15] = cmd_info_11_dummy_en_11_qs;
        reg_rdata_next[19:16] = cmd_info_11_payload_en_11_qs;
        reg_rdata_next[20] = cmd_info_11_payload_dir_11_qs;
        reg_rdata_next[21] = cmd_info_11_payload_swap_en_11_qs;
        reg_rdata_next[23:22] = cmd_info_11_read_pipeline_mode_11_qs;
        reg_rdata_next[24] = cmd_info_11_upload_11_qs;
        reg_rdata_next[25] = cmd_info_11_busy_11_qs;
        reg_rdata_next[31] = cmd_info_11_valid_11_qs;
      end

      racl_addr_hit_read[43]: begin
        reg_rdata_next[7:0] = cmd_info_12_opcode_12_qs;
        reg_rdata_next[9:8] = cmd_info_12_addr_mode_12_qs;
        reg_rdata_next[10] = cmd_info_12_addr_swap_en_12_qs;
        reg_rdata_next[11] = cmd_info_12_mbyte_en_12_qs;
        reg_rdata_next[14:12] = cmd_info_12_dummy_size_12_qs;
        reg_rdata_next[15] = cmd_info_12_dummy_en_12_qs;
        reg_rdata_next[19:16] = cmd_info_12_payload_en_12_qs;
        reg_rdata_next[20] = cmd_info_12_payload_dir_12_qs;
        reg_rdata_next[21] = cmd_info_12_payload_swap_en_12_qs;
        reg_rdata_next[23:22] = cmd_info_12_read_pipeline_mode_12_qs;
        reg_rdata_next[24] = cmd_info_12_upload_12_qs;
        reg_rdata_next[25] = cmd_info_12_busy_12_qs;
        reg_rdata_next[31] = cmd_info_12_valid_12_qs;
      end

      racl_addr_hit_read[44]: begin
        reg_rdata_next[7:0] = cmd_info_13_opcode_13_qs;
        reg_rdata_next[9:8] = cmd_info_13_addr_mode_13_qs;
        reg_rdata_next[10] = cmd_info_13_addr_swap_en_13_qs;
        reg_rdata_next[11] = cmd_info_13_mbyte_en_13_qs;
        reg_rdata_next[14:12] = cmd_info_13_dummy_size_13_qs;
        reg_rdata_next[15] = cmd_info_13_dummy_en_13_qs;
        reg_rdata_next[19:16] = cmd_info_13_payload_en_13_qs;
        reg_rdata_next[20] = cmd_info_13_payload_dir_13_qs;
        reg_rdata_next[21] = cmd_info_13_payload_swap_en_13_qs;
        reg_rdata_next[23:22] = cmd_info_13_read_pipeline_mode_13_qs;
        reg_rdata_next[24] = cmd_info_13_upload_13_qs;
        reg_rdata_next[25] = cmd_info_13_busy_13_qs;
        reg_rdata_next[31] = cmd_info_13_valid_13_qs;
      end

      racl_addr_hit_read[45]: begin
        reg_rdata_next[7:0] = cmd_info_14_opcode_14_qs;
        reg_rdata_next[9:8] = cmd_info_14_addr_mode_14_qs;
        reg_rdata_next[10] = cmd_info_14_addr_swap_en_14_qs;
        reg_rdata_next[11] = cmd_info_14_mbyte_en_14_qs;
        reg_rdata_next[14:12] = cmd_info_14_dummy_size_14_qs;
        reg_rdata_next[15] = cmd_info_14_dummy_en_14_qs;
        reg_rdata_next[19:16] = cmd_info_14_payload_en_14_qs;
        reg_rdata_next[20] = cmd_info_14_payload_dir_14_qs;
        reg_rdata_next[21] = cmd_info_14_payload_swap_en_14_qs;
        reg_rdata_next[23:22] = cmd_info_14_read_pipeline_mode_14_qs;
        reg_rdata_next[24] = cmd_info_14_upload_14_qs;
        reg_rdata_next[25] = cmd_info_14_busy_14_qs;
        reg_rdata_next[31] = cmd_info_14_valid_14_qs;
      end

      racl_addr_hit_read[46]: begin
        reg_rdata_next[7:0] = cmd_info_15_opcode_15_qs;
        reg_rdata_next[9:8] = cmd_info_15_addr_mode_15_qs;
        reg_rdata_next[10] = cmd_info_15_addr_swap_en_15_qs;
        reg_rdata_next[11] = cmd_info_15_mbyte_en_15_qs;
        reg_rdata_next[14:12] = cmd_info_15_dummy_size_15_qs;
        reg_rdata_next[15] = cmd_info_15_dummy_en_15_qs;
        reg_rdata_next[19:16] = cmd_info_15_payload_en_15_qs;
        reg_rdata_next[20] = cmd_info_15_payload_dir_15_qs;
        reg_rdata_next[21] = cmd_info_15_payload_swap_en_15_qs;
        reg_rdata_next[23:22] = cmd_info_15_read_pipeline_mode_15_qs;
        reg_rdata_next[24] = cmd_info_15_upload_15_qs;
        reg_rdata_next[25] = cmd_info_15_busy_15_qs;
        reg_rdata_next[31] = cmd_info_15_valid_15_qs;
      end

      racl_addr_hit_read[47]: begin
        reg_rdata_next[7:0] = cmd_info_16_opcode_16_qs;
        reg_rdata_next[9:8] = cmd_info_16_addr_mode_16_qs;
        reg_rdata_next[10] = cmd_info_16_addr_swap_en_16_qs;
        reg_rdata_next[11] = cmd_info_16_mbyte_en_16_qs;
        reg_rdata_next[14:12] = cmd_info_16_dummy_size_16_qs;
        reg_rdata_next[15] = cmd_info_16_dummy_en_16_qs;
        reg_rdata_next[19:16] = cmd_info_16_payload_en_16_qs;
        reg_rdata_next[20] = cmd_info_16_payload_dir_16_qs;
        reg_rdata_next[21] = cmd_info_16_payload_swap_en_16_qs;
        reg_rdata_next[23:22] = cmd_info_16_read_pipeline_mode_16_qs;
        reg_rdata_next[24] = cmd_info_16_upload_16_qs;
        reg_rdata_next[25] = cmd_info_16_busy_16_qs;
        reg_rdata_next[31] = cmd_info_16_valid_16_qs;
      end

      racl_addr_hit_read[48]: begin
        reg_rdata_next[7:0] = cmd_info_17_opcode_17_qs;
        reg_rdata_next[9:8] = cmd_info_17_addr_mode_17_qs;
        reg_rdata_next[10] = cmd_info_17_addr_swap_en_17_qs;
        reg_rdata_next[11] = cmd_info_17_mbyte_en_17_qs;
        reg_rdata_next[14:12] = cmd_info_17_dummy_size_17_qs;
        reg_rdata_next[15] = cmd_info_17_dummy_en_17_qs;
        reg_rdata_next[19:16] = cmd_info_17_payload_en_17_qs;
        reg_rdata_next[20] = cmd_info_17_payload_dir_17_qs;
        reg_rdata_next[21] = cmd_info_17_payload_swap_en_17_qs;
        reg_rdata_next[23:22] = cmd_info_17_read_pipeline_mode_17_qs;
        reg_rdata_next[24] = cmd_info_17_upload_17_qs;
        reg_rdata_next[25] = cmd_info_17_busy_17_qs;
        reg_rdata_next[31] = cmd_info_17_valid_17_qs;
      end

      racl_addr_hit_read[49]: begin
        reg_rdata_next[7:0] = cmd_info_18_opcode_18_qs;
        reg_rdata_next[9:8] = cmd_info_18_addr_mode_18_qs;
        reg_rdata_next[10] = cmd_info_18_addr_swap_en_18_qs;
        reg_rdata_next[11] = cmd_info_18_mbyte_en_18_qs;
        reg_rdata_next[14:12] = cmd_info_18_dummy_size_18_qs;
        reg_rdata_next[15] = cmd_info_18_dummy_en_18_qs;
        reg_rdata_next[19:16] = cmd_info_18_payload_en_18_qs;
        reg_rdata_next[20] = cmd_info_18_payload_dir_18_qs;
        reg_rdata_next[21] = cmd_info_18_payload_swap_en_18_qs;
        reg_rdata_next[23:22] = cmd_info_18_read_pipeline_mode_18_qs;
        reg_rdata_next[24] = cmd_info_18_upload_18_qs;
        reg_rdata_next[25] = cmd_info_18_busy_18_qs;
        reg_rdata_next[31] = cmd_info_18_valid_18_qs;
      end

      racl_addr_hit_read[50]: begin
        reg_rdata_next[7:0] = cmd_info_19_opcode_19_qs;
        reg_rdata_next[9:8] = cmd_info_19_addr_mode_19_qs;
        reg_rdata_next[10] = cmd_info_19_addr_swap_en_19_qs;
        reg_rdata_next[11] = cmd_info_19_mbyte_en_19_qs;
        reg_rdata_next[14:12] = cmd_info_19_dummy_size_19_qs;
        reg_rdata_next[15] = cmd_info_19_dummy_en_19_qs;
        reg_rdata_next[19:16] = cmd_info_19_payload_en_19_qs;
        reg_rdata_next[20] = cmd_info_19_payload_dir_19_qs;
        reg_rdata_next[21] = cmd_info_19_payload_swap_en_19_qs;
        reg_rdata_next[23:22] = cmd_info_19_read_pipeline_mode_19_qs;
        reg_rdata_next[24] = cmd_info_19_upload_19_qs;
        reg_rdata_next[25] = cmd_info_19_busy_19_qs;
        reg_rdata_next[31] = cmd_info_19_valid_19_qs;
      end

      racl_addr_hit_read[51]: begin
        reg_rdata_next[7:0] = cmd_info_20_opcode_20_qs;
        reg_rdata_next[9:8] = cmd_info_20_addr_mode_20_qs;
        reg_rdata_next[10] = cmd_info_20_addr_swap_en_20_qs;
        reg_rdata_next[11] = cmd_info_20_mbyte_en_20_qs;
        reg_rdata_next[14:12] = cmd_info_20_dummy_size_20_qs;
        reg_rdata_next[15] = cmd_info_20_dummy_en_20_qs;
        reg_rdata_next[19:16] = cmd_info_20_payload_en_20_qs;
        reg_rdata_next[20] = cmd_info_20_payload_dir_20_qs;
        reg_rdata_next[21] = cmd_info_20_payload_swap_en_20_qs;
        reg_rdata_next[23:22] = cmd_info_20_read_pipeline_mode_20_qs;
        reg_rdata_next[24] = cmd_info_20_upload_20_qs;
        reg_rdata_next[25] = cmd_info_20_busy_20_qs;
        reg_rdata_next[31] = cmd_info_20_valid_20_qs;
      end

      racl_addr_hit_read[52]: begin
        reg_rdata_next[7:0] = cmd_info_21_opcode_21_qs;
        reg_rdata_next[9:8] = cmd_info_21_addr_mode_21_qs;
        reg_rdata_next[10] = cmd_info_21_addr_swap_en_21_qs;
        reg_rdata_next[11] = cmd_info_21_mbyte_en_21_qs;
        reg_rdata_next[14:12] = cmd_info_21_dummy_size_21_qs;
        reg_rdata_next[15] = cmd_info_21_dummy_en_21_qs;
        reg_rdata_next[19:16] = cmd_info_21_payload_en_21_qs;
        reg_rdata_next[20] = cmd_info_21_payload_dir_21_qs;
        reg_rdata_next[21] = cmd_info_21_payload_swap_en_21_qs;
        reg_rdata_next[23:22] = cmd_info_21_read_pipeline_mode_21_qs;
        reg_rdata_next[24] = cmd_info_21_upload_21_qs;
        reg_rdata_next[25] = cmd_info_21_busy_21_qs;
        reg_rdata_next[31] = cmd_info_21_valid_21_qs;
      end

      racl_addr_hit_read[53]: begin
        reg_rdata_next[7:0] = cmd_info_22_opcode_22_qs;
        reg_rdata_next[9:8] = cmd_info_22_addr_mode_22_qs;
        reg_rdata_next[10] = cmd_info_22_addr_swap_en_22_qs;
        reg_rdata_next[11] = cmd_info_22_mbyte_en_22_qs;
        reg_rdata_next[14:12] = cmd_info_22_dummy_size_22_qs;
        reg_rdata_next[15] = cmd_info_22_dummy_en_22_qs;
        reg_rdata_next[19:16] = cmd_info_22_payload_en_22_qs;
        reg_rdata_next[20] = cmd_info_22_payload_dir_22_qs;
        reg_rdata_next[21] = cmd_info_22_payload_swap_en_22_qs;
        reg_rdata_next[23:22] = cmd_info_22_read_pipeline_mode_22_qs;
        reg_rdata_next[24] = cmd_info_22_upload_22_qs;
        reg_rdata_next[25] = cmd_info_22_busy_22_qs;
        reg_rdata_next[31] = cmd_info_22_valid_22_qs;
      end

      racl_addr_hit_read[54]: begin
        reg_rdata_next[7:0] = cmd_info_23_opcode_23_qs;
        reg_rdata_next[9:8] = cmd_info_23_addr_mode_23_qs;
        reg_rdata_next[10] = cmd_info_23_addr_swap_en_23_qs;
        reg_rdata_next[11] = cmd_info_23_mbyte_en_23_qs;
        reg_rdata_next[14:12] = cmd_info_23_dummy_size_23_qs;
        reg_rdata_next[15] = cmd_info_23_dummy_en_23_qs;
        reg_rdata_next[19:16] = cmd_info_23_payload_en_23_qs;
        reg_rdata_next[20] = cmd_info_23_payload_dir_23_qs;
        reg_rdata_next[21] = cmd_info_23_payload_swap_en_23_qs;
        reg_rdata_next[23:22] = cmd_info_23_read_pipeline_mode_23_qs;
        reg_rdata_next[24] = cmd_info_23_upload_23_qs;
        reg_rdata_next[25] = cmd_info_23_busy_23_qs;
        reg_rdata_next[31] = cmd_info_23_valid_23_qs;
      end

      racl_addr_hit_read[55]: begin
        reg_rdata_next[7:0] = cmd_info_en4b_opcode_qs;
        reg_rdata_next[31] = cmd_info_en4b_valid_qs;
      end

      racl_addr_hit_read[56]: begin
        reg_rdata_next[7:0] = cmd_info_ex4b_opcode_qs;
        reg_rdata_next[31] = cmd_info_ex4b_valid_qs;
      end

      racl_addr_hit_read[57]: begin
        reg_rdata_next[7:0] = cmd_info_wren_opcode_qs;
        reg_rdata_next[31] = cmd_info_wren_valid_qs;
      end

      racl_addr_hit_read[58]: begin
        reg_rdata_next[7:0] = cmd_info_wrdi_opcode_qs;
        reg_rdata_next[31] = cmd_info_wrdi_valid_qs;
      end

      racl_addr_hit_read[59]: begin
        reg_rdata_next[7:0] = tpm_cap_rev_qs;
        reg_rdata_next[8] = tpm_cap_locality_qs;
        reg_rdata_next[18:16] = tpm_cap_max_wr_size_qs;
        reg_rdata_next[22:20] = tpm_cap_max_rd_size_qs;
      end

      racl_addr_hit_read[60]: begin
        reg_rdata_next[0] = tpm_cfg_en_qs;
        reg_rdata_next[1] = tpm_cfg_tpm_mode_qs;
        reg_rdata_next[2] = tpm_cfg_hw_reg_dis_qs;
        reg_rdata_next[3] = tpm_cfg_tpm_reg_chk_dis_qs;
        reg_rdata_next[4] = tpm_cfg_invalid_locality_qs;
      end

      racl_addr_hit_read[61]: begin
        reg_rdata_next[0] = tpm_status_cmdaddr_notempty_qs;
        reg_rdata_next[1] = tpm_status_wrfifo_pending_qs;
        reg_rdata_next[2] = tpm_status_rdfifo_aborted_qs;
      end

      racl_addr_hit_read[62]: begin
        reg_rdata_next[7:0] = tpm_access_0_access_0_qs;
        reg_rdata_next[15:8] = tpm_access_0_access_1_qs;
        reg_rdata_next[23:16] = tpm_access_0_access_2_qs;
        reg_rdata_next[31:24] = tpm_access_0_access_3_qs;
      end

      racl_addr_hit_read[63]: begin
        reg_rdata_next[7:0] = tpm_access_1_qs;
      end

      racl_addr_hit_read[64]: begin
        reg_rdata_next[31:0] = tpm_sts_qs;
      end

      racl_addr_hit_read[65]: begin
        reg_rdata_next[31:0] = tpm_intf_capability_qs;
      end

      racl_addr_hit_read[66]: begin
        reg_rdata_next[31:0] = tpm_int_enable_qs;
      end

      racl_addr_hit_read[67]: begin
        reg_rdata_next[7:0] = tpm_int_vector_qs;
      end

      racl_addr_hit_read[68]: begin
        reg_rdata_next[31:0] = tpm_int_status_qs;
      end

      racl_addr_hit_read[69]: begin
        reg_rdata_next[15:0] = tpm_did_vid_vid_qs;
        reg_rdata_next[31:16] = tpm_did_vid_did_qs;
      end

      racl_addr_hit_read[70]: begin
        reg_rdata_next[7:0] = tpm_rid_qs;
      end

      racl_addr_hit_read[71]: begin
        reg_rdata_next[23:0] = tpm_cmd_addr_addr_qs;
        reg_rdata_next[31:24] = tpm_cmd_addr_cmd_qs;
      end

      racl_addr_hit_read[72]: begin
        reg_rdata_next[31:0] = '0;
      end

      default: begin
        reg_rdata_next = '1;
      end
    endcase
  end

  // shadow busy
  logic shadow_busy;
  assign shadow_busy = 1'b0;

  // register busy
  assign reg_busy = shadow_busy;

  // Unused signal tieoff

  // wdata / byte enable are not always fully used
  // add a blanket unused statement to handle lint waivers
  logic unused_wdata;
  logic unused_be;
  assign unused_wdata = ^reg_wdata;
  assign unused_be = ^reg_be;
  logic unused_policy_sel;
  assign unused_policy_sel = ^racl_policies_i;

  // Assertions for Register Interface
  `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
  `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)

  `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)

  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)

  // this is formulated as an assumption such that the FPV testbenches do disprove this
  // property by mistake
  //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)

endmodule
