// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `rdl2ot`

`include "prim_assert.sv"

module mbx_soc_reg_top
  # (
    parameter bit          EnableRacl           = 1'b0,
    parameter bit          RaclErrorRsp         = 1'b1,
    parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[mbx_reg_pkg::NumRegsSoc] =
      '{mbx_reg_pkg::NumRegsSoc{0}}
  ) (
  input clk_i,
  input rst_ni,
  input  tlul_pkg::tl_h2d_t tl_i,
  output tlul_pkg::tl_d2h_t tl_o,

  // Output port for window
  output tlul_pkg::tl_h2d_t tl_win_o  [2],
  input  tlul_pkg::tl_d2h_t tl_win_i  [2],
  // To HW
  output mbx_reg_pkg::mbx_soc_reg2hw_t reg2hw, // Write
  input  mbx_reg_pkg::mbx_soc_hw2reg_t hw2reg, // Read

  // RACL interface
  input  top_racl_pkg::racl_policy_vec_t racl_policies_i,
  output top_racl_pkg::racl_error_log_t  racl_error_o,

  // Integrity check errors
  output logic intg_err_o
);

  import mbx_reg_pkg::* ;

  localparam int AW = 5;
  localparam int DW = 32;
  localparam int DBW = DW/8;                    // Byte Width

  // register signals
  logic           reg_we;
  logic           reg_re;
  logic [AW-1:0]  reg_addr;
  logic [DW-1:0]  reg_wdata;
  logic [DBW-1:0] reg_be;
  logic [DW-1:0]  reg_rdata;
  logic           reg_error;

  logic          addrmiss, wr_err;

  logic [DW-1:0] reg_rdata_next;
  logic reg_busy;

  tlul_pkg::tl_h2d_t tl_reg_h2d;
  tlul_pkg::tl_d2h_t tl_reg_d2h;


  // incoming payload check
  logic intg_err;
  tlul_cmd_intg_chk u_chk (
    .tl_i(tl_i),
    .err_o(intg_err)
  );

  // also check for spurious write enables
  logic reg_we_err;
  logic [3:0] reg_we_check;
  prim_reg_we_check #(
    .OneHotWidth(4)
  ) u_prim_reg_we_check (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .oh_i  (reg_we_check),
    .en_i  (reg_we && !addrmiss),
    .err_o (reg_we_err)
  );

  logic err_q;
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      err_q <= '0;
    end else if (intg_err || reg_we_err) begin
      err_q <= 1'b1;
    end
  end

  // integrity error output is permanent and should be used for alert generation
  // register errors are transactional
  assign intg_err_o = err_q | intg_err | reg_we_err;

  // outgoing integrity generation
  tlul_pkg::tl_d2h_t tl_o_pre;
  tlul_rsp_intg_gen #(
    .EnableRspIntgGen(1),
    .EnableDataIntgGen(1)
  ) u_rsp_intg_gen (
    .tl_i(tl_o_pre),
    .tl_o(tl_o)
  );

  tlul_pkg::tl_h2d_t tl_socket_h2d [3];
  tlul_pkg::tl_d2h_t tl_socket_d2h [3];

  logic [1:0] reg_steer;

  // socket_1n connection
  assign tl_reg_h2d = tl_socket_h2d[2];
  assign tl_socket_d2h[2] = tl_reg_d2h;

  assign tl_win_o[0] = tl_socket_h2d[0];
  assign tl_socket_d2h[0] = tl_win_i[0];
  assign tl_win_o[1] = tl_socket_h2d[1];
  assign tl_socket_d2h[1] = tl_win_i[1];

  // Create Socket_1n
  tlul_socket_1n #(
    .N            (3),
    .HReqPass     (1'b1),
    .HRspPass     (1'b1),
    .DReqPass     ({3{1'b1}}),
    .DRspPass     ({3{1'b1}}),
    .HReqDepth    (4'h0),
    .HRspDepth    (4'h0),
    .DReqDepth    ({3{4'h0}}),
    .DRspDepth    ({3{4'h0}}),
    .ExplicitErrs (1'b0)
  ) u_socket (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),
    .tl_h_i (tl_i),
    .tl_h_o (tl_o_pre),
    .tl_d_o (tl_socket_h2d),
    .tl_d_i (tl_socket_d2h),
    .dev_select_i (reg_steer)
  );

  // Create steering logic
  always_comb begin
    reg_steer =
        tl_i.a_address[AW-1:0] inside {[16:19]} ? 2'd0 :
        tl_i.a_address[AW-1:0] inside {[20:23]} ? 2'd1 :
        // Default set to register
        2'd2;

    // Override this in case of an integrity error
    if (intg_err) begin
      reg_steer = 2'd2;
    end
  end

  tlul_adapter_reg #(
    .RegAw(AW),
    .RegDw(DW),
    .EnableDataIntgGen(0)
  ) u_reg_if (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),

    .tl_i (tl_reg_h2d),
    .tl_o (tl_reg_d2h),

    .en_ifetch_i(prim_mubi_pkg::MuBi4False),
    .intg_error_o(),

    .we_o    (reg_we),
    .re_o    (reg_re),
    .addr_o  (reg_addr),
    .wdata_o (reg_wdata),
    .be_o    (reg_be),
    .busy_i  (reg_busy),
    .rdata_i (reg_rdata),
    // Translate RACL error to TLUL error if enabled
    .error_i (reg_error | (RaclErrorRsp & racl_error_o.valid))
  );

  // cdc oversampling signals

  assign reg_rdata = reg_rdata_next ;
  assign reg_error = addrmiss | wr_err | intg_err;

  // Define SW related signals
  // Format: <reg>_<field>_{wd|we|qs}
  //        or <reg>_{wd|we|qs} if field == 1 or 0
  logic soc_control_re;
  logic soc_control_we;
  logic soc_control_abort_wd;
  logic soc_control_doe_intr_en_qs;
  logic soc_control_doe_intr_en_wd;
  logic soc_control_doe_async_msg_en_qs;
  logic soc_control_doe_async_msg_en_wd;
  logic soc_control_go_wd;
  logic soc_status_we;
  logic soc_status_busy_qs;
  logic soc_status_doe_intr_status_qs;
  logic soc_status_doe_intr_status_wd;
  logic soc_status_error_qs;
  logic soc_status_doe_async_msg_status_qs;
  logic soc_status_ready_qs;
  logic soc_doe_intr_msg_addr_we;
  logic [31:0] soc_doe_intr_msg_addr_qs;
  logic [31:0] soc_doe_intr_msg_addr_wd;
  logic soc_doe_intr_msg_data_we;
  logic [31:0] soc_doe_intr_msg_data_qs;
  logic [31:0] soc_doe_intr_msg_data_wd;
  // Register instances
  // R[soc_control]: V(True)
  logic soc_control_qe;
  logic [3:0] soc_control_flds_we;
  assign soc_control_qe = &soc_control_flds_we;
  //   F[abort]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_soc_control_abort (
    .re     (1'b0),
    .we     (soc_control_we),
    .wd     (soc_control_abort_wd),
    .d      (hw2reg.soc_control.abort.d),
    .qre    (),
    .qe     (soc_control_flds_we[0]),
    .q      (reg2hw.soc_control.abort.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.soc_control.abort.qe = soc_control_qe;

  //   F[doe_intr_en]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_soc_control_doe_intr_en (
    .re     (soc_control_re),
    .we     (soc_control_we),
    .wd     (soc_control_doe_intr_en_wd),
    .d      (hw2reg.soc_control.doe_intr_en.d),
    .qre    (),
    .qe     (soc_control_flds_we[1]),
    .q      (reg2hw.soc_control.doe_intr_en.q),
    .ds     (),
    .qs     (soc_control_doe_intr_en_qs)
  );
  assign reg2hw.soc_control.doe_intr_en.qe = soc_control_qe;

  //   F[doe_async_msg_en]: 3:3
  prim_subreg_ext #(
    .DW    (1)
  ) u_soc_control_doe_async_msg_en (
    .re     (soc_control_re),
    .we     (soc_control_we),
    .wd     (soc_control_doe_async_msg_en_wd),
    .d      (hw2reg.soc_control.doe_async_msg_en.d),
    .qre    (),
    .qe     (soc_control_flds_we[2]),
    .q      (reg2hw.soc_control.doe_async_msg_en.q),
    .ds     (),
    .qs     (soc_control_doe_async_msg_en_qs)
  );
  assign reg2hw.soc_control.doe_async_msg_en.qe = soc_control_qe;

  //   F[go]: 31:31
  prim_subreg_ext #(
    .DW    (1)
  ) u_soc_control_go (
    .re     (1'b0),
    .we     (soc_control_we),
    .wd     (soc_control_go_wd),
    .d      (hw2reg.soc_control.go.d),
    .qre    (),
    .qe     (soc_control_flds_we[3]),
    .q      (reg2hw.soc_control.go.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.soc_control.go.qe = soc_control_qe;


  // R[soc_status]: V(False)
  //   F[busy]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h1),
    .Mubi    (1'b0)
  ) u_soc_status_busy (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.soc_status.busy.de),
    .d      (hw2reg.soc_status.busy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.soc_status.busy.q),
    .ds     (),

    // to register interface (read)
    .qs     (soc_status_busy_qs)
  );

  //   F[doe_intr_status]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_soc_status_doe_intr_status (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (soc_status_we),
    .wd     (soc_status_doe_intr_status_wd),

    // from internal hardware
    .de     (hw2reg.soc_status.doe_intr_status.de),
    .d      (hw2reg.soc_status.doe_intr_status.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.soc_status.doe_intr_status.q),
    .ds     (),

    // to register interface (read)
    .qs     (soc_status_doe_intr_status_qs)
  );

  //   F[error]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_soc_status_error (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.soc_status.error.de),
    .d      (hw2reg.soc_status.error.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.soc_status.error.q),
    .ds     (),

    // to register interface (read)
    .qs     (soc_status_error_qs)
  );

  //   F[doe_async_msg_status]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_soc_status_doe_async_msg_status (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.soc_status.doe_async_msg_status.de),
    .d      (hw2reg.soc_status.doe_async_msg_status.d),

    // to internal hardware
    .qe     (),
    .q      (),
    .ds     (),

    // to register interface (read)
    .qs     (soc_status_doe_async_msg_status_qs)
  );

  //   F[ready]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h0),
    .Mubi    (1'b0)
  ) u_soc_status_ready (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.soc_status.ready.de),
    .d      (hw2reg.soc_status.ready.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.soc_status.ready.q),
    .ds     (),

    // to register interface (read)
    .qs     (soc_status_ready_qs)
  );


  // R[soc_doe_intr_msg_addr]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_soc_doe_intr_msg_addr (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (soc_doe_intr_msg_addr_we),
    .wd     (soc_doe_intr_msg_addr_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.soc_doe_intr_msg_addr.q),
    .ds     (),

    // to register interface (read)
    .qs     (soc_doe_intr_msg_addr_qs)
  );


  // R[soc_doe_intr_msg_data]: V(False)
  prim_subreg #(
    .DW      (32),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (32'h0),
    .Mubi    (1'b0)
  ) u_soc_doe_intr_msg_data (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (soc_doe_intr_msg_data_we),
    .wd     (soc_doe_intr_msg_data_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.soc_doe_intr_msg_data.q),
    .ds     (),

    // to register interface (read)
    .qs     (soc_doe_intr_msg_data_qs)
  );



  logic [3:0] addr_hit;
  top_racl_pkg::racl_role_vec_t racl_role_vec;
  top_racl_pkg::racl_role_t racl_role;

  logic [3:0] racl_addr_hit_read;
  logic [3:0] racl_addr_hit_write;

  if (EnableRacl) begin : gen_racl_role_logic
    // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap
    assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd);

    prim_onehot_enc #(
      .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) )
    ) u_racl_role_encode (
      .in_i ( racl_role     ),
      .en_i ( 1'b1          ),
      .out_o( racl_role_vec )
    );
  end else begin : gen_no_racl_role_logic
    assign racl_role     = '0;
    assign racl_role_vec = '0;
  end
  always_comb begin
    racl_addr_hit_read  = '0;
    racl_addr_hit_write = '0;
    addr_hit[0] = (reg_addr == MBX_SOC_CONTROL_OFFSET);
    addr_hit[1] = (reg_addr == MBX_SOC_STATUS_OFFSET);
    addr_hit[2] = (reg_addr == MBX_SOC_DOE_INTR_MSG_ADDR_OFFSET);
    addr_hit[3] = (reg_addr == MBX_SOC_DOE_INTR_MSG_DATA_OFFSET);

    if (EnableRacl) begin : gen_racl_hit
      for (int unsigned slice_idx = 0; slice_idx < 4; slice_idx++) begin
        racl_addr_hit_read[slice_idx] =
            addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].read_perm
                                      & racl_role_vec));
        racl_addr_hit_write[slice_idx] =
            addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].write_perm
                                      & racl_role_vec));
      end
    end else begin : gen_no_racl
      racl_addr_hit_read  = addr_hit;
      racl_addr_hit_write = addr_hit;
    end
  end

  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
  // A valid address hit, access, but failed the RACL check
  assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) |
                                           (reg_we & ~|racl_addr_hit_write));
  assign racl_error_o.request_address = top_pkg::TL_AW'(reg_addr);
  assign racl_error_o.racl_role       = racl_role;
  assign racl_error_o.overflow        = 1'b0;

  if (EnableRacl) begin : gen_racl_log
    assign racl_error_o.ctn_uid     = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd);
    assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get;
  end else begin : gen_no_racl_log
    assign racl_error_o.ctn_uid     = '0;
    assign racl_error_o.read_access = 1'b0;
  end

  // Check sub-word write is permitted
  always_comb begin
    wr_err = (reg_we &
              ((racl_addr_hit_write[0] & (|(MBX_SOC_PERMIT[0] & ~reg_be))) |
               (racl_addr_hit_write[1] & (|(MBX_SOC_PERMIT[1] & ~reg_be))) |
               (racl_addr_hit_write[2] & (|(MBX_SOC_PERMIT[2] & ~reg_be))) |
               (racl_addr_hit_write[3] & (|(MBX_SOC_PERMIT[3] & ~reg_be)))));
  end

  // Generate write-enables
  assign soc_control_re = racl_addr_hit_read[0] & reg_re & !reg_error;
  assign soc_control_we = racl_addr_hit_write[0] & reg_we & !reg_error;

  assign soc_control_abort_wd = reg_wdata[0];

  assign soc_control_doe_intr_en_wd = reg_wdata[1];

  assign soc_control_doe_async_msg_en_wd = reg_wdata[3];

  assign soc_control_go_wd = reg_wdata[31];

  assign soc_status_we = racl_addr_hit_write[1] & reg_we & !reg_error;

  assign soc_status_doe_intr_status_wd = reg_wdata[1];

  assign soc_doe_intr_msg_addr_we = racl_addr_hit_write[2] & reg_we & !reg_error;

  assign soc_doe_intr_msg_addr_wd = reg_wdata[31:0];

  assign soc_doe_intr_msg_data_we = racl_addr_hit_write[3] & reg_we & !reg_error;

  assign soc_doe_intr_msg_data_wd = reg_wdata[31:0];


  // Assign write-enables to checker logic vector.
  always_comb begin
    reg_we_check[0] = soc_control_we;
    reg_we_check[1] = soc_status_we;
    reg_we_check[2] = soc_doe_intr_msg_addr_we;
    reg_we_check[3] = soc_doe_intr_msg_data_we;
  end

  // Read data return
  always_comb begin
    reg_rdata_next = '0;
    unique case (1'b1)
      racl_addr_hit_read[0]: begin
        reg_rdata_next[0] = '0;
        reg_rdata_next[1] = soc_control_doe_intr_en_qs;
        reg_rdata_next[3] = soc_control_doe_async_msg_en_qs;
        reg_rdata_next[31] = '0;
      end

      racl_addr_hit_read[1]: begin
        reg_rdata_next[0] = soc_status_busy_qs;
        reg_rdata_next[1] = soc_status_doe_intr_status_qs;
        reg_rdata_next[2] = soc_status_error_qs;
        reg_rdata_next[3] = soc_status_doe_async_msg_status_qs;
        reg_rdata_next[31] = soc_status_ready_qs;
      end

      racl_addr_hit_read[2]: begin
        reg_rdata_next[31:0] = soc_doe_intr_msg_addr_qs;
      end

      racl_addr_hit_read[3]: begin
        reg_rdata_next[31:0] = soc_doe_intr_msg_data_qs;
      end

      default: begin
        reg_rdata_next = '1;
      end
    endcase
  end

  // shadow busy
  logic shadow_busy;
  assign shadow_busy = 1'b0;

  // register busy
  assign reg_busy = shadow_busy;

  // Unused signal tieoff

  // wdata / byte enable are not always fully used
  // add a blanket unused statement to handle lint waivers
  logic unused_wdata;
  logic unused_be;
  assign unused_wdata = ^reg_wdata;
  assign unused_be = ^reg_be;
  logic unused_policy_sel;
  assign unused_policy_sel = ^racl_policies_i;

  // Assertions for Register Interface
  `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
  `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)

  `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)

  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)

  // this is formulated as an assumption such that the FPV testbenches do disprove this
  // property by mistake
  //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)

endmodule
