LICENSE
MANIFEST.in
README.md
setup.py
pythondata_cpu_serv/__init__.py
pythondata_cpu_serv.egg-info/PKG-INFO
pythondata_cpu_serv.egg-info/SOURCES.txt
pythondata_cpu_serv.egg-info/dependency_links.txt
pythondata_cpu_serv.egg-info/not-zip-safe
pythondata_cpu_serv.egg-info/top_level.txt
pythondata_cpu_serv/verilog/.gitmodules
pythondata_cpu_serv/verilog/LICENSE
pythondata_cpu_serv/verilog/README.md
pythondata_cpu_serv/verilog/serv.core
pythondata_cpu_serv/verilog/servant.core
pythondata_cpu_serv/verilog/serving.core
pythondata_cpu_serv/verilog/west.yml
pythondata_cpu_serv/verilog/.github/workflows/ci.yml
pythondata_cpu_serv/verilog/.github/workflows/lint.yml
pythondata_cpu_serv/verilog/.github/workflows/openlane.yml
pythondata_cpu_serv/verilog/.github/workflows/pages.yml
pythondata_cpu_serv/verilog/bench/servant_sim.v
pythondata_cpu_serv/verilog/bench/servant_tb.cpp
pythondata_cpu_serv/verilog/bench/servant_tb.v
pythondata_cpu_serv/verilog/bench/uart_decoder.v
pythondata_cpu_serv/verilog/data/ac701.xdc
pythondata_cpu_serv/verilog/data/alhambra.pcf
pythondata_cpu_serv/verilog/data/arty_a7_35t.xdc
pythondata_cpu_serv/verilog/data/cmod_a7_35t.xdc
pythondata_cpu_serv/verilog/data/cyc1000.sdc
pythondata_cpu_serv/verilog/data/cyc1000.tcl
pythondata_cpu_serv/verilog/data/de0_nano.sdc
pythondata_cpu_serv/verilog/data/de0_nano.tcl
pythondata_cpu_serv/verilog/data/de10_nano.sdc
pythondata_cpu_serv/verilog/data/de10_nano.tcl
pythondata_cpu_serv/verilog/data/deca.sdc
pythondata_cpu_serv/verilog/data/deca.tcl
pythondata_cpu_serv/verilog/data/ebaz4205.xdc
pythondata_cpu_serv/verilog/data/go_board.pcf
pythondata_cpu_serv/verilog/data/icebreaker.pcf
pythondata_cpu_serv/verilog/data/icestick.pcf
pythondata_cpu_serv/verilog/data/icesugar.pcf
pythondata_cpu_serv/verilog/data/lx9_microboard.ucf
pythondata_cpu_serv/verilog/data/nexys_a7.xdc
pythondata_cpu_serv/verilog/data/orangecrab_r02.lpf
pythondata_cpu_serv/verilog/data/params.tcl
pythondata_cpu_serv/verilog/data/pipistrello.ucf
pythondata_cpu_serv/verilog/data/sockit.sdc
pythondata_cpu_serv/verilog/data/sockit.tcl
pythondata_cpu_serv/verilog/data/tinyfpga_bx.pcf
pythondata_cpu_serv/verilog/data/ulx3s.lpf
pythondata_cpu_serv/verilog/data/upduino2.pcf
pythondata_cpu_serv/verilog/data/verilator_waiver.vlt
pythondata_cpu_serv/verilog/data/zcu106.xdc
pythondata_cpu_serv/verilog/doc/.nojekyll
pythondata_cpu_serv/verilog/doc/Makefile
pythondata_cpu_serv/verilog/doc/conf.py
pythondata_cpu_serv/verilog/doc/index.rst
pythondata_cpu_serv/verilog/doc/life_cycle.png
pythondata_cpu_serv/verilog/doc/make.bat
pythondata_cpu_serv/verilog/doc/requirements.txt
pythondata_cpu_serv/verilog/doc/serv_alu.png
pythondata_cpu_serv/verilog/doc/serv_alu_int.png
pythondata_cpu_serv/verilog/doc/serv_bufreg.png
pythondata_cpu_serv/verilog/doc/serv_bufreg_int.png
pythondata_cpu_serv/verilog/doc/serv_csr.png
pythondata_cpu_serv/verilog/doc/serv_csr_int.png
pythondata_cpu_serv/verilog/doc/serv_ctrl.png
pythondata_cpu_serv/verilog/doc/serv_ctrl_int.png
pythondata_cpu_serv/verilog/doc/serv_dataflow.png
pythondata_cpu_serv/verilog/doc/serv_decode.png
pythondata_cpu_serv/verilog/doc/serv_decode_int.png
pythondata_cpu_serv/verilog/doc/serv_immdec.png
pythondata_cpu_serv/verilog/doc/serv_immdec_int.png
pythondata_cpu_serv/verilog/doc/serv_mem_if.png
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pythondata_cpu_serv/verilog/doc/serv_rf_if.png
pythondata_cpu_serv/verilog/doc/serv_rf_if_int.png
pythondata_cpu_serv/verilog/doc/serv_rf_top.png
pythondata_cpu_serv/verilog/riscv-target/serv/compliance_io.h
pythondata_cpu_serv/verilog/riscv-target/serv/compliance_test.h
pythondata_cpu_serv/verilog/riscv-target/serv/link.ld
pythondata_cpu_serv/verilog/riscv-target/serv/makehex.py
pythondata_cpu_serv/verilog/riscv-target/serv/device/rv32i/Makefile.include
pythondata_cpu_serv/verilog/rtl/serv_alu.v
pythondata_cpu_serv/verilog/rtl/serv_bufreg.v
pythondata_cpu_serv/verilog/rtl/serv_csr.v
pythondata_cpu_serv/verilog/rtl/serv_ctrl.v
pythondata_cpu_serv/verilog/rtl/serv_decode.v
pythondata_cpu_serv/verilog/rtl/serv_immdec.v
pythondata_cpu_serv/verilog/rtl/serv_mem_if.v
pythondata_cpu_serv/verilog/rtl/serv_rf_if.v
pythondata_cpu_serv/verilog/rtl/serv_rf_ram.v
pythondata_cpu_serv/verilog/rtl/serv_rf_ram_if.v
pythondata_cpu_serv/verilog/rtl/serv_rf_top.v
pythondata_cpu_serv/verilog/rtl/serv_state.v
pythondata_cpu_serv/verilog/rtl/serv_synth_wrapper.v
pythondata_cpu_serv/verilog/rtl/serv_top.v
pythondata_cpu_serv/verilog/servant/ecppll.v
pythondata_cpu_serv/verilog/servant/ice40_pll.v
pythondata_cpu_serv/verilog/servant/servant.v
pythondata_cpu_serv/verilog/servant/servant_ac701.v
pythondata_cpu_serv/verilog/servant/servant_arbiter.v
pythondata_cpu_serv/verilog/servant/servant_clock_gen.v
pythondata_cpu_serv/verilog/servant/servant_ecp5.v
pythondata_cpu_serv/verilog/servant/servant_ecp5_clock_gen.v
pythondata_cpu_serv/verilog/servant/servant_gpio.v
pythondata_cpu_serv/verilog/servant/servant_lx9.v
pythondata_cpu_serv/verilog/servant/servant_lx9_clock_gen.v
pythondata_cpu_serv/verilog/servant/servant_mux.v
pythondata_cpu_serv/verilog/servant/servant_orangecrab.v
pythondata_cpu_serv/verilog/servant/servant_ram.v
pythondata_cpu_serv/verilog/servant/servant_ram_quartus.sv
pythondata_cpu_serv/verilog/servant/servant_timer.v
pythondata_cpu_serv/verilog/servant/servant_upduino2.v
pythondata_cpu_serv/verilog/servant/servclone10.v
pythondata_cpu_serv/verilog/servant/servclone10_clock_gen.v
pythondata_cpu_serv/verilog/servant/service.v
pythondata_cpu_serv/verilog/servant/service_go_board.v
pythondata_cpu_serv/verilog/servant/servis.v
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pythondata_cpu_serv/verilog/servant/servive.v
pythondata_cpu_serv/verilog/servant/servive_clock_gen.v
pythondata_cpu_serv/verilog/servant/servix.v
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pythondata_cpu_serv/verilog/servant/servix_ebaz4205.v
pythondata_cpu_serv/verilog/servant/servix_ebaz4205_clock_gen.v
pythondata_cpu_serv/verilog/servant/servus.v
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pythondata_cpu_serv/verilog/serving/serving.v
pythondata_cpu_serv/verilog/serving/serving_arbiter.v
pythondata_cpu_serv/verilog/serving/serving_mux.v
pythondata_cpu_serv/verilog/serving/serving_ram.v
pythondata_cpu_serv/verilog/sw/Makefile
pythondata_cpu_serv/verilog/sw/blinky.S
pythondata_cpu_serv/verilog/sw/blinky.hex
pythondata_cpu_serv/verilog/sw/link.ld
pythondata_cpu_serv/verilog/sw/makehex.py
pythondata_cpu_serv/verilog/sw/zephyr_hello.hex
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pythondata_cpu_serv/verilog/sw/zephyr_phil.hex
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pythondata_cpu_serv/verilog/zephyr/CMakeLists.txt
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pythondata_cpu_serv/verilog/zephyr/module.yml
pythondata_cpu_serv/verilog/zephyr/boards/riscv/service/Kconfig.board
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pythondata_cpu_serv/verilog/zephyr/drivers/Kconfig
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pythondata_cpu_serv/verilog/zephyr/drivers/serial/Kconfig
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pythondata_cpu_serv/verilog/zephyr/drivers/timer/CMakeLists.txt
pythondata_cpu_serv/verilog/zephyr/drivers/timer/Kconfig
pythondata_cpu_serv/verilog/zephyr/drivers/timer/serv_timer.c
pythondata_cpu_serv/verilog/zephyr/dts/riscv/serv.dtsi
pythondata_cpu_serv/verilog/zephyr/soc/riscv/servant/CMakeLists.txt
pythondata_cpu_serv/verilog/zephyr/soc/riscv/servant/Kconfig.defconfig
pythondata_cpu_serv/verilog/zephyr/soc/riscv/servant/Kconfig.soc
pythondata_cpu_serv/verilog/zephyr/soc/riscv/servant/irq.c
pythondata_cpu_serv/verilog/zephyr/soc/riscv/servant/linker.ld
pythondata_cpu_serv/verilog/zephyr/soc/riscv/servant/soc.h
pythondata_cpu_serv/verilog/zephyr/soc/riscv/servant/soc_common.h
pythondata_cpu_serv/verilog/zephyr/soc/riscv/servant/soc_irq.S
pythondata_cpu_serv/verilog/zephyr/soc/riscv/servant/vector.S