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An abstract language model of SystemVerilog (incl. Verilog) written in Python.


# Main Goals

This package provides a unified abstract language model for SystemVerilog (incl. Verilog).
Projects reading from source files can derive own classes and implement additional logic to create a concrete language
model for their tools.

Projects consuming pre-processed System Verilog data (parsed, analyzed or elaborated) can build higher level features
and services on such a model, while supporting multiple frontends.


# Use Cases

## pySVModel Generators

* See [#11: Interfacing Surelog/UHDM](https://GitHub.com/edaa-org/pySVModel/issues/11)

*TBD*

## pySVModel Consumers

* [Electronic Design Automation Abstraction (EDA²)](https://edaa-org.github.io/)

*TBD*

# Examples

## List all Modules with Parameters and Ports

*TBD*

# Contributors

* [Patrick Lehmann](https://GitHub.com/Paebbels) (Maintainer)
* [Unai Martinez-Corral](https://GitHub.com/umarcor)
* [and more...](https://GitHub.com/edaa-org/pySVModel/graphs/contributors)

# License

This Python package (source code) licensed under [Apache License 2.0](LICENSE.md).  
The accompanying documentation is licensed under [Creative Commons - Attribution 4.0 (CC-BY 4.0)](doc/Doc-License.rst).

-------------------------
SPDX-License-Identifier: Apache-2.0
