Exporting and Importing Designs
===============================

Exporting Hardware Designs
--------------------------

.. autofunction:: pyrtl.output_to_verilog

.. autofunction:: pyrtl.output_to_firrtl

Exporting Testbenches
---------------------

.. autofunction:: pyrtl.output_verilog_testbench

Importing Verilog
-----------------

.. autofunction:: pyrtl.input_from_blif
.. autofunction:: pyrtl.input_from_verilog

Outputting for Visualization
----------------------------

.. autofunction:: pyrtl.output_to_trivialgraph
.. autofunction:: pyrtl.output_to_graphviz
.. autofunction:: pyrtl.graphviz_detailed_namer
.. autofunction:: pyrtl.output_to_svg
.. autofunction:: pyrtl.block_to_graphviz_string
.. autofunction:: pyrtl.block_to_svg
.. autofunction:: pyrtl.trace_to_html
.. autofunction:: pyrtl.net_graph
