// 
// Revision:    $Revision: 1506 $
// Date:        $Date: 2009-04-25 23:51:56 -0700 (Sat, 25 Apr 2009) $
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 /*------------------------------------------------------------------------------
 * Simple TLM CGU
 * Clock diviser PV example. Produces a clock vector of 8 bits.
 * Each Clock output line has a 8 bits devide register.
 * If register[i]=0 => No divide (reset state)
 * If register[i]=1 => divide by 2 (reset state)
 * If register[i]=2 => divide by 4 
 * If register[i]=3 => divide by 8 ...
 *------------------------------------------------------------------------------*/

#ifndef _CGU_H_
#define _CGU_H_

/*------------------------------------------------------------------------------
 * Includes							       
 *----------------------------------------------------------------------------*/
#include "systemc.h"
#include "pv_slave_base.h"
#include "pv_target_port.h"
#include "user_types.h"

/*------------------------------------------------------------------------------
 * CGU 
 *----------------------------------------------------------------------------*/
class cgu :
   public sc_module,
   public pv_slave_base < ADDRESS_TYPE , DATA_TYPE >
{
 public :
  cgu( sc_module_name module_name);
  SC_HAS_PROCESS( cgu );
  
  static const unsigned int NUMCLOCKS = 8;
  pv_target_port <ADDRESS_TYPE , DATA_TYPE> apb_slave_port;
  sc_in<bool>       clkin;
  sc_out<sc_logic>  clkout[8];
  
  tlm::tlm_status write( const ADDRESS_TYPE &addr , const DATA_TYPE &data,
			 const unsigned int byte_enable = tlm::NO_BE,
			 const tlm::tlm_mode mode = tlm::REGULAR,
			 const unsigned int export_id = 0 );
  tlm::tlm_status read( const ADDRESS_TYPE &addr , DATA_TYPE &data,
			const unsigned int byte_enable = tlm::NO_BE,
			const tlm::tlm_mode mode = tlm::REGULAR,
			const unsigned int export_id = 0 );

 private:
  sc_pvector<int> registers;
  sc_pvector<int> counters;
  void init_registers();
  void init_counters();
  void gen_clocks();
};
 

#endif  /* _CGU_H_ */
