# -*- coding: utf-8 -*-
from setuptools import setup

packages = \
['aiger']

package_data = \
{'': ['*']}

install_requires = \
['attrs>=21,<22',
 'bidict>=0.21.0,<0.22.0',
 'funcy>=1.12,<2.0',
 'parsimonious>=0.8.1,<0.9.0',
 'pyrsistent>=0.18.0,<0.19.0',
 'sortedcontainers>=2.3.0,<3.0.0',
 'toposort>=1.5,<2.0']

setup_kwargs = {
    'name': 'py-aiger',
    'version': '6.1.19',
    'description': 'A python library for manipulating sequential and-inverter gates.',
    'long_description': '<figure>\n  <img src="assets/logo_text.svg" alt="py-aiger logo" width=300px>\n  <figcaption>\n      pyAiger: A python library for manipulating sequential and\n      combinatorial circuits.\n  </figcaption>\n\n</figure>\n\n\n[![Build Status](https://cloud.drone.io/api/badges/mvcisback/py-aiger/status.svg)](https://cloud.drone.io/mvcisback/py-aiger)\n[![codecov](https://codecov.io/gh/mvcisback/py-aiger/branch/master/graph/badge.svg)](https://codecov.io/gh/mvcisback/py-aiger)\n[![PyPI version](https://badge.fury.io/py/py-aiger.svg)](https://badge.fury.io/py/py-aiger)\n[![License: MIT](https://img.shields.io/badge/License-MIT-yellow.svg)](https://opensource.org/licenses/MIT)\n[![DOI](https://zenodo.org/badge/DOI/10.5281/zenodo.1405781.svg)](https://doi.org/10.5281/zenodo.1405781)\n\n<!-- markdown-toc start - Don\'t edit this section. Run M-x markdown-toc-generate-toc again -->\n**Table of Contents**\n\n- [About PyAiger](#about-pyaiger)\n- [Installation](#installation)\n- [Boolean Expression DSL](#boolean-expression-dsl)\n- [Sequential Circuit DSL](#sequential-circuit-dsl)\n    - [Sequential composition](#sequential-composition)\n    - [Parallel composition](#parallel-composition)\n    - [Circuits with Latches/Feedback/Delay](#circuits-with-latchesfeedbackdelay)\n    - [Relabeling](#relabeling)\n    - [Evaluation](#evaluation)\n    - [Useful circuits](#useful-circuits)\n- [Extra](#extra)\n- [Ecosystem](#ecosystem)\n- [Related Projects](#related-projects)\n- [Citing](#citing)\n\n<!-- markdown-toc end -->\n\n\n# About PyAiger\n\n1. Q: How is Py-Aiger pronounced? A: Like "pie" + "grrr".\n2. Q: Why python? Aren\'t you worried about performance?! A: No. The goals of this library are ease of use and hackability. \n3. Q: No, I\'m really concerned about performance! A: This library is not suited to implement logic solvers. For everything else, such as the creation and manipulation of circuits with many thousands of gates in between solver calls, the library is really fast enough.\n4. Q: Where does the name come from? A: <a href="http://fmv.jku.at/aiger/">Aiger</a> is a popular circuit format. The format is used in <a href="http://fmv.jku.at/hwmcc17/">hardware model checking</a>, <a href="http://www.syntcomp.org/">synthesis</a>, and is supported by <a href="https://github.com/berkeley-abc/abc">ABC</a>. The name is a combination of AIG (standing for <a href="https://en.wikipedia.org/wiki/And-inverter_graph">And-Inverter-Graph</a>) and the mountain <a href="https://en.wikipedia.org/wiki/Eiger">Eiger</a>.\n\n# Installation\n\nIf you just need to use `aiger`, you can just run:\n\n`$ pip install py-aiger`\n\nFor developers, note that this project uses the\n[poetry](https://poetry.eustace.io/) python package/dependency\nmanagement tool. Please familarize yourself with it and then\nrun:\n\n`$ poetry install`\n\n# Usage\n\n```\nimport aiger\n\nx, y, z, w = aiger.atoms(\'x\', \'y\', \'z\', \'w\')\n\nexpr1 = z.implies(x & y)\nexpr2 = z & w\n\ncirc1 = expr1.with_output(\'z\') \\      # Get AIG for expr1 with output \'z\'.\n             .aig\ncirc2 = circ1 >> circ2                # Feed outputs of circ1 into circ2.\n```\n\n# Boolean Expression DSL\nWhile powerful, when writing combinatorial circuits, the Sequential\nCircuit DSL can be somewhat clumsy. For this common usecase, we have\ndeveloped the Boolean Expression DSL. All circuits generated this way\nhave a single output.\n\n```python\nimport aiger\nx, y, z = aiger.atoms(\'x\', \'y\', \'z\')\nexpr1 = x & y  # circuit with inputs \'x\', \'y\' and 1 output computing x AND y.\nexpr2 = x | y  # logical or.\nexpr3 = x ^ y  # logical xor.\nexpr4 = x == y  # logical ==, xnor.\nexpr5 = x.implies(y)\nexpr6 = ~x  # logical negation.\nexpr7 = aiger.ite(x, y, z)  # if x then y else z.\n\n# Atoms can be constants.\nexpr8 = x & True  # Equivalent to just x.\nexpr9 = x & False # Equivalent to const False.\n\n# Specifying output name of boolean expression.\n# - Output is a long uuid otherwise.\nexpr10 = expr5.with_output(\'x_implies_y\')\nassert expr10.output == \'x_implies_y\'\n\n# And you can inspect the AIG if needed.\ncirc = x.aig\n\n# And of course, you can get a BoolExpr from a single output aig.\nexpr10 = aiger.BoolExpr(circ)\n```\n\n\n# Sequential Circuit DSL\n\n```python\nimport aiger\nfrom aiger import utils\n\n# Parser for ascii AIGER format.\naig1 = aiger.load(path_to_aig1_file.aag)\naig2 = aiger.load(path_to_aig2_file.aag)\n```\n\n## Sequential composition\n```python\naig3 = aig1 >> aig2\n```\n\n## Parallel composition\n```python\naig4 = aig1 | aig2\n```\n\n## Circuits with Latches and Delayed Feedback\nSometimes one requires some outputs to be feed back into the circuits\nas time delayed inputs. This can be accomplished using the `loopback`\nmethod. This method takes in a variable number of dictionaries\nencoding how to wire an input to an output. The wiring dictionaries\nwith the following keys and default values:\n\n| Key         | Default | Meaning                          |\n| ----------- | ------- | -------------------------------- |\n| input       |         | Input port                       |\n| output      |         | Output port                      |\n| latch       | input   | Latch name                       |\n| init        | True    | Initial latch value              |\n| keep_output | True    | Keep loopbacked output as output |\n\n\n```python\n# Connect output y to input x with delay, initialized to True.\n# (Default initialization is False.)\naig5 = aig1.loopback({\n  "input": "x", "output": "y",\n})\n\naig6 = aig1.loopback({\n  "input": "x", "output": "y",\n}, {\n  "input": "z", "output": "z", "latch": "z_latch",\n  "init": False, "keep_outputs": False\n})\n\n```\n\n## Relabeling\n\nThere are two syntaxes for relabeling. The first uses indexing\nsyntax in a nod to [notation often used variable substition in math](https://mathoverflow.net/questions/243084/history-of-the-notation-for-substitution).\n\nThe syntax is the relabel method, which is preferable when one wants\nto be explicit, even for those not familar with `py-aiger`.\n\n```python\n# Relabel input \'x\' to \'z\'.\naig1[\'i\', {\'x\': \'z\'}]\naig1.relabel(\'input\', {\'x\': \'z\'})\n\n# Relabel output \'y\' to \'w\'.\naig1[\'o\', {\'y\': \'w\'}]\naig1.relabel(\'output\', {\'y\': \'w\'})\n\n# Relabel latches \'l1\' to \'l2\'.\naig1[\'l\', {\'l1\': \'l2\'}]\naig1.relabel(\'latch\', {\'l1\': \'l2\'})\n```\n\n## Evaluation\n```python\n# Combinatoric evaluation.\naig3(inputs={\'x\':True, \'y\':False})\n\n# Sequential evaluation.\nsim = aig3.simulate([{\'x\': 0, \'y\': 0}, \n                    {\'x\': 1, \'y\': 2},\n                    {\'x\': 3, \'y\': 4}])\n\n# Simulation Coroutine\nsim = aig3.simulator()  # Coroutine\nnext(sim)  # Initialize\nprint(sim.send({\'x\': 0, \'y\': 0}))\nprint(sim.send({\'x\': 1, \'y\': 2}))\nprint(sim.send({\'x\': 3, \'y\': 4}))\n\n\n# Unroll\naig4 = aig3.unroll(steps=10, init=True)\n```\n\n## Useful circuits\n```python\n# Fix input x to be False.\naig4 = aiger.source({\'x\': False}) >> aig3\n\n# Remove output y. \naig4 = aig3 >> aiger.sink([\'y\'])\n\n# Create duplicate w of output y.\naig4 = aig3 >> aiger.tee({\'y\': [\'y\', \'w\']})\n```\n\n# Extra\n```python\naiger.common.eval_order(aig1)  # Returns topological ordering of circuit gates.\n\n# Convert object into an AIG from multiple formats including BoolExpr, AIG, str, and filepaths.\naiger.to_aig(aig1)\n```\n\n# Ecosystem\n\n### Stable\n- [py-aiger-bv](https://github.com/mvcisback/py-aiger-bv): Extension of pyAiger for manipulating sequential bitvector circuits.\n- [py-aiger-cnf](https://github.com/mvcisback/py-aiger-cnf): BoolExpr to Object representing CNF. Mostly used for interfacing with py-aiger-sat.\n- [py-aiger-past-ltl](https://github.com/mvcisback/py-aiger-past-ltl): Converts Past Linear Temporal Logic to aiger circuits.\n- [py-aiger-coins](https://github.com/mvcisback/py-aiger-coins): Library for creating circuits that encode discrete distributions.\n- [py-aiger-sat](https://github.com/mvcisback/py-aiger-sat): Bridge between py-aiger and py-sat.\n- [py-aiger-bdd](https://github.com/mvcisback/py-aiger-bdd): Aiger <-> BDD bridge.\n- [py-aiger-gridworld](https://github.com/mvcisback/py-aiger-gridworld): Create aiger circuits representing gridworlds.\n- [py-aiger-dfa](https://pypi.org/project/py-aiger-dfa/): Convert between finite automata and sequential circuits.\n\n\n### Underdevelopment\n\n\n- [py-aiger-spectral](https://github.com/mvcisback/py-aiger-spectral): A tool for performing (Fourier) Analysis of Boolean Functions.\n- [py-aiger-abc](https://pypi.org/project/py-aiger-abc/): Aiger and abc bridge.\n\n# Related Projects\n- [pyAig](https://github.com/sterin/pyaig): Another python library\n  for working with AIGER circuits.\n',
    'author': 'Marcell Vazquez-Chanlatte',
    'author_email': 'marcell.vc@eecs.berkeley.edu',
    'maintainer': None,
    'maintainer_email': None,
    'url': 'https://github.com/mvcisback/py-aiger',
    'packages': packages,
    'package_data': package_data,
    'install_requires': install_requires,
    'python_requires': '>=3.7,<4.0',
}


setup(**setup_kwargs)
